; -------------------------------------------------------------------------------- ; @Title: RCARV3U On-Chip Peripherals ; @Props: Released ; @Author: KRZ ; @Changelog: 2025-02-05 KRZ ; @Manufacturer: RENESAS - Renesas Technology, Corp. ; @Doc: Generated (TRACE32, build: 176288.), based on: V3U_Register_IpxACT_20200819 ; @Core: Cortex-A76, Cortex-R52 ; @Chip: R8A779A0 ; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perrcarv3u.per 19100 2025-02-24 14:34:34Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (CORENAME()=="CORTEXR52") AUTOINDENT.PUSH AUTOINDENT.OFF tree "Core Registers (Cortex-R52)" AUTOINDENT.PUSH AUTOINDENT.ON center tree tree "ID Registers" rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. "STATE3,Thumb execution environment (thumb-EE) support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for jazelle extension" "Reserved,No cleaning,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb encoding supported by the processor type" "Reserved,Reserved,Reserved,After thumb-2,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM instruction set support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU support" "Reserved,Enabled,?..." bitfld.long 0x00 24.--27. "VF,Virtualization fractional support" "Not supported,?..." bitfld.long 0x00 20.--23. "SF,Security fractional support" "Reserved,VBAR,?..." newline bitfld.long 0x00 16.--19. "GT,Generic timer support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization extensions support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller programmer's model support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security extensions architecture v1 support" "Not supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 programmer's model support" "Reserved,Supported,?..." rgroup.long c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Non-cacheable,?..." bitfld.long 0x00 24.--27. "FCSE,Fast context switch memory mappings support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary register support" "Reserved,Reserved,Control/fault status,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and associated DMA support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer shareable support" "Non-cacheable,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical memory system architecture (PMSA) support" "Reserved,Reserved,Reserved,Reserved,ARMv8-R base+limit PMSA,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual memory system architecture (VMSA) support" "Not supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and clean operations on data cache/harvard/unified architecture support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 cache/all maintenance operations/unified architecture support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/all maintenance operations/harvard architecture support" "Not supported,?..." bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 cache line maintenance operations by set and way/unified architecture support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 cache line maintenance operations by set and way/harvard architecture support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 cache line maintenance operations by MVA/unified architecture support" "Not supported,?..." bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 cache line maintenance operations by MVA/harvard architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware access flag support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for interrupt stalling support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory barrier operations support" "Reserved,Reserved,DSB/ISB/DMB,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB maintenance operations/unified architecture support" "Not supported,?..." bitfld.long 0x00 12.--15. "HTLBMO,TLB maintenance operations/harvard architecture support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache maintenance range operations/harvard architecture support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "HL1BPCRO,Background prefetch cache range operations/harvard architecture support" "Not supported,?..." bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground prefetch cache range operations/harvard architecture support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not supported" bitfld.long 0x00 24.--27. "CMEMSZ,Cached memory size" "4GByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk. Indicates whether translation table updates require a clean to the point of unification" "Reserved,Not required,?..." newline bitfld.long 0x00 12.--15. "MB,Maintenance broadcast support" "Reserved,Reserved,Shareability/defined behavior,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate branch predictor support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. "HCMOSW,Invalidate cache by set and way/clean by set and way/invalidate and clean by set and way support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate cache MVA support" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,Memory Model Feature Register 4" bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Reserved,Supported,?..." rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. "DIVI,Divide instructions support" "Reserved,Reserved,T32/A32,?..." bitfld.long 0x00 20.--23. "DEBI,Debug instructions support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor instructions support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined compare and branch instructions support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield instructions support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit counting instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap instructions support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 28.--31. "JI,Jazelle instructions support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork instructions support" "Reserved,Reserved,Reserved,A32-BX like,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If then instructions support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend instructions support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM instructions support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian instructions support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. "RI,Reversal instructions support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR instructions support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced unsigned multiply instructions support" "Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced signed multiply instructions support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. "MI,Multiply instructions support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-access interruptible instructions support" "Reserved,Restartable,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory hint instructions support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLDW,?..." bitfld.long 0x00 0.--3. "LSI,Load and store instructions support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE extensions support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP instructions support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb copy instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table branch instructions support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization primitive instructions support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single instruction multiple data (SIMD) instructions support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate instructions support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory system locking support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M instructions support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier instructions support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC instructions support" "Not supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-back instructions support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-shift instructions support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged instructions support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 16.--19. "CRC32,CRC32 instructions support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,SHA2 instructions support" "Not supported,?..." bitfld.long 0x00 8.--11. "SHA1,SHA1 instructions support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "AES,AES instructions support" "Not supported,?..." bitfld.long 0x00 0.--3. "SEVL,SEVL instructions support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. "PMM,Performance monitor model support" "Reserved,Reserved,Reserved,PMUv3,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped debug model for M profile processors support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace model (memory-mapped) support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-based trace debug model support" "Not supported,?..." bitfld.long 0x00 0.--3. "CDM_CB,Secure debug model (Coprocessor) support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0000++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" hexmask.long.word 0x00 4.--15. 1. "PART,Primary part number" newline bitfld.long 0x00 0.--3. "REV,Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x0700++0x00 line.long 0x00 "MIDR,Main ID Register (Alias)" hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" hexmask.long.word 0x00 4.--15. 1. "PART,Primary part number" newline bitfld.long 0x00 0.--3. "REV,Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x0200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 29.--31. "TCMS,TCM implemented" "No TCMs,Reserved,Reserved,Reserved,1 TCMs,?..." bitfld.long 0x00 2. "CTCM,CTCM implemented with non zero size" "Not implemented,Implemented" bitfld.long 0x00 1. "BTCM,BTCM implemented with non zero size" "Not implemented,Implemented" newline bitfld.long 0x00 0. "ATCM,ATCM implemented with non zero size" "Not implemented,Implemented" rgroup.long c15:0x0300++0x00 line.long 0x00 "TLBTR,TLB Type Register" rgroup.long c15:0x0500++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Single core system as distinct from core 0 in a cluster" "Part of a cluster,?..." bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..." newline hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. The least significant affinity field for this PE in the system" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. The intermediate affinity level field for this PE in the system" hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. The most significant affinity level field for this PE in the system" rgroup.long c15:0x0600++0x00 line.long 0x00 "REVIDR,Revision ID Register" hexmask.long.word 0x00 0.--11. 1. "IDNUMBER,Implementation-specific revision information" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" tree.end tree "System Control and Configuration" group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" rbitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies EL1 Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 18. "NTWE,Do not trap WFE (Wait for Event) instruction" "Trapped,Not trapped" newline bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled" bitfld.long 0x00 16. "NTWI,Do not trap WFI (Wait For Interrupt) instruction" "Trapped,Not trapped" bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,EL1-controlled MPU enable" "Disabled,Enabled" newline group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled" newline bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled" bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,EL2-controlled MPU enable" "Disabled,Enabled" newline group.long c15:0x0201++0x00 line.long 0x00 "CPACR,Architectural Feature Access Control Register" bitfld.long 0x00 31. "ASEDIS,Disable advanced SIMD extension functionality" "No,Yes" bitfld.long 0x00 22.--23. "CP11,Coprocessor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x00 20.--21. "CP10,Coprocessor access control" "Denied,Privileged,Reserved,Full" rgroup.long c15:0x0101++0x00 line.long 0x00 "ACTLR,Auxiliary Control Register" rgroup.long c15:0x0301++0x00 line.long 0x00 "ACTLR2,Auxiliary Control Register 2" rgroup.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" group.long c15:0x000B++0x00 line.long 0x00 "IMP_SLAVEPCTLR,Slave Port Control Register" bitfld.long 0x00 0.--1. "TCMACCLVL,Indicates the privilege level required for the AXIS to access the TCM" "Denied,Privileged,Reserved,Full" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector base address" rgroup.long c15:0x010C++0x00 line.long 0x00 "RVBAR,Reset Vector Base Address Register" hexmask.long 0x00 1.--31. 0x02 "ADDR,Reset address" rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending" bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Internal interface,ATCM,BTCM,CTCM,Overlap" bitfld.long 0x00 0.--1. "TYPE,Fault type" "Other error,External bus control,TCM/cache/bus data,Bus timeout" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Reserved,ATCM,BTCM,CTCM,Overlap" bitfld.long 0x00 0.--1. "TYPE,Fault type" "Other error,External bus control,TCM/cache/bus data,Bus timeout" group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault" bitfld.long 0x00 12. "EXT,External abort qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 11. "WNR,Access caused an abort type" "Read,Write" bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Reserved,Reserved,Reserved,Reserved,Translation fault/0th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault/0th level,Reserved,Reserved,Reserved,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,?..." group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 16. "FNV,FAR not Valid for a Synchronous External abort" "Valid,?..." bitfld.long 0x00 12. "EXT,External abort qualifier" "DECERR,SLVERR" newline bitfld.long 0x00 9. "LPAE,Translation table formats on Data Abort exception" "Reserved,Long-descriptor" bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Reserved,Reserved,Reserved,Reserved,Translation fault/0th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault/0th level,Reserved,Reserved,Reserved,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" rgroup.long c15:0x000D++0x00 line.long 0x00 "FCSEIDR,FCSE PID Register" rgroup.long c15:0x103F++0x00 line.long 0x00 "IMP_CBAR,Configuration Base Address Register" hexmask.long.word 0x00 21.--31. 0x20 "PERIPHBASE,Upper bits of base physical address of memory-mapped peripherals" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,Thread Pointer ID Register Unprivileged Read-Write" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,Thread Pointer ID Register Unprivileged Read-Only" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,Thread Pointer ID Register Privileged Read-Write" tree "System Instructions" wgroup.long c15:0x0017++0x00 line.long 0x00 "ICIALLUIS,ICIALLUIS" wgroup.long c15:0x0617++0x00 line.long 0x00 "BPIALLIS,BPIALLIS" wgroup.long c15:0x0057++0x00 line.long 0x00 "ICIALLU,ICIALLU" wgroup.long c15:0x0157++0x00 line.long 0x00 "ICIMVAU,ICIMVAU" wgroup.long c15:0x0457++0x00 line.long 0x00 "CP15ISB,CP15ISB" wgroup.long c15:0x0657++0x00 line.long 0x00 "BPIALL,BPIALL" wgroup.long c15:0x0757++0x00 line.long 0x00 "BPIMVA,BPIMVA" wgroup.long c15:0x0167++0x00 line.long 0x00 "DCIMVAC,DCIMVAC" wgroup.long c15:0x0267++0x00 line.long 0x00 "DCISW,DCISW" wgroup.long c15:0x0087++0x00 line.long 0x00 "ATS1CPR,ATS1CPR" wgroup.long c15:0x0187++0x00 line.long 0x00 "ATS1CPW,ATS1CPW" wgroup.long c15:0x0287++0x00 line.long 0x00 "ATS1CUR,ATS1CUR" wgroup.long c15:0x0387++0x00 line.long 0x00 "ATS1CUW,ATS1CUW" wgroup.long c15:0x0487++0x00 line.long 0x00 "ATS12NSOPR,ATS12NSOPR" wgroup.long c15:0x0587++0x00 line.long 0x00 "ATS12NSOPW,ATS12NSOPW" wgroup.long c15:0x0687++0x00 line.long 0x00 "ATS12NSOUR,ATS12NSOUR" wgroup.long c15:0x0787++0x00 line.long 0x00 "ATS12NSOUW,ATS12NSOUW" wgroup.long c15:0x01A7++0x00 line.long 0x00 "DCCMVAC,DCCMVAC" wgroup.long c15:0x02A7++0x00 line.long 0x00 "DCCSW,DCCSW" wgroup.long c15:0x04A7++0x00 line.long 0x00 "CP15DSB,CP15DSB" wgroup.long c15:0x05A7++0x00 line.long 0x00 "CP15DMB,CP15DMB" wgroup.long c15:0x01B7++0x00 line.long 0x00 "DCCMVAU,DCCMVAU" wgroup.long c15:0x01E7++0x00 line.long 0x00 "DCCIMVAC,DCCIMVAC" wgroup.long c15:0x02E7++0x00 line.long 0x00 "DCCISW,DCCISW" wgroup.long c15:0x4087++0x00 line.long 0x00 "ATS1HR,ATS1HR" wgroup.long c15:0x4187++0x00 line.long 0x00 "ATS1HW,ATS1HW" tree.end tree.end tree "MPU Control and Configuration" group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline rbitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies EL1 Execute Never (XN)" "Not forced,Forced" newline bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 18. "NTWE,Do not trap WFE (Wait for Event) instruction" "Trapped,Not trapped" newline bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled" bitfld.long 0x00 16. "NTWI,Do not trap WFI (Wait For Interrupt) instruction" "Trapped,Not trapped" newline bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes" newline bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "M,EL1-controlled MPU enable" "Disabled,Enabled" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled" bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced" newline bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled" bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes" newline bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled" bitfld.long 0x00 2. "C,Data cache enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,EL2-controlled MPU enable" "Disabled,Enabled" newline if (((per.l(c15:0x10070))&0x1)==0x0) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA" hexmask.quad.long 0x00 12.--31. 0x1000 "PA,Physical address" newline bitfld.quad 0x00 9. "NS,Non-secure" "Reserved,Yes" bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,?..." newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Reserved,Reserved,Reserved,Reserved,Translation fault/0th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault/0th level,Reserved,Reserved,Reserved,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unsupported Exclusive access,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif tree.open "Memory Attribute Indirection Registers" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" rgroup.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" rgroup.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" group.long c15:0x010D++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" tree.end newline group.long c15:(0x0019+0x0)++0x00 line.long 0x00 "IMP_ATCMREGIONR,TCM Region Register A" hexmask.long.long 0x00 13.--31. 0x2000 "BASEADDRESS,TCM base address" bitfld.long 0x00 8. "WAITSTATES,Wait states for TCM accesses" "0,1" newline bitfld.long 0x00 2.--6. "SIZE,TCM size" "No TCM,Reserved,Reserved,Reserved,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,?..." bitfld.long 0x00 1. "ENABLEEL2,Enable TCM at EL2" "Disabled,Enabled" newline bitfld.long 0x00 0. "ENABLEEL10,Enable TCM at EL1 and EL0" "Disabled,Enabled" group.long c15:(0x0019+0x100)++0x00 line.long 0x00 "IMP_BTCMREGIONR,TCM Region Register B" hexmask.long.long 0x00 13.--31. 0x2000 "BASEADDRESS,TCM base address" bitfld.long 0x00 8. "WAITSTATES,Wait states for TCM accesses" "0,1" newline bitfld.long 0x00 2.--6. "SIZE,TCM size" "No TCM,Reserved,Reserved,Reserved,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,?..." bitfld.long 0x00 1. "ENABLEEL2,Enable TCM at EL2" "Disabled,Enabled" newline bitfld.long 0x00 0. "ENABLEEL10,Enable TCM at EL1 and EL0" "Disabled,Enabled" group.long c15:(0x0019+0x200)++0x00 line.long 0x00 "IMP_CTCMREGIONR,TCM Region Register C" hexmask.long.long 0x00 13.--31. 0x2000 "BASEADDRESS,TCM base address" bitfld.long 0x00 8. "WAITSTATES,Wait states for TCM accesses" "0,1" newline bitfld.long 0x00 2.--6. "SIZE,TCM size" "No TCM,Reserved,Reserved,Reserved,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,?..." bitfld.long 0x00 1. "ENABLEEL2,Enable TCM at EL2" "Disabled,Enabled" newline bitfld.long 0x00 0. "ENABLEEL10,Enable TCM at EL1 and EL0" "Disabled,Enabled" group.long c15:0x1219++0x00 line.long 0x00 "IMP_MEMPROTCTLR,Memory Protection Control Register" rbitfld.long 0x00 5. "FLASHPROTIMP,Flash protection implemented" "Not implemented,Implemented" rbitfld.long 0x00 4. "RAMPROTIMP,RAM protection implemented" "Not implemented,Implemented" newline bitfld.long 0x00 1. "FLASHPROTEN,Flash interface protection enable" "Disabled,Enabled" bitfld.long 0x00 0. "RAMPROTEN,TCM and L1 cache RAM protection enable" "Disabled,Enabled" group.long c15:0x000F++0x00 line.long 0x00 "IMP_PERIPHPREGIONR,Peripheral Port Region Register" hexmask.long.tbyte 0x00 12.--31. 0x10 "BASEADDRESS,Peripheral port region base address" bitfld.long 0x00 2.--6. "SIZE,Peripheral port region size" "No peripheral port,Reserved,Reserved,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,?..." newline bitfld.long 0x00 1. "ENABLEEL2,Enable peripheral port at EL2" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEEL10,Enable peripheral port at EL1 and EL0" "Disabled,Enabled" group.long c15:0x010F++0x00 line.long 0x00 "IMP_FLASHIFREGIONR,Flash Interface Region Register" hexmask.long.byte 0x00 27.--31. 0x08 "BASEADDRESS,Peripheral port region base address" bitfld.long 0x00 2.--6. "SIZE,Flash interface region size" "No flash,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,?..." newline bitfld.long 0x00 0. "ENABLE,Enable the flash interface" "Disabled,Enabled" rgroup.long c15:0x002F++0x00 line.long 0x00 "IMP_BUILDOPTR,Build Options Register" bitfld.long 0x00 30.--31. "LOCK_STEP,DCLS functionality implemented" "Not implemented,DCLS configuration,Split/lock configuration,?..." bitfld.long 0x00 28.--29. "BUS_PROTECTION,Bus protection scheme implemented (signal integrity/interconnect protection)" "Not implemented,Implemented/Not implemented,Implemented,?..." newline bitfld.long 0x00 26.--27. "FLASH_DATA_ECC_SCHEME,Flash memory interface data ECC chunk size" "Reserved,64 bit,128 bit,?..." bitfld.long 0x00 20.--23. "AXIS_ID_WIDTH,Width of AXIS interface ID signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8. "NUM_GIC_EXT_DEV,Number of external device interfaces to the GIC" "0,1" bitfld.long 0x00 0.--3. "NUM_CORES,Number of cores in the Cortex-R52 processor" "0,1,2,3,?..." rgroup.long c15:0x072F++0x00 line.long 0x00 "IMP_PINOPTR,Pin Options Register" hexmask.long.byte 0x00 24.--31. 1. "CFGAXISTCMBASEADDR,Value of the CFGAXISTCMBASEADDR signal" bitfld.long 0x00 23. "CFGSLSPLIT,Value of the CFGSLSPLIT signal" "0,1" newline bitfld.long 0x00 21.--22. "CFGCLUSTERUTID,Value of the CFGCLUSTERUTID signal" "0,1,2,3" bitfld.long 0x00 18. "CFGFLASHPROTEN,Value of the CFGFLASHPROTEN signal" "0,1" newline bitfld.long 0x00 17. "CFGRAMPROTEN,Value of the CFGRAMPROTEN signal" "0,1" bitfld.long 0x00 16. "CFGINITREG,Value of the CFGINITREG signal" "0,1" newline bitfld.long 0x00 15. "CFGMRPEN,Value of the CFGMRPEN signal" "0,1" bitfld.long 0x00 6. "CFGL1CACHEINVDISX,Value of the CFGL1CACHEINVDISx signal" "0,1" newline bitfld.long 0x00 5. "CFGENDIANNESSX,Value of the CFGENDIANNESSX signal" "0,1" bitfld.long 0x00 4. "CFGTHUMBEXCEPTIONSX,Value of the CFGTHUMBEXCEPTIONSx signal" "0,1" newline bitfld.long 0x00 2. "CFGFLASHENX,Value of the CFGFLASHENx signal" "0,1" bitfld.long 0x00 0. "CFGTCMBOOTX,Value of the CFGTCMBOOTx signal" "0,1" group.long c15:0x113F++0x00 line.long 0x00 "IMP_QOSR,Quality Of Service Register" bitfld.long 0x00 8.--11. "AWQOS[3:0],QoS identifier sent on the write address channel for each write transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "ARQOS[3:0],QoS identifier sent on the read address channel for each read transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x123F++0x00 line.long 0x00 "IMP_BUSTIMEOUTR,Bus Timeout Register" hexmask.long.byte 0x00 24.--31. 1. "MAXCYCLESBY16FLASH,Flash interface timeout value in cycles divided by 16" hexmask.long.byte 0x00 16.--23. 1. "MAXCYCLESBY16LLPP,LLPP timeout value in cycles divided by 16" newline hexmask.long.byte 0x00 8.--15. 1. "MAXCYCLESBY16AXIM,AXIM interface timeout value in cycles divided by 16" bitfld.long 0x00 6. "ABORTFLASH,Abort flash access" "Not aborted,Aborted" newline bitfld.long 0x00 5. "ABORTLLPP,Abort LLPP access" "Not aborted,Aborted" bitfld.long 0x00 4. "ABORTAXIM,Abort AXIM access" "Not aborted,Aborted" newline bitfld.long 0x00 2. "ENABLEFLASH,Timeout counter enable for flash interface" "Disabled,Enabled" bitfld.long 0x00 1. "ENABLELLPP,Timeout counter enable for LLPP" "Disabled,Enabled" newline bitfld.long 0x00 0. "ENABLEAXIM,Timeout counter enable for AXIM interface" "Disabled,Enabled" group.long c15:0x143F++0x00 line.long 0x00 "IMP_INTMONR,Interrupt Monitoring Register" hexmask.long.byte 0x00 8.--15. 1. "MAXCYCLESBY16,Maximum count divided by 16" bitfld.long 0x00 4. "MODE,Operation mode of the counter" "Watchdog,Maximum value monitor" newline bitfld.long 0x00 2. "ENABLESER,Enable counting of cycles in which physical system errors are masked" "Disabled,Enabled" bitfld.long 0x00 1. "ENABLEIRQ,Enable counting of physical interrupts that cannot be taken" "Disabled,Enabled" newline bitfld.long 0x00 0. "ENABLEFIQ,Enable counting of fast interrupts that cannot be taken" "Disabled,Enabled" group.long c15:(0x200F+0x0)++0x00 line.long 0x00 "IMP_ICERR0,Instruction Cache Error Record Register 0" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank" hexmask.long.byte 0x00 4.--10. 1. "INDEX,Instruction cache index" newline bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x200F+0x100)++0x00 line.long 0x00 "IMP_ICERR1,Instruction Cache Error Record Register 1" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank" hexmask.long.byte 0x00 4.--10. 1. "INDEX,Instruction cache index" newline bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x201F+0x0)++0x00 line.long 0x00 "IMP_DCERR0,Data Cache Error Record Register 0" hexmask.long.word 0x00 20.--31. 1. "RAMID,RAM bank" hexmask.long.byte 0x00 4.--10. 1. "INDEX,Data cache index" newline bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x201F+0x100)++0x00 line.long 0x00 "IMP_DCERR1,Data Cache Error Record Register 1" hexmask.long.word 0x00 20.--31. 1. "RAMID,RAM bank" hexmask.long.byte 0x00 4.--10. 1. "INDEX,Data cache index" newline bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x202F+0x0)++0x00 line.long 0x00 "IMP_TCMERR0,TCM Error Record Register 0" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank" hexmask.long.tbyte 0x00 4.--20. 1. "INDEX,Bits [19:3] of the access address" newline bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal" bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x202F+0x100)++0x00 line.long 0x00 "IMP_TCMERR1,TCM Error Record Register 1" hexmask.long.byte 0x00 24.--31. 1. "RAMID,RAM bank" hexmask.long.tbyte 0x00 4.--20. 1. "INDEX,Bits [19:3] of the access address" newline bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal" bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" rgroup.long c15:(0x222F+0x0)++0x00 line.long 0x00 "IMP_TCMSYNDR0,TCM Syndrome Register 0" hexmask.long.byte 0x00 8.--14. 1. "BANK1,Syndrome for a bank 1 error" hexmask.long.byte 0x00 0.--7. 1. "BANK0,Syndrome for a bank 0 error" rgroup.long c15:(0x222F+0x100)++0x00 line.long 0x00 "IMP_TCMSYNDR1,TCM Syndrome Register 1" hexmask.long.byte 0x00 8.--14. 1. "BANK1,Syndrome for a bank 1 error" hexmask.long.byte 0x00 0.--7. 1. "BANK0,Syndrome for a bank 0 error" group.long c15:(0x203F+0x0)++0x00 line.long 0x00 "IMP_FLASHERR0,Flash Error Record Register 0" hexmask.long 0x00 4.--28. 1. "INDEX,Bits [25:1] of the access address" bitfld.long 0x00 2. "LATE,Late error" "Not late,Late" newline bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal" bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" group.long c15:(0x203F+0x100)++0x00 line.long 0x00 "IMP_FLASHERR1,Flash Error Record Register 1" hexmask.long 0x00 4.--28. 1. "INDEX,Bits [25:1] of the access address" bitfld.long 0x00 2. "LATE,Late error" "Not late,Late" newline bitfld.long 0x00 1. "FATAL,Fatal error" "Correctable,Fatal" bitfld.long 0x00 0. "VALID,Register contents are valid" "Not valid,Valid" rgroup.long c15:0x400F++0x00 line.long 0x00 "IMP_TESTR0,Test Register 0" bitfld.long 0x00 5. "VSEI,Virtual system error interrupt signal value" "0,1" bitfld.long 0x00 4. "SEI,System error interrupt signal value" "0,1" newline bitfld.long 0x00 3. "VIRQ,Virtual IRQ interrupt signal value" "0,1" bitfld.long 0x00 2. "IRQ,IRQ interrupt signal value" "0,1" newline bitfld.long 0x00 1. "VFIQ,Virtual FIQ interrupt signal value" "0,1" bitfld.long 0x00 0. "FIQ,FIQ interrupt signal value" "0,1" wgroup.long c15:0x410F++0x00 line.long 0x00 "IMP_TESTR1,Test Register 1" tree.end tree "Memory Protection Unit EL1" group.long c15:0x0001++0x00 line.long 0x00 "SCTLR,System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" rbitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled" newline bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies EL1 Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 18. "NTWE,Do not trap WFE (Wait for Event) instruction" "Trapped,Not trapped" newline bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled" bitfld.long 0x00 16. "NTWI,Do not trap WFI (Wait For Interrupt) instruction" "Trapped,Not trapped" bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,EL1-controlled MPU enable" "Disabled,Enabled" newline rgroup.long c15:0x400++0x00 line.long 0x00 "MPUIR,MPU Type Register" bitfld.long 0x00 8.--15. 1. "DREGION,Number of programmable memory regions" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,Reserved,Reserved,Reserved,20,Reserved,Reserved,Reserved,24,?..." bitfld.long 0x00 0. "NU,Not unified MPU" "Unified,?..." if (((per.l(c15:0x400))&0xFF00)>=0x1800) group.long c15:0x0126++0x00 line.long 0x00 "PRSELR,Protection Region Selection Register" bitfld.long 0x00 0.--4. "REGION,Indicates the memory region accessed by PRBAR and PRBAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (((per.l(c15:0x400))&0xFF00)>=0x1400) group.long c15:0x0126++0x00 line.long 0x00 "PRSELR,Protection Region Selection Register" bitfld.long 0x00 0.--4. "REGION,Indicates the memory region accessed by PRBAR and PRBAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..." elif (((per.l(c15:0x400))&0xFF00)>=0x1000) group.long c15:0x0126++0x00 line.long 0x00 "PRSELR,Protection Region Selection Register" bitfld.long 0x00 0.--3. "REGION,Indicates the memory region accessed by PRBAR and PRBAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long c15:0x0126++0x00 hide.long 0x00 "PRSELR,Protection Region Selection Register" endif group.long c15:0x0036++0x00 line.long 0x00 "PRBAR,Protection Region Base Address Register" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:0x0136++0x00 line.long 0x00 "PRLAR,Protection Region Limit Address Register" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" tree "MPU regions" if (((per.l(c15:0x400))&0xFF00)>=0x1000) group.long c15:(0x0086+0x0)++0x00 "Region 0" line.long 0x00 "PRBAR0,Protection Region Base Address Register 0" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x0)++0x00 line.long 0x00 "PRLAR0,Protection Region Limit Address Register 0" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x0)++0x00 "Region 1" line.long 0x00 "PRBAR1,Protection Region Base Address Register 1" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x0)++0x00 line.long 0x00 "PRLAR1,Protection Region Limit Address Register 1" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x10)++0x00 "Region 2" line.long 0x00 "PRBAR2,Protection Region Base Address Register 2" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x10)++0x00 line.long 0x00 "PRLAR2,Protection Region Limit Address Register 2" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x10)++0x00 "Region 3" line.long 0x00 "PRBAR3,Protection Region Base Address Register 3" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x10)++0x00 line.long 0x00 "PRLAR3,Protection Region Limit Address Register 3" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x20)++0x00 "Region 4" line.long 0x00 "PRBAR4,Protection Region Base Address Register 4" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x20)++0x00 line.long 0x00 "PRLAR4,Protection Region Limit Address Register 4" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x20)++0x00 "Region 5" line.long 0x00 "PRBAR5,Protection Region Base Address Register 5" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x20)++0x00 line.long 0x00 "PRLAR5,Protection Region Limit Address Register 5" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x30)++0x00 "Region 6" line.long 0x00 "PRBAR6,Protection Region Base Address Register 6" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x30)++0x00 line.long 0x00 "PRLAR6,Protection Region Limit Address Register 6" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x30)++0x00 "Region 7" line.long 0x00 "PRBAR7,Protection Region Base Address Register 7" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x30)++0x00 line.long 0x00 "PRLAR7,Protection Region Limit Address Register 7" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x40)++0x00 "Region 8" line.long 0x00 "PRBAR8,Protection Region Base Address Register 8" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x40)++0x00 line.long 0x00 "PRLAR8,Protection Region Limit Address Register 8" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x40)++0x00 "Region 9" line.long 0x00 "PRBAR9,Protection Region Base Address Register 9" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x40)++0x00 line.long 0x00 "PRLAR9,Protection Region Limit Address Register 9" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x50)++0x00 "Region 10" line.long 0x00 "PRBAR10,Protection Region Base Address Register 10" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x50)++0x00 line.long 0x00 "PRLAR10,Protection Region Limit Address Register 10" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x50)++0x00 "Region 11" line.long 0x00 "PRBAR11,Protection Region Base Address Register 11" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x50)++0x00 line.long 0x00 "PRLAR11,Protection Region Limit Address Register 11" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x60)++0x00 "Region 12" line.long 0x00 "PRBAR12,Protection Region Base Address Register 12" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x60)++0x00 line.long 0x00 "PRLAR12,Protection Region Limit Address Register 12" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x60)++0x00 "Region 13" line.long 0x00 "PRBAR13,Protection Region Base Address Register 13" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x60)++0x00 line.long 0x00 "PRLAR13,Protection Region Limit Address Register 13" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0086+0x70)++0x00 "Region 14" line.long 0x00 "PRBAR14,Protection Region Base Address Register 14" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0186+0x70)++0x00 line.long 0x00 "PRLAR14,Protection Region Limit Address Register 14" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x0486+0x70)++0x00 "Region 15" line.long 0x00 "PRBAR15,Protection Region Base Address Register 15" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x0586+0x70)++0x00 line.long 0x00 "PRLAR15,Protection Region Limit Address Register 15" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x0086+0x0)++0x00 "Region 0 (not implemented)" hide.long 0x00 "PRBAR0,Protection Region Base Address Register 0" newline hgroup.long c15:(0x0186+0x0)++0x00 hide.long 0x00 "PRLAR0,Protection Region Limit Address Register 0" hgroup.long c15:(0x0486+0x0)++0x00 "Region 1 (not implemented)" hide.long 0x00 "PRBAR1,Protection Region Base Address Register 1" newline hgroup.long c15:(0x0586+0x0)++0x00 hide.long 0x00 "PRLAR1,Protection Region Limit Address Register 1" hgroup.long c15:(0x0086+0x10)++0x00 "Region 2 (not implemented)" hide.long 0x00 "PRBAR2,Protection Region Base Address Register 2" newline hgroup.long c15:(0x0186+0x10)++0x00 hide.long 0x00 "PRLAR2,Protection Region Limit Address Register 2" hgroup.long c15:(0x0486+0x10)++0x00 "Region 3 (not implemented)" hide.long 0x00 "PRBAR3,Protection Region Base Address Register 3" newline hgroup.long c15:(0x0586+0x10)++0x00 hide.long 0x00 "PRLAR3,Protection Region Limit Address Register 3" hgroup.long c15:(0x0086+0x20)++0x00 "Region 4 (not implemented)" hide.long 0x00 "PRBAR4,Protection Region Base Address Register 4" newline hgroup.long c15:(0x0186+0x20)++0x00 hide.long 0x00 "PRLAR4,Protection Region Limit Address Register 4" hgroup.long c15:(0x0486+0x20)++0x00 "Region 5 (not implemented)" hide.long 0x00 "PRBAR5,Protection Region Base Address Register 5" newline hgroup.long c15:(0x0586+0x20)++0x00 hide.long 0x00 "PRLAR5,Protection Region Limit Address Register 5" hgroup.long c15:(0x0086+0x30)++0x00 "Region 6 (not implemented)" hide.long 0x00 "PRBAR6,Protection Region Base Address Register 6" newline hgroup.long c15:(0x0186+0x30)++0x00 hide.long 0x00 "PRLAR6,Protection Region Limit Address Register 6" hgroup.long c15:(0x0486+0x30)++0x00 "Region 7 (not implemented)" hide.long 0x00 "PRBAR7,Protection Region Base Address Register 7" newline hgroup.long c15:(0x0586+0x30)++0x00 hide.long 0x00 "PRLAR7,Protection Region Limit Address Register 7" hgroup.long c15:(0x0086+0x40)++0x00 "Region 8 (not implemented)" hide.long 0x00 "PRBAR8,Protection Region Base Address Register 8" newline hgroup.long c15:(0x0186+0x40)++0x00 hide.long 0x00 "PRLAR8,Protection Region Limit Address Register 8" hgroup.long c15:(0x0486+0x40)++0x00 "Region 9 (not implemented)" hide.long 0x00 "PRBAR9,Protection Region Base Address Register 9" newline hgroup.long c15:(0x0586+0x40)++0x00 hide.long 0x00 "PRLAR9,Protection Region Limit Address Register 9" hgroup.long c15:(0x0086+0x50)++0x00 "Region 10 (not implemented)" hide.long 0x00 "PRBAR10,Protection Region Base Address Register 10" newline hgroup.long c15:(0x0186+0x50)++0x00 hide.long 0x00 "PRLAR10,Protection Region Limit Address Register 10" hgroup.long c15:(0x0486+0x50)++0x00 "Region 11 (not implemented)" hide.long 0x00 "PRBAR11,Protection Region Base Address Register 11" newline hgroup.long c15:(0x0586+0x50)++0x00 hide.long 0x00 "PRLAR11,Protection Region Limit Address Register 11" hgroup.long c15:(0x0086+0x60)++0x00 "Region 12 (not implemented)" hide.long 0x00 "PRBAR12,Protection Region Base Address Register 12" newline hgroup.long c15:(0x0186+0x60)++0x00 hide.long 0x00 "PRLAR12,Protection Region Limit Address Register 12" hgroup.long c15:(0x0486+0x60)++0x00 "Region 13 (not implemented)" hide.long 0x00 "PRBAR13,Protection Region Base Address Register 13" newline hgroup.long c15:(0x0586+0x60)++0x00 hide.long 0x00 "PRLAR13,Protection Region Limit Address Register 13" hgroup.long c15:(0x0086+0x70)++0x00 "Region 14 (not implemented)" hide.long 0x00 "PRBAR14,Protection Region Base Address Register 14" newline hgroup.long c15:(0x0186+0x70)++0x00 hide.long 0x00 "PRLAR14,Protection Region Limit Address Register 14" hgroup.long c15:(0x0486+0x70)++0x00 "Region 15 (not implemented)" hide.long 0x00 "PRBAR15,Protection Region Base Address Register 15" newline hgroup.long c15:(0x0586+0x70)++0x00 hide.long 0x00 "PRLAR15,Protection Region Limit Address Register 15" endif if (((per.l(c15:0x400))&0xFF00)>=0x1400) group.long c15:(0x1086+0x0)++0x00 "Region 16" line.long 0x00 "PRBAR16,Protection Region Base Address Register 16" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1186+0x0)++0x00 line.long 0x00 "PRLAR16,Protection Region Limit Address Register 16" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1486+0x0)++0x00 "Region 17" line.long 0x00 "PRBAR17,Protection Region Base Address Register 17" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1586+0x0)++0x00 line.long 0x00 "PRLAR17,Protection Region Limit Address Register 17" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1086+0x10)++0x00 "Region 18" line.long 0x00 "PRBAR18,Protection Region Base Address Register 18" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1186+0x10)++0x00 line.long 0x00 "PRLAR18,Protection Region Limit Address Register 18" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1486+0x10)++0x00 "Region 19" line.long 0x00 "PRBAR19,Protection Region Base Address Register 19" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1586+0x10)++0x00 line.long 0x00 "PRLAR19,Protection Region Limit Address Register 19" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x1086+0x0)++0x00 "Region 16 (not implemented)" hide.long 0x00 "PRBAR16,Protection Region Base Address Register 16" newline hgroup.long c15:(0x1186+0x0)++0x00 hide.long 0x00 "PRLAR16,Protection Region Limit Address Register 16" hgroup.long c15:(0x1486+0x0)++0x00 "Region 17 (not implemented)" hide.long 0x00 "PRBAR17,Protection Region Base Address Register 17" newline hgroup.long c15:(0x1586+0x0)++0x00 hide.long 0x00 "PRLAR17,Protection Region Limit Address Register 17" hgroup.long c15:(0x1086+0x10)++0x00 "Region 18 (not implemented)" hide.long 0x00 "PRBAR18,Protection Region Base Address Register 18" newline hgroup.long c15:(0x1186+0x10)++0x00 hide.long 0x00 "PRLAR18,Protection Region Limit Address Register 18" hgroup.long c15:(0x1486+0x10)++0x00 "Region 19 (not implemented)" hide.long 0x00 "PRBAR19,Protection Region Base Address Register 19" newline hgroup.long c15:(0x1586+0x10)++0x00 hide.long 0x00 "PRLAR19,Protection Region Limit Address Register 19" endif if (((per.l(c15:0x400))&0xFF00)>=0x1800) group.long c15:(0x1086+0x20)++0x00 "Region 20" line.long 0x00 "PRBAR20,Protection Region Base Address Register 20" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1186+0x20)++0x00 line.long 0x00 "PRLAR20,Protection Region Limit Address Register 20" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1486+0x20)++0x00 "Region 21" line.long 0x00 "PRBAR21,Protection Region Base Address Register 21" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1586+0x20)++0x00 line.long 0x00 "PRLAR21,Protection Region Limit Address Register 21" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1086+0x30)++0x00 "Region 22" line.long 0x00 "PRBAR22,Protection Region Base Address Register 22" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1186+0x30)++0x00 line.long 0x00 "PRLAR22,Protection Region Limit Address Register 22" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x1486+0x30)++0x00 "Region 23" line.long 0x00 "PRBAR23,Protection Region Base Address Register 23" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access Permission bits" "None/RW,R/W,None/RO,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x1586+0x30)++0x00 line.long 0x00 "PRLAR23,Protection Region Limit Address Register 23" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL1 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x1086+0x20)++0x00 "Region 20 (not implemented)" hide.long 0x00 "PRBAR20,Protection Region Base Address Register 20" newline hgroup.long c15:(0x1186+0x20)++0x00 hide.long 0x00 "PRLAR20,Protection Region Limit Address Register 20" hgroup.long c15:(0x1486+0x20)++0x00 "Region 21 (not implemented)" hide.long 0x00 "PRBAR21,Protection Region Base Address Register 21" newline hgroup.long c15:(0x1586+0x20)++0x00 hide.long 0x00 "PRLAR21,Protection Region Limit Address Register 21" hgroup.long c15:(0x1086+0x30)++0x00 "Region 22 (not implemented)" hide.long 0x00 "PRBAR22,Protection Region Base Address Register 22" newline hgroup.long c15:(0x1186+0x30)++0x00 hide.long 0x00 "PRLAR22,Protection Region Limit Address Register 22" hgroup.long c15:(0x1486+0x30)++0x00 "Region 23 (not implemented)" hide.long 0x00 "PRBAR23,Protection Region Base Address Register 23" newline hgroup.long c15:(0x1586+0x30)++0x00 hide.long 0x00 "PRLAR23,Protection Region Limit Address Register 23" endif tree.end tree.end tree "Memory Protection Unit EL2" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled" newline bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled" bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,EL2-controlled MPU enable" "Disabled,Enabled" newline rgroup.long c15:0x4400++0x00 line.long 0x00 "HMPUIR,Hypervisor MPU Type Register" bitfld.long 0x00 0.--7. 1. "REGION,Identifies the number of implemented regions" "0,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,Reserved,Reserved,Reserved,20,Reserved,Reserved,Reserved,24,?..." if (((per.l(c15:0x4400))&0xFF)>=0x18) group.long c15:0x4116++0x00 line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register" bitfld.long 0x00 23. "EN23,Region enable 23" "Disabled,Enabled" bitfld.long 0x00 22. "EN22,Region enable 22" "Disabled,Enabled" bitfld.long 0x00 21. "EN21,Region enable 21" "Disabled,Enabled" newline bitfld.long 0x00 20. "EN20,Region enable 20" "Disabled,Enabled" bitfld.long 0x00 19. "EN19,Region enable 19" "Disabled,Enabled" bitfld.long 0x00 18. "EN18,Region enable 18" "Disabled,Enabled" newline bitfld.long 0x00 17. "EN17,Region enable 17" "Disabled,Enabled" bitfld.long 0x00 16. "EN16,Region enable 16" "Disabled,Enabled" bitfld.long 0x00 15. "EN15,Region enable 15" "Disabled,Enabled" newline bitfld.long 0x00 14. "EN14,Region enable 14" "Disabled,Enabled" bitfld.long 0x00 13. "EN13,Region enable 13" "Disabled,Enabled" bitfld.long 0x00 12. "EN12,Region enable 12" "Disabled,Enabled" newline bitfld.long 0x00 11. "EN11,Region enable 11" "Disabled,Enabled" bitfld.long 0x00 10. "EN10,Region enable 10" "Disabled,Enabled" bitfld.long 0x00 9. "EN9,Region enable 9" "Disabled,Enabled" newline bitfld.long 0x00 8. "EN8,Region enable 8" "Disabled,Enabled" bitfld.long 0x00 7. "EN7,Region enable 7" "Disabled,Enabled" bitfld.long 0x00 6. "EN6,Region enable 6" "Disabled,Enabled" newline bitfld.long 0x00 5. "EN5,Region enable 5" "Disabled,Enabled" bitfld.long 0x00 4. "EN4,Region enable 4" "Disabled,Enabled" bitfld.long 0x00 3. "EN3,Region enable 3" "Disabled,Enabled" newline bitfld.long 0x00 2. "EN2,Region enable 2" "Disabled,Enabled" bitfld.long 0x00 1. "EN1,Region enable 1" "Disabled,Enabled" bitfld.long 0x00 0. "EN0,Region enable 0" "Disabled,Enabled" elif (((per.l(c15:0x4400))&0xFF)>=0x14) group.long c15:0x4116++0x00 line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register" bitfld.long 0x00 19. "EN19,Region enable 19" "Disabled,Enabled" bitfld.long 0x00 18. "EN18,Region enable 18" "Disabled,Enabled" bitfld.long 0x00 17. "EN17,Region enable 17" "Disabled,Enabled" newline bitfld.long 0x00 16. "EN16,Region enable 16" "Disabled,Enabled" bitfld.long 0x00 15. "EN15,Region enable 15" "Disabled,Enabled" bitfld.long 0x00 14. "EN14,Region enable 14" "Disabled,Enabled" newline bitfld.long 0x00 13. "EN13,Region enable 13" "Disabled,Enabled" bitfld.long 0x00 12. "EN12,Region enable 12" "Disabled,Enabled" bitfld.long 0x00 11. "EN11,Region enable 11" "Disabled,Enabled" newline bitfld.long 0x00 10. "EN10,Region enable 10" "Disabled,Enabled" bitfld.long 0x00 9. "EN9,Region enable 9" "Disabled,Enabled" bitfld.long 0x00 8. "EN8,Region enable 8" "Disabled,Enabled" newline bitfld.long 0x00 7. "EN7,Region enable 7" "Disabled,Enabled" bitfld.long 0x00 6. "EN6,Region enable 6" "Disabled,Enabled" bitfld.long 0x00 5. "EN5,Region enable 5" "Disabled,Enabled" newline bitfld.long 0x00 4. "EN4,Region enable 4" "Disabled,Enabled" bitfld.long 0x00 3. "EN3,Region enable 3" "Disabled,Enabled" bitfld.long 0x00 2. "EN2,Region enable 2" "Disabled,Enabled" newline bitfld.long 0x00 1. "EN1,Region enable 1" "Disabled,Enabled" bitfld.long 0x00 0. "EN0,Region enable 0" "Disabled,Enabled" elif (((per.l(c15:0x4400))&0xFF)>=0x10) group.long c15:0x4116++0x00 line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register" bitfld.long 0x00 15. "EN15,Region enable 15" "Disabled,Enabled" bitfld.long 0x00 14. "EN14,Region enable 14" "Disabled,Enabled" bitfld.long 0x00 13. "EN13,Region enable 13" "Disabled,Enabled" newline bitfld.long 0x00 12. "EN12,Region enable 12" "Disabled,Enabled" bitfld.long 0x00 11. "EN11,Region enable 11" "Disabled,Enabled" bitfld.long 0x00 10. "EN10,Region enable 10" "Disabled,Enabled" newline bitfld.long 0x00 9. "EN9,Region enable 9" "Disabled,Enabled" bitfld.long 0x00 8. "EN8,Region enable 8" "Disabled,Enabled" bitfld.long 0x00 7. "EN7,Region enable 7" "Disabled,Enabled" newline bitfld.long 0x00 6. "EN6,Region enable 6" "Disabled,Enabled" bitfld.long 0x00 5. "EN5,Region enable 5" "Disabled,Enabled" bitfld.long 0x00 4. "EN4,Region enable 4" "Disabled,Enabled" newline bitfld.long 0x00 3. "EN3,Region enable 3" "Disabled,Enabled" bitfld.long 0x00 2. "EN2,Region enable 2" "Disabled,Enabled" bitfld.long 0x00 1. "EN1,Region enable 1" "Disabled,Enabled" newline bitfld.long 0x00 0. "EN0,Region enable 0" "Disabled,Enabled" else rgroup.long c15:0x4116++0x00 line.long 0x00 "HPRENR,Hypervisor MPU Region Enable Register" endif if (((per.l(c15:0x4400))&0xFF)>=0x18) group.long c15:0x4126++0x00 line.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register" bitfld.long 0x00 0.--4. "REGION,The number of the current region visible in HPRBAR and HPRLAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (((per.l(c15:0x4400))&0xFF)>=0x14) group.long c15:0x4126++0x00 line.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register" bitfld.long 0x00 0.--4. "REGION,The number of the current region visible in HPRBAR and HPRLAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..." elif (((per.l(c15:0x4400))&0xFF)>=0x10) group.long c15:0x4126++0x00 line.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register" bitfld.long 0x00 0.--3. "REGION,The number of the current region visible in HPRBAR and HPRLAR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else hgroup.long c15:0x4126++0x00 hide.long 0x00 "HPRSELR,Hypervisor Protection Region Selection Register" endif group.long c15:0x4036++0x00 line.long 0x00 "HPRBAR,Hypervisor Protection Region Base Address Register" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:0x4136++0x00 line.long 0x00 "HPRLAR,Hypervisor Protection Region Limit Address Register" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" tree "MPU regions" if (((per.l(c15:0x4400))&0xFF)>=0x10) group.long c15:(0x4086+0x0)++0x00 "Region 0" line.long 0x00 "HPRBAR0,Hypervisor Protection Region Base Address Register 0" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x0)++0x00 line.long 0x00 "HPRLAR0,Hypervisor Protection Region Limit Address Register 0" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x0)++0x00 "Region 1" line.long 0x00 "HPRBAR1,Hypervisor Protection Region Base Address Register 1" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x0)++0x00 line.long 0x00 "HPRLAR1,Hypervisor Protection Region Limit Address Register 1" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x10)++0x00 "Region 2" line.long 0x00 "HPRBAR2,Hypervisor Protection Region Base Address Register 2" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x10)++0x00 line.long 0x00 "HPRLAR2,Hypervisor Protection Region Limit Address Register 2" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x10)++0x00 "Region 3" line.long 0x00 "HPRBAR3,Hypervisor Protection Region Base Address Register 3" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x10)++0x00 line.long 0x00 "HPRLAR3,Hypervisor Protection Region Limit Address Register 3" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x20)++0x00 "Region 4" line.long 0x00 "HPRBAR4,Hypervisor Protection Region Base Address Register 4" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x20)++0x00 line.long 0x00 "HPRLAR4,Hypervisor Protection Region Limit Address Register 4" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x20)++0x00 "Region 5" line.long 0x00 "HPRBAR5,Hypervisor Protection Region Base Address Register 5" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x20)++0x00 line.long 0x00 "HPRLAR5,Hypervisor Protection Region Limit Address Register 5" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x30)++0x00 "Region 6" line.long 0x00 "HPRBAR6,Hypervisor Protection Region Base Address Register 6" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x30)++0x00 line.long 0x00 "HPRLAR6,Hypervisor Protection Region Limit Address Register 6" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x30)++0x00 "Region 7" line.long 0x00 "HPRBAR7,Hypervisor Protection Region Base Address Register 7" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x30)++0x00 line.long 0x00 "HPRLAR7,Hypervisor Protection Region Limit Address Register 7" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x40)++0x00 "Region 8" line.long 0x00 "HPRBAR8,Hypervisor Protection Region Base Address Register 8" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x40)++0x00 line.long 0x00 "HPRLAR8,Hypervisor Protection Region Limit Address Register 8" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x40)++0x00 "Region 9" line.long 0x00 "HPRBAR9,Hypervisor Protection Region Base Address Register 9" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x40)++0x00 line.long 0x00 "HPRLAR9,Hypervisor Protection Region Limit Address Register 9" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x50)++0x00 "Region 10" line.long 0x00 "HPRBAR10,Hypervisor Protection Region Base Address Register 10" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x50)++0x00 line.long 0x00 "HPRLAR10,Hypervisor Protection Region Limit Address Register 10" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x50)++0x00 "Region 11" line.long 0x00 "HPRBAR11,Hypervisor Protection Region Base Address Register 11" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x50)++0x00 line.long 0x00 "HPRLAR11,Hypervisor Protection Region Limit Address Register 11" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x60)++0x00 "Region 12" line.long 0x00 "HPRBAR12,Hypervisor Protection Region Base Address Register 12" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x60)++0x00 line.long 0x00 "HPRLAR12,Hypervisor Protection Region Limit Address Register 12" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x60)++0x00 "Region 13" line.long 0x00 "HPRBAR13,Hypervisor Protection Region Base Address Register 13" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x60)++0x00 line.long 0x00 "HPRLAR13,Hypervisor Protection Region Limit Address Register 13" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4086+0x70)++0x00 "Region 14" line.long 0x00 "HPRBAR14,Hypervisor Protection Region Base Address Register 14" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4186+0x70)++0x00 line.long 0x00 "HPRLAR14,Hypervisor Protection Region Limit Address Register 14" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x4486+0x70)++0x00 "Region 15" line.long 0x00 "HPRBAR15,Hypervisor Protection Region Base Address Register 15" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x4586+0x70)++0x00 line.long 0x00 "HPRLAR15,Hypervisor Protection Region Limit Address Register 15" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x4086+0x0)++0x00 "Region 0 (not implemented)" hide.long 0x00 "HPRBAR0,Hypervisor Protection Region Base Address Register 0" newline hgroup.long c15:(0x4186+0x0)++0x00 hide.long 0x00 "HPRLAR0,Hypervisor Protection Region Limit Address Register 0" hgroup.long c15:(0x4486+0x0)++0x00 "Region 1 (not implemented)" hide.long 0x00 "HPRBAR1,Hypervisor Protection Region Base Address Register 1" newline hgroup.long c15:(0x4586+0x0)++0x00 hide.long 0x00 "HPRLAR1,Hypervisor Protection Region Limit Address Register 1" hgroup.long c15:(0x4086+0x10)++0x00 "Region 2 (not implemented)" hide.long 0x00 "HPRBAR2,Hypervisor Protection Region Base Address Register 2" newline hgroup.long c15:(0x4186+0x10)++0x00 hide.long 0x00 "HPRLAR2,Hypervisor Protection Region Limit Address Register 2" hgroup.long c15:(0x4486+0x10)++0x00 "Region 3 (not implemented)" hide.long 0x00 "HPRBAR3,Hypervisor Protection Region Base Address Register 3" newline hgroup.long c15:(0x4586+0x10)++0x00 hide.long 0x00 "HPRLAR3,Hypervisor Protection Region Limit Address Register 3" hgroup.long c15:(0x4086+0x20)++0x00 "Region 4 (not implemented)" hide.long 0x00 "HPRBAR4,Hypervisor Protection Region Base Address Register 4" newline hgroup.long c15:(0x4186+0x20)++0x00 hide.long 0x00 "HPRLAR4,Hypervisor Protection Region Limit Address Register 4" hgroup.long c15:(0x4486+0x20)++0x00 "Region 5 (not implemented)" hide.long 0x00 "HPRBAR5,Hypervisor Protection Region Base Address Register 5" newline hgroup.long c15:(0x4586+0x20)++0x00 hide.long 0x00 "HPRLAR5,Hypervisor Protection Region Limit Address Register 5" hgroup.long c15:(0x4086+0x30)++0x00 "Region 6 (not implemented)" hide.long 0x00 "HPRBAR6,Hypervisor Protection Region Base Address Register 6" newline hgroup.long c15:(0x4186+0x30)++0x00 hide.long 0x00 "HPRLAR6,Hypervisor Protection Region Limit Address Register 6" hgroup.long c15:(0x4486+0x30)++0x00 "Region 7 (not implemented)" hide.long 0x00 "HPRBAR7,Hypervisor Protection Region Base Address Register 7" newline hgroup.long c15:(0x4586+0x30)++0x00 hide.long 0x00 "HPRLAR7,Hypervisor Protection Region Limit Address Register 7" hgroup.long c15:(0x4086+0x40)++0x00 "Region 8 (not implemented)" hide.long 0x00 "HPRBAR8,Hypervisor Protection Region Base Address Register 8" newline hgroup.long c15:(0x4186+0x40)++0x00 hide.long 0x00 "HPRLAR8,Hypervisor Protection Region Limit Address Register 8" hgroup.long c15:(0x4486+0x40)++0x00 "Region 9 (not implemented)" hide.long 0x00 "HPRBAR9,Hypervisor Protection Region Base Address Register 9" newline hgroup.long c15:(0x4586+0x40)++0x00 hide.long 0x00 "HPRLAR9,Hypervisor Protection Region Limit Address Register 9" hgroup.long c15:(0x4086+0x50)++0x00 "Region 10 (not implemented)" hide.long 0x00 "HPRBAR10,Hypervisor Protection Region Base Address Register 10" newline hgroup.long c15:(0x4186+0x50)++0x00 hide.long 0x00 "HPRLAR10,Hypervisor Protection Region Limit Address Register 10" hgroup.long c15:(0x4486+0x50)++0x00 "Region 11 (not implemented)" hide.long 0x00 "HPRBAR11,Hypervisor Protection Region Base Address Register 11" newline hgroup.long c15:(0x4586+0x50)++0x00 hide.long 0x00 "HPRLAR11,Hypervisor Protection Region Limit Address Register 11" hgroup.long c15:(0x4086+0x60)++0x00 "Region 12 (not implemented)" hide.long 0x00 "HPRBAR12,Hypervisor Protection Region Base Address Register 12" newline hgroup.long c15:(0x4186+0x60)++0x00 hide.long 0x00 "HPRLAR12,Hypervisor Protection Region Limit Address Register 12" hgroup.long c15:(0x4486+0x60)++0x00 "Region 13 (not implemented)" hide.long 0x00 "HPRBAR13,Hypervisor Protection Region Base Address Register 13" newline hgroup.long c15:(0x4586+0x60)++0x00 hide.long 0x00 "HPRLAR13,Hypervisor Protection Region Limit Address Register 13" hgroup.long c15:(0x4086+0x70)++0x00 "Region 14 (not implemented)" hide.long 0x00 "HPRBAR14,Hypervisor Protection Region Base Address Register 14" newline hgroup.long c15:(0x4186+0x70)++0x00 hide.long 0x00 "HPRLAR14,Hypervisor Protection Region Limit Address Register 14" hgroup.long c15:(0x4486+0x70)++0x00 "Region 15 (not implemented)" hide.long 0x00 "HPRBAR15,Hypervisor Protection Region Base Address Register 15" newline hgroup.long c15:(0x4586+0x70)++0x00 hide.long 0x00 "HPRLAR15,Hypervisor Protection Region Limit Address Register 15" endif if (((per.l(c15:0x4400))&0xFF)>=0x14) group.long c15:(0x5086+0x0)++0x00 "Region 16" line.long 0x00 "HPRBAR16,Hypervisor Protection Region Base Address Register 16" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5186+0x0)++0x00 line.long 0x00 "HPRLAR16,Hypervisor Protection Region Limit Address Register 16" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5486+0x0)++0x00 "Region 17" line.long 0x00 "HPRBAR17,Hypervisor Protection Region Base Address Register 17" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5586+0x0)++0x00 line.long 0x00 "HPRLAR17,Hypervisor Protection Region Limit Address Register 17" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5086+0x10)++0x00 "Region 18" line.long 0x00 "HPRBAR18,Hypervisor Protection Region Base Address Register 18" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5186+0x10)++0x00 line.long 0x00 "HPRLAR18,Hypervisor Protection Region Limit Address Register 18" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5486+0x10)++0x00 "Region 19" line.long 0x00 "HPRBAR19,Hypervisor Protection Region Base Address Register 19" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5586+0x10)++0x00 line.long 0x00 "HPRLAR19,Hypervisor Protection Region Limit Address Register 19" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x5086+0x0)++0x00 "Region 16 (not implemented)" hide.long 0x00 "HPRBAR16,Hypervisor Protection Region Base Address Register 16" newline hgroup.long c15:(0x5186+0x0)++0x00 hide.long 0x00 "HPRLAR16,Hypervisor Protection Region Limit Address Register 16" hgroup.long c15:(0x5486+0x0)++0x00 "Region 17 (not implemented)" hide.long 0x00 "HPRBAR17,Hypervisor Protection Region Base Address Register 17" newline hgroup.long c15:(0x5586+0x0)++0x00 hide.long 0x00 "HPRLAR17,Hypervisor Protection Region Limit Address Register 17" hgroup.long c15:(0x5086+0x10)++0x00 "Region 18 (not implemented)" hide.long 0x00 "HPRBAR18,Hypervisor Protection Region Base Address Register 18" newline hgroup.long c15:(0x5186+0x10)++0x00 hide.long 0x00 "HPRLAR18,Hypervisor Protection Region Limit Address Register 18" hgroup.long c15:(0x5486+0x10)++0x00 "Region 19 (not implemented)" hide.long 0x00 "HPRBAR19,Hypervisor Protection Region Base Address Register 19" newline hgroup.long c15:(0x5586+0x10)++0x00 hide.long 0x00 "HPRLAR19,Hypervisor Protection Region Limit Address Register 19" endif if (((per.l(c15:0x4400))&0xFF)>=0x18) group.long c15:(0x5086+0x20)++0x00 "Region 20" line.long 0x00 "HPRBAR20,Hypervisor Protection Region Base Address Register 20" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5186+0x20)++0x00 line.long 0x00 "HPRLAR20,Hypervisor Protection Region Limit Address Register 20" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5486+0x20)++0x00 "Region 21" line.long 0x00 "HPRBAR21,Hypervisor Protection Region Base Address Register 21" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5586+0x20)++0x00 line.long 0x00 "HPRLAR21,Hypervisor Protection Region Limit Address Register 21" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5086+0x30)++0x00 "Region 22" line.long 0x00 "HPRBAR22,Hypervisor Protection Region Base Address Register 22" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5186+0x30)++0x00 line.long 0x00 "HPRLAR22,Hypervisor Protection Region Limit Address Register 22" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" group.long c15:(0x5486+0x30)++0x00 "Region 23" line.long 0x00 "HPRBAR23,Hypervisor Protection Region Base Address Register 23" hexmask.long 0x00 6.--31. 0x40 "BASE,Contains bits[31:6] of the lower inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 3.--4. "SH,Shareability field" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.long 0x00 1.--2. "AP,Access permission bits" "R/W EL2 only,R/W,RO EL2 only,RO" newline bitfld.long 0x00 0. "XN,Execute-never" "0,1" group.long c15:(0x5586+0x30)++0x00 line.long 0x00 "HPRLAR23,Hypervisor Protection Region Limit Address Register 23" hexmask.long 0x00 6.--31. 0x40 "LIMIT,Contains bits[31:6] of the upper inclusive limit of the selected EL2 MPU memory region" bitfld.long 0x00 1.--3. "ATTRINDX[2:0],Associates a set of attributes in the HMAIR0/1 fields" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "EN,Region enable" "Disabled,Enabled" else hgroup.long c15:(0x5086+0x20)++0x00 "Region 20 (not implemented)" hide.long 0x00 "HPRBAR20,Hypervisor Protection Region Base Address Register 20" newline hgroup.long c15:(0x5186+0x20)++0x00 hide.long 0x00 "HPRLAR20,Hypervisor Protection Region Limit Address Register 20" hgroup.long c15:(0x5486+0x20)++0x00 "Region 21 (not implemented)" hide.long 0x00 "HPRBAR21,Hypervisor Protection Region Base Address Register 21" newline hgroup.long c15:(0x5586+0x20)++0x00 hide.long 0x00 "HPRLAR21,Hypervisor Protection Region Limit Address Register 21" hgroup.long c15:(0x5086+0x30)++0x00 "Region 22 (not implemented)" hide.long 0x00 "HPRBAR22,Hypervisor Protection Region Base Address Register 22" newline hgroup.long c15:(0x5186+0x30)++0x00 hide.long 0x00 "HPRLAR22,Hypervisor Protection Region Limit Address Register 22" hgroup.long c15:(0x5486+0x30)++0x00 "Region 23 (not implemented)" hide.long 0x00 "HPRBAR23,Hypervisor Protection Region Base Address Register 23" newline hgroup.long c15:(0x5586+0x30)++0x00 hide.long 0x00 "HPRLAR23,Hypervisor Protection Region Limit Address Register 23" endif tree.end tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x00 line.long 0x00 "VPIDR,Virtualization Processor ID Register" hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "ARCH,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme" hexmask.long.word 0x00 4.--15. 1. "PART,Primary part number" newline bitfld.long 0x00 0.--3. "REV,Minor revision of the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register" bitfld.long 0x00 30. "U,Single core system as distinct from core 0 in a cluster" "Part of a cluster,?..." bitfld.long 0x00 24. "MT,Multi-threading type approach for logical cores in lowest level of affinity" "Largely independent,?..." newline hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2" hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1" hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.long 0x00 21. "FI,Fast interrupts configuration enable" "Disabled,Enabled" newline bitfld.long 0x00 19. "WXN,Write permission implies Execute Never (XN)" "Not forced,Forced" bitfld.long 0x00 17. "BR,Background region enable" "Disabled,Enabled" bitfld.long 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction disable" "No,Yes" bitfld.long 0x00 5. "CP15BEN,CP15* barrier operations enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "C,Data cache enable" "Disabled,Enabled" bitfld.long 0x00 1. "A,Alignment fault checking enable" "Disabled,Enabled" bitfld.long 0x00 0. "M,EL2-controlled MPU enable" "Disabled,Enabled" group.long c15:0x4002++0x00 line.long 0x00 "VSCTLR,Virtualization System Control Register" hexmask.long.byte 0x00 16.--23. 1. "VMID,Virtual machine ID" bitfld.long 0x00 2. "S2NIE,Stage-2 normal interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. "S2DMAD,Stage-2 device multiple access disable" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 15. "TESTR1,Controls access to TESTR1 at EL0 and EL1" "Trapped,Enabled" bitfld.long 0x00 13. "ERR,Controls access to IMP_DCERR0, IMP_DCERR1, IMP_ICERR0, IMP_ICERR1, IMP_TCMERR0, IMP_TCMERR1, IMP_FLASHERR0 and IMP_FLASHERR1 registers" "Trapped,Enabled" bitfld.long 0x00 12. "INTMONR,Controls access to IMP_INTMONR at EL1" "Trapped,Enabled" newline bitfld.long 0x00 10. "BUSTIMEOUTR,Controls access to IMP_BUSTIMEOUTR at EL1" "Trapped,Enabled" bitfld.long 0x00 9. "QOSR,Controls access to QOSR at EL1" "Trapped,Enabled" bitfld.long 0x00 8. "PERIPHPREGIONR,Controls access to IMP_PERIPHPREGIONR at EL1" "Trapped,Enabled" newline bitfld.long 0x00 7. "FLASHIFREGIONR,Controls access to IMP_FLASHIFREGIONR at EL1" "Trapped,Enabled" bitfld.long 0x00 1. "CDBGDCI,Controls access to CDBGDCI at EL1" "Trapped,Enabled" bitfld.long 0x00 0. "CPUACTLR,IMP_CPUACTLR write access control" "Trapped,Enabled" rgroup.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap read of virtual memory controls" "Disabled,Enabled" bitfld.long 0x00 29. "HCD,HVC instruction disable" "No,Yes" bitfld.long 0x00 27. "TGE,Trap general exceptions" "Disabled,Enabled" newline bitfld.long 0x00 26. "TVM,Trap virtual memory controls" "Disabled,Enabled" bitfld.long 0x00 24. "TPU,Trap cache maintenance instructions that operate to the point of unification" "Disabled,Enabled" bitfld.long 0x00 23. "TPC,Trap Data Cache maintenance operations that operate to the point of coherency" "Disabled,Enabled" newline bitfld.long 0x00 22. "TSW,Trap data/unified cache maintenance instructions by set/way" "Disabled,Enabled" bitfld.long 0x00 21. "TAC,Trap ACTLR accesses" "Disabled,Enabled" bitfld.long 0x00 20. "TIDCP,Trap lockdown" "Disabled,Enabled" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled" newline bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled" newline bitfld.long 0x00 12. "DC,Default cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier shareability upgrade" "No effect,Inner shareable,Outer shareable,Full system" bitfld.long 0x00 9. "FB,Force broadcast" "Not forced,Forced" newline bitfld.long 0x00 8. "VA,Virtual asynchronous abort exception" "Not pending,Pending" bitfld.long 0x00 7. "VI,Virtual IRQ exception" "Not pending,Pending" bitfld.long 0x00 6. "VF,Virtual FIQ exception" "Not pending,Pending" newline bitfld.long 0x00 5. "AMO,A-bit mask override" "Disabled,Enabled" bitfld.long 0x00 4. "IMO,I-bit mask override" "Disabled,Enabled" bitfld.long 0x00 3. "FMO,F-bit mask override" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. "VM,Second stage of translation enable" "Disabled,Enabled" rgroup.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register 2" group.long c15:0x3054++0x00 line.long 0x00 "DSPSR,Debug Saved Program Status Register" bitfld.long 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.long 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.long 0x00 29. "C,Carry condition flag" "Not carry,Carry" newline bitfld.long 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" bitfld.long 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.long 0x00 21. "SS,Software step" "0,1" newline bitfld.long 0x00 20. "IL,Illegal execution state" "0,1" bitfld.long 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (if-then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (if-then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "GE,Greater than or equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9. "E,Endianness state bit" "Little,Big" bitfld.long 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" newline bitfld.long 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.long 0x00 6. "F,FIQ mask bit" "Not masked,Masked" bitfld.long 0x00 5. "T,T32 Instruction set state" "A32,T32" newline bitfld.long 0x00 4. "M[4],Execution state that the exception was taken from" "Reserved,AArch32" bitfld.long 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,Reserved,Reserved,Monitor,Abort,Reserved,Reserved,Hyp,Undefined,Reserved,Reserved,Reserved,System" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to hypervisor performance monitors registers disabled" "No,Yes" bitfld.long 0x00 17. "HPMD,Hypervisor performance monitors disable" "No,Yes" bitfld.long 0x00 11. "TDRA,Trap debug ROM access" "No effect,Valid" newline bitfld.long 0x00 10. "TDOSA,Trap debug OS-related register access" "No effect,Valid" bitfld.long 0x00 9. "TDA,Trap debug access" "No effect,Valid" bitfld.long 0x00 8. "TDE,Trap debug exceptions" "No effect,Valid" newline bitfld.long 0x00 7. "HPME,Hypervisor performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 6. "TPM,Trap performance monitors accesses" "No effect,Valid" bitfld.long 0x00 5. "TPMCR,Trap performance monitor control register accesses" "No effect,Valid" newline bitfld.long 0x00 0.--4. "HPMN,Defines the number of performance monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register" bitfld.long 0x00 31. "TCPAC,Trap coprocessor access control" "Not trapped,Trapped" bitfld.long 0x00 15. "TASE,Trap advanced SIMD extensions" "Not trapped,Trapped" newline bitfld.long 0x00 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped" bitfld.long 0x00 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap" bitfld.long 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap" bitfld.long 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap" newline bitfld.long 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap" bitfld.long 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap" bitfld.long 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap" newline bitfld.long 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap" bitfld.long 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap" bitfld.long 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap" newline bitfld.long 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap" bitfld.long 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap" bitfld.long 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap" newline bitfld.long 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap" bitfld.long 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap" rgroup.long c15:0x4301++0x00 line.long 0x00 "HACTLR2,Hypervisor Auxiliary Control Register 2" group.long c15:0x3154++0x00 line.long 0x00 "DLR,Debug Link Register" group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register" bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Internal interface,ATCM,BTCM,CTCM,?..." bitfld.long 0x00 0.--1. "TYPE,Fault type" "Undefined,Response,ECC on data,Bus timeout" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" if (((per.l(c15:0x4025))&0xFC000000)==(0x00000000||0x38000000||0x88000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." elif (((per.l(c15:0x4025))&0xFC000000)==0x04000000) if (((per.l(c15:0x4025))&0x01000000)==0x01000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.l(c15:0x4025))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) if (((per.l(c15:0x4025))&0x01000000)==0x01000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.long 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000)) if (((per.l(c15:0x4025))&0x01000000)==0x01000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--13. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.long 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--13. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--8. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000) if (((per.l(c15:0x4025))&0x01000000)==0x01000000) if (((per.l(c15:0x4025))&0x08)==0x00) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--8. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..." newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif else if (((per.l(c15:0x4025))&0x08)==0x00) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--8. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif endif elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000) if (((per.l(c15:0x4025))&0x01000000)==0x01000000) if (((per.l(c15:0x4025))&0x20)==0x20) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped" bitfld.long 0x00 0.--3. "COPROC,COPROC" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,0b1010,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped" endif else if (((per.l(c15:0x4025))&0x20)==0x20) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped" bitfld.long 0x00 0.--3. "COPROC,COPROC" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,0b1010,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.long 0x00 5. "TA,Indicates trapped use of advanced SIMD functionality" "Not trapped,Trapped" endif endif elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x48000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000)) if (((per.l(c15:0x4025))&0x3F)==0x10) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.long 0x00 10. "FNV,FAR not valid" "No,Yes" newline bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 0.--5. "IFSC,Instruction fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.long 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.long 0x00 0.--5. "IFSC,Instruction fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug,?..." endif elif (((per.l(c15:0x4025))&0xFD00003F)==(0x95000010||0x91000010)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.long 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword" bitfld.long 0x00 21. "SSE,Syndrome sign extend" "Not required,Required" bitfld.long 0x00 16.--19. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.long 0x00 10. "FNV,FAR not valid" "No,Yes" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not read" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..." elif (((per.l(c15:0x4025))&0xFD000000)==(0x95000000||0x91000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.long 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword" bitfld.long 0x00 21. "SSE,Syndrome sign extend" "Not required,Required" bitfld.long 0x00 16.--19. "SRT,Syndrome register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not read" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..." elif (((per.l(c15:0x4025))&0xFD00003F)==(0x90000010||0x94000010)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline bitfld.long 0x00 10. "FNV,FAR not valid" "No,Yes" newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not read" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..." elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR" bitfld.long 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes" bitfld.long 0x00 6. "WNR,Write not read" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data fault status code" "Reserved,Reserved,Reserved,Reserved,Translation fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Permission fault,Reserved,Reserved,Reserved,Synch. external abort,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synch. parity/ECC,SError/parity/ECC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache lockdown fault,Unsupported Exclusive access,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Hypervisor class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/MRC,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC executed,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Prefetch abort routed to hyp,Prefetch abort taken from hyp,PC alignment fault,Reserved,Data abort routed to hyp,Data abort taken from hyp,?..." bitfld.long 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" endif group.long c15:0x4115++0x00 line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Register" bitfld.long 0x00 2.--4. "PORT,Memory or port that caused the fault" "AXIM,Flash interface,LLPP,Reserved,ATCM,BTCM,CTCM,UNKNOWN" bitfld.long 0x00 0.--1. "TYPE,Fault type" "Undefined,Response,ECC on data,Bus timeout" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. "FIPA,Faulting IPA bits" tree.open "Hypervisor Memory Attribute Indirection Registers" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory. Outer Write-through transient. Allocate R=0 W=1,Normal Memory. Outer Write-through transient. Allocate R=1 W=0,Normal Memory. Outer Write-through transient. Allocate R=1 W=1,Normal Memory. Outer Non-Cacheable,Normal Memory. Outer Write-back transient. Allocate R=0 W=1,Normal Memory. Outer Write-back transient. Allocate R=1 W=0,Normal Memory. Outer Write-back transient. Allocate R=1 W=1,Normal Memory. Outer Write-through non-transient,Normal Memory. Outer Write-through non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-through non-transient. Allocate R=1 W=1,Normal Memory. Outer Write-back non-transient,Normal Memory. Outer Write-back non-transient. Allocate R=0 W=1,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=0,Normal Memory. Outer Write-back non-transient. Allocate R=1 W=1" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem|Normal mem)" "Device-nGnRnE memory| -UNPREDICTABLE-, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient, -UNPREDICTABLE- |Normal memory. Inner Write-through transient,Device-nGnRE memory|Normal memory. Inner Non-Cacheable, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient, -UNPREDICTABLE- |Normal memory. Inner Write-back transient,Device-nGRE memory |Normal memory. Inner Write-through, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-through non-transient,Device-GRE memory |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient, -UNPREDICTABLE- |Normal memory. Inner Write-back non-transient" rgroup.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" tree.end newline group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector base address" group.long c15:0x420C++0x00 line.long 0x00 "HRMR,Hypervisor Reset Management Register" bitfld.long 0x00 1. "RR,Reset request" "Not requested,Requested" group.long c15:0x1119++0x00 line.long 0x00 "IMP_BPCTLR,Branch Predictor Control Register" bitfld.long 0x00 2. "DBPEL2DIS,Disable dynamic branch predictor when running at EL2" "No,Yes" bitfld.long 0x00 1. "DBPEL1DIS,Disable dynamic branch predictor when running at EL1" "No,Yes" bitfld.long 0x00 0. "DBPEL0DIS,Disable dynamic branch predictor when running at EL0" "No,Yes" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x0100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. "CWG,Cache write-back granule" "Reserved,2 words,?..." bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 16.--19. "DMINLINE,D-cache minimum line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x00 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.long 0x00 0.--3. "IMINLINE,I-cache minimum line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." group.long c15:0x2000++0x00 line.long 0x00 "CSSELR,Cache Size Selection Register" rbitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,?..." bitfld.long 0x00 0. "IND,Instruction/not data" "Data/unified,Instruction" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. "WT,Write-through" "Not supported,Supported" bitfld.long 0x00 30. "WB,Write-back" "Not supported,?..." newline bitfld.long 0x00 29. "RA,Read-allocate" "Reserved,Supported" bitfld.long 0x00 28. "WA,Write-allocate" "Not supported,Supported" newline hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Number of words in each cache line" "Reserved,Reserved,16,?..." rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..." bitfld.long 0x00 27.--29. "LOUU,Level of unification" "Level 0,Level 1,?..." bitfld.long 0x00 24.--26. "LOC,Level of coherency" "Level 0,Level 1,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of unification inner shareable" "Level 0,Level 1,?..." bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..." newline bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..." newline bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..." newline bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,?..." bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "No cache,Instruction cache,Data cache,Both separated,?..." group.long c15:0x1019++0x00 line.long 0x00 "IMP_CSCTLR,Cache Segregation Control Register" bitfld.long 0x00 8.--10. "IFLW,Instruction cache flash ways" "Reserved,0,0-1,0-2,0-3,?..." bitfld.long 0x00 0.--2. "DFLW,Data cache flash ways" "Reserved,0,0-1,0-2,0-3,?..." group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" bitfld.quad 0x00 47. "FIXEDDIV,Enable fixed latency for integer divide instructions" "Disabled,Enabled" bitfld.quad 0x00 46. "ETACDIS,Disable PFU exception target address cache" "No,Yes" bitfld.quad 0x00 45. "OOODIVDIS,Disable out-of-order completion of divide instructions" "No,Yes" newline bitfld.quad 0x00 41. "TLACDIS,Disable the store unit (STU) tag lookup avoidance cache" "No,Yes" bitfld.quad 0x00 40. "FLASHNDDIS,Disable flash accesses use of non-flash-dedicated resources" "No,Yes" bitfld.quad 0x00 39. "FLASHARBCTL,Flash interface arbitration control" "D-side,I-side" newline bitfld.quad 0x00 38. "AXIMARBCTL,AXIM interface arbitration control" "D-side,I-side" bitfld.quad 0x00 33. "ISPECDIS,Disable I-side speculative access" "No,Yes" bitfld.quad 0x00 32. "DSPECDIS,Disable D-side speculative access" "No,Yes" newline bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes" bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes" bitfld.quad 0x00 25.--26. "WSTRNOL1ACTL,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled streaming" newline bitfld.quad 0x00 19.--20. "DPFSTRCTL,Number of independent data prefetch streams" "1,2,3,4" bitfld.quad 0x00 17. "STRIDECTL,Enable stride detection" "2,3" bitfld.quad 0x00 13.--15. "L1DPFCTL,L1 Data prefetch control" "Disabled,1 outstanding prefetch,2 outstanding prefetch,3 outstanding prefetch,4 outstanding prefetch,5 outstanding prefetch,6 outstanding prefetch,8 outstanding prefetch" newline bitfld.quad 0x00 11. "L1IPFCTL,L1 Instruction prefetch control" "Disabled,Enabled" bitfld.quad 0x00 10. "DMB2DSBEN,Enable data memory barrier behaving as data synchronization barrier" "Disabled,Enabled" wgroup.long c15:0x10EF++0x00 line.long 0x00 "IMP_CDBGDCI,Invalidate All Register" tree "Level 1 memory system" rgroup.long c15:0x300F++0x00 line.long 0x00 "IMP_CDBGDR0,Cache Debug Data Register 0" bitfld.long 0x00 22. "V,Valid" "0,1" hexmask.long.tbyte 0x00 0.--21. 1. "TB,Tag bits" rgroup.long c15:0x310F++0x00 line.long 0x00 "IMP_CDBGDR1,Cache Debug Data Register 1" wgroup.long c15:0x302F++0x00 line.long 0x00 "IMP_CDBGDCT,Data Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3" hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index" wgroup.long c15:0x312F++0x00 line.long 0x00 "IMP_CDBGICT,Instruction Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3" hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index" wgroup.long c15:0x304F++0x00 line.long 0x00 "IMP_CDBGDCD,Data Cache Data Read Operation Register" bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3" hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index" bitfld.long 0x00 3.--5. "DO,Data offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x314F++0x00 line.long 0x00 "IMP_CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3" hexmask.long.word 0x00 6.--12. 1. "SETIND,Set index" bitfld.long 0x00 3.--5. "DO,Data offset" "0,1,2,3,4,5,6,7" tree.end tree.end tree "System Performance Monitor" group.long c15:0x00C9++0x00 line.long 0x00 "PMCR,Performance Monitors Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,4,?..." bitfld.long 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock counter reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance counter reset" "No reset,Reset" bitfld.long 0x00 0. "E,All counters enable" "Disabled,Enabled" group.long c15:0x01C9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register" bitfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled" group.long c15:0x02C9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" bitfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled" group.long c15:0x03C9++0x00 line.long 0x00 "PMOVSR,Overflow Status Flags Register" eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" newline eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" wgroup.long c15:0x04C9++0x00 line.long 0x00 "PMSWINC,Software Increment Register" bitfld.long 0x00 3. "P3,PMN3 software increment" "No effect,Increment" bitfld.long 0x00 2. "P2,PMN2 software increment" "No effect,Increment" bitfld.long 0x00 1. "P1,PMN1 software increment" "No effect,Increment" bitfld.long 0x00 0. "P0,PMN0 software increment" "No effect,Increment" group.long c15:0x05C9++0x00 line.long 0x00 "PMSELR,Event Counter Selection Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.open "Common Event Identification Registers" rgroup.long c15:0x06C9++0x00 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 30. "CHAIN,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 27. "INST_SPEC,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Not implemented,Implemented" newline bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Not implemented,Implemented" bitfld.long 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. "MEM_ACCESS,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Not implemented,Implemented" newline bitfld.long 0x00 17. "CPU_CYCLES,CPU cycle" "Not implemented,Implemented" bitfld.long 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "UNALIGNED_LDST_RETIRED,Instruction architecturally executed condition code check pass unaligned load or store" "Not implemented,Implemented" bitfld.long 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" newline bitfld.long 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" newline bitfld.long 0x00 9. "EXC_TAKEN,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" newline bitfld.long 0x00 4. "L1D_CACHE,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "SW_INCR,Software increment" "Not implemented,Implemented" rgroup.long c15:0x07C9++0x00 line.long 0x00 "PMCEID1,Common Event Identification Register 1" bitfld.long 0x00 19. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented" bitfld.long 0x00 18. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented" bitfld.long 0x00 17. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Not implemented,Implemented" bitfld.long 0x00 16. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented" tree.end newline group.long c15:0x00D9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register [31:0]" group.quad c15:0x10090++0x01 line.quad 0x00 "PMCCNTR,Performance Monitor Cycle Count Register [63:0]" if (((per.l(c15:0x05C9))&0x1F)==0x1F) group.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Selected Event Type and Filter Register - PMCCFILTR" bitfld.long 0x00 31. "P,Privileged modes filtering" "Disabled,Enabled" bitfld.long 0x00 30. "U,User modes filtering" "Disabled,Enabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering" "Disabled,Enabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering" "Disabled,Enabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering" "Disabled,Enabled" elif (((per.l(c15:0x05C9))&0x1F)<=0x03) group.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Selected Event Type and Filter Register - PMEVTYPER" bitfld.long 0x00 31. "P,Privileged modes filtering" "Disabled,Enabled" bitfld.long 0x00 30. "U,User modes filtering" "Disabled,Enabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering" "Disabled,Enabled" bitfld.long 0x00 28. "NSU,Non-secure user modes filtering" "Disabled,Enabled" newline bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering" "Disabled,Enabled" bitfld.long 0x00 25. "MT,Multithreading" "Disabled,Enabled" hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event number" else rgroup.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Selected Event Type and Filter Register" endif group.long c15:0x02D9++0x00 line.long 0x00 "PMXEVCNTR,Selected Event Counter Register" group.long c15:0x00E9++0x00 line.long 0x00 "PMUSERENR,User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User enable" "Disabled,Enabled" group.long c15:0x01E9++0x00 line.long 0x00 "PMINTENSET,Interrupt Enable Set Register" bitfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,PMCNT3 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMCNT0 overflow interrupt enable" "Disabled,Enabled" group.long c15:0x02E9++0x00 line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. "C,CCNT overflow interrupt enable" "Disabled,Enabled" newline eventfld.long 0x00 3. "P3,PMCNT3 overflow interrupt enable" "Disabled,Enabled" eventfld.long 0x00 2. "P2,PMCNT2 overflow interrupt enable" "Disabled,Enabled" eventfld.long 0x00 1. "P1,PMCNT1 overflow interrupt enable" "Disabled,Enabled" eventfld.long 0x00 0. "P0,PMCNT0 overflow interrupt enable" "Disabled,Enabled" group.long c15:0x3E9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" group.long c15:(0x008E+0x0)++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x00CE+0x0)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Event Type Register 0" group.long c15:(0x008E+0x100)++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x00CE+0x100)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Event Type Register 1" group.long c15:(0x008E+0x200)++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x00CE+0x200)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Event Type Register 2" group.long c15:(0x008E+0x300)++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x00CE+0x300)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Event Type Register 3" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" rgroup.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" rgroup.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer EL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure EL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTPCT trigger bit, defined by EVNTI" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL1PCEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" newline bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter EL1 Physical Timer Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter EL1 Physical Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter EL1 Physical Compare Value Register" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter EL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter EL1 Virtual Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter EL1 Virtual Compare Value Register" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure EL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure EL2 Physical Timer Control Register" bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure EL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch32 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:(0x048C+0x0)++0x00 line.long 0x00 "ICC_AP0R0,Interrupt Controller Active Priorities Group 0x0 Register" bitfld.long 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:(0x048C+0xFFFFFFFFFFFFFC10)++0x00 line.long 0x00 "ICC_AP1R0,Interrupt Controller Active Priorities Group 0xFFFFFFFFFFFFFC10 Register" bitfld.long 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline group.long c15:(0x038C+0x0)++0x00 line.long 0x00 "ICC_BPR0,Interrupt Controller Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7" group.long c15:(0x038C+0x40)++0x00 line.long 0x00 "ICC_BPR1,Interrupt Controller Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Register for EL1" rbitfld.long 0x00 15. "A3V,Affinity 3 valid" "Not supported,?..." rbitfld.long 0x00 14. "SEIS,SEI support" "Not supported,?..." rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" bitfld.long 0x00 0. "CBPR,Common binary point register" "0,1" wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register" hexmask.long.word 0x00 0.--9. 1. "INTID,Interrupt ID" wgroup.long c15:(0x018C+0x0)++0x00 line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID from the corresponding ICC_IAR0 access" rgroup.long c15:(0x028C+0x0)++0x00 line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the highest priority pending Group 0 interrupt" rgroup.long c15:(0x008C+0x0)++0x00 line.long 0x00 "ICC_IAR0,Interrupt Controller Interrupt Acknowledge Register 0" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the signaled interrupt" group.long c15:(0x06CC+0x0)++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Controller Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enable group 0 interrupts" "Disabled,Enabled" wgroup.long c15:(0x018C+0x40)++0x00 line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID from the corresponding ICC_IAR0 access" rgroup.long c15:(0x028C+0x40)++0x00 line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the highest priority pending Group 1 interrupt" rgroup.long c15:(0x008C+0x40)++0x00 line.long 0x00 "ICC_IAR1,Interrupt Controller Interrupt Acknowledge Register 1" hexmask.long.word 0x00 0.--9. 1. "INTID,INTID of the signaled interrupt" group.long c15:(0x06CC+0x100)++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Controller Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enable group 1 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Interrupt Controller Interrupt Priority Mask Register" bitfld.long 0x00 3.--7. "PRIORITY,The priority mask level for the CPU interface" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Lowest" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Interrupt Controller Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" wgroup.quad c15:(0x120C0-0x0)++0x01 line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" bitfld.quad 0x00 0.--4. "TARGETLIST,Target list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.quad c15:(0x120C0-0x2000)++0x01 line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" bitfld.quad 0x00 0.--4. "TARGETLIST,Target list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Alias SGI Generation Register $2" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Disabled,Enabled" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" bitfld.quad 0x00 0.--4. "TARGETLIST,Target list" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "Reserved,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "Reserved,Yes" bitfld.long 0x00 0. "SRE,System register enable" "Reserved,Enabled" group.long c15:0x459C++0x00 line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2" bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Reserved,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "Reserved,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "Reserved,Yes" newline bitfld.long 0x00 0. "SRE,System register enable" "Reserved,Enabled" tree.end tree "AArch32 GIC Virtual CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:(0x048C+0x0)++0x00 line.long 0x00 "ICV_AP0R0,Interrupt Controller Virtual Active Priorities Group 0x0 Register 0" bitfld.long 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:(0x048C+0xFFFFFFFFFFFFFC10)++0x00 line.long 0x00 "ICV_AP1R0,Interrupt Controller Virtual Active Priorities Group 0xFFFFFFFFFFFFFC10 Register 0" bitfld.long 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline group.long c15:0x04CC++0x00 line.long 0x00 "ICV_CTLR,Interrupt Controller Virtual Control Register" rbitfld.long 0x00 15. "A3V,Affinity 3 valid" "Not supported,?..." rbitfld.long 0x00 14. "SEIS,SEI support" "Not supported,?..." rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1" bitfld.long 0x00 0. "CBPR,Common binary point register" "0,1" wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICV_DIR,Interrupt Controller Virtual Deactivate Interrupt Register" hexmask.long.word 0x00 0.--15. 1. "INTID,Interrupt ID" hgroup.long c15:(0x008C+0x0)++0x00 hide.long 0x00 "ICV_IAR0,Interrupt Controller Vitrtual Interrupt Acknowledge Register 0" wgroup.long c15:(0x018C+0x0)++0x00 line.long 0x00 "ICV_EOIR0,Interrupt Controller Vitrtual End Of Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,INTID from the corresponding ICC_IAR0 access" rgroup.long c15:(0x028C+0x0)++0x00 line.long 0x00 "ICV_HPPIR0,Interrupt Controller Vitrtual Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,INTID of the highest priority pending Group 0 interrupt" group.long c15:(0x038C+0x0)++0x00 line.long 0x00 "ICV_BPR0,Interrupt Controller Vitrtual Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7" hgroup.long c15:(0x008C+0x40)++0x00 hide.long 0x00 "ICV_IAR1,Interrupt Controller Vitrtual Interrupt Acknowledge Register 1" wgroup.long c15:(0x018C+0x40)++0x00 line.long 0x00 "ICV_EOIR1,Interrupt Controller Vitrtual End Of Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,INTID from the corresponding ICC_IAR1 access" rgroup.long c15:(0x028C+0x40)++0x00 line.long 0x00 "ICV_HPPIR1,Interrupt Controller Vitrtual Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,INTID of the highest priority pending Group 1 interrupt" group.long c15:(0x038C+0x40)++0x00 line.long 0x00 "ICV_BPR1,Interrupt Controller Vitrtual Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,5-bit interrupt priority field control" "Reserved,Reserved,2,3,4,5,6,7" group.long c15:0x07CC++0x00 line.long 0x00 "ICV_IGRPEN1,Interrupt Controller Virtual Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enable group 1 interrupts" "Disabled,Enabled" group.long c15:0x06CC++0x00 line.long 0x00 "ICV_IGRPEN0,Interrupt Controller Virtual Interrupt Group 0 Enable Register" bitfld.long 0x00 0. "ENABLE,Enable group 0 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICV_PMR,Interrupt Controller Virtual Interrupt Priority Mask Register" bitfld.long 0x00 3.--7. "PRIORITY,The priority mask level for the CPU interface" "Highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Lowest" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICV_RPR,Interrupt Controller Virtual Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Interrupt Controller Hypervisor Active Priorities Register" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.long 0x00 28. "P[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.long 0x00 27. "P[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.long 0x00 25. "P[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.long 0x00 23. "P[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.long 0x00 22. "P[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 18. "P[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.long 0x00 16. "P[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.long 0x00 15. "P[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.long 0x00 13. "P[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.long 0x00 11. "P[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.long 0x00 10. "P[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.long 0x00 4. "P[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.long 0x00 3. "P[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "P[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,Number of successful write to a virtual EOIR or DIR resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap virtual EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.long 0x00 12. "TALL1,Trap all virtual EL1 accesses to ICC_* system registers for Group 1 interrupts to EL2" "Not trapped,Trapped" newline bitfld.long 0x00 11. "TALL0,Trap all virtual EL1 accesses to ICC_* system registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.long 0x00 10. "TC,Trap all virtual EL1 accesses to system registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" bitfld.long 0x00 7. "VGRP1DIE,VM group 1 disabled interrupt enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM group 1 enabled interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "VGRP0DIE,VM group 0 disabled interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. "VGRP0EIE,VM group 0 enabled interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No pending interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List register entry not present interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,Interrupt Controller Hypervisor Control VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,Priority bits" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.long 0x00 26.--28. "PREBITS,Preemption bits" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.long 0x00 23.--25. "IDBITS,The number of virtual interrupt identifier bits supported" "16 bits,?..." bitfld.long 0x00 22. "SEIS,SEI Support" "Not supported,?..." newline bitfld.long 0x00 21. "A3V,Affinity 3 support" "Not supported,?..." bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Reserved,Not supported" bitfld.long 0x00 19. "TDS,Separate trapping EL1 writes to ICV_DIR supported" "Reserved,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers" "Reserved,Reserved,Reserved,4,?..." rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt Status Register" bitfld.long 0x00 7. "VGRP1D,vPE group 1 disabled" "No,Yes" bitfld.long 0x00 6. "VGRP1E,vPE group 1 enabled" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0D,vPE group 0 disabled" "No,Yes" bitfld.long 0x00 4. "VGRP0E,vPE group 0 enabled" "Disabled,Enabled" newline bitfld.long 0x00 3. "NP,No pending maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List register entry not present" "Not present,Present" bitfld.long 0x00 1. "U,Underflow assertion" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End of interrupt assertion" "Not asserted,Asserted" rgroup.long c15:0x43BC++0x00 line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS[3],EOI maintenance interrupt status bit for List (ICH_LR3) register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS[2],EOI maintenance interrupt status bit for List (ICH_LR2) register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS[1],EOI maintenance interrupt status bit for List (ICH_LR1) register 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "STATUS[0],EOI maintenance interrupt status bit for List (ICH_LR0) register 0" "No interrupt,Interrupt" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register" bitfld.long 0x00 27.--31. "VPMR,Virtual priority mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 21.--23. "VBPR0,Virtual binary point register for group 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. "VBPR1,Virtual binary point register for group 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9. "VEOIM,Virtual EOI mode" "Drop & interrupt,Drop" newline bitfld.long 0x00 4. "VCBPR,Virtual common binary point register" "Separate,Both" bitfld.long 0x00 1. "VENG1,Virtual group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual group 0 interrupt enable" "Disabled,Enabled" rgroup.long c15:0x45BC++0x00 line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register" bitfld.long 0x00 3. "STATUS[3],Status bit for list (ICH_LR3) register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS[2],Status bit for list (ICH_LR2) register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS[1],Status bit for list (ICH_LR1) register 1" "Interrupt,No interrupt" bitfld.long 0x00 0. "STATUS[0],Status bit for list (ICH_LR0) register 0" "Interrupt,No interrupt" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0" hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1" hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2" hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3" hexmask.long.word 0x00 0.--15. 1. "VINTID,Virtual INTID of the interrupt" if (((per.l(c15:0x40EC+0x0))&0x20000000)==0x00) group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register 0" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI" else group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,Interrupt Controller List Register 0" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" endif if (((per.l(c15:0x40EC+0x100))&0x20000000)==0x00) group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register 1" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI" else group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,Interrupt Controller List Register 1" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" endif if (((per.l(c15:0x40EC+0x200))&0x20000000)==0x00) group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register 2" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI" else group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,Interrupt Controller List Register 2" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" endif if (((per.l(c15:0x40EC+0x300))&0x20000000)==0x00) group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register 3" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. "EOI,End of interrupt" "Not EOI,EOI" else group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,Interrupt Controller List Register 3" bitfld.long 0x00 30.--31. "STATE,Interrupt state" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.long 0x00 28. "GROUP,Group for this virtual interrupt" "Group 0,Group 1" newline bitfld.long 0x00 19.--23. "PRIORITY,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" endif tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" rgroup.long c14:0x0000++0x00 line.long 0x00 "DBGDIDR,Debug ID Register" bitfld.long 0x00 28.--31. "WRP,Number of watchpoint register pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8,?..." bitfld.long 0x00 24.--27. "BRP,Number of breakpoint register pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8,?..." newline bitfld.long 0x00 20.--23. "CTX_CMP,Number of BRPs with context ID comparison capability" "Reserved,2,?..." bitfld.long 0x00 16.--19. "VERSION,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8,?..." newline bitfld.long 0x00 14. "NSUHD_IMP,Secure user halting debug-mode" "Not supported,?..." bitfld.long 0x00 12. "SE_IMP,Security extensions implemented" "Not implemented,?..." rgroup.long c14:0x0060++0x00 line.long 0x00 "DBGWFAR,Debug Watchpoint Fault Address Register" group.long c14:0x0070++0x00 line.long 0x00 "DBGVCR,Debug Vector Catch Register" bitfld.long 0x00 7. "FIQVCE,FIQ vector catch enable" "Disabled,Enabled" bitfld.long 0x00 6. "IRQVCE,IRQ vector catch enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "DAVCE,Data abort vector catch enable" "Disabled,Enabled" bitfld.long 0x00 3. "PAVCE,Prefetch abort vector catch enable" "Disabled,Enabled" newline bitfld.long 0x00 2. "SVCVCE,Supervisor call (SVC) vector catch enable" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE,Undefined instruction vector catch enable" "Disabled,Enabled" group.long c14:0x0200++0x00 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" rgroup.long c14:0x0050++0x00 line.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,Debug Comms Channel Interrupt Enable Register" bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" rgroup.long c14:0x0010++0x00 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full" newline bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to communications channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software breakpoint (BKPT),Reserved,Vector catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..." if (((per.l(c14:0x0411))&0x02)==0x02) group.long c14:0x0220++0x00 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full" newline bitfld.long 0x00 27. "RXO,DBGDTRRX overflow" "No overflow,Overflow" bitfld.long 0x00 26. "TXU,DBGDTRTX underflow" "No underflow,Underflow" newline bitfld.long 0x00 22.--23. "INTDIS,Interrupt disable" "Don't disable interrupts,Disable interrupts targeting non-sec EL1,Disable interrupts targeting EL1 & EL2,Disable all interrupts" bitfld.long 0x00 21. "TDA,Trap debug register access" "Not trapped,Trapped" newline rbitfld.long 0x00 18. "NS,Non-secure status bit" "Reserved,Non-secure" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 14. "HDE,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to communications channel disable" "No,Yes" newline bitfld.long 0x00 6. "ERR,Cummulative error flag" "Not error,Error" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software breakpoint (BKPT),Reserved,Vector catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..." else group.long c14:0x0220++0x00 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" rbitfld.long 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full" rbitfld.long 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full" newline rbitfld.long 0x00 27. "RXO,DBGDTRRX overflow" "No overflow,Overflow" rbitfld.long 0x00 26. "TXU,DBGDTRTX underflow" "No underflow,Underflow" newline rbitfld.long 0x00 22.--23. "INTDIS,Interrupt disable" "Don't disable interrupts,Disable interrupts targeting non-sec EL1,Disable interrupts targeting EL1 & EL2,Disable all interrupts" rbitfld.long 0x00 21. "TDA,Trap debug register access" "Not trapped,Trapped" newline rbitfld.long 0x00 18. "NS,Non-secure status bit" "Reserved,Non-secure" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline rbitfld.long 0x00 14. "HDE,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to communications channel disable" "No,Yes" newline rbitfld.long 0x00 6. "ERR,Cummulative error flag" "Not error,Error" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software breakpoint (BKPT),Reserved,Vector catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..." endif group.long c14:0x0230++0x00 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" if (((per.l(c14:0x0411))&0x02)==0x02) group.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else rgroup.long c14:0x0260++0x00 line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif wgroup.long c14:0x0050++0x00 line.long 0x00 "DBGDTRTXINT,Debug Transmit Register (Internal View)" rgroup.long c14:0x0707++0x00 line.long 0x00 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x00 line.long 0x00 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. "PCSROFFSET,PC samples returned offset" "Reserved,Reserved,No offset,?..." rgroup.long c14:0x0727++0x00 line.long 0x00 "DBGDEVID0,Debug Device ID Register 0" bitfld.long 0x00 28.--31. "CIDMASK,Level of support for the context ID matching breakpoint masking capability." "Not implemented,?..." bitfld.long 0x00 24.--27. "AR,Debug external auxiliary control register support status" "Not supported,?..." newline bitfld.long 0x00 20.--23. "DL,Support for debug OS double lock register" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "VE,Specifies implementation of virtualization extension" "Reserved,Implemented,?..." newline bitfld.long 0x00 12.--15. "VC,Form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x00 8.--11. "BPAM,Level of support for immediate virtual address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.long 0x00 4.--7. "WPAM,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." bitfld.long 0x00 0.--3. "PCS,Level of support for program counter sampling using debug registers 40 and 43" "Reserved,Reserved,Reserved,Implemented,?..." newline tree.end rgroup.long c14:0x0001++0x00 line.long 0x00 "DBGDRAR,Debug ROM Address Register" hexmask.long 0x00 12.--31. 0x1000 "ROMADDR,ROM physical address" newline bitfld.long 0x00 0. "VALID,ROM table address valid" "Not valid,Valid" rgroup.long c14:0x0002++0x00 line.long 0x00 "DBGDSAR,Debug Self Address Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-bit access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" newline bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,OS Double-lock Register" bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Powered down,Emulated" group.long c14:0x0687++0x00 line.long 0x00 "DBGCLAIMSET,Debug Claim Tag Set Register" bitfld.long 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set" newline bitfld.long 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.long 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.long 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x00 line.long 0x00 "DBGCLAIMCLR,Debug Claim Tag Clear Register" bitfld.long 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" newline bitfld.long 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.long 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.long 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 10.--11. "HNID,Hyp non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x00 8.--9. "HID,Hyp invasive debug" "Reserved,Reserved,Disabled,Enabled" newline bitfld.long 0x00 6.--7. "SNID,Secure non-invasive debug" "Not implemented,?..." bitfld.long 0x00 4.--5. "SID,Secure invasive debug" "Not implemented,?..." newline bitfld.long 0x00 2.--3. "NSNID,Non-secure non-invasive debug" "Reserved,Reserved,Disabled,Enabled" bitfld.long 0x00 0.--1. "NSID,Non-secure invasive debug" "Reserved,Reserved,Disabled,Enabled" rgroup.long c14:0x7000++0x00 "Jazelle Registers" line.long 0x00 "JIDR,Jazelle ID Register" rgroup.long c14:0x7001++0x00 line.long 0x00 "JOSCR,Jazelle OS Control Register" rgroup.long c14:0x7002++0x00 line.long 0x00 "JMCR,Jazelle Main Configuration Register" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if (((per.l(c14:0x0500+0x0))&0xA00000)==0x0) group.long c14:(0x0400+0x0)++0x00 line.long 0x00 "DBGBVR0,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x0))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x0)++0x00 line.long 0x00 "DBGBVR0,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x0)++0x00 line.long 0x00 "DBGBVR0,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x0)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x0)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x0)&0xC000)==0x8000) group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 1" if (((per.l(c14:0x0500+0x10))&0xA00000)==0x0) group.long c14:(0x0400+0x10)++0x00 line.long 0x00 "DBGBVR1,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x10))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x10)++0x00 line.long 0x00 "DBGBVR1,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x10)++0x00 line.long 0x00 "DBGBVR1,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x10)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x10)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x10)&0xC000)==0x8000) group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 2" if (((per.l(c14:0x0500+0x20))&0xA00000)==0x0) group.long c14:(0x0400+0x20)++0x00 line.long 0x00 "DBGBVR2,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x20))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x20)++0x00 line.long 0x00 "DBGBVR2,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x20)++0x00 line.long 0x00 "DBGBVR2,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x20)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x20)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x20)&0xC000)==0x8000) group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 3" if (((per.l(c14:0x0500+0x30))&0xA00000)==0x0) group.long c14:(0x0400+0x30)++0x00 line.long 0x00 "DBGBVR3,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x30))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x30)++0x00 line.long 0x00 "DBGBVR3,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x30)++0x00 line.long 0x00 "DBGBVR3,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x30)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x30)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x30)&0xC000)==0x8000) group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 4" if (((per.l(c14:0x0500+0x40))&0xA00000)==0x0) group.long c14:(0x0400+0x40)++0x00 line.long 0x00 "DBGBVR4,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x40))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x40)++0x00 line.long 0x00 "DBGBVR4,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x40)++0x00 line.long 0x00 "DBGBVR4,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x40)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x40)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x40)&0xC000)==0x8000) group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 5" if (((per.l(c14:0x0500+0x50))&0xA00000)==0x0) group.long c14:(0x0400+0x50)++0x00 line.long 0x00 "DBGBVR5,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x50))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x50)++0x00 line.long 0x00 "DBGBVR5,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x50)++0x00 line.long 0x00 "DBGBVR5,Debug Breakpoint Value Register" endif if ((per.l(c14:0x0500+0x50)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x50)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x50)&0xC000)==0x8000) group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 6" if (((per.l(c14:0x0500+0x60))&0xA00000)==0x0) group.long c14:(0x0400+0x60)++0x00 line.long 0x00 "DBGBVR6,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x60))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x60)++0x00 line.long 0x00 "DBGBVR6,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x60)++0x00 line.long 0x00 "DBGBVR6,Debug Breakpoint Value Register" endif group.long c14:(0x0101+0x60)++0x00 line.long 0x00 "DBGBXVR6,Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. "VMID,VMID value for comparison" if ((per.l(c14:0x0500+0x60)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x60)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x60)++0x00 line.long 0x00 "DBGBCR6,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x60)&0xC000)==0x8000) group.long c14:(0x0500+0x60)++0x00 line.long 0x00 "DBGBCR6,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x60)++0x00 line.long 0x00 "DBGBCR6,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x60)++0x00 line.long 0x00 "DBGBCR6,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree "Breakpoint 7" if (((per.l(c14:0x0500+0x70))&0xA00000)==0x0) group.long c14:(0x0400+0x70)++0x00 line.long 0x00 "DBGBVR7,Debug Breakpoint Value Register" hexmask.long 0x0 2.--31. 0x4 "VA,Address Value for comparison bits (31:2)" elif (((per.l(c14:0x0500+0x70))&0xA00000)==(0xA00000||0x200000)) group.long c14:(0x0400+0x70)++0x00 line.long 0x00 "DBGBVR7,Debug Breakpoint Value Register" else rgroup.long c14:(0x0400+0x70)++0x00 line.long 0x00 "DBGBVR7,Debug Breakpoint Value Register" endif group.long c14:(0x0101+0x70)++0x00 line.long 0x00 "DBGBXVR7,Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. "VMID,VMID value for comparison" if ((per.l(c14:0x0500+0x70)&0x2000)==0x2000) if ((per.l(c14:0x0500+0x70)&0xC000)==(0x0000||0x4000)) group.long c14:(0x0500+0x70)++0x00 line.long 0x00 "DBGBCR7,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif ((per.l(c14:0x0500+0x70)&0xC000)==0x8000) group.long c14:(0x0500+0x70)++0x00 line.long 0x00 "DBGBCR7,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,Reserved,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.long c14:(0x0500+0x70)++0x00 line.long 0x00 "DBGBCR7,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,?..." newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else group.long c14:(0x0500+0x70)++0x00 line.long 0x00 "DBGBCR7,Breakpoint Control Register" bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch" bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID" newline bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" newline bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif tree.end tree.end tree "Watchpoint Registers" tree "Watchpoint 0" group.long c14:(0x0600+0x0)++0x00 line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x0)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x0))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x0)&0xC000)==0x8000) group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 1" group.long c14:(0x0600+0x10)++0x00 line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x10)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x10))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x10)&0xC000)==0x8000) group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 2" group.long c14:(0x0600+0x20)++0x00 line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x20)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x20))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x20)&0xC000)==0x8000) group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 3" group.long c14:(0x0600+0x30)++0x00 line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x30)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x30))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x30)&0xC000)==0x8000) group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 4" group.long c14:(0x0600+0x40)++0x00 line.long 0x00 "DBGWVR4,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x40)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x40))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x40)++0x00 line.long 0x00 "DBGWCR4,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x40)&0xC000)==0x8000) group.long c14:(0x0700+0x40)++0x00 line.long 0x00 "DBGWCR4,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x40)++0x00 line.long 0x00 "DBGWCR4,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x40)++0x00 line.long 0x00 "DBGWCR4,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 5" group.long c14:(0x0600+0x50)++0x00 line.long 0x00 "DBGWVR5,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x50)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x50))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x50)++0x00 line.long 0x00 "DBGWCR5,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x50)&0xC000)==0x8000) group.long c14:(0x0700+0x50)++0x00 line.long 0x00 "DBGWCR5,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x50)++0x00 line.long 0x00 "DBGWCR5,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x50)++0x00 line.long 0x00 "DBGWCR5,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 6" group.long c14:(0x0600+0x60)++0x00 line.long 0x00 "DBGWVR6,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x60)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x60))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x60)++0x00 line.long 0x00 "DBGWCR6,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x60)&0xC000)==0x8000) group.long c14:(0x0700+0x60)++0x00 line.long 0x00 "DBGWCR6,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x60)++0x00 line.long 0x00 "DBGWCR6,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x60)++0x00 line.long 0x00 "DBGWCR6,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree "Watchpoint 7" group.long c14:(0x0600+0x70)++0x00 line.long 0x00 "DBGWVR7,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "VA,Address value" if ((per.l(c14:0x0700+0x70)&0x2000)==0x2000) if ((per.l(c14:(0x0700+0x70))&0xC000)==(0x0000||0x4000)) group.long c14:(0x0700+0x70)++0x00 line.long 0x00 "DBGWCR7,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" elif ((per.l(c14:0x0700+0x70)&0xC000)==0x8000) group.long c14:(0x0700+0x70)++0x00 line.long 0x00 "DBGWCR7,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" else group.long c14:(0x0700+0x70)++0x00 line.long 0x00 "DBGWCR7,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,?..." bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif else group.long c14:(0x0700+0x70)++0x00 line.long 0x00 "DBGWCR7,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 0x02 "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/Store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" endif tree.end tree.end AUTOINDENT.OFF AUTOINDENT.POP AUTOINDENT.PUSH AUTOINDENT.OFF tree.open "Interrupt Controller (GIC-500)" sif COMP.AVAILABLE("GICD") base COMP.BASE("GICD",-1.) tree "Distributor Interface" width 11. group.long 0x0000++0x03 "Interrupt Controller Distributor" line.long 0x00 "GICD_CTLR,Distributor Control Register" rbitfld.long 0x00 31. " RWP ,Register Write Pending" "Not pending,Pending" rbitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" rbitfld.long 0x00 6. " DS ,Disable Security" "Reserved,Yes" textline " " bitfld.long 0x00 4. " ARE ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 1. " ENABLEGRP1 ,Group 1 interrupts Enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Group 1 interrupts Enable" "Disabled,Enabled" rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 25. " NO1N ,GIC Distributor supports 1 of N SPIs" "Reserved,Not supported" bitfld.long 0x00 24. " A3V ,GIC Distributor supports non zero values of Affinity level 3" "Supported,?..." bitfld.long 0x00 19.--23. " IDBITS ,Number of INTID bits that the GIC Distributor supports" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,10 bits,?..." textline " " bitfld.long 0x00 18. " DVIS ,GIC Distributor supports Direct Virtual LPI injection" "Not supported,?..." bitfld.long 0x00 17. " LPIS ,GIC Distributor supports Locality-specific Peripheral Interrupts" "Not supported,?..." bitfld.long 0x00 16. " MBIS ,GIC Distributor supports Message-Based Interrupts Supported" "Not supported,?..." textline " " bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,?..." bitfld.long 0x00 5.--7. " CPUNUMBER ,Number of cores that can be used as interrupt targets when GICD_CTLR.ARE is 0" "Not supported,?..." bitfld.long 0x00 0.--4. " ITLINESNUMBER ,Number of SPI INTIDs that the GIC Distributor supports" "Reserved,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved" rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" hexmask.long.byte 0x00 24.--31. 1. " PRODUCTID ,Product ID" bitfld.long 0x00 16.--19. " VARIANT ,Major revision number" "Reserved,r1p3,?..." textline " " bitfld.long 0x00 12.--15. " REVISION ,Minor revision number" "Reserved,Reserved,Reserved,r1p3,?..." hexmask.long.word 0x00 0.--11. 1. " IMPLEMENTER ,Implementer" width 17. tree "Group Registers" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else rgroup.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else rgroup.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else rgroup.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else rgroup.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else rgroup.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else rgroup.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else rgroup.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else rgroup.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else rgroup.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else rgroup.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else rgroup.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else rgroup.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else rgroup.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else rgroup.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else rgroup.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else rgroup.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else rgroup.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else rgroup.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else rgroup.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else rgroup.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else rgroup.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else rgroup.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else rgroup.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else rgroup.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else rgroup.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else rgroup.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else rgroup.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else rgroup.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else rgroup.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else rgroup.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" endif tree.end width 22. tree "Set/Clear Enable Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else rgroup.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else rgroup.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else rgroup.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else rgroup.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else rgroup.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else rgroup.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else rgroup.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else rgroup.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else rgroup.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else rgroup.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else rgroup.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else rgroup.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else rgroup.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else rgroup.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else rgroup.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else rgroup.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else rgroup.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else rgroup.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else rgroup.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else rgroup.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else rgroup.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else rgroup.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else rgroup.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else rgroup.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else rgroup.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else rgroup.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else rgroup.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else rgroup.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else rgroup.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else rgroup.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" endif tree.end width 22. tree "Set/Clear Pending Registers" rgroup.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else rgroup.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else rgroup.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else rgroup.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else rgroup.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else rgroup.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else rgroup.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else rgroup.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else rgroup.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else rgroup.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else rgroup.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else rgroup.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else rgroup.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else rgroup.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else rgroup.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else rgroup.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else rgroup.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else rgroup.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else rgroup.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else rgroup.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else rgroup.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else rgroup.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else rgroup.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else rgroup.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else rgroup.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else rgroup.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else rgroup.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else rgroup.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else rgroup.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else rgroup.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else rgroup.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" endif tree.end width 24. tree "Set/Clear Active Registers" rgroup.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active" else rgroup.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active" else rgroup.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active" else rgroup.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active" else rgroup.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active" else rgroup.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active" else rgroup.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active" else rgroup.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active" else rgroup.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active" else rgroup.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active" else rgroup.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active" else rgroup.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active" else rgroup.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active" else rgroup.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active" else rgroup.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active" else rgroup.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" endif tree.end width 20. tree "Priority Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 27.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 19.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 11.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 3.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 27.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 19.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 11.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 3.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 27.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 19.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 11.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 3.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 27.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 19.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 11.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 3.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 27.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 19.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 11.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 3.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 27.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 19.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 11.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 3.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 27.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 19.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 11.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 3.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 27.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 19.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 11.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 3.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else rgroup.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" rgroup.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" rgroup.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" rgroup.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" rgroup.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" rgroup.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" rgroup.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" rgroup.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 27.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 19.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 11.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 3.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 27.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 19.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 11.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 3.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 27.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 19.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 11.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 3.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 27.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 19.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 11.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 3.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 27.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 19.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 11.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 3.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 27.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 19.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 11.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 3.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 27.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 19.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 11.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 3.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 27.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 19.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 11.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 3.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else rgroup.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" rgroup.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" rgroup.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" rgroup.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" rgroup.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" rgroup.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" rgroup.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" rgroup.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 27.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 19.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 11.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 3.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 27.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 19.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 11.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 3.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 27.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 19.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 11.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 3.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 27.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 19.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 11.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 3.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 27.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 19.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 11.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 3.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 27.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 19.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 11.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 3.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 27.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 19.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 11.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 3.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 27.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 19.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 11.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 3.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else rgroup.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" rgroup.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" rgroup.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" rgroup.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" rgroup.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" rgroup.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" rgroup.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" rgroup.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 27.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 19.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 11.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 3.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 27.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 19.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 11.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 3.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 27.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 19.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 11.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 3.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 27.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 19.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 11.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 3.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 27.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 19.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 11.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 3.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 27.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 19.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 11.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 3.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 27.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 19.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 11.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 3.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 27.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 19.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 11.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 3.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else rgroup.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" rgroup.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" rgroup.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" rgroup.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" rgroup.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" rgroup.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" rgroup.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" rgroup.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 27.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 19.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 11.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 3.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 27.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 19.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 11.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 3.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 27.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 19.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 11.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 3.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 27.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 19.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 11.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 3.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 27.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 19.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 11.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 3.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 27.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 19.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 11.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 3.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 27.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 19.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 11.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 3.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 27.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 19.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 11.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 3.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else rgroup.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" rgroup.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" rgroup.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" rgroup.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" rgroup.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" rgroup.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" rgroup.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" rgroup.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 27.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 19.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 11.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 3.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 27.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 19.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 11.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 3.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 27.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 19.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 11.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 3.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 27.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 19.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 11.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 3.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 27.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 19.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 11.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 3.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 27.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 19.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 11.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 3.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 27.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 19.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 11.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 3.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 27.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 19.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 11.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 3.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else rgroup.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" rgroup.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" rgroup.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" rgroup.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" rgroup.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" rgroup.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" rgroup.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" rgroup.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 27.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 19.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 11.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 3.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 27.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 19.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 11.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 3.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 27.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 19.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 11.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 3.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 27.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 19.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 11.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 3.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 27.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 19.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 11.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 3.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 27.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 19.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 11.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 3.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 27.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 19.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 11.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 3.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 27.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 19.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 11.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 3.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else rgroup.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" rgroup.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" rgroup.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" rgroup.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" rgroup.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" rgroup.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" rgroup.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" rgroup.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 27.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 19.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 11.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 3.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 27.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 19.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 11.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 3.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 27.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 19.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 11.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 3.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 27.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 19.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 11.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 3.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 27.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 19.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 11.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 3.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 27.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 19.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 11.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 3.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 27.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 19.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 11.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 3.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 27.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 19.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 11.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 3.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else rgroup.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" rgroup.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" rgroup.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" rgroup.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" rgroup.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" rgroup.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" rgroup.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" rgroup.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 27.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 19.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 11.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 3.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 27.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 19.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 11.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 3.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 27.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 19.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 11.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 3.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 27.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 19.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 11.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 3.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 27.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 19.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 11.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 3.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 27.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 19.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 11.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 3.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 27.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 19.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 11.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 3.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 27.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 19.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 11.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 3.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else rgroup.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" rgroup.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" rgroup.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" rgroup.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" rgroup.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" rgroup.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" rgroup.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" rgroup.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 27.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 19.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 11.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 3.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 27.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 19.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 11.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 3.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 27.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 19.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 11.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 3.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 27.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 19.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 11.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 3.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 27.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 19.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 11.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 3.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 27.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 19.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 11.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 3.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 27.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 19.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 11.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 3.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 27.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 19.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 11.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 3.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else rgroup.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" rgroup.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" rgroup.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" rgroup.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" rgroup.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" rgroup.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" rgroup.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" rgroup.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 27.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 19.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 11.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 3.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 27.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 19.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 11.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 3.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 27.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 19.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 11.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 3.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 27.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 19.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 11.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 3.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 27.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 19.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 11.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 3.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 27.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 19.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 11.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 3.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 27.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 19.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 11.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 3.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 27.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 19.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 11.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 3.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else rgroup.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" rgroup.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" rgroup.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" rgroup.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" rgroup.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" rgroup.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" rgroup.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" rgroup.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 27.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 19.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 11.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 3.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 27.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 19.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 11.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 3.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 27.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 19.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 11.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 3.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 27.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 19.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 11.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 3.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 27.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 19.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 11.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 3.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 27.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 19.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 11.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 3.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 27.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 19.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 11.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 3.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 27.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 19.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 11.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 3.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else rgroup.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" rgroup.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" rgroup.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" rgroup.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" rgroup.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" rgroup.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" rgroup.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" rgroup.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 27.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 19.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 11.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 3.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 27.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 19.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 11.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 3.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 27.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 19.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 11.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 3.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 27.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 19.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 11.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 3.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 27.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 19.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 11.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 3.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 27.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 19.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 11.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 3.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 27.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 19.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 11.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 3.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 27.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 19.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 11.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 3.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else rgroup.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" rgroup.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" rgroup.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" rgroup.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" rgroup.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" rgroup.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" rgroup.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" rgroup.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 27.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 19.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 11.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 3.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 27.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 19.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 11.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 3.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 27.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 19.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 11.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 3.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 27.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 19.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 11.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 3.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 27.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 19.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 11.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 3.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 27.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 19.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 11.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 3.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 27.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 19.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 11.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 3.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 27.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 19.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 11.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 3.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else rgroup.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" rgroup.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" rgroup.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" rgroup.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" rgroup.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" rgroup.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" rgroup.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" rgroup.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 27.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 19.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 11.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 3.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 27.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 19.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 11.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 3.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 27.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 19.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 11.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 3.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 27.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 19.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 11.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 3.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 27.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 19.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 11.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 3.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 27.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 19.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 11.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 3.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 27.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 19.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 11.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 3.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 27.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 19.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 11.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 3.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else rgroup.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" rgroup.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" rgroup.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" rgroup.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" rgroup.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" rgroup.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" rgroup.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" rgroup.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 27.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 19.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 11.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 3.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 27.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 19.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 11.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 3.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 27.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 19.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 11.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 3.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 27.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 19.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 11.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 3.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 27.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 19.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 11.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 3.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 27.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 19.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 11.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 3.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 27.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 19.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 11.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 3.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 27.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 19.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 11.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 3.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else rgroup.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" rgroup.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" rgroup.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" rgroup.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" rgroup.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" rgroup.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" rgroup.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" rgroup.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 27.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 19.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 11.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 3.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 27.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 19.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 11.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 3.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 27.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 19.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 11.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 3.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 27.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 19.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 11.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 3.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 27.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 19.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 11.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 3.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 27.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 19.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 11.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 3.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 27.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 19.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 11.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 3.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 27.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 19.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 11.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 3.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else rgroup.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" rgroup.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" rgroup.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" rgroup.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" rgroup.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" rgroup.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" rgroup.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" rgroup.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 27.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 19.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 11.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 3.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 27.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 19.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 11.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 3.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 27.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 19.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 11.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 3.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 27.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 19.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 11.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 3.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 27.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 19.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 11.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 3.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 27.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 19.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 11.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 3.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 27.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 19.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 11.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 3.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 27.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 19.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 11.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 3.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else rgroup.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" rgroup.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" rgroup.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" rgroup.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" rgroup.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" rgroup.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" rgroup.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" rgroup.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 27.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 19.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 11.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 3.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 27.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 19.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 11.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 3.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 27.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 19.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 11.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 3.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 27.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 19.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 11.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 3.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 27.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 19.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 11.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 3.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 27.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 19.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 11.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 3.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 27.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 19.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 11.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 3.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 27.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 19.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 11.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 3.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else rgroup.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" rgroup.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" rgroup.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" rgroup.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" rgroup.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" rgroup.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" rgroup.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" rgroup.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 27.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 19.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 11.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 3.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 27.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 19.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 11.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 3.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 27.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 19.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 11.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 3.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 27.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 19.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 11.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 3.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 27.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 19.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 11.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 3.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 27.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 19.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 11.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 3.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 27.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 19.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 11.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 3.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 27.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 19.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 11.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 3.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else rgroup.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" rgroup.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" rgroup.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" rgroup.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" rgroup.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" rgroup.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" rgroup.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" rgroup.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 27.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 19.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 11.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 3.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 27.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 19.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 11.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 3.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 27.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 19.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 11.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 3.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 27.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 19.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 11.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 3.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 27.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 19.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 11.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 3.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 27.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 19.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 11.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 3.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 27.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 19.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 11.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 3.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 27.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 19.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 11.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 3.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else rgroup.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" rgroup.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" rgroup.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" rgroup.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" rgroup.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" rgroup.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" rgroup.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" rgroup.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 27.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 19.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 11.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 3.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 27.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 19.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 11.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 3.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 27.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 19.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 11.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 3.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 27.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 19.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 11.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 3.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 27.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 19.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 11.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 3.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 27.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 19.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 11.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 3.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 27.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 19.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 11.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 3.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 27.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 19.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 11.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 3.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else rgroup.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" rgroup.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" rgroup.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" rgroup.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" rgroup.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" rgroup.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" rgroup.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" rgroup.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 27.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 19.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 11.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 3.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 27.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 19.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 11.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 3.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 27.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 19.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 11.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 3.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 27.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 19.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 11.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 3.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 27.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 19.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 11.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 3.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 27.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 19.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 11.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 3.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 27.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 19.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 11.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 3.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 27.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 19.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 11.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 3.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else rgroup.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" rgroup.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" rgroup.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" rgroup.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" rgroup.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" rgroup.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" rgroup.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" rgroup.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 27.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 19.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 11.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 3.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 27.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 19.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 11.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 3.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 27.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 19.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 11.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 3.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 27.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 19.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 11.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 3.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 27.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 19.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 11.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 3.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 27.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 19.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 11.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 3.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 27.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 19.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 11.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 3.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 27.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 19.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 11.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 3.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else rgroup.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" rgroup.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" rgroup.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" rgroup.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" rgroup.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" rgroup.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" rgroup.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" rgroup.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 27.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 19.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 11.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 3.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 27.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 19.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 11.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 3.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 27.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 19.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 11.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 3.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 27.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 19.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 11.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 3.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 27.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 19.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 11.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 3.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 27.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 19.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 11.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 3.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 27.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 19.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 11.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 3.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 27.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 19.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 11.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 3.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else rgroup.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" rgroup.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" rgroup.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" rgroup.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" rgroup.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" rgroup.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" rgroup.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" rgroup.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 27.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 19.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 11.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 3.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 27.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 19.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 11.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 3.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 27.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 19.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 11.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 3.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 27.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 19.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 11.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 3.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 27.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 19.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 11.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 3.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 27.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 19.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 11.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 3.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 27.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 19.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 11.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 3.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 27.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 19.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 11.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 3.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else rgroup.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" rgroup.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" rgroup.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" rgroup.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" rgroup.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" rgroup.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" rgroup.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" rgroup.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 27.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 19.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 11.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 3.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 27.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 19.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 11.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 3.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 27.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 19.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 11.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 3.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 27.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 19.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 11.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 3.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 27.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 19.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 11.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 3.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 27.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 19.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 11.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 3.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 27.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 19.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 11.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 3.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 27.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 19.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 11.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 3.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else rgroup.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" rgroup.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" rgroup.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" rgroup.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" rgroup.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" rgroup.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" rgroup.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" rgroup.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 27.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 19.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 11.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 3.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 27.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 19.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 11.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 3.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 27.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 19.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 11.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 3.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 27.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 19.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 11.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 3.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 27.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 19.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 11.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 3.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 27.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 19.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 11.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 3.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 27.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 19.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 11.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 3.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 27.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 19.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 11.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 3.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else rgroup.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" rgroup.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" rgroup.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" rgroup.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" rgroup.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" rgroup.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" rgroup.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" rgroup.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 27.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 19.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 11.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 3.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 27.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 19.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 11.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 3.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 27.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 19.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 11.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 3.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 27.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 19.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 11.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 3.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 27.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 19.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 11.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 3.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 27.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 19.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 11.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 3.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 27.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 19.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 11.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 3.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 27.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 19.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 11.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 3.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else rgroup.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" rgroup.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" rgroup.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" rgroup.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" rgroup.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" rgroup.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" rgroup.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" rgroup.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 27.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 19.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 11.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 3.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 27.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 19.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 11.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 3.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 27.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 19.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 11.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 3.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 27.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 19.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 11.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 3.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 27.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 19.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 11.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 3.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 27.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 19.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 11.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 3.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 27.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 19.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 11.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 3.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 27.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 19.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 11.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 3.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else rgroup.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" rgroup.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" rgroup.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" rgroup.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" rgroup.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" rgroup.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" rgroup.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" rgroup.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif tree.end width 14. tree "Configuration Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" rgroup.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" rgroup.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" rgroup.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" rgroup.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" rgroup.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" rgroup.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" rgroup.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" rgroup.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" rgroup.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" rgroup.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" rgroup.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" rgroup.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" rgroup.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" rgroup.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" rgroup.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" rgroup.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" rgroup.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" rgroup.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" rgroup.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" rgroup.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" rgroup.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" rgroup.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" rgroup.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" rgroup.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" rgroup.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" rgroup.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" rgroup.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" rgroup.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" rgroup.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else rgroup.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" rgroup.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif tree.end width 24. tree "Interrupt Routing Registers" group.quad 0x6100++0x07 line.quad 0x00 "GICD_IROUTER32,Interrupt Routing Register 32" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6108++0x07 line.quad 0x00 "GICD_IROUTER33,Interrupt Routing Register 33" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6110++0x07 line.quad 0x00 "GICD_IROUTER34,Interrupt Routing Register 34" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6118++0x07 line.quad 0x00 "GICD_IROUTER35,Interrupt Routing Register 35" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6120++0x07 line.quad 0x00 "GICD_IROUTER36,Interrupt Routing Register 36" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6128++0x07 line.quad 0x00 "GICD_IROUTER37,Interrupt Routing Register 37" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6130++0x07 line.quad 0x00 "GICD_IROUTER38,Interrupt Routing Register 38" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6138++0x07 line.quad 0x00 "GICD_IROUTER39,Interrupt Routing Register 39" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6140++0x07 line.quad 0x00 "GICD_IROUTER40,Interrupt Routing Register 40" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6148++0x07 line.quad 0x00 "GICD_IROUTER41,Interrupt Routing Register 41" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6150++0x07 line.quad 0x00 "GICD_IROUTER42,Interrupt Routing Register 42" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6158++0x07 line.quad 0x00 "GICD_IROUTER43,Interrupt Routing Register 43" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6160++0x07 line.quad 0x00 "GICD_IROUTER44,Interrupt Routing Register 44" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6168++0x07 line.quad 0x00 "GICD_IROUTER45,Interrupt Routing Register 45" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6170++0x07 line.quad 0x00 "GICD_IROUTER46,Interrupt Routing Register 46" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6178++0x07 line.quad 0x00 "GICD_IROUTER47,Interrupt Routing Register 47" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6180++0x07 line.quad 0x00 "GICD_IROUTER48,Interrupt Routing Register 48" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6188++0x07 line.quad 0x00 "GICD_IROUTER49,Interrupt Routing Register 49" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6190++0x07 line.quad 0x00 "GICD_IROUTER50,Interrupt Routing Register 50" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6198++0x07 line.quad 0x00 "GICD_IROUTER51,Interrupt Routing Register 51" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A0++0x07 line.quad 0x00 "GICD_IROUTER52,Interrupt Routing Register 52" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A8++0x07 line.quad 0x00 "GICD_IROUTER53,Interrupt Routing Register 53" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B0++0x07 line.quad 0x00 "GICD_IROUTER54,Interrupt Routing Register 54" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B8++0x07 line.quad 0x00 "GICD_IROUTER55,Interrupt Routing Register 55" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C0++0x07 line.quad 0x00 "GICD_IROUTER56,Interrupt Routing Register 56" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C8++0x07 line.quad 0x00 "GICD_IROUTER57,Interrupt Routing Register 57" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D0++0x07 line.quad 0x00 "GICD_IROUTER58,Interrupt Routing Register 58" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D8++0x07 line.quad 0x00 "GICD_IROUTER59,Interrupt Routing Register 59" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E0++0x07 line.quad 0x00 "GICD_IROUTER60,Interrupt Routing Register 60" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E8++0x07 line.quad 0x00 "GICD_IROUTER61,Interrupt Routing Register 61" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F0++0x07 line.quad 0x00 "GICD_IROUTER62,Interrupt Routing Register 62" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F8++0x07 line.quad 0x00 "GICD_IROUTER63,Interrupt Routing Register 63" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6200++0x07 line.quad 0x00 "GICD_IROUTER64,Interrupt Routing Register 64" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6208++0x07 line.quad 0x00 "GICD_IROUTER65,Interrupt Routing Register 65" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6210++0x07 line.quad 0x00 "GICD_IROUTER66,Interrupt Routing Register 66" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6218++0x07 line.quad 0x00 "GICD_IROUTER67,Interrupt Routing Register 67" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6220++0x07 line.quad 0x00 "GICD_IROUTER68,Interrupt Routing Register 68" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6228++0x07 line.quad 0x00 "GICD_IROUTER69,Interrupt Routing Register 69" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6230++0x07 line.quad 0x00 "GICD_IROUTER70,Interrupt Routing Register 70" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6238++0x07 line.quad 0x00 "GICD_IROUTER71,Interrupt Routing Register 71" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6240++0x07 line.quad 0x00 "GICD_IROUTER72,Interrupt Routing Register 72" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6248++0x07 line.quad 0x00 "GICD_IROUTER73,Interrupt Routing Register 73" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6250++0x07 line.quad 0x00 "GICD_IROUTER74,Interrupt Routing Register 74" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6258++0x07 line.quad 0x00 "GICD_IROUTER75,Interrupt Routing Register 75" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6260++0x07 line.quad 0x00 "GICD_IROUTER76,Interrupt Routing Register 76" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6268++0x07 line.quad 0x00 "GICD_IROUTER77,Interrupt Routing Register 77" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6270++0x07 line.quad 0x00 "GICD_IROUTER78,Interrupt Routing Register 78" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6278++0x07 line.quad 0x00 "GICD_IROUTER79,Interrupt Routing Register 79" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6280++0x07 line.quad 0x00 "GICD_IROUTER80,Interrupt Routing Register 80" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6288++0x07 line.quad 0x00 "GICD_IROUTER81,Interrupt Routing Register 81" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6290++0x07 line.quad 0x00 "GICD_IROUTER82,Interrupt Routing Register 82" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6298++0x07 line.quad 0x00 "GICD_IROUTER83,Interrupt Routing Register 83" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A0++0x07 line.quad 0x00 "GICD_IROUTER84,Interrupt Routing Register 84" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A8++0x07 line.quad 0x00 "GICD_IROUTER85,Interrupt Routing Register 85" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B0++0x07 line.quad 0x00 "GICD_IROUTER86,Interrupt Routing Register 86" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B8++0x07 line.quad 0x00 "GICD_IROUTER87,Interrupt Routing Register 87" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C0++0x07 line.quad 0x00 "GICD_IROUTER88,Interrupt Routing Register 88" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C8++0x07 line.quad 0x00 "GICD_IROUTER89,Interrupt Routing Register 89" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D0++0x07 line.quad 0x00 "GICD_IROUTER90,Interrupt Routing Register 90" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D8++0x07 line.quad 0x00 "GICD_IROUTER91,Interrupt Routing Register 91" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E0++0x07 line.quad 0x00 "GICD_IROUTER92,Interrupt Routing Register 92" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E8++0x07 line.quad 0x00 "GICD_IROUTER93,Interrupt Routing Register 93" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F0++0x07 line.quad 0x00 "GICD_IROUTER94,Interrupt Routing Register 94" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F8++0x07 line.quad 0x00 "GICD_IROUTER95,Interrupt Routing Register 95" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6300++0x07 line.quad 0x00 "GICD_IROUTER96,Interrupt Routing Register 96" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6308++0x07 line.quad 0x00 "GICD_IROUTER97,Interrupt Routing Register 97" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6310++0x07 line.quad 0x00 "GICD_IROUTER98,Interrupt Routing Register 98" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6318++0x07 line.quad 0x00 "GICD_IROUTER99,Interrupt Routing Register 99" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6320++0x07 line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6328++0x07 line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6330++0x07 line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6338++0x07 line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6340++0x07 line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6348++0x07 line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6350++0x07 line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6358++0x07 line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6360++0x07 line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6368++0x07 line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6370++0x07 line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6378++0x07 line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6380++0x07 line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6388++0x07 line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6390++0x07 line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6398++0x07 line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A0++0x07 line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A8++0x07 line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B0++0x07 line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B8++0x07 line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C0++0x07 line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C8++0x07 line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D0++0x07 line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D8++0x07 line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E0++0x07 line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E8++0x07 line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F0++0x07 line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F8++0x07 line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6400++0x07 line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6408++0x07 line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6410++0x07 line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6418++0x07 line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6420++0x07 line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6428++0x07 line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6430++0x07 line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6438++0x07 line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6440++0x07 line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6448++0x07 line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6450++0x07 line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6458++0x07 line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6460++0x07 line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6468++0x07 line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6470++0x07 line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6478++0x07 line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6480++0x07 line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6488++0x07 line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6490++0x07 line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6498++0x07 line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A0++0x07 line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A8++0x07 line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B0++0x07 line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B8++0x07 line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C0++0x07 line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C8++0x07 line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D0++0x07 line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D8++0x07 line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E0++0x07 line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E8++0x07 line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F0++0x07 line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F8++0x07 line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6500++0x07 line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6508++0x07 line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6510++0x07 line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6518++0x07 line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6520++0x07 line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6528++0x07 line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6530++0x07 line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6538++0x07 line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6540++0x07 line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6548++0x07 line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6550++0x07 line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6558++0x07 line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6560++0x07 line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6568++0x07 line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6570++0x07 line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6578++0x07 line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6580++0x07 line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6588++0x07 line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6590++0x07 line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6598++0x07 line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A0++0x07 line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A8++0x07 line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B0++0x07 line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B8++0x07 line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C0++0x07 line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C8++0x07 line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D0++0x07 line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D8++0x07 line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E0++0x07 line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E8++0x07 line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F0++0x07 line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F8++0x07 line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6600++0x07 line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6608++0x07 line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6610++0x07 line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6618++0x07 line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6620++0x07 line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6628++0x07 line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6630++0x07 line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6638++0x07 line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6640++0x07 line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6648++0x07 line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6650++0x07 line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6658++0x07 line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6660++0x07 line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6668++0x07 line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6670++0x07 line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6678++0x07 line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6680++0x07 line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6688++0x07 line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6690++0x07 line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6698++0x07 line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A0++0x07 line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A8++0x07 line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B0++0x07 line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B8++0x07 line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C0++0x07 line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C8++0x07 line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D0++0x07 line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D8++0x07 line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E0++0x07 line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E8++0x07 line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F0++0x07 line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F8++0x07 line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6700++0x07 line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6708++0x07 line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6710++0x07 line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6718++0x07 line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6720++0x07 line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6728++0x07 line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6730++0x07 line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6738++0x07 line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6740++0x07 line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6748++0x07 line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6750++0x07 line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6758++0x07 line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6760++0x07 line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6768++0x07 line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6770++0x07 line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6778++0x07 line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6780++0x07 line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6788++0x07 line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6790++0x07 line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6798++0x07 line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A0++0x07 line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A8++0x07 line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B0++0x07 line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B8++0x07 line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C0++0x07 line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C8++0x07 line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D0++0x07 line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D8++0x07 line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E0++0x07 line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E8++0x07 line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F0++0x07 line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F8++0x07 line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6800++0x07 line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6808++0x07 line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6810++0x07 line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6818++0x07 line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6820++0x07 line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6828++0x07 line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6830++0x07 line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6838++0x07 line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6840++0x07 line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6848++0x07 line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6850++0x07 line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6858++0x07 line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6860++0x07 line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6868++0x07 line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6870++0x07 line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6878++0x07 line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6880++0x07 line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6888++0x07 line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6890++0x07 line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6898++0x07 line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A0++0x07 line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A8++0x07 line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B0++0x07 line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B8++0x07 line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C0++0x07 line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C8++0x07 line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D0++0x07 line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D8++0x07 line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E0++0x07 line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E8++0x07 line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F0++0x07 line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F8++0x07 line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6900++0x07 line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6908++0x07 line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6910++0x07 line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6918++0x07 line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6920++0x07 line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6928++0x07 line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6930++0x07 line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6938++0x07 line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6940++0x07 line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6948++0x07 line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6950++0x07 line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6958++0x07 line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6960++0x07 line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6968++0x07 line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6970++0x07 line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6978++0x07 line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6980++0x07 line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6988++0x07 line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6990++0x07 line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6998++0x07 line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A0++0x07 line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A8++0x07 line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B0++0x07 line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B8++0x07 line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C0++0x07 line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C8++0x07 line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D0++0x07 line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D8++0x07 line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E0++0x07 line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E8++0x07 line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F0++0x07 line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F8++0x07 line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A00++0x07 line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A08++0x07 line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A10++0x07 line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A18++0x07 line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A20++0x07 line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A28++0x07 line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A30++0x07 line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A38++0x07 line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A40++0x07 line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A48++0x07 line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A50++0x07 line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A58++0x07 line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A60++0x07 line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A68++0x07 line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A70++0x07 line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A78++0x07 line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A80++0x07 line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A88++0x07 line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A90++0x07 line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A98++0x07 line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA0++0x07 line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA8++0x07 line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB0++0x07 line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB8++0x07 line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC0++0x07 line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC8++0x07 line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD0++0x07 line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD8++0x07 line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE0++0x07 line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE8++0x07 line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF0++0x07 line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF8++0x07 line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B00++0x07 line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B08++0x07 line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B10++0x07 line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B18++0x07 line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B20++0x07 line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B28++0x07 line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B30++0x07 line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B38++0x07 line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B40++0x07 line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B48++0x07 line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B50++0x07 line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B58++0x07 line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B60++0x07 line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B68++0x07 line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B70++0x07 line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B78++0x07 line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B80++0x07 line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B88++0x07 line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B90++0x07 line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B98++0x07 line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA0++0x07 line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA8++0x07 line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB0++0x07 line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB8++0x07 line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC0++0x07 line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC8++0x07 line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD0++0x07 line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD8++0x07 line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE0++0x07 line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE8++0x07 line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF0++0x07 line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF8++0x07 line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C00++0x07 line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C08++0x07 line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C10++0x07 line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C18++0x07 line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C20++0x07 line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C28++0x07 line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C30++0x07 line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C38++0x07 line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C40++0x07 line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C48++0x07 line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C50++0x07 line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C58++0x07 line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C60++0x07 line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C68++0x07 line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C70++0x07 line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C78++0x07 line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C80++0x07 line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C88++0x07 line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C90++0x07 line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C98++0x07 line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA0++0x07 line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA8++0x07 line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB0++0x07 line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB8++0x07 line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC0++0x07 line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC8++0x07 line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD0++0x07 line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD8++0x07 line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE0++0x07 line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE8++0x07 line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF0++0x07 line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF8++0x07 line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D00++0x07 line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D08++0x07 line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D10++0x07 line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D18++0x07 line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D20++0x07 line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D28++0x07 line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D30++0x07 line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D38++0x07 line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D40++0x07 line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D48++0x07 line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D50++0x07 line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D58++0x07 line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D60++0x07 line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D68++0x07 line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D70++0x07 line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D78++0x07 line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D80++0x07 line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D88++0x07 line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D90++0x07 line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D98++0x07 line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA0++0x07 line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA8++0x07 line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB0++0x07 line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB8++0x07 line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC0++0x07 line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC8++0x07 line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD0++0x07 line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD8++0x07 line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE0++0x07 line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE8++0x07 line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF0++0x07 line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF8++0x07 line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E00++0x07 line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E08++0x07 line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E10++0x07 line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E18++0x07 line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E20++0x07 line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E28++0x07 line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E30++0x07 line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E38++0x07 line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E40++0x07 line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E48++0x07 line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E50++0x07 line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E58++0x07 line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E60++0x07 line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E68++0x07 line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E70++0x07 line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E78++0x07 line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E80++0x07 line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E88++0x07 line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E90++0x07 line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E98++0x07 line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA0++0x07 line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA8++0x07 line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB0++0x07 line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB8++0x07 line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC0++0x07 line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC8++0x07 line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED0++0x07 line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED8++0x07 line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE0++0x07 line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE8++0x07 line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF0++0x07 line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF8++0x07 line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F00++0x07 line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F08++0x07 line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F10++0x07 line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F18++0x07 line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F20++0x07 line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F28++0x07 line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F30++0x07 line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F38++0x07 line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F40++0x07 line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F48++0x07 line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F50++0x07 line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F58++0x07 line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F60++0x07 line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F68++0x07 line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F70++0x07 line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F78++0x07 line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F80++0x07 line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F88++0x07 line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F90++0x07 line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F98++0x07 line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA0++0x07 line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA8++0x07 line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB0++0x07 line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB8++0x07 line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC0++0x07 line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC8++0x07 line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD0++0x07 line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD8++0x07 line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE0++0x07 line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE8++0x07 line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF0++0x07 line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF8++0x07 line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7000++0x07 line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7008++0x07 line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7010++0x07 line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7018++0x07 line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7020++0x07 line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7028++0x07 line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7030++0x07 line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7038++0x07 line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7040++0x07 line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7048++0x07 line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7050++0x07 line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7058++0x07 line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7060++0x07 line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7068++0x07 line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7070++0x07 line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7078++0x07 line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7080++0x07 line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7088++0x07 line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7090++0x07 line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7098++0x07 line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A0++0x07 line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A8++0x07 line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B0++0x07 line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B8++0x07 line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C0++0x07 line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C8++0x07 line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D0++0x07 line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D8++0x07 line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E0++0x07 line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E8++0x07 line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F0++0x07 line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F8++0x07 line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7100++0x07 line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7108++0x07 line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7110++0x07 line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7118++0x07 line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7120++0x07 line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7128++0x07 line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7130++0x07 line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7138++0x07 line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7140++0x07 line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7148++0x07 line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7150++0x07 line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7158++0x07 line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7160++0x07 line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7168++0x07 line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7170++0x07 line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7178++0x07 line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7180++0x07 line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7188++0x07 line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7190++0x07 line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7198++0x07 line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A0++0x07 line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A8++0x07 line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B0++0x07 line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B8++0x07 line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C0++0x07 line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C8++0x07 line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D0++0x07 line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D8++0x07 line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E0++0x07 line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E8++0x07 line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F0++0x07 line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F8++0x07 line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7200++0x07 line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7208++0x07 line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7210++0x07 line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7218++0x07 line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7220++0x07 line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7228++0x07 line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7230++0x07 line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7238++0x07 line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7240++0x07 line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7248++0x07 line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7250++0x07 line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7258++0x07 line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7260++0x07 line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7268++0x07 line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7270++0x07 line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7278++0x07 line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7280++0x07 line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7288++0x07 line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7290++0x07 line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7298++0x07 line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A0++0x07 line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A8++0x07 line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B0++0x07 line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B8++0x07 line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C0++0x07 line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C8++0x07 line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D0++0x07 line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D8++0x07 line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E0++0x07 line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E8++0x07 line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F0++0x07 line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F8++0x07 line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7300++0x07 line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7308++0x07 line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7310++0x07 line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7318++0x07 line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7320++0x07 line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7328++0x07 line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7330++0x07 line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7338++0x07 line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7340++0x07 line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7348++0x07 line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7350++0x07 line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7358++0x07 line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7360++0x07 line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7368++0x07 line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7370++0x07 line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7378++0x07 line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7380++0x07 line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7388++0x07 line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7390++0x07 line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7398++0x07 line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A0++0x07 line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A8++0x07 line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B0++0x07 line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B8++0x07 line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C0++0x07 line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C8++0x07 line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D0++0x07 line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D8++0x07 line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E0++0x07 line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E8++0x07 line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F0++0x07 line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F8++0x07 line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7400++0x07 line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7408++0x07 line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7410++0x07 line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7418++0x07 line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7420++0x07 line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7428++0x07 line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7430++0x07 line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7438++0x07 line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7440++0x07 line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7448++0x07 line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7450++0x07 line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7458++0x07 line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7460++0x07 line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7468++0x07 line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7470++0x07 line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7478++0x07 line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7480++0x07 line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7488++0x07 line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7490++0x07 line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7498++0x07 line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A0++0x07 line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A8++0x07 line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B0++0x07 line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B8++0x07 line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C0++0x07 line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C8++0x07 line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D0++0x07 line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D8++0x07 line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E0++0x07 line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E8++0x07 line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F0++0x07 line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F8++0x07 line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7500++0x07 line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7508++0x07 line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7510++0x07 line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7518++0x07 line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7520++0x07 line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7528++0x07 line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7530++0x07 line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7538++0x07 line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7540++0x07 line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7548++0x07 line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7550++0x07 line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7558++0x07 line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7560++0x07 line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7568++0x07 line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7570++0x07 line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7578++0x07 line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7580++0x07 line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7588++0x07 line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7590++0x07 line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7598++0x07 line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A0++0x07 line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A8++0x07 line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B0++0x07 line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B8++0x07 line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C0++0x07 line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C8++0x07 line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D0++0x07 line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D8++0x07 line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E0++0x07 line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E8++0x07 line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F0++0x07 line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F8++0x07 line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7600++0x07 line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7608++0x07 line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7610++0x07 line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7618++0x07 line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7620++0x07 line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7628++0x07 line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7630++0x07 line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7638++0x07 line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7640++0x07 line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7648++0x07 line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7650++0x07 line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7658++0x07 line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7660++0x07 line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7668++0x07 line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7670++0x07 line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7678++0x07 line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7680++0x07 line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7688++0x07 line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7690++0x07 line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7698++0x07 line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A0++0x07 line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A8++0x07 line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B0++0x07 line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B8++0x07 line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C0++0x07 line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C8++0x07 line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D0++0x07 line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D8++0x07 line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E0++0x07 line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E8++0x07 line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F0++0x07 line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F8++0x07 line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7700++0x07 line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7708++0x07 line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7710++0x07 line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7718++0x07 line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7720++0x07 line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7728++0x07 line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7730++0x07 line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7738++0x07 line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7740++0x07 line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7748++0x07 line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7750++0x07 line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7758++0x07 line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7760++0x07 line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7768++0x07 line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7770++0x07 line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7778++0x07 line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7780++0x07 line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7788++0x07 line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7790++0x07 line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7798++0x07 line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A0++0x07 line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A8++0x07 line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B0++0x07 line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B8++0x07 line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C0++0x07 line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C8++0x07 line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D0++0x07 line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D8++0x07 line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E0++0x07 line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E8++0x07 line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F0++0x07 line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F8++0x07 line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7800++0x07 line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7808++0x07 line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7810++0x07 line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7818++0x07 line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7820++0x07 line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7828++0x07 line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7830++0x07 line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7838++0x07 line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7840++0x07 line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7848++0x07 line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7850++0x07 line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7858++0x07 line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7860++0x07 line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7868++0x07 line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7870++0x07 line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7878++0x07 line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7880++0x07 line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7888++0x07 line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7890++0x07 line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7898++0x07 line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A0++0x07 line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A8++0x07 line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B0++0x07 line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B8++0x07 line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C0++0x07 line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C8++0x07 line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D0++0x07 line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D8++0x07 line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E0++0x07 line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E8++0x07 line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F0++0x07 line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F8++0x07 line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7900++0x07 line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7908++0x07 line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7910++0x07 line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7918++0x07 line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7920++0x07 line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7928++0x07 line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7930++0x07 line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7938++0x07 line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7940++0x07 line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7948++0x07 line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7950++0x07 line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7958++0x07 line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7960++0x07 line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7968++0x07 line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7970++0x07 line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7978++0x07 line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7980++0x07 line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7988++0x07 line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7990++0x07 line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7998++0x07 line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A0++0x07 line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A8++0x07 line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B0++0x07 line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B8++0x07 line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C0++0x07 line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C8++0x07 line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D0++0x07 line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D8++0x07 line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E0++0x07 line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E8++0x07 line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F0++0x07 line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F8++0x07 line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A00++0x07 line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A08++0x07 line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A10++0x07 line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A18++0x07 line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A20++0x07 line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A28++0x07 line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A30++0x07 line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A38++0x07 line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A40++0x07 line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A48++0x07 line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A50++0x07 line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A58++0x07 line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A60++0x07 line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A68++0x07 line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A70++0x07 line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A78++0x07 line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A80++0x07 line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A88++0x07 line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A90++0x07 line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A98++0x07 line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA0++0x07 line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA8++0x07 line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB0++0x07 line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB8++0x07 line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC0++0x07 line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC8++0x07 line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD0++0x07 line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD8++0x07 line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE0++0x07 line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE8++0x07 line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF0++0x07 line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF8++0x07 line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B00++0x07 line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B08++0x07 line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B10++0x07 line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B18++0x07 line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B20++0x07 line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B28++0x07 line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B30++0x07 line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B38++0x07 line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B40++0x07 line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B48++0x07 line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B50++0x07 line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B58++0x07 line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B60++0x07 line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B68++0x07 line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B70++0x07 line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B78++0x07 line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B80++0x07 line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B88++0x07 line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B90++0x07 line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B98++0x07 line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA0++0x07 line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA8++0x07 line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB0++0x07 line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB8++0x07 line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC0++0x07 line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC8++0x07 line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD0++0x07 line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD8++0x07 line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE0++0x07 line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE8++0x07 line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF0++0x07 line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF8++0x07 line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C00++0x07 line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C08++0x07 line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C10++0x07 line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C18++0x07 line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C20++0x07 line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C28++0x07 line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C30++0x07 line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C38++0x07 line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C40++0x07 line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C48++0x07 line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C50++0x07 line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C58++0x07 line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C60++0x07 line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C68++0x07 line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C70++0x07 line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C78++0x07 line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C80++0x07 line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C88++0x07 line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C90++0x07 line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C98++0x07 line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA0++0x07 line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA8++0x07 line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB0++0x07 line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB8++0x07 line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC0++0x07 line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC8++0x07 line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD0++0x07 line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD8++0x07 line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE0++0x07 line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE8++0x07 line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF0++0x07 line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF8++0x07 line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D00++0x07 line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D08++0x07 line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D10++0x07 line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D18++0x07 line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D20++0x07 line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D28++0x07 line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D30++0x07 line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D38++0x07 line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D40++0x07 line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D48++0x07 line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D50++0x07 line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D58++0x07 line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D60++0x07 line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D68++0x07 line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D70++0x07 line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D78++0x07 line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D80++0x07 line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D88++0x07 line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D90++0x07 line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D98++0x07 line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA0++0x07 line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA8++0x07 line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB0++0x07 line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB8++0x07 line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC0++0x07 line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC8++0x07 line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD0++0x07 line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD8++0x07 line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE0++0x07 line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE8++0x07 line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF0++0x07 line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF8++0x07 line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E00++0x07 line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E08++0x07 line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E10++0x07 line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E18++0x07 line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E20++0x07 line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E28++0x07 line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E30++0x07 line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E38++0x07 line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E40++0x07 line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E48++0x07 line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E50++0x07 line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E58++0x07 line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E60++0x07 line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E68++0x07 line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E70++0x07 line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E78++0x07 line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E80++0x07 line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E88++0x07 line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E90++0x07 line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E98++0x07 line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA0++0x07 line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA8++0x07 line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB0++0x07 line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB8++0x07 line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC0++0x07 line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC8++0x07 line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED0++0x07 line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED8++0x07 line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE0++0x07 line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE8++0x07 line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF0++0x07 line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF8++0x07 line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD4++0x03 line.long 0x00 "GICD_PIDR5,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD8++0x03 line.long 0x00 "GICD_PIDR6,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFDC++0x03 line.long 0x00 "GICD_PIDR7,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" textline " " rgroup.long 0xFFF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" textline " " tree.end tree.end width 0x0B endif sif COMP.AVAILABLE("GICR") base COMP.BASE("GICR",-1.) width 15. tree "Redistributor Interface" tree "Control Registers" rgroup.long 0x00++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" bitfld.long 0x00 31. " UWP ,Upstream writes pending" "Not pending,?..." bitfld.long 0x00 3. " RWP ,Register Write Pending" "Not pending,Pending" rgroup.long 0x0004++0x03 line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register" hexmask.long.byte 0x00 24.--31. 1. " PRODUCTID ,Product ID" bitfld.long 0x00 16.--19. " VARIANT ,Major revision number" "Reserved,r1p3,?..." textline " " bitfld.long 0x00 12.--15. " REVISION ,Minor revision number" "Reserved,Reserved,Reserved,r1p3,?..." hexmask.long.word 0x00 0.--11. 1. " IMPLEMENTER ,Implementer" rgroup.quad 0x0008++0x07 line.quad 0x00 "GICR_TYPER,Redistributor Type Register" hexmask.quad.byte 0x00 32.--39. 1. " AFF0 ,Affinity level 0" hexmask.quad.word 0x00 8.--23. 1. " PROCESSOR_NUMBER ,Processor Number" textline " " bitfld.quad 0x00 5. " DPGS ,GICR_CTLR.DPG* bits support" "Not supported,?..." bitfld.quad 0x00 4. " LAST ,Last numbered Redistributor" "Not last,Last" bitfld.quad 0x00 3. " DIRECTLPI ,Direct injection of LPIs support" "Not supported,?..." textline " " bitfld.quad 0x00 1. " VLPIS ,Virtual LPIs support" "Not supported,?..." bitfld.quad 0x00 0. " PLPIS ,Physical LPI support" "Not supported,?..." group.long 0x0014++0x03 line.long 0x00 "GICR_WAKER,Redistributor Wake Register" bitfld.long 0x00 2. " CHILDRENASLEEP ,Connected target quiescent" "Not quiescent,Quiescent" bitfld.long 0x00 1. " PROCESSORSLEEP ,Target is entering the processor sleep state" "No,Yes" tree.end tree "SGI and PPI Registers" group.long 0x10080++0x03 line.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " PPIS[15] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 30. " PPIS[14] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 29. " PPIS[13] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " PPIS[12] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 27. " PPIS[11] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 26. " PPIS[10] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " PPIS[9] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 24. " PPIS[8] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 23. " PPIS[7] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " PPIS[6] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 21. " PPIS[5] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 20. " PPIS[4] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " PPIS[3] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 18. " PPIS[2] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 17. " PPIS[1] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " PPIS[0] ,Controls the group for the corresponding PPIs" "Group 0,Group 1" bitfld.long 0x00 15. " SGI[15] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 14. " SGI[14] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " SGI[13] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 12. " SGI[12] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 11. " SGI[11] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " SGI[10] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 9. " SGI[9] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 8. " SGI[8] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " SGI[7] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 6. " SGI[6] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 5. " SGI[5] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " SGI[4] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 3. " SGI[3] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 2. " SGI[2] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " SGI[1] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" bitfld.long 0x00 0. " SGI[0] ,Controls the group for the corresponding SGIs" "Group 0,Group 1" textline " " width 24. group.long 0x10100++0x03 line.long 0x00 "GICR_ISET/CLR_ENABLER0,Interrupt Group Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PPI[15] ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PPI[14] ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PPI[13] ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PPI[12] ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PPI[11] ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PPI[10] ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PPI[9] ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PPI[8] ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PPI[7] ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PPI[6] ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PPI[5] ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PPI[4] ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PPI[3] ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PPI[2] ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PPI[1] ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PPI[0] ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SGI[15] ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SGI[14] ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SGI[13] ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SGI[12] ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SGI[11] ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SGI[10] ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SGI[9] ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SGI[8] ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SGI[7] ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SGI[6] ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SGI[5] ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SGI[4] ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SGI[3] ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SGI[2] ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SGI[1] ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SGI[0] ,Set/Clear Enable Bit 0" "Disabled,Enabled" group.long 0x10200++0x03 line.long 0x00 "GICR_ISET/CLR_PENDR0,Interrupt Set/Clear-Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PPI[15] ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PPI[14] ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PPI[13] ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PPI[12] ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PPI[11] ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PPI[10] ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PPI[9] ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PPI[8] ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PPI[7] ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PPI[6] ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PPI[5] ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PPI[4] ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PPI[3] ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PPI[2] ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PPI[1] ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PPI[0] ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SGI[15] ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SGI[14] ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SGI[13] ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SGI[12] ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SGI[11] ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SGI[10] ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SGI[9] ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SGI[8] ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SGI[7] ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SGI[6] ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SGI[5] ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SGI[4] ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SGI[3] ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SGI[2] ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SGI[1] ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SGI[0] ,Set/Clear Pending Bit 0" "Not pending,Pending" group.long 0x10300++0x03 line.long 0x00 "GICR_ISET/CLR_ACTIVER0,Interrupt Set/Clear-Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PPI[15] ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PPI[14] ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PPI[13] ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PPI[12] ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PPI[11] ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PPI[10] ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PPI[9] ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PPI[8] ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PPI[7] ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PPI[6] ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PPI[5] ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PPI[4] ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PPI[3] ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PPI[2] ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PPI[1] ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PPI[0] ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SGI[15] ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SGI[14] ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SGI[13] ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SGI[12] ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SGI[11] ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SGI[10] ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SGI[9] ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SGI[8] ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SGI[7] ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SGI[6] ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SGI[5] ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SGI[4] ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SGI[3] ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SGI[2] ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SGI[1] ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SGI[0] ,Set/Clear Active Bit 0" "Not active,Active" textline " " width 18. group.long 0x10400++0x03 line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 27.--31. 1. " PRI3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 19.--23. 1. " PRI2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 11.--15. 1. " PRI1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 3.--7. 1. " PRI0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x10404++0x03 line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 27.--31. 1. " PRI7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 19.--23. 1. " PRI6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 11.--15. 1. " PRI5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 3.--7. 1. " PRI4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x10408++0x03 line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 27.--31. 1. " PRI11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 19.--23. 1. " PRI10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 11.--15. 1. " PRI9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 3.--7. 1. " PRI8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x1040C++0x03 line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 27.--31. 1. " PRI15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 19.--23. 1. " PRI14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 11.--15. 1. " PRI13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 3.--7. 1. " PRI12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x10410++0x03 line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 27.--31. 1. " PRI19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 19.--23. 1. " PRI18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 11.--15. 1. " PRI17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 3.--7. 1. " PRI16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x10414++0x03 line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 27.--31. 1. " PRI23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 19.--23. 1. " PRI22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 11.--15. 1. " PRI21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 3.--7. 1. " PRI20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x10418++0x03 line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 27.--31. 1. " PRI27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 19.--23. 1. " PRI26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 11.--15. 1. " PRI25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 3.--7. 1. " PRI24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x1041C++0x03 line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 27.--31. 1. " PRI31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 19.--23. 1. " PRI30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 11.--15. 1. " PRI29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 3.--7. 1. " PRI28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " textline " " rgroup.long 0x10C00++0x03 line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register 0" bitfld.long 0x00 31. " ICF[15] ,Interrupt configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF[14] ,Interrupt configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF[13] ,Interrupt configuration 13 (SGI)" "Level,Edge" bitfld.long 0x00 25. " ICF[12] ,Interrupt configuration 12 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 23. " ICF[11] ,Interrupt configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF[10] ,Interrupt configuration 10 (SGI)" "Level,Edge" bitfld.long 0x00 19. " ICF[9] ,Interrupt configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF[8] ,Interrupt configuration 8 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 15. " ICF[7] ,Interrupt configuration 7 (SGI)" "Level,Edge" bitfld.long 0x00 13. " ICF[6] ,Interrupt configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF[5] ,Interrupt configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF[4] ,Interrupt configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF[3] ,Interrupt configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF[2] ,Interrupt configuration 2 (SGI)" "Level,Edge" bitfld.long 0x00 3. " ICF[1] ,Interrupt configuration 1 (SGI)" "Level,Edge" bitfld.long 0x00 1. " ICF[0] ,Interrupt configuration 0 (SGI)" "Level,Edge" group.long 0x10C04++0x03 line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register 1" bitfld.long 0x00 31. " ICF[15] ,Interrupt configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF[14] ,Interrupt configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF[13] ,Interrupt configuration 13 (PPI)" "Level,Edge" bitfld.long 0x00 25. " ICF[12] ,Interrupt configuration 12 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 23. " ICF[11] ,Interrupt configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF[10] ,Interrupt configuration 10 (PPI)" "Level,Edge" bitfld.long 0x00 19. " ICF[9] ,Interrupt configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF[8] ,Interrupt configuration 8 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 15. " ICF[7] ,Interrupt configuration 7 (PPI)" "Level,Edge" bitfld.long 0x00 13. " ICF[6] ,Interrupt configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF[5] ,Interrupt configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF[4] ,Interrupt configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF[3] ,Interrupt configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF[2] ,Interrupt configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF[1] ,Interrupt configuration 1 (PPI)" "Level,Edge" bitfld.long 0x00 1. " ICF[0] ,Interrupt configuration 0 (PPI)" "Level,Edge" textline " " tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICR_PIDR0,Redistributor Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICR_PIDR1,Redistributor Identification Register 1" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICR_PIDR2,Redistributor Identification Register 2" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICR_PIDR3,Redistributor Identification Register 3" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_PIDR4,Redistributor Identification Register 4" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_PIDR5,Redistributor Identification Register 5" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_PIDR6,Redistributor Identification Register 6" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_PIDR7,Redistributor Identification Register 7" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICR_PIDR4,Redistributor Identification Register 4" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD4++0x03 line.long 0x00 "GICR_PIDR5,Redistributor Identification Register 5" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFD8++0x03 line.long 0x00 "GICR_PIDR6,Redistributor Identification Register 6" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFDC++0x03 line.long 0x00 "GICR_PIDR7,Redistributor Identification Register 7" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_CIDR0,Redistributor Component Identification Register 0" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_CIDR1,Redistributor Component Identification Register 1" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_CIDR2,Redistributor Component Identification Register 2" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_CIDR3,Redistributor Component Identification Register 3" hexmask.long.byte 0x00 0.--7. 1. " COMPONENTID ,Component ID" tree.end tree.end width 0x0B endif tree.end AUTOINDENT.POP tree.end AUTOINDENT.POP endif sif (CORENAME()=="CORTEXA76") tree "Core Registers (Cortex-A76)" AUTOINDENT.PUSH AUTOINDENT.ON center tree tree.open ("AArch64") tree "ID Registers" rgroup.quad spr:0x30000++0x00 line.quad 0x00 "MIDR_EL1,Main ID Register" hexmask.quad.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer code" bitfld.quad 0x00 20.--23. "VARIANT,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "ARCHITECTURE,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ID reg. defined" newline hexmask.quad.word 0x00 4.--15. 1. "PARTNUM,Primary Part Number" bitfld.quad 0x00 0.--3. "REVISION,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0" bitfld.quad 0x00 60.--63. "CSV3,Speculative use of faulting data" "Reserved,Forbidden,?..." bitfld.quad 0x00 56.--59. "CSV2,Speculative use of out of context branch targets / Additional SCXTNUM_ELx registers support" "Reserved,Not supported,?..." bitfld.quad 0x00 28.--31. "RAS,Reliability, Availability, and Serviceability (RAS) Extension support" "Not supported,RASv1p0 (ARMv8.2),?..." newline bitfld.quad 0x00 24.--27. "GIC,System register GIC CPU interface support" "Not supported,Up to GICv4,?..." bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD support" "Reserved,Supported + FP16,?..." bitfld.quad 0x00 16.--19. "FP,Floating-point" "Reserved,Supported + FP16,?..." newline bitfld.quad 0x00 12.--15. "EL3,EL3 exception level handling" "Reserved,AArch64,?..." bitfld.quad 0x00 8.--11. "EL2,EL2 exception level handling" "Reserved,AArch64,?..." bitfld.quad 0x00 4.--7. "EL1,EL1 exception level handling" "Reserved,AArch64,?..." newline bitfld.quad 0x00 0.--3. "EL0,EL0 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..." rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware" "Reserved,2,?..." bitfld.quad 0x00 20.--23. "WRPS,Number of watchpoints" "Reserved,Reserved,Reserved,4,?..." bitfld.quad 0x00 12.--15. "BRPS,Number of breakpoints" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitor Extension (PMU) version" "Reserved,Reserved,Reserved,Reserved,PMUv3p1 (ARMv8.2),?..." bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension version. Indicates whether System register interface to a PE trace unit is implemented" "Not supported,?..." bitfld.quad 0x00 0.--3. "DEBUGVER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8.2,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0" bitfld.quad 0x00 44.--47. "DP,Dot Product instructions support in AArch64 state" "Reserved,Supported,?..." bitfld.quad 0x00 28.--31. "RDM,Rounding Double Multiply Add/Subtract instructions (SQRDMLAH/SQRDMLSH) support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "ATOMIC,Atomic instructions support in AArch64 state" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "CRC32,CRC32 instructions support in AArch64 state" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions support in AArch64 state" "Not supported,Supported,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions support in AArch64 state" "Not supported,Supported,?..." newline bitfld.quad 0x00 4.--7. "AES,AES instructions (AESE/AESD/AESMC/AESIMC/PMULL/PMULL2) support in AArch64 state" "Not supported,Reserved,Supported,?..." rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "TGRAN4,4KB memory translation granule size support" "Supported,?..." bitfld.quad 0x00 24.--27. "TGRAN64,64KB memory translation granule size support" "Supported,?..." bitfld.quad 0x00 20.--23. "TGRAN16,16KB memory translation granule size support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "BIGENDEL0,Mixed-endian support only at EL0" "Not supported,?..." bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..." rgroup.quad spr:0x30041++0x00 line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1" bitfld.quad 0x00 4.--7. "SSBS,Speculative Store Bypass Safe (SSBS) support. Indicates whether AArch64 provides the PSTATE.SSBS mechanism" "Reserved,Supported,?..." rgroup.quad spr:0x30051++0x00 line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1" rgroup.quad spr:0x30061++0x00 line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1" bitfld.quad 0x00 20.--23. "LRCPC,LDAPUR*/STLUR*/LDAPR* instructions support" "Reserved,LDAPR*,?..." bitfld.quad 0x00 0.--3. "DPB,DC CVAP and DC CVADP instructions support" "Reserved,DC CVAP,?..." rgroup.quad spr:0x30071++0x00 line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1" bitfld.quad 0x00 28.--31. "XNX,EL0/EL1 execute-never control distinction at stage 2 support" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "SPECSEI,Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory" "Not possible,?..." bitfld.quad 0x00 20.--23. "PAN,Privileged Access Never (PAN) support" "Reserved,Reserved,Extended,?..." newline bitfld.quad 0x00 16.--19. "LO,Limited Order Regions support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "HPDS,Hierarchical Permission Disables support" "Reserved,Reserved,Extended,?..." bitfld.quad 0x00 8.--11. "VH,Virtualization Host Extensions support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "VMIDBITS,Number of VMID bits" "Reserved,Reserved,16 bits,?..." bitfld.quad 0x00 0.--3. "HAFDBS,Hardware updates to Access flag and Dirty state in translation tables support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30072++0x00 line.quad 0x00 "ID_AA64MMFR2_EL1,AArch64 Memory Model Feature Register 2" bitfld.quad 0x00 16.--19. "LVA,Larger VA support" "Supported 48-bit,?..." bitfld.quad 0x00 12.--15. "IESB,SCTLR_ELx.IESB bit support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "LSM,LSMAOE and nTLSMD bits support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "UAO,User Access Override support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "CNP,Common not Private translations support" "Reserved,Supported,?..." rgroup.quad spr:0x30054++0x00 line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0" rgroup.quad spr:0x30055++0x00 line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1" rgroup.quad spr:0x30010++0x00 line.quad 0x00 "ID_PFR0_EL1,AArch32 Processor Feature Register 0" bitfld.quad 0x00 28.--31. "RAS,Reliability, Availability and Serviceability (RAS) Extension support" "Reserved,RASv1p0 (ARMv8.2),?..." bitfld.quad 0x00 16.--19. "CSV2,Speculative use of out of context branch targets" "Not supported,Forbidden,?..." bitfld.quad 0x00 12.--15. "STATE3,T32EE instruction set support" "Not supported,?..." newline bitfld.quad 0x00 8.--11. "STATE2,Jazelle extension support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "STATE1,T32 instruction set support" "Reserved,Reserved,Reserved,After Thumb-2,?..." bitfld.quad 0x00 0.--3. "STATE0,A32 instruction set support" "Reserved,Supported,?..." rgroup.quad spr:0x30011++0x00 line.quad 0x00 "ID_PFR1_EL1,AArch32 Processor Feature Register 1" bitfld.quad 0x00 28.--31. "GIC_CPU,System register GIC CPU interface support" "Not supported,Up to GICv4,?..." bitfld.quad 0x00 24.--27. "VIRT_FRAC,Virtualization fractional support" "Not supported,?..." bitfld.quad 0x00 20.--23. "SEC_FRAC,Security fractional support" "Not supported,?..." newline bitfld.quad 0x00 16.--19. "GENTIMER,Generic timer support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "V,Virtualization extensions support" "Not supported,?..." bitfld.quad 0x00 8.--11. "MPM,Microcontroller programmer's model support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "S,Security extensions architecture v1 support" "Not supported,?..." bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 programmer's model support" "Not supported,?..." rgroup.quad spr:0x30034++0x00 line.quad 0x00 "ID_PFR2_EL1,AArch32 Processor Feature Register 2" bitfld.quad 0x00 4.--7. "SSBS,Speculative Store Bypass Safe (SSBS) support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "CSV3,Speculative use of faulting data" "Reserved,Forbidden,?..." rgroup.quad spr:0x30012++0x00 line.quad 0x00 "ID_DFR0_EL1,AArch32 Debug Feature Register 0" bitfld.quad 0x00 24.--27. "PERFMON,Performance Monitor Model support" "Reserved,Reserved,Reserved,Reserved,PMUv3,?..." bitfld.quad 0x00 20.--23. "MPROFDBG,M Profile Debug support" "Not supported,?..." bitfld.quad 0x00 16.--19. "MMAPTRC,Trace Model (Memory-Mapped) support" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "COPTRC,Coprocessor-Based Trace Debug Model support" "Not supported,?..." bitfld.quad 0x00 4.--7. "COPSDBG,Secure Debug Model (Coprocessor) support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..." bitfld.quad 0x00 0.--3. "COPDBG,Coprocessor Debug Model support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..." rgroup.quad spr:0x30013++0x00 line.quad 0x00 "ID_AFR0_EL1,AArch32 Auxiliary Feature Register 0" rgroup.quad spr:0x30014++0x00 line.quad 0x00 "ID_MMFR0_EL1,AArch32 Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "INNERSHR,Indicates the innermost shareability domain implemented" "Reserved,HW coherency,?..." bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings support" "Not supported,?..." bitfld.quad 0x00 20.--23. "AUXREG,Auxiliary Register Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA support" "Not supported,?..." bitfld.quad 0x00 12.--15. "SHARELVL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.quad 0x00 8.--11. "OUTERSHR,Indicates the outermost shareability domain implemented" "Reserved,HW coherency,?..." newline bitfld.quad 0x00 4.--7. "PMSA,Protected Memory System Architecture (PMSA) support" "Not supported,?..." bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7/PXN/L-DESC,?..." rgroup.quad spr:0x30015++0x00 line.quad 0x00 "ID_MMFR1_EL1,AArch32 Memory Model Feature Register 1" bitfld.quad 0x00 28.--31. "BPRED,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..." bitfld.quad 0x00 24.--27. "L1TSTCLN,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "L1UNI,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 16.--19. "L1HVD,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "L1UNISW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "L1HVDSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "L1UNIVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "L1HVDVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture support" "Not supported,?..." rgroup.quad spr:0x30016++0x00 line.quad 0x00 "ID_MMFR2_EL1,AArch32 Memory Model Feature Register 2" bitfld.quad 0x00 28.--31. "HWACCFLG,Hardware Access Flag support" "Not supported,?..." bitfld.quad 0x00 24.--27. "WFISTALL,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MEMBARR,Memory Barrier Operations Support" "Reserved,Reserved,DSB/ISB/DMB,?..." newline bitfld.quad 0x00 16.--19. "UNITLB,TLB Maintenance Operations/Unified Architecture support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,All operations,?..." bitfld.quad 0x00 12.--15. "HVDTLB,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "LL1HVDRNG,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "L1HVDBG,Background Prefetch Cache Range Operations/Harvard Architecture support" "Not supported,?..." bitfld.quad 0x00 0.--3. "L1HVDFG,Foreground Prefetch Cache Range Operations/Harvard Architecture support" "Not supported,?..." rgroup.quad spr:0x30017++0x00 line.quad 0x00 "ID_MMFR3_EL1,AArch32 Memory Model Feature Register 3" bitfld.quad 0x00 28.--31. "SUPERSEC,Supersection support" "Supported,?..." bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.quad 0x00 20.--23. "COHWALK,Coherent walk. Indicates whether translation table updates require a clean to the point of unification" "Reserved,Not required,?..." newline bitfld.quad 0x00 16.--19. "PAN,Privileged Access Never support" "Reserved,Reserved,Extended,?..." bitfld.quad 0x00 12.--15. "MAINTBCST,Maintenance broadcast Support" "Reserved,Reserved,Shareability,?..." bitfld.quad 0x00 8.--11. "BPMAINT,Invalidate Branch predictor Support" "Reserved,Reserved,VA,?..." newline bitfld.quad 0x00 4.--7. "CMAINTSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "CMAINTVA,Invalidate Cache MVA support" "Reserved,Supported,?..." rgroup.quad spr:0x30026++0x00 line.quad 0x00 "ID_MMFR4_EL1,AArch32 Memory Model Feature Register 4" bitfld.quad 0x00 20.--23. "LSM,Load/store multiple" "Not supported,?..." bitfld.quad 0x00 16.--19. "HPDS,Hierarchical Permission Disabled support" "Reserved,Reserved,Extended,?..." bitfld.quad 0x00 12.--15. "CNP,Common not Private support" "Reserved,Supported,?..." newline bitfld.quad 0x00 8.--11. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "AC2,Indicates the extension of the HACTLR register using HACTLR2" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SPECSEI,Describes whether the PE can generate SError interrupt exceptions from speculative reads of memory" "Not possible,?..." rgroup.quad spr:0x30020++0x00 line.quad 0x00 "ID_ISAR0_EL1,AArch32 Instruction Set Attribute Register 0" bitfld.quad 0x00 24.--27. "DIVIDE,Divide instructions support" "Reserved,Reserved,T32/A32,?..." bitfld.quad 0x00 20.--23. "DEBUG,Debug instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 16.--19. "COPROC,Coprocessor instructions support" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "CMPBRANCH,Combined Compare and Branch instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BITFIELD,Bitfield instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "BITCOUNT,Bit Counting instructions support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "SWAP,Swap instructions support" "Not supported,?..." rgroup.quad spr:0x30021++0x00 line.quad 0x00 "ID_ISAR1_EL1,AArch32 Instruction Set Attribute Register 1" bitfld.quad 0x00 28.--31. "JAZELLE,Jazelle instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "INTERWORK,Interwork instructions support" "Reserved,Reserved,Reserved,A32-BX like,?..." bitfld.quad 0x00 20.--23. "IMMEDIATE,Immediate instructions support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "IFTHEN,If then instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "EXTEND,Extend instructions support" "Reserved,Reserved,Fully supported,?..." bitfld.quad 0x00 8.--11. "EXCEPT_AR,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "EXCEPT,Exception in A32 instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "ENDIAN,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30022++0x00 line.quad 0x00 "ID_ISAR2_EL1,AArch32 Instruction Set Attribute Register 2" bitfld.quad 0x00 28.--31. "REVERSAL,Reversal instructions support" "Reserved,Reserved,REV/REV16/REVSH/RBIT,?..." bitfld.quad 0x00 24.--27. "PSR_AR,PSR Instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MULTU,Advanced unsigned multiply instructions support" "Reserved,Reserved,UMULL/UMLAL/UMAAL,?..." newline bitfld.quad 0x00 16.--19. "MULTS,Advanced signed multiply instructions support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "MULT,Multiply instructions support" "Reserved,Reserved,MUL/MLA/MLS,?..." bitfld.quad 0x00 8.--11. "MULTIACCESSINT,Multi-access interruptible instructions support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "MEMHINT,Memory hint instructions support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLDW,?..." bitfld.quad 0x00 0.--3. "LOADSTORE,Load and store instructions support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30023++0x00 line.quad 0x00 "ID_ISAR3_EL1,AArch32 Instruction Set Attribute Register 3" bitfld.quad 0x00 28.--31. "T32EE,T32EE Instructions support" "Not supported,?..." bitfld.quad 0x00 24.--27. "TRUENOP,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "T32COPY,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "TABBRANCH,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SYNCHPRIM,Synchronization primitive instructions support [LDREX/STREX/CLREX/LDREXB/STREXB/STREXH/LDREXD/STREXD]" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "SVC,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "SIMD,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Full support,?..." bitfld.quad 0x00 0.--3. "SATURATE,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30024++0x00 line.quad 0x00 "ID_ISAR4_EL1,AArch32 Instruction Set Attribute Register 4" bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking support" "Not supported,?..." bitfld.quad 0x00 24.--27. "PSR_M,PSR_M Instructions Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "SYNCHPRIM_FRAC,Synchronization Primitive instructions" "Full support,?..." newline bitfld.quad 0x00 16.--19. "BARRIER,Barrier instructions in A32/T32 support" "Reserved,DMB/DSB/ISB,?..." bitfld.quad 0x00 12.--15. "SMC,SMC Instructions support" "Not supported,?..." bitfld.quad 0x00 8.--11. "WRITEBACK,Write-Back Instructions support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "WITHSHIFTS,With-Shift Instructions support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "UNPRIV,Unprivileged Instructions support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30025++0x00 line.quad 0x00 "ID_ISAR5_EL1,AArch32 Instruction Set Attribute Register 5" bitfld.quad 0x00 24.--27. "RDM,VQRDMLAH and VQRDMLSH instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 16.--19. "CRC32,CRC32 instructions support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions support" "Not supported,Supported,?..." newline bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions support" "Not supported,Supported,?..." bitfld.quad 0x00 4.--7. "AES,AES instructions support" "Not supported,Reserved,Fully supported,?..." bitfld.quad 0x00 0.--3. "SEVL,SEVL instructions support" "Reserved,Supported,?..." rgroup.quad spr:0x30027++0x00 line.quad 0x00 "ID_ISAR6_EL1,AArch32 Instruction Set Attribute Register 6" bitfld.quad 0x00 4.--7. "DP,Indicates support for dot product instructions (UDOT/VSDOT) in AArch32 state" "Reserved,Implemented,?..." rgroup.quad spr:0x30005++0x00 line.quad 0x00 "MPIDR_EL1,Multiprocessor Affinity Register" hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Affinity level 3" bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Reserved,Very interdependent" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0" rgroup.quad spr:0x30006++0x00 line.quad 0x00 "REVIDR_EL1,Revision ID Register" rgroup.quad spr:0x33007++0x00 line.quad 0x00 "DCZID_EL0,Data Cache Zero ID Register" bitfld.quad 0x00 4. "DZP,Data zero prohibited. Indicates whether use of rDC ZVA instructions is permitted or prohibited" "Permitted,Prohibited" bitfld.quad 0x00 0.--3. "BS,Block size" "Reserved,Reserved,Reserved,Reserved,64 bytes,?..." rgroup.quad spr:0x30030++0x00 line.quad 0x00 "MVFR0_EL1,AArch32 Media And VFP Feature Register 0" bitfld.quad 0x00 28.--31. "FPROUND,Indicates whether the floating point implementation provides support for rounding modes" "Reserved,Implemented,?..." bitfld.quad 0x00 24.--27. "FPSHVEC,Indicates whether the floating-point implementation provides support for the use of short vectors" "Not implemented,?..." bitfld.quad 0x00 20.--23. "FPSQRT,Indicates whether the floating-point implementation provides support for the ARMv6 VFP square root operations" "Reserved,Implemented,?..." newline bitfld.quad 0x00 16.--19. "FPDIVIDE,Indicates whether the floating-point implementation provides support for VFP divide operations" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "FPTRAP,Indicates whether the floating-point implementation provides support for exception trapping" "Not implemented,?..." bitfld.quad 0x00 8.--11. "FPDP,Indicates whether the floating-point implementation provides support for double-precision operations" "Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 4.--7. "FPSP,Indicates whether the floating-point implementation provides support for single-precision operations" "Reserved,Reserved,Implemented (VFPv3/VFPv4),?..." bitfld.quad 0x00 0.--3. "SIMDREG,Indicates whether the Advanced SIMD and floating-point implementation provides support for the Advanced SIMD and floating-point register bank" "Reserved,Reserved,32x64-bit registers,?..." rgroup.quad spr:0x30031++0x00 line.quad 0x00 "MVFR1_EL1,AArch32 Media And VFP Feature Register 1" bitfld.quad 0x00 28.--31. "SIMDFMAC,Indicates whether the Advanced SIMD implementation provides fused multiply accumulate instructions" "Reserved,Implemented,?..." bitfld.quad 0x00 24.--27. "FPHP,Indicates the level of half-precision floating-point support" "Reserved,Reserved,Reserved,Conversions/Arithmetic,?..." bitfld.quad 0x00 20.--23. "SIMDHP,Indicates the level of half-precision floating-point support" "Reserved,Reserved,Conversions/Arithmetic,?..." newline bitfld.quad 0x00 16.--19. "SIMDSP,Indicates whether the floating-point and Advanced SIMD implementation provides single-precision floating-point instructions" "Reserved,Implemented,?..." bitfld.quad 0x00 12.--15. "SIMDINT,Indicates whether the floating-point and Advanced SIMD implementation provides integer instructions" "Reserved,Implemented,?..." bitfld.quad 0x00 8.--11. "SIMDLS,Indicates whether the floating-point and Advanced SIMD implementation provides load/store instructions" "Reserved,Implemented,?..." newline bitfld.quad 0x00 4.--7. "FPDNAN,Indicates whether the floating-point implementation provides support only for the Default NaN mode" "Reserved,Propagation of NaN values,?..." bitfld.quad 0x00 0.--3. "FPFTZ,Indicates whether the floating-point implementation provides support only for the Flush-to-Zero mode of operation" "Reserved,Implemented,?..." rgroup.quad spr:0x30032++0x00 line.quad 0x00 "MVFR2_EL1,AArch32 Media And VFP Feature Register 2" bitfld.quad 0x00 4.--7. "FPMISC,Indicates whether the floating-point implementation provides support for miscellaneous VFP features" "Reserved,Reserved,Reserved,Reserved,Fully supported,?..." bitfld.quad 0x00 0.--3. "SIMDMISC,Indicates whether the Advanced SIMD implementation provides support for miscellaneous Advanced SIMD features" "Reserved,Reserved,Reserved,Fully supported,?..." rgroup.quad spr:0x31007++0x00 line.quad 0x00 "AIDR_EL1,Auxiliary ID Register" group.quad spr:0x34000++0x00 line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID Register" hexmask.quad.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer code" bitfld.quad 0x00 20.--23. "VARIANT,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "ARCHITECTURE,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ID reg. defined" newline hexmask.quad.word 0x00 4.--15. 1. "PARTNUM,Primary Part Number" bitfld.quad 0x00 0.--3. "REVISION,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.quad spr:0x34005++0x00 line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID Register" hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Affinity level 3" bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,Uniprocessor" bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Largely independent,Very interdependent" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0" tree.end tree "System Control And Configuration" group.quad spr:0x30100++0x00 line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)" bitfld.quad 0x00 44. "DSSBS,Default PSTATE.SSBS value on Exception Entry" "0,1" bitfld.quad 0x00 26. "UCI,Traps EL0 execution of cache maintenance instructions" "Trapped,Not trapped" newline bitfld.quad 0x00 25. "EE,Endianness of data accesses at EL1 and stage 1 translation table walks in the EL1&0 translation regime" "Little,Big" bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big" newline bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Set,Unchanged" bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization event enable" "Disabled,Enabled" newline bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Disabled,Enabled" bitfld.quad 0x00 18. "NTWE,Traps EL0 execution of WFE instructions" "Trapped,Not trapped" newline bitfld.quad 0x00 16. "NTWI,Traps EL0 execution of WFI instructions" "Trapped,Not trapped" bitfld.quad 0x00 15. "UCT,Traps EL0 accesses to the CTR_EL0 register" "Trapped,Not trapped" newline bitfld.quad 0x00 14. "DZE,Traps EL0 execution of DC ZVA instructions" "Trapped,Not trapped" bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 9. "UMA,User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D, A, I, F} masks" "Trapped,Not trapped" bitfld.quad 0x00 8. "SED,SETEND instruction availability" "No,Yes" newline bitfld.quad 0x00 7. "ITD,IT Disable" "No,Yes" bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier operation enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "SA0,SP Alignment check enable for EL0" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP Alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU enable for EL1&0 stage 1 address translation" "Disabled,Enabled" group.quad spr:0x35100++0x00 line.quad 0x00 "SCTLR_EL12,System Control Register (EL12)" bitfld.quad 0x00 44. "DSSBS,Default PSTATE.SSBS value on Exception Entry" "0,1" bitfld.quad 0x00 26. "UCI,Traps EL0 execution of cache maintenance instructions" "Trapped,Not trapped" newline bitfld.quad 0x00 25. "EE,Endianness of data accesses at EL1 and stage 1 translation table walks in the EL1&0 translation regime" "Little,Big" bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big" newline bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Set,Unchanged" bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization event enable" "Disabled,Enabled" newline bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Disabled,Enabled" bitfld.quad 0x00 18. "NTWE,Traps EL0 execution of WFE instructions" "Trapped,Not trapped" newline bitfld.quad 0x00 16. "NTWI,Traps EL0 execution of WFI instructions" "Trapped,Not trapped" bitfld.quad 0x00 15. "UCT,Traps EL0 accesses to the CTR_EL0 register" "Trapped,Not trapped" newline bitfld.quad 0x00 14. "DZE,Traps EL0 execution of DC ZVA instructions" "Trapped,Not trapped" bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 9. "UMA,User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D, A, I, F} masks" "Trapped,Not trapped" bitfld.quad 0x00 8. "SED,SETEND instruction availability" "No,Yes" newline bitfld.quad 0x00 7. "ITD,IT Disable" "No,Yes" bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier operation enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "SA0,SP Alignment check enable for EL0" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP Alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU enable for EL1&0 stage 1 address translation" "Disabled,Enabled" if (((per.q(spr:0x34110))&0x408000000)==0x408000000) group.quad spr:0x34100++0x00 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 44. "DSSBS,Default PSTATE.SSBS value on Exception Entry" "0,1" bitfld.quad 0x00 26. "UCI,Traps EL0 execution of cache maintenance instructions" "Trapped,Not trapped" newline bitfld.quad 0x00 25. "EE,Endianness of data accesses at EL2 and stage 1 translation table walks in the EL2&0 translation regime" "Little,Big" bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big" newline bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL2 exception level" "Set,Unchanged" bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization event enable" "Disabled,Enabled" newline bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Disabled,Enabled" bitfld.quad 0x00 18. "NTWE,Traps EL0 execution of WFE instructions" "Trapped,Not trapped" newline bitfld.quad 0x00 16. "NTWI,Traps EL0 execution of WFI instructions" "Trapped,Not trapped" bitfld.quad 0x00 15. "UCT,Traps EL0 accesses to the CTR_EL0 register" "Trapped,Not trapped" newline bitfld.quad 0x00 14. "DZE,Traps EL0 execution of DC ZVA instructions" "Trapped,Not trapped" bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND instruction availability" "No,Yes" bitfld.quad 0x00 7. "ITD,IT Disable" "No,Yes" newline bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier operation enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,SP Alignment check enable for EL0" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,SP Alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Alignment check enable" "Disabled,Enabled" bitfld.quad 0x00 0. "M,MMU enable for EL2&0 stage 1 address translation" "Disabled,Enabled" else group.quad spr:0x34100++0x00 line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)" bitfld.quad 0x00 44. "DSSBS,Default PSTATE.SSBS value on Exception Entry" "0,1" bitfld.quad 0x00 25. "EE,Endianness of data accesses at EL2 and stage 1 translation table walks in the EL2&0 translation regime" "Little,Big" newline bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization event enable" "Disabled,Enabled" bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,SP Alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU enable for EL2&0 stage 1 address translation" "Disabled,Enabled" endif group.quad spr:0x36100++0x00 line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)" bitfld.quad 0x00 44. "DSSBS,Default PSTATE.SSBS value on Exception Entry" "0,1" bitfld.quad 0x00 25. "EE,Endianness of data accesses at EL3 and stage 1 translation table walks in the EL3&0 translation regime" "Little,Big" newline bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization event enable" "Disabled,Enabled" bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Disabled,Enabled" newline bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Alignment check enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "M,MMU enable for EL3&0 stage 1 address translation" "Disabled,Enabled" group.quad spr:0x30101++0x00 line.quad 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)" group.quad spr:0x34101++0x00 line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)" bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance management registers enable" "Trapped,Not trapped" bitfld.quad 0x00 11. "SMEN,Scheme management registers enable" "Trapped,Not trapped" newline bitfld.quad 0x00 10. "TSIDEN,Thread scheme ID register enable" "Trapped,Not trapped" bitfld.quad 0x00 7. "PWREN,Power Control Registers enable" "Trapped,Not trapped" newline bitfld.quad 0x00 5. "ERXPFGEN,Error Record Register enable" "Trapped,Not trapped" bitfld.quad 0x00 4. "AMEN,Activity Monitor enable" "Trapped,Not trapped" newline bitfld.quad 0x00 1. "ECTLREN,Extended control registers enable" "Trapped,Not trapped" bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers enable" "Trapped,Not trapped" group.quad spr:0x36101++0x00 line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)" bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance management registers enable" "Trapped,Not trapped" bitfld.quad 0x00 11. "SMEN,Scheme management registers enable" "Trapped,Not trapped" newline bitfld.quad 0x00 10. "TSIDEN,Thread scheme ID register enable" "Trapped,Not trapped" bitfld.quad 0x00 7. "PWREN,Power Control Registers enable" "Trapped,Not trapped" newline bitfld.quad 0x00 5. "ERXPFGEN,Error Record Register enable" "Trapped,Not trapped" bitfld.quad 0x00 4. "AMEN,Activity Monitor enable" "Trapped,Not trapped" newline bitfld.quad 0x00 1. "ECTLREN,Extended control registers enable" "Trapped,Not trapped" bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers enable" "Trapped,Not trapped" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" group.quad spr:0x30F70++0x00 line.quad 0x00 "ATCR_EL1,CPU Auxiliary Translation Control Register (EL1)" bitfld.quad 0x00 13. "HWVAL160,Value of PBHA[1] on memory accesses due to page table walks using TTBR1_EL1 if HWEN160 is set" "0,1" bitfld.quad 0x00 12. "HWVAL159,Value of PBHA[0] on memory accesses due to page table walks using TTBR1_EL1 if HWEN159 is set" "0,1" newline bitfld.quad 0x00 9. "HWVAL060,Value of PBHA[1] on memory accesses due to page table walks using TTBR0_EL1 if HWEN060 is set" "0,1" bitfld.quad 0x00 8. "HWVAL059,Value of PBHA[0] on memory accesses due to page table walks using TTBR0_EL1 if HWEN059 is set" "0,1" newline bitfld.quad 0x00 5. "HWEN160,Enable use of PBHA[1] on memory accesses due to page table walks using TTBR1_EL1" "0,1" bitfld.quad 0x00 4. "HWEN159,Enable use of PBHA[0] on memory accesses due to page table walks using TTBR1_EL1" "0,1" newline bitfld.quad 0x00 1. "HWEN060,Enable use of PBHA[1] on memory accesses due to page table walks using TTBR0_EL1" "0,1" bitfld.quad 0x00 0. "HWEN059,Enable use of PBHA[0] on memory accesses due to page table walks using TTBR0_EL1" "0,1" if (((per.q(spr:0x34110))&0x400000000)==0x400000000) group.quad spr:0x35F70++0x00 line.quad 0x00 "ATCR_EL12,CPU Auxiliary Translation Control Register (EL12)" bitfld.quad 0x00 13. "HWVAL160,Value of PBHA[1] on memory accesses due to page table walks using TTBR1_EL1 if HWEN160 is set" "0,1" bitfld.quad 0x00 12. "HWVAL159,Value of PBHA[0] on memory accesses due to page table walks using TTBR1_EL1 if HWEN159 is set" "0,1" newline bitfld.quad 0x00 9. "HWVAL060,Value of PBHA[1] on memory accesses due to page table walks using TTBR0_EL1 if HWEN060 is set" "0,1" bitfld.quad 0x00 8. "HWVAL059,Value of PBHA[0] on memory accesses due to page table walks using TTBR0_EL1 if HWEN059 is set" "0,1" newline bitfld.quad 0x00 5. "HWEN160,Enable use of PBHA[1] on memory accesses due to page table walks using TTBR1_EL1" "0,1" bitfld.quad 0x00 4. "HWEN159,Enable use of PBHA[0] on memory accesses due to page table walks using TTBR1_EL1" "0,1" newline bitfld.quad 0x00 1. "HWEN060,Enable use of PBHA[1] on memory accesses due to page table walks using TTBR0_EL1" "0,1" bitfld.quad 0x00 0. "HWEN059,Enable use of PBHA[0] on memory accesses due to page table walks using TTBR0_EL1" "0,1" else group.quad spr:0x35F70++0x00 line.quad 0x00 "ATCR_EL12,CPU Auxiliary Translation Control Register (EL12)" endif group.quad spr:0x34F70++0x00 line.quad 0x00 "ATCR_EL2,CPU Auxiliary Translation Control Register (EL2)" bitfld.quad 0x00 13. "HWVAL160,Value of PBHA[1] on memory accesses due to page table walks using TTBR1_EL2 if HWEN160 is set" "0,1" bitfld.quad 0x00 12. "HWVAL159,Value of PBHA[0] on memory accesses due to page table walks using TTBR1_EL2 if HWEN159 is set" "0,1" newline bitfld.quad 0x00 9. "HWVAL060,Value of PBHA[1] on memory accesses due to page table walks using TTBR0_EL2 if HWEN060 is set" "0,1" bitfld.quad 0x00 8. "HWVAL059,Value of PBHA[0] on memory accesses due to page table walks using TTBR0_EL2 if HWEN059 is set" "0,1" newline bitfld.quad 0x00 5. "HWEN160,Enable use of PBHA[1] on memory accesses due to page table walks using TTBR1_EL2" "0,1" bitfld.quad 0x00 4. "HWEN159,Enable use of PBHA[0] on memory accesses due to page table walks using TTBR1_EL2" "0,1" newline bitfld.quad 0x00 1. "HWEN060,Enable use of PBHA[1] on memory accesses due to page table walks using TTBR0_EL2" "0,1" bitfld.quad 0x00 0. "HWEN059,Enable use of PBHA[0] on memory accesses due to page table walks using TTBR0_EL2" "0,1" group.quad spr:0x36F70++0x00 line.quad 0x00 "ATCR_EL3,CPU Auxiliary Translation Control Register (EL3)" bitfld.quad 0x00 9. "HWVAL060,Value of PBHA[1] on memory accesses due to page table walks using TTBR0_EL3 if HWEN060 is set" "0,1" bitfld.quad 0x00 8. "HWVAL059,Value of PBHA[0] on memory accesses due to page table walks using TTBR0_EL3 if HWEN059 is set" "0,1" newline bitfld.quad 0x00 1. "HWEN060,Enable use of PBHA[1] on memory accesses due to page table walks using TTBR0_EL3" "0,1" bitfld.quad 0x00 0. "HWEN059,Enable use of PBHA[0] on memory accesses due to page table walks using TTBR0_EL3" "0,1" group.quad spr:0x34F71++0x00 line.quad 0x00 "AVTCR_EL2,CPU Virtualization Auxiliary Translation Control Register (EL2)" bitfld.quad 0x00 9. "HWVAL060,Value of PBHA[1] on memory accesses due to page table walks using TTBR0_EL2 if HWEN060 is set" "0,1" bitfld.quad 0x00 8. "HWVAL059,Value of PBHA[0] on memory accesses due to page table walks using TTBR0_EL2 if HWEN059 is set" "0,1" newline bitfld.quad 0x00 1. "HWEN060,Enable use of PBHA[1] on memory accesses due to page table walks using TTBR0_EL2" "0,1" bitfld.quad 0x00 0. "HWEN059,Enable use of PBHA[0] on memory accesses due to page table walks using TTBR0_EL2" "0,1" rgroup.quad spr:0x30F00++0x00 line.quad 0x00 "CPUCFR_EL1,CPU Configuration Register" bitfld.quad 0x00 0.--1. "ECC,Indicates whether ECC is present or not" "Not present,Present,?..." group.quad spr:0x30F10++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" group.quad spr:0x30F11++0x00 line.quad 0x00 "CPUACTLR2_EL1,CPU Auxiliary Control Register 2" group.quad spr:0x30F12++0x00 line.quad 0x00 "CPUACTLR3_EL1,CPU Auxiliary Control Register 3" group.quad spr:0x30F14++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 61. "MXP_EN,Max-power throttle enable" "Disabled,Enabled" bitfld.quad 0x00 57.--58. "MXP_TP,Percentage of throttling in the load-store and vector execute units" "60%,50%,40%,30%" newline bitfld.quad 0x00 55.--56. "MXP_ATHR,Peak activity threshold at which max-power throttling is triggered" "70%,60%,50%,40%" bitfld.quad 0x00 54. "MM_VMID_THR,VMID filter threshold" "16,32" newline bitfld.quad 0x00 53. "MM_ASP_EN,Allocation of splintered pages in L2 TLB disable" "No,Yes" bitfld.quad 0x00 52. "MM_CH_DIS,Contiguous hint disable" "No,Yes" newline bitfld.quad 0x00 51. "MM_TLBPF_DIS,L2 TLB prefetcher disable" "No,Yes" bitfld.quad 0x00 49.--50. "HPA_MODE,Hardware page aggregation mode" "Moderately conservative,Aggressive,Moderately aggressive,Conservative" newline bitfld.quad 0x00 48. "HPA_CAP,Limited or full hardware page aggregation selection" "Limited,Full" bitfld.quad 0x00 47. "HPA_L1_DIS,HPA in L1 TLBs disable" "No,Yes" newline bitfld.quad 0x00 46. "HPA_DIS,Hardware page aggregation disable" "No,Yes" bitfld.quad 0x00 43. "L2_FLUSH,Allocation behavior of copybacks caused by L2 cache hardware flush" "Not allocated,Allocated" newline bitfld.quad 0x00 40.--41. "PFT_MM,DRAM prefetch using PrefetchTgt transactions for table walk requests" "Disabled,Conservatively,Aggressively,Always" bitfld.quad 0x00 38.--39. "PFT_LS,DRAM prefetch using PrefetchTgt transactions for load and store requests" "Disabled,Conservatively,Aggressively,Always" newline bitfld.quad 0x00 36.--37. "PFT_IF,DRAM prefetch using PrefetchTgt transactions for instruction fetch requests" "Disabled,Conservatively,Aggressively,Always" bitfld.quad 0x00 35. "CA_UCLEAN_EVICT_EN,Enable sending WriteEvict transactions on the CPU CHI interface" "Disabled,Enabled" newline bitfld.quad 0x00 34. "CA_EVICT_DIS,Disable sending of Evict transactions on the CPU CHI interface" "No,Yes" bitfld.quad 0x00 32. "ATOMIC_ACQ_NEAR,An atomic instruction to WB memory with acquire semantics" "Exclusive,Make up to 1" newline bitfld.quad 0x00 31. "ATOMIC_ST_NEAR,A store atomic instruction to WB memory that does not hit in the cache in Exclusive state" "Exclusive,Make up to 1" bitfld.quad 0x00 30. "ATOMIC_REL_NEAR,An atomic instruction to WB memory with release semantics that does not hit in the cache in Exclusive state" "Exclusive,Make up to 1" newline bitfld.quad 0x00 29. "ATOMIC_LD_NEAR,A load atomic (including SWP & CAS) instruction to WB memory that does not hit in the cache in Exclusive state" "Exclusive,Make up to 1" bitfld.quad 0x00 28. "TLD_PRED_DIS,Transient load prediction disable" "No,Yes" newline bitfld.quad 0x00 26. "DTLB_CABT_EN,TLB conflict data abort exception enable" "Disabled,Enabled" bitfld.quad 0x00 24.--25. "WS_THR_L2,Threshold for direct stream to L2 cache on store" "256B,4KB,8KB,Disabled" newline bitfld.quad 0x00 22.--23. "WS_THR_L3,Threshold for direct stream to L3 cache on store" "768B,16KB,32KB,Disabled" bitfld.quad 0x00 20.--21. "WS_THR_L4,Threshold for direct stream to L4 cache on store" "16KB,64KB,128KB,Disabled" newline bitfld.quad 0x00 18.--19. "WS_THR_DRAM,Threshold for direct stream to DRAM on store" "64KB,1MB designated as outer-allocate,1MB irrespective of outer-allocate,Disabled" bitfld.quad 0x00 17. "WS_THR_DCZVA,Have DCZVA use a lower WS_THR_L2 configuration" "Normal store,One lower stream" newline bitfld.quad 0x00 15. "PF_DIS,Data-side hardware prefetching disable" "No,Yes" bitfld.quad 0x00 12.--13. "PF_SS_L2_DIST,Single cache line stride prefetching L2 distance" "22,28,34,40" newline bitfld.quad 0x00 8. "PF_STI_DIS,Store prefetches at issue (not overriden by CPUECTLR_EL1[15]) disable" "No,Yes" bitfld.quad 0x00 7. "PF_STS_DIS,Store-stride prefetches disable" "No,Yes" newline bitfld.quad 0x00 5. "RPF_DIS,Region prefetcher disable" "No,Yes" bitfld.quad 0x00 4. "RPF_LO_CONF,Region prefetcher training behavior" "Limited,Always" newline bitfld.quad 0x00 3. "RPF_PHIT_EN,Region prefetcher propagation on hit enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EXTLLC,Internal or external Last-level cache in the system" "Internal,External" group.quad spr:0x36F80++0x00 line.quad 0x00 "CPUPSELR_EL3,Selected Instruction Private Select Register" group.quad spr:0x36F81++0x00 line.quad 0x00 "CPUPCR_EL3,Selected Instruction Private Control Register" group.quad spr:0x36F82++0x00 line.quad 0x00 "CPUPOR_EL3,Selected Instruction Private Opcode Register" group.quad spr:0x36F83++0x00 line.quad 0x00 "CPUPMR_EL3,Selected Instruction Private Mask Register" group.quad spr:0x30F27++0x00 line.quad 0x00 "CPUPWRCTLR_EL1,CPU Power Control Register" bitfld.quad 0x00 7.--9. "WFE_RET_CTRL,Wait for Event retention control" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" bitfld.quad 0x00 4.--6. "WFI_RET_CTRL,Wait for Interrupt retention control" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" newline bitfld.quad 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFE/WFI state" "Not requested,Requested" group.quad spr:0x30102++0x00 line.quad 0x00 "CPACR_EL1,Architectural Feature Access Control Register (EL1)" bitfld.quad 0x00 20.--21. "FPEN,Trap EL0/EL1 instructions that access the Advanced SIMD and floating-point registers" "EL0/EL1,EL0,EL0/EL1,Not trapped" group.quad spr:0x35102++0x00 line.quad 0x00 "CPACR_EL12,Architectural Feature Access Control Register (EL12)" bitfld.quad 0x00 20.--21. "FPEN,Trap EL0/EL1 instructions that access the Advanced SIMD and floating-point registers" "EL0/EL1,EL0,EL0/EL1,Not trapped" group.quad spr:0x34112++0x00 line.quad 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)" bitfld.quad 0x00 31. "TCPAC,Trap accesses to CPACR_EL1 register" "Not trapped,Trapped" bitfld.quad 0x00 10. "TFP,Trap EL0/EL1/EL2 instructions that access the Advanced SIMD and floating-point functionality" "Not trapped,Trapped" group.quad spr:0x36112++0x00 line.quad 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)" bitfld.quad 0x00 31. "TCPAC,Trap accesses to CPACR_EL1 register" "Not trapped,Trapped" bitfld.quad 0x00 10. "TFP,Trap EL0/EL1/EL2 instructions that access the Advanced SIMD and floating-point functionality" "Not trapped,Trapped" group.quad spr:0x36110++0x00 line.quad 0x00 "SCR_EL3,Secure Configuration Register" bitfld.quad 0x00 15. "TERR,Trap Error record accesses" "Not trapped,Trapped" bitfld.quad 0x00 14. "TLOR,Trap access to the LOR Registers from Non-secure EL1 and EL2 to EL3" "Not trapped,Trapped" newline bitfld.quad 0x00 13. "TWE,Trap EL2/EL1/EL0 execution of WFE instructions to EL3" "Not trapped,Trapped" bitfld.quad 0x00 12. "TWI,Trap EL2/EL1/EL0 execution of WFI instructions to EL3" "Not trapped,Trapped" newline bitfld.quad 0x00 11. "ST,Trap Secure EL1 accesses to the Counter-timer Physical Secure timer registers to EL3" "Trapped,Not trapped" bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" newline bitfld.quad 0x00 8. "HCE,Hypervisor Call instruction (HVC) enable" "Disabled,Enabled" bitfld.quad 0x00 7. "SMD,Secure Monitor Call instruction (SMC) disable" "No,Yes" newline bitfld.quad 0x00 3. "EA,External abort and SError interrupt routing" "Abort,Monitor" bitfld.quad 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" newline bitfld.quad 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" bitfld.quad 0x00 0. "NS,Secure mode" "Secure,Non-secure" if (((per.q(spr:0x34110))&0x8000000)==0x0000000)&&(((per.q(spr:0x34110))&0x08)==0x08)&&(((per.q(spr:0x34110))&0x10)==0x10)&&(((per.q(spr:0x34110))&0x20)==0x20) group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 38. "MIOCNCE,Mismatched Inner/Outer Cacheable Non-Coherency Enable" "Disabled,Enabled" newline bitfld.quad 0x00 37. "TEA,Route synchronous external abort exceptions to EL2" "Disabled,Enabled" bitfld.quad 0x00 36. "TERR,Trap Error record accesses" "Not trapped,Trapped" newline bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Not trapped,Trapped" bitfld.quad 0x00 34. "E2H,EL2 Host" "Disabled,Enabled" newline bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" newline bitfld.quad 0x00 30. "TRVM,Trap reads of virtual memory controls" "Not trapped,Trapped" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Not trapped,Trapped" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions from EL0" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Not trapped,Trapped" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 23. "TPCP,Trap Data/Unified Cache maintenance instructions to Point of Coherency to EL2" "Not trapped,Trapped" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Registers" "Not trapped,Trapped" bitfld.quad 0x00 20. "TIDCP,Trap IMPLEMENTATION DEFINED functionality" "Not trapped,Trapped" newline bitfld.quad 0x00 19. "TSC,Trap SMC instructions" "Not trapped,Trapped" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Not trapped,Trapped" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Not trapped,Trapped" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Not trapped,Trapped" newline bitfld.quad 0x00 14. "TWE,Trap WFE instructions" "Not trapped,Trapped" bitfld.quad 0x00 13. "TWI,Trap WFI instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "DC,Default Cacheability" "Disabled,Enabled" bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. Determines the minimum shareability domain that is applied to any barrier instruction executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.quad 0x00 8. "VSE,Virtual SError interrupt" "No pending,Pending" newline bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "Not pending,Pending" bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "Not pending,Pending" newline bitfld.quad 0x00 5. "AMO,Physical SError interrupt routing" "Disabled,Enabled" bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled" newline bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime" "Disabled,Enabled" elif (((per.q(spr:0x34110))&0x8000000)==0x0000000)&&(((per.q(spr:0x34110))&0x10)==0x10)&&(((per.q(spr:0x34110))&0x20)==0x20) group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 38. "MIOCNCE,Mismatched Inner/Outer Cacheable Non-Coherency Enable" "Disabled,Enabled" newline bitfld.quad 0x00 37. "TEA,Route synchronous external abort exceptions to EL2" "Disabled,Enabled" bitfld.quad 0x00 36. "TERR,Trap Error record accesses" "Not trapped,Trapped" newline bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Not trapped,Trapped" bitfld.quad 0x00 34. "E2H,EL2 Host" "Disabled,Enabled" newline bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" newline bitfld.quad 0x00 30. "TRVM,Trap reads of virtual memory controls" "Not trapped,Trapped" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Not trapped,Trapped" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions from EL0" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Not trapped,Trapped" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 23. "TPCP,Trap Data/Unified Cache maintenance instructions to Point of Coherency to EL2" "Not trapped,Trapped" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Registers" "Not trapped,Trapped" bitfld.quad 0x00 20. "TIDCP,Trap IMPLEMENTATION DEFINED functionality" "Not trapped,Trapped" newline bitfld.quad 0x00 19. "TSC,Trap SMC instructions" "Not trapped,Trapped" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Not trapped,Trapped" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Not trapped,Trapped" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Not trapped,Trapped" newline bitfld.quad 0x00 14. "TWE,Trap WFE instructions" "Not trapped,Trapped" bitfld.quad 0x00 13. "TWI,Trap WFI instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "DC,Default Cacheability" "Disabled,Enabled" bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. Determines the minimum shareability domain that is applied to any barrier instruction executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.quad 0x00 8. "VSE,Virtual SError interrupt" "No pending,Pending" newline bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,Physical SError interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 0. "VM,Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime" "Disabled,Enabled" elif (((per.q(spr:0x34110))&0x8000000)==0x0000000)&&(((per.q(spr:0x34110))&0x08)==0x08)&&(((per.q(spr:0x34110))&0x10)==0x10) group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 38. "MIOCNCE,Mismatched Inner/Outer Cacheable Non-Coherency Enable" "Disabled,Enabled" newline bitfld.quad 0x00 37. "TEA,Route synchronous external abort exceptions to EL2" "Disabled,Enabled" bitfld.quad 0x00 36. "TERR,Trap Error record accesses" "Not trapped,Trapped" newline bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Not trapped,Trapped" bitfld.quad 0x00 34. "E2H,EL2 Host" "Disabled,Enabled" newline bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" newline bitfld.quad 0x00 30. "TRVM,Trap reads of virtual memory controls" "Not trapped,Trapped" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Not trapped,Trapped" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions from EL0" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Not trapped,Trapped" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 23. "TPCP,Trap Data/Unified Cache maintenance instructions to Point of Coherency to EL2" "Not trapped,Trapped" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Registers" "Not trapped,Trapped" bitfld.quad 0x00 20. "TIDCP,Trap IMPLEMENTATION DEFINED functionality" "Not trapped,Trapped" newline bitfld.quad 0x00 19. "TSC,Trap SMC instructions" "Not trapped,Trapped" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Not trapped,Trapped" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Not trapped,Trapped" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Not trapped,Trapped" newline bitfld.quad 0x00 14. "TWE,Trap WFE instructions" "Not trapped,Trapped" bitfld.quad 0x00 13. "TWI,Trap WFI instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "DC,Default Cacheability" "Disabled,Enabled" bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. Determines the minimum shareability domain that is applied to any barrier instruction executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.quad 0x00 8. "VSE,Virtual SError interrupt" "No pending,Pending" newline bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "Not pending,Pending" bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "Not pending,Pending" newline bitfld.quad 0x00 5. "AMO,Physical SError interrupt routing" "Disabled,Enabled" bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled" newline bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime" "Disabled,Enabled" elif (((per.q(spr:0x34110))&0x8000000)==0x0000000)&&(((per.q(spr:0x34110))&0x08)==0x08)&&(((per.q(spr:0x34110))&0x20)==0x20) group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 38. "MIOCNCE,Mismatched Inner/Outer Cacheable Non-Coherency Enable" "Disabled,Enabled" newline bitfld.quad 0x00 37. "TEA,Route synchronous external abort exceptions to EL2" "Disabled,Enabled" bitfld.quad 0x00 36. "TERR,Trap Error record accesses" "Not trapped,Trapped" newline bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Not trapped,Trapped" bitfld.quad 0x00 34. "E2H,EL2 Host" "Disabled,Enabled" newline bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" newline bitfld.quad 0x00 30. "TRVM,Trap reads of virtual memory controls" "Not trapped,Trapped" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Not trapped,Trapped" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions from EL0" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Not trapped,Trapped" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 23. "TPCP,Trap Data/Unified Cache maintenance instructions to Point of Coherency to EL2" "Not trapped,Trapped" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Registers" "Not trapped,Trapped" bitfld.quad 0x00 20. "TIDCP,Trap IMPLEMENTATION DEFINED functionality" "Not trapped,Trapped" newline bitfld.quad 0x00 19. "TSC,Trap SMC instructions" "Not trapped,Trapped" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Not trapped,Trapped" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Not trapped,Trapped" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Not trapped,Trapped" newline bitfld.quad 0x00 14. "TWE,Trap WFE instructions" "Not trapped,Trapped" bitfld.quad 0x00 13. "TWI,Trap WFI instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "DC,Default Cacheability" "Disabled,Enabled" bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. Determines the minimum shareability domain that is applied to any barrier instruction executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.quad 0x00 8. "VSE,Virtual SError interrupt" "No pending,Pending" newline bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "Not pending,Pending" bitfld.quad 0x00 5. "AMO,Physical SError interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 0. "VM,Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime" "Disabled,Enabled" elif (((per.q(spr:0x34110))&0x8000000)==0x0000000)&&(((per.q(spr:0x34110))&0x08)==0x08) group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 38. "MIOCNCE,Mismatched Inner/Outer Cacheable Non-Coherency Enable" "Disabled,Enabled" newline bitfld.quad 0x00 37. "TEA,Route synchronous external abort exceptions to EL2" "Disabled,Enabled" bitfld.quad 0x00 36. "TERR,Trap Error record accesses" "Not trapped,Trapped" newline bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Not trapped,Trapped" bitfld.quad 0x00 34. "E2H,EL2 Host" "Disabled,Enabled" newline bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" newline bitfld.quad 0x00 30. "TRVM,Trap reads of virtual memory controls" "Not trapped,Trapped" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Not trapped,Trapped" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions from EL0" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Not trapped,Trapped" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 23. "TPCP,Trap Data/Unified Cache maintenance instructions to Point of Coherency to EL2" "Not trapped,Trapped" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Registers" "Not trapped,Trapped" bitfld.quad 0x00 20. "TIDCP,Trap IMPLEMENTATION DEFINED functionality" "Not trapped,Trapped" newline bitfld.quad 0x00 19. "TSC,Trap SMC instructions" "Not trapped,Trapped" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Not trapped,Trapped" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Not trapped,Trapped" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Not trapped,Trapped" newline bitfld.quad 0x00 14. "TWE,Trap WFE instructions" "Not trapped,Trapped" bitfld.quad 0x00 13. "TWI,Trap WFI instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "DC,Default Cacheability" "Disabled,Enabled" bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. Determines the minimum shareability domain that is applied to any barrier instruction executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "Not pending,Pending" newline bitfld.quad 0x00 5. "AMO,Physical SError interrupt routing" "Disabled,Enabled" bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled" newline bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime" "Disabled,Enabled" elif (((per.q(spr:0x34110))&0x8000000)==0x0000000)&&(((per.q(spr:0x34110))&0x10)==0x10) group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 38. "MIOCNCE,Mismatched Inner/Outer Cacheable Non-Coherency Enable" "Disabled,Enabled" newline bitfld.quad 0x00 37. "TEA,Route synchronous external abort exceptions to EL2" "Disabled,Enabled" bitfld.quad 0x00 36. "TERR,Trap Error record accesses" "Not trapped,Trapped" newline bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Not trapped,Trapped" bitfld.quad 0x00 34. "E2H,EL2 Host" "Disabled,Enabled" newline bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" newline bitfld.quad 0x00 30. "TRVM,Trap reads of virtual memory controls" "Not trapped,Trapped" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Not trapped,Trapped" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions from EL0" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Not trapped,Trapped" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 23. "TPCP,Trap Data/Unified Cache maintenance instructions to Point of Coherency to EL2" "Not trapped,Trapped" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Registers" "Not trapped,Trapped" bitfld.quad 0x00 20. "TIDCP,Trap IMPLEMENTATION DEFINED functionality" "Not trapped,Trapped" newline bitfld.quad 0x00 19. "TSC,Trap SMC instructions" "Not trapped,Trapped" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Not trapped,Trapped" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Not trapped,Trapped" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Not trapped,Trapped" newline bitfld.quad 0x00 14. "TWE,Trap WFE instructions" "Not trapped,Trapped" bitfld.quad 0x00 13. "TWI,Trap WFI instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "DC,Default Cacheability" "Disabled,Enabled" bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. Determines the minimum shareability domain that is applied to any barrier instruction executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "Not pending,Pending" newline bitfld.quad 0x00 5. "AMO,Physical SError interrupt routing" "Disabled,Enabled" bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled" newline bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime" "Disabled,Enabled" elif (((per.q(spr:0x34110))&0x8000000)==0x0000000)&&(((per.q(spr:0x34110))&0x20)==0x20) group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 38. "MIOCNCE,Mismatched Inner/Outer Cacheable Non-Coherency Enable" "Disabled,Enabled" newline bitfld.quad 0x00 37. "TEA,Route synchronous external abort exceptions to EL2" "Disabled,Enabled" bitfld.quad 0x00 36. "TERR,Trap Error record accesses" "Not trapped,Trapped" newline bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Not trapped,Trapped" bitfld.quad 0x00 34. "E2H,EL2 Host" "Disabled,Enabled" newline bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" newline bitfld.quad 0x00 30. "TRVM,Trap reads of virtual memory controls" "Not trapped,Trapped" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Not trapped,Trapped" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions from EL0" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Not trapped,Trapped" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 23. "TPCP,Trap Data/Unified Cache maintenance instructions to Point of Coherency to EL2" "Not trapped,Trapped" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Registers" "Not trapped,Trapped" bitfld.quad 0x00 20. "TIDCP,Trap IMPLEMENTATION DEFINED functionality" "Not trapped,Trapped" newline bitfld.quad 0x00 19. "TSC,Trap SMC instructions" "Not trapped,Trapped" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Not trapped,Trapped" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Not trapped,Trapped" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Not trapped,Trapped" newline bitfld.quad 0x00 14. "TWE,Trap WFE instructions" "Not trapped,Trapped" bitfld.quad 0x00 13. "TWI,Trap WFI instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "DC,Default Cacheability" "Disabled,Enabled" bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. Determines the minimum shareability domain that is applied to any barrier instruction executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.quad 0x00 8. "VSE,Virtual SError interrupt" "No pending,Pending" newline bitfld.quad 0x00 5. "AMO,Physical SError interrupt routing" "Disabled,Enabled" bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled" newline bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime" "Disabled,Enabled" else group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 38. "MIOCNCE,Mismatched Inner/Outer Cacheable Non-Coherency Enable" "Disabled,Enabled" newline bitfld.quad 0x00 37. "TEA,Route synchronous external abort exceptions to EL2" "Disabled,Enabled" bitfld.quad 0x00 36. "TERR,Trap Error record accesses" "Not trapped,Trapped" newline bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Not trapped,Trapped" bitfld.quad 0x00 34. "E2H,EL2 Host" "Disabled,Enabled" newline bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes" newline bitfld.quad 0x00 30. "TRVM,Trap reads of virtual memory controls" "Not trapped,Trapped" bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Not trapped,Trapped" newline bitfld.quad 0x00 27. "TGE,Trap General Exceptions from EL0" "Disabled,Enabled" bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Not trapped,Trapped" bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 23. "TPCP,Trap Data/Unified Cache maintenance instructions to Point of Coherency to EL2" "Not trapped,Trapped" bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Registers" "Not trapped,Trapped" bitfld.quad 0x00 20. "TIDCP,Trap IMPLEMENTATION DEFINED functionality" "Not trapped,Trapped" newline bitfld.quad 0x00 19. "TSC,Trap SMC instructions" "Not trapped,Trapped" bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Not trapped,Trapped" newline bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Not trapped,Trapped" bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Not trapped,Trapped" newline bitfld.quad 0x00 14. "TWE,Trap WFE instructions" "Not trapped,Trapped" bitfld.quad 0x00 13. "TWI,Trap WFI instructions" "Not trapped,Trapped" newline bitfld.quad 0x00 12. "DC,Default Cacheability" "Disabled,Enabled" bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. Determines the minimum shareability domain that is applied to any barrier instruction executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.quad 0x00 5. "AMO,Physical SError interrupt routing" "Disabled,Enabled" newline bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled" bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled" newline bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" bitfld.quad 0x00 0. "VM,Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime" "Disabled,Enabled" endif group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)" group.quad spr:0x35510++0x00 line.quad 0x00 "AFSR0_EL12,Auxiliary Fault Status Register 0 (EL12)" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)" group.quad spr:0x35511++0x00 line.quad 0x00 "AFSR1_EL12,Auxiliary Fault Status Register 1 (EL12)" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)" tree.open "Exception Syndrome Registers" if (((per.q(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x64000000||0x88000000||0x98000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x30520))&0xFC000000)==0x04000000) if (((per.q(spr:0x30520))&0x01000000)==0x01000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) if (((per.q(spr:0x30520))&0x01000000)==0x01000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRn,CRn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRn,CRn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" endif elif (((per.q(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x30520))&0x01000000)==0x01000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 10.--14. "RT2,Rt2 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCRR),Read(MRRC)" endif elif (((per.q(spr:0x30520))&0xFC000000)==0x18000000) if (((per.q(spr:0x30520))&0x01000000)==0x01000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,Immediate value from issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicated whether offset is added or subtracted" "Subtract,Add" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Unindexed,Post-indexed,Offset,Pre-indexed,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(STC),Read(LDC)" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" hexmask.quad.byte 0x00 12.--19. 1. "IMM8,Immediate value from issued instruction" newline bitfld.quad 0x00 5.--9. "RN,Rn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 4. "OFFSET,Indicated whether offset is added or subtracted" "Subtract,Add" newline bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Unindexed,Post-indexed,Offset,Pre-indexed,?..." bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(STC),Read(LDC)" endif elif (((per.q(spr:0x30520))&0xFC000000)==(0x1C000000||0x64000000)) if (((per.q(spr:0x30520))&0x01000000)==0x01000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x30520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x30520))&0xFC000000)==0x60000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS" elif (((per.q(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000||0x90000000||0x94000000)) if (((per.q(spr:0x30520))&0x3F)==0x10) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..." else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..." endif elif (((per.q(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x30520))&0x3F)==0x10) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL1 code" "Not generated,Generated" bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL1 code" "Not generated,Generated" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." endif elif (((per.q(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x30520))&0x3F)==0x10) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL1 code" "Not generated,Generated" bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL1 code" "Not generated,Generated" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." endif elif (((per.q(spr:0x30520))&0xFC800000)==0xB0800000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x30520))&0xFD000000)==0xBC000000) if (((per.q(spr:0x30520))&0x3F)==0x11) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,Reserved,Reserved,CE,?..." bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x30520))&0xFD000000)==0xBD000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Additional information about the SError interrupt" elif (((per.q(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x30520))&0xFD000000)==(0xC9000000||0xCD000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x30520))&0xFD000000)==(0xC8000000||0xCC000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL1 code" "Not generated,Generated" bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." endif if (((per.q(spr:0x35520))&0xFC000000)==(0x00000000||0x38000000||0x64000000||0x88000000||0x98000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x35520))&0xFC000000)==0x04000000) if (((per.q(spr:0x35520))&0x01000000)==0x01000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x35520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) if (((per.q(spr:0x35520))&0x01000000)==0x01000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRn,CRn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRn,CRn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" endif elif (((per.q(spr:0x35520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x35520))&0x01000000)==0x01000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 10.--14. "RT2,Rt2 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCRR),Read(MRRC)" endif elif (((per.q(spr:0x35520))&0xFC000000)==0x18000000) if (((per.q(spr:0x35520))&0x01000000)==0x01000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,Immediate value from issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicated whether offset is added or subtracted" "Subtract,Add" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Unindexed,Post-indexed,Offset,Pre-indexed,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(STC),Read(LDC)" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" hexmask.quad.byte 0x00 12.--19. 1. "IMM8,Immediate value from issued instruction" newline bitfld.quad 0x00 5.--9. "RN,Rn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 4. "OFFSET,Indicated whether offset is added or subtracted" "Subtract,Add" newline bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Unindexed,Post-indexed,Offset,Pre-indexed,?..." bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(STC),Read(LDC)" endif elif (((per.q(spr:0x35520))&0xFC000000)==(0x1C000000||0x64000000)) if (((per.q(spr:0x35520))&0x01000000)==0x01000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x35520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x35520))&0xFC000000)==0x60000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS" elif (((per.q(spr:0x35520))&0xFC000000)==(0x80000000||0x84000000||0x90000000||0x94000000)) if (((per.q(spr:0x35520))&0x3F)==0x10) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..." else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..." endif elif (((per.q(spr:0x35520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x35520))&0x3F)==0x10) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL12 code" "Not generated,Generated" bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL12 code" "Not generated,Generated" newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." endif elif (((per.q(spr:0x35520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x35520))&0x3F)==0x10) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL12 code" "Not generated,Generated" bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL12 code" "Not generated,Generated" newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." endif elif (((per.q(spr:0x35520))&0xFC800000)==0xB0800000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x35520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x35520))&0xFD000000)==0xBC000000) if (((per.q(spr:0x35520))&0x3F)==0x11) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,Reserved,Reserved,CE,?..." bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x35520))&0xFD000000)==0xBD000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Additional information about the SError interrupt" elif (((per.q(spr:0x35520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x35520))&0xFD000000)==(0xC9000000||0xCD000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x35520))&0xFD000000)==(0xC8000000||0xCC000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x35520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL12 code" "Not generated,Generated" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x35520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." endif if (((per.q(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x64000000||0x88000000||0x98000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x34520))&0xFC000000)==0x04000000) if (((per.q(spr:0x34520))&0x01000000)==0x01000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) if (((per.q(spr:0x34520))&0x01000000)==0x01000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRn,CRn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRn,CRn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x34520))&0x01000000)==0x01000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 10.--14. "RT2,Rt2 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCRR),Read(MRRC)" endif elif (((per.q(spr:0x34520))&0xFC000000)==0x18000000) if (((per.q(spr:0x34520))&0x01000000)==0x01000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,Immediate value from issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicated whether offset is added or subtracted" "Subtract,Add" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Unindexed,Post-indexed,Offset,Pre-indexed,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(STC),Read(LDC)" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" hexmask.quad.byte 0x00 12.--19. 1. "IMM8,Immediate value from issued instruction" newline bitfld.quad 0x00 5.--9. "RN,Rn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 4. "OFFSET,Indicated whether offset is added or subtracted" "Subtract,Add" newline bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Unindexed,Post-indexed,Offset,Pre-indexed,?..." bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(STC),Read(LDC)" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x1C000000||0x64000000)) if (((per.q(spr:0x34520))&0x01000000)==0x01000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==(0x4C000000||0x5C000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the SMC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==0x60000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS" elif (((per.q(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000||0x90000000||0x94000000)) if (((per.q(spr:0x34520))&0x3F)==0x10) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..." else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..." endif elif (((per.q(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x34520))&0x3F)==0x10) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL2 code" "Not generated,Generated" bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL2 code" "Not generated,Generated" newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." endif elif (((per.q(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x34520))&0x3F)==0x10) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL2 code" "Not generated,Generated" bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL2 code" "Not generated,Generated" newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." endif elif (((per.q(spr:0x34520))&0xFC800000)==0xB0800000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" newline bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x34520))&0xFD000000)==0xBC000000) if (((per.q(spr:0x34520))&0x3F)==0x11) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,Reserved,Reserved,CE,?..." bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x34520))&0xFD000000)==0xBD000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Additional information about the SError interrupt" elif (((per.q(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x34520))&0xFD000000)==(0xC9000000||0xCD000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x34520))&0xFD000000)==(0xC8000000||0xCC000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL2 code" "Not generated,Generated" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." endif if (((per.q(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x64000000||0x88000000||0x98000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x36520))&0xFC000000)==0x04000000) if (((per.q(spr:0x36520))&0x01000000)==0x01000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) if (((per.q(spr:0x36520))&0x01000000)==0x01000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRn,CRn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRn,CRn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" endif elif (((per.q(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x36520))&0x01000000)==0x01000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCR),Read(MRC/VMRS)" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 10.--14. "RT2,Rt2 value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 5.--9. "RT,Rt value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRm,CRm value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(MCRR),Read(MRRC)" endif elif (((per.q(spr:0x36520))&0xFC000000)==0x18000000) if (((per.q(spr:0x36520))&0x01000000)==0x01000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,Immediate value from issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicated whether offset is added or subtracted" "Subtract,Add" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Unindexed,Post-indexed,Offset,Pre-indexed,?..." newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(STC),Read(LDC)" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" hexmask.quad.byte 0x00 12.--19. 1. "IMM8,Immediate value from issued instruction" newline bitfld.quad 0x00 5.--9. "RN,Rn value from issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 4. "OFFSET,Indicated whether offset is added or subtracted" "Subtract,Add" newline bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Unindexed,Post-indexed,Offset,Pre-indexed,?..." bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write(STC),Read(LDC)" endif elif (((per.q(spr:0x36520))&0xFC000000)==(0x1C000000||0x64000000)) if (((per.q(spr:0x36520))&0x01000000)==0x01000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x36520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==(0x4C000000||0x5C000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the SMC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==0x60000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS" elif (((per.q(spr:0x36520))&0xFC000000)==0x7C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Exception_PACTrap,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad 0x00 0.--24. 1. "IMPL_DEF,Implementation defined" elif (((per.q(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000||0x90000000||0x94000000)) if (((per.q(spr:0x36520))&0x3F)==0x10) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..." else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..." endif elif (((per.q(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x36520))&0x3F)==0x10) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL3 code" "Not generated,Generated" bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL3 code" "Not generated,Generated" newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." endif elif (((per.q(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x36520))&0x3F)==0x10) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL3 code" "Not generated,Generated" bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL3 code" "Not generated,Generated" newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..." endif elif (((per.q(spr:0x36520))&0xFC800000)==0xB0800000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x36520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x36520))&0xFD000000)==0xBC000000) if (((per.q(spr:0x36520))&0x3F)==0x11) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,Reserved,Reserved,CE,?..." bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x36520))&0xFD000000)==0xBD000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Additional information about the SError interrupt" elif (((per.q(spr:0x36520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x36520))&0xFD000000)==(0xC9000000||0xCD000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x36520))&0xFD000000)==(0xC8000000||0xCC000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x36520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 13. "VNCR,Fault came from use of VNCR_EL2 register by EL3 code" "Not generated,Generated" bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug exception,?..." elif (((per.q(spr:0x36520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,Reserved,Reserved,Reserved,Reserved,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,Reserved,BTI instruction,Illegal execution,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Access to SVE,Reserved,TSTART instructions,Authorization failure,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..." endif tree.end newline rgroup.quad spr:0x30530++0x00 line.quad 0x00 "ERRIDR_EL1,Error ID Register" hexmask.quad.word 0x00 0.--15. 1. "NUM,Number of records that can be accessed through the Error Record system registers" group.quad spr:0x30531++0x00 line.quad 0x00 "ERRSELR_EL1,Error Record Select Register" bitfld.quad 0x00 0. "SEL,Selects the record accessed through the ERX registers" "Record 0,Record 1" if (((per.q(spr:0x30531))&0x01)==0x00) rgroup.quad spr:0x30540++0x00 line.quad 0x00 "ERXFR_EL1,Selected Error Record Feature Register - ERR0FR - Record 0" bitfld.quad 0x00 18.--19. "CEO,Corrected error overwrite" "No overwrite,?..." bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..." newline bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented" bitfld.quad 0x00 12.--14. "CEC,Corrected error counter" "Reserved,Reserved,Implemented/8-bit,?..." newline bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..." newline bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 0.--1. "ED,Error detection and correction[Lock/Split]" "Reserved,Reserved,Implemented,?..." group.quad spr:0x30541++0x00 line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register - ER0CTLR - Record 0" bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled" bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled" group.quad spr:0x30542++0x00 line.quad 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register - ER0STATUS - Record 0" bitfld.quad 0x00 31. "AV,Address valid" "Not valid,Valid" bitfld.quad 0x00 30. "V,Status register valid" "Not valid,Valid" newline bitfld.quad 0x00 29. "UE,Uncorrected Error" "No error,>=1 error" bitfld.quad 0x00 28. "ER,Error reported" "No error,Error" newline bitfld.quad 0x00 27. "OF,Error overflow" "No error,>=1 error" bitfld.quad 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid" newline bitfld.quad 0x00 24.--25. "CE,Corrected errors" "No error,>=1 transient,>=1 error,>=1 persistent" bitfld.quad 0x00 23. "DE,Deferred errors" "No error,>=1 error" newline bitfld.quad 0x00 22. "PN,Poison" "Cannot distinguish,?..." bitfld.quad 0x00 20.--21. "UET,Uncorrected error type" "UC,?..." newline bitfld.quad 0x00 0.--4. "SERR,Primary error code" "No error,Reserved,Internal data buffer,Reserved,Reserved,Reserved,Cache data RAM,Cache tag/dirty RAM,TLB data RAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache copyback,Not supported,?..." group.quad spr:0x30544++0x00 line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register - ER0PFGF - Record 0" bitfld.quad 0x00 31. "PFG,Pseudo fault generation" "Reserved,Supported" bitfld.quad 0x00 30. "R,Restartable bit" "Reserved,Supported" newline bitfld.quad 0x00 6. "CE,Corrected error generation" "Reserved,Supported" bitfld.quad 0x00 5. "DE,Deferred error generation" "Reserved,Supported" newline bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..." bitfld.quad 0x00 3. "UER,Signalled or recoverable error generation" "Not supported,?..." newline bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,?..." bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Reserved,Supported" group.quad spr:0x30545++0x00 line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register - ER0PFGCTL - Record 0" bitfld.quad 0x00 31. "CDNEN,Countdown enable. Control transfers from the value that is held in the ERR0PFGCDN into the Error Generation Counter" "Disabled,Enabled" bitfld.quad 0x00 30. "R,Restart. Controls whether on reaching zero the Error Generation Counter restarts from the ext-CLUSTERRAS_ERR0PFGCDN value or stops" "Disabled,Enabled" newline bitfld.quad 0x00 6. "CE,Corrected error generation enable" "No error,Non-specific" bitfld.quad 0x00 5. "DE,Deferred error generation enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled" group.quad spr:0x30546++0x00 line.quad 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register - ER0PFGCDN_EL1 - Record 0" hexmask.quad.long 0x00 0.--31. 1. "CDN,Countdown value" group.quad spr:0x30543++0x00 line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register" bitfld.quad 0x00 63. "NS,Non-secure attribute" "Secure,Non-secure" hexmask.quad 0x00 0.--39. 1. "PADDR,Physical Address" group.quad spr:0x30550++0x00 line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0 - ER0MISC0_EL1 - Record 0" bitfld.quad 0x00 47. "OFO,Sticky overflow bit for other errors" "No overflow,Overflow" hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count for other errors" newline bitfld.quad 0x00 39. "OFR,Sticky overflow bit for repeat errors" "No overflow,Overflow" hexmask.quad.byte 0x00 32.--38. 1. "CECR,Corrected error count for repeat errors" newline bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 25. "SUBBANK,Dependent on unit from which error was detected" "0,1" newline bitfld.quad 0x00 23.--24. "BANK,Dependent on unit from which error was detected" "0,1,2,3" bitfld.quad 0x00 19.--22. "SUBARRAY,Dependent on unit from which error was detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.word 0x00 6.--18. 1. "INDEX,Indicates the index that contained the error" bitfld.quad 0x00 4.--5. "ARRAY,Dependent on unit from which error was detected" "L2 Tag RAM/LS Tag RAM 0/Tag,L2 Data RAM/LS Tag RAM1/Data,LS Data RAM/Micro-OP cache,CHI Error/LS Tag RAM 2" newline bitfld.quad 0x00 0.--3. "UNIT,Unit which detected error" "Reserved,L1 Instruction Cache,Reserved,Reserved,L1 Data Cache,L2 TLB,Reserved,Reserved,L2 Cache,?..." else rgroup.quad spr:0x30540++0x00 line.quad 0x00 "ERXFR_EL1,Selected Error Record Feature Register - CLUSTERRAS_ERR1FR - Record 1" bitfld.quad 0x00 18.--19. "CEO,Corrected error overwrite" "No overwrite,?..." bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..." newline bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented" bitfld.quad 0x00 12.--14. "CEC,Corrected error counter" "Reserved,Reserved,Implemented/8-bit,?..." newline bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..." newline bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 2.--3. "DE,Deferred error enable" "Reserved,Enabled,?..." bitfld.quad 0x00 0.--1. "ED,Error detection and correction[Lock/Split]" "Reserved,Reserved,Implemented,?..." group.quad spr:0x30541++0x00 line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register - CLUSTERRAS_ER1CTLR - Record 1" bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled" bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled" group.quad spr:0x30542++0x00 line.quad 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register - CLUSTERRAS_ER1STATUS - Record 1" bitfld.quad 0x00 31. "AV,Address valid" "Not valid,?..." bitfld.quad 0x00 30. "V,Status register valid" "Not valid,Valid" newline bitfld.quad 0x00 29. "UE,Uncorrected Error" "No error,>=1 error" bitfld.quad 0x00 28. "ER,Error reported" "No error,?..." newline bitfld.quad 0x00 27. "OF,Error overflow" "No error,>=1 error" bitfld.quad 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid" newline bitfld.quad 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..." bitfld.quad 0x00 23. "DE,Deferred errors" "No error,>=1 error" newline bitfld.quad 0x00 22. "PN,Poison" "Corrupt,Poison" bitfld.quad 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..." newline hexmask.quad.byte 0x00 8.--15. 1. "IERR,Implementation defined error code" hexmask.quad.byte 0x00 0.--7. 1. "SERR,Architecturally-defined primary error code" group.quad spr:0x30544++0x00 line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register - CLUSTERRAS_ER1PFGF - Record 1" bitfld.quad 0x00 31. "PFG,Pseudo fault generation" "Not supported,Supported" bitfld.quad 0x00 30. "R,Restartable bit" "Not supported,Supported" newline bitfld.quad 0x00 6. "CE,Corrected error generation" "Not supported,Supported" bitfld.quad 0x00 5. "DE,Deferred error generation" "Not supported,Supported" newline bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,Supported" bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,Supported" newline bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,Supported" bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Reserved,Supported" group.quad spr:0x30545++0x00 line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register - CLUSTERRAS_ER1PFGCTL - Record 1" bitfld.quad 0x00 31. "CDNEN,Countdown enable. Control transfers from the value that is held in the ERR0PFGCDN into the Error Generation Counter" "Disabled,Enabled" bitfld.quad 0x00 30. "R,Restart. Controls whether on reaching zero the Error Generation Counter restarts from the ext-CLUSTERRAS_ERR0PFGCDN value or stops" "Disabled,Enabled" newline bitfld.quad 0x00 6. "CE,Corrected error generation enable" "Disabled,Enabled" bitfld.quad 0x00 5. "DE,Deferred error generation enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled" group.quad spr:0x30546++0x00 line.quad 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register - CLUSTERRAS_ER1PFGCDN - Record 1" hexmask.quad.long 0x00 0.--31. 1. "CDN,Countdown value" group.quad spr:0x30550++0x00 line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0 - CLUSTERRAS_ER0MISC0 - Record 0 - DSU RAMs" bitfld.quad 0x00 47. "OFO,Sticky overflow bit for other errors" "No overflow,Overflow" hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count for other errors" newline bitfld.quad 0x00 39. "OFR,Sticky overflow bit for repeat errors" "No overflow,Overflow" hexmask.quad.byte 0x00 32.--38. 1. "CECR,Corrected error count for repeat errors" newline bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.tbyte 0x00 6.--23. 1. "INDX,Indicates the index that contained the error" newline bitfld.quad 0x00 1.--3. "LVL,Indicates the level that contained the error" "Reserved,Reserved,Level 3,?..." bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "Data,?..." group.quad spr:0x30551++0x00 line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1 - CLUSTERRAS_ER1MISC1 - Record 1" group.quad spr:0x30552++0x00 line.quad 0x00 "ERXMISC2_EL1,Selected Error Record Miscellaneous Register 2 - CLUSTERRAS_ER1MISC2 - Record 1" group.quad spr:0x30553++0x00 line.quad 0x00 "ERXMISC3_EL1,Selected Error Record Miscellaneous Register 3 - CLUSTERRAS_ER1MISC3 - Record 1" endif group.quad spr:0x30C11++0x00 line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register" bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.quad 0x00 24. "IDS,Indicates the deferred SError interrupt type" "Architecturally defined,?..." newline bitfld.quad 0x00 10.--12. "AET,Asynchronous error type" "UC,UEU,?..." bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 0.--5. "DFSC,Fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError,?..." group.quad spr:0x34523++0x00 line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register" bitfld.quad 0x00 24. "IDS,Indicates the deferred SError interrupt type" "Architecturally defined,?..." hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Implementation defined SError interrupt syndrome" group.quad spr:0x34C11++0x00 line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register" bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.quad 0x00 24. "IDS,Indicates the deferred SError interrupt type" "Architecturally defined,?..." newline hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Implementation defined SError interrupt syndrome" group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register (EL1)" group.quad spr:0x35600++0x00 line.quad 0x00 "FAR_EL12,Fault Address Register (EL12)" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register (EL2)" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register (EL3)" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad.long 0x00 4.--31. 0x10 "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register (EL1)" hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector base address" group.quad spr:0x35C00++0x00 line.quad 0x00 "VBAR_EL12,Vector Base Address Register (EL12)" hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector base address" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register (EL2)" hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector base address" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register (EL3)" hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector base address" rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" group.quad spr:0x36C02++0x00 line.quad 0x00 "RMR_EL3,Reset Management Register" bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested" rgroup.quad spr:0x30C10++0x00 line.quad 0x00 "ISR_EL1,Interrupt Status Register" bitfld.quad 0x00 8. "A,SError interrupt pending bit" "Not pending,Pending" bitfld.quad 0x00 7. "I,IRQ pending bit" "Not pending,Pending" newline bitfld.quad 0x00 6. "F,FIQ pending bit" "Not pending,Pending" group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register (EL1)" hexmask.quad.long 0x00 0.--31. 1. "PROCID,Process identifier" group.quad spr:0x35D01++0x00 line.quad 0x00 "CONTEXTIDR_EL12,Context ID Register (EL12)" hexmask.quad.long 0x00 0.--31. 1. "PROCID,Process identifier" group.quad spr:0x34D01++0x00 line.quad 0x00 "CONTEXTIDR_EL2,Context ID Register (EL2)" hexmask.quad.long 0x00 0.--31. 1. "PROCID,Process identifier" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID Register (EL0)" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Read-Only Software Thread ID Register (EL0)" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID Register (EL1)" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID Register (EL2)" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID Register (EL3)" tree.end tree "System Instructions" wgroup.quad spr:0x10710++0x00 line.quad 0x00 "IC_IALLUIS,IC_IALLUIS" wgroup.quad spr:0x10750++0x00 line.quad 0x00 "IC_IALLU,IC_IALLU" wgroup.quad spr:0x13751++0x00 line.quad 0x00 "IC_IVAU,IC_IVAU" wgroup.quad spr:0x13741++0x00 line.quad 0x00 "DC_ZVA,DC_ZVA" wgroup.quad spr:0x10761++0x00 line.quad 0x00 "DC_IVAC,DC_IVAC" wgroup.quad spr:0x10762++0x00 line.quad 0x00 "DC_ISW,DC_ISW" wgroup.quad spr:0x137A1++0x00 line.quad 0x00 "DC_CVAC,DC_CVAC" wgroup.quad spr:0x137C1++0x00 line.quad 0x00 "DC_CVAP,DC_CVAP" wgroup.quad spr:0x107A2++0x00 line.quad 0x00 "DC_CSW,DC_CSW" wgroup.quad spr:0x137B1++0x00 line.quad 0x00 "DC_CVAU,DC_CVAU" wgroup.quad spr:0x137E1++0x00 line.quad 0x00 "DC_CIVAC,DC_CIVAC" wgroup.quad spr:0x107E2++0x00 line.quad 0x00 "DC_CISW,DC_CISW" wgroup.quad spr:0x10780++0x00 line.quad 0x00 "AT_S1E1R,AT_S1E1R" wgroup.quad spr:0x10781++0x00 line.quad 0x00 "AT_S1E1W,AT_S1E1W" wgroup.quad spr:0x10782++0x00 line.quad 0x00 "AT_S1E0R,AT_S1E0R" wgroup.quad spr:0x10790++0x00 line.quad 0x00 "AT_S1E1RP,AT_S1E1RP" wgroup.quad spr:0x10791++0x00 line.quad 0x00 "AT_S1E1WP,AT_S1E1WP" wgroup.quad spr:0x10783++0x00 line.quad 0x00 "AT_S1E0W,AT_S1E0W" wgroup.quad spr:0x14784++0x00 line.quad 0x00 "AT_S12E1R,AT_S12E1R" wgroup.quad spr:0x14785++0x00 line.quad 0x00 "AT_S12E1W,AT_S12E1W" wgroup.quad spr:0x14786++0x00 line.quad 0x00 "AT_S12E0R,AT_S12E0R" wgroup.quad spr:0x14787++0x00 line.quad 0x00 "AT_S12E0W,AT_S12E0W" wgroup.quad spr:0x14780++0x00 line.quad 0x00 "AT_S1E2R,AT_S1E2R" wgroup.quad spr:0x14781++0x00 line.quad 0x00 "AT_S1E2W,AT_S1E2W" wgroup.quad spr:0x16780++0x00 line.quad 0x00 "AT_S1E3R,AT_S1E3R" wgroup.quad spr:0x16781++0x00 line.quad 0x00 "AT_S1E3W,AT_S1E3W" wgroup.quad spr:0x10870++0x00 line.quad 0x00 "TLBI_VMALLE1,TLBI_VMALLE1" wgroup.quad spr:0x10871++0x00 line.quad 0x00 "TLBI_VAE1,TLBI_VAE1" wgroup.quad spr:0x10872++0x00 line.quad 0x00 "TLBI_ASIDE1,TLBI_ASIDE1" wgroup.quad spr:0x10873++0x00 line.quad 0x00 "TLBI_VAAE1,TLBI_VAAE1" wgroup.quad spr:0x10875++0x00 line.quad 0x00 "TLBI_VALE1,TLBI_VALE1" wgroup.quad spr:0x10877++0x00 line.quad 0x00 "TLBI_VAALE1,TLBI_VAALE1" wgroup.quad spr:0x10830++0x00 line.quad 0x00 "TLBI_VMALLE1IS,TLBI_VMALLE1IS" wgroup.quad spr:0x10831++0x00 line.quad 0x00 "TLBI_VAE1IS,TLBI_VAE1IS" wgroup.quad spr:0x10832++0x00 line.quad 0x00 "TLBI_ASIDE1IS,TLBI_ASIDE1IS" wgroup.quad spr:0x10833++0x00 line.quad 0x00 "TLBI_VAAE1IS,TLBI_VAAE1IS" wgroup.quad spr:0x10835++0x00 line.quad 0x00 "TLBI_VALE1IS,TLBI_VALE1IS" wgroup.quad spr:0x10837++0x00 line.quad 0x00 "TLBI_VAALE1IS,TLBI_VAALE1IS" wgroup.quad spr:0x14801++0x00 line.quad 0x00 "TLBI_IPAS2E1IS,TLBI_IPAS2E1IS" wgroup.quad spr:0x14805++0x00 line.quad 0x00 "TLBI_IPAS2LE1IS,TLBI_IPAS2LE1IS" wgroup.quad spr:0x14841++0x00 line.quad 0x00 "TLBI_IPAS2E1,TLBI_IPAS2E1" wgroup.quad spr:0x14845++0x00 line.quad 0x00 "TLBI_IPAS2LE1,TLBI_IPAS2LE1" wgroup.quad spr:0x14871++0x00 line.quad 0x00 "TLBI_VAE2,TLBI_VAE2" wgroup.quad spr:0x14875++0x00 line.quad 0x00 "TLBI_VALE2,TLBI_VALE2" wgroup.quad spr:0x14876++0x00 line.quad 0x00 "TLBI_VMALLS12E1,TLBI_VMALLS12E1" wgroup.quad spr:0x14831++0x00 line.quad 0x00 "TLBI_VAE2IS,TLBI_VAE2IS" wgroup.quad spr:0x14835++0x00 line.quad 0x00 "TLBI_VALE2IS,TLBI_VALE2IS" wgroup.quad spr:0x14836++0x00 line.quad 0x00 "TLBI_VMALLS12E1IS,TLBI_VMALLS12E1IS" wgroup.quad spr:0x16871++0x00 line.quad 0x00 "TLBI_VAE3,TLBI_VAE3" wgroup.quad spr:0x16875++0x00 line.quad 0x00 "TLBI_VALE3,TLBI_VALE3" wgroup.quad spr:0x16831++0x00 line.quad 0x00 "TLBI_VAE3IS,TLBI_VAE3IS" wgroup.quad spr:0x16835++0x00 line.quad 0x00 "TLBI_VALE3IS,TLBI_VALE3IS" wgroup.quad spr:0x14870++0x00 line.quad 0x00 "TLBI_ALLE2,TLBI_ALLE2" wgroup.quad spr:0x14830++0x00 line.quad 0x00 "TLBI_ALLE2IS,TLBI_ALLE2IS" wgroup.quad spr:0x14874++0x00 line.quad 0x00 "TLBI_ALLE1,TLBI_ALLE1" wgroup.quad spr:0x14834++0x00 line.quad 0x00 "TLBI_ALLE1IS,TLBI_ALLE1IS" wgroup.quad spr:0x16870++0x00 line.quad 0x00 "TLBI_ALLE3,TLBI_ALLE3" wgroup.quad spr:0x16830++0x00 line.quad 0x00 "TLBI_ALLE3IS,TLBI_ALLE3IS" tree.end tree "Memory Management Unit" tree.open "Hypervisor System Register" group.quad spr:0x34113++0x00 line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.quad 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No effect,Trap" bitfld.quad 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No effect,Trap" bitfld.quad 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No effect,Trap" bitfld.quad 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No effect,Trap" newline bitfld.quad 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No effect,Trap" bitfld.quad 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No effect,Trap" bitfld.quad 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No effect,Trap" bitfld.quad 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No effect,Trap" newline bitfld.quad 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No effect,Trap" bitfld.quad 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No effect,Trap" bitfld.quad 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No effect,Trap" bitfld.quad 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No effect,Trap" newline bitfld.quad 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No effect,Trap" bitfld.quad 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No effect,Trap" group.quad spr:0x34117++0x00 line.quad 0x00 "HACR_EL2,Hypervisor Auxiliary Control Register" tree.end newline group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)" hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)" hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common" group.quad spr:0x35200++0x00 line.quad 0x00 "TTBR0_EL12,Translation Table Base Register 0 (EL12)" hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common" group.quad spr:0x35201++0x00 line.quad 0x00 "TTBR1_EL12,Translation Table Base Register 1 (EL12)" hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common" group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)" hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common" group.quad spr:0x34201++0x00 line.quad 0x00 "TTBR1_EL2,Translation Table Base Register 1 (EL2)" hexmask.quad.word 0x00 48.--63. 0x01 "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common" group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)" hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address" bitfld.quad 0x00 0. "CNP,Common not private" "Private,Common" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.word 0x00 48.--63. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 1.--47. 0x02 "BADDR[1:47],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Private,Common" group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)" bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage 1 translation table block or page entry for translations using TTBR1_EL1" "Not possible,Possible" bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage 1 translation table block or page entry for translations using TTBR1_EL1" "Not possible,Possible" newline bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage 1 translation table block or page entry for translations using TTBR1_EL1" "Not possible,Possible" bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage 1 translation table block or page entry for translations using TTBR1_EL1" "Not possible,Possible" newline bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage 1 translation table block or page entry for translations using TTBR0_EL1" "Not possible,Possible" bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage 1 translation table block or page entry for translations using TTBR0_EL1" "Not possible,Possible" newline bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage 1 translation table block or page entry for translations using TTBR0_EL1" "Not possible,Possible" bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage 1 translation table block or page entry for translations using TTBR0_EL1" "Not possible,Possible" newline bitfld.quad 0x00 42. "HPD1,Hierarchical permission disable for the TTBR1 region" "No,Yes" bitfld.quad 0x00 41. "HPD0,Hierarchical permission disable for the TTBR0 region" "No,Yes" newline bitfld.quad 0x00 40. "HD,Hardware management of dirty state in stage 1 translations" "Disabled,Enabled" bitfld.quad 0x00 39. "HA,Hardware Access flag update in stage 1 translations" "Disabled,Enabled" newline bitfld.quad 0x00 38. "TBI1,Top Byte ignored. Indicates whether the top byte of an address is used for address match for the TTBR1_EL1 region or ignored and used for tagged addresses" "Used,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte ignored. Indicates whether the top byte of an address is used for address match for the TTBR0_EL1 region or ignored and used for tagged addresses" "Used,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8 bit,16 bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate physical address size" "32-bit/4GB,36-bit/64GB,40-bit/1TB,42-bit/4TB,44-bit/16TB,48-bit/256TB,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,16KB,4KB,64KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1_EL1" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attributes for TTBR1_EL1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attributes for TTBR1_EL1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for TTBR1_EL1 as described in LPAE" "No,Yes" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1 The region size is 2^(64-T1SZ) bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4KB,64KB,16KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0_EL1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for TTBR0_EL1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for TTBR0_EL1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 7. "EPD0,Translation table walk disable for TTBR0_EL1 as described in LPAE" "No,Yes" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1 The region size is 2^(64-T0SZ) bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x35202++0x00 line.quad 0x00 "TCR_EL12,Translation Control Register (EL12)" bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage 1 translation table block or page entry for translations using TTBR1_EL1" "Not possible,Possible" bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage 1 translation table block or page entry for translations using TTBR1_EL1" "Not possible,Possible" newline bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage 1 translation table block or page entry for translations using TTBR1_EL1" "Not possible,Possible" bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage 1 translation table block or page entry for translations using TTBR1_EL1" "Not possible,Possible" newline bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage 1 translation table block or page entry for translations using TTBR0_EL1" "Not possible,Possible" bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage 1 translation table block or page entry for translations using TTBR0_EL1" "Not possible,Possible" newline bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage 1 translation table block or page entry for translations using TTBR0_EL1" "Not possible,Possible" bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage 1 translation table block or page entry for translations using TTBR0_EL1" "Not possible,Possible" newline bitfld.quad 0x00 42. "HPD1,Hierarchical permission disable for the TTBR1 region" "No,Yes" bitfld.quad 0x00 41. "HPD0,Hierarchical permission disable for the TTBR0 region" "No,Yes" newline bitfld.quad 0x00 40. "HD,Hardware management of dirty state in stage 1 translations" "Disabled,Enabled" bitfld.quad 0x00 39. "HA,Hardware Access flag update in stage 1 translations" "Disabled,Enabled" newline bitfld.quad 0x00 38. "TBI1,Top Byte ignored. Indicates whether the top byte of an address is used for address match for the TTBR1_EL1 region or ignored and used for tagged addresses" "Used,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte ignored. Indicates whether the top byte of an address is used for address match for the TTBR0_EL1 region or ignored and used for tagged addresses" "Used,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8 bit,16 bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate physical address size" "32-bit/4GB,36-bit/64GB,40-bit/1TB,42-bit/4TB,44-bit/16TB,48-bit/256TB,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,16KB,4KB,64KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1_EL1" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attributes for TTBR1_EL1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attributes for TTBR1_EL1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for TTBR1_EL1 as described in LPAE" "No,Yes" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1 The region size is 2^(64-T1SZ) bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4KB,64KB,16KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0_EL1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for TTBR0_EL1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for TTBR0_EL1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 7. "EPD0,Translation table walk disable for TTBR0_EL1 as described in LPAE" "No,Yes" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1 The region size is 2^(64-T0SZ) bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.q(spr:0x34110))&0x400000000)==0x000000000) group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 28. "HWU62,Hardware use of bit[62] of the stage 1 translation table block or page entry" "Not possible,Possible" bitfld.quad 0x00 27. "HWU61,Hardware use of bit[61] of the stage 1 translation table block or page entry" "Not possible,Possible" newline bitfld.quad 0x00 26. "HWU60,Hardware use of bit[60] of the stage 1 translation table block or page entry" "Not possible,Possible" bitfld.quad 0x00 25. "HWU59,Hardware use of bit[59] of the stage 1 translation table block or page entry" "Not possible,Possible" newline bitfld.quad 0x00 24. "HPD,Hierarchical permission disable" "No,Yes" bitfld.quad 0x00 22. "HD,Hardware management of dirty state in stage 1 translations" "Disabled,Enabled" newline bitfld.quad 0x00 21. "HA,Hardware Access flag update in stage 1 translations" "Disabled,Enabled" bitfld.quad 0x00 20. "TBI,Top Byte ignored. Indicates whether the top byte of an address is used for address match for the TTBR0_EL2 region or ignored and used for tagged addresses" "Used,Ignored" newline bitfld.quad 0x00 16.--18. "PS,Physical address size" "32-bit/4GB,36-bit/64GB,40-bit/1TB,42-bit/4TB,44-bit/16TB,48-bit/256TB,?..." bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4KB,64KB,16KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for TTBR0_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for TTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2 The region size is 2^(64-T0SZ) bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)" bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage 1 translation table block or page entry for translations using TTBR1_EL2" "Not possible,Possible" bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage 1 translation table block or page entry for translations using TTBR1_EL2" "Not possible,Possible" newline bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage 1 translation table block or page entry for translations using TTBR1_EL2" "Not possible,Possible" bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage 1 translation table block or page entry for translations using TTBR1_EL2" "Not possible,Possible" newline bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage 1 translation table block or page entry for translations using TTBR0_EL2" "Not possible,Possible" bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage 1 translation table block or page entry for translations using TTBR0_EL2" "Not possible,Possible" newline bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage 1 translation table block or page entry for translations using TTBR0_EL2" "Not possible,Possible" bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage 1 translation table block or page entry for translations using TTBR0_EL2" "Not possible,Possible" newline bitfld.quad 0x00 42. "HPD1,Hierarchical permission disable for the TTBR1_EL2 region" "No,Yes" bitfld.quad 0x00 41. "HPD0,Hierarchical Permission Disable for the TTBR0_EL2 region" "No,Yes" newline bitfld.quad 0x00 40. "HD,Hardware management of dirty state in stage 1 translations" "Disabled,Enabled" bitfld.quad 0x00 39. "HA,Hardware Access flag update in stage 1 translations" "Disabled,Enabled" newline bitfld.quad 0x00 38. "TBI1,Top Byte ignored. Indicates whether the top byte of an address is used for address match for the TTBR1_EL2 region or ignored and used for tagged addresses" "Used,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte ignored. Indicates whether the top byte of an address is used for address match for the TTBR0_EL2 region or ignored and used for tagged addresses" "Used,Ignored" newline bitfld.quad 0x00 36. "AS,ASID size" "8 bit,16 bit" bitfld.quad 0x00 32.--34. "IPS,Intermediate physical address size" "32-bit/4GB,36-bit/64GB,40-bit/1TB,42-bit/4TB,44-bit/16TB,48-bit/256TB,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,16KB,4KB,64KB" bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1_EL2 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attributes for TTBR1_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attributes for TTBR1_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation table walk disable for TTBR1_EL2 as described in LPAE" "No,Yes" bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL2 or TTBR1_EL2 defines the ASID" "TTBR0_EL2,TTBR1_EL2" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1_EL2 The region size is 2^(64-T1SZ) bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4KB,64KB,16KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0_EL2 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for TTBR0_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for TTBR0_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 7. "EPD0,Translation table walk disable for TTBR0_EL2 as described in LPAE" "No,Yes" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0_EL2 The region size is 2^(64-T0SZ) bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)" bitfld.quad 0x00 28. "HWU62,Hardware use of bit[62] of the stage 1 translation table block or page entry" "Not possible,Possible" bitfld.quad 0x00 27. "HWU61,Hardware use of bit[61] of the stage 1 translation table block or page entry" "Not possible,Possible" newline bitfld.quad 0x00 26. "HWU60,Hardware use of bit[60] of the stage 1 translation table block or page entry" "Not possible,Possible" bitfld.quad 0x00 25. "HWU59,Hardware use of bit[59] of the stage 1 translation table block or page entry" "Not possible,Possible" newline bitfld.quad 0x00 24. "HPD,Hierarchical permission disable" "No,Yes" bitfld.quad 0x00 22. "HD,Hardware management of dirty state in stage 1 translations" "Disabled,Enabled" newline bitfld.quad 0x00 21. "HA,Hardware Access flag update in stage 1 translations" "Disabled,Enabled" bitfld.quad 0x00 20. "TBI,Top Byte ignored. Indicates whether the top byte of an address is used for address match for the TTBR0_EL3 region or ignored and used for tagged addresses" "Used,Ignored" newline bitfld.quad 0x00 16.--18. "PS,Physical address size" "32-bit/4GB,36-bit/64GB,40-bit/1TB,42-bit/4TB,44-bit/16TB,48-bit/256TB,?..." bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4KB,64KB,16KB,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0_EL3 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for TTBR0_EL3 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for TTBR0_EL3 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3. The region size is 2^(64-T0SZ) bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 28. "HWU62,Hardware use of bit[62] of the stage 2 translation table block or page entry" "Not possible,Possible" bitfld.quad 0x00 27. "HWU61,Hardware use of bit[61] of the stage 2 translation table block or page entry" "Not possible,Possible" newline bitfld.quad 0x00 26. "HWU60,Hardware use of bit[60] of the stage 2 translation table block or page entry" "Not possible,Possible" bitfld.quad 0x00 25. "HWU59,Hardware use of bit[59] of the stage 2 translation table block or page entry" "Not possible,Possible" newline bitfld.quad 0x00 22. "HD,Hardware management of dirty state in stage 2 translations" "Disabled,Enabled" bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 2" "Disabled,Enabled" newline bitfld.quad 0x00 19. "VS,VMID size" "8 bit,16 bit" bitfld.quad 0x00 16.--18. "PS,Physical address size for the second stage of translation" "32-bit/4GB,36-bit/64GB,40-bit/1TB,42-bit/4TB,44-bit/16TB,48-bit/256TB,?..." newline bitfld.quad 0x00 14.--15. "TG0,VTTBR_EL2 granule size" "4KB,64KB,16KB,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT no WA cacheable,Outer WB no WA cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT no WA cacheable,Inner WB no WA cacheable" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by VTTBR_EL2 The region size is 2^(64-T0SZ) bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA" hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure translation regime" "No,Yes" newline bitfld.quad 0x00 7.--8. "SH,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif newline tree.open "Memory Attribute Indirection Registers" group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x35A20++0x00 line.quad 0x00 "MAIR_EL12,Memory Attribute Indirection Register (EL12)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x30A30++0x00 line.quad 0x00 "AMAIR_EL1,Auxiliary Memory Attribute Indirection Register (EL1)" group.quad spr:0x35A30++0x00 line.quad 0x00 "AMAIR_EL12,Auxiliary Memory Attribute Indirection Register (EL12)" group.quad spr:0x34A30++0x00 line.quad 0x00 "AMAIR_EL2,Auxiliary Memory Attribute Indirection Register (EL2)" group.quad spr:0x36A30++0x00 line.quad 0x00 "AMAIR_EL3,Auxiliary Memory Attribute Indirection Register (EL3)" tree.end newline group.quad spr:0x34300++0x00 line.quad 0x00 "DACR32_EL2,Domain Access Control Register" tree.end tree "Virtualization Extensions" group.quad spr:0x34111++0x00 line.quad 0x00 "MDCR_EL2,Monitor Debug Configuration Register (EL2)" bitfld.quad 0x00 17. "HPMD,Guest Performance Monitors disable" "No,Yes" bitfld.quad 0x00 11. "TDRA,Trap debug ROM address register access" "Not trapped,Trapped" bitfld.quad 0x00 10. "TDOSA,Trap debug OS-related register access" "Not trapped,Trapped" newline bitfld.quad 0x00 9. "TDA,Trap debug access" "Not trapped,Trapped" bitfld.quad 0x00 8. "TDE,Route debug exceptions from Non-secure EL1 and EL0 to EL2" "Disabled,Enabled" bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors enable" "Disabled,Enabled" bitfld.quad 0x00 6. "TPM,Trap Performance Monitors accesses" "Not trapped,Trapped" newline bitfld.quad 0x00 5. "TPMCR,Trap PMCR_EL0 or PMCR accesses" "Not trapped,Trapped" bitfld.quad 0x00 0.--4. "HPMN,Defines the number of event counters that are accessible from EL3/EL2/EL1 and from EL0 if permitted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.quad spr:0x36131++0x00 line.quad 0x00 "MDCR_EL3,Monitor Debug Configuration Register (EL3)" bitfld.quad 0x00 21. "EPMAD,External debugger register access disable" "No,Yes" bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" newline bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.quad 0x00 16. "SDD,Secure (monitor) debug disable" "No,Yes" newline bitfld.quad 0x00 10. "TDOSA,Trap valid accesses to OS-related debug registers to EL3" "No effect,Trapped" bitfld.quad 0x00 9. "TDA,Trap valid Non-secure accesses to Debug registers to EL3" "No effect,Trapped" bitfld.quad 0x00 6. "TPM,Trap Non-secure EL0/EL1/EL2 accesses to Performance Monitors registers that are not UNALLOCATED or trapped to a lower exception level to EL3" "No effect,Trapped" rgroup.quad spr:0x30012++0x00 line.quad 0x00 "ID_DFR0_EL1,AArch32 Debug Feature Register 0" bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model support" "Reserved,Reserved,Reserved,Reserved,PMUv3,?..." bitfld.quad 0x00 20.--23. "M_PROF_DBG,M Profile Debug support" "Not supported,?..." bitfld.quad 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) support" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model support" "Not supported,?..." bitfld.quad 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..." bitfld.quad 0x00 0.--3. "CDM_CB,Coprocessor Debug Model support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..." tree.end tree "Cache Control And Configuration" rgroup.quad spr:0x33001++0x00 line.quad 0x00 "CTR_EL0,Cache Type Register" bitfld.quad 0x00 28. "IDC,Data cache clean requirements for instruction to data coherence" "Required,Not required" bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,64 bytes,?..." newline bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,64 bytes,?..." bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,64 bytes,?..." newline bitfld.quad 0x00 14.--15. "L1IP,Level 1 instruction cache policy" "Reserved,Reserved,Reserved,PIPT" bitfld.quad 0x00 0.--3. "IMINLINE,Smallest instruction cache line size" "Reserved,Reserved,Reserved,Reserved,64 bytes,?..." group.quad spr:0x32000++0x00 line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register" bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..." bitfld.quad 0x00 0. "IND,Instruction/Not data" "Data/Unified,Instruction" rgroup.quad spr:0x31000++0x00 line.quad 0x00 "CCSIDR_EL1,Cache Size And ID Register" bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,?..." bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported" newline bitfld.quad 0x00 29. "RA,Read-Allocate" "Not Supported,Supported" bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported" newline hexmask.quad.word 0x00 13.--27. 1. 1. "NUMSETS,Number of sets" hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOCIATIVITY,Associativity" newline bitfld.quad 0x00 0.--2. "LINESIZE,Line size" "16 bytes,32 bytes,64 bytes,128 bytes,?..." rgroup.quad spr:0x31001++0x00 line.quad 0x00 "CLIDR_EL1,Cache Level ID Register" bitfld.quad 0x00 30.--32. "ICB,Inner cache boundary" "Reserved,Reserved,Level 2,Level 3,?..." bitfld.quad 0x00 27.--29. "LOUU,Level of unification uniprocessor" "Clean/Invalidate not required,?..." bitfld.quad 0x00 24.--26. "LOC,Level 3 of coherency" "Reserved,Reserved,Not implemented,Implemented,?..." newline bitfld.quad 0x00 21.--23. "LOUIS,Level of unification inner shareable" "Clean/Invalidate not required,?..." bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "Not implemented,Reserved,Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified cache,?..." bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate instruction,?..." tree.end tree "System Performance Monitor" group.quad spr:0x339C0++0x00 line.quad 0x00 "PMCR_EL0,Performance Monitors Control Register" hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code" newline bitfld.quad 0x00 11.--15. "N,Number of event counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.quad 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "DP,Disable cycle counter when event counting is prohibited" "No,Yes" bitfld.quad 0x00 4. "X,Export of events enable" "Disabled,Enabled" bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" newline bitfld.quad 0x00 2. "C,Cycle Counter reset" "No effect,Reset" bitfld.quad 0x00 1. "P,Event Counter reset" "No effect,Reset" bitfld.quad 0x00 0. "E,All Counters enable" "Disabled,Enabled" if (((per.q(spr:0x339C0))&0xF800)==0x3000) group.quad spr:0x339C1++0x00 line.quad 0x00 "PMCNTENSET_EL0,Performance Monitors Count Enable Set Register" bitfld.quad 0x00 31. "C,Cycle counter register PMCCNTR_EL0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.quad 0x00 5. "P5,Event counter PMEVCNTR5_EL0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 4. "P4,Event counter PMEVCNTR4_EL0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 3. "P3,Event counter PMEVCNTR3_EL0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.quad 0x00 2. "P2,Event counter PMEVCNTR2_EL0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 1. "P1,Event counter PMEVCNTR1_EL0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 0. "P0,Event counter PMEVCNTR0_EL0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" group.quad spr:0x339C2++0x00 line.quad 0x00 "PMCNTENCLR_EL0,Performance Monitors Count Enable Clear Register" bitfld.quad 0x00 31. "C,Cycle counter register PMCCNTR_EL0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline bitfld.quad 0x00 5. "P5,Event counter PMEVCNTR5_EL0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 4. "P4,Event counter PMEVCNTR4_EL0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 3. "P3,Event counter PMEVCNTR3_EL0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline bitfld.quad 0x00 2. "P2,Event counter PMEVCNTR2_EL0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 1. "P1,Event counter PMEVCNTR1_EL0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 0. "P0,Event counter PMEVCNTR0_EL0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x339C3++0x00 line.quad 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Status Flags Clear Register" eventfld.quad 0x00 31. "C,Cycle counter register PMCCNTR_EL0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.quad 0x00 5. "P5,Event counter PMEVCNTR5_EL0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 4. "P4,Event counter PMEVCNTR4_EL0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 3. "P3,Event counter PMEVCNTR3_EL0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.quad 0x00 2. "P2,Event counter PMEVCNTR2_EL0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 1. "P1,Event counter PMEVCNTR1_EL0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 0. "P0,Event counter PMEVCNTR0_EL0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" wgroup.quad spr:0x339C4++0x00 line.quad 0x00 "PMSWINC_EL0,Performance Monitors Software Increment Register" bitfld.quad 0x00 5. "P5,Event counter PMEVCNTR5_EL0 software increment bit" "No effect,Increment" bitfld.quad 0x00 4. "P4,Event counter PMEVCNTR4_EL0 software increment bit" "No effect,Increment" bitfld.quad 0x00 3. "P3,Event counter PMEVCNTR3_EL0 software increment bit" "No effect,Increment" newline bitfld.quad 0x00 2. "P2,Event counter PMEVCNTR2_EL0 software increment bit" "No effect,Increment" bitfld.quad 0x00 1. "P1,Event counter PMEVCNTR1_EL0 software increment bit" "No effect,Increment" bitfld.quad 0x00 0. "P0,Event counter PMEVCNTR0_EL0 software increment bit" "No effect,Increment" group.quad spr:0x339C5++0x00 line.quad 0x00 "PMSELR_EL0,Performance Monitors Event Counter Selection Register" bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,31" else group.quad spr:0x339C1++0x00 line.quad 0x00 "PMCNTENSET_EL0,Performance Monitors Count Enable Set Register" bitfld.quad 0x00 31. "C,Cycle counter register PMCCNTR_EL0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" group.quad spr:0x339C2++0x00 line.quad 0x00 "PMCNTENCLR_EL0,Performance Monitors Count Enable Clear Register" bitfld.quad 0x00 31. "C,Cycle counter register PMCCNTR_EL0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x339C3++0x00 line.quad 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Status Flags Clear Register" eventfld.quad 0x00 31. "C,Cycle counter register PMCCNTR_EL0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" rgroup.quad spr:0x339C4++0x00 line.quad 0x00 "PMSWINC_EL0,Performance Monitors Software Increment Register" group.quad spr:0x339C5++0x00 line.quad 0x00 "PMSELR_EL0,Performance Monitors Event Counter Selection Register" bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,31" endif tree.open "Common Event Identification Registers" rgroup.quad spr:0x339C6++0x00 line.quad 0x00 "PMCEID0_EL0,Performance Monitors Common Event Identification Register 0" bitfld.quad 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,?..." bitfld.quad 0x00 30. "CHAIN,Chain" "Reserved,Implemented" bitfld.quad 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented" newline bitfld.quad 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Reserved,Implemented" bitfld.quad 0x00 27. "INST_SPEC,Instruction speculatively executed" "Reserved,Implemented" bitfld.quad 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented" newline bitfld.quad 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented" bitfld.quad 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Reserved,Implemented" bitfld.quad 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Reserved,Implemented" newline bitfld.quad 0x00 22. "L2D_CACHE,Level 2 data cache access" "Reserved,Implemented" bitfld.quad 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Reserved,Implemented" bitfld.quad 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Reserved,Implemented" newline bitfld.quad 0x00 19. "MEM_ACCESS,Data memory access" "Reserved,Implemented" bitfld.quad 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Reserved,Implemented" bitfld.quad 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented" newline bitfld.quad 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented" bitfld.quad 0x00 15. "UNALIGNED_LDST_RETIRED,UNALIGNED_LDST_RETIRED" "Not implemented,?..." bitfld.quad 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,?..." newline bitfld.quad 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,?..." bitfld.quad 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,?..." bitfld.quad 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented" newline bitfld.quad 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented" bitfld.quad 0x00 9. "EXC_TAKEN,Exception taken" "Reserved,Implemented" bitfld.quad 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Reserved,Implemented" newline bitfld.quad 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,?..." bitfld.quad 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,?..." bitfld.quad 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Reserved,Implemented" newline bitfld.quad 0x00 4. "L1D_CACHE,Level 1 data cache access" "Reserved,Implemented" bitfld.quad 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Reserved,Implemented" bitfld.quad 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Reserved,Implemented" newline bitfld.quad 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Reserved,Implemented" bitfld.quad 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented" rgroup.quad spr:0x339C7++0x00 line.quad 0x00 "PMCEID1_EL0,Performance Monitors Common Event Identification Register 1" bitfld.quad 0x00 23. "LL_CACHE_MISS_RD,Attributable last level cache memory read miss" "Reserved,Implemented" newline bitfld.quad 0x00 22. "LL_CACHE_RD,Attributable last level cache memory read" "Reserved,Implemented" bitfld.quad 0x00 21. "ITLB_WLK,Attributable instruction TLB access with at least one translation table walk" "Reserved,Implemented" bitfld.quad 0x00 20. "DTLB_WLK,Attributable data or unified TLB access with at least one translation table walk" "Reserved,Implemented" newline bitfld.quad 0x00 17. "REMOTE_ACCESS,Attributable access to another socket in a multi-socket system" "Reserved,Implemented" bitfld.quad 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Reserved,Implemented" newline bitfld.quad 0x00 14. "L2I_TLB_REFILL,Attributable Level 2 instruction TLB refill" "Not implemented,?..." bitfld.quad 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Reserved,Implemented" bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Reserved,Implemented" newline bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Reserved,Implemented" bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented" newline bitfld.quad 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Reserved,Implemented" bitfld.quad 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Reserved,Implemented" newline bitfld.quad 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Reserved,Implemented" bitfld.quad 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Reserved,Implemented" bitfld.quad 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Reserved,Implemented" newline bitfld.quad 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Reserved,Implemented" bitfld.quad 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Reserved,Implemented" tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitors Cycle Count Register" if (((per.q(spr:0x339C5))&0x1F)==0x1F) group.quad spr:0x339D1++0x00 line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitors Selected Event Type Register - PMCCFILTR_EL0" bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3 [P=0/1]" "Yes/No,No/Yes" else group.quad spr:0x339D1++0x00 line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitors Selected Event Type Register - PMEVTYPER_EL0" bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3 [P=0/1]" "Yes/No,No/Yes" newline hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event to count" endif group.quad spr:0x339D2++0x00 line.quad 0x00 "PMXEVCNTR_EL0,Performance Monitors Selected Event Counter Register" group.quad spr:0x339E0++0x00 line.quad 0x00 "PMUSERENR_EL0,Performance Monitors User Enable Register" bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.quad 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,EL0 access enable bit" "Disabled,Enabled" group.quad spr:0x309E1++0x00 line.quad 0x00 "PMINTENSET_EL1,Performance Monitors Interrupt Enable Set Register" bitfld.quad 0x00 31. "C,Cycle counter register PMCCNTR_EL0 overflow interrupt request enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.quad 0x00 5. "P5,Event counter PMEVCNTR5_EL0 overflow interrupt request enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 4. "P4,Event counter PMEVCNTR4_EL0 overflow interrupt request enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 3. "P3,Event counter PMEVCNTR3_EL0 overflow interrupt request enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.quad 0x00 2. "P2,Event counter PMEVCNTR2_EL0 overflow interrupt request enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 1. "P1,Event counter PMEVCNTR1_EL0 overflow interrupt request enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 0. "P0,Event counter PMEVCNTR0_EL0 overflow interrupt request enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" group.quad spr:0x309E2++0x00 line.quad 0x00 "PMINTENCLR_EL1,Performance Monitors Interrupt Enable Clear Register" eventfld.quad 0x00 31. "C,Cycle counter register PMCCNTR_EL0 overflow interrupt request disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.quad 0x00 5. "P5,Event counter PMEVCNTR5_EL0 overflow interrupt request disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 4. "P4,Event counter PMEVCNTR4_EL0 overflow interrupt request disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 3. "P3,Event counter PMEVCNTR3_EL0 overflow interrupt request disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.quad 0x00 2. "P2,Event counter PMEVCNTR2_EL0 overflow interrupt request disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 1. "P1,Event counter PMEVCNTR1_EL0 overflow interrupt request disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 0. "P0,Event counter PMEVCNTR0_EL0 overflow interrupt request disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x339E3++0x00 line.quad 0x00 "PMOVSSET_EL0,Performance Monitors Overflow Status Flags Set Register" bitfld.quad 0x00 31. "C,Cycle counter overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" newline bitfld.quad 0x00 5. "P5,Event counter PMEVCNTR5_EL0 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" bitfld.quad 0x00 4. "P4,Event counter PMEVCNTR4_EL0 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" bitfld.quad 0x00 3. "P3,Event counter PMEVCNTR3_EL0 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" newline bitfld.quad 0x00 2. "P2,Event counter PMEVCNTR2_EL0 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" bitfld.quad 0x00 1. "P1,Event counter PMEVCNTR1_EL0 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" bitfld.quad 0x00 0. "P0,Event counter PMEVCNTR0_EL0 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" group.quad spr:(0x33E80+0x0)++0x00 line.quad 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0" group.quad spr:(0x33E80+0x1)++0x00 line.quad 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1" group.quad spr:(0x33E80+0x2)++0x00 line.quad 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2" group.quad spr:(0x33E80+0x3)++0x00 line.quad 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3" group.quad spr:(0x33E80+0x4)++0x00 line.quad 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4" group.quad spr:(0x33E80+0x5)++0x00 line.quad 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5" group.quad spr:(0x33EC0+0x0)++0x00 line.quad 0x00 "PMEVTYPER0_EL0,Performance Monitors Event Type Register 0" bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event number" group.quad spr:(0x33EC0+0x1)++0x00 line.quad 0x00 "PMEVTYPER1_EL0,Performance Monitors Event Type Register 1" bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event number" group.quad spr:(0x33EC0+0x2)++0x00 line.quad 0x00 "PMEVTYPER2_EL0,Performance Monitors Event Type Register 2" bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event number" group.quad spr:(0x33EC0+0x3)++0x00 line.quad 0x00 "PMEVTYPER3_EL0,Performance Monitors Event Type Register 3" bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event number" group.quad spr:(0x33EC0+0x4)++0x00 line.quad 0x00 "PMEVTYPER4_EL0,Performance Monitors Event Type Register 4" bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event number" group.quad spr:(0x33EC0+0x5)++0x00 line.quad 0x00 "PMEVTYPER5_EL0,Performance Monitors Event Type Register 5" bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,Event number" group.quad spr:0x33EF7++0x00 line.quad 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register" bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" tree.end tree "System Timer Registers" group.quad spr:0x33E00++0x00 line.quad 0x00 "CNTFRQ_EL0,Counter-timer Frequency Register" hexmask.quad.long 0x00 0.--31. 1. "CF,Clock frequency" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter-timer Physical Count Register" rgroup.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter-timer Virtual Count Register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter-timer Virtual Offset Register" group.quad spr:0x30E10++0x00 line.quad 0x00 "CNTKCTL_EL1,Counter-timer Kernel Control Register" bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled" newline bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter CNTVCT and the frequency register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter CNTPCT and the frequency register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled" group.quad spr:0x35E10++0x00 line.quad 0x00 "CNTKCTL_EL12,Counter-timer Kernel Control Register" bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled" newline bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter CNTVCT and the frequency register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter CNTPCT and the frequency register CNTFRQ are accessible from EL0 mode" "Disabled,Enabled" if (((per.q(spr:0x34110))&0x400000000)==0x400000000) group.quad spr:0x34E10++0x00 line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control Register" bitfld.quad 0x00 11. "EL1PTEN,Physical timer register accessing instructions are accessible from Non-secure EL1 and EL0" "Not accessible,Accessible" bitfld.quad 0x00 10. "EL1PCTEN,Physical counter is accessible from Non-secure EL1 and EL0" "Not accessible,Accessible" newline bitfld.quad 0x00 9. "EL0PTEN,Physical timer register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible" bitfld.quad 0x00 8. "EL0VTEN,Virtual timer register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible" newline bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Virtual counter register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible" newline bitfld.quad 0x00 0. "EL0PCTEN,Physical counter is accessible from Non-secure EL0 modes" "Not accessible,Accessible" else group.quad spr:0x34E10++0x00 line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control Register" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI generates an event when the event stream is enabled" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL1PCEN,Physical timer register is accessible from Non-secure EL1 and EL0" "Not accessible,Accessible" newline bitfld.quad 0x00 0. "EL1PCTEN,Physical counter register is accessible from Non-secure EL1 and EL0" "Not accessible,Accessible" endif group.quad spr:0x33E20++0x00 line.quad 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL1 physical timer" group.quad spr:0x35E20++0x00 line.quad 0x00 "CNTP_TVAL_EL02,Counter-timer Physical Timer TimerValue Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL1 physical timer" group.quad spr:0x33E21++0x00 line.quad 0x00 "CNTP_CTL_EL0,Counter-timer Physical Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x35E21++0x00 line.quad 0x00 "CNTP_CTL_EL02,Counter-timer Physical Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter-timer Physical Timer CompareValue Register" group.quad spr:0x35E22++0x00 line.quad 0x00 "CNTP_CVAL_EL02,Counter-timer Physical Timer CompareValue Register" group.quad spr:0x33E30++0x00 line.quad 0x00 "CNTV_TVAL_EL0,Counter-timer Virtual Timer TimerValue Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL1 virtual timer" group.quad spr:0x35E30++0x00 line.quad 0x00 "CNTV_TVAL_EL02,Counter-timer Virtual Timer TimerValue Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL1 virtual timer" group.quad spr:0x33E31++0x00 line.quad 0x00 "CNTV_CTL_EL0,Counter-timer Virtual Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x35E31++0x00 line.quad 0x00 "CNTV_CTL_EL02,Counter-timer Virtual Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter-timer Virtual Timer CompareValue Register" group.quad spr:0x35E32++0x00 line.quad 0x00 "CNTV_CVAL_EL02,Counter-timer Virtual Timer CompareValue Register" group.quad spr:0x34E20++0x00 line.quad 0x00 "CNTHP_TVAL_EL2,Counter-timer Hypervisor Physical Timer TimerValue Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL2 physical timer" group.quad spr:0x34E21++0x00 line.quad 0x00 "CNTHP_CTL_EL2,Counter-timer Hypervisor Physical Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter-timer Hypervisor Physical Timer CompareValue Register" group.quad spr:0x34E30++0x00 line.quad 0x00 "CNTHV_TVAL_EL2,Counter-timer Hypervisor Virtual Timer Value Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL2 virtual timer" group.quad spr:0x34E31++0x00 line.quad 0x00 "CNTHV_CTL_EL2,Counter-timer Hypervisor Virtual Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E32++0x00 line.quad 0x00 "CNTHV_CVAL_EL2,Counter-Timer Hypervisor Virtual Timer CompareValue Register" group.quad spr:0x37E20++0x00 line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical Secure Timer TimerValue Register" hexmask.quad.long 0x00 0.--31. 1. "TV,TimerValue view of the EL2 physical timer" group.quad spr:0x37E21++0x00 line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control Register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue Register" tree.end tree "Generic Interrupt Controller CPU Interface" tree "AArch64 GIC Physical CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)" bitfld.quad 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.quad 0x00 27. "[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.quad 0x00 26. "[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.quad 0x00 23. "[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.quad 0x00 21. "[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.quad 0x00 19. "[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.quad 0x00 16. "[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.quad 0x00 15. "[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.quad 0x00 7. "[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.quad 0x00 6. "[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.quad 0x00 3. "[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)" bitfld.quad 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.quad 0x00 27. "[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.quad 0x00 26. "[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.quad 0x00 23. "[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.quad 0x00 21. "[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.quad 0x00 19. "[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.quad 0x00 16. "[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.quad 0x00 15. "[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.quad 0x00 7. "[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.quad 0x00 6. "[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.quad 0x00 3. "[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline if (((per.q(spr:0x30CB6))&0x10000000000)==0x00) wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register (EL1)" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register (EL1)" bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0 (EL1)" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt priority field control and interrupt preemption control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1 (EL1)" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt priority field control and interrupt preemption control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)" rbitfld.quad 0x00 15. "A3V,Affinity 3 valid" "Reserved,Non-zero" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..." rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5 bits (32 levels),?..." bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask register is used as a hint for interrupt distribution" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an end of interrupt register also deactivates the interrupt" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CBPR,Controls whether the same register is used for interrupt preemption of both group 0 and group 1 interrupts" "Separate registers,Same register" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)" rbitfld.quad 0x00 17. "NDS,Disable security not supported" "Reserved,Not supported" rbitfld.quad 0x00 15. "A3V,Affinity 3 valid" "Reserved,Supported" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,?..." newline rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..." rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5 bits (32 levels),?..." bitfld.quad 0x00 6. "PMHE,Priority mask hint enable" "Disabled,Enabled" newline bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an end of interrupt register also deactivates the interrupt (non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an end of interrupt register also deactivates the interrupt (secure EL1)" "Priority drop/Deactivation,Priority drop" bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an end of interrupt register also deactivates the interrupt (EL3)" "Enabled,Disabled" newline bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both group 0 and group 1 non-secure interrupts at EL1" "Separate registers,Same register" bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both group 0 and group 1 secure interrupts in secure non-monitor modes" "Separate registers,Same register" wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" newline hgroup.quad spr:0x30C80++0x00 hide.quad 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.quad 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad spr:0x30CC6++0x00 line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Controller Interrupt Group 0 Enable Register" bitfld.quad 0x00 0. "ENABLE,Group 0 interrupts enable" "Disabled,Enabled" group.quad spr:0x30CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Controller Interrupt Group 1 Enable Register" bitfld.quad 0x00 0. "ENABLE,Group 1 interrupts enable" "Disabled,Enabled" group.quad spr:0x36CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Controller Interrupt Group 1 Enable Register (EL3)" bitfld.quad 0x00 1. "ENABLEGRP1S,Group 1 interrupts enable for the secure state" "Disabled,Enabled" bitfld.quad 0x00 0. "ENABLEGRP1NS,Group 1 interrupts enable for the non-secure state" "Disabled,Enabled" group.quad spr:0x30460++0x00 line.quad 0x00 "ICC_PMR_EL1,Interrupt Controller Interrupt Priority Mask Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,The priority mask level for the CPU interface" rgroup.quad spr:0x30CB3++0x00 line.quad 0x00 "ICC_RPR_EL1,Interrupt Controller Running Priority Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,The current running priority on the CPU interface" if (((per.q(spr:0x30CB7))&0x10000000000)==0x00) wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated." else wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.q(spr:0x30CB5))&0x10000000000)==0x00) wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" newline hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.quad spr:0x30CC5++0x00 line.quad 0x00 "ICC_SRE_EL1,Interrupt Controller System Register Enable Register (EL1)" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" bitfld.quad 0x00 0. "SRE,System register enable" "Disabled,Enabled" group.quad spr:0x34C95++0x00 line.quad 0x00 "ICC_SRE_EL2,Interrupt Controller System Register Enable Register (EL2)" bitfld.quad 0x00 3. "ENABLE,Enables lower exception level access to ICC_SRE_EL1" "Trapped,Not trapped" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System register Enable" "Disabled,Enabled" group.quad spr:0x36CC5++0x00 line.quad 0x00 "ICC_SRE_EL3,Interrupt Controller System Register Enable Register (EL3)" bitfld.quad 0x00 3. "ENABLE,Enables lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Trapped,Not trapped" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline bitfld.quad 0x00 0. "SRE,System register enable" "Disabled,Enabled" tree.end tree "AArch64 GIC Virtual CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICV_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)" bitfld.quad 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.quad 0x00 27. "[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.quad 0x00 26. "[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.quad 0x00 23. "[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.quad 0x00 21. "[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.quad 0x00 19. "[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.quad 0x00 16. "[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.quad 0x00 15. "[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.quad 0x00 7. "[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.quad 0x00 6. "[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.quad 0x00 3. "[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICV_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)" bitfld.quad 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.quad 0x00 27. "[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.quad 0x00 26. "[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.quad 0x00 23. "[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.quad 0x00 21. "[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.quad 0x00 19. "[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.quad 0x00 16. "[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.quad 0x00 15. "[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.quad 0x00 7. "[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.quad 0x00 6. "[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.quad 0x00 3. "[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline group.quad spr:0x30C83++0x00 line.quad 0x00 "ICV_BPR0_EL1,Interrupt Controller Binary Point Register 0 (EL1)" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt priority field control and interrupt preemption control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICV_BPR1_EL1,Interrupt Controller Binary Point Register 1 (EL1)" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt priority field control and interrupt preemption control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICV_CTLR_EL1,Interrupt Controller Virtual Control Register (EL1)" rbitfld.quad 0x00 15. "A3V,Affinity 3 valid" "Reserved,Non-zero" rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..." rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5 bits (32 levels),?..." bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an end of interrupt register also deactivates the interrupt" "Disabled,Enabled" newline bitfld.quad 0x00 0. "CBPR,Controls whether the same register is used for interrupt preemption of both group 0 and group 1 interrupts" "Separate registers,Same register" wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICV_DIR_EL1,Interrupt Controller Deactivate Interrupt Register" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICV_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICV_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICV_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICV_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1" rgroup.quad spr:0x30C80++0x00 line.quad 0x00 "ICV_IAR0_EL1,Interrupt Controller Interrupt Acknowledge Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the signaled interrupt" rgroup.quad spr:0x30CC0++0x00 line.quad 0x00 "ICV_IAR1_EL1,Interrupt Controller Interrupt Acknowledge Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the signaled interrupt" group.quad spr:0x30CC6++0x00 line.quad 0x00 "ICV_IGRPEN0_EL1,Interrupt Controller Interrupt Group 0 Enable Register" bitfld.quad 0x00 0. "ENABLE,Group 0 interrupts enable" "Disabled,Enabled" group.quad spr:0x30CC7++0x00 line.quad 0x00 "ICV_IGRPEN1_EL1,Interrupt Controller Interrupt Group 1 Enable Register" bitfld.quad 0x00 0. "ENABLE,Group 1 interrupts enable" "Disabled,Enabled" group.quad spr:0x30460++0x00 line.quad 0x00 "ICV_PMR_EL1,Interrupt Controller Interrupt Priority Mask Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,The priority mask level for the CPU interface" rgroup.quad spr:0x30CB3++0x00 line.quad 0x00 "ICV_RPR_EL1,Interrupt Controller Running Priority Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,The current running priority on the CPU interface" tree.end tree "AArch64 Virtual Interface Control System Register Summary" tree.open "Interrupt Controller Hypervisor Active Priorities Registers" group.quad spr:0x34C80++0x00 line.quad 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0" bitfld.quad 0x00 31. "P[31],Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "[30],Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "[29],Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "[28],Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.quad 0x00 27. "[27],Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.quad 0x00 26. "[26],Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "[25],Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "[24],Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.quad 0x00 23. "[23],Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "[22],Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.quad 0x00 21. "[21],Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "[20],Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.quad 0x00 19. "[19],Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "[18],Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "[17],Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.quad 0x00 16. "[16],Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.quad 0x00 15. "[15],Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "[14],Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "[13],Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "[12],Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "[11],Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "[10],Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "[9],Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "[8],Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.quad 0x00 7. "[7],Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.quad 0x00 6. "[6],Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "[5],Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "[4],Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.quad 0x00 3. "[3],Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "[2],Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "[1],Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "[0],Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x34C90++0x00 line.quad 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0" bitfld.quad 0x00 31. "P[31],Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "[30],Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "[29],Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "[28],Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" newline bitfld.quad 0x00 27. "[27],Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.quad 0x00 26. "[26],Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "[25],Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "[24],Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" newline bitfld.quad 0x00 23. "[23],Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "[22],Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.quad 0x00 21. "[21],Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "[20],Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.quad 0x00 19. "[19],Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "[18],Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "[17],Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" bitfld.quad 0x00 16. "[16],Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" newline bitfld.quad 0x00 15. "[15],Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "[14],Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "[13],Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "[12],Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "[11],Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "[10],Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "[9],Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "[8],Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.quad 0x00 7. "[7],Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.quad 0x00 6. "[6],Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "[5],Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "[4],Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" newline bitfld.quad 0x00 3. "[3],Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "[2],Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "[1],Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "[0],Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline rgroup.quad spr:0x34CB3++0x00 line.quad 0x00 "ICH_EISR_EL2,Interrupt Controller End Of Interrupt Status Register" bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for list register 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for list register 2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for list register 1" "No interrupt,Interrupt" newline bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for list register 0" "No interrupt,Interrupt" rgroup.quad spr:0x34CB5++0x00 line.quad 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register" bitfld.quad 0x00 3. "STATUS3,Status bit for list register 3" "Interrupt,No interrupt" bitfld.quad 0x00 2. "STATUS2,Status bit for list register 2" "Interrupt,No interrupt" bitfld.quad 0x00 1. "STATUS1,Status bit for list register 1" "Interrupt,No interrupt" newline bitfld.quad 0x00 0. "STATUS0,Status bit for list register 0" "Interrupt,No interrupt" group.quad spr:0x34CB0++0x00 line.quad 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register" bitfld.quad 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 14. "TDIR,Trap non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped" bitfld.quad 0x00 13. "TSEI, Trap all locally generated SEIs" "Not trapped,?..." newline bitfld.quad 0x00 12. "TALL1,Trap all non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 11. "TALL0,Trap all non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped" bitfld.quad 0x00 10. "TC,Trap all non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped" newline bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 disabled interrupt enable" "Disabled,Enabled" newline bitfld.quad 0x00 6. "VGRP1EIE,VM group 1 enabled interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 5. "VGRP0DIE,VM group 0 disabled interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 enabled interrupt enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NPIE,No pending interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 2. "LRENPIE,List register entry not present interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 1. "UIE,Underflow interrupt enable" "Disabled,Enabled" newline bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" if (((per.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x0)++0x00 line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x1)++0x00 line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x2)++0x00 line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00) group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" bitfld.quad 0x00 41. "PINTID_EOI,End of interrupt" "Interrupt,No interrupt" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" else group.quad spr:(0x34CC0+0x3)++0x00 line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt meaning that it corresponds to a physical interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" newline hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" endif rgroup.quad spr:0x34CB2++0x00 line.quad 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register" bitfld.quad 0x00 7. "VGRP1D,VPE group 1 disabled" "Not asserted,Asserted" bitfld.quad 0x00 6. "VGRP1E,VPE group 1 enabled" "Not asserted,Asserted" bitfld.quad 0x00 5. "VGRP0D,VPE group 0 disabled" "Not asserted,Asserted" newline bitfld.quad 0x00 4. "VGRP0E,VPE Group 0 enabled" "Not asserted,Asserted" bitfld.quad 0x00 3. "NP,No pending" "Not asserted,Asserted" bitfld.quad 0x00 2. "LRENP,List register entry not present" "Not asserted,Asserted" newline bitfld.quad 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.quad 0x00 0. "EOI,End of interrupt" "Not asserted,Asserted" group.quad spr:0x34CB7++0x00 line.quad 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register" hexmask.quad.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.quad 0x00 21.--23. "VBPR0,Virtual binary point register group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.quad 0x00 18.--20. "VBPR1,Virtual binary point register group 1" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.quad 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.quad 0x00 4. "VCBPR,Virtual common binary point register" "Separate registers,Same register" bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs" newline bitfld.quad 0x00 1. "VENG1,Virtual group 1 interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "VENG0,Virtual group 0 interrupt enable" "Disabled,Enabled" rgroup.quad spr:0x34CB1++0x00 line.quad 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register" bitfld.quad 0x00 29.--31. "PRIBITS,The number of virtual priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5 bits (32 levels),?..." bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented" "Reserved,Reserved,Reserved,Reserved,5 bits,?..." bitfld.quad 0x00 23.--25. "IDBITS,The number of virtual interrupt identifier bits supported" "16 bits,?..." newline bitfld.quad 0x00 22. "SEIS,Indicates whethesr the virtual CPU interface supports local generation of SEIs" "Not supported,?..." bitfld.quad 0x00 21. "A3V,Affinity 3 valid" "Reserved,Non-zero" bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,?..." newline bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Reserved,Supported" bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented list registers" "Reserved,Reserved,Reserved,4,?..." tree.end tree.end tree "Debug Registers" rgroup.quad spr:0x23010++0x00 line.quad 0x00 "MDCCSR_EL0,Monitor DCC Status Register" bitfld.quad 0x00 30. "RXFULL,DTRRX register full" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,DTRTX register full" "Empty,Full" group.quad spr:0x20020++0x00 line.quad 0x00 "MDCCINT_EL1,Monitor DCC Interrupt Enable Register" bitfld.quad 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled" bitfld.quad 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" hexmask.quad.long 0x00 32.--63. 1. "HIGHWORD,Writes to this register set DTRRX to the value in this field and do not change RXfull" hexmask.quad.long 0x00 0.--31. 1. "LOWWORD,Writes to this register set DTRTX to the value in this field and set TXfull" rgroup.quad spr:0x23050++0x00 line.quad 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" hexmask.quad.long 0x00 0.--31. 1. "UDTRRX,Update DTRRX" wgroup.quad spr:0x23050++0x00 line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" hexmask.quad.long 0x00 0.--31. 1. "RDTRTX,Return DTRTX" group.quad spr:0x20002++0x00 line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" hexmask.quad.long 0x00 0.--31. 1. "UDTRRX,Update DTRRX without side-effect" if (((per.q(spr:0x20114)&0x02)==0x00)) group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" rbitfld.quad 0x00 31. "TFO,Trace Filter override" "Disabled,Enabled" rbitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full save/restore bit" "Empty,Full" rbitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full save/restore bit" "Empty,Full" rbitfld.quad 0x00 27. "RXO,Save/restore bit" "Low,High" newline rbitfld.quad 0x00 26. "TXU,Save/restore bit" "Low,High" rbitfld.quad 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3" rbitfld.quad 0x00 21. "TDA,Save/restore bit" "Low,High" bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" newline rbitfld.quad 0x00 14. "HDE,Save/restore bit" "Low,High" bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled" rbitfld.quad 0x00 6. "ERR,Save/restore bit" "Low,High" newline bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" else group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.quad 0x00 31. "TFO,Trace Filter override" "Disabled,Enabled" bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full save/restore bit" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full save/restore bit" "Empty,Full" bitfld.quad 0x00 27. "RXO,Save/restore bit" "Low,High" newline bitfld.quad 0x00 26. "TXU,Save/restore bit" "Low,High" bitfld.quad 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3" bitfld.quad 0x00 21. "TDA,Save/restore bit" "Low,High" bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" newline bitfld.quad 0x00 14. "HDE,Save/restore bit" "Low,High" bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled" bitfld.quad 0x00 6. "ERR,Save/restore bit" "Low,High" newline bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" endif group.quad spr:0x20032++0x00 line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" hexmask.quad.long 0x00 0.--31. 1. "RDTRRX,Return DTRRX without side-effect" if (((per.q(spr:0x20114)&0x02)==0x02)) group.quad spr:0x20062++0x00 line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" hexmask.quad.long 0x00 0.--31. 1. "EDECCR,Used for save/restore to EDECCR over powerdown" else rgroup.quad spr:0x20062++0x00 line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" endif rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" hexmask.quad 0x00 12.--47. 0x10 "ROMADDR,ROM base physical address" bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid" wgroup.quad spr:0x20104++0x00 line.quad 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad spr:0x20114++0x00 line.quad 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,High" bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Not implemented,Reserved,Implemented,?..." group.quad spr:0x20134++0x00 line.quad 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad spr:0x20144++0x00 line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "Powered down,Emulated" group.quad spr:0x20786++0x00 line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag Register Set" bitfld.quad 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.quad 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.quad 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.quad 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.quad 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.quad 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set" bitfld.quad 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.quad 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.quad spr:0x20796++0x00 line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag Register Clear" bitfld.quad 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.quad 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.quad 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.quad 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.quad 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.quad 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" bitfld.quad 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.quad 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.quad spr:0x207E6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status Register" bitfld.quad 0x00 26.--27. "RTNID,Root non-invasive debug" "Not implemented,Reserved,Disabled,Enabled" bitfld.quad 0x00 24.--25. "RTID,Root invasive debug" "Not implemented,Reserved,Disabled,Enabled" bitfld.quad 0x00 14.--15. "RLNID,Realm non-invasive debug" "Not implemented,Reserved,Disabled,Enabled" bitfld.quad 0x00 12.--13. "RLID,Realm invasive debug" "Not implemented,Reserved,Disabled,Enabled" newline bitfld.quad 0x00 6.--7. "SNID,Secure non-invasive debug" "Not implemented,Reserved,Implemented and disabled,Implemented and enabled" bitfld.quad 0x00 4.--5. "SID,Secure invasive debug" "Not implemented,Reserved,Implemented and disabled,Implemented and enabled" bitfld.quad 0x00 2.--3. "NSNID,Non-secure non-invasive debug" "Not implemented,Reserved,Reserved,Implemented and enabled" bitfld.quad 0x00 0.--1. "NSID,Non-secure invasive debug" "Not implemented,Reserved,Implemented and disabled,Implemented and enabled" group.quad spr:0x30400++0x00 line.quad 0x00 "SPSR_EL1,Saved Program Status Register (EL1)" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 25. "TCO,Tag check override" "Unaffected,Unchecked" bitfld.quad 0x00 24. "DIT,Data Independent Timing" "No,Yes" bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" newline bitfld.quad 0x00 21. "SS,Software step" "0,1" bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 12. "SSBS,Speculative store bypass safe mechanism" "Not permitted,Permitted" bitfld.quad 0x00 10.--11. "BTYPE,Branch Type Indicator" "0,1,2,3" newline bitfld.quad 0x00 9. "D,Process state D mask" "Not masked,Masked" bitfld.quad 0x00 8. "A,SError interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,Reserved,Reserved,Reserved,EL1t,EL1h,?..." group.quad spr:0x35400++0x00 line.quad 0x00 "SPSR_EL12,Saved Program Status Register (EL12)" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 25. "TCO,Tag check override" "Unaffected,Unchecked" bitfld.quad 0x00 24. "DIT,Data Independent Timing" "No,Yes" bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" newline bitfld.quad 0x00 21. "SS,Software step" "0,1" bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 12. "SSBS,Speculative store bypass safe mechanism" "Not permitted,Permitted" bitfld.quad 0x00 10.--11. "BTYPE,Branch Type Indicator" "0,1,2,3" newline bitfld.quad 0x00 9. "D,Process state D mask" "Not masked,Masked" bitfld.quad 0x00 8. "A,SError interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,Reserved,Reserved,Reserved,EL1t,EL1h,?..." group.quad spr:0x34400++0x00 line.quad 0x00 "SPSR_EL2,Saved Program Status Register (EL2)" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 25. "TCO,Tag check override" "Unaffected,Unchecked" bitfld.quad 0x00 24. "DIT,Data Independent Timing" "No,Yes" bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" newline bitfld.quad 0x00 21. "SS,Software step" "0,1" bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 12. "SSBS,Speculative store bypass safe mechanism" "Not permitted,Permitted" bitfld.quad 0x00 10.--11. "BTYPE,Branch Type Indicator" "0,1,2,3" newline bitfld.quad 0x00 9. "D,Process state D mask" "Not masked,Masked" bitfld.quad 0x00 8. "A,SError interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,Reserved,Reserved,Reserved,EL1t,EL1h,Reserved,Reserved,EL2t,EL2h,?..." group.quad spr:0x36400++0x00 line.quad 0x00 "SPSR_EL3,Saved Program Status Register (EL3)" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 25. "TCO,Tag check override" "Unaffected,Unchecked" bitfld.quad 0x00 24. "DIT,Data Independent Timing" "No,Yes" bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" newline bitfld.quad 0x00 21. "SS,Software step" "0,1" bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 12. "SSBS,Speculative store bypass safe mechanism" "Not permitted,Permitted" bitfld.quad 0x00 10.--11. "BTYPE,Branch Type Indicator" "0,1,2,3" newline bitfld.quad 0x00 9. "D,Process state D mask" "Not masked,Masked" bitfld.quad 0x00 8. "A,SError interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,Reserved,Reserved,Reserved,EL1t,EL1h,Reserved,Reserved,EL2t,EL2h,Reserved,Reserved,EL3t,EL3h,?..." group.quad spr:0x33450++0x00 line.quad 0x00 "DSPSR_EL0,Debug Saved Program Status Register" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 25. "TCO,Tag check override" "Unaffected,Unchecked" bitfld.quad 0x00 24. "DIT,Data Independent Timing" "No,Yes" bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" newline bitfld.quad 0x00 21. "SS,Software step" "0,1" bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 12. "SSBS,Speculative store bypass safe mechanism" "Not permitted,Permitted" bitfld.quad 0x00 10.--11. "BTYPE,Branch Type Indicator" "0,1,2,3" newline bitfld.quad 0x00 9. "D,Process state D mask" "Not masked,Masked" bitfld.quad 0x00 8. "A,SError interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,Reserved,Reserved,Reserved,EL1t,EL1h,Reserved,Reserved,EL2t,EL2h,Reserved,Reserved,EL3t,EL3h,?..." group.quad spr:0x33451++0x00 line.quad 0x00 "DLR_EL0,Debug Link Register" group.quad spr:0x30423++0x00 line.quad 0x00 "PAN,Privileged Access Never" bitfld.quad 0x00 22. "PAN,Privileged access never disabled" "No,Yes" group.quad spr:0x30401++0x00 line.quad 0x00 "ELR_EL1,Exception Link Register (EL1)" group.quad spr:0x34401++0x00 line.quad 0x00 "ELR_EL2,Exception Link Register (EL2)" group.quad spr:0x36401++0x00 line.quad 0x00 "ELR_EL3,Exception Link Register (EL3)" group.quad spr:0x30410++0x00 line.quad 0x00 "SP_EL0,Stack Pointer (EL0)" group.quad spr:0x34410++0x00 line.quad 0x00 "SP_EL1,Stack Pointer (EL1)" group.quad spr:0x36410++0x00 line.quad 0x00 "SP_EL2,Stack Pointer (EL2)" group.quad spr:0x30420++0x00 line.quad 0x00 "SPSel,Stack Pointer Select" bitfld.quad 0x00 0. "SP,Stack pointer to use" "SP_EL0,SP_ELx" group.quad spr:0x33426++0x00 line.quad 0x00 "SSBS,Speculative Store Bypass Safe" bitfld.quad 0x00 12. "SSBS,Speculative Store Bypass Safe" "Disabled,Enabled" group.quad spr:0x30424++0x00 line.quad 0x00 "UAO,User Access Override" bitfld.quad 0x00 23. "UAO,User access override" "0,1" group.quad spr:0x34431++0x00 line.quad 0x00 "SPSR_ABT,Saved Program Status Register (Abort Mode)" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 23. "SSBS,Speculative store bypass safe mechanism" "Not permitted,Permitted" bitfld.quad 0x00 22. "PAN,Privileged access never" "No,Yes" bitfld.quad 0x00 21. "DIT,Data independent timing" "0,1" newline bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,Reserved,Reserved,Monitor,Abort,Reserved,Reserved,Hyp,Undefined,Reserved,Reserved,Reserved,System" group.quad spr:0x34433++0x00 line.quad 0x00 "SPSR_FIQ,Saved Program Status Register (FIQ Mode)" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 23. "SSBS,Speculative store bypass safe mechanism" "Not permitted,Permitted" bitfld.quad 0x00 22. "PAN,Privileged access never" "No,Yes" bitfld.quad 0x00 21. "DIT,Data independent timing" "0,1" newline bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,Reserved,Reserved,Monitor,Abort,Reserved,Reserved,Reserved,Undefined,Reserved,Reserved,Reserved,System" group.quad spr:0x34430++0x00 line.quad 0x00 "SPSR_IRQ,Saved Program Status Register (IRQ Mode)" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 23. "SSBS,Speculative store bypass safe mechanism" "Not permitted,Permitted" bitfld.quad 0x00 22. "PAN,Privileged access never" "No,Yes" bitfld.quad 0x00 21. "DIT,Data independent timing" "0,1" newline bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,Reserved,Reserved,Monitor,Abort,Reserved,Reserved,Reserved,Undefined,Reserved,Reserved,Reserved,System" group.quad spr:0x34432++0x00 line.quad 0x00 "SPSR_UND,Saved Program Status Register (Undefined MODE)" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 23. "SSBS,Speculative store bypass safe mechanism" "Not permitted,Permitted" bitfld.quad 0x00 22. "PAN,Privileged access never" "No,Yes" bitfld.quad 0x00 21. "DIT,Data independent timing" "0,1" newline bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,Reserved,Reserved,Monitor,Abort,Reserved,Reserved,Hyp,Undefined,Reserved,Reserved,Reserved,System" rgroup.quad spr:0x30422++0x00 line.quad 0x00 "CURRENTEL,Current Exception Level" bitfld.quad 0x00 2.--3. "EL,Current exception level" "EL0,EL1,EL2,EL3" group.quad spr:0x33421++0x00 line.quad 0x00 "DAIF,Interrupt Mask Bits" bitfld.quad 0x00 9. "D,Process state D mask" "Not masked,Masked" bitfld.quad 0x00 8. "A,SError interrupt mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" group.quad spr:0x33420++0x00 line.quad 0x00 "NZCV,Condition Flags" bitfld.quad 0x00 31. "N,Negative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not occurred,Occurred" bitfld.quad 0x00 29. "C,Carry condition flag" "Not occurred,Occurred" bitfld.quad 0x00 28. "V,Overflow condition flag" "Not occurred,Occurred" rgroup.quad spr:0x36F10++0x00 line.quad 0x00 "DDATA0_EL3,DDATA0_EL3" rgroup.quad spr:0x36F11++0x00 line.quad 0x00 "DDATA1_EL3,DDATA1_EL3" rgroup.quad spr:0x36F12++0x00 line.quad 0x00 "DDATA2_EL3,DDATA2_EL3" rgroup.quad spr:0x36F00++0x00 line.quad 0x00 "IDATA0_EL3,DDATA0_EL3" rgroup.quad spr:0x36F01++0x00 line.quad 0x00 "IDATA1_EL3,DDATA1_EL3" rgroup.quad spr:0x36F02++0x00 line.quad 0x00 "IDATA2_EL3,DDATA2_EL3" tree.end tree "Activity Monitors Unit" group.quad spr:0x33F97++0x00 line.quad 0x00 "AMCNTENCLR_EL0,Activity Monitors Count Enable Clear Register" bitfld.quad 0x00 4. "P4,AMEVCNTR4 disable bit [read/write]" "Disabled/No effect,Enabled/Disables" newline bitfld.quad 0x00 3. "P3,AMEVCNTR3 disable bit [read/write]" "Disabled/No effect,Enabled/Disables" bitfld.quad 0x00 2. "P2,AMEVCNTR2 disable bit [read/write]" "Disabled/No effect,Enabled/Disables" bitfld.quad 0x00 1. "P1,AMEVCNTR1 disable bit [read/write]" "Disabled/No effect,Enabled/Disables" bitfld.quad 0x00 0. "P0,AMEVCNTR0 disable bit [read/write]" "Disabled/No effect,Enabled/Disables" group.quad spr:0x33F96++0x00 line.quad 0x00 "AMCNTENSET_EL0,Activity Monitors Count Enable Set Register" bitfld.quad 0x00 4. "P4,AMEVCNTR4 enable bit [read/write]" "Disabled/No effect,Enabled/Enables" bitfld.quad 0x00 3. "P3,AMEVCNTR3 enable bit [read/write]" "Disabled/No effect,Enabled/Enables" bitfld.quad 0x00 2. "P2,AMEVCNTR2 enable bit [read/write]" "Disabled/No effect,Enabled/Enables" bitfld.quad 0x00 1. "P1,AMEVCNTR1 enable bit [read/write]" "Disabled/No effect,Enabled/Enables" newline bitfld.quad 0x00 0. "P0,AMEVCNTR0 enable bit" "Disabled/No effect,Enabled/Enables" rgroup.quad spr:0x33FA6++0x00 line.quad 0x00 "AMCFGR_EL0,Activity Monitors Configuration Register" bitfld.quad 0x00 8.--13. "SIZE,Size of counters" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" hexmask.quad.byte 0x00 0.--7. 1. 1. "N,Number of activity counters implemented" group.quad spr:0x33FA7++0x00 line.quad 0x00 "AMUSERENR_EL0,Activity Monitor EL0 Enable access" bitfld.quad 0x00 0. "EN,Traps EL0 accesses to the activity monitor registers to EL1" "Trapped,Not trapped" newline group.quad spr:0x33F90++0x00 line.quad 0x00 "AMEVCNTR0_EL0,Activity Monitor Event Counter Register 0" group.quad spr:(0x33F90+0x10)++0x00 line.quad 0x00 "AMEVTYPER0_EL0,Activity Monitor Event Type Register 0" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT" group.quad spr:0x33F91++0x00 line.quad 0x00 "AMEVCNTR1_EL0,Activity Monitor Event Counter Register 1" group.quad spr:(0x33F91+0x10)++0x00 line.quad 0x00 "AMEVTYPER1_EL0,Activity Monitor Event Type Register 1" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT" group.quad spr:0x33F92++0x00 line.quad 0x00 "AMEVCNTR2_EL0,Activity Monitor Event Counter Register 2" group.quad spr:(0x33F92+0x10)++0x00 line.quad 0x00 "AMEVTYPER2_EL0,Activity Monitor Event Type Register 2" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT" group.quad spr:0x33F93++0x00 line.quad 0x00 "AMEVCNTR3_EL0,Activity Monitor Event Counter Register 3" group.quad spr:(0x33F93+0x10)++0x00 line.quad 0x00 "AMEVTYPER3_EL0,Activity Monitor Event Type Register 3" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT" group.quad spr:0x33F94++0x00 line.quad 0x00 "AMEVCNTR4_EL0,Activity Monitor Event Counter Register 4" group.quad spr:(0x33F94+0x10)++0x00 line.quad 0x00 "AMEVTYPER4_EL0,Activity Monitor Event Type Register 4" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if (((per.q(spr:0x20005+0x0))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((per.q(spr:0x20005+0x0))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x300000)||(((per.q(spr:0x20005+0x0))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x700000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x0))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xD00000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" elif (((per.q(spr:0x20005+0x0))&0xF00000)>=0xE00000) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x0))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x0))&0xC000)==0x0000) group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x0))&0xC000)==0x4000) group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x0))&0xC000)==0x8000) group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x0))&0xC000)==0x00)||(((per.q(spr:0x20005+0x0))&0xC000)==0x4000)||(((per.q(spr:0x20005+0x0))&0xC000)==0x8000) group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree "Breakpoint 1" if (((per.q(spr:0x20005+0x10))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((per.q(spr:0x20005+0x10))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x300000)||(((per.q(spr:0x20005+0x10))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x700000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x10))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xD00000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" elif (((per.q(spr:0x20005+0x10))&0xF00000)>=0xE00000) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x10))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x10))&0xC000)==0x0000) group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x10))&0xC000)==0x4000) group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x10))&0xC000)==0x8000) group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x10))&0xC000)==0x00)||(((per.q(spr:0x20005+0x10))&0xC000)==0x4000)||(((per.q(spr:0x20005+0x10))&0xC000)==0x8000) group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree "Breakpoint 2" if (((per.q(spr:0x20005+0x20))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((per.q(spr:0x20005+0x20))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x300000)||(((per.q(spr:0x20005+0x20))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x700000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x20))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xD00000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" elif (((per.q(spr:0x20005+0x20))&0xF00000)>=0xE00000) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x20))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x20))&0xC000)==0x0000) group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x20))&0xC000)==0x4000) group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x20))&0xC000)==0x8000) group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x20))&0xC000)==0x00)||(((per.q(spr:0x20005+0x20))&0xC000)==0x4000)||(((per.q(spr:0x20005+0x20))&0xC000)==0x8000) group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree "Breakpoint 3" if (((per.q(spr:0x20005+0x30))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((per.q(spr:0x20005+0x30))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x300000)||(((per.q(spr:0x20005+0x30))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x700000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x30))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xD00000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" elif (((per.q(spr:0x20005+0x30))&0xF00000)>=0xE00000) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x30))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x30))&0xC000)==0x0000) group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x30))&0xC000)==0x4000) group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x30))&0xC000)==0x8000) group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x30))&0xC000)==0x00)||(((per.q(spr:0x20005+0x30))&0xC000)==0x4000)||(((per.q(spr:0x20005+0x30))&0xC000)==0x8000) group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree "Breakpoint 4" if (((per.q(spr:0x20005+0x40))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((per.q(spr:0x20005+0x40))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x300000)||(((per.q(spr:0x20005+0x40))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x700000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x40))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xD00000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" elif (((per.q(spr:0x20005+0x40))&0xF00000)>=0xE00000) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x40))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x40))&0xC000)==0x0000) group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x40))&0xC000)==0x4000) group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x40))&0xC000)==0x8000) group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x40))&0xC000)==0x00)||(((per.q(spr:0x20005+0x40))&0xC000)==0x4000)||(((per.q(spr:0x20005+0x40))&0xC000)==0x8000) group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree "Breakpoint 5" if (((per.q(spr:0x20005+0x50))&0xF00000)<=0x100000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison" elif (((per.q(spr:0x20005+0x50))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x300000)||(((per.q(spr:0x20005+0x50))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x700000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" elif (((per.q(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif (((per.q(spr:0x20005+0x50))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xD00000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" elif (((per.q(spr:0x20005+0x50))&0xF00000)>=0xE00000) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison" newline hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" endif if (((per.q(spr:0x20005+0x50))&0x2000)==0x2000) if (((per.q(spr:0x20005+0x50))&0xC000)==0x0000) group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x50))&0xC000)==0x4000) group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" elif (((per.q(spr:0x20005+0x50))&0xC000)==0x8000) group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20005+0x50))&0xC000)==0x00)||(((per.q(spr:0x20005+0x50))&0xC000)==0x4000)||(((per.q(spr:0x20005+0x50))&0xC000)==0x8000) group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" else group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Reserved,Reserved,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked full Context ID match,Linked full Context ID match" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" newline bitfld.quad 0x00 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1" newline bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" endif endif tree.end tree.end tree "Watchpoint Registers" tree "Watchpoint 0" group.quad spr:(0x20006+0x0)++0x00 line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x04 "VA,Data address" if (((per.q(spr:0x20007+0x0))&0x2000)==0x2000) if (((per.q(spr:0x20007+0x0))&0xC000)==0x0000) group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,TrustZone/Supervisor/System,Reserved,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x0))&0xC000)==0x4000) group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x0))&0xC000)==0x8000) group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,TrustZone/Supervisor/System,Reserved,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20007+0x0))&0xC000)==0x00)||(((per.q(spr:0x20007+0x0))&0xC000)==0x4000)||(((per.q(spr:0x20007+0x0))&0xC000)==0x8000) group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif endif tree.end tree "Watchpoint 1" group.quad spr:(0x20006+0x10)++0x00 line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x04 "VA,Data address" if (((per.q(spr:0x20007+0x10))&0x2000)==0x2000) if (((per.q(spr:0x20007+0x10))&0xC000)==0x0000) group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,TrustZone/Supervisor/System,Reserved,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x10))&0xC000)==0x4000) group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x10))&0xC000)==0x8000) group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,TrustZone/Supervisor/System,Reserved,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20007+0x10))&0xC000)==0x00)||(((per.q(spr:0x20007+0x10))&0xC000)==0x4000)||(((per.q(spr:0x20007+0x10))&0xC000)==0x8000) group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif endif tree.end tree "Watchpoint 2" group.quad spr:(0x20006+0x20)++0x00 line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x04 "VA,Data address" if (((per.q(spr:0x20007+0x20))&0x2000)==0x2000) if (((per.q(spr:0x20007+0x20))&0xC000)==0x0000) group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,TrustZone/Supervisor/System,Reserved,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x20))&0xC000)==0x4000) group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x20))&0xC000)==0x8000) group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,TrustZone/Supervisor/System,Reserved,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20007+0x20))&0xC000)==0x00)||(((per.q(spr:0x20007+0x20))&0xC000)==0x4000)||(((per.q(spr:0x20007+0x20))&0xC000)==0x8000) group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif endif tree.end tree "Watchpoint 3" group.quad spr:(0x20006+0x30)++0x00 line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x04 "VA,Data address" if (((per.q(spr:0x20007+0x30))&0x2000)==0x2000) if (((per.q(spr:0x20007+0x30))&0xC000)==0x0000) group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,TrustZone/Supervisor/System,Reserved,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x30))&0xC000)==0x4000) group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" elif (((per.q(spr:0x20007+0x30))&0xC000)==0x8000) group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "TrustZone,TrustZone/Supervisor/System,Reserved,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif else if (((per.q(spr:0x20007+0x30))&0xC000)==0x00)||(((per.q(spr:0x20007+0x30))&0xC000)==0x4000)||(((per.q(spr:0x20007+0x30))&0xC000)==0x8000) group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" else group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" newline bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure" bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.word 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" endif endif tree.end tree.end tree "LORegions Registers" group.quad spr:0x30A40++0x00 line.quad 0x00 "LORSA_EL1,LORegion Start Address" hexmask.quad.long 0x00 16.--47. 0x01 "SA,Start physical address bits[47:16]" bitfld.quad 0x00 0. "VALID,Indicates whether the LORegion Descriptor is enabled" "Not valid,Valid" group.quad spr:0x30A41++0x00 line.quad 0x00 "LOREA_EL1,LORegion End Address" hexmask.quad.long 0x00 16.--47. 0x01 "EA,End physical address bits[47:16]" group.quad spr:0x30A42++0x00 line.quad 0x00 "LORN_EL1,LORegion Number" hexmask.quad.byte 0x00 0.--7. 1. "NUM,Number of the LORegion described in the current LORegion descriptor selected by LORC_EL1.DS" group.quad spr:0x30A43++0x00 line.quad 0x00 "LORC_EL1,LORegion Control" hexmask.quad.word 0x00 2.--9. 1. "DS,Descriptor select" bitfld.quad 0x00 0. "EN,Enable" "Disabled,Enabled" rgroup.quad spr:0x30A47++0x00 line.quad 0x00 "LORID_EL1,LORegionID" hexmask.quad.byte 0x00 16.--23. 1. "LD,Number of LORegion descriptors supported by the PE" hexmask.quad.byte 0x00 0.--7. 1. "LR,Number of LORegions supported by the PE" tree.end tree "DynamIQ Shared Unit" tree "Cluster Control Registers" if (((per.l(spr:0x30F30))&0x2000)==(0x00)) rgroup.quad spr:0x30F30++0x00 line.quad 0x00 "CLUSTERCFR_EL1,Cluster Configuration Register" bitfld.quad 0x00 24.--27. "PE,Number of PEs" "1,2,?..." bitfld.quad 0x00 23. "L3_DATA_RAM_WD,L3 data RAM write delay" "Not limited,Limited" newline bitfld.quad 0x00 21. "CRSP7,Core 7 register slice present" "Not present,Present" bitfld.quad 0x00 20. "CRSP6,Core 6 register slice present" "Not present,Present" bitfld.quad 0x00 19. "CRSP5,Core 5 register slice present" "Not present,Present" newline bitfld.quad 0x00 18. "CRSP4,Core 4 register slice present" "Not present,Present" bitfld.quad 0x00 17. "CRSP3,Core 3 register slice present" "Not present,Present" bitfld.quad 0x00 16. "CRSP2,Core 2 register slice present" "Not present,Present" newline bitfld.quad 0x00 15. "CRSP1,Core 1 register slice present" "Not present,Present" bitfld.quad 0x00 14. "CRSP0,Core 0 register slice present" "Not present,Present" bitfld.quad 0x00 13. "BIE,Bus interface extended" "Single,Dual" newline bitfld.quad 0x00 12. "PPP,Peripheral port present" "Not present,Present" newline bitfld.quad 0x00 11. "ACP,ACP interface present" "Not present,Present" bitfld.quad 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Single 256-bit CHI" bitfld.quad 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC" newline bitfld.quad 0x00 7. "L3_DATA_RAM_RS,L3 data RAM register slice present" "Not present,Present" bitfld.quad 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles" bitfld.quad 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles" newline bitfld.quad 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present" bitfld.quad 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,5,6,7,8" else rgroup.quad spr:0x30F30++0x00 line.quad 0x00 "CLUSTERCFR_EL1,Cluster Configuration Register" bitfld.quad 0x00 24.--27. "PE,Number of PEs" "1,2,?..." bitfld.quad 0x00 23. "L3_DATA_RAM_WD,,L3 data RAM write delay" "Not limited,Limited" newline bitfld.quad 0x00 21. "CRSP7,Core 7 register slice present" "Not present,Present" bitfld.quad 0x00 20. "CRSP6,Core 6 register slice present" "Not present,Present" bitfld.quad 0x00 19. "CRSP5,Core 5 register slice present" "Not present,Present" newline bitfld.quad 0x00 18. "CRSP4,Core 4 register slice present" "Not present,Present" bitfld.quad 0x00 17. "CRSP3,Core 3 register slice present" "Not present,Present" bitfld.quad 0x00 16. "CRSP2,Core 2 register slice present" "Not present,Present" newline bitfld.quad 0x00 15. "CRSP1,Core 1 register slice present" "Not present,Present" bitfld.quad 0x00 14. "CRSP0,Core 0 register slice present" "Not present,Present" bitfld.quad 0x00 13. "BIE,Bus interface extended" "Single,Dual" newline bitfld.quad 0x00 12. "PPP,Peripheral port present" "Not present,Present" newline bitfld.quad 0x00 11. "ACP,ACP interface present" "Not present,Present" bitfld.quad 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Dual 256-bit CHI" bitfld.quad 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC" newline bitfld.quad 0x00 7. "L3_DATA_RAM_RS,L3 data RAM register slice present" "Not present,Present" bitfld.quad 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles" bitfld.quad 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles" newline bitfld.quad 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present" bitfld.quad 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,5,6,7,8" endif rgroup.quad spr:0x30F31++0x00 line.quad 0x00 "CLUSTERIDR_EL1,Cluster Main Revision Register" hexmask.quad.byte 0x00 4.--7. 1. "VARIANT,Indicates the variant of the DSU" hexmask.quad.byte 0x00 0.--3. 1. "REVISION,Indicates the minor revision number of the DSU" rgroup.quad spr:0x30F32++0x00 line.quad 0x00 "CLUSTERREVIDR_EL1,Cluster ECO ID Register" group.quad spr:0x30F33++0x00 line.quad 0x00 "CLUSTERACTLR_EL1,Cluster Auxiliary Control Register" group.quad spr:0x30F34++0x00 line.quad 0x00 "CLUSTERECTLR_EL1,Cluster Extended Control Register" bitfld.quad 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled" bitfld.quad 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128" bitfld.quad 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes" newline bitfld.quad 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported" bitfld.quad 0x00 3. "CTEC,Disables send evict transactions on the ACE/CHI master" "No,Yes" bitfld.quad 0x00 2. "CFUCEC,Disables WriteEvict requests on the ACE/CHI master (Powering down part/All L3 cache)" "No,Yes" newline bitfld.quad 0x00 0. "DNCWL,Enable normal non-cachable writes to all master interfaces" "Disabled,Enabled" group.quad spr:0x30F35++0x00 line.quad 0x00 "CLUSTERPWRCTLR_EL1,Cluster Power Control Register" bitfld.quad 0x00 4.--7. "CPPR,Cache portion power request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0.--2. "FRC,Functional retention control [Number of Architectural Timer ticks required before retention entry]" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" group.quad spr:0x30F36++0x00 line.quad 0x00 "CLUSTERPWRDN_EL1,Cluster Power Down Register" bitfld.quad 0x00 1. "MRR,Memory retention required" "Not required,Required" bitfld.quad 0x00 0. "CPR,Cluster power required" "Not required,Required" rgroup.quad spr:0x30F37++0x00 line.quad 0x00 "CLUSTERPWRSTAT_EL1,Cluster Power Status Register" bitfld.quad 0x00 4.--7. "CPPS,This bits indicates which cache portions are currently powered up and available" "No ways,Ways 0-3,Reserved,Ways 0-7,Reserved,Reserved,Reserved,Ways 0-11,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ways 0-15" bitfld.quad 0x00 1. "RWPD,Enabled memory retention when all cores are powered down" "Disabled,Enabled" bitfld.quad 0x00 0. "DCPD,Disabled cluster power down when all cores are powered down" "No,Yes" group.quad spr:0x30F40++0x00 line.quad 0x00 "CLUSTERTHREADSID_EL1,Cluster Thread Scheme ID Register" bitfld.quad 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for current thread" "0,1,2,3,4,5,6,7" group.quad spr:0x30F41++0x00 line.quad 0x00 "CLUSTERACPSID_EL1,Cluster ACP Scheme ID Register" bitfld.quad 0x00 0.--2. "SCHEME_ID_ACP,Scheme ID for ACP transactions" "0,1,2,3,4,5,6,7" group.quad spr:0x30F42++0x00 line.quad 0x00 "CLUSTERSTASHSID_EL1,Cluster Stash Scheme ID Register" bitfld.quad 0x00 0.--2. "SCHEME_ID_SR,Scheme ID for stash requests received from the interconnect" "0,1,2,3,4,5,6,7" group.quad spr:0x30F43++0x00 line.quad 0x00 "CLUSTERPARTCR_EL1,Cluster Partition Control Register" bitfld.quad 0x00 31. "W3_ID7,Way group 3 is assigned as private to scheme ID 7" "Not assigned,Assigned" bitfld.quad 0x00 30. "W2_ID7,Way group 2 is assigned as private to scheme ID 7" "Not assigned,Assigned" bitfld.quad 0x00 29. "W1_ID7,Way group 1 is assigned as private to scheme ID 7" "Not assigned,Assigned" newline bitfld.quad 0x00 28. "W0_ID7,Way group 0 is assigned as private to scheme ID 7" "Not assigned,Assigned" bitfld.quad 0x00 27. "W3_ID6,Way group 3 is assigned as private to scheme ID 6" "Not assigned,Assigned" bitfld.quad 0x00 26. "W2_ID6,Way group 2 is assigned as private to scheme ID 6" "Not assigned,Assigned" newline bitfld.quad 0x00 25. "W1_ID6,Way group 1 is assigned as private to scheme ID 6" "Not assigned,Assigned" bitfld.quad 0x00 24. "W0_ID6,Way group 0 is assigned as private to scheme ID 6" "Not assigned,Assigned" bitfld.quad 0x00 23. "W3_ID5,Way group 3 is assigned as private to scheme ID 5" "Not assigned,Assigned" newline bitfld.quad 0x00 22. "W2_ID5,Way group 2 is assigned as private to scheme ID 5" "Not assigned,Assigned" bitfld.quad 0x00 21. "W1_ID5,Way group 1 is assigned as private to scheme ID 5" "Not assigned,Assigned" bitfld.quad 0x00 20. "W0_ID5,Way group 0 is assigned as private to scheme ID 5" "Not assigned,Assigned" newline bitfld.quad 0x00 19. "W3_ID4,Way group 3 is assigned as private to scheme ID 4" "Not assigned,Assigned" bitfld.quad 0x00 18. "W2_ID4,Way group 2 is assigned as private to scheme ID 4" "Not assigned,Assigned" bitfld.quad 0x00 17. "W1_ID4,Way group 1 is assigned as private to scheme ID 4" "Not assigned,Assigned" newline bitfld.quad 0x00 16. "W0_ID4,Way group 0 is assigned as private to scheme ID 4" "Not assigned,Assigned" bitfld.quad 0x00 15. "W3_ID3,Way group 3 is assigned as private to scheme ID 3" "Not assigned,Assigned" bitfld.quad 0x00 14. "W2_ID3,Way group 2 is assigned as private to scheme ID 3" "Not assigned,Assigned" newline bitfld.quad 0x00 13. "W1_ID3,Way group 1 is assigned as private to scheme ID 3" "Not assigned,Assigned" bitfld.quad 0x00 12. "W0_ID3,Way group 0 is assigned as private to scheme ID 3" "Not assigned,Assigned" bitfld.quad 0x00 11. "W3_ID2,Way group 3 is assigned as private to scheme ID 2" "Not assigned,Assigned" newline bitfld.quad 0x00 10. "W2_ID2,Way group 2 is assigned as private to scheme ID 2" "Not assigned,Assigned" bitfld.quad 0x00 9. "W1_ID2,Way group 1 is assigned as private to scheme ID 2" "Not assigned,Assigned" bitfld.quad 0x00 8. "W0_ID2,Way group 0 is assigned as private to scheme ID 2" "Not assigned,Assigned" newline bitfld.quad 0x00 7. "W3_ID1,Way group 3 is assigned as private to scheme ID 1" "Not assigned,Assigned" bitfld.quad 0x00 6. "W2_ID1,Way group 2 is assigned as private to scheme ID 1" "Not assigned,Assigned" bitfld.quad 0x00 5. "W1_ID1,Way group 1 is assigned as private to scheme ID 1" "Not assigned,Assigned" newline bitfld.quad 0x00 4. "W0_ID1,Way group 0 is assigned as private to scheme ID 1" "Not assigned,Assigned" bitfld.quad 0x00 3. "W3_ID0,Way group 3 is assigned as private to scheme ID 0" "Not assigned,Assigned" bitfld.quad 0x00 2. "W2_ID0,Way group 2 is assigned as private to scheme ID 0" "Not assigned,Assigned" newline bitfld.quad 0x00 1. "W1_ID0,Way group 1 is assigned as private to scheme ID 0" "Not assigned,Assigned" bitfld.quad 0x00 0. "W0_ID0,Way group 0 is assigned as private to scheme ID 0" "Not assigned,Assigned" group.quad spr:0x30F44++0x00 line.quad 0x00 "CLUSTERBUSQOS_EL1,Cluster Bus QoS Control Register" bitfld.quad 0x00 28.--31. "CHI_BUS_QOS_SCHEME_ID7,Value driven on the CHI bus QoS field for scheme ID 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 24.--27. "CHI_BUS_QOS_SCHEME_ID6,Value driven on the CHI bus QoS field for scheme ID 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 20.--23. "CHI_BUS_QOS_SCHEME_ID5,Value driven on the CHI bus QoS field for scheme ID 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 16.--19. "CHI_BUS_QOS_SCHEME_ID4,Value driven on the CHI bus QoS field for scheme ID 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 12.--15. "CHI_BUS_QOS_SCHEME_ID3,Value driven on the CHI bus QoS field for scheme ID 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 8.--11. "CHI_BUS_QOS_SCHEME_ID2,Value driven on the CHI bus QoS field for scheme ID 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 4.--7. "CHI_BUS_QOS_SCHEME_ID1,Value driven on the CHI bus QoS field for scheme ID 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0.--3. "CHI_BUS_QOS_SCHEME_ID0,Value driven on the CHI bus QoS field for scheme ID 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.quad spr:0x30F45++0x00 line.quad 0x00 "CLUSTERL3HIT_EL1,Cluster L3 Hit Counter Register" hexmask.quad.long 0x00 0.--31. 1. "HITCNT,Count of number of L3 hits for use in portion control calculations" group.quad spr:0x30F46++0x00 line.quad 0x00 "CLUSTERL3MISS_EL1,Cluster L3 Miss Counter Register" hexmask.quad.long 0x00 0.--31. 1. "MISSCNT,Count of number of L3 misses for use in portion control calculations" group.quad spr:0x30F47++0x00 line.quad 0x00 "CLUSTERTHREADSIDOVR_EL1,Cluster Thread Scheme ID Override Register" bitfld.quad 0x00 16.--18. "SCHEME_ID_MASK,A bit set in the mask causes the matching bit to be taken from this register rather than from the CLUSTERTHREADSID_EL1 register" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for this thread if masked" "0,1,2,3,4,5,6,7" tree.end tree "Error System Registers" rgroup.quad spr:0x30530++0x00 line.quad 0x00 "ERRIDR_EL1,Error ID Register" hexmask.quad.word 0x00 0.--15. 1. "NUM,Number of records that can be accessed through the Error Record system registers" group.quad spr:0x30531++0x00 line.quad 0x00 "ERRSELR_EL1,Error Record Select Register" bitfld.quad 0x00 0. "SEL,Selects the record accessed through the ERX registers" "Record 0,Record 1" if (((per.q(spr:0x30531))&0x01)==0x00) rgroup.quad spr:0x30540++0x00 line.quad 0x00 "ERXFR_EL1,Selected Error Record Feature Register - ERR0FR - Record 0" bitfld.quad 0x00 18.--19. "CEO,Corrected error overwrite" "No overwrite,?..." newline bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..." bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented" newline bitfld.quad 0x00 12.--14. "CEC,Corrected error counter" "Reserved,Reserved,Implemented/8-bit,?..." bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..." bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 0.--1. "ED,Error detection and correction[Lock/Split]" "Reserved,Reserved,Implemented,?..." group.quad spr:0x30541++0x00 line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register - ER0CTLR - Record 0" bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled" bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled" group.quad spr:0x30542++0x00 line.quad 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register - ER0STATUS - Record 0" bitfld.quad 0x00 31. "AV,Address valid" "Not valid,Valid" bitfld.quad 0x00 30. "V,Status register valid" "Not valid,Valid" newline bitfld.quad 0x00 29. "UE,Uncorrected Error" "No error,>=1 error" bitfld.quad 0x00 28. "ER,Error reported" "No error,Error" newline bitfld.quad 0x00 27. "OF,Error overflow" "No error,>=1 error" bitfld.quad 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid" newline bitfld.quad 0x00 24.--25. "CE,Corrected errors" "No error,>=1 transient,>=1 error,>=1 persistent" bitfld.quad 0x00 23. "DE,Deferred errors" "No error,>=1 error" newline bitfld.quad 0x00 22. "PN,Poison" "Cannot distinguish,?..." bitfld.quad 0x00 20.--21. "UET,Uncorrected error type" "UC,?..." bitfld.quad 0x00 0.--4. "SERR,Primary error code" "No error,Reserved,Internal data buffer,Reserved,Reserved,Reserved,Cache data RAM,Cache tag/dirty RAM,TLB data RAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache copyback,Not supported,?..." group.quad spr:0x30F20++0x00 line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register - ER0PFGF - Record 0" bitfld.quad 0x00 31. "PFG,Pseudo fault generation" "Reserved,Supported" bitfld.quad 0x00 30. "R,Restartable bit" "Reserved,Supported" newline bitfld.quad 0x00 6. "CE,Corrected error generation" "Reserved,Supported" newline bitfld.quad 0x00 5. "DE,Deferred error generation" "Reserved,Supported" bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..." newline bitfld.quad 0x00 3. "UER,Signalled or recoverable error generation" "Not supported,?..." bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,?..." newline bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Reserved,Supported" group.quad spr:0x30F21++0x00 line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register - ER0PFGCTL - Record 0" bitfld.quad 0x00 31. "CDNEN,Countdown enable. Control transfers from the value that is held in the ERR0PFGCDN into the Error Generation Counter" "Disabled,Enabled" bitfld.quad 0x00 30. "R,Restart. Controls whether on reaching zero the Error Generation Counter restarts from the ext-CLUSTERRAS_ERR0PFGCDN value or stops" "Disabled,Enabled" newline bitfld.quad 0x00 6. "CE,Corrected error generation enable" "No error,Non-specific" bitfld.quad 0x00 5. "DE,Deferred error generation enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled" group.quad spr:0x30F22++0x00 line.quad 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register - ER0PFGCDN_EL1 - Record 0" hexmask.quad.long 0x00 0.--31. 1. "CDN,Countdown value" group.quad spr:0x30543++0x00 line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register" bitfld.quad 0x00 63. "NS,Non-secure attribute" "Secure,Non-secure" hexmask.quad 0x00 0.--39. 1. "PADDR,Physical Address" group.quad spr:0x30550++0x00 line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0 - ER0MISC0_EL1 - Record 0" bitfld.quad 0x00 47. "OFO,Sticky overflow bit for other errors" "No overflow,Overflow" hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count for other errors" newline bitfld.quad 0x00 39. "OFR,Sticky overflow bit for repeat errors" "No overflow,Overflow" hexmask.quad.byte 0x00 32.--38. 1. "CECR,Corrected error count for repeat errors" newline bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 25. "SUBBANK,Dependent on unit from which error was detected" "0,1" newline bitfld.quad 0x00 23.--24. "BANK,Dependent on unit from which error was detected" "0,1,2,3" bitfld.quad 0x00 19.--22. "SUBARRAY,Dependent on unit from which error was detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.word 0x00 6.--18. 1. "INDEX,Indicates the index that contained the error" bitfld.quad 0x00 4.--5. "ARRAY,Dependent on unit from which error was detected" "L2 Tag RAM/LS Tag RAM 0/Tag,L2 Data RAM/LS Tag RAM1/Data,LS Data RAM/Micro-OP cache,CHI Error/LS Tag RAM 2" bitfld.quad 0x00 0.--3. "UNIT,Unit which detected error" "Reserved,L1 Instruction Cache,Reserved,Reserved,L1 Data Cache,L2 TLB,Reserved,Reserved,L2 Cache,?..." group.quad spr:0x30551++0x00 line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1" else rgroup.quad spr:0x30540++0x00 line.quad 0x00 "ERXFR_EL1,Selected Error Record Feature Register - CLUSTERRAS_ERR1FR - Record 1" bitfld.quad 0x00 18.--19. "CEO,Corrected error overwrite" "No overwrite,?..." bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..." newline bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented" bitfld.quad 0x00 12.--14. "CEC,Corrected error counter" "Reserved,Reserved,Implemented/8-bit,?..." newline bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..." newline bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 2.--3. "DE,Deferred error enable" "Reserved,Enabled,?..." bitfld.quad 0x00 0.--1. "ED,Error detection and correction[Lock/Split]" "Reserved,Reserved,Implemented,?..." group.quad spr:0x30541++0x00 line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register - CLUSTERRAS_ER1CTLR - Record 1" bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled" bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled" group.quad spr:0x30542++0x00 line.quad 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register - CLUSTERRAS_ER1STATUS - Record 1" bitfld.quad 0x00 31. "AV,Address valid" "Not valid,?..." bitfld.quad 0x00 30. "V,Status register valid" "Not valid,Valid" newline bitfld.quad 0x00 29. "UE,Uncorrected Error" "No error,>=1 error" bitfld.quad 0x00 28. "ER,Error reported" "No error,?..." newline bitfld.quad 0x00 27. "OF,Error overflow" "No error,>=1 error" bitfld.quad 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid" newline bitfld.quad 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..." bitfld.quad 0x00 23. "DE,Deferred errors" "No error,>=1 error" newline bitfld.quad 0x00 22. "PN,Poison" "Corrupt,Poison" bitfld.quad 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..." newline hexmask.quad.byte 0x00 8.--15. 1. "IERR,Implementation defined error code" newline hexmask.quad.byte 0x00 0.--7. 1. "SERR,Architecturally-defined primary error code" group.quad spr:0x30F20++0x00 line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register - CLUSTERRAS_ER1PFGF - Record 1" bitfld.quad 0x00 31. "PFG,Pseudo fault generation" "Not supported,Supported" bitfld.quad 0x00 30. "R,Restartable bit" "Not supported,Supported" newline bitfld.quad 0x00 6. "CE,Corrected error generation" "Not supported,Supported" newline bitfld.quad 0x00 5. "DE,Deferred error generation" "Not supported,Supported" bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,Supported" newline bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,Supported" bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,Supported" newline bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Reserved,Supported" group.quad spr:0x30F21++0x00 line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register - CLUSTERRAS_ER1PFGCTL - Record 1" bitfld.quad 0x00 31. "CDNEN,Countdown enable. Control transfers from the value that is held in the ERR0PFGCDN into the Error Generation Counter" "Disabled,Enabled" bitfld.quad 0x00 30. "R,Restart. Controls whether on reaching zero the Error Generation Counter restarts from the ext-CLUSTERRAS_ERR0PFGCDN value or stops" "Disabled,Enabled" newline bitfld.quad 0x00 6. "CE,Corrected error generation enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "DE,Deferred error generation enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled" group.quad spr:0x30F22++0x00 line.quad 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register - CLUSTERRAS_ER1PFGCDN - Record 1" hexmask.quad.long 0x00 0.--31. 1. "CDN,Countdown value" group.quad spr:0x30550++0x00 line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0 - CLUSTERRAS_ER0MISC0 - Record 0 - DSU RAMs" bitfld.quad 0x00 47. "OFO,Sticky overflow bit for other errors" "No overflow,Overflow" hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count for other errors" newline bitfld.quad 0x00 39. "OFR,Sticky overflow bit for repeat errors" "No overflow,Overflow" hexmask.quad.byte 0x00 32.--38. 1. "CECR,Corrected error count for repeat errors" newline bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.tbyte 0x00 6.--23. 1. "INDX,Indicates the index that contained the error" newline bitfld.quad 0x00 1.--3. "LVL,Indicates the level that contained the error" "Reserved,Reserved,Level 3,?..." bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "Data,?..." group.quad spr:0x30551++0x00 line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1 - CLUSTERRAS_ER1MISC1 - Record 1" group.quad spr:0x30552++0x00 line.quad 0x00 "ERXMISC2_EL1,Selected Error Record Miscellaneous Register 2 - CLUSTERRAS_ER1MISC2 - Record 1" group.quad spr:0x30553++0x00 line.quad 0x00 "ERXMISC3_EL1,Selected Error Record Miscellaneous Register 3 - CLUSTERRAS_ER1MISC3 - Record 1" endif newline tree.end tree "Cluster PMU Registers" group.quad spr:0x30F50++0x00 line.quad 0x00 "CLUSTERPMCR_EL1,Cluster Performance Monitors Control Register (EL1)" hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.quad 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset" bitfld.quad 0x00 1. "P,Event Counter Reset" "No reset,Reset" bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad spr:0x30F51++0x00 line.quad 0x00 "CLUSTERPMCNTENSET_EL1,Cluster Performance Monitors Count Enable Set Register (EL1)" bitfld.quad 0x00 31. "C,Enables the cycle counter register [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.quad 0x00 5. "P5,Event counter CLUSTERPMEVCNTR5 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 4. "P4,Event counter CLUSTERPMEVCNTR4 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 3. "P3,Event counter CLUSTERPMEVCNTR3 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.quad 0x00 2. "P2,Event counter CLUSTERPMEVCNTR2 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 1. "P1,Event counter CLUSTERPMEVCNTR1 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 0. "P0,Event counter CLUSTERPMEVCNTR0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" group.quad spr:0x30F52++0x00 line.quad 0x00 "CLUSTERPMCNTENCLR_EL1,Cluster Performance Monitors Count Enable Clear Register (EL1)" bitfld.quad 0x00 31. "C,Disables the cycle counter register [Read/Write]" "Disabled/No effect,Enabled/Disable" newline bitfld.quad 0x00 5. "P5,Event counter CLUSTERPMEVCNTR5 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 4. "P4,Event counter CLUSTERPMEVCNTR4 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 3. "P3,Event counter CLUSTERPMEVCNTR3 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline bitfld.quad 0x00 2. "P2,Event counter CLUSTERPMEVCNTR2 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 1. "P1,Event counter CLUSTERPMEVCNTR1 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 0. "P0,Event counter CLUSTERPMEVCNTR0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x30F53++0x00 line.quad 0x00 "CLUSTERPMOVSSET_EL1,Cluster Performance Monitors Overflow Flag Status Set Register (EL1)" bitfld.quad 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Set" newline bitfld.quad 0x00 5. "P5,CLUSTERPMEVCNTR5 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.quad 0x00 4. "P4,CLUSTERPMEVCNTR4 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.quad 0x00 3. "P3,CLUSTERPMEVCNTR3 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" newline bitfld.quad 0x00 2. "P2,CLUSTERPMEVCNTR2 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.quad 0x00 1. "P1,CLUSTERPMEVCNTR1 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.quad 0x00 0. "P0,CLUSTERPMEVCNTR0 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" group.quad spr:0x30F54++0x00 line.quad 0x00 "CLUSTERPMOVSCLR_EL1,Cluster Performance Monitors Overflow Flag Status Clear Register (EL1)" eventfld.quad 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.quad 0x00 5. "P5,CLUSTERPMEVCNTR5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 4. "P4,CLUSTERPMEVCNTR4 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 3. "P3,CLUSTERPMEVCNTR3 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.quad 0x00 2. "P2,CLUSTERPMEVCNTR2 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 1. "P1,CLUSTERPMEVCNTR1 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.quad 0x00 0. "P0,CLUSTERPMEVCNTR0 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" group.quad spr:0x30F55++0x00 line.quad 0x00 "CLUSTERPMSELR_EL1,Cluster Performance Monitors Event Counter Selection Register (EL1)" bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.quad spr:0x30F56++0x00 line.quad 0x00 "CLUSTERPMINTENSET_EL1,Cluster Performance Monitors Interrupt Enable Set Register (EL1)" bitfld.quad 0x00 31. "C,PMCCNTR Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.quad 0x00 5. "P5,CLUSTERPMEVCNTR5 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 4. "P4,CLUSTERPMEVCNTR4 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 3. "P3,CLUSTERPMEVCNTR3 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.quad 0x00 2. "P2,CLUSTERPMEVCNTR2 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 1. "P1,CLUSTERPMEVCNTR1 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.quad 0x00 0. "P0,CLUSTERPMEVCNTR0 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" group.quad spr:0x30F57++0x00 line.quad 0x00 "CLUSTERPMINTENCLR_EL1,Cluster Performance Monitors Interrupt Enable Clear Register (EL1)" eventfld.quad 0x00 31. "C,PMCCNTR Overflow Interrupt Request Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.quad 0x00 5. "P5,CLUSTERPMEVCNTR5 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 4. "P4,CLUSTERPMEVCNTR4 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 3. "P3,CLUSTERPMEVCNTR3 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.quad 0x00 2. "P2,CLUSTERPMEVCNTR2 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 1. "P1,CLUSTERPMEVCNTR1 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.quad 0x00 0. "P0,CLUSTERPMEVCNTR0 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x30F60++0x00 line.quad 0x00 "CLUSTERPMCCNTR_EL1,Cluster Performance Monitors Cycle Counter (EL1)" group.quad spr:0x30F61++0x00 line.quad 0x00 "CLUSTERPMXEVTYPER_EL1,Cluster Selected Event Type and Filter Register (EL1)" bitfld.quad 0x00 31. "S,Disable counting of events that are generated by Secure transactions" "No,Yes" bitfld.quad 0x00 29. "NS,Disable counting of events that are generated by Non-secure transactions" "No,Yes" newline hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.quad spr:0x30F62++0x00 line.quad 0x00 "CLUSTERPMXEVCNTR_EL1,Cluster Performance Monitors Selected Event Counter Register (EL1)" group.quad spr:0x36F63++0x00 line.quad 0x00 "CLUSTERPMMDCR_EL3,Cluster Monitor Debug Configuration Register (EL3)" bitfld.quad 0x00 0. "SPME,Secure performance monitors enable" "Disabled,Enabled" tree.open "Common Event Identification Registers" rgroup.quad spr:0x30F64++0x00 line.quad 0x00 "CLUSTERPMCEID0_EL1,Cluster Performance Monitors Common Event Identification Register 0 (EL1)" bitfld.quad 0x00 30. "CHAIN,CHAIN event implemented" "Reserved,Implemented" bitfld.quad 0x00 29. "BUS_CYCLES,BUS_CYCLES event implemented" "Reserved,Implemented" newline bitfld.quad 0x00 26. "MEMORY_ERROR,MEMORY_ERROR event implemented" "Reserved,Implemented" bitfld.quad 0x00 25. "BUS_ACCESS,BUS_ACCESS event implemented" "Reserved,Implemented" bitfld.quad 0x00 17. "CYCLES,CYCLES event implemented" "Reserved,Implemented" rgroup.quad spr:0x30F65++0x00 line.quad 0x00 "CLUSTERPMCEID1_EL1,Cluster Common Event Identification ID1 Register (EL1)" bitfld.quad 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Reserved,Implemented" bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Reserved,Implemented" bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Reserved,Implemented" newline bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented" tree.end newline group.quad spr:0x30F66++0x00 line.quad 0x00 "CLUSTERPMCLAIMSET_EL1,Cluster Performance Monitor Claim Tag Set Register (EL1)" bitfld.quad 0x00 3. "SET[3],Set the claim tag bit 3 [Write/Read]" "No effect/Not implemented,Set/Implemented" bitfld.quad 0x00 2. "[2],Set the claim tag bit 2 [Write/Read]" "No effect/Not implemented,Set/Implemented" bitfld.quad 0x00 1. "[1],Set the claim tag bit 1 [Write/Read]" "No effect/Not implemented,Set/Implemented" newline bitfld.quad 0x00 0. "[0],Set the claim tag bit 0 [Write/Read]" "No effect/Not implemented,Set/Implemented" group.quad spr:0x30F67++0x00 line.quad 0x00 "CLUSTERPMCLAIMCLR_EL1,Cluster Performance Monitor Claim Tag Clear Register (EL1)" bitfld.quad 0x00 3. "CLR[3],Clear the claim tag bit 3 [Write/Read]" "No effect/Not implemented,Clear/Implemented" bitfld.quad 0x00 2. "[2],Clear the claim tag bit 2 [Write/Read]" "No effect/Not implemented,Clear/Implemented" bitfld.quad 0x00 1. "[1],Clear the claim tag bit 1 [Write/Read]" "No effect/Not implemented,Clear/Implemented" newline bitfld.quad 0x00 0. "[0],Clear the claim tag bit 0 [Write/Read]" "No effect/Not implemented,Clear/Implemented" tree.end tree.end tree.end tree.open ("AArch32") tree "System Control and Configuration" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register" tree.end tree "System Instructions" wgroup.long c15:0x0017++0x00 line.long 0x00 "ICIALLUIS,ICIALLUIS" wgroup.long c15:0x0057++0x00 line.long 0x00 "ICIALLU,ICIALLU" wgroup.long c15:0x0157++0x00 line.long 0x00 "ICIMVAU,ICIMVAU" wgroup.long c15:0x3147++0x00 line.long 0x00 "DCZVA,DCZVA" wgroup.long c15:0x0167++0x00 line.long 0x00 "DCIMVAC,DCIMVAC" wgroup.long c15:0x0267++0x00 line.long 0x00 "DCISW,DCISW" wgroup.long c15:0x01A7++0x00 line.long 0x00 "DCCMVAC,DCCMVAC" wgroup.long c15:0x02A7++0x00 line.long 0x00 "DCCSW,DCCSW" wgroup.long c15:0x01B7++0x00 line.long 0x00 "DCCMVAU,DCCMVAU" wgroup.long c15:0x01E7++0x00 line.long 0x00 "DCCIMVAC,DCCIMVAC" wgroup.long c15:0x02E7++0x00 line.long 0x00 "DCCISW,DCCISW" wgroup.long c15:0x0087++0x00 line.long 0x00 "ATS1CPR,ATS1CPR" wgroup.long c15:0x0097++0x00 line.long 0x00 "ATS1CPRP,ATS1CPRP" wgroup.long c15:0x0187++0x00 line.long 0x00 "ATS1CPW,ATS1CPW" wgroup.long c15:0x0197++0x00 line.long 0x00 "ATS1CPWP,ATS1CPWP" wgroup.long c15:0x0287++0x00 line.long 0x00 "ATS1CUR,ATS1CUR" wgroup.long c15:0x0387++0x00 line.long 0x00 "ATS1CUW,ATS1CUW" wgroup.long c15:0x0487++0x00 line.long 0x00 "ATS12NSOPR,ATS12NSOPR" wgroup.long c15:0x0587++0x00 line.long 0x00 "ATS12NSOPW,ATS12NSOPW" wgroup.long c15:0x0687++0x00 line.long 0x00 "ATS12NSOUR,ATS12NSOUR" wgroup.long c15:0x0787++0x00 line.long 0x00 "ATS12NSOUW,ATS12NSOUW" wgroup.long c15:0x4087++0x00 line.long 0x00 "ATS1HR,ATS1HR" wgroup.long c15:0x4187++0x00 line.long 0x00 "ATS1HW,ATS1HW" wgroup.long c15:0x0078++0x00 line.long 0x00 "TLBIALL,TLBIALL" wgroup.long c15:0x0178++0x00 line.long 0x00 "TLBIMVA,TLBIMVA" wgroup.long c15:0x4178++0x00 line.long 0x00 "TLBIMVAH,Invalidate Hyp unified TLB entry by MVA" wgroup.long c15:0x0278++0x00 line.long 0x00 "TLBIASID,TLBIASID" wgroup.long c15:0x0378++0x00 line.long 0x00 "TLBIMVAA,TLBIMVAA" wgroup.long c15:0x0578++0x00 line.long 0x00 "TLBIMVAL,TLBIMVAL" wgroup.long c15:0x0778++0x00 line.long 0x00 "TLBIMVAAL,TLBIMVAAL" wgroup.long c15:0x0038++0x00 line.long 0x00 "TLBIALLIS,TLBIALLIS" wgroup.long c15:0x0138++0x00 line.long 0x00 "TLBIMVAIS,TLBIMVAIS" wgroup.long c15:0x0238++0x00 line.long 0x00 "TLBIASIDIS,TLBIASIDIS" wgroup.long c15:0x0338++0x00 line.long 0x00 "TLBIMVAAIS,TLBIMVAAIS" wgroup.long c15:0x0538++0x00 line.long 0x00 "TLBIMVALIS,TLBIMVALIS" wgroup.long c15:0x0738++0x00 line.long 0x00 "TLBIMVAALI,TLBIMVAALI" wgroup.long c15:0x4108++0x00 line.long 0x00 "TLBIIPAS2IS,TLBIIPAS2IS" wgroup.long c15:0x4508++0x00 line.long 0x00 "TLBIIPAS2LIS,TLBIIPAS2LIS" wgroup.long c15:0x4148++0x00 line.long 0x00 "TLBIIPAS2,TLBIIPAS2" wgroup.long c15:0x4548++0x00 line.long 0x00 "TLBIIPAS2L,TLBIIPAS2L" wgroup.long c15:0x4178++0x00 line.long 0x00 "TLBIIPAS2L,TLBIIPAS2L" wgroup.long c15:0x4578++0x00 line.long 0x00 "TLBIMVALH,TLBIMVALH" wgroup.long c15:0x4138++0x00 line.long 0x00 "TLBIMVAHIS,TLBIMVAHIS" wgroup.long c15:0x4538++0x00 line.long 0x00 "TLBIMVALHIS,TLBIMVALHIS" wgroup.long c15:0x4078++0x00 line.long 0x00 "TLBIALLH,TLBIALLH" wgroup.long c15:0x4038++0x00 line.long 0x00 "TLBIALLHIS,TLBIALLHIS" wgroup.long c15:0x4478++0x00 line.long 0x00 "TLBIALLNSNH,TLBIALLNSNH" wgroup.long c15:0x4438++0x00 line.long 0x00 "TLBIALLNSNHIS,TLBIALLNSNHIS" wgroup.long c15:0x0457++0x00 line.long 0x00 "CP15ISB,CP15ISB" wgroup.long c15:0x04A7++0x00 line.long 0x00 "CP15DSB,CP15DSB" wgroup.long c15:0x05A7++0x00 line.long 0x00 "CP15DMB,CP15DMB" tree.end tree "Virtualization Extensions" group.long c15:0x3054++0x00 line.long 0x00 "DSPSR,Debug Saved Program Status Register" bitfld.long 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.long 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.long 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.long 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.long 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.long 0x00 22. "PAN,Privileged access never" "No,Yes" bitfld.long 0x00 21. "SS,Software step" "0,1" bitfld.long 0x00 20. "IL,Illegal execution state" "0,1" newline bitfld.long 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "GE,Greater than or equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9. "E,Endianness state bit" "Little,Big" newline bitfld.long 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.long 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.long 0x00 6. "F,FIQ mask bit" "Not masked,Masked" bitfld.long 0x00 5. "T,T32 Instruction set state" "A32,T32" newline bitfld.long 0x00 4. "M[4],Execution state that the exception was taken from" ",AArch32" bitfld.long 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,Monitor,Abort,,,Hyp,Undefined,,,,System" group.long c15:0x3154++0x00 line.long 0x00 "DLR,Debug Link Register" tree.end tree "System Performance Monitor" group.long c15:0x00C9++0x00 line.long 0x00 "PMCR,Performance Monitors Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" newline rbitfld.long 0x00 11.--15. "N,Number of event counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,20,?..." bitfld.long 0x00 7. "LP,Long event counter enable" "Disabled,Enabled" bitfld.long 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled" bitfld.long 0x00 5. "DP,Disable cycle counter when event counting is prohibited" "No,Yes" newline bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter reset" "No effect,Reset" bitfld.long 0x00 1. "P,Performance Counter reset" "No effect,Reset" bitfld.long 0x00 0. "E,All Counters enable" "Disabled,Enabled" group.long c15:0x01C9++0x00 line.long 0x00 "PMCNTENSET,Performance Monitors Count Enable Set Register" bitfld.long 0x00 31. "C,Cycle counter register PMCCNTR enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.long 0x00 5. "P5,Event counter PMEVCNTR5 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 4. "P4,Event counter PMEVCNTR4 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 3. "P3,Event counter PMEVCNTR3 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.long 0x00 2. "P2,Event counter PMEVCNTR2 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 1. "P1,Event counter PMEVCNTR1 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 0. "P0,Event counter PMEVCNTR0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" group.long c15:0x02C9++0x00 line.long 0x00 "PMCNTENCLR,Performance Monitors Count Enable Clear Register" bitfld.long 0x00 31. "C,Cycle counter register PMCCNTR disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline bitfld.long 0x00 5. "P5,Event counter PMEVCNTR5 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 4. "P4,Event counter PMEVCNTR4 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 3. "P3,Event counter PMEVCNTR3 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline bitfld.long 0x00 2. "P2,Event counter PMEVCNTR2 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 1. "P1,Event counter PMEVCNTR1 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 0. "P0,Event counter PMEVCNTR0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.long c15:0x03C9++0x00 line.long 0x00 "PMOVSR,Performance Monitors Overflow Flag Status Register" eventfld.long 0x00 31. "C,Cycle counter register PMCCNTR overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 5. "P5,Event counter PMEVCNTR5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 4. "P4,Event counter PMEVCNTR4 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 3. "P3,Event counter PMEVCNTR3 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 2. "P2,Event counter PMEVCNTR2 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 1. "P1,Event counter PMEVCNTR1 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 0. "P0,Event counter PMEVCNTR0 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" wgroup.long c15:0x04C9++0x00 line.long 0x00 "PMSWINC,Performance Monitors Software Increment Register" bitfld.long 0x00 5. "P5,Event counter PMEVCNTR5 software increment bit" "No effect,Increment" bitfld.long 0x00 4. "P4,Event counter PMEVCNTR4 software increment bit" "No effect,Increment" bitfld.long 0x00 3. "P3,Event counter PMEVCNTR3 software increment bit" "No effect,Increment" newline bitfld.long 0x00 2. "P2,Event counter PMEVCNTR2 software increment bit" "No effect,Increment" bitfld.long 0x00 1. "P1,Event counter PMEVCNTR1 software increment bit" "No effect,Increment" bitfld.long 0x00 0. "P0,Event counter PMEVCNTR0 software increment bit" "No effect,Increment" group.long c15:0x05C9++0x00 line.long 0x00 "PMSELR,Performance Monitors Event Counter Selection Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,31" tree.open "Common Event Identification Registers" rgroup.long c15:0x06C9++0x00 line.long 0x00 "PMCEID0,Performance Monitors Common Event Identification Register 0" bitfld.long 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,?..." bitfld.long 0x00 30. "CHAIN,Chain" "Reserved,Implemented" bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented" newline bitfld.long 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Reserved,Implemented" bitfld.long 0x00 27. "INST_SPEC,Instruction speculatively executed" "Reserved,Implemented" bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented" newline bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented" bitfld.long 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Reserved,Implemented" bitfld.long 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Reserved,Implemented" newline bitfld.long 0x00 22. "L2D_CACHE,Level 2 data cache access" "Reserved,Implemented" bitfld.long 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Reserved,Implemented" bitfld.long 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Reserved,Implemented" newline bitfld.long 0x00 19. "MEM_ACCESS,Data memory access" "Reserved,Implemented" bitfld.long 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Reserved,Implemented" bitfld.long 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented" newline bitfld.long 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented" bitfld.long 0x00 15. "UNALIGNED_LDST_RETIRED,UNALIGNED_LDST_RETIRED" "Not implemented,?..." bitfld.long 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,?..." newline bitfld.long 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,?..." bitfld.long 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,?..." bitfld.long 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented" newline bitfld.long 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented" bitfld.long 0x00 9. "EXC_TAKEN,Exception taken" "Reserved,Implemented" bitfld.long 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Reserved,Implemented" newline bitfld.long 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,?..." bitfld.long 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,?..." bitfld.long 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Reserved,Implemented" newline bitfld.long 0x00 4. "L1D_CACHE,Level 1 data cache access" "Reserved,Implemented" bitfld.long 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Reserved,Implemented" bitfld.long 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Reserved,Implemented" newline bitfld.long 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Reserved,Implemented" bitfld.long 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented" rgroup.long c15:0x07C9++0x00 line.long 0x00 "PMCEID1,Performance Monitors Common Event Identification Register 1" bitfld.long 0x00 23. "LL_CACHE_MISS_RD,Attributable last level cache memory read miss" "Reserved,Implemented" newline bitfld.long 0x00 22. "LL_CACHE_RD,Attributable last level cache memory read" "Reserved,Implemented" bitfld.long 0x00 21. "ITLB_WLK,Attributable instruction TLB access with at least one translation table walk" "Reserved,Implemented" bitfld.long 0x00 20. "DTLB_WLK,Attributable data or unified TLB access with at least one translation table walk" "Reserved,Implemented" newline bitfld.long 0x00 17. "REMOTE_ACCESS,Attributable access to another socket in a multi-socket system" "Reserved,Implemented" bitfld.long 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Reserved,Implemented" newline bitfld.long 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Reserved,Implemented" bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Reserved,Implemented" newline bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Reserved,Implemented" bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented" newline bitfld.long 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Reserved,Implemented" bitfld.long 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Reserved,Implemented" newline bitfld.long 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Reserved,Implemented" bitfld.long 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Reserved,Implemented" bitfld.long 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Reserved,Implemented" newline bitfld.long 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Reserved,Implemented" bitfld.long 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Reserved,Implemented" rgroup.long c15:0x04E9++0x00 line.long 0x00 "PMCEID2,Common Event Identification Register" rgroup.long c15:0x05E9++0x00 line.long 0x00 "PMCEID3,Common Event Identification Register" tree.end newline group.long c15:0x00D9++0x00 line.long 0x00 "PMCCNTR,Performance Monitors Cycle Count Register (32-bit)" group.quad c15:0x10090++0x01 line.quad 0x00 "PMCCNTR,Performance Monitors Cycle Count Register (64-bit)" if (((per.l(c15:0x05C9))&0x1F)==0x1F) group.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type Register - PMCCFILTR" bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" newline bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" elif (((per.l(c15:0x05C9))&0x1F)<=0x05) group.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type Register - PMEVTYPER" bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" newline bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.long 0x00 26. "M,Count events in secure EL3 [P=0/1]" "Yes/No,No/Yes" newline hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event to count" else rgroup.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type Register - PMEVTYPER" endif group.long c15:0x02D9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitors Selected Event Counter Register" group.long c15:0x00E9++0x00 line.long 0x00 "PMUSERENR,Performance Monitors User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,EL0 access enable bit" "Disabled,Enabled" newline group.long c15:0x03E9++0x00 line.long 0x00 "PMOVSSET,Performance Monitors Overflow Status Flags Set Register" bitfld.long 0x00 31. "C,Cycle counter overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" newline bitfld.long 0x00 5. "P5,Event counter PMEVCNTR5 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" bitfld.long 0x00 4. "P4,Event counter PMEVCNTR4 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" bitfld.long 0x00 3. "P3,Event counter PMEVCNTR3 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" newline bitfld.long 0x00 2. "P2,Event counter PMEVCNTR2 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" bitfld.long 0x00 1. "P1,Event counter PMEVCNTR1 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" bitfld.long 0x00 0. "P0,Event counter PMEVCNTR0 overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set overflow" group.long c15:(0x008E+0x0)++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Counter Register 0" group.long c15:(0x008E+0x100)++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Counter Register 1" group.long c15:(0x008E+0x200)++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Counter Register 2" group.long c15:(0x008E+0x300)++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Counter Register 3" group.long c15:(0x008E+0x400)++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Counter Register 4" group.long c15:(0x008E+0x500)++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Counter Register 5" group.long c15:(0x00CE+0x0)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Event Type Register 0" bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.long 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline bitfld.long 0x00 24. "SH,Count events in secure EL2 [NSH=0/1]" "Yes/No,No/Yes" hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.long c15:(0x00CE+0x100)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Event Type Register 1" bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.long 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline bitfld.long 0x00 24. "SH,Count events in secure EL2 [NSH=0/1]" "Yes/No,No/Yes" hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.long c15:(0x00CE+0x200)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Event Type Register 2" bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.long 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline bitfld.long 0x00 24. "SH,Count events in secure EL2 [NSH=0/1]" "Yes/No,No/Yes" hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.long c15:(0x00CE+0x300)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Event Type Register 3" bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.long 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline bitfld.long 0x00 24. "SH,Count events in secure EL2 [NSH=0/1]" "Yes/No,No/Yes" hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.long c15:(0x00CE+0x400)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Event Type Register 4" bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.long 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline bitfld.long 0x00 24. "SH,Count events in secure EL2 [NSH=0/1]" "Yes/No,No/Yes" hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.long c15:(0x00CE+0x500)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Event Type Register 5" bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" newline bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.long 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline bitfld.long 0x00 24. "SH,Count events in secure EL2 [NSH=0/1]" "Yes/No,No/Yes" hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes" bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes" bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes" newline bitfld.long 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" tree.end tree "System Timer Registers" rgroup.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter-timer Frequency Register" rgroup.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter-timer Physical Count Register" rgroup.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter-timer Virtual Count Register" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter-timer Physical Timer TimerValue Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter-timer Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter-timer Physical Timer CompareValue Register" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter-timer Virtual Timer TimerValue Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter-timer Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter-timer Virtual Timer CompareValue Register" tree.end tree "Debug Registers" rgroup.long c14:0x0010++0x00 line.long 0x00 "DBGDSCRINT,Debug Status And Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX register full" "Empty,Full" newline bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" bitfld.long 0x00 17. "SPNIDDIS,Secure privileged non-invasive debug disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure privileged invasive debug disable" "No,Yes" newline bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" bitfld.long 0x00 12. "UDCCDIS,User mode access to communications channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software Breakpoint (BKPT),Reserved,Vector catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..." wgroup.long c14:0x0050++0x00 line.long 0x00 "DBGDTRTXINT,Debug Data Transmit Register (Internal View)" rgroup.long c14:0x0050++0x00 line.long 0x00 "DBGDTRRXINT,Debug Data Receive Register (Internal View)" tree.end tree.end AUTOINDENT.OFF AUTOINDENT.POP tree.open "Interrupt Controller (GIC-600)" AUTOINDENT.PUSH AUTOINDENT.OFF base COMP.BASE("GICD",-1.) width 17. tree "Distributor Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 6. " DS ,Disable Security" "No,Yes" textline " " bitfld.long 0x00 5. " ARE_NS ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_S ,Affinity Routing Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ENABLEGRP1S ,Enable Secure Group 1 interrupts" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" bitfld.long 0x00 4. " ARE_NS ,Affinity Routing Enable" "Reserved,Enabled" textline " " bitfld.long 0x00 1. " ENABLEGRP1A ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" rbitfld.long 0x00 31. " RWP ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending" bitfld.long 0x00 7. " E1NWF ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled" rbitfld.long 0x00 6. " DS ,Disable Security" "Reserved,Yes" textline " " bitfld.long 0x00 4. " ARE ,Affinity Routing Enable" "Reserved,Enabled" bitfld.long 0x00 1. " ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 25. " NO1N ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported" bitfld.long 0x00 24. " A3V ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported" bitfld.long 0x00 19.--23. " IDBITS ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." textline " " bitfld.long 0x00 18. " DVIS ,Direct virtual LPI injection support" "Not supported,Supported" bitfld.long 0x00 17. " LPIS ,Indicates whether the implementation supports LPIs" "Not supported,Supported" bitfld.long 0x00 16. " MBIS ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported" textline " " bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" bitfld.long 0x00 5.--7. " CPUNUMBER ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8" bitfld.long 0x00 0.--4. " ITLN ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved" rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?,GIC-600,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0020)) group.long 0x0020++0x03 line.long 0x00 "GICD_FCTLR,Function Control Register" bitfld.long 0x00 21. " DCC ,Disable Cache Conversion (DCC)" "Disable,Enable" bitfld.long 0x00 18. " SLPIA ,Strict LPI Allocation (SLPIA).Controls whether LPI reverts to a fixed index behavior. This bit can only be written when in full sleep (quiescent)." "Not Strict,Strict" bitfld.long 0x00 16.--17. " NSACR , Non-secure Access Control. This is the value that is used ifa SPI has an error." "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " hexmask.long.word 0x00 4.--13. 1. " CGO ,One bit per clock gate: 1 = Leave clock running. 0 = Use full clock gating." bitfld.long 0x00 0. " SIP ,Scrub in progress. This bit is read and written by software. When a scrub is complete, the GIC clears the bit to 0." "Completed,In Progress" else group.long 0x0020++0x03 line.long 0x00 "GICD_FCTLR,Function Control Register" bitfld.long 0x00 21. " DCC ,Disable Cache Conversion (DCC)" "Disable,Enable" bitfld.long 0x00 18. " SLPIA ,Strict LPI Allocation (SLPIA).Controls whether LPI reverts to a fixed index behavior. This bit can only be written when in full sleep (quiescent)." "Not Strict,Strict" textline " " hexmask.long.word 0x00 4.--13. 1. " CGO ,One bit per clock gate: 1 = Leave clock running. 0 = Use full clock gating." bitfld.long 0x00 0. " SIP ,Scrub in progress. This bit is read and written by software. When a scrub is complete, the GIC clears the bit to 0." "Completed,In Progress" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0024))) group.long 0xE08++0x03 line.long 0x00 "GICD_SAC,Secure Access Control Register" bitfld.long 0x00 2. " GICPNS ,Allow Non-secure access to the GICP registers. This enables Non-secure access to Secure PMU data." "Not Allowed,Allowed" bitfld.long 0x00 1. " GICTNS ,Allow Non-secure access to the GICT registers. This enables Non-secure access to Secure trace data." "Not Allowed,Allowed" bitfld.long 0x00 0. " DSL ,Disable Security Lock. WriteOnce (WO) bit to lock GICD_CTLR.DS to be WO at its current value." "0,1" else hgroup.long 0xE08++0x03 hide.long 0x00 "GICD_SAC,Secure Access Control Register" endif wgroup.long 0x40++0x03 line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" wgroup.long 0x48++0x03 line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50)) wgroup.long 0x50++0x03 line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x50++0x03 hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58)) wgroup.long 0x58++0x03 line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x58++0x03 hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)" endif tree "Message Based Alias Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000) wgroup.long 0x40++0x03 line.long 0x00 "GICA_SETSPI_NSR,Non-secure SPI Set Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" wgroup.long 0x48++0x03 line.long 0x00 "GICA_CLRSPI_NSR,Non-secure SPI Clear Register" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50)) wgroup.long 0x50++0x03 line.long 0x00 "GICA_SETSPI_SR,Secure SPI Set Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x50++0x03 hide.long 0x00 "GICA_SETSPI_SR,Secure SPI Set Register (Non-secure access)" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58)) wgroup.long 0x58++0x03 line.long 0x00 "GICA_CLRSPI_SR,Secure SPI Clear Register (Secure access)" hexmask.long.word 0x00 0.--9. 1. " INTID ,The INTID of the SPI" else hgroup.long 0x58++0x03 hide.long 0x00 "GICA_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)" endif else hgroup.long 0x40++0x03 hide.long 0x00 "GICA_SETSPI_NSR,Non-secure SPI Set Register" hgroup.long 0x48++0x03 hide.long 0x00 "GICA_CLRSPI_NSR,Non-secure SPI Clear Register" hgroup.long 0x50++0x03 hide.long 0x00 "GICA_SETSPI_SR,Secure SPI Set Register" hgroup.long 0x58++0x03 hide.long 0x00 "GICA_CLRSPI_SR,Secure SPI Clear Register" endif tree.end width 17. tree "Group Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080)) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x0080++0x03 hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 " endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x00E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x00F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1" elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" endif tree.end width 24. tree "Set/Clear Enable Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0100++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" endif tree.end width 22. tree "Set/Clear Pending Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0200++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0300++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" newline newline newline newline newline newline newline newline newline newline else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active" else hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active" else hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active" else hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active" else hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active" else hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active" else hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active" else hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active" else hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active" else hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active" else hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active" else hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active" else hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active" else hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active" else hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active" else hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" endif tree.end width 20. tree "Priority Registers" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x400++0x03 hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hgroup.long 0x404++0x03 hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hgroup.long 0x408++0x03 hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hgroup.long 0x40C++0x03 hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hgroup.long 0x410++0x03 hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hgroup.long 0x414++0x03 hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hgroup.long 0x418++0x03 hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hgroup.long 0x41C++0x03 hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" else group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif tree.end width 19. tree "Interrupt Targets Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1) hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SGI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SGI)" "Level,Edge" group.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (PPI)" "Level,Edge" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SPI)" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SPI)" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SPI)" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (SPI)" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0 (SPI)" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif tree.end width 17. tree "Interrupt Group Modifier Registers" hgroup.long 0x0D00++0x03 hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)) group.long 0x0D04++0x03 line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" bitfld.long 0x00 31. " GMB63 ,Group Modifier Bit 63" "0,1" bitfld.long 0x00 30. " GMB62 ,Group Modifier Bit 62" "0,1" bitfld.long 0x00 29. " GMB61 ,Group Modifier Bit 61" "0,1" textline " " bitfld.long 0x00 28. " GMB60 ,Group Modifier Bit 60" "0,1" bitfld.long 0x00 27. " GMB59 ,Group Modifier Bit 59" "0,1" bitfld.long 0x00 26. " GMB58 ,Group Modifier Bit 58" "0,1" textline " " bitfld.long 0x00 25. " GMB57 ,Group Modifier Bit 57" "0,1" bitfld.long 0x00 24. " GMB56 ,Group Modifier Bit 56" "0,1" bitfld.long 0x00 23. " GMB55 ,Group Modifier Bit 55" "0,1" textline " " bitfld.long 0x00 22. " GMB54 ,Group Modifier Bit 54" "0,1" bitfld.long 0x00 21. " GMB53 ,Group Modifier Bit 53" "0,1" bitfld.long 0x00 20. " GMB52 ,Group Modifier Bit 52" "0,1" textline " " bitfld.long 0x00 19. " GMB51 ,Group Modifier Bit 51" "0,1" bitfld.long 0x00 18. " GMB50 ,Group Modifier Bit 50" "0,1" bitfld.long 0x00 17. " GMB49 ,Group Modifier Bit 49" "0,1" textline " " bitfld.long 0x00 16. " GMB48 ,Group Modifier Bit 48" "0,1" bitfld.long 0x00 15. " GMB47 ,Group Modifier Bit 47" "0,1" bitfld.long 0x00 14. " GMB46 ,Group Modifier Bit 46" "0,1" textline " " bitfld.long 0x00 13. " GMB45 ,Group Modifier Bit 45" "0,1" bitfld.long 0x00 12. " GMB44 ,Group Modifier Bit 44" "0,1" bitfld.long 0x00 11. " GMB43 ,Group Modifier Bit 43" "0,1" textline " " bitfld.long 0x00 10. " GMB42 ,Group Modifier Bit 42" "0,1" bitfld.long 0x00 9. " GMB41 ,Group Modifier Bit 41" "0,1" bitfld.long 0x00 8. " GMB40 ,Group Modifier Bit 40" "0,1" textline " " bitfld.long 0x00 7. " GMB39 ,Group Modifier Bit 39" "0,1" bitfld.long 0x00 6. " GMB38 ,Group Modifier Bit 38" "0,1" bitfld.long 0x00 5. " GMB37 ,Group Modifier Bit 37" "0,1" textline " " bitfld.long 0x00 4. " GMB36 ,Group Modifier Bit 36" "0,1" bitfld.long 0x00 3. " GMB35 ,Group Modifier Bit 35" "0,1" bitfld.long 0x00 2. " GMB34 ,Group Modifier Bit 34" "0,1" textline " " bitfld.long 0x00 1. " GMB33 ,Group Modifier Bit 33" "0,1" bitfld.long 0x00 0. " GMB32 ,Group Modifier Bit 32" "0,1" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)) group.long 0x0D08++0x03 line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" bitfld.long 0x00 31. " GMB95 ,Group Modifier Bit 95" "0,1" bitfld.long 0x00 30. " GMB94 ,Group Modifier Bit 94" "0,1" bitfld.long 0x00 29. " GMB93 ,Group Modifier Bit 93" "0,1" textline " " bitfld.long 0x00 28. " GMB92 ,Group Modifier Bit 92" "0,1" bitfld.long 0x00 27. " GMB91 ,Group Modifier Bit 91" "0,1" bitfld.long 0x00 26. " GMB90 ,Group Modifier Bit 90" "0,1" textline " " bitfld.long 0x00 25. " GMB89 ,Group Modifier Bit 89" "0,1" bitfld.long 0x00 24. " GMB88 ,Group Modifier Bit 88" "0,1" bitfld.long 0x00 23. " GMB87 ,Group Modifier Bit 87" "0,1" textline " " bitfld.long 0x00 22. " GMB86 ,Group Modifier Bit 86" "0,1" bitfld.long 0x00 21. " GMB85 ,Group Modifier Bit 85" "0,1" bitfld.long 0x00 20. " GMB84 ,Group Modifier Bit 84" "0,1" textline " " bitfld.long 0x00 19. " GMB83 ,Group Modifier Bit 83" "0,1" bitfld.long 0x00 18. " GMB82 ,Group Modifier Bit 82" "0,1" bitfld.long 0x00 17. " GMB81 ,Group Modifier Bit 81" "0,1" textline " " bitfld.long 0x00 16. " GMB80 ,Group Modifier Bit 80" "0,1" bitfld.long 0x00 15. " GMB79 ,Group Modifier Bit 79" "0,1" bitfld.long 0x00 14. " GMB78 ,Group Modifier Bit 78" "0,1" textline " " bitfld.long 0x00 13. " GMB77 ,Group Modifier Bit 77" "0,1" bitfld.long 0x00 12. " GMB76 ,Group Modifier Bit 76" "0,1" bitfld.long 0x00 11. " GMB75 ,Group Modifier Bit 75" "0,1" textline " " bitfld.long 0x00 10. " GMB74 ,Group Modifier Bit 74" "0,1" bitfld.long 0x00 9. " GMB73 ,Group Modifier Bit 73" "0,1" bitfld.long 0x00 8. " GMB72 ,Group Modifier Bit 72" "0,1" textline " " bitfld.long 0x00 7. " GMB71 ,Group Modifier Bit 71" "0,1" bitfld.long 0x00 6. " GMB70 ,Group Modifier Bit 70" "0,1" bitfld.long 0x00 5. " GMB69 ,Group Modifier Bit 69" "0,1" textline " " bitfld.long 0x00 4. " GMB68 ,Group Modifier Bit 68" "0,1" bitfld.long 0x00 3. " GMB67 ,Group Modifier Bit 67" "0,1" bitfld.long 0x00 2. " GMB66 ,Group Modifier Bit 66" "0,1" textline " " bitfld.long 0x00 1. " GMB65 ,Group Modifier Bit 65" "0,1" bitfld.long 0x00 0. " GMB64 ,Group Modifier Bit 64" "0,1" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)) group.long 0x0D0C++0x03 line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1" bitfld.long 0x00 30. " GMB126 ,Group Modifier Bit 126" "0,1" bitfld.long 0x00 29. " GMB125 ,Group Modifier Bit 125" "0,1" textline " " bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1" bitfld.long 0x00 27. " GMB123 ,Group Modifier Bit 123" "0,1" bitfld.long 0x00 26. " GMB122 ,Group Modifier Bit 122" "0,1" textline " " bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1" bitfld.long 0x00 24. " GMB120 ,Group Modifier Bit 120" "0,1" bitfld.long 0x00 23. " GMB119 ,Group Modifier Bit 119" "0,1" textline " " bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1" bitfld.long 0x00 21. " GMB117 ,Group Modifier Bit 117" "0,1" bitfld.long 0x00 20. " GMB116 ,Group Modifier Bit 116" "0,1" textline " " bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1" bitfld.long 0x00 18. " GMB114 ,Group Modifier Bit 114" "0,1" bitfld.long 0x00 17. " GMB113 ,Group Modifier Bit 113" "0,1" textline " " bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1" bitfld.long 0x00 15. " GMB111 ,Group Modifier Bit 111" "0,1" bitfld.long 0x00 14. " GMB110 ,Group Modifier Bit 110" "0,1" textline " " bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1" bitfld.long 0x00 12. " GMB108 ,Group Modifier Bit 108" "0,1" bitfld.long 0x00 11. " GMB107 ,Group Modifier Bit 107" "0,1" textline " " bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1" bitfld.long 0x00 9. " GMB105 ,Group Modifier Bit 105" "0,1" bitfld.long 0x00 8. " GMB104 ,Group Modifier Bit 104" "0,1" textline " " bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1" bitfld.long 0x00 6. " GMB102 ,Group Modifier Bit 102" "0,1" bitfld.long 0x00 5. " GMB101 ,Group Modifier Bit 101" "0,1" textline " " bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1" bitfld.long 0x00 3. " GMB99 ,Group Modifier Bit 99" "0,1" bitfld.long 0x00 2. " GMB98 ,Group Modifier Bit 98" "0,1" textline " " bitfld.long 0x00 1. " GMB97 ,Group Modifier Bit 97" "0,1" bitfld.long 0x00 0. " GMB96 ,Group Modifier Bit 96" "0,1" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)) group.long 0x0D10++0x03 line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1" bitfld.long 0x00 30. " GMB158 ,Group Modifier Bit 158" "0,1" bitfld.long 0x00 29. " GMB157 ,Group Modifier Bit 157" "0,1" textline " " bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1" bitfld.long 0x00 27. " GMB155 ,Group Modifier Bit 155" "0,1" bitfld.long 0x00 26. " GMB154 ,Group Modifier Bit 154" "0,1" textline " " bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1" bitfld.long 0x00 24. " GMB152 ,Group Modifier Bit 152" "0,1" bitfld.long 0x00 23. " GMB151 ,Group Modifier Bit 151" "0,1" textline " " bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1" bitfld.long 0x00 21. " GMB149 ,Group Modifier Bit 149" "0,1" bitfld.long 0x00 20. " GMB148 ,Group Modifier Bit 148" "0,1" textline " " bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1" bitfld.long 0x00 18. " GMB146 ,Group Modifier Bit 146" "0,1" bitfld.long 0x00 17. " GMB145 ,Group Modifier Bit 145" "0,1" textline " " bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1" bitfld.long 0x00 15. " GMB143 ,Group Modifier Bit 143" "0,1" bitfld.long 0x00 14. " GMB142 ,Group Modifier Bit 142" "0,1" textline " " bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1" bitfld.long 0x00 12. " GMB140 ,Group Modifier Bit 140" "0,1" bitfld.long 0x00 11. " GMB139 ,Group Modifier Bit 139" "0,1" textline " " bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1" bitfld.long 0x00 9. " GMB137 ,Group Modifier Bit 137" "0,1" bitfld.long 0x00 8. " GMB136 ,Group Modifier Bit 136" "0,1" textline " " bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1" bitfld.long 0x00 6. " GMB134 ,Group Modifier Bit 134" "0,1" bitfld.long 0x00 5. " GMB133 ,Group Modifier Bit 133" "0,1" textline " " bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1" bitfld.long 0x00 3. " GMB131 ,Group Modifier Bit 131" "0,1" bitfld.long 0x00 2. " GMB130 ,Group Modifier Bit 130" "0,1" textline " " bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1" bitfld.long 0x00 0. " GMB128 ,Group Modifier Bit 128" "0,1" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)) group.long 0x0D14++0x03 line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1" bitfld.long 0x00 30. " GMB190 ,Group Modifier Bit 190" "0,1" bitfld.long 0x00 29. " GMB189 ,Group Modifier Bit 189" "0,1" textline " " bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1" bitfld.long 0x00 27. " GMB187 ,Group Modifier Bit 187" "0,1" bitfld.long 0x00 26. " GMB186 ,Group Modifier Bit 186" "0,1" textline " " bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1" bitfld.long 0x00 24. " GMB184 ,Group Modifier Bit 184" "0,1" bitfld.long 0x00 23. " GMB183 ,Group Modifier Bit 183" "0,1" textline " " bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1" bitfld.long 0x00 21. " GMB181 ,Group Modifier Bit 181" "0,1" bitfld.long 0x00 20. " GMB180 ,Group Modifier Bit 180" "0,1" textline " " bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1" bitfld.long 0x00 18. " GMB178 ,Group Modifier Bit 178" "0,1" bitfld.long 0x00 17. " GMB177 ,Group Modifier Bit 177" "0,1" textline " " bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1" bitfld.long 0x00 15. " GMB175 ,Group Modifier Bit 175" "0,1" bitfld.long 0x00 14. " GMB174 ,Group Modifier Bit 174" "0,1" textline " " bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1" bitfld.long 0x00 12. " GMB172 ,Group Modifier Bit 172" "0,1" bitfld.long 0x00 11. " GMB171 ,Group Modifier Bit 171" "0,1" textline " " bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1" bitfld.long 0x00 9. " GMB169 ,Group Modifier Bit 169" "0,1" bitfld.long 0x00 8. " GMB168 ,Group Modifier Bit 168" "0,1" textline " " bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1" bitfld.long 0x00 6. " GMB166 ,Group Modifier Bit 166" "0,1" bitfld.long 0x00 5. " GMB165 ,Group Modifier Bit 165" "0,1" textline " " bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1" bitfld.long 0x00 3. " GMB163 ,Group Modifier Bit 163" "0,1" bitfld.long 0x00 2. " GMB162 ,Group Modifier Bit 162" "0,1" textline " " bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1" bitfld.long 0x00 0. " GMB160 ,Group Modifier Bit 160" "0,1" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)) group.long 0x0D18++0x03 line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1" bitfld.long 0x00 30. " GMB222 ,Group Modifier Bit 222" "0,1" bitfld.long 0x00 29. " GMB221 ,Group Modifier Bit 221" "0,1" textline " " bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1" bitfld.long 0x00 27. " GMB219 ,Group Modifier Bit 219" "0,1" bitfld.long 0x00 26. " GMB218 ,Group Modifier Bit 218" "0,1" textline " " bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1" bitfld.long 0x00 24. " GMB216 ,Group Modifier Bit 216" "0,1" bitfld.long 0x00 23. " GMB215 ,Group Modifier Bit 215" "0,1" textline " " bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1" bitfld.long 0x00 21. " GMB213 ,Group Modifier Bit 213" "0,1" bitfld.long 0x00 20. " GMB212 ,Group Modifier Bit 212" "0,1" textline " " bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1" bitfld.long 0x00 18. " GMB210 ,Group Modifier Bit 210" "0,1" bitfld.long 0x00 17. " GMB209 ,Group Modifier Bit 209" "0,1" textline " " bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1" bitfld.long 0x00 15. " GMB207 ,Group Modifier Bit 207" "0,1" bitfld.long 0x00 14. " GMB206 ,Group Modifier Bit 206" "0,1" textline " " bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1" bitfld.long 0x00 12. " GMB204 ,Group Modifier Bit 204" "0,1" bitfld.long 0x00 11. " GMB203 ,Group Modifier Bit 203" "0,1" textline " " bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1" bitfld.long 0x00 9. " GMB201 ,Group Modifier Bit 201" "0,1" bitfld.long 0x00 8. " GMB200 ,Group Modifier Bit 200" "0,1" textline " " bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1" bitfld.long 0x00 6. " GMB198 ,Group Modifier Bit 198" "0,1" bitfld.long 0x00 5. " GMB197 ,Group Modifier Bit 197" "0,1" textline " " bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1" bitfld.long 0x00 3. " GMB195 ,Group Modifier Bit 195" "0,1" bitfld.long 0x00 2. " GMB194 ,Group Modifier Bit 194" "0,1" textline " " bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1" bitfld.long 0x00 0. " GMB192 ,Group Modifier Bit 192" "0,1" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)) group.long 0x0D1C++0x03 line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1" bitfld.long 0x00 30. " GMB254 ,Group Modifier Bit 254" "0,1" bitfld.long 0x00 29. " GMB253 ,Group Modifier Bit 253" "0,1" textline " " bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1" bitfld.long 0x00 27. " GMB251 ,Group Modifier Bit 251" "0,1" bitfld.long 0x00 26. " GMB250 ,Group Modifier Bit 250" "0,1" textline " " bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1" bitfld.long 0x00 24. " GMB248 ,Group Modifier Bit 248" "0,1" bitfld.long 0x00 23. " GMB247 ,Group Modifier Bit 247" "0,1" textline " " bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1" bitfld.long 0x00 21. " GMB245 ,Group Modifier Bit 245" "0,1" bitfld.long 0x00 20. " GMB244 ,Group Modifier Bit 244" "0,1" textline " " bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1" bitfld.long 0x00 18. " GMB242 ,Group Modifier Bit 242" "0,1" bitfld.long 0x00 17. " GMB241 ,Group Modifier Bit 241" "0,1" textline " " bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1" bitfld.long 0x00 15. " GMB239 ,Group Modifier Bit 239" "0,1" bitfld.long 0x00 14. " GMB238 ,Group Modifier Bit 238" "0,1" textline " " bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1" bitfld.long 0x00 12. " GMB236 ,Group Modifier Bit 236" "0,1" bitfld.long 0x00 11. " GMB235 ,Group Modifier Bit 235" "0,1" textline " " bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1" bitfld.long 0x00 9. " GMB233 ,Group Modifier Bit 233" "0,1" bitfld.long 0x00 8. " GMB232 ,Group Modifier Bit 232" "0,1" textline " " bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1" bitfld.long 0x00 6. " GMB230 ,Group Modifier Bit 230" "0,1" bitfld.long 0x00 5. " GMB229 ,Group Modifier Bit 229" "0,1" textline " " bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1" bitfld.long 0x00 3. " GMB227 ,Group Modifier Bit 227" "0,1" bitfld.long 0x00 2. " GMB226 ,Group Modifier Bit 226" "0,1" textline " " bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1" bitfld.long 0x00 0. " GMB224 ,Group Modifier Bit 224" "0,1" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)) group.long 0x0D20++0x03 line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1" bitfld.long 0x00 30. " GMB286 ,Group Modifier Bit 286" "0,1" bitfld.long 0x00 29. " GMB285 ,Group Modifier Bit 285" "0,1" textline " " bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1" bitfld.long 0x00 27. " GMB283 ,Group Modifier Bit 283" "0,1" bitfld.long 0x00 26. " GMB282 ,Group Modifier Bit 282" "0,1" textline " " bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1" bitfld.long 0x00 24. " GMB280 ,Group Modifier Bit 280" "0,1" bitfld.long 0x00 23. " GMB279 ,Group Modifier Bit 279" "0,1" textline " " bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1" bitfld.long 0x00 21. " GMB277 ,Group Modifier Bit 277" "0,1" bitfld.long 0x00 20. " GMB276 ,Group Modifier Bit 276" "0,1" textline " " bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1" bitfld.long 0x00 18. " GMB274 ,Group Modifier Bit 274" "0,1" bitfld.long 0x00 17. " GMB273 ,Group Modifier Bit 273" "0,1" textline " " bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1" bitfld.long 0x00 15. " GMB271 ,Group Modifier Bit 271" "0,1" bitfld.long 0x00 14. " GMB270 ,Group Modifier Bit 270" "0,1" textline " " bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1" bitfld.long 0x00 12. " GMB268 ,Group Modifier Bit 268" "0,1" bitfld.long 0x00 11. " GMB267 ,Group Modifier Bit 267" "0,1" textline " " bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1" bitfld.long 0x00 9. " GMB265 ,Group Modifier Bit 265" "0,1" bitfld.long 0x00 8. " GMB264 ,Group Modifier Bit 264" "0,1" textline " " bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1" bitfld.long 0x00 6. " GMB262 ,Group Modifier Bit 262" "0,1" bitfld.long 0x00 5. " GMB261 ,Group Modifier Bit 261" "0,1" textline " " bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1" bitfld.long 0x00 3. " GMB259 ,Group Modifier Bit 259" "0,1" bitfld.long 0x00 2. " GMB258 ,Group Modifier Bit 258" "0,1" textline " " bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1" bitfld.long 0x00 0. " GMB256 ,Group Modifier Bit 256" "0,1" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)) group.long 0x0D24++0x03 line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1" bitfld.long 0x00 30. " GMB318 ,Group Modifier Bit 318" "0,1" bitfld.long 0x00 29. " GMB317 ,Group Modifier Bit 317" "0,1" textline " " bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1" bitfld.long 0x00 27. " GMB315 ,Group Modifier Bit 315" "0,1" bitfld.long 0x00 26. " GMB314 ,Group Modifier Bit 314" "0,1" textline " " bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1" bitfld.long 0x00 24. " GMB312 ,Group Modifier Bit 312" "0,1" bitfld.long 0x00 23. " GMB311 ,Group Modifier Bit 311" "0,1" textline " " bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1" bitfld.long 0x00 21. " GMB309 ,Group Modifier Bit 309" "0,1" bitfld.long 0x00 20. " GMB308 ,Group Modifier Bit 308" "0,1" textline " " bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1" bitfld.long 0x00 18. " GMB306 ,Group Modifier Bit 306" "0,1" bitfld.long 0x00 17. " GMB305 ,Group Modifier Bit 305" "0,1" textline " " bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1" bitfld.long 0x00 15. " GMB303 ,Group Modifier Bit 303" "0,1" bitfld.long 0x00 14. " GMB302 ,Group Modifier Bit 302" "0,1" textline " " bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1" bitfld.long 0x00 12. " GMB300 ,Group Modifier Bit 300" "0,1" bitfld.long 0x00 11. " GMB299 ,Group Modifier Bit 299" "0,1" textline " " bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1" bitfld.long 0x00 9. " GMB297 ,Group Modifier Bit 297" "0,1" bitfld.long 0x00 8. " GMB296 ,Group Modifier Bit 296" "0,1" textline " " bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1" bitfld.long 0x00 6. " GMB294 ,Group Modifier Bit 294" "0,1" bitfld.long 0x00 5. " GMB293 ,Group Modifier Bit 293" "0,1" textline " " bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1" bitfld.long 0x00 3. " GMB291 ,Group Modifier Bit 291" "0,1" bitfld.long 0x00 2. " GMB290 ,Group Modifier Bit 290" "0,1" textline " " bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1" bitfld.long 0x00 0. " GMB288 ,Group Modifier Bit 288" "0,1" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)) group.long 0x0D28++0x03 line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1" bitfld.long 0x00 30. " GMB350 ,Group Modifier Bit 350" "0,1" bitfld.long 0x00 29. " GMB349 ,Group Modifier Bit 349" "0,1" textline " " bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1" bitfld.long 0x00 27. " GMB347 ,Group Modifier Bit 347" "0,1" bitfld.long 0x00 26. " GMB346 ,Group Modifier Bit 346" "0,1" textline " " bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1" bitfld.long 0x00 24. " GMB344 ,Group Modifier Bit 344" "0,1" bitfld.long 0x00 23. " GMB343 ,Group Modifier Bit 343" "0,1" textline " " bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1" bitfld.long 0x00 21. " GMB341 ,Group Modifier Bit 341" "0,1" bitfld.long 0x00 20. " GMB340 ,Group Modifier Bit 340" "0,1" textline " " bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1" bitfld.long 0x00 18. " GMB338 ,Group Modifier Bit 338" "0,1" bitfld.long 0x00 17. " GMB337 ,Group Modifier Bit 337" "0,1" textline " " bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1" bitfld.long 0x00 15. " GMB335 ,Group Modifier Bit 335" "0,1" bitfld.long 0x00 14. " GMB334 ,Group Modifier Bit 334" "0,1" textline " " bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1" bitfld.long 0x00 12. " GMB332 ,Group Modifier Bit 332" "0,1" bitfld.long 0x00 11. " GMB331 ,Group Modifier Bit 331" "0,1" textline " " bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1" bitfld.long 0x00 9. " GMB329 ,Group Modifier Bit 329" "0,1" bitfld.long 0x00 8. " GMB328 ,Group Modifier Bit 328" "0,1" textline " " bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1" bitfld.long 0x00 6. " GMB326 ,Group Modifier Bit 326" "0,1" bitfld.long 0x00 5. " GMB325 ,Group Modifier Bit 325" "0,1" textline " " bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1" bitfld.long 0x00 3. " GMB323 ,Group Modifier Bit 323" "0,1" bitfld.long 0x00 2. " GMB322 ,Group Modifier Bit 322" "0,1" textline " " bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1" bitfld.long 0x00 0. " GMB320 ,Group Modifier Bit 320" "0,1" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)) group.long 0x0D2C++0x03 line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1" bitfld.long 0x00 30. " GMB382 ,Group Modifier Bit 382" "0,1" bitfld.long 0x00 29. " GMB381 ,Group Modifier Bit 381" "0,1" textline " " bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1" bitfld.long 0x00 27. " GMB379 ,Group Modifier Bit 379" "0,1" bitfld.long 0x00 26. " GMB378 ,Group Modifier Bit 378" "0,1" textline " " bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1" bitfld.long 0x00 24. " GMB376 ,Group Modifier Bit 376" "0,1" bitfld.long 0x00 23. " GMB375 ,Group Modifier Bit 375" "0,1" textline " " bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1" bitfld.long 0x00 21. " GMB373 ,Group Modifier Bit 373" "0,1" bitfld.long 0x00 20. " GMB372 ,Group Modifier Bit 372" "0,1" textline " " bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1" bitfld.long 0x00 18. " GMB370 ,Group Modifier Bit 370" "0,1" bitfld.long 0x00 17. " GMB369 ,Group Modifier Bit 369" "0,1" textline " " bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1" bitfld.long 0x00 15. " GMB367 ,Group Modifier Bit 367" "0,1" bitfld.long 0x00 14. " GMB366 ,Group Modifier Bit 366" "0,1" textline " " bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1" bitfld.long 0x00 12. " GMB364 ,Group Modifier Bit 364" "0,1" bitfld.long 0x00 11. " GMB363 ,Group Modifier Bit 363" "0,1" textline " " bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1" bitfld.long 0x00 9. " GMB361 ,Group Modifier Bit 361" "0,1" bitfld.long 0x00 8. " GMB360 ,Group Modifier Bit 360" "0,1" textline " " bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1" bitfld.long 0x00 6. " GMB358 ,Group Modifier Bit 358" "0,1" bitfld.long 0x00 5. " GMB357 ,Group Modifier Bit 357" "0,1" textline " " bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1" bitfld.long 0x00 3. " GMB355 ,Group Modifier Bit 355" "0,1" bitfld.long 0x00 2. " GMB354 ,Group Modifier Bit 354" "0,1" textline " " bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1" bitfld.long 0x00 0. " GMB352 ,Group Modifier Bit 352" "0,1" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)) group.long 0x0D30++0x03 line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1" bitfld.long 0x00 30. " GMB414 ,Group Modifier Bit 414" "0,1" bitfld.long 0x00 29. " GMB413 ,Group Modifier Bit 413" "0,1" textline " " bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1" bitfld.long 0x00 27. " GMB411 ,Group Modifier Bit 411" "0,1" bitfld.long 0x00 26. " GMB410 ,Group Modifier Bit 410" "0,1" textline " " bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1" bitfld.long 0x00 24. " GMB408 ,Group Modifier Bit 408" "0,1" bitfld.long 0x00 23. " GMB407 ,Group Modifier Bit 407" "0,1" textline " " bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1" bitfld.long 0x00 21. " GMB405 ,Group Modifier Bit 405" "0,1" bitfld.long 0x00 20. " GMB404 ,Group Modifier Bit 404" "0,1" textline " " bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1" bitfld.long 0x00 18. " GMB402 ,Group Modifier Bit 402" "0,1" bitfld.long 0x00 17. " GMB401 ,Group Modifier Bit 401" "0,1" textline " " bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1" bitfld.long 0x00 15. " GMB399 ,Group Modifier Bit 399" "0,1" bitfld.long 0x00 14. " GMB398 ,Group Modifier Bit 398" "0,1" textline " " bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1" bitfld.long 0x00 12. " GMB396 ,Group Modifier Bit 396" "0,1" bitfld.long 0x00 11. " GMB395 ,Group Modifier Bit 395" "0,1" textline " " bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1" bitfld.long 0x00 9. " GMB393 ,Group Modifier Bit 393" "0,1" bitfld.long 0x00 8. " GMB392 ,Group Modifier Bit 392" "0,1" textline " " bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1" bitfld.long 0x00 6. " GMB390 ,Group Modifier Bit 390" "0,1" bitfld.long 0x00 5. " GMB389 ,Group Modifier Bit 389" "0,1" textline " " bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1" bitfld.long 0x00 3. " GMB387 ,Group Modifier Bit 387" "0,1" bitfld.long 0x00 2. " GMB386 ,Group Modifier Bit 386" "0,1" textline " " bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1" bitfld.long 0x00 0. " GMB384 ,Group Modifier Bit 384" "0,1" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)) group.long 0x0D34++0x03 line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1" bitfld.long 0x00 30. " GMB446 ,Group Modifier Bit 446" "0,1" bitfld.long 0x00 29. " GMB445 ,Group Modifier Bit 445" "0,1" textline " " bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1" bitfld.long 0x00 27. " GMB443 ,Group Modifier Bit 443" "0,1" bitfld.long 0x00 26. " GMB442 ,Group Modifier Bit 442" "0,1" textline " " bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1" bitfld.long 0x00 24. " GMB440 ,Group Modifier Bit 440" "0,1" bitfld.long 0x00 23. " GMB439 ,Group Modifier Bit 439" "0,1" textline " " bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1" bitfld.long 0x00 21. " GMB437 ,Group Modifier Bit 437" "0,1" bitfld.long 0x00 20. " GMB436 ,Group Modifier Bit 436" "0,1" textline " " bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1" bitfld.long 0x00 18. " GMB434 ,Group Modifier Bit 434" "0,1" bitfld.long 0x00 17. " GMB433 ,Group Modifier Bit 433" "0,1" textline " " bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1" bitfld.long 0x00 15. " GMB431 ,Group Modifier Bit 431" "0,1" bitfld.long 0x00 14. " GMB430 ,Group Modifier Bit 430" "0,1" textline " " bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1" bitfld.long 0x00 12. " GMB428 ,Group Modifier Bit 428" "0,1" bitfld.long 0x00 11. " GMB427 ,Group Modifier Bit 427" "0,1" textline " " bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1" bitfld.long 0x00 9. " GMB425 ,Group Modifier Bit 425" "0,1" bitfld.long 0x00 8. " GMB424 ,Group Modifier Bit 424" "0,1" textline " " bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1" bitfld.long 0x00 6. " GMB422 ,Group Modifier Bit 422" "0,1" bitfld.long 0x00 5. " GMB421 ,Group Modifier Bit 421" "0,1" textline " " bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1" bitfld.long 0x00 3. " GMB419 ,Group Modifier Bit 419" "0,1" bitfld.long 0x00 2. " GMB418 ,Group Modifier Bit 418" "0,1" textline " " bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1" bitfld.long 0x00 0. " GMB416 ,Group Modifier Bit 416" "0,1" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)) group.long 0x0D38++0x03 line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1" bitfld.long 0x00 30. " GMB478 ,Group Modifier Bit 478" "0,1" bitfld.long 0x00 29. " GMB477 ,Group Modifier Bit 477" "0,1" textline " " bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1" bitfld.long 0x00 27. " GMB475 ,Group Modifier Bit 475" "0,1" bitfld.long 0x00 26. " GMB474 ,Group Modifier Bit 474" "0,1" textline " " bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1" bitfld.long 0x00 24. " GMB472 ,Group Modifier Bit 472" "0,1" bitfld.long 0x00 23. " GMB471 ,Group Modifier Bit 471" "0,1" textline " " bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1" bitfld.long 0x00 21. " GMB469 ,Group Modifier Bit 469" "0,1" bitfld.long 0x00 20. " GMB468 ,Group Modifier Bit 468" "0,1" textline " " bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1" bitfld.long 0x00 18. " GMB466 ,Group Modifier Bit 466" "0,1" bitfld.long 0x00 17. " GMB465 ,Group Modifier Bit 465" "0,1" textline " " bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1" bitfld.long 0x00 15. " GMB463 ,Group Modifier Bit 463" "0,1" bitfld.long 0x00 14. " GMB462 ,Group Modifier Bit 462" "0,1" textline " " bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1" bitfld.long 0x00 12. " GMB460 ,Group Modifier Bit 460" "0,1" bitfld.long 0x00 11. " GMB459 ,Group Modifier Bit 459" "0,1" textline " " bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1" bitfld.long 0x00 9. " GMB457 ,Group Modifier Bit 457" "0,1" bitfld.long 0x00 8. " GMB456 ,Group Modifier Bit 456" "0,1" textline " " bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1" bitfld.long 0x00 6. " GMB454 ,Group Modifier Bit 454" "0,1" bitfld.long 0x00 5. " GMB453 ,Group Modifier Bit 453" "0,1" textline " " bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1" bitfld.long 0x00 3. " GMB451 ,Group Modifier Bit 451" "0,1" bitfld.long 0x00 2. " GMB450 ,Group Modifier Bit 450" "0,1" textline " " bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1" bitfld.long 0x00 0. " GMB448 ,Group Modifier Bit 448" "0,1" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)) group.long 0x0D3C++0x03 line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1" bitfld.long 0x00 30. " GMB510 ,Group Modifier Bit 510" "0,1" bitfld.long 0x00 29. " GMB509 ,Group Modifier Bit 509" "0,1" textline " " bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1" bitfld.long 0x00 27. " GMB507 ,Group Modifier Bit 507" "0,1" bitfld.long 0x00 26. " GMB506 ,Group Modifier Bit 506" "0,1" textline " " bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1" bitfld.long 0x00 24. " GMB504 ,Group Modifier Bit 504" "0,1" bitfld.long 0x00 23. " GMB503 ,Group Modifier Bit 503" "0,1" textline " " bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1" bitfld.long 0x00 21. " GMB501 ,Group Modifier Bit 501" "0,1" bitfld.long 0x00 20. " GMB500 ,Group Modifier Bit 500" "0,1" textline " " bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1" bitfld.long 0x00 18. " GMB498 ,Group Modifier Bit 498" "0,1" bitfld.long 0x00 17. " GMB497 ,Group Modifier Bit 497" "0,1" textline " " bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1" bitfld.long 0x00 15. " GMB495 ,Group Modifier Bit 495" "0,1" bitfld.long 0x00 14. " GMB494 ,Group Modifier Bit 494" "0,1" textline " " bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1" bitfld.long 0x00 12. " GMB492 ,Group Modifier Bit 492" "0,1" bitfld.long 0x00 11. " GMB491 ,Group Modifier Bit 491" "0,1" textline " " bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1" bitfld.long 0x00 9. " GMB489 ,Group Modifier Bit 489" "0,1" bitfld.long 0x00 8. " GMB488 ,Group Modifier Bit 488" "0,1" textline " " bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1" bitfld.long 0x00 6. " GMB486 ,Group Modifier Bit 486" "0,1" bitfld.long 0x00 5. " GMB485 ,Group Modifier Bit 485" "0,1" textline " " bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1" bitfld.long 0x00 3. " GMB483 ,Group Modifier Bit 483" "0,1" bitfld.long 0x00 2. " GMB482 ,Group Modifier Bit 482" "0,1" textline " " bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1" bitfld.long 0x00 0. " GMB480 ,Group Modifier Bit 480" "0,1" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)) group.long 0x0D40++0x03 line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1" bitfld.long 0x00 30. " GMB542 ,Group Modifier Bit 542" "0,1" bitfld.long 0x00 29. " GMB541 ,Group Modifier Bit 541" "0,1" textline " " bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1" bitfld.long 0x00 27. " GMB539 ,Group Modifier Bit 539" "0,1" bitfld.long 0x00 26. " GMB538 ,Group Modifier Bit 538" "0,1" textline " " bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1" bitfld.long 0x00 24. " GMB536 ,Group Modifier Bit 536" "0,1" bitfld.long 0x00 23. " GMB535 ,Group Modifier Bit 535" "0,1" textline " " bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1" bitfld.long 0x00 21. " GMB533 ,Group Modifier Bit 533" "0,1" bitfld.long 0x00 20. " GMB532 ,Group Modifier Bit 532" "0,1" textline " " bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1" bitfld.long 0x00 18. " GMB530 ,Group Modifier Bit 530" "0,1" bitfld.long 0x00 17. " GMB529 ,Group Modifier Bit 529" "0,1" textline " " bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1" bitfld.long 0x00 15. " GMB527 ,Group Modifier Bit 527" "0,1" bitfld.long 0x00 14. " GMB526 ,Group Modifier Bit 526" "0,1" textline " " bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1" bitfld.long 0x00 12. " GMB524 ,Group Modifier Bit 524" "0,1" bitfld.long 0x00 11. " GMB523 ,Group Modifier Bit 523" "0,1" textline " " bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1" bitfld.long 0x00 9. " GMB521 ,Group Modifier Bit 521" "0,1" bitfld.long 0x00 8. " GMB520 ,Group Modifier Bit 520" "0,1" textline " " bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1" bitfld.long 0x00 6. " GMB518 ,Group Modifier Bit 518" "0,1" bitfld.long 0x00 5. " GMB517 ,Group Modifier Bit 517" "0,1" textline " " bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1" bitfld.long 0x00 3. " GMB515 ,Group Modifier Bit 515" "0,1" bitfld.long 0x00 2. " GMB514 ,Group Modifier Bit 514" "0,1" textline " " bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1" bitfld.long 0x00 0. " GMB512 ,Group Modifier Bit 512" "0,1" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)) group.long 0x0D44++0x03 line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1" bitfld.long 0x00 30. " GMB574 ,Group Modifier Bit 574" "0,1" bitfld.long 0x00 29. " GMB573 ,Group Modifier Bit 573" "0,1" textline " " bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1" bitfld.long 0x00 27. " GMB571 ,Group Modifier Bit 571" "0,1" bitfld.long 0x00 26. " GMB570 ,Group Modifier Bit 570" "0,1" textline " " bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1" bitfld.long 0x00 24. " GMB568 ,Group Modifier Bit 568" "0,1" bitfld.long 0x00 23. " GMB567 ,Group Modifier Bit 567" "0,1" textline " " bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1" bitfld.long 0x00 21. " GMB565 ,Group Modifier Bit 565" "0,1" bitfld.long 0x00 20. " GMB564 ,Group Modifier Bit 564" "0,1" textline " " bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1" bitfld.long 0x00 18. " GMB562 ,Group Modifier Bit 562" "0,1" bitfld.long 0x00 17. " GMB561 ,Group Modifier Bit 561" "0,1" textline " " bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1" bitfld.long 0x00 15. " GMB559 ,Group Modifier Bit 559" "0,1" bitfld.long 0x00 14. " GMB558 ,Group Modifier Bit 558" "0,1" textline " " bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1" bitfld.long 0x00 12. " GMB556 ,Group Modifier Bit 556" "0,1" bitfld.long 0x00 11. " GMB555 ,Group Modifier Bit 555" "0,1" textline " " bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1" bitfld.long 0x00 9. " GMB553 ,Group Modifier Bit 553" "0,1" bitfld.long 0x00 8. " GMB552 ,Group Modifier Bit 552" "0,1" textline " " bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1" bitfld.long 0x00 6. " GMB550 ,Group Modifier Bit 550" "0,1" bitfld.long 0x00 5. " GMB549 ,Group Modifier Bit 549" "0,1" textline " " bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1" bitfld.long 0x00 3. " GMB547 ,Group Modifier Bit 547" "0,1" bitfld.long 0x00 2. " GMB546 ,Group Modifier Bit 546" "0,1" textline " " bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1" bitfld.long 0x00 0. " GMB544 ,Group Modifier Bit 544" "0,1" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)) group.long 0x0D48++0x03 line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1" bitfld.long 0x00 30. " GMB606 ,Group Modifier Bit 606" "0,1" bitfld.long 0x00 29. " GMB605 ,Group Modifier Bit 605" "0,1" textline " " bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1" bitfld.long 0x00 27. " GMB603 ,Group Modifier Bit 603" "0,1" bitfld.long 0x00 26. " GMB602 ,Group Modifier Bit 602" "0,1" textline " " bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1" bitfld.long 0x00 24. " GMB600 ,Group Modifier Bit 600" "0,1" bitfld.long 0x00 23. " GMB599 ,Group Modifier Bit 599" "0,1" textline " " bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1" bitfld.long 0x00 21. " GMB597 ,Group Modifier Bit 597" "0,1" bitfld.long 0x00 20. " GMB596 ,Group Modifier Bit 596" "0,1" textline " " bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1" bitfld.long 0x00 18. " GMB594 ,Group Modifier Bit 594" "0,1" bitfld.long 0x00 17. " GMB593 ,Group Modifier Bit 593" "0,1" textline " " bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1" bitfld.long 0x00 15. " GMB591 ,Group Modifier Bit 591" "0,1" bitfld.long 0x00 14. " GMB590 ,Group Modifier Bit 590" "0,1" textline " " bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1" bitfld.long 0x00 12. " GMB588 ,Group Modifier Bit 588" "0,1" bitfld.long 0x00 11. " GMB587 ,Group Modifier Bit 587" "0,1" textline " " bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1" bitfld.long 0x00 9. " GMB585 ,Group Modifier Bit 585" "0,1" bitfld.long 0x00 8. " GMB584 ,Group Modifier Bit 584" "0,1" textline " " bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1" bitfld.long 0x00 6. " GMB582 ,Group Modifier Bit 582" "0,1" bitfld.long 0x00 5. " GMB581 ,Group Modifier Bit 581" "0,1" textline " " bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1" bitfld.long 0x00 3. " GMB579 ,Group Modifier Bit 579" "0,1" bitfld.long 0x00 2. " GMB578 ,Group Modifier Bit 578" "0,1" textline " " bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1" bitfld.long 0x00 0. " GMB576 ,Group Modifier Bit 576" "0,1" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)) group.long 0x0D4C++0x03 line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1" bitfld.long 0x00 30. " GMB638 ,Group Modifier Bit 638" "0,1" bitfld.long 0x00 29. " GMB637 ,Group Modifier Bit 637" "0,1" textline " " bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1" bitfld.long 0x00 27. " GMB635 ,Group Modifier Bit 635" "0,1" bitfld.long 0x00 26. " GMB634 ,Group Modifier Bit 634" "0,1" textline " " bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1" bitfld.long 0x00 24. " GMB632 ,Group Modifier Bit 632" "0,1" bitfld.long 0x00 23. " GMB631 ,Group Modifier Bit 631" "0,1" textline " " bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1" bitfld.long 0x00 21. " GMB629 ,Group Modifier Bit 629" "0,1" bitfld.long 0x00 20. " GMB628 ,Group Modifier Bit 628" "0,1" textline " " bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1" bitfld.long 0x00 18. " GMB626 ,Group Modifier Bit 626" "0,1" bitfld.long 0x00 17. " GMB625 ,Group Modifier Bit 625" "0,1" textline " " bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1" bitfld.long 0x00 15. " GMB623 ,Group Modifier Bit 623" "0,1" bitfld.long 0x00 14. " GMB622 ,Group Modifier Bit 622" "0,1" textline " " bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1" bitfld.long 0x00 12. " GMB620 ,Group Modifier Bit 620" "0,1" bitfld.long 0x00 11. " GMB619 ,Group Modifier Bit 619" "0,1" textline " " bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1" bitfld.long 0x00 9. " GMB617 ,Group Modifier Bit 617" "0,1" bitfld.long 0x00 8. " GMB616 ,Group Modifier Bit 616" "0,1" textline " " bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1" bitfld.long 0x00 6. " GMB614 ,Group Modifier Bit 614" "0,1" bitfld.long 0x00 5. " GMB613 ,Group Modifier Bit 613" "0,1" textline " " bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1" bitfld.long 0x00 3. " GMB611 ,Group Modifier Bit 611" "0,1" bitfld.long 0x00 2. " GMB610 ,Group Modifier Bit 610" "0,1" textline " " bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1" bitfld.long 0x00 0. " GMB608 ,Group Modifier Bit 608" "0,1" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)) group.long 0x0D50++0x03 line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1" bitfld.long 0x00 30. " GMB670 ,Group Modifier Bit 670" "0,1" bitfld.long 0x00 29. " GMB669 ,Group Modifier Bit 669" "0,1" textline " " bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1" bitfld.long 0x00 27. " GMB667 ,Group Modifier Bit 667" "0,1" bitfld.long 0x00 26. " GMB666 ,Group Modifier Bit 666" "0,1" textline " " bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1" bitfld.long 0x00 24. " GMB664 ,Group Modifier Bit 664" "0,1" bitfld.long 0x00 23. " GMB663 ,Group Modifier Bit 663" "0,1" textline " " bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1" bitfld.long 0x00 21. " GMB661 ,Group Modifier Bit 661" "0,1" bitfld.long 0x00 20. " GMB660 ,Group Modifier Bit 660" "0,1" textline " " bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1" bitfld.long 0x00 18. " GMB658 ,Group Modifier Bit 658" "0,1" bitfld.long 0x00 17. " GMB657 ,Group Modifier Bit 657" "0,1" textline " " bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1" bitfld.long 0x00 15. " GMB655 ,Group Modifier Bit 655" "0,1" bitfld.long 0x00 14. " GMB654 ,Group Modifier Bit 654" "0,1" textline " " bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1" bitfld.long 0x00 12. " GMB652 ,Group Modifier Bit 652" "0,1" bitfld.long 0x00 11. " GMB651 ,Group Modifier Bit 651" "0,1" textline " " bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1" bitfld.long 0x00 9. " GMB649 ,Group Modifier Bit 649" "0,1" bitfld.long 0x00 8. " GMB648 ,Group Modifier Bit 648" "0,1" textline " " bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1" bitfld.long 0x00 6. " GMB646 ,Group Modifier Bit 646" "0,1" bitfld.long 0x00 5. " GMB645 ,Group Modifier Bit 645" "0,1" textline " " bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1" bitfld.long 0x00 3. " GMB643 ,Group Modifier Bit 643" "0,1" bitfld.long 0x00 2. " GMB642 ,Group Modifier Bit 642" "0,1" textline " " bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1" bitfld.long 0x00 0. " GMB640 ,Group Modifier Bit 640" "0,1" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)) group.long 0x0D54++0x03 line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1" bitfld.long 0x00 30. " GMB702 ,Group Modifier Bit 702" "0,1" bitfld.long 0x00 29. " GMB701 ,Group Modifier Bit 701" "0,1" textline " " bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1" bitfld.long 0x00 27. " GMB699 ,Group Modifier Bit 699" "0,1" bitfld.long 0x00 26. " GMB698 ,Group Modifier Bit 698" "0,1" textline " " bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1" bitfld.long 0x00 24. " GMB696 ,Group Modifier Bit 696" "0,1" bitfld.long 0x00 23. " GMB695 ,Group Modifier Bit 695" "0,1" textline " " bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1" bitfld.long 0x00 21. " GMB693 ,Group Modifier Bit 693" "0,1" bitfld.long 0x00 20. " GMB692 ,Group Modifier Bit 692" "0,1" textline " " bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1" bitfld.long 0x00 18. " GMB690 ,Group Modifier Bit 690" "0,1" bitfld.long 0x00 17. " GMB689 ,Group Modifier Bit 689" "0,1" textline " " bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1" bitfld.long 0x00 15. " GMB687 ,Group Modifier Bit 687" "0,1" bitfld.long 0x00 14. " GMB686 ,Group Modifier Bit 686" "0,1" textline " " bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1" bitfld.long 0x00 12. " GMB684 ,Group Modifier Bit 684" "0,1" bitfld.long 0x00 11. " GMB683 ,Group Modifier Bit 683" "0,1" textline " " bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1" bitfld.long 0x00 9. " GMB681 ,Group Modifier Bit 681" "0,1" bitfld.long 0x00 8. " GMB680 ,Group Modifier Bit 680" "0,1" textline " " bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1" bitfld.long 0x00 6. " GMB678 ,Group Modifier Bit 678" "0,1" bitfld.long 0x00 5. " GMB677 ,Group Modifier Bit 677" "0,1" textline " " bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1" bitfld.long 0x00 3. " GMB675 ,Group Modifier Bit 675" "0,1" bitfld.long 0x00 2. " GMB674 ,Group Modifier Bit 674" "0,1" textline " " bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1" bitfld.long 0x00 0. " GMB672 ,Group Modifier Bit 672" "0,1" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)) group.long 0x0D58++0x03 line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1" bitfld.long 0x00 30. " GMB734 ,Group Modifier Bit 734" "0,1" bitfld.long 0x00 29. " GMB733 ,Group Modifier Bit 733" "0,1" textline " " bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1" bitfld.long 0x00 27. " GMB731 ,Group Modifier Bit 731" "0,1" bitfld.long 0x00 26. " GMB730 ,Group Modifier Bit 730" "0,1" textline " " bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1" bitfld.long 0x00 24. " GMB728 ,Group Modifier Bit 728" "0,1" bitfld.long 0x00 23. " GMB727 ,Group Modifier Bit 727" "0,1" textline " " bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1" bitfld.long 0x00 21. " GMB725 ,Group Modifier Bit 725" "0,1" bitfld.long 0x00 20. " GMB724 ,Group Modifier Bit 724" "0,1" textline " " bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1" bitfld.long 0x00 18. " GMB722 ,Group Modifier Bit 722" "0,1" bitfld.long 0x00 17. " GMB721 ,Group Modifier Bit 721" "0,1" textline " " bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1" bitfld.long 0x00 15. " GMB719 ,Group Modifier Bit 719" "0,1" bitfld.long 0x00 14. " GMB718 ,Group Modifier Bit 718" "0,1" textline " " bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1" bitfld.long 0x00 12. " GMB716 ,Group Modifier Bit 716" "0,1" bitfld.long 0x00 11. " GMB715 ,Group Modifier Bit 715" "0,1" textline " " bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1" bitfld.long 0x00 9. " GMB713 ,Group Modifier Bit 713" "0,1" bitfld.long 0x00 8. " GMB712 ,Group Modifier Bit 712" "0,1" textline " " bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1" bitfld.long 0x00 6. " GMB710 ,Group Modifier Bit 710" "0,1" bitfld.long 0x00 5. " GMB709 ,Group Modifier Bit 709" "0,1" textline " " bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1" bitfld.long 0x00 3. " GMB707 ,Group Modifier Bit 707" "0,1" bitfld.long 0x00 2. " GMB706 ,Group Modifier Bit 706" "0,1" textline " " bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1" bitfld.long 0x00 0. " GMB704 ,Group Modifier Bit 704" "0,1" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)) group.long 0x0D5C++0x03 line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1" bitfld.long 0x00 30. " GMB766 ,Group Modifier Bit 766" "0,1" bitfld.long 0x00 29. " GMB765 ,Group Modifier Bit 765" "0,1" textline " " bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1" bitfld.long 0x00 27. " GMB763 ,Group Modifier Bit 763" "0,1" bitfld.long 0x00 26. " GMB762 ,Group Modifier Bit 762" "0,1" textline " " bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1" bitfld.long 0x00 24. " GMB760 ,Group Modifier Bit 760" "0,1" bitfld.long 0x00 23. " GMB759 ,Group Modifier Bit 759" "0,1" textline " " bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1" bitfld.long 0x00 21. " GMB757 ,Group Modifier Bit 757" "0,1" bitfld.long 0x00 20. " GMB756 ,Group Modifier Bit 756" "0,1" textline " " bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1" bitfld.long 0x00 18. " GMB754 ,Group Modifier Bit 754" "0,1" bitfld.long 0x00 17. " GMB753 ,Group Modifier Bit 753" "0,1" textline " " bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1" bitfld.long 0x00 15. " GMB751 ,Group Modifier Bit 751" "0,1" bitfld.long 0x00 14. " GMB750 ,Group Modifier Bit 750" "0,1" textline " " bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1" bitfld.long 0x00 12. " GMB748 ,Group Modifier Bit 748" "0,1" bitfld.long 0x00 11. " GMB747 ,Group Modifier Bit 747" "0,1" textline " " bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1" bitfld.long 0x00 9. " GMB745 ,Group Modifier Bit 745" "0,1" bitfld.long 0x00 8. " GMB744 ,Group Modifier Bit 744" "0,1" textline " " bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1" bitfld.long 0x00 6. " GMB742 ,Group Modifier Bit 742" "0,1" bitfld.long 0x00 5. " GMB741 ,Group Modifier Bit 741" "0,1" textline " " bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1" bitfld.long 0x00 3. " GMB739 ,Group Modifier Bit 739" "0,1" bitfld.long 0x00 2. " GMB738 ,Group Modifier Bit 738" "0,1" textline " " bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1" bitfld.long 0x00 0. " GMB736 ,Group Modifier Bit 736" "0,1" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)) group.long 0x0D60++0x03 line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1" bitfld.long 0x00 30. " GMB798 ,Group Modifier Bit 798" "0,1" bitfld.long 0x00 29. " GMB797 ,Group Modifier Bit 797" "0,1" textline " " bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1" bitfld.long 0x00 27. " GMB795 ,Group Modifier Bit 795" "0,1" bitfld.long 0x00 26. " GMB794 ,Group Modifier Bit 794" "0,1" textline " " bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1" bitfld.long 0x00 24. " GMB792 ,Group Modifier Bit 792" "0,1" bitfld.long 0x00 23. " GMB791 ,Group Modifier Bit 791" "0,1" textline " " bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1" bitfld.long 0x00 21. " GMB789 ,Group Modifier Bit 789" "0,1" bitfld.long 0x00 20. " GMB788 ,Group Modifier Bit 788" "0,1" textline " " bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1" bitfld.long 0x00 18. " GMB786 ,Group Modifier Bit 786" "0,1" bitfld.long 0x00 17. " GMB785 ,Group Modifier Bit 785" "0,1" textline " " bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1" bitfld.long 0x00 15. " GMB783 ,Group Modifier Bit 783" "0,1" bitfld.long 0x00 14. " GMB782 ,Group Modifier Bit 782" "0,1" textline " " bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1" bitfld.long 0x00 12. " GMB780 ,Group Modifier Bit 780" "0,1" bitfld.long 0x00 11. " GMB779 ,Group Modifier Bit 779" "0,1" textline " " bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1" bitfld.long 0x00 9. " GMB777 ,Group Modifier Bit 777" "0,1" bitfld.long 0x00 8. " GMB776 ,Group Modifier Bit 776" "0,1" textline " " bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1" bitfld.long 0x00 6. " GMB774 ,Group Modifier Bit 774" "0,1" bitfld.long 0x00 5. " GMB773 ,Group Modifier Bit 773" "0,1" textline " " bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1" bitfld.long 0x00 3. " GMB771 ,Group Modifier Bit 771" "0,1" bitfld.long 0x00 2. " GMB770 ,Group Modifier Bit 770" "0,1" textline " " bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1" bitfld.long 0x00 0. " GMB768 ,Group Modifier Bit 768" "0,1" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)) group.long 0x0D64++0x03 line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1" bitfld.long 0x00 30. " GMB830 ,Group Modifier Bit 830" "0,1" bitfld.long 0x00 29. " GMB829 ,Group Modifier Bit 829" "0,1" textline " " bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1" bitfld.long 0x00 27. " GMB827 ,Group Modifier Bit 827" "0,1" bitfld.long 0x00 26. " GMB826 ,Group Modifier Bit 826" "0,1" textline " " bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1" bitfld.long 0x00 24. " GMB824 ,Group Modifier Bit 824" "0,1" bitfld.long 0x00 23. " GMB823 ,Group Modifier Bit 823" "0,1" textline " " bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1" bitfld.long 0x00 21. " GMB821 ,Group Modifier Bit 821" "0,1" bitfld.long 0x00 20. " GMB820 ,Group Modifier Bit 820" "0,1" textline " " bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1" bitfld.long 0x00 18. " GMB818 ,Group Modifier Bit 818" "0,1" bitfld.long 0x00 17. " GMB817 ,Group Modifier Bit 817" "0,1" textline " " bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1" bitfld.long 0x00 15. " GMB815 ,Group Modifier Bit 815" "0,1" bitfld.long 0x00 14. " GMB814 ,Group Modifier Bit 814" "0,1" textline " " bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1" bitfld.long 0x00 12. " GMB812 ,Group Modifier Bit 812" "0,1" bitfld.long 0x00 11. " GMB811 ,Group Modifier Bit 811" "0,1" textline " " bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1" bitfld.long 0x00 9. " GMB809 ,Group Modifier Bit 809" "0,1" bitfld.long 0x00 8. " GMB808 ,Group Modifier Bit 808" "0,1" textline " " bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1" bitfld.long 0x00 6. " GMB806 ,Group Modifier Bit 806" "0,1" bitfld.long 0x00 5. " GMB805 ,Group Modifier Bit 805" "0,1" textline " " bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1" bitfld.long 0x00 3. " GMB803 ,Group Modifier Bit 803" "0,1" bitfld.long 0x00 2. " GMB802 ,Group Modifier Bit 802" "0,1" textline " " bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1" bitfld.long 0x00 0. " GMB800 ,Group Modifier Bit 800" "0,1" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A)) group.long 0x0D68++0x03 line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1" bitfld.long 0x00 30. " GMB862 ,Group Modifier Bit 862" "0,1" bitfld.long 0x00 29. " GMB861 ,Group Modifier Bit 861" "0,1" textline " " bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1" bitfld.long 0x00 27. " GMB859 ,Group Modifier Bit 859" "0,1" bitfld.long 0x00 26. " GMB858 ,Group Modifier Bit 858" "0,1" textline " " bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1" bitfld.long 0x00 24. " GMB856 ,Group Modifier Bit 856" "0,1" bitfld.long 0x00 23. " GMB855 ,Group Modifier Bit 855" "0,1" textline " " bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1" bitfld.long 0x00 21. " GMB853 ,Group Modifier Bit 853" "0,1" bitfld.long 0x00 20. " GMB852 ,Group Modifier Bit 852" "0,1" textline " " bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1" bitfld.long 0x00 18. " GMB850 ,Group Modifier Bit 850" "0,1" bitfld.long 0x00 17. " GMB849 ,Group Modifier Bit 849" "0,1" textline " " bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1" bitfld.long 0x00 15. " GMB847 ,Group Modifier Bit 847" "0,1" bitfld.long 0x00 14. " GMB846 ,Group Modifier Bit 846" "0,1" textline " " bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1" bitfld.long 0x00 12. " GMB844 ,Group Modifier Bit 844" "0,1" bitfld.long 0x00 11. " GMB843 ,Group Modifier Bit 843" "0,1" textline " " bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1" bitfld.long 0x00 9. " GMB841 ,Group Modifier Bit 841" "0,1" bitfld.long 0x00 8. " GMB840 ,Group Modifier Bit 840" "0,1" textline " " bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1" bitfld.long 0x00 6. " GMB838 ,Group Modifier Bit 838" "0,1" bitfld.long 0x00 5. " GMB837 ,Group Modifier Bit 837" "0,1" textline " " bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1" bitfld.long 0x00 3. " GMB835 ,Group Modifier Bit 835" "0,1" bitfld.long 0x00 2. " GMB834 ,Group Modifier Bit 834" "0,1" textline " " bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1" bitfld.long 0x00 0. " GMB832 ,Group Modifier Bit 832" "0,1" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)) group.long 0x0D6C++0x03 line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1" bitfld.long 0x00 30. " GMB894 ,Group Modifier Bit 894" "0,1" bitfld.long 0x00 29. " GMB893 ,Group Modifier Bit 893" "0,1" textline " " bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1" bitfld.long 0x00 27. " GMB891 ,Group Modifier Bit 891" "0,1" bitfld.long 0x00 26. " GMB890 ,Group Modifier Bit 890" "0,1" textline " " bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1" bitfld.long 0x00 24. " GMB888 ,Group Modifier Bit 888" "0,1" bitfld.long 0x00 23. " GMB887 ,Group Modifier Bit 887" "0,1" textline " " bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1" bitfld.long 0x00 21. " GMB885 ,Group Modifier Bit 885" "0,1" bitfld.long 0x00 20. " GMB884 ,Group Modifier Bit 884" "0,1" textline " " bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1" bitfld.long 0x00 18. " GMB882 ,Group Modifier Bit 882" "0,1" bitfld.long 0x00 17. " GMB881 ,Group Modifier Bit 881" "0,1" textline " " bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1" bitfld.long 0x00 15. " GMB879 ,Group Modifier Bit 879" "0,1" bitfld.long 0x00 14. " GMB878 ,Group Modifier Bit 878" "0,1" textline " " bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1" bitfld.long 0x00 12. " GMB876 ,Group Modifier Bit 876" "0,1" bitfld.long 0x00 11. " GMB875 ,Group Modifier Bit 875" "0,1" textline " " bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1" bitfld.long 0x00 9. " GMB873 ,Group Modifier Bit 873" "0,1" bitfld.long 0x00 8. " GMB872 ,Group Modifier Bit 872" "0,1" textline " " bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1" bitfld.long 0x00 6. " GMB870 ,Group Modifier Bit 870" "0,1" bitfld.long 0x00 5. " GMB869 ,Group Modifier Bit 869" "0,1" textline " " bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1" bitfld.long 0x00 3. " GMB867 ,Group Modifier Bit 867" "0,1" bitfld.long 0x00 2. " GMB866 ,Group Modifier Bit 866" "0,1" textline " " bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1" bitfld.long 0x00 0. " GMB864 ,Group Modifier Bit 864" "0,1" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)) group.long 0x0D70++0x03 line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1" bitfld.long 0x00 30. " GMB926 ,Group Modifier Bit 926" "0,1" bitfld.long 0x00 29. " GMB925 ,Group Modifier Bit 925" "0,1" textline " " bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1" bitfld.long 0x00 27. " GMB923 ,Group Modifier Bit 923" "0,1" bitfld.long 0x00 26. " GMB922 ,Group Modifier Bit 922" "0,1" textline " " bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1" bitfld.long 0x00 24. " GMB920 ,Group Modifier Bit 920" "0,1" bitfld.long 0x00 23. " GMB919 ,Group Modifier Bit 919" "0,1" textline " " bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1" bitfld.long 0x00 21. " GMB917 ,Group Modifier Bit 917" "0,1" bitfld.long 0x00 20. " GMB916 ,Group Modifier Bit 916" "0,1" textline " " bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1" bitfld.long 0x00 18. " GMB914 ,Group Modifier Bit 914" "0,1" bitfld.long 0x00 17. " GMB913 ,Group Modifier Bit 913" "0,1" textline " " bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1" bitfld.long 0x00 15. " GMB911 ,Group Modifier Bit 911" "0,1" bitfld.long 0x00 14. " GMB910 ,Group Modifier Bit 910" "0,1" textline " " bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1" bitfld.long 0x00 12. " GMB908 ,Group Modifier Bit 908" "0,1" bitfld.long 0x00 11. " GMB907 ,Group Modifier Bit 907" "0,1" textline " " bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1" bitfld.long 0x00 9. " GMB905 ,Group Modifier Bit 905" "0,1" bitfld.long 0x00 8. " GMB904 ,Group Modifier Bit 904" "0,1" textline " " bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1" bitfld.long 0x00 6. " GMB902 ,Group Modifier Bit 902" "0,1" bitfld.long 0x00 5. " GMB901 ,Group Modifier Bit 901" "0,1" textline " " bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1" bitfld.long 0x00 3. " GMB899 ,Group Modifier Bit 899" "0,1" bitfld.long 0x00 2. " GMB898 ,Group Modifier Bit 898" "0,1" textline " " bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1" bitfld.long 0x00 0. " GMB896 ,Group Modifier Bit 896" "0,1" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)) group.long 0x0D74++0x03 line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1" bitfld.long 0x00 30. " GMB958 ,Group Modifier Bit 958" "0,1" bitfld.long 0x00 29. " GMB957 ,Group Modifier Bit 957" "0,1" textline " " bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1" bitfld.long 0x00 27. " GMB955 ,Group Modifier Bit 955" "0,1" bitfld.long 0x00 26. " GMB954 ,Group Modifier Bit 954" "0,1" textline " " bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1" bitfld.long 0x00 24. " GMB952 ,Group Modifier Bit 952" "0,1" bitfld.long 0x00 23. " GMB951 ,Group Modifier Bit 951" "0,1" textline " " bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1" bitfld.long 0x00 21. " GMB949 ,Group Modifier Bit 949" "0,1" bitfld.long 0x00 20. " GMB948 ,Group Modifier Bit 948" "0,1" textline " " bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1" bitfld.long 0x00 18. " GMB946 ,Group Modifier Bit 946" "0,1" bitfld.long 0x00 17. " GMB945 ,Group Modifier Bit 945" "0,1" textline " " bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1" bitfld.long 0x00 15. " GMB943 ,Group Modifier Bit 943" "0,1" bitfld.long 0x00 14. " GMB942 ,Group Modifier Bit 942" "0,1" textline " " bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1" bitfld.long 0x00 12. " GMB940 ,Group Modifier Bit 940" "0,1" bitfld.long 0x00 11. " GMB939 ,Group Modifier Bit 939" "0,1" textline " " bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1" bitfld.long 0x00 9. " GMB937 ,Group Modifier Bit 937" "0,1" bitfld.long 0x00 8. " GMB936 ,Group Modifier Bit 936" "0,1" textline " " bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1" bitfld.long 0x00 6. " GMB934 ,Group Modifier Bit 934" "0,1" bitfld.long 0x00 5. " GMB933 ,Group Modifier Bit 933" "0,1" textline " " bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1" bitfld.long 0x00 3. " GMB931 ,Group Modifier Bit 931" "0,1" bitfld.long 0x00 2. " GMB930 ,Group Modifier Bit 930" "0,1" textline " " bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1" bitfld.long 0x00 0. " GMB928 ,Group Modifier Bit 928" "0,1" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)) group.long 0x0D78++0x03 line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1" bitfld.long 0x00 30. " GMB990 ,Group Modifier Bit 990" "0,1" bitfld.long 0x00 29. " GMB989 ,Group Modifier Bit 989" "0,1" textline " " bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1" bitfld.long 0x00 27. " GMB987 ,Group Modifier Bit 987" "0,1" bitfld.long 0x00 26. " GMB986 ,Group Modifier Bit 986" "0,1" textline " " bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1" bitfld.long 0x00 24. " GMB984 ,Group Modifier Bit 984" "0,1" bitfld.long 0x00 23. " GMB983 ,Group Modifier Bit 983" "0,1" textline " " bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1" bitfld.long 0x00 21. " GMB981 ,Group Modifier Bit 981" "0,1" bitfld.long 0x00 20. " GMB980 ,Group Modifier Bit 980" "0,1" textline " " bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1" bitfld.long 0x00 18. " GMB978 ,Group Modifier Bit 978" "0,1" bitfld.long 0x00 17. " GMB977 ,Group Modifier Bit 977" "0,1" textline " " bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1" bitfld.long 0x00 15. " GMB975 ,Group Modifier Bit 975" "0,1" bitfld.long 0x00 14. " GMB974 ,Group Modifier Bit 974" "0,1" textline " " bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1" bitfld.long 0x00 12. " GMB972 ,Group Modifier Bit 972" "0,1" bitfld.long 0x00 11. " GMB971 ,Group Modifier Bit 971" "0,1" textline " " bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1" bitfld.long 0x00 9. " GMB969 ,Group Modifier Bit 969" "0,1" bitfld.long 0x00 8. " GMB968 ,Group Modifier Bit 968" "0,1" textline " " bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1" bitfld.long 0x00 6. " GMB966 ,Group Modifier Bit 966" "0,1" bitfld.long 0x00 5. " GMB965 ,Group Modifier Bit 965" "0,1" textline " " bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1" bitfld.long 0x00 3. " GMB963 ,Group Modifier Bit 963" "0,1" bitfld.long 0x00 2. " GMB962 ,Group Modifier Bit 962" "0,1" textline " " bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1" bitfld.long 0x00 0. " GMB960 ,Group Modifier Bit 960" "0,1" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30" endif tree.end width 14. tree "Non-secure Access Control Registers" hgroup.long 0x0E00++0x03 hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0" hgroup.long 0xE04++0x03 hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08))) group.long 0xE08++0x03 line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" bitfld.long 0x00 30.--31. " NS_ACCESS47 ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS46 ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS45 ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS44 ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS43 ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS42 ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS41 ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS40 ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS39 ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS38 ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS37 ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS36 ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS35 ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS34 ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS33 ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS32 ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE08++0x03 hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C))) group.long 0xE0C++0x03 line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" bitfld.long 0x00 30.--31. " NS_ACCESS63 ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS62 ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS61 ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS60 ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS59 ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS58 ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS57 ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS56 ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS55 ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS54 ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS53 ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS52 ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS51 ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS50 ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS49 ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS48 ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE0C++0x03 hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10))) group.long 0xE10++0x03 line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" bitfld.long 0x00 30.--31. " NS_ACCESS79 ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS78 ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS77 ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS76 ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS75 ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS74 ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS73 ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS72 ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS71 ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS70 ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS69 ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS68 ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS67 ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS66 ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS65 ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS64 ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE10++0x03 hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14))) group.long 0xE14++0x03 line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" bitfld.long 0x00 30.--31. " NS_ACCESS95 ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS94 ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS93 ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS92 ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS91 ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS90 ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS89 ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS88 ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS87 ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS86 ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS85 ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS84 ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS83 ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS82 ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS81 ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS80 ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE14++0x03 hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18))) group.long 0xE18++0x03 line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS99 ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS98 ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS97 ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS96 ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE18++0x03 hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C))) group.long 0xE1C++0x03 line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE1C++0x03 hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20))) group.long 0xE20++0x03 line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE20++0x03 hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24))) group.long 0xE24++0x03 line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE24++0x03 hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28))) group.long 0xE28++0x03 line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE28++0x03 hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C))) group.long 0xE2C++0x03 line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE2C++0x03 hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30))) group.long 0xE30++0x03 line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE30++0x03 hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34))) group.long 0xE34++0x03 line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE34++0x03 hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38))) group.long 0xE38++0x03 line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE38++0x03 hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C))) group.long 0xE3C++0x03 line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE3C++0x03 hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40))) group.long 0xE40++0x03 line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE40++0x03 hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44))) group.long 0xE44++0x03 line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE44++0x03 hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48))) group.long 0xE48++0x03 line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE48++0x03 hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C))) group.long 0xE4C++0x03 line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE4C++0x03 hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50))) group.long 0xE50++0x03 line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE50++0x03 hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54))) group.long 0xE54++0x03 line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE54++0x03 hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58))) group.long 0xE58++0x03 line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE58++0x03 hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C))) group.long 0xE5C++0x03 line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE5C++0x03 hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60))) group.long 0xE60++0x03 line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE60++0x03 hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64))) group.long 0xE64++0x03 line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE64++0x03 hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68))) group.long 0xE68++0x03 line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE68++0x03 hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C))) group.long 0xE6C++0x03 line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE6C++0x03 hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70))) group.long 0xE70++0x03 line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE70++0x03 hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74))) group.long 0xE74++0x03 line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE74++0x03 hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78))) group.long 0xE78++0x03 line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE78++0x03 hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C))) group.long 0xE7C++0x03 line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE7C++0x03 hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80))) group.long 0xE80++0x03 line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE80++0x03 hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84))) group.long 0xE84++0x03 line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE84++0x03 hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88))) group.long 0xE88++0x03 line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE88++0x03 hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C))) group.long 0xE8C++0x03 line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE8C++0x03 hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90))) group.long 0xE90++0x03 line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE90++0x03 hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94))) group.long 0xE94++0x03 line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE94++0x03 hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98))) group.long 0xE98++0x03 line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE98++0x03 hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C))) group.long 0xE9C++0x03 line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xE9C++0x03 hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0))) group.long 0xEA0++0x03 line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA0++0x03 hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4))) group.long 0xEA4++0x03 line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA4++0x03 hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8))) group.long 0xEA8++0x03 line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEA8++0x03 hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC))) group.long 0xEAC++0x03 line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEAC++0x03 hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0))) group.long 0xEB0++0x03 line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB0++0x03 hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4))) group.long 0xEB4++0x03 line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB4++0x03 hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8))) group.long 0xEB8++0x03 line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEB8++0x03 hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC))) group.long 0xEBC++0x03 line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEBC++0x03 hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0))) group.long 0xEC0++0x03 line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC0++0x03 hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4))) group.long 0xEC4++0x03 line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC4++0x03 hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8))) group.long 0xEC8++0x03 line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEC8++0x03 hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC))) group.long 0xECC++0x03 line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xECC++0x03 hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0))) group.long 0xED0++0x03 line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED0++0x03 hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4))) group.long 0xED4++0x03 line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED4++0x03 hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8))) group.long 0xED8++0x03 line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xED8++0x03 hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC))) group.long 0xEDC++0x03 line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEDC++0x03 hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0))) group.long 0xEE0++0x03 line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE0++0x03 hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4))) group.long 0xEE4++0x03 line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE4++0x03 hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8))) group.long 0xEE8++0x03 line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEE8++0x03 hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC))) group.long 0xEEC++0x03 line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEEC++0x03 hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0))) group.long 0xEF0++0x03 line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF0++0x03 hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60" endif if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4))) group.long 0xEF4++0x03 line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" textline " " bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER" else hgroup.long 0xEF4++0x03 hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61" endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10) hgroup.long 0x0F00++0x03 hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" hgroup.long 0xF10++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" hgroup.long 0xF14++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" hgroup.long 0xF18++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" hgroup.long 0xF1C++0x03 hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" hgroup.long 0xF20++0x03 hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" hgroup.long 0xF24++0x03 hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" hgroup.long 0xF28++0x03 hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" hgroup.long 0xF2C++0x03 hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" group.long 0xF10++0x03 line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0" group.long 0xF14++0x03 line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1" group.long 0xF18++0x03 line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2" group.long 0xF1C++0x03 line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3" group.long 0xF20++0x03 line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0" group.long 0xF24++0x03 line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1" group.long 0xF28++0x03 line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2" group.long 0xF2C++0x03 line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3" endif tree.end width 24. tree "Interrupt Routing Registers" group.quad 0x6100++0x07 line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6108++0x07 line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6110++0x07 line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6118++0x07 line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6120++0x07 line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6128++0x07 line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6130++0x07 line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6138++0x07 line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6140++0x07 line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6148++0x07 line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6150++0x07 line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6158++0x07 line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6160++0x07 line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6168++0x07 line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6170++0x07 line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6178++0x07 line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6180++0x07 line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6188++0x07 line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6190++0x07 line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6198++0x07 line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A0++0x07 line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61A8++0x07 line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B0++0x07 line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61B8++0x07 line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C0++0x07 line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61C8++0x07 line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D0++0x07 line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61D8++0x07 line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E0++0x07 line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61E8++0x07 line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F0++0x07 line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x61F8++0x07 line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6200++0x07 line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6208++0x07 line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6210++0x07 line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6218++0x07 line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6220++0x07 line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6228++0x07 line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6230++0x07 line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6238++0x07 line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6240++0x07 line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6248++0x07 line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6250++0x07 line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6258++0x07 line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6260++0x07 line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6268++0x07 line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6270++0x07 line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6278++0x07 line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6280++0x07 line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6288++0x07 line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6290++0x07 line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6298++0x07 line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A0++0x07 line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62A8++0x07 line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B0++0x07 line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62B8++0x07 line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C0++0x07 line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62C8++0x07 line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D0++0x07 line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62D8++0x07 line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E0++0x07 line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62E8++0x07 line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F0++0x07 line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x62F8++0x07 line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6300++0x07 line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6308++0x07 line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6310++0x07 line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6318++0x07 line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 " hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6320++0x07 line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6328++0x07 line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6330++0x07 line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6338++0x07 line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6340++0x07 line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6348++0x07 line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6350++0x07 line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6358++0x07 line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6360++0x07 line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6368++0x07 line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6370++0x07 line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6378++0x07 line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6380++0x07 line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6388++0x07 line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6390++0x07 line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6398++0x07 line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A0++0x07 line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63A8++0x07 line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B0++0x07 line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63B8++0x07 line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C0++0x07 line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63C8++0x07 line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D0++0x07 line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63D8++0x07 line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E0++0x07 line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63E8++0x07 line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F0++0x07 line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x63F8++0x07 line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6400++0x07 line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6408++0x07 line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6410++0x07 line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6418++0x07 line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6420++0x07 line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6428++0x07 line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6430++0x07 line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6438++0x07 line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6440++0x07 line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6448++0x07 line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6450++0x07 line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6458++0x07 line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6460++0x07 line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6468++0x07 line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6470++0x07 line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6478++0x07 line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6480++0x07 line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6488++0x07 line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6490++0x07 line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6498++0x07 line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A0++0x07 line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64A8++0x07 line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B0++0x07 line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64B8++0x07 line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C0++0x07 line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64C8++0x07 line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D0++0x07 line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64D8++0x07 line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E0++0x07 line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64E8++0x07 line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F0++0x07 line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x64F8++0x07 line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6500++0x07 line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6508++0x07 line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6510++0x07 line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6518++0x07 line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6520++0x07 line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6528++0x07 line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6530++0x07 line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6538++0x07 line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6540++0x07 line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6548++0x07 line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6550++0x07 line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6558++0x07 line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6560++0x07 line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6568++0x07 line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6570++0x07 line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6578++0x07 line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6580++0x07 line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6588++0x07 line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6590++0x07 line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6598++0x07 line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A0++0x07 line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65A8++0x07 line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B0++0x07 line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65B8++0x07 line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C0++0x07 line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65C8++0x07 line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D0++0x07 line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65D8++0x07 line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E0++0x07 line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65E8++0x07 line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F0++0x07 line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x65F8++0x07 line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6600++0x07 line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6608++0x07 line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6610++0x07 line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6618++0x07 line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6620++0x07 line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6628++0x07 line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6630++0x07 line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6638++0x07 line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6640++0x07 line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6648++0x07 line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6650++0x07 line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6658++0x07 line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6660++0x07 line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6668++0x07 line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6670++0x07 line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6678++0x07 line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6680++0x07 line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6688++0x07 line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6690++0x07 line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6698++0x07 line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A0++0x07 line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66A8++0x07 line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B0++0x07 line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66B8++0x07 line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C0++0x07 line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66C8++0x07 line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D0++0x07 line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66D8++0x07 line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E0++0x07 line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66E8++0x07 line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F0++0x07 line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x66F8++0x07 line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6700++0x07 line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6708++0x07 line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6710++0x07 line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6718++0x07 line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6720++0x07 line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6728++0x07 line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6730++0x07 line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6738++0x07 line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6740++0x07 line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6748++0x07 line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6750++0x07 line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6758++0x07 line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6760++0x07 line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6768++0x07 line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6770++0x07 line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6778++0x07 line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6780++0x07 line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6788++0x07 line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6790++0x07 line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6798++0x07 line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A0++0x07 line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67A8++0x07 line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B0++0x07 line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67B8++0x07 line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C0++0x07 line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67C8++0x07 line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D0++0x07 line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67D8++0x07 line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E0++0x07 line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67E8++0x07 line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F0++0x07 line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x67F8++0x07 line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6800++0x07 line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6808++0x07 line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6810++0x07 line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6818++0x07 line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6820++0x07 line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6828++0x07 line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6830++0x07 line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6838++0x07 line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6840++0x07 line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6848++0x07 line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6850++0x07 line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6858++0x07 line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6860++0x07 line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6868++0x07 line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6870++0x07 line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6878++0x07 line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6880++0x07 line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6888++0x07 line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6890++0x07 line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6898++0x07 line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A0++0x07 line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68A8++0x07 line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B0++0x07 line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68B8++0x07 line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C0++0x07 line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68C8++0x07 line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D0++0x07 line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68D8++0x07 line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E0++0x07 line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68E8++0x07 line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F0++0x07 line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x68F8++0x07 line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6900++0x07 line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6908++0x07 line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6910++0x07 line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6918++0x07 line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6920++0x07 line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6928++0x07 line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6930++0x07 line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6938++0x07 line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6940++0x07 line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6948++0x07 line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6950++0x07 line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6958++0x07 line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6960++0x07 line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6968++0x07 line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6970++0x07 line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6978++0x07 line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6980++0x07 line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6988++0x07 line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6990++0x07 line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6998++0x07 line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A0++0x07 line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69A8++0x07 line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B0++0x07 line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69B8++0x07 line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C0++0x07 line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69C8++0x07 line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D0++0x07 line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69D8++0x07 line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E0++0x07 line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69E8++0x07 line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F0++0x07 line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x69F8++0x07 line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A00++0x07 line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A08++0x07 line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A10++0x07 line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A18++0x07 line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A20++0x07 line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A28++0x07 line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A30++0x07 line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A38++0x07 line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A40++0x07 line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A48++0x07 line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A50++0x07 line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A58++0x07 line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A60++0x07 line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A68++0x07 line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A70++0x07 line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A78++0x07 line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A80++0x07 line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A88++0x07 line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A90++0x07 line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6A98++0x07 line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA0++0x07 line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AA8++0x07 line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB0++0x07 line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AB8++0x07 line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC0++0x07 line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AC8++0x07 line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD0++0x07 line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AD8++0x07 line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE0++0x07 line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AE8++0x07 line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF0++0x07 line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6AF8++0x07 line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B00++0x07 line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B08++0x07 line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B10++0x07 line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B18++0x07 line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B20++0x07 line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B28++0x07 line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B30++0x07 line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B38++0x07 line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B40++0x07 line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B48++0x07 line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B50++0x07 line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B58++0x07 line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B60++0x07 line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B68++0x07 line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B70++0x07 line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B78++0x07 line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B80++0x07 line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B88++0x07 line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B90++0x07 line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6B98++0x07 line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA0++0x07 line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BA8++0x07 line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB0++0x07 line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BB8++0x07 line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC0++0x07 line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BC8++0x07 line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD0++0x07 line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BD8++0x07 line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE0++0x07 line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BE8++0x07 line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF0++0x07 line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6BF8++0x07 line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C00++0x07 line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C08++0x07 line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C10++0x07 line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C18++0x07 line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C20++0x07 line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C28++0x07 line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C30++0x07 line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C38++0x07 line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C40++0x07 line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C48++0x07 line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C50++0x07 line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C58++0x07 line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C60++0x07 line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C68++0x07 line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C70++0x07 line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C78++0x07 line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C80++0x07 line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C88++0x07 line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C90++0x07 line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6C98++0x07 line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA0++0x07 line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CA8++0x07 line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB0++0x07 line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CB8++0x07 line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC0++0x07 line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CC8++0x07 line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD0++0x07 line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CD8++0x07 line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE0++0x07 line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CE8++0x07 line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF0++0x07 line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6CF8++0x07 line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D00++0x07 line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D08++0x07 line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D10++0x07 line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D18++0x07 line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D20++0x07 line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D28++0x07 line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D30++0x07 line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D38++0x07 line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D40++0x07 line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D48++0x07 line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D50++0x07 line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D58++0x07 line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D60++0x07 line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D68++0x07 line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D70++0x07 line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D78++0x07 line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D80++0x07 line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D88++0x07 line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D90++0x07 line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6D98++0x07 line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA0++0x07 line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DA8++0x07 line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB0++0x07 line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DB8++0x07 line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC0++0x07 line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DC8++0x07 line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD0++0x07 line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DD8++0x07 line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE0++0x07 line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DE8++0x07 line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF0++0x07 line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6DF8++0x07 line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E00++0x07 line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E08++0x07 line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E10++0x07 line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E18++0x07 line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E20++0x07 line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E28++0x07 line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E30++0x07 line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E38++0x07 line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E40++0x07 line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E48++0x07 line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E50++0x07 line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E58++0x07 line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E60++0x07 line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E68++0x07 line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E70++0x07 line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E78++0x07 line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E80++0x07 line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E88++0x07 line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E90++0x07 line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6E98++0x07 line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA0++0x07 line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EA8++0x07 line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB0++0x07 line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EB8++0x07 line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC0++0x07 line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EC8++0x07 line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED0++0x07 line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6ED8++0x07 line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE0++0x07 line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EE8++0x07 line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF0++0x07 line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6EF8++0x07 line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F00++0x07 line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F08++0x07 line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F10++0x07 line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F18++0x07 line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F20++0x07 line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F28++0x07 line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F30++0x07 line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F38++0x07 line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F40++0x07 line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F48++0x07 line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F50++0x07 line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F58++0x07 line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F60++0x07 line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F68++0x07 line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F70++0x07 line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F78++0x07 line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F80++0x07 line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F88++0x07 line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F90++0x07 line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6F98++0x07 line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA0++0x07 line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FA8++0x07 line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB0++0x07 line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FB8++0x07 line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC0++0x07 line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FC8++0x07 line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD0++0x07 line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FD8++0x07 line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE0++0x07 line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FE8++0x07 line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF0++0x07 line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x6FF8++0x07 line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7000++0x07 line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7008++0x07 line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7010++0x07 line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7018++0x07 line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7020++0x07 line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7028++0x07 line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7030++0x07 line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7038++0x07 line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7040++0x07 line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7048++0x07 line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7050++0x07 line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7058++0x07 line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7060++0x07 line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7068++0x07 line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7070++0x07 line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7078++0x07 line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7080++0x07 line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7088++0x07 line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7090++0x07 line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7098++0x07 line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A0++0x07 line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70A8++0x07 line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B0++0x07 line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70B8++0x07 line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C0++0x07 line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70C8++0x07 line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D0++0x07 line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70D8++0x07 line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E0++0x07 line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70E8++0x07 line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F0++0x07 line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x70F8++0x07 line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7100++0x07 line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7108++0x07 line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7110++0x07 line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7118++0x07 line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7120++0x07 line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7128++0x07 line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7130++0x07 line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7138++0x07 line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7140++0x07 line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7148++0x07 line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7150++0x07 line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7158++0x07 line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7160++0x07 line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7168++0x07 line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7170++0x07 line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7178++0x07 line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7180++0x07 line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7188++0x07 line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7190++0x07 line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7198++0x07 line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A0++0x07 line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71A8++0x07 line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B0++0x07 line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71B8++0x07 line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C0++0x07 line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71C8++0x07 line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D0++0x07 line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71D8++0x07 line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E0++0x07 line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71E8++0x07 line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F0++0x07 line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x71F8++0x07 line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7200++0x07 line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7208++0x07 line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7210++0x07 line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7218++0x07 line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7220++0x07 line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7228++0x07 line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7230++0x07 line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7238++0x07 line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7240++0x07 line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7248++0x07 line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7250++0x07 line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7258++0x07 line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7260++0x07 line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7268++0x07 line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7270++0x07 line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7278++0x07 line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7280++0x07 line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7288++0x07 line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7290++0x07 line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7298++0x07 line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A0++0x07 line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72A8++0x07 line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B0++0x07 line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72B8++0x07 line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C0++0x07 line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72C8++0x07 line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D0++0x07 line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72D8++0x07 line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E0++0x07 line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72E8++0x07 line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F0++0x07 line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x72F8++0x07 line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7300++0x07 line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7308++0x07 line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7310++0x07 line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7318++0x07 line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7320++0x07 line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7328++0x07 line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7330++0x07 line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7338++0x07 line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7340++0x07 line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7348++0x07 line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7350++0x07 line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7358++0x07 line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7360++0x07 line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7368++0x07 line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7370++0x07 line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7378++0x07 line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7380++0x07 line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7388++0x07 line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7390++0x07 line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7398++0x07 line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A0++0x07 line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73A8++0x07 line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B0++0x07 line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73B8++0x07 line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C0++0x07 line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73C8++0x07 line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D0++0x07 line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73D8++0x07 line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E0++0x07 line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73E8++0x07 line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F0++0x07 line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x73F8++0x07 line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7400++0x07 line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7408++0x07 line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7410++0x07 line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7418++0x07 line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7420++0x07 line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7428++0x07 line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7430++0x07 line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7438++0x07 line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7440++0x07 line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7448++0x07 line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7450++0x07 line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7458++0x07 line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7460++0x07 line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7468++0x07 line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7470++0x07 line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7478++0x07 line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7480++0x07 line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7488++0x07 line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7490++0x07 line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7498++0x07 line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A0++0x07 line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74A8++0x07 line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B0++0x07 line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74B8++0x07 line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C0++0x07 line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74C8++0x07 line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D0++0x07 line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74D8++0x07 line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E0++0x07 line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74E8++0x07 line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F0++0x07 line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x74F8++0x07 line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7500++0x07 line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7508++0x07 line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7510++0x07 line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7518++0x07 line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7520++0x07 line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7528++0x07 line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7530++0x07 line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7538++0x07 line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7540++0x07 line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7548++0x07 line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7550++0x07 line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7558++0x07 line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7560++0x07 line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7568++0x07 line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7570++0x07 line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7578++0x07 line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7580++0x07 line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7588++0x07 line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7590++0x07 line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7598++0x07 line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A0++0x07 line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75A8++0x07 line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B0++0x07 line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75B8++0x07 line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C0++0x07 line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75C8++0x07 line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D0++0x07 line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75D8++0x07 line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E0++0x07 line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75E8++0x07 line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F0++0x07 line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x75F8++0x07 line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7600++0x07 line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7608++0x07 line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7610++0x07 line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7618++0x07 line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7620++0x07 line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7628++0x07 line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7630++0x07 line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7638++0x07 line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7640++0x07 line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7648++0x07 line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7650++0x07 line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7658++0x07 line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7660++0x07 line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7668++0x07 line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7670++0x07 line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7678++0x07 line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7680++0x07 line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7688++0x07 line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7690++0x07 line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7698++0x07 line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A0++0x07 line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76A8++0x07 line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B0++0x07 line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76B8++0x07 line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C0++0x07 line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76C8++0x07 line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D0++0x07 line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76D8++0x07 line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E0++0x07 line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76E8++0x07 line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F0++0x07 line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x76F8++0x07 line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7700++0x07 line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7708++0x07 line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7710++0x07 line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7718++0x07 line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7720++0x07 line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7728++0x07 line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7730++0x07 line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7738++0x07 line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7740++0x07 line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7748++0x07 line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7750++0x07 line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7758++0x07 line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7760++0x07 line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7768++0x07 line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7770++0x07 line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7778++0x07 line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7780++0x07 line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7788++0x07 line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7790++0x07 line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7798++0x07 line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A0++0x07 line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77A8++0x07 line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B0++0x07 line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77B8++0x07 line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C0++0x07 line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77C8++0x07 line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D0++0x07 line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77D8++0x07 line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E0++0x07 line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77E8++0x07 line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F0++0x07 line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x77F8++0x07 line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7800++0x07 line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7808++0x07 line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7810++0x07 line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7818++0x07 line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7820++0x07 line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7828++0x07 line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7830++0x07 line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7838++0x07 line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7840++0x07 line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7848++0x07 line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7850++0x07 line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7858++0x07 line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7860++0x07 line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7868++0x07 line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7870++0x07 line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7878++0x07 line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7880++0x07 line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7888++0x07 line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7890++0x07 line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7898++0x07 line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A0++0x07 line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78A8++0x07 line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B0++0x07 line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78B8++0x07 line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C0++0x07 line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78C8++0x07 line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D0++0x07 line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78D8++0x07 line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E0++0x07 line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78E8++0x07 line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F0++0x07 line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x78F8++0x07 line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7900++0x07 line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7908++0x07 line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7910++0x07 line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7918++0x07 line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7920++0x07 line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7928++0x07 line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7930++0x07 line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7938++0x07 line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7940++0x07 line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7948++0x07 line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7950++0x07 line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7958++0x07 line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7960++0x07 line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7968++0x07 line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7970++0x07 line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7978++0x07 line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7980++0x07 line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7988++0x07 line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7990++0x07 line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7998++0x07 line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A0++0x07 line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79A8++0x07 line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B0++0x07 line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79B8++0x07 line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C0++0x07 line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79C8++0x07 line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D0++0x07 line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79D8++0x07 line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E0++0x07 line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79E8++0x07 line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F0++0x07 line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x79F8++0x07 line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A00++0x07 line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A08++0x07 line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A10++0x07 line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A18++0x07 line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A20++0x07 line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A28++0x07 line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A30++0x07 line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A38++0x07 line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A40++0x07 line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A48++0x07 line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A50++0x07 line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A58++0x07 line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A60++0x07 line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A68++0x07 line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A70++0x07 line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A78++0x07 line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A80++0x07 line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A88++0x07 line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A90++0x07 line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7A98++0x07 line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA0++0x07 line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AA8++0x07 line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB0++0x07 line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AB8++0x07 line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC0++0x07 line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AC8++0x07 line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD0++0x07 line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AD8++0x07 line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE0++0x07 line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AE8++0x07 line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF0++0x07 line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7AF8++0x07 line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B00++0x07 line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B08++0x07 line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B10++0x07 line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B18++0x07 line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B20++0x07 line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B28++0x07 line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B30++0x07 line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B38++0x07 line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B40++0x07 line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B48++0x07 line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B50++0x07 line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B58++0x07 line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B60++0x07 line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B68++0x07 line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B70++0x07 line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B78++0x07 line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B80++0x07 line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B88++0x07 line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B90++0x07 line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7B98++0x07 line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA0++0x07 line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BA8++0x07 line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB0++0x07 line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BB8++0x07 line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC0++0x07 line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BC8++0x07 line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD0++0x07 line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BD8++0x07 line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE0++0x07 line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BE8++0x07 line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF0++0x07 line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7BF8++0x07 line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C00++0x07 line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C08++0x07 line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C10++0x07 line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C18++0x07 line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C20++0x07 line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C28++0x07 line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C30++0x07 line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C38++0x07 line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C40++0x07 line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C48++0x07 line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C50++0x07 line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C58++0x07 line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C60++0x07 line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C68++0x07 line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C70++0x07 line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C78++0x07 line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C80++0x07 line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C88++0x07 line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C90++0x07 line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7C98++0x07 line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA0++0x07 line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CA8++0x07 line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB0++0x07 line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CB8++0x07 line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC0++0x07 line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CC8++0x07 line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD0++0x07 line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CD8++0x07 line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE0++0x07 line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CE8++0x07 line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF0++0x07 line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7CF8++0x07 line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D00++0x07 line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D08++0x07 line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D10++0x07 line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D18++0x07 line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D20++0x07 line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D28++0x07 line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D30++0x07 line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D38++0x07 line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D40++0x07 line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D48++0x07 line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D50++0x07 line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D58++0x07 line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D60++0x07 line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D68++0x07 line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D70++0x07 line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D78++0x07 line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D80++0x07 line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D88++0x07 line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D90++0x07 line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7D98++0x07 line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA0++0x07 line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DA8++0x07 line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB0++0x07 line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DB8++0x07 line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC0++0x07 line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DC8++0x07 line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD0++0x07 line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DD8++0x07 line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE0++0x07 line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DE8++0x07 line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF0++0x07 line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7DF8++0x07 line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E00++0x07 line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E08++0x07 line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E10++0x07 line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E18++0x07 line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E20++0x07 line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E28++0x07 line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E30++0x07 line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E38++0x07 line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E40++0x07 line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E48++0x07 line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E50++0x07 line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E58++0x07 line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E60++0x07 line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E68++0x07 line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E70++0x07 line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E78++0x07 line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E80++0x07 line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E88++0x07 line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E90++0x07 line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7E98++0x07 line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA0++0x07 line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EA8++0x07 line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB0++0x07 line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EB8++0x07 line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC0++0x07 line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EC8++0x07 line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED0++0x07 line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7ED8++0x07 line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE0++0x07 line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EE8++0x07 line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF0++0x07 line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" group.quad 0x7EF8++0x07 line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991" hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3" bitfld.quad 0x00 31. " IRM ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node" textline " " hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2" hexmask.quad.byte 0x00 8.--15. 1. " AFF1 ,Affinity level 1" textline " " hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0" tree.end width 22. tree "Interrupt Class Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=1.) group.long (0xE000+0x8)++0x03 line.long 0x0 "GICD_ICLAR2,Interrupt Class Register 2" bitfld.long 0x00 31. " SPI047_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI047_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI046_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI046_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI045_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI045_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI044_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI044_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI043_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI043_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI042_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI042_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI041_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI041_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI040_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI040_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI039_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI039_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI038_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI038_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI037_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI037_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI036_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI036_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI035_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI035_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI034_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI034_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI033_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI033_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI032_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI032_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x8)++0x03 hide.long 0x0 "GICD_ICLAR2,Interrupt Class Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=1.) group.long (0xE000+0xc)++0x03 line.long 0x0 "GICD_ICLAR3,Interrupt Class Register 3" bitfld.long 0x00 31. " SPI063_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI063_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI062_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI062_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI061_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI061_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI060_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI060_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI059_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI059_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI058_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI058_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI057_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI057_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI056_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI056_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI055_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI055_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI054_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI054_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI053_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI053_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI052_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI052_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI051_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI051_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI050_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI050_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI049_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI049_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI048_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI048_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xc)++0x03 hide.long 0x0 "GICD_ICLAR3,Interrupt Class Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=2.) group.long (0xE000+0x10)++0x03 line.long 0x0 "GICD_ICLAR4,Interrupt Class Register 4" bitfld.long 0x00 31. " SPI079_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI079_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI078_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI078_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI077_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI077_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI076_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI076_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI075_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI075_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI074_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI074_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI073_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI073_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI072_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI072_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI071_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI071_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI070_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI070_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI069_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI069_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI068_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI068_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI067_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI067_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI066_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI066_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI065_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI065_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI064_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI064_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x10)++0x03 hide.long 0x0 "GICD_ICLAR4,Interrupt Class Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=2.) group.long (0xE000+0x14)++0x03 line.long 0x0 "GICD_ICLAR5,Interrupt Class Register 5" bitfld.long 0x00 31. " SPI095_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI095_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI094_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI094_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI093_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI093_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI092_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI092_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI091_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI091_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI090_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI090_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI089_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI089_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI088_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI088_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI087_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI087_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI086_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI086_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI085_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI085_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI084_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI084_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI083_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI083_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI082_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI082_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI081_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI081_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI080_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI080_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x14)++0x03 hide.long 0x0 "GICD_ICLAR5,Interrupt Class Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=3.) group.long (0xE000+0x18)++0x03 line.long 0x0 "GICD_ICLAR6,Interrupt Class Register 6" bitfld.long 0x00 31. " SPI111_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI111_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI110_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI110_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI109_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI109_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI108_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI108_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI107_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI107_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI106_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI106_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI105_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI105_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI104_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI104_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI103_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI103_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI102_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI102_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI101_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI101_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI100_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI100_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI099_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI099_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI098_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI098_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI097_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI097_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI096_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI096_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x18)++0x03 hide.long 0x0 "GICD_ICLAR6,Interrupt Class Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=3.) group.long (0xE000+0x1c)++0x03 line.long 0x0 "GICD_ICLAR7,Interrupt Class Register 7" bitfld.long 0x00 31. " SPI127_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI127_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI126_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI126_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI125_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI125_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI124_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI124_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI123_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI123_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI122_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI122_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI121_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI121_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI120_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI120_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI119_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI119_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI118_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI118_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI117_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI117_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI116_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI116_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI115_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI115_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI114_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI114_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI113_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI113_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI112_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI112_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x1c)++0x03 hide.long 0x0 "GICD_ICLAR7,Interrupt Class Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=4.) group.long (0xE000+0x20)++0x03 line.long 0x0 "GICD_ICLAR8,Interrupt Class Register 8" bitfld.long 0x00 31. " SPI143_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI143_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI142_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI142_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI141_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI141_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI140_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI140_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI139_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI139_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI138_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI138_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI137_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI137_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI136_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI136_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI135_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI135_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI134_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI134_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI133_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI133_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI132_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI132_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI131_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI131_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI130_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI130_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI129_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI129_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI128_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI128_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x20)++0x03 hide.long 0x0 "GICD_ICLAR8,Interrupt Class Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=4.) group.long (0xE000+0x24)++0x03 line.long 0x0 "GICD_ICLAR9,Interrupt Class Register 9" bitfld.long 0x00 31. " SPI159_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI159_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI158_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI158_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI157_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI157_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI156_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI156_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI155_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI155_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI154_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI154_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI153_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI153_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI152_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI152_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI151_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI151_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI150_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI150_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI149_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI149_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI148_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI148_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI147_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI147_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI146_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI146_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI145_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI145_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI144_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI144_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x24)++0x03 hide.long 0x0 "GICD_ICLAR9,Interrupt Class Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=5.) group.long (0xE000+0x28)++0x03 line.long 0x0 "GICD_ICLAR10,Interrupt Class Register 10" bitfld.long 0x00 31. " SPI175_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI175_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI174_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI174_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI173_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI173_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI172_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI172_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI171_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI171_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI170_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI170_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI169_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI169_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI168_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI168_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI167_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI167_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI166_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI166_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI165_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI165_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI164_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI164_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI163_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI163_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI162_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI162_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI161_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI161_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI160_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI160_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x28)++0x03 hide.long 0x0 "GICD_ICLAR10,Interrupt Class Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=5.) group.long (0xE000+0x2c)++0x03 line.long 0x0 "GICD_ICLAR11,Interrupt Class Register 11" bitfld.long 0x00 31. " SPI191_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI191_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI190_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI190_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI189_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI189_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI188_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI188_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI187_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI187_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI186_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI186_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI185_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI185_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI184_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI184_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI183_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI183_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI182_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI182_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI181_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI181_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI180_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI180_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI179_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI179_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI178_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI178_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI177_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI177_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI176_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI176_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x2c)++0x03 hide.long 0x0 "GICD_ICLAR11,Interrupt Class Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=6.) group.long (0xE000+0x30)++0x03 line.long 0x0 "GICD_ICLAR12,Interrupt Class Register 12" bitfld.long 0x00 31. " SPI207_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI207_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI206_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI206_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI205_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI205_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI204_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI204_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI203_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI203_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI202_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI202_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI201_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI201_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI200_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI200_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI199_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI199_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI198_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI198_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI197_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI197_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI196_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI196_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI195_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI195_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI194_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI194_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI193_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI193_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI192_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI192_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x30)++0x03 hide.long 0x0 "GICD_ICLAR12,Interrupt Class Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=6.) group.long (0xE000+0x34)++0x03 line.long 0x0 "GICD_ICLAR13,Interrupt Class Register 13" bitfld.long 0x00 31. " SPI223_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI223_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI222_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI222_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI221_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI221_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI220_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI220_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI219_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI219_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI218_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI218_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI217_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI217_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI216_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI216_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI215_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI215_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI214_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI214_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI213_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI213_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI212_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI212_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI211_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI211_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI210_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI210_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI209_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI209_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI208_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI208_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x34)++0x03 hide.long 0x0 "GICD_ICLAR13,Interrupt Class Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=7.) group.long (0xE000+0x38)++0x03 line.long 0x0 "GICD_ICLAR14,Interrupt Class Register 14" bitfld.long 0x00 31. " SPI239_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI239_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI238_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI238_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI237_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI237_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI236_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI236_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI235_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI235_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI234_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI234_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI233_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI233_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI232_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI232_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI231_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI231_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI230_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI230_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI229_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI229_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI228_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI228_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI227_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI227_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI226_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI226_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI225_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI225_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI224_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI224_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x38)++0x03 hide.long 0x0 "GICD_ICLAR14,Interrupt Class Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=7.) group.long (0xE000+0x3c)++0x03 line.long 0x0 "GICD_ICLAR15,Interrupt Class Register 15" bitfld.long 0x00 31. " SPI255_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI255_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI254_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI254_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI253_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI253_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI252_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI252_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI251_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI251_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI250_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI250_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI249_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI249_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI248_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI248_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI247_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI247_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI246_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI246_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI245_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI245_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI244_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI244_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI243_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI243_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI242_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI242_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI241_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI241_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI240_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI240_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x3c)++0x03 hide.long 0x0 "GICD_ICLAR15,Interrupt Class Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=8.) group.long (0xE000+0x40)++0x03 line.long 0x0 "GICD_ICLAR16,Interrupt Class Register 16" bitfld.long 0x00 31. " SPI271_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI271_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI270_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI270_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI269_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI269_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI268_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI268_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI267_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI267_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI266_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI266_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI265_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI265_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI264_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI264_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI263_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI263_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI262_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI262_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI261_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI261_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI260_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI260_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI259_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI259_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI258_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI258_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI257_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI257_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI256_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI256_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x40)++0x03 hide.long 0x0 "GICD_ICLAR16,Interrupt Class Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=8.) group.long (0xE000+0x44)++0x03 line.long 0x0 "GICD_ICLAR17,Interrupt Class Register 17" bitfld.long 0x00 31. " SPI287_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI287_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI286_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI286_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI285_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI285_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI284_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI284_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI283_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI283_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI282_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI282_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI281_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI281_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI280_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI280_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI279_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI279_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI278_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI278_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI277_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI277_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI276_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI276_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI275_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI275_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI274_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI274_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI273_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI273_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI272_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI272_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x44)++0x03 hide.long 0x0 "GICD_ICLAR17,Interrupt Class Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=9.) group.long (0xE000+0x48)++0x03 line.long 0x0 "GICD_ICLAR18,Interrupt Class Register 18" bitfld.long 0x00 31. " SPI303_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI303_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI302_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI302_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI301_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI301_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI300_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI300_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI299_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI299_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI298_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI298_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI297_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI297_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI296_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI296_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI295_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI295_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI294_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI294_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI293_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI293_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI292_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI292_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI291_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI291_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI290_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI290_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI289_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI289_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI288_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI288_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x48)++0x03 hide.long 0x0 "GICD_ICLAR18,Interrupt Class Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=9.) group.long (0xE000+0x4c)++0x03 line.long 0x0 "GICD_ICLAR19,Interrupt Class Register 19" bitfld.long 0x00 31. " SPI319_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI319_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI318_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI318_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI317_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI317_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI316_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI316_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI315_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI315_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI314_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI314_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI313_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI313_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI312_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI312_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI311_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI311_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI310_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI310_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI309_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI309_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI308_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI308_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI307_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI307_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI306_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI306_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI305_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI305_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI304_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI304_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x4c)++0x03 hide.long 0x0 "GICD_ICLAR19,Interrupt Class Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=10.) group.long (0xE000+0x50)++0x03 line.long 0x0 "GICD_ICLAR20,Interrupt Class Register 20" bitfld.long 0x00 31. " SPI335_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI335_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI334_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI334_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI333_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI333_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI332_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI332_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI331_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI331_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI330_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI330_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI329_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI329_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI328_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI328_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI327_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI327_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI326_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI326_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI325_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI325_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI324_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI324_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI323_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI323_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI322_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI322_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI321_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI321_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI320_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI320_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x50)++0x03 hide.long 0x0 "GICD_ICLAR20,Interrupt Class Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=10.) group.long (0xE000+0x54)++0x03 line.long 0x0 "GICD_ICLAR21,Interrupt Class Register 21" bitfld.long 0x00 31. " SPI351_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI351_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI350_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI350_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI349_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI349_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI348_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI348_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI347_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI347_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI346_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI346_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI345_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI345_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI344_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI344_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI343_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI343_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI342_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI342_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI341_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI341_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI340_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI340_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI339_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI339_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI338_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI338_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI337_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI337_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI336_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI336_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x54)++0x03 hide.long 0x0 "GICD_ICLAR21,Interrupt Class Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=11.) group.long (0xE000+0x58)++0x03 line.long 0x0 "GICD_ICLAR22,Interrupt Class Register 22" bitfld.long 0x00 31. " SPI367_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI367_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI366_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI366_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI365_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI365_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI364_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI364_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI363_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI363_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI362_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI362_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI361_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI361_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI360_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI360_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI359_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI359_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI358_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI358_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI357_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI357_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI356_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI356_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI355_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI355_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI354_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI354_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI353_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI353_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI352_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI352_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x58)++0x03 hide.long 0x0 "GICD_ICLAR22,Interrupt Class Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=11.) group.long (0xE000+0x5c)++0x03 line.long 0x0 "GICD_ICLAR23,Interrupt Class Register 23" bitfld.long 0x00 31. " SPI383_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI383_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI382_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI382_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI381_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI381_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI380_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI380_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI379_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI379_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI378_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI378_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI377_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI377_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI376_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI376_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI375_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI375_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI374_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI374_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI373_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI373_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI372_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI372_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI371_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI371_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI370_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI370_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI369_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI369_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI368_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI368_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x5c)++0x03 hide.long 0x0 "GICD_ICLAR23,Interrupt Class Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=12.) group.long (0xE000+0x60)++0x03 line.long 0x0 "GICD_ICLAR24,Interrupt Class Register 24" bitfld.long 0x00 31. " SPI399_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI399_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI398_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI398_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI397_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI397_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI396_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI396_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI395_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI395_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI394_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI394_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI393_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI393_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI392_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI392_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI391_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI391_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI390_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI390_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI389_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI389_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI388_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI388_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI387_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI387_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI386_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI386_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI385_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI385_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI384_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI384_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x60)++0x03 hide.long 0x0 "GICD_ICLAR24,Interrupt Class Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=12.) group.long (0xE000+0x64)++0x03 line.long 0x0 "GICD_ICLAR25,Interrupt Class Register 25" bitfld.long 0x00 31. " SPI415_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI415_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI414_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI414_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI413_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI413_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI412_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI412_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI411_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI411_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI410_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI410_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI409_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI409_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI408_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI408_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI407_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI407_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI406_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI406_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI405_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI405_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI404_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI404_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI403_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI403_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI402_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI402_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI401_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI401_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI400_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI400_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x64)++0x03 hide.long 0x0 "GICD_ICLAR25,Interrupt Class Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=13.) group.long (0xE000+0x68)++0x03 line.long 0x0 "GICD_ICLAR26,Interrupt Class Register 26" bitfld.long 0x00 31. " SPI431_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI431_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI430_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI430_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI429_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI429_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI428_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI428_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI427_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI427_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI426_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI426_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI425_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI425_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI424_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI424_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI423_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI423_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI422_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI422_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI421_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI421_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI420_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI420_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI419_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI419_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI418_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI418_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI417_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI417_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI416_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI416_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x68)++0x03 hide.long 0x0 "GICD_ICLAR26,Interrupt Class Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=13.) group.long (0xE000+0x6c)++0x03 line.long 0x0 "GICD_ICLAR27,Interrupt Class Register 27" bitfld.long 0x00 31. " SPI447_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI447_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI446_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI446_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI445_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI445_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI444_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI444_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI443_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI443_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI442_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI442_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI441_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI441_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI440_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI440_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI439_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI439_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI438_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI438_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI437_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI437_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI436_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI436_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI435_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI435_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI434_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI434_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI433_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI433_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI432_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI432_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x6c)++0x03 hide.long 0x0 "GICD_ICLAR27,Interrupt Class Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=14.) group.long (0xE000+0x70)++0x03 line.long 0x0 "GICD_ICLAR28,Interrupt Class Register 28" bitfld.long 0x00 31. " SPI463_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI463_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI462_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI462_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI461_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI461_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI460_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI460_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI459_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI459_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI458_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI458_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI457_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI457_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI456_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI456_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI455_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI455_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI454_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI454_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI453_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI453_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI452_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI452_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI451_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI451_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI450_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI450_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI449_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI449_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI448_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI448_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x70)++0x03 hide.long 0x0 "GICD_ICLAR28,Interrupt Class Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=14.) group.long (0xE000+0x74)++0x03 line.long 0x0 "GICD_ICLAR29,Interrupt Class Register 29" bitfld.long 0x00 31. " SPI479_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI479_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI478_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI478_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI477_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI477_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI476_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI476_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI475_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI475_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI474_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI474_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI473_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI473_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI472_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI472_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI471_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI471_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI470_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI470_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI469_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI469_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI468_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI468_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI467_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI467_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI466_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI466_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI465_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI465_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI464_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI464_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x74)++0x03 hide.long 0x0 "GICD_ICLAR29,Interrupt Class Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=15.) group.long (0xE000+0x78)++0x03 line.long 0x0 "GICD_ICLAR30,Interrupt Class Register 30" bitfld.long 0x00 31. " SPI495_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI495_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI494_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI494_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI493_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI493_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI492_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI492_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI491_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI491_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI490_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI490_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI489_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI489_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI488_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI488_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI487_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI487_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI486_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI486_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI485_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI485_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI484_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI484_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI483_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI483_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI482_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI482_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI481_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI481_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI480_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI480_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x78)++0x03 hide.long 0x0 "GICD_ICLAR30,Interrupt Class Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=15.) group.long (0xE000+0x7c)++0x03 line.long 0x0 "GICD_ICLAR31,Interrupt Class Register 31" bitfld.long 0x00 31. " SPI511_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI511_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI510_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI510_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI509_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI509_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI508_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI508_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI507_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI507_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI506_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI506_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI505_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI505_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI504_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI504_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI503_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI503_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI502_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI502_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI501_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI501_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI500_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI500_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI499_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI499_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI498_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI498_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI497_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI497_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI496_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI496_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x7c)++0x03 hide.long 0x0 "GICD_ICLAR31,Interrupt Class Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=16.) group.long (0xE000+0x80)++0x03 line.long 0x0 "GICD_ICLAR32,Interrupt Class Register 32" bitfld.long 0x00 31. " SPI527_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI527_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI526_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI526_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI525_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI525_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI524_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI524_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI523_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI523_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI522_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI522_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI521_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI521_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI520_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI520_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI519_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI519_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI518_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI518_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI517_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI517_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI516_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI516_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI515_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI515_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI514_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI514_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI513_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI513_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI512_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI512_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x80)++0x03 hide.long 0x0 "GICD_ICLAR32,Interrupt Class Register 32" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=16.) group.long (0xE000+0x84)++0x03 line.long 0x0 "GICD_ICLAR33,Interrupt Class Register 33" bitfld.long 0x00 31. " SPI543_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI543_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI542_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI542_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI541_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI541_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI540_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI540_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI539_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI539_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI538_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI538_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI537_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI537_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI536_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI536_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI535_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI535_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI534_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI534_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI533_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI533_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI532_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI532_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI531_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI531_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI530_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI530_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI529_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI529_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI528_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI528_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x84)++0x03 hide.long 0x0 "GICD_ICLAR33,Interrupt Class Register 33" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=17.) group.long (0xE000+0x88)++0x03 line.long 0x0 "GICD_ICLAR34,Interrupt Class Register 34" bitfld.long 0x00 31. " SPI559_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI559_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI558_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI558_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI557_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI557_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI556_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI556_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI555_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI555_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI554_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI554_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI553_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI553_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI552_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI552_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI551_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI551_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI550_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI550_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI549_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI549_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI548_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI548_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI547_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI547_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI546_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI546_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI545_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI545_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI544_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI544_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x88)++0x03 hide.long 0x0 "GICD_ICLAR34,Interrupt Class Register 34" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=17.) group.long (0xE000+0x8c)++0x03 line.long 0x0 "GICD_ICLAR35,Interrupt Class Register 35" bitfld.long 0x00 31. " SPI575_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI575_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI574_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI574_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI573_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI573_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI572_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI572_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI571_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI571_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI570_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI570_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI569_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI569_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI568_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI568_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI567_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI567_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI566_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI566_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI565_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI565_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI564_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI564_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI563_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI563_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI562_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI562_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI561_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI561_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI560_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI560_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x8c)++0x03 hide.long 0x0 "GICD_ICLAR35,Interrupt Class Register 35" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=18.) group.long (0xE000+0x90)++0x03 line.long 0x0 "GICD_ICLAR36,Interrupt Class Register 36" bitfld.long 0x00 31. " SPI591_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI591_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI590_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI590_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI589_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI589_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI588_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI588_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI587_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI587_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI586_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI586_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI585_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI585_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI584_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI584_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI583_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI583_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI582_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI582_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI581_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI581_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI580_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI580_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI579_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI579_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI578_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI578_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI577_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI577_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI576_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI576_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x90)++0x03 hide.long 0x0 "GICD_ICLAR36,Interrupt Class Register 36" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=18.) group.long (0xE000+0x94)++0x03 line.long 0x0 "GICD_ICLAR37,Interrupt Class Register 37" bitfld.long 0x00 31. " SPI607_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI607_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI606_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI606_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI605_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI605_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI604_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI604_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI603_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI603_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI602_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI602_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI601_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI601_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI600_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI600_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI599_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI599_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI598_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI598_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI597_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI597_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI596_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI596_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI595_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI595_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI594_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI594_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI593_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI593_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI592_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI592_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x94)++0x03 hide.long 0x0 "GICD_ICLAR37,Interrupt Class Register 37" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=19.) group.long (0xE000+0x98)++0x03 line.long 0x0 "GICD_ICLAR38,Interrupt Class Register 38" bitfld.long 0x00 31. " SPI623_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI623_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI622_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI622_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI621_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI621_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI620_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI620_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI619_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI619_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI618_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI618_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI617_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI617_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI616_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI616_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI615_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI615_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI614_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI614_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI613_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI613_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI612_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI612_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI611_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI611_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI610_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI610_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI609_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI609_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI608_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI608_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x98)++0x03 hide.long 0x0 "GICD_ICLAR38,Interrupt Class Register 38" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=19.) group.long (0xE000+0x9c)++0x03 line.long 0x0 "GICD_ICLAR39,Interrupt Class Register 39" bitfld.long 0x00 31. " SPI639_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI639_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI638_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI638_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI637_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI637_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI636_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI636_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI635_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI635_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI634_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI634_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI633_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI633_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI632_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI632_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI631_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI631_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI630_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI630_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI629_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI629_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI628_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI628_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI627_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI627_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI626_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI626_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI625_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI625_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI624_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI624_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0x9c)++0x03 hide.long 0x0 "GICD_ICLAR39,Interrupt Class Register 39" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=20.) group.long (0xE000+0xa0)++0x03 line.long 0x0 "GICD_ICLAR40,Interrupt Class Register 40" bitfld.long 0x00 31. " SPI655_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI655_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI654_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI654_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI653_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI653_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI652_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI652_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI651_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI651_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI650_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI650_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI649_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI649_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI648_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI648_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI647_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI647_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI646_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI646_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI645_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI645_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI644_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI644_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI643_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI643_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI642_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI642_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI641_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI641_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI640_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI640_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xa0)++0x03 hide.long 0x0 "GICD_ICLAR40,Interrupt Class Register 40" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=20.) group.long (0xE000+0xa4)++0x03 line.long 0x0 "GICD_ICLAR41,Interrupt Class Register 41" bitfld.long 0x00 31. " SPI671_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI671_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI670_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI670_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI669_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI669_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI668_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI668_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI667_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI667_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI666_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI666_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI665_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI665_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI664_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI664_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI663_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI663_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI662_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI662_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI661_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI661_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI660_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI660_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI659_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI659_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI658_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI658_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI657_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI657_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI656_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI656_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xa4)++0x03 hide.long 0x0 "GICD_ICLAR41,Interrupt Class Register 41" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=21.) group.long (0xE000+0xa8)++0x03 line.long 0x0 "GICD_ICLAR42,Interrupt Class Register 42" bitfld.long 0x00 31. " SPI687_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI687_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI686_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI686_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI685_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI685_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI684_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI684_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI683_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI683_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI682_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI682_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI681_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI681_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI680_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI680_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI679_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI679_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI678_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI678_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI677_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI677_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI676_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI676_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI675_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI675_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI674_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI674_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI673_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI673_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI672_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI672_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xa8)++0x03 hide.long 0x0 "GICD_ICLAR42,Interrupt Class Register 42" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=21.) group.long (0xE000+0xac)++0x03 line.long 0x0 "GICD_ICLAR43,Interrupt Class Register 43" bitfld.long 0x00 31. " SPI703_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI703_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI702_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI702_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI701_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI701_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI700_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI700_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI699_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI699_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI698_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI698_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI697_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI697_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI696_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI696_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI695_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI695_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI694_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI694_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI693_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI693_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI692_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI692_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI691_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI691_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI690_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI690_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI689_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI689_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI688_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI688_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xac)++0x03 hide.long 0x0 "GICD_ICLAR43,Interrupt Class Register 43" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=22.) group.long (0xE000+0xb0)++0x03 line.long 0x0 "GICD_ICLAR44,Interrupt Class Register 44" bitfld.long 0x00 31. " SPI719_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI719_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI718_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI718_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI717_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI717_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI716_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI716_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI715_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI715_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI714_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI714_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI713_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI713_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI712_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI712_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI711_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI711_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI710_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI710_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI709_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI709_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI708_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI708_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI707_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI707_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI706_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI706_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI705_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI705_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI704_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI704_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xb0)++0x03 hide.long 0x0 "GICD_ICLAR44,Interrupt Class Register 44" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=22.) group.long (0xE000+0xb4)++0x03 line.long 0x0 "GICD_ICLAR45,Interrupt Class Register 45" bitfld.long 0x00 31. " SPI735_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI735_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI734_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI734_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI733_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI733_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI732_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI732_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI731_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI731_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI730_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI730_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI729_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI729_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI728_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI728_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI727_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI727_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI726_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI726_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI725_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI725_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI724_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI724_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI723_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI723_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI722_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI722_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI721_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI721_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI720_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI720_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xb4)++0x03 hide.long 0x0 "GICD_ICLAR45,Interrupt Class Register 45" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=23.) group.long (0xE000+0xb8)++0x03 line.long 0x0 "GICD_ICLAR46,Interrupt Class Register 46" bitfld.long 0x00 31. " SPI751_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI751_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI750_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI750_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI749_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI749_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI748_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI748_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI747_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI747_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI746_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI746_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI745_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI745_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI744_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI744_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI743_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI743_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI742_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI742_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI741_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI741_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI740_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI740_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI739_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI739_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI738_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI738_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI737_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI737_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI736_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI736_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xb8)++0x03 hide.long 0x0 "GICD_ICLAR46,Interrupt Class Register 46" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=23.) group.long (0xE000+0xbc)++0x03 line.long 0x0 "GICD_ICLAR47,Interrupt Class Register 47" bitfld.long 0x00 31. " SPI767_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI767_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI766_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI766_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI765_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI765_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI764_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI764_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI763_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI763_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI762_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI762_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI761_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI761_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI760_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI760_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI759_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI759_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI758_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI758_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI757_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI757_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI756_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI756_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI755_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI755_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI754_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI754_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI753_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI753_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI752_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI752_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xbc)++0x03 hide.long 0x0 "GICD_ICLAR47,Interrupt Class Register 47" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=24.) group.long (0xE000+0xc0)++0x03 line.long 0x0 "GICD_ICLAR48,Interrupt Class Register 48" bitfld.long 0x00 31. " SPI783_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI783_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI782_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI782_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI781_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI781_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI780_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI780_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI779_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI779_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI778_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI778_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI777_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI777_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI776_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI776_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI775_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI775_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI774_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI774_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI773_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI773_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI772_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI772_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI771_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI771_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI770_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI770_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI769_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI769_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI768_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI768_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xc0)++0x03 hide.long 0x0 "GICD_ICLAR48,Interrupt Class Register 48" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=24.) group.long (0xE000+0xc4)++0x03 line.long 0x0 "GICD_ICLAR49,Interrupt Class Register 49" bitfld.long 0x00 31. " SPI799_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI799_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI798_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI798_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI797_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI797_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI796_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI796_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI795_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI795_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI794_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI794_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI793_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI793_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI792_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI792_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI791_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI791_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI790_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI790_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI789_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI789_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI788_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI788_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI787_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI787_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI786_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI786_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI785_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI785_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI784_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI784_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xc4)++0x03 hide.long 0x0 "GICD_ICLAR49,Interrupt Class Register 49" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=25.) group.long (0xE000+0xc8)++0x03 line.long 0x0 "GICD_ICLAR50,Interrupt Class Register 50" bitfld.long 0x00 31. " SPI815_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI815_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI814_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI814_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI813_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI813_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI812_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI812_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI811_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI811_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI810_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI810_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI809_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI809_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI808_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI808_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI807_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI807_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI806_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI806_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI805_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI805_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI804_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI804_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI803_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI803_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI802_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI802_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI801_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI801_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI800_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI800_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xc8)++0x03 hide.long 0x0 "GICD_ICLAR50,Interrupt Class Register 50" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=25.) group.long (0xE000+0xcc)++0x03 line.long 0x0 "GICD_ICLAR51,Interrupt Class Register 51" bitfld.long 0x00 31. " SPI831_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI831_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI830_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI830_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI829_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI829_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI828_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI828_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI827_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI827_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI826_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI826_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI825_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI825_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI824_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI824_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI823_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI823_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI822_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI822_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI821_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI821_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI820_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI820_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI819_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI819_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI818_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI818_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI817_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI817_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI816_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI816_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xcc)++0x03 hide.long 0x0 "GICD_ICLAR51,Interrupt Class Register 51" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=26.) group.long (0xE000+0xd0)++0x03 line.long 0x0 "GICD_ICLAR52,Interrupt Class Register 52" bitfld.long 0x00 31. " SPI847_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI847_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI846_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI846_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI845_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI845_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI844_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI844_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI843_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI843_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI842_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI842_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI841_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI841_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI840_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI840_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI839_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI839_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI838_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI838_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI837_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI837_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI836_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI836_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI835_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI835_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI834_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI834_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI833_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI833_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI832_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI832_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xd0)++0x03 hide.long 0x0 "GICD_ICLAR52,Interrupt Class Register 52" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=26.) group.long (0xE000+0xd4)++0x03 line.long 0x0 "GICD_ICLAR53,Interrupt Class Register 53" bitfld.long 0x00 31. " SPI863_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI863_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI862_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI862_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI861_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI861_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI860_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI860_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI859_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI859_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI858_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI858_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI857_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI857_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI856_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI856_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI855_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI855_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI854_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI854_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI853_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI853_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI852_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI852_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI851_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI851_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI850_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI850_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI849_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI849_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI848_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI848_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xd4)++0x03 hide.long 0x0 "GICD_ICLAR53,Interrupt Class Register 53" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=27.) group.long (0xE000+0xd8)++0x03 line.long 0x0 "GICD_ICLAR54,Interrupt Class Register 54" bitfld.long 0x00 31. " SPI879_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI879_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI878_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI878_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI877_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI877_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI876_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI876_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI875_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI875_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI874_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI874_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI873_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI873_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI872_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI872_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI871_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI871_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI870_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI870_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI869_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI869_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI868_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI868_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI867_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI867_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI866_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI866_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI865_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI865_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI864_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI864_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xd8)++0x03 hide.long 0x0 "GICD_ICLAR54,Interrupt Class Register 54" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=27.) group.long (0xE000+0xdc)++0x03 line.long 0x0 "GICD_ICLAR55,Interrupt Class Register 55" bitfld.long 0x00 31. " SPI895_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI895_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI894_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI894_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI893_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI893_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI892_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI892_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI891_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI891_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI890_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI890_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI889_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI889_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI888_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI888_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI887_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI887_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI886_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI886_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI885_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI885_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI884_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI884_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI883_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI883_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI882_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI882_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI881_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI881_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI880_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI880_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xdc)++0x03 hide.long 0x0 "GICD_ICLAR55,Interrupt Class Register 55" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=28.) group.long (0xE000+0xe0)++0x03 line.long 0x0 "GICD_ICLAR56,Interrupt Class Register 56" bitfld.long 0x00 31. " SPI911_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI911_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI910_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI910_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI909_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI909_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI908_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI908_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI907_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI907_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI906_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI906_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI905_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI905_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI904_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI904_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI903_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI903_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI902_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI902_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI901_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI901_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI900_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI900_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI899_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI899_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI898_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI898_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI897_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI897_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI896_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI896_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xe0)++0x03 hide.long 0x0 "GICD_ICLAR56,Interrupt Class Register 56" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=28.) group.long (0xE000+0xe4)++0x03 line.long 0x0 "GICD_ICLAR57,Interrupt Class Register 57" bitfld.long 0x00 31. " SPI927_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI927_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI926_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI926_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI925_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI925_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI924_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI924_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI923_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI923_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI922_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI922_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI921_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI921_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI920_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI920_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI919_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI919_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI918_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI918_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI917_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI917_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI916_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI916_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI915_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI915_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI914_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI914_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI913_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI913_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI912_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI912_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xe4)++0x03 hide.long 0x0 "GICD_ICLAR57,Interrupt Class Register 57" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=29.) group.long (0xE000+0xe8)++0x03 line.long 0x0 "GICD_ICLAR58,Interrupt Class Register 58" bitfld.long 0x00 31. " SPI943_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI943_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI942_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI942_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI941_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI941_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI940_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI940_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI939_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI939_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI938_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI938_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI937_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI937_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI936_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI936_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI935_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI935_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI934_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI934_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI933_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI933_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI932_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI932_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI931_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI931_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI930_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI930_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI929_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI929_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI928_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI928_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xe8)++0x03 hide.long 0x0 "GICD_ICLAR58,Interrupt Class Register 58" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=29.) group.long (0xE000+0xec)++0x03 line.long 0x0 "GICD_ICLAR59,Interrupt Class Register 59" bitfld.long 0x00 31. " SPI959_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI959_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI958_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI958_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI957_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI957_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI956_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI956_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI955_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI955_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI954_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI954_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI953_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI953_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI952_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI952_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI951_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI951_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI950_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI950_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI949_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI949_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI948_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI948_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI947_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI947_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI946_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI946_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI945_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI945_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI944_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI944_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xec)++0x03 hide.long 0x0 "GICD_ICLAR59,Interrupt Class Register 59" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=30.) group.long (0xE000+0xf0)++0x03 line.long 0x0 "GICD_ICLAR60,Interrupt Class Register 60" bitfld.long 0x00 31. " SPI975_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI975_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI974_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI974_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI973_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI973_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI972_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI972_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI971_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI971_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI970_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI970_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI969_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI969_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI968_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI968_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI967_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI967_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI966_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI966_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI965_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI965_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI964_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI964_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI963_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI963_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI962_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI962_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI961_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI961_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI960_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI960_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xf0)++0x03 hide.long 0x0 "GICD_ICLAR60,Interrupt Class Register 60" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=30.) group.long (0xE000+0xf4)++0x03 line.long 0x0 "GICD_ICLAR61,Interrupt Class Register 61" bitfld.long 0x00 31. " SPI991_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 30. " SPI991_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 29. " SPI990_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 28. " SPI990_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 27. " SPI989_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 26. " SPI989_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 25. " SPI988_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 24. " SPI988_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 23. " SPI987_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 22. " SPI987_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 21. " SPI986_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 20. " SPI986_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 19. " SPI985_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 18. " SPI985_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 17. " SPI984_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 16. " SPI984_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 15. " SPI983_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 14. " SPI983_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 13. " SPI982_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 12. " SPI982_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 11. " SPI981_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 10. " SPI981_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 9. " SPI980_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 8. " SPI980_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 7. " SPI979_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 6. " SPI979_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 5. " SPI978_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 4. " SPI978_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" textline " " bitfld.long 0x00 3. " SPI977_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 2. " SPI977_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" bitfld.long 0x00 1. " SPI976_CLASS1 ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1" bitfld.long 0x00 0. " SPI976_CLASS0 ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1" else hgroup.long (0xE000+0xf4)++0x03 hide.long 0x0 "GICD_ICLAR61,Interrupt Class Register 61" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end tree "Interrupt Error Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=1.) group.long (0xE100+0x4)++0x03 line.long 0x0 "GICD_IERRR1,Interrupt Error Register 1" bitfld.long 0x00 31. " SPI049_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI048_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI047_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI046_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI047_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI046_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI045_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI044_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI045_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI044_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI043_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI042_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI043_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI042_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI041_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI040_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI041_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI040_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI039_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI038_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI039_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI038_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI037_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI036_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI037_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI036_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI035_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI034_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI035_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI034_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI033_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI032_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x4)++0x03 hide.long 0x0 "GICD_IERRR1,Interrupt Error Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=2.) group.long (0xE100+0x8)++0x03 line.long 0x0 "GICD_IERRR2,Interrupt Error Register 2" bitfld.long 0x00 31. " SPI081_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI080_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI079_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI078_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI079_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI078_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI077_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI076_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI077_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI076_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI075_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI074_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI075_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI074_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI073_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI072_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI073_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI072_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI071_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI070_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI071_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI070_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI069_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI068_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI069_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI068_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI067_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI066_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI067_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI066_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI065_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI064_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x8)++0x03 hide.long 0x0 "GICD_IERRR2,Interrupt Error Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=3.) group.long (0xE100+0xc)++0x03 line.long 0x0 "GICD_IERRR3,Interrupt Error Register 3" bitfld.long 0x00 31. " SPI113_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI112_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI111_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI110_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI111_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI110_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI109_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI108_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI109_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI108_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI107_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI106_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI107_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI106_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI105_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI104_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI105_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI104_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI103_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI102_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI103_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI102_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI101_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI100_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI101_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI100_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI099_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI098_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI099_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI098_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI097_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI096_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0xc)++0x03 hide.long 0x0 "GICD_IERRR3,Interrupt Error Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=4.) group.long (0xE100+0x10)++0x03 line.long 0x0 "GICD_IERRR4,Interrupt Error Register 4" bitfld.long 0x00 31. " SPI145_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI144_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI143_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI142_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI143_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI142_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI141_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI140_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI141_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI140_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI139_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI138_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI139_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI138_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI137_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI136_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI137_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI136_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI135_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI134_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI135_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI134_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI133_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI132_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI133_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI132_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI131_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI130_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI131_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI130_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI129_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI128_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x10)++0x03 hide.long 0x0 "GICD_IERRR4,Interrupt Error Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=5.) group.long (0xE100+0x14)++0x03 line.long 0x0 "GICD_IERRR5,Interrupt Error Register 5" bitfld.long 0x00 31. " SPI177_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI176_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI175_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI174_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI175_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI174_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI173_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI172_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI173_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI172_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI171_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI170_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI171_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI170_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI169_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI168_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI169_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI168_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI167_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI166_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI167_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI166_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI165_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI164_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI165_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI164_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI163_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI162_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI163_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI162_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI161_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI160_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x14)++0x03 hide.long 0x0 "GICD_IERRR5,Interrupt Error Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=6.) group.long (0xE100+0x18)++0x03 line.long 0x0 "GICD_IERRR6,Interrupt Error Register 6" bitfld.long 0x00 31. " SPI209_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI208_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI207_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI206_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI207_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI206_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI205_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI204_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI205_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI204_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI203_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI202_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI203_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI202_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI201_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI200_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI201_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI200_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI199_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI198_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI199_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI198_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI197_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI196_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI197_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI196_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI195_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI194_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI195_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI194_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI193_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI192_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x18)++0x03 hide.long 0x0 "GICD_IERRR6,Interrupt Error Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=7.) group.long (0xE100+0x1c)++0x03 line.long 0x0 "GICD_IERRR7,Interrupt Error Register 7" bitfld.long 0x00 31. " SPI241_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI240_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI239_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI238_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI239_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI238_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI237_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI236_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI237_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI236_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI235_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI234_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI235_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI234_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI233_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI232_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI233_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI232_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI231_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI230_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI231_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI230_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI229_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI228_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI229_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI228_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI227_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI226_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI227_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI226_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI225_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI224_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x1c)++0x03 hide.long 0x0 "GICD_IERRR7,Interrupt Error Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=8.) group.long (0xE100+0x20)++0x03 line.long 0x0 "GICD_IERRR8,Interrupt Error Register 8" bitfld.long 0x00 31. " SPI273_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI272_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI271_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI270_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI271_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI270_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI269_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI268_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI269_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI268_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI267_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI266_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI267_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI266_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI265_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI264_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI265_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI264_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI263_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI262_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI263_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI262_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI261_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI260_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI261_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI260_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI259_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI258_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI259_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI258_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI257_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI256_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x20)++0x03 hide.long 0x0 "GICD_IERRR8,Interrupt Error Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=9.) group.long (0xE100+0x24)++0x03 line.long 0x0 "GICD_IERRR9,Interrupt Error Register 9" bitfld.long 0x00 31. " SPI305_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI304_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI303_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI302_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI303_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI302_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI301_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI300_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI301_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI300_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI299_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI298_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI299_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI298_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI297_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI296_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI297_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI296_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI295_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI294_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI295_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI294_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI293_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI292_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI293_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI292_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI291_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI290_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI291_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI290_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI289_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI288_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x24)++0x03 hide.long 0x0 "GICD_IERRR9,Interrupt Error Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=10.) group.long (0xE100+0x28)++0x03 line.long 0x0 "GICD_IERRR10,Interrupt Error Register 10" bitfld.long 0x00 31. " SPI337_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI336_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI335_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI334_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI335_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI334_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI333_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI332_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI333_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI332_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI331_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI330_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI331_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI330_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI329_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI328_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI329_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI328_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI327_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI326_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI327_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI326_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI325_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI324_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI325_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI324_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI323_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI322_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI323_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI322_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI321_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI320_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x28)++0x03 hide.long 0x0 "GICD_IERRR10,Interrupt Error Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=11.) group.long (0xE100+0x2c)++0x03 line.long 0x0 "GICD_IERRR11,Interrupt Error Register 11" bitfld.long 0x00 31. " SPI369_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI368_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI367_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI366_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI367_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI366_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI365_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI364_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI365_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI364_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI363_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI362_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI363_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI362_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI361_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI360_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI361_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI360_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI359_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI358_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI359_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI358_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI357_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI356_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI357_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI356_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI355_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI354_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI355_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI354_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI353_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI352_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x2c)++0x03 hide.long 0x0 "GICD_IERRR11,Interrupt Error Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=12.) group.long (0xE100+0x30)++0x03 line.long 0x0 "GICD_IERRR12,Interrupt Error Register 12" bitfld.long 0x00 31. " SPI401_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI400_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI399_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI398_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI399_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI398_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI397_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI396_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI397_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI396_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI395_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI394_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI395_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI394_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI393_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI392_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI393_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI392_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI391_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI390_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI391_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI390_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI389_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI388_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI389_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI388_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI387_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI386_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI387_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI386_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI385_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI384_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x30)++0x03 hide.long 0x0 "GICD_IERRR12,Interrupt Error Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=13.) group.long (0xE100+0x34)++0x03 line.long 0x0 "GICD_IERRR13,Interrupt Error Register 13" bitfld.long 0x00 31. " SPI433_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI432_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI431_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI430_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI431_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI430_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI429_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI428_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI429_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI428_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI427_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI426_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI427_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI426_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI425_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI424_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI425_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI424_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI423_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI422_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI423_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI422_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI421_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI420_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI421_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI420_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI419_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI418_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI419_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI418_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI417_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI416_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x34)++0x03 hide.long 0x0 "GICD_IERRR13,Interrupt Error Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=14.) group.long (0xE100+0x38)++0x03 line.long 0x0 "GICD_IERRR14,Interrupt Error Register 14" bitfld.long 0x00 31. " SPI465_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI464_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI463_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI462_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI463_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI462_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI461_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI460_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI461_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI460_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI459_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI458_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI459_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI458_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI457_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI456_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI457_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI456_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI455_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI454_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI455_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI454_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI453_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI452_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI453_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI452_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI451_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI450_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI451_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI450_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI449_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI448_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x38)++0x03 hide.long 0x0 "GICD_IERRR14,Interrupt Error Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=15.) group.long (0xE100+0x3c)++0x03 line.long 0x0 "GICD_IERRR15,Interrupt Error Register 15" bitfld.long 0x00 31. " SPI497_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI496_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI495_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI494_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI495_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI494_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI493_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI492_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI493_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI492_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI491_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI490_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI491_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI490_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI489_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI488_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI489_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI488_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI487_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI486_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI487_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI486_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI485_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI484_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI485_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI484_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI483_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI482_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI483_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI482_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI481_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI480_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x3c)++0x03 hide.long 0x0 "GICD_IERRR15,Interrupt Error Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=16.) group.long (0xE100+0x40)++0x03 line.long 0x0 "GICD_IERRR16,Interrupt Error Register 16" bitfld.long 0x00 31. " SPI529_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI528_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI527_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI526_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI527_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI526_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI525_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI524_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI525_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI524_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI523_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI522_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI523_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI522_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI521_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI520_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI521_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI520_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI519_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI518_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI519_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI518_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI517_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI516_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI517_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI516_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI515_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI514_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI515_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI514_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI513_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI512_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x40)++0x03 hide.long 0x0 "GICD_IERRR16,Interrupt Error Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=17.) group.long (0xE100+0x44)++0x03 line.long 0x0 "GICD_IERRR17,Interrupt Error Register 17" bitfld.long 0x00 31. " SPI561_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI560_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI559_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI558_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI559_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI558_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI557_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI556_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI557_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI556_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI555_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI554_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI555_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI554_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI553_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI552_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI553_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI552_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI551_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI550_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI551_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI550_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI549_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI548_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI549_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI548_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI547_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI546_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI547_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI546_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI545_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI544_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x44)++0x03 hide.long 0x0 "GICD_IERRR17,Interrupt Error Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=18.) group.long (0xE100+0x48)++0x03 line.long 0x0 "GICD_IERRR18,Interrupt Error Register 18" bitfld.long 0x00 31. " SPI593_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI592_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI591_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI590_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI591_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI590_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI589_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI588_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI589_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI588_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI587_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI586_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI587_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI586_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI585_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI584_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI585_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI584_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI583_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI582_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI583_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI582_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI581_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI580_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI581_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI580_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI579_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI578_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI579_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI578_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI577_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI576_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x48)++0x03 hide.long 0x0 "GICD_IERRR18,Interrupt Error Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=19.) group.long (0xE100+0x4c)++0x03 line.long 0x0 "GICD_IERRR19,Interrupt Error Register 19" bitfld.long 0x00 31. " SPI625_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI624_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI623_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI622_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI623_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI622_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI621_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI620_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI621_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI620_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI619_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI618_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI619_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI618_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI617_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI616_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI617_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI616_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI615_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI614_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI615_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI614_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI613_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI612_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI613_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI612_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI611_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI610_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI611_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI610_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI609_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI608_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x4c)++0x03 hide.long 0x0 "GICD_IERRR19,Interrupt Error Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=20.) group.long (0xE100+0x50)++0x03 line.long 0x0 "GICD_IERRR20,Interrupt Error Register 20" bitfld.long 0x00 31. " SPI657_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI656_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI655_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI654_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI655_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI654_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI653_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI652_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI653_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI652_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI651_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI650_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI651_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI650_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI649_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI648_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI649_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI648_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI647_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI646_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI647_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI646_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI645_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI644_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI645_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI644_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI643_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI642_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI643_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI642_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI641_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI640_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x50)++0x03 hide.long 0x0 "GICD_IERRR20,Interrupt Error Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=21.) group.long (0xE100+0x54)++0x03 line.long 0x0 "GICD_IERRR21,Interrupt Error Register 21" bitfld.long 0x00 31. " SPI689_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI688_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI687_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI686_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI687_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI686_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI685_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI684_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI685_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI684_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI683_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI682_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI683_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI682_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI681_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI680_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI681_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI680_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI679_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI678_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI679_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI678_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI677_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI676_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI677_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI676_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI675_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI674_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI675_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI674_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI673_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI672_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x54)++0x03 hide.long 0x0 "GICD_IERRR21,Interrupt Error Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=22.) group.long (0xE100+0x58)++0x03 line.long 0x0 "GICD_IERRR22,Interrupt Error Register 22" bitfld.long 0x00 31. " SPI721_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI720_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI719_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI718_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI719_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI718_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI717_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI716_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI717_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI716_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI715_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI714_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI715_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI714_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI713_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI712_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI713_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI712_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI711_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI710_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI711_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI710_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI709_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI708_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI709_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI708_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI707_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI706_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI707_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI706_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI705_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI704_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x58)++0x03 hide.long 0x0 "GICD_IERRR22,Interrupt Error Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=23.) group.long (0xE100+0x5c)++0x03 line.long 0x0 "GICD_IERRR23,Interrupt Error Register 23" bitfld.long 0x00 31. " SPI753_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI752_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI751_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI750_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI751_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI750_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI749_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI748_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI749_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI748_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI747_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI746_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI747_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI746_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI745_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI744_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI745_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI744_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI743_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI742_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI743_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI742_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI741_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI740_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI741_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI740_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI739_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI738_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI739_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI738_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI737_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI736_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x5c)++0x03 hide.long 0x0 "GICD_IERRR23,Interrupt Error Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=24.) group.long (0xE100+0x60)++0x03 line.long 0x0 "GICD_IERRR24,Interrupt Error Register 24" bitfld.long 0x00 31. " SPI785_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI784_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI783_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI782_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI783_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI782_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI781_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI780_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI781_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI780_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI779_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI778_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI779_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI778_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI777_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI776_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI777_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI776_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI775_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI774_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI775_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI774_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI773_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI772_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI773_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI772_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI771_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI770_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI771_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI770_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI769_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI768_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x60)++0x03 hide.long 0x0 "GICD_IERRR24,Interrupt Error Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=25.) group.long (0xE100+0x64)++0x03 line.long 0x0 "GICD_IERRR25,Interrupt Error Register 25" bitfld.long 0x00 31. " SPI817_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI816_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI815_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI814_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI815_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI814_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI813_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI812_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI813_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI812_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI811_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI810_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI811_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI810_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI809_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI808_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI809_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI808_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI807_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI806_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI807_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI806_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI805_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI804_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI805_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI804_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI803_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI802_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI803_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI802_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI801_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI800_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x64)++0x03 hide.long 0x0 "GICD_IERRR25,Interrupt Error Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=26.) group.long (0xE100+0x68)++0x03 line.long 0x0 "GICD_IERRR26,Interrupt Error Register 26" bitfld.long 0x00 31. " SPI849_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI848_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI847_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI846_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI847_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI846_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI845_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI844_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI845_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI844_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI843_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI842_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI843_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI842_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI841_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI840_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI841_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI840_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI839_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI838_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI839_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI838_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI837_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI836_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI837_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI836_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI835_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI834_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI835_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI834_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI833_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI832_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x68)++0x03 hide.long 0x0 "GICD_IERRR26,Interrupt Error Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=27.) group.long (0xE100+0x6c)++0x03 line.long 0x0 "GICD_IERRR27,Interrupt Error Register 27" bitfld.long 0x00 31. " SPI881_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI880_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI879_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI878_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI879_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI878_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI877_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI876_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI877_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI876_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI875_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI874_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI875_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI874_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI873_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI872_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI873_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI872_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI871_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI870_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI871_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI870_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI869_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI868_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI869_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI868_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI867_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI866_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI867_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI866_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI865_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI864_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x6c)++0x03 hide.long 0x0 "GICD_IERRR27,Interrupt Error Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=28.) group.long (0xE100+0x70)++0x03 line.long 0x0 "GICD_IERRR28,Interrupt Error Register 28" bitfld.long 0x00 31. " SPI913_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI912_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI911_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI910_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI911_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI910_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI909_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI908_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI909_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI908_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI907_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI906_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI907_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI906_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI905_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI904_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI905_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI904_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI903_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI902_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI903_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI902_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI901_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI900_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI901_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI900_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI899_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI898_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI899_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI898_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI897_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI896_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x70)++0x03 hide.long 0x0 "GICD_IERRR28,Interrupt Error Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=29.) group.long (0xE100+0x74)++0x03 line.long 0x0 "GICD_IERRR29,Interrupt Error Register 29" bitfld.long 0x00 31. " SPI945_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI944_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI943_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI942_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI943_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI942_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI941_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI940_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI941_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI940_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI939_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI938_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI939_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI938_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI937_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI936_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI937_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI936_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI935_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI934_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI935_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI934_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI933_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI932_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI933_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI932_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI931_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI930_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI931_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI930_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI929_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI928_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x74)++0x03 hide.long 0x0 "GICD_IERRR29,Interrupt Error Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=30.) group.long (0xE100+0x78)++0x03 line.long 0x0 "GICD_IERRR30,Interrupt Error Register 30" bitfld.long 0x00 31. " SPI977_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 30. " SPI976_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 29. " SPI975_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 28. " SPI974_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 27. " SPI975_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 26. " SPI974_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 25. " SPI973_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 24. " SPI972_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 23. " SPI973_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 22. " SPI972_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 21. " SPI971_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 20. " SPI970_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 19. " SPI971_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 18. " SPI970_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 17. " SPI969_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 16. " SPI968_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 15. " SPI969_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 14. " SPI968_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 13. " SPI967_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 12. " SPI966_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 11. " SPI967_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 10. " SPI966_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 9. " SPI965_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 8. " SPI964_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 7. " SPI965_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 6. " SPI964_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 5. " SPI963_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 4. " SPI962_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" textline " " bitfld.long 0x00 3. " SPI963_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 2. " SPI962_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 1. " SPI961_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" bitfld.long 0x00 0. " SPI960_STATUS ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR" else hgroup.long (0xE100+0x78)++0x03 hide.long 0x0 "GICD_IERRR30,Interrupt Error Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 14. tree "Peripheral/Component ID Registers" rgroup.quad 0xF000++0x07 line.quad 0x00 "GICD_CFGID,Configuration ID Register" bitfld.quad 0x00 44.--47. " AFF3 ,Returns the Affinity3 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40.--43. " AFF2 ,Returns the Affinity2 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 36.--39. " AFF1 ,Returns the Affinity1 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.quad 0x00 32.--35. " AFF0 ,Returns the Affinity0 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 15.--20. " SPIS ,SPI Groups" "0,1,2,3,4,5,6,7,8,9,10,%d..." bitfld.quad 0x00 14. " AFSL ,Chip affinity selection level" "0,1" textline " " bitfld.quad 0x00 13. " DLPI ,Direct LPI registers supported" "Not Supported,Supported" bitfld.quad 0x00 12. " LPIS ,LPI supported" "Not Supported,Supported" bitfld.quad 0x00 4.--7. " SNUM ,Chip number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.quad 0x00 0. " SO ,Chip offline" "OFFLINE,ONLINE" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-600 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end width 0x0B base (COMP.BASE("GICD",-1.)+0x20000) AUTOINDENT.ON CENTER TREE tree "Trace and Debug" tree "Error Record 0: Software error in GICD programming" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((0.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR0FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (0.==0.) group.quad ((0.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((0.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((0.&0x1)==0x0) group.quad ((0.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((0.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((0.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((0.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+0.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((0.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((0.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register" else group.quad ((0.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((0.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR0MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((0.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR0FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((0.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register" NEWLINE hgroup.quad ((0.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((0.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register" hgroup.quad ((0.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR0MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((0.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR0FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (0.==0.) group.quad ((0.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((0.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((0.&0x1)==0x0) group.quad ((0.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((0.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((0.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((0.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+0.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((0.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((0.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register" else group.quad ((0.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((0.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR0MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((0.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR0FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((0.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register" NEWLINE hgroup.quad ((0.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((0.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register" hgroup.quad ((0.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR0MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 1: Correctable SPI RAM errors" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((1.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR1FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (1.==0.) group.quad ((1.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((1.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((1.&0x1)==0x0) group.quad ((1.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((1.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((1.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((1.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+1.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((1.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((1.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register" else group.quad ((1.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((1.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR1MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((1.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR1FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((1.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register" NEWLINE hgroup.quad ((1.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((1.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register" hgroup.quad ((1.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR1MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((1.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR1FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (1.==0.) group.quad ((1.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((1.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((1.&0x1)==0x0) group.quad ((1.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((1.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((1.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((1.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+1.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((1.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((1.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register" else group.quad ((1.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((1.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR1MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((1.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR1FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((1.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register" NEWLINE hgroup.quad ((1.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((1.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register" hgroup.quad ((1.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR1MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 2: Uncorrectable SPI RAM errors" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((2.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR2FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (2.==0.) group.quad ((2.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((2.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((2.&0x1)==0x0) group.quad ((2.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((2.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((2.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((2.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+2.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((2.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((2.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register" else group.quad ((2.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((2.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR2MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((2.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR2FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((2.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register" NEWLINE hgroup.quad ((2.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((2.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register" hgroup.quad ((2.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR2MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((2.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR2FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (2.==0.) group.quad ((2.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((2.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((2.&0x1)==0x0) group.quad ((2.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((2.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((2.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((2.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+2.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((2.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((2.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register" else group.quad ((2.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((2.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR2MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((2.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR2FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((2.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register" NEWLINE hgroup.quad ((2.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((2.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register" hgroup.quad ((2.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR2MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 3: Correctable SGI RAM errors" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((3.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR3FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (3.==0.) group.quad ((3.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((3.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((3.&0x1)==0x0) group.quad ((3.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((3.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((3.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((3.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+3.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((3.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((3.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register" else group.quad ((3.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((3.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR3MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((3.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR3FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((3.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register" NEWLINE hgroup.quad ((3.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((3.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register" hgroup.quad ((3.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR3MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((3.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR3FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (3.==0.) group.quad ((3.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((3.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((3.&0x1)==0x0) group.quad ((3.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((3.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((3.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((3.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+3.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((3.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((3.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register" else group.quad ((3.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((3.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR3MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((3.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR3FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((3.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register" NEWLINE hgroup.quad ((3.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((3.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register" hgroup.quad ((3.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR3MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 4: Uncorrectable SGI RAM errors" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((4.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR4FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (4.==0.) group.quad ((4.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((4.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((4.&0x1)==0x0) group.quad ((4.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((4.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((4.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((4.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+4.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((4.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((4.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register" else group.quad ((4.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((4.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR4MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((4.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR4FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((4.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register" NEWLINE hgroup.quad ((4.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((4.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register" hgroup.quad ((4.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR4MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((4.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR4FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (4.==0.) group.quad ((4.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((4.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((4.&0x1)==0x0) group.quad ((4.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((4.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((4.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((4.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+4.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((4.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((4.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register" else group.quad ((4.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((4.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR4MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((4.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR4FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((4.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register" NEWLINE hgroup.quad ((4.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((4.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register" hgroup.quad ((4.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR4MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 5: Correctable TGT cache errors" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((5.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR5FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (5.==0.) group.quad ((5.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((5.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((5.&0x1)==0x0) group.quad ((5.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((5.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((5.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((5.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+5.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((5.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((5.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register" else group.quad ((5.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((5.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR5MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((5.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR5FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((5.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register" NEWLINE hgroup.quad ((5.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((5.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register" hgroup.quad ((5.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR5MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((5.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR5FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (5.==0.) group.quad ((5.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((5.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((5.&0x1)==0x0) group.quad ((5.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((5.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((5.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((5.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+5.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((5.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((5.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register" else group.quad ((5.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((5.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR5MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((5.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR5FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((5.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register" NEWLINE hgroup.quad ((5.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((5.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register" hgroup.quad ((5.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR5MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 6: Uncorrectable TGT cache errors" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((6.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR6FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (6.==0.) group.quad ((6.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((6.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((6.&0x1)==0x0) group.quad ((6.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((6.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((6.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((6.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+6.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((6.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((6.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register" else group.quad ((6.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((6.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR6MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((6.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR6FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((6.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register" NEWLINE hgroup.quad ((6.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((6.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register" hgroup.quad ((6.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR6MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((6.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR6FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (6.==0.) group.quad ((6.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((6.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((6.&0x1)==0x0) group.quad ((6.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((6.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((6.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((6.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+6.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((6.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((6.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register" else group.quad ((6.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((6.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR6MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((6.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR6FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((6.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register" NEWLINE hgroup.quad ((6.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((6.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register" hgroup.quad ((6.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR6MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 7: Correctable PPI RAM errors" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((7.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR7FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (7.==0.) group.quad ((7.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((7.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((7.&0x1)==0x0) group.quad ((7.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((7.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((7.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((7.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+7.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((7.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((7.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register" else group.quad ((7.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((7.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR7MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((7.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR7FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((7.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register" NEWLINE hgroup.quad ((7.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((7.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register" hgroup.quad ((7.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR7MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((7.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR7FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (7.==0.) group.quad ((7.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((7.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((7.&0x1)==0x0) group.quad ((7.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((7.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((7.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((7.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+7.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((7.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((7.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register" else group.quad ((7.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((7.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR7MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((7.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR7FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((7.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register" NEWLINE hgroup.quad ((7.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((7.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register" hgroup.quad ((7.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR7MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 8: Uncorrectable PPI RAM errors" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((8.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR8FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (8.==0.) group.quad ((8.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((8.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((8.&0x1)==0x0) group.quad ((8.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((8.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((8.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((8.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+8.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((8.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((8.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register" else group.quad ((8.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((8.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR8MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((8.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR8FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((8.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register" NEWLINE hgroup.quad ((8.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((8.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register" hgroup.quad ((8.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR8MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((8.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR8FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (8.==0.) group.quad ((8.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((8.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((8.&0x1)==0x0) group.quad ((8.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((8.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((8.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((8.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+8.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((8.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((8.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register" else group.quad ((8.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((8.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR8MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((8.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR8FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((8.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register" NEWLINE hgroup.quad ((8.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((8.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register" hgroup.quad ((8.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR8MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 9: Correctable LPI RAM errors" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((9.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR9FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (9.==0.) group.quad ((9.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((9.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((9.&0x1)==0x0) group.quad ((9.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((9.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((9.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((9.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+9.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((9.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((9.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register" else group.quad ((9.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((9.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR9MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((9.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR9FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((9.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register" NEWLINE hgroup.quad ((9.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((9.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register" hgroup.quad ((9.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR9MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((9.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR9FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (9.==0.) group.quad ((9.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((9.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((9.&0x1)==0x0) group.quad ((9.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((9.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((9.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((9.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+9.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((9.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((9.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register" else group.quad ((9.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((9.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR9MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((9.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR9FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((9.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register" NEWLINE hgroup.quad ((9.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((9.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register" hgroup.quad ((9.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR9MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 10: Uncorrectable LPI RAM errors" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((10.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR10FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (10.==0.) group.quad ((10.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((10.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((10.&0x1)==0x0) group.quad ((10.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((10.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((10.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((10.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+10.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((10.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((10.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register" else group.quad ((10.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((10.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR10MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((10.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR10FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((10.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register" NEWLINE hgroup.quad ((10.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((10.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register" hgroup.quad ((10.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR10MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((10.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR10FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (10.==0.) group.quad ((10.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((10.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((10.&0x1)==0x0) group.quad ((10.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((10.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((10.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((10.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+10.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((10.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((10.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register" else group.quad ((10.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((10.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR10MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((10.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR10FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((10.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register" NEWLINE hgroup.quad ((10.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((10.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register" hgroup.quad ((10.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR10MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 11: Correctable error from ITS RAM" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((11.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR11FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (11.==0.) group.quad ((11.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((11.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((11.&0x1)==0x0) group.quad ((11.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((11.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((11.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((11.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+11.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((11.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((11.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register" else group.quad ((11.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((11.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR11MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((11.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR11FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((11.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register" NEWLINE hgroup.quad ((11.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((11.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register" hgroup.quad ((11.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR11MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((11.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR11FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (11.==0.) group.quad ((11.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((11.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((11.&0x1)==0x0) group.quad ((11.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((11.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((11.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((11.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+11.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((11.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((11.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register" else group.quad ((11.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((11.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR11MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((11.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR11FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((11.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register" NEWLINE hgroup.quad ((11.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((11.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register" hgroup.quad ((11.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR11MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 12: Uncorrectable error from ITS RAM" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((12.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR12FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (12.==0.) group.quad ((12.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((12.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((12.&0x1)==0x0) group.quad ((12.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((12.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((12.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((12.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+12.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((12.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((12.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register" else group.quad ((12.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((12.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR12MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((12.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR12FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((12.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register" NEWLINE hgroup.quad ((12.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((12.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register" hgroup.quad ((12.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR12MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((12.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR12FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (12.==0.) group.quad ((12.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((12.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((12.&0x1)==0x0) group.quad ((12.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((12.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((12.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((12.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+12.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((12.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((12.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register" else group.quad ((12.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((12.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR12MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((12.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR12FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((12.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register" NEWLINE hgroup.quad ((12.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((12.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register" hgroup.quad ((12.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR12MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Error Record 13: Software error in ITS" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) if 1==1 rgroup.quad ((13.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR13FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (13.==0.) group.quad ((13.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((13.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((13.&0x1)==0x0) group.quad ((13.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((13.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((13.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((13.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+13.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((13.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((13.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register" else group.quad ((13.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((13.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR13MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((13.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR13FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((13.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register" NEWLINE hgroup.quad ((13.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((13.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register" hgroup.quad ((13.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR13MISC0,Error Record Miscellaneous Register 0" endif else if 0==1 rgroup.quad ((13.*0x40)+0x000)++0x07 line.quad 0x00 "GICT_ERR13FR,Error Record Feature Register" bitfld.quad 0x00 15. " RP ,Repeat corrected error counter implemented." "0,1" hexmask.quad.byte 0x00 12.--14. 1. " CEC ,Corrected error count." bitfld.quad 0x00 10.--11. " CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 8.--9. " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 6.--7. " FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?" bitfld.quad 0x00 4.--5. " UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?" NEWLINE bitfld.quad 0x00 2.--3. " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?" bitfld.quad 0x00 0.--1. " ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?" if (13.==0.) group.quad ((13.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((13.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." elif ((13.&0x1)==0x0) group.quad ((13.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" bitfld.quad 0x00 4. " UE ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert" group.quad ((13.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 20.--21. " UET ," "?,UEO,?,UER" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." else group.quad ((13.*0x40)+0x008)++0x07 line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register" bitfld.quad 0x00 15. " RP ,Controls whether an error response to a transition is reported." "Report,No Report" bitfld.quad 0x00 8. " CFI ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert" NEWLINE bitfld.quad 0x00 3. " FI ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1" bitfld.quad 0x00 2. " UI ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1" group.quad ((13.*0x40)+0x010)++0x07 line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register" bitfld.quad 0x00 31. " AV ,Indicates if the GICT_ERRADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid" bitfld.quad 0x00 30. " V ,Indicates if this GICT_ERRSTATUS register is valid and one or more errors are recorded." "Not Valid,Valid" bitfld.quad 0x00 29. " UE ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1" NEWLINE bitfld.quad 0x00 28. " ER ,Indicates that at least one error has been reported over ACE-Lite." "0,1" bitfld.quad 0x00 27. " OF ,Indicates that record has overflowed." "0,1" bitfld.quad 0x00 26. " MV ,Indicates if the GICT miscellaneous GICT_ERRMISC0 and GICT_ERRMISC1 registers are valid." "Not Valid,Valid" NEWLINE bitfld.quad 0x00 24.--25. " CE ,Indicates if an CE was recorded." "No Record,?,Record,?" hexmask.quad.byte 0x00 8.--15. 1. " IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information." NEWLINE hexmask.quad.byte 0x00 0.--7. 1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information." endif if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+13.*0x40)+0x010))&0x80000000)==0x80000000 rgroup.quad ((13.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00) hgroup.quad ((13.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register" else group.quad ((13.*0x40)+0x018)++0x07 line.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register" bitfld.quad 0x00 63. " NS ,Indicates if address is secure or non-secure." "Secure,Non-Secure" hexmask.quad.quad 0x00 0.--47. 1. " PADDR ,The error address." endif group.quad ((13.*0x40)+0x020)++0x07 line.quad 0x00 "GICT_ERR13MISC0,Error Record Miscellaneous Register 0" bitfld.quad 0x00 41. " RE ,Rounding Error. The rounding error counter is under-reporting." "0,1" bitfld.quad 0x00 40. " OVERFLOW ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1" hexmask.quad.word 0x00 32.--39. 1. " COUNT ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome." NEWLINE hexmask.quad.long 0x00 0.--31. 1. " DATA ,Information associated with the error. See table in the TRM." else hgroup.quad ((13.*0x40)+0x000)++0x07 hide.quad 0x00 "GICT_ERR13FR,Error Record Feature Register" NEWLINE NEWLINE hgroup.quad ((13.*0x40)+0x008)++0x07 hide.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register" NEWLINE hgroup.quad ((13.*0x40)+0x010)++0x07 hide.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register" NEWLINE NEWLINE NEWLINE hgroup.quad ((13.*0x40)+0x018)++0x07 hide.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register" hgroup.quad ((13.*0x40)+0x020)++0x07 hide.quad 0x00 "GICT_ERR13MISC0,Error Record Miscellaneous Register 0" endif endif tree.end tree "Common Registers" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) group.quad ((10.*0x40)+0x028)++0x07 line.quad 0x00 "GICT_ERR10MISC1,Error Record Miscellaneous Register 1" hexmask.quad.quad 0x00 0.--63. 1. " INFO ,Value represents either data that is written to the LPI RAM when an uncorrectable error is detected, or ITS software information for one of 13, or more, error records." else hgroup.quad (((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x028)++0x07 hide.quad 0x00 "GICT_ERR10MISC1,Error Record Miscellaneous Register 1" endif rgroup.quad 0xE000++0x07 line.quad 0x00 "GICT_ERRGSR,Group Status Register" rgroup.long 0xFFBC++0x03 line.long 0x00 "GICT_ERRDEVARCH,Device Architecture register" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2))) rgroup.long 0xFFC8++0x03 line.long 0x00 "GICT_ERRIDR,Error Record ID Register" bitfld.long 0x00 0.--15. " NUM , Identifies the device configuration." "?,?,?,?,?,?,?,?,?,?,No LPI available,?,LPI available but no ITS,?,LPI available and 1*ITS,LPI available and 2*ITS,LPI available and 3*ITS,?..." else hgroup.long 0xFFC8++0x03 hide.long 0x00 "GICT_ERRIDR,Error Record ID Register" endif tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICT_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICT_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICT_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-600 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICT_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICT_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICT_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICT_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICT_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICT_CIDR0,Component ID0 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICT_CIDR1,Component ID1 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICT_CIDR2,Component ID2 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICT_CIDR3,Component ID3 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end AUTOINDENT.OFF base (COMP.BASE("GICD",-1.)+0x30000) AUTOINDENT.ON CENTER TREE tree "Performance Monitoring Unit" group.long (0x000+0x0)++0x03 line.long 0x00 "GICP_EVCNTR0,Event Counter Register" hexmask.long.long 0x00 0.--31. 1. " COUNT ,Counter value. If the counter is enabled, the counter value increments when an event matching GICP_EVTYPERn.EVENT occurs." group.long (0x400+0x0)++0x03 line.long 0x00 "GICP_EVTYPER0,Event Type Configuration Register" bitfld.long 0x00 31. " OVFCAP ,When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set." "0,1" bitfld.long 0x00 16.--17. " EVENTTYPE ,Event tracking type." "Count,Accumulate,Maximum,Reserved" hexmask.long.byte 0x00 0.--7. 1. " EVENT ,Event identifier. All events reset to an UNKNOWN value. Registers corresponding to unimplemented counters are RES0. See table in TRM" rgroup.long (0x600+0x0)++0x03 line.long 0x00 "GICP_SVR0,Shadow Value Registers" hexmask.long.long 0x00 0.--31. 1. " COUNT,Captured counter value.This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn." group.long (0xA00+0x0)++0x03 line.long 0x00 "GICP_FR0,Filter Registers" bitfld.long 0x00 30.--31. " FILTERTYPE ,Filter Type." "Core,INTID,Chip/ITS,Reserved" bitfld.long 0x00 29. " FILTERENCODING ,Filter Encoding." "Range,Exact" hexmask.long.byte 0x00 0.--15. 1. " Filter ,If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this register is ignored." NEWLINE group.long (0x000+0x4)++0x03 line.long 0x00 "GICP_EVCNTR1,Event Counter Register" hexmask.long.long 0x00 0.--31. 1. " COUNT ,Counter value. If the counter is enabled, the counter value increments when an event matching GICP_EVTYPERn.EVENT occurs." group.long (0x400+0x4)++0x03 line.long 0x00 "GICP_EVTYPER1,Event Type Configuration Register" bitfld.long 0x00 31. " OVFCAP ,When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set." "0,1" bitfld.long 0x00 16.--17. " EVENTTYPE ,Event tracking type." "Count,Accumulate,Maximum,Reserved" hexmask.long.byte 0x00 0.--7. 1. " EVENT ,Event identifier. All events reset to an UNKNOWN value. Registers corresponding to unimplemented counters are RES0. See table in TRM" rgroup.long (0x600+0x4)++0x03 line.long 0x00 "GICP_SVR1,Shadow Value Registers" hexmask.long.long 0x00 0.--31. 1. " COUNT,Captured counter value.This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn." group.long (0xA00+0x4)++0x03 line.long 0x00 "GICP_FR1,Filter Registers" bitfld.long 0x00 30.--31. " FILTERTYPE ,Filter Type." "Core,INTID,Chip/ITS,Reserved" bitfld.long 0x00 29. " FILTERENCODING ,Filter Encoding." "Range,Exact" hexmask.long.byte 0x00 0.--15. 1. " Filter ,If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this register is ignored." NEWLINE group.long (0x000+0x8)++0x03 line.long 0x00 "GICP_EVCNTR2,Event Counter Register" hexmask.long.long 0x00 0.--31. 1. " COUNT ,Counter value. If the counter is enabled, the counter value increments when an event matching GICP_EVTYPERn.EVENT occurs." group.long (0x400+0x8)++0x03 line.long 0x00 "GICP_EVTYPER2,Event Type Configuration Register" bitfld.long 0x00 31. " OVFCAP ,When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set." "0,1" bitfld.long 0x00 16.--17. " EVENTTYPE ,Event tracking type." "Count,Accumulate,Maximum,Reserved" hexmask.long.byte 0x00 0.--7. 1. " EVENT ,Event identifier. All events reset to an UNKNOWN value. Registers corresponding to unimplemented counters are RES0. See table in TRM" rgroup.long (0x600+0x8)++0x03 line.long 0x00 "GICP_SVR2,Shadow Value Registers" hexmask.long.long 0x00 0.--31. 1. " COUNT,Captured counter value.This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn." group.long (0xA00+0x8)++0x03 line.long 0x00 "GICP_FR2,Filter Registers" bitfld.long 0x00 30.--31. " FILTERTYPE ,Filter Type." "Core,INTID,Chip/ITS,Reserved" bitfld.long 0x00 29. " FILTERENCODING ,Filter Encoding." "Range,Exact" hexmask.long.byte 0x00 0.--15. 1. " Filter ,If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this register is ignored." NEWLINE group.long (0x000+0xC)++0x03 line.long 0x00 "GICP_EVCNTR3,Event Counter Register" hexmask.long.long 0x00 0.--31. 1. " COUNT ,Counter value. If the counter is enabled, the counter value increments when an event matching GICP_EVTYPERn.EVENT occurs." group.long (0x400+0xC)++0x03 line.long 0x00 "GICP_EVTYPER3,Event Type Configuration Register" bitfld.long 0x00 31. " OVFCAP ,When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set." "0,1" bitfld.long 0x00 16.--17. " EVENTTYPE ,Event tracking type." "Count,Accumulate,Maximum,Reserved" hexmask.long.byte 0x00 0.--7. 1. " EVENT ,Event identifier. All events reset to an UNKNOWN value. Registers corresponding to unimplemented counters are RES0. See table in TRM" rgroup.long (0x600+0xC)++0x03 line.long 0x00 "GICP_SVR3,Shadow Value Registers" hexmask.long.long 0x00 0.--31. 1. " COUNT,Captured counter value.This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn." group.long (0xA00+0xC)++0x03 line.long 0x00 "GICP_FR3,Filter Registers" bitfld.long 0x00 30.--31. " FILTERTYPE ,Filter Type." "Core,INTID,Chip/ITS,Reserved" bitfld.long 0x00 29. " FILTERENCODING ,Filter Encoding." "Range,Exact" hexmask.long.byte 0x00 0.--15. 1. " Filter ,If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this register is ignored." NEWLINE group.long (0x000+0x10)++0x03 line.long 0x00 "GICP_EVCNTR4,Event Counter Register" hexmask.long.long 0x00 0.--31. 1. " COUNT ,Counter value. If the counter is enabled, the counter value increments when an event matching GICP_EVTYPERn.EVENT occurs." group.long (0x400+0x10)++0x03 line.long 0x00 "GICP_EVTYPER4,Event Type Configuration Register" bitfld.long 0x00 31. " OVFCAP ,When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set." "0,1" bitfld.long 0x00 16.--17. " EVENTTYPE ,Event tracking type." "Count,Accumulate,Maximum,Reserved" hexmask.long.byte 0x00 0.--7. 1. " EVENT ,Event identifier. All events reset to an UNKNOWN value. Registers corresponding to unimplemented counters are RES0. See table in TRM" rgroup.long (0x600+0x10)++0x03 line.long 0x00 "GICP_SVR4,Shadow Value Registers" hexmask.long.long 0x00 0.--31. 1. " COUNT,Captured counter value.This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn." group.long (0xA00+0x10)++0x03 line.long 0x00 "GICP_FR4,Filter Registers" bitfld.long 0x00 30.--31. " FILTERTYPE ,Filter Type." "Core,INTID,Chip/ITS,Reserved" bitfld.long 0x00 29. " FILTERENCODING ,Filter Encoding." "Range,Exact" hexmask.long.byte 0x00 0.--15. 1. " Filter ,If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this register is ignored." NEWLINE group.quad 0xC00++0x07 line.quad 0x00 "GICP_CNTENSET0,Counter Enable Set Register 0" bitfld.quad 0x00 4. " CNTEN4 ,Counter disable. Writing 1 to a bit location sets the enable for the associated counter. Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register. Reads return the state of the counter enables." "0,1" bitfld.quad 0x00 3. " CNTEN3 ,Counter disable. Writing 1 to a bit location sets the enable for the associated counter. Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register. Reads return the state of the counter enables." "0,1" bitfld.quad 0x00 2. " CNTEN2 ,Counter disable. Writing 1 to a bit location sets the enable for the associated counter. Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register. Reads return the state of the counter enables." "0,1" NEWLINE bitfld.quad 0x00 1. " CNTEN1 ,Counter disable. Writing 1 to a bit location sets the enable for the associated counter. Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register. Reads return the state of the counter enables." "0,1" bitfld.quad 0x00 0. " CNTEN0 ,Counter disable. Writing 1 to a bit location sets the enable for the associated counter. Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register. Reads return the state of the counter enables." "0,1" group.quad 0xC20++0x07 line.quad 0x00 "GICP_INTENCLR0,Counter Enable Clear Register 0" bitfld.quad 0x00 4. " CNTEN4 ,Counter disable. Writing 1 to a bit location clears the enable for the associated counter. Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register. Reads return the state of the counter enables." "0,1" bitfld.quad 0x00 3. " CNTEN3 ,Counter disable. Writing 1 to a bit location clears the enable for the associated counter. Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register. Reads return the state of the counter enables." "0,1" bitfld.quad 0x00 2. " CNTEN2 ,Counter disable. Writing 1 to a bit location clears the enable for the associated counter. Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register. Reads return the state of the counter enables." "0,1" NEWLINE bitfld.quad 0x00 1. " CNTEN1 ,Counter disable. Writing 1 to a bit location clears the enable for the associated counter. Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register. Reads return the state of the counter enables." "0,1" bitfld.quad 0x00 0. " CNTEN0 ,Counter disable. Writing 1 to a bit location clears the enable for the associated counter. Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register. Reads return the state of the counter enables." "0,1" group.quad 0xC40++0x07 line.quad 0x00 "GICP_INTENSET0,Interrupt Contribution Enable Set Register 0" bitfld.quad 0x00 4. " INTEN4 ,Interrupt enable. Writing 1 sets the interrupt enable for the associated counter. Writing 0 has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register. Reads return the state of the interrupt enables." "0,1" bitfld.quad 0x00 3. " INTEN3 ,Interrupt enable. Writing 1 sets the interrupt enable for the associated counter. Writing 0 has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register. Reads return the state of the interrupt enables." "0,1" bitfld.quad 0x00 2. " INTEN2 ,Interrupt enable. Writing 1 sets the interrupt enable for the associated counter. Writing 0 has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register. Reads return the state of the interrupt enables." "0,1" NEWLINE bitfld.quad 0x00 1. " INTEN1 ,Interrupt enable. Writing 1 sets the interrupt enable for the associated counter. Writing 0 has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register. Reads return the state of the interrupt enables." "0,1" bitfld.quad 0x00 0. " INTEN0 ,Interrupt enable. Writing 1 sets the interrupt enable for the associated counter. Writing 0 has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register. Reads return the state of the interrupt enables." "0,1" group.quad 0xC60++0x07 line.quad 0x00 "GICP_INTENCLR0,Interrupt Contribution Enable Clear Register 0" bitfld.quad 0x00 4. " INTEN4 ,Interrupt enable. Writing 1 clears the interrupt enable for the associated counter. Writing 0 has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register. Reads return the state of the interrupt enables." "0,1" bitfld.quad 0x00 3. " INTEN3 ,Interrupt enable. Writing 1 clears the interrupt enable for the associated counter. Writing 0 has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register. Reads return the state of the interrupt enables." "0,1" bitfld.quad 0x00 2. " INTEN2 ,Interrupt enable. Writing 1 clears the interrupt enable for the associated counter. Writing 0 has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register. Reads return the state of the interrupt enables." "0,1" NEWLINE bitfld.quad 0x00 1. " INTEN1 ,Interrupt enable. Writing 1 clears the interrupt enable for the associated counter. Writing 0 has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register. Reads return the state of the interrupt enables." "0,1" bitfld.quad 0x00 0. " INTEN0 ,Interrupt enable. Writing 1 clears the interrupt enable for the associated counter. Writing 0 has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register. Reads return the state of the interrupt enables." "0,1" group.quad 0xC80++0x07 line.quad 0x00 "GICP_OVSCLR0,Overflow Status Clear Register 0" bitfld.quad 0x00 4. " OVS4 ,Overflow status. Writing 1 clears the overflow status for the associated counter. Writing 0 has no effect. To set the counter overflow status, use the GICP_OVSSET0 register. Reads return the state of the overflow status bits." "0,1" bitfld.quad 0x00 3. " OVS3 ,Overflow status. Writing 1 clears the overflow status for the associated counter. Writing 0 has no effect. To set the counter overflow status, use the GICP_OVSSET0 register. Reads return the state of the overflow status bits." "0,1" bitfld.quad 0x00 2. " OVS2 ,Overflow status. Writing 1 clears the overflow status for the associated counter. Writing 0 has no effect. To set the counter overflow status, use the GICP_OVSSET0 register. Reads return the state of the overflow status bits." "0,1" NEWLINE bitfld.quad 0x00 1. " OVS1 ,Overflow status. Writing 1 clears the overflow status for the associated counter. Writing 0 has no effect. To set the counter overflow status, use the GICP_OVSSET0 register. Reads return the state of the overflow status bits." "0,1" bitfld.quad 0x00 0. " OVS0 ,Overflow status. Writing 1 clears the overflow status for the associated counter. Writing 0 has no effect. To set the counter overflow status, use the GICP_OVSSET0 register. Reads return the state of the overflow status bits." "0,1" group.quad 0xCC0++0x07 line.quad 0x00 "GICP_OVSSET0,Overflow Status Set Register 0" bitfld.quad 0x00 4. " OVS4 ,Writing 1 sets the overflow status for the associated counter. Writing 0 has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register. Reads return the state of the overflow status bits." "0,1" bitfld.quad 0x00 3. " OVS3 ,Writing 1 sets the overflow status for the associated counter. Writing 0 has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register. Reads return the state of the overflow status bits." "0,1" bitfld.quad 0x00 2. " OVS2 ,Writing 1 sets the overflow status for the associated counter. Writing 0 has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register. Reads return the state of the overflow status bits." "0,1" NEWLINE bitfld.quad 0x00 1. " OVS1 ,Writing 1 sets the overflow status for the associated counter. Writing 0 has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register. Reads return the state of the overflow status bits." "0,1" bitfld.quad 0x00 0. " OVS0 ,Writing 1 sets the overflow status for the associated counter. Writing 0 has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register. Reads return the state of the overflow status bits." "0,1" wgroup.long 0xD88++0x03 line.long 0x00 "GICP_CAPR,Counter Shadow Value Capture Register" bitfld.long 0x00 0. " CAPTURE ,When GICP_CFGR.CAPTURE == 1, a write of 1 to this bit triggers a capture of all values within the PMU into their respective shadow registers. When GICP_CFGR.CAPTURE == 0, this bit is zero." "-,1" rgroup.long 0xE00++0x03 line.long 0x00 "GICP_CFGR,Configuration Information Register" bitfld.long 0x00 22. " CAPTURE ,Indicates if the GIC supports capture." "Not Supported,Supported" hexmask.long.byte 0x00 8.--13. 1. " SIZE ,Indicates the counter width+1." hexmask.long.byte 0x00 0.--5. 1. " NCTR ,Indicates the amount of available counters+1." group.long 0xE04++0x03 line.long 0x00 "GICP_CR,Control Register" bitfld.long 0x00 0. " E ,Global counter enable. This bit takes precedence over the GICP_CNTENSET0.CNTEN bits." "Disabled,Enabled" rgroup.long 0xFCC++0x03 line.long 0x00 "GICP_PMDEVTYPE,-" NEWLINE tree "Peripheral/Component ID Registers" rgroup.long 0xFE0++0x03 line.long 0x00 "GICP_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFE4++0x03 line.long 0x00 "GICP_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFE8++0x03 line.long 0x00 "GICP_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-600 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFEC++0x03 line.long 0x00 "GICP_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFD0++0x03 line.long 0x00 "GICP_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFD4++0x03 hide.long 0x00 "GICP_PIDR5,Peripheral ID5 Register" hgroup.long 0xFD8++0x03 hide.long 0x00 "GICP_PIDR6,Peripheral ID6 Register" hgroup.long 0xFDC++0x03 hide.long 0x00 "GICP_PIDR7,Peripheral ID7 Register" rgroup.long 0xFF0++0x03 line.long 0x00 "GICP_CIDR0,Component ID0 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFF4++0x03 line.long 0x00 "GICP_CIDR1,Component ID1 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFF8++0x03 line.long 0x00 "GICP_CIDR2,Component ID2 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFC++0x03 line.long 0x00 "GICP_CIDR3,Component ID3 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end AUTOINDENT.OFF base (COMP.BASE("GICD",-1.)+0x40000) AUTOINDENT.ON CENTER TREE tree "Interrupt Translation Service" group.long 0x00++0x03 line.long 0x00 "GITS_CTLR,ITS Control Register" rbitfld.long 0x00 31. " QUIESCENT ,Indicates completion of all ITS operations" "Not quiescent,Quiescent" bitfld.long 0x00 0. " ENABLED ,Controls whether the ITS is enabled" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?,GIC-600,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" NEWLINE bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" if (((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "0,1" NEWLINE bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits set by " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" NEWLINE bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "Not suppported,Supported" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" NEWLINE bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" NEWLINE rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" elif (((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0008))&0x1000000000)==0x1000000000) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "0,1" NEWLINE bitfld.quad 0x00 32.--35. " CIDBITS ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" NEWLINE bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "Not suppported,Supported" bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" NEWLINE bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" NEWLINE rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0008))&0xFF000000)!=0x00) rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "0,1" NEWLINE hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "Not suppported,Supported" NEWLINE bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" NEWLINE bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" NEWLINE bitfld.quad 0x00 2. " CCT ,Cumulative Collection Tables" "0,1" else rgroup.quad 0x08++0x07 line.quad 0x00 "GITS_TYPER,ITS Type Register" bitfld.quad 0x00 37. " VMOVP ,Indicates the form of the VMOVP command" "All ITSs,One ITS" bitfld.quad 0x00 36. " CIL ,Collection ID Limit" "0,1" NEWLINE hexmask.quad.byte 0x00 24.--31. 1. " HCC ,Hardware Collection Count" bitfld.quad 0x00 19. " PTA ,Indicates the format of the target address" "Not suppported,Supported" NEWLINE bitfld.quad 0x00 18. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported" bitfld.quad 0x00 13.--17. " DEVBITS ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" NEWLINE bitfld.quad 0x00 8.--12. " ID_BITS ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.quad 0x00 4.--7. " ITT_ENTRY_SIZE ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x20++0x03 line.long 0x00 "GITS_FCTLR,Function Control Register" bitfld.long 0x00 31. " DCC ,Disable Cache Conversion (DCC)." "Disabled,Enabled" bitfld.long 0x00 30. " PWE ,Powerdown While Enabled. Request GITS_CTLR.Quiescent to indicate ITS is quiescent." "Disabled,Enabled" NEWLINE bitfld.long 0x00 18. " IEC ,Invalidate Event Cache." "Disabled,Enabled" bitfld.long 0x00 17. " IDC ,Invalidate Device Cache." "Disabled,Enabled" NEWLINE bitfld.long 0x00 16. " ICC ,Invalidate Collection Cache." "Disabled,Enabled" bitfld.long 0x00 9. " QD ,Q Deny. Indicates if Q-Channel requests are denied." "Not denied,Denied" NEWLINE bitfld.long 0x00 8. " AEE ,Access Error Enable. Indicates if reporting of slave access errors is enabled." "Disabled,Enabled" hexmask.long.byte 0x00 4.--7. 1. " CGO ,One bit per clock gate. Indicates if full clock gating is active." NEWLINE bitfld.long 0x00 3. " CEE ,Command error enable." "Disabled,Enabled" bitfld.long 0x00 2. " UEE ,Unmapped error enable. Indicates if unmapped interrupt errors are enabled" "Disabled,Enabled" NEWLINE bitfld.long 0x00 1. " LTE ,Latency tracking enable. Indicates if latency tracking of interrupts is enabled" "Disabled,Enabled" bitfld.long 0x00 0. " SIP ,Scrub in progress. This bit is read and written by software. When a scrub is complete, the GIC clears the bit to 0." "Completed,In Progress" group.quad 0x28++0x07 line.quad 0x00 "GITS_OPR,Operations Register" bitfld.quad 0x00 60.--63. " LOCKTYPE ,Lock-Type. Supported lock types" "Track,Trial,ITS lock,ITS unlock,Track abort,?,LPI lock, LPI unlock, ITS unlock all,?,?,?,?,?,?,?" hexmask.quad.long 0x00 32.--59. 1. " DEVICEID ,Device-ID. 0-maximum DeviceID supported." NEWLINE hexmask.quad.word 0x00 0.--15. 1. " EVENTID ,Event-ID. 8192-maximum EventID supported." rgroup.quad 0x30++0x07 line.quad 0x00 "GITS_OPSR,Operation Status Register" bitfld.quad 0x00 63. " REQUESTCOMPLETE ,Request to GITS_OPR completed." "In Progress,Completed" bitfld.quad 0x00 62. " REQUESTPASS ,Request to GITS_OPR completed without error." "Not passed,Passed" NEWLINE bitfld.quad 0x00 61. " REQUESTINPROGRESS ,Translation in progress." "Completed,In Progress" bitfld.quad 0x00 48. " ENTRYLOCKED ,Locked entry in cache corresponds to request." "Unlocked,Locked" NEWLINE hexmask.quad.word 0x00 32.--44. 1. " TARGET ,Target of interrupt requested." hexmask.quad.word 0x00 0.--15. 1. " PID ,Physical ID of interrupt requested." group.quad 0x80++0x07 line.quad 0x00 "GITS_CBASER,The command queue control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated" bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" NEWLINE bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the base physical address of the command queue" NEWLINE bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of 4KB pages of physical memory allocated to the command queue minus one" group.quad 0x88++0x7 line.quad 0x00 "GITS_CWRITER,The command queue write pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " RETRY ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted" group.quad 0x90++0x07 line.quad 0x00 "GITS_CREADR,The command queue read pointer" hexmask.quad.word 0x00 5.--19. 0x20 " OFFSET ,Bits [19:5] of the offset from GITS_CBASER" bitfld.quad 0x00 0. " STALLED ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled" if (((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0100))&0x700000000000000)==0x00) group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" NEWLINE bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." NEWLINE bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" NEWLINE hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." NEWLINE bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." else group.quad 0x100++0x07 line.quad 0x00 "GITS_BASER0,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" NEWLINE bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." NEWLINE bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" NEWLINE hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." NEWLINE bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of pages of physical memory allocated to the table minus one" endif if (((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0108))&0x700000000000000)==0x00) group.quad 0x108++0x07 line.quad 0x00 "GITS_BASER1,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" NEWLINE bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." NEWLINE bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" NEWLINE hexmask.quad 0x00 12.--47. 1. " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." NEWLINE bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." else group.quad 0x108++0x07 line.quad 0x00 "GITS_BASER1,ITS table control register" bitfld.quad 0x00 63. " VALID ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated" bitfld.quad 0x00 62. " INDIRECT ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level" NEWLINE bitfld.quad 0x00 59.--61. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" rbitfld.quad 0x00 56.--58. " TYPE ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..." NEWLINE bitfld.quad 0x00 53.--55. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" rbitfld.quad 0x00 48.--52. " ENTRY_SIZE ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" NEWLINE hexmask.quad 0x00 12.--47. 0x10 " PHYSICAL_ADDRESS ,Physical Address" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..." NEWLINE bitfld.quad 0x00 8.--9. " PAGE_SIZE ,The size of page that the translation table uses" "4KB,16KB,64KB,?..." hexmask.quad.byte 0x00 0.--7. 1. " SIZE ,The number of pages of physical memory allocated to the table minus one" endif NEWLINE rgroup.long 0xFFE0++0x03 line.long 0x00 "GITS_CFGID,Configuration ID Register" hexmask.long.byte 0x00 0.--3. 1. " ITSNUMBER ,Returns the ITS block ID. The its_id[7:0] tie-off signal controls the ID value. Each ITS block must have a unique ID." rgroup.long 0xFFE0++0x03 line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-600 complies." "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used." "Low,High" NEWLINE bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]. Bits[3:0] of the JEP106 identity code are assigned to GITS_PIDR1." "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GITS_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GITS_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GITS_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GITS_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" NEWLINE base (COMP.BASE("GICD",-1.)+0x40000)+0x10000 if (((per.l((COMP.BASE("GICD",-1.)+0x40000)))&0x01)==0x01) wgroup.long 0x40++0x03 line.long 0x00 "GITS_TRANSLATER,ITS Translation Register" else hgroup.long 0x40++0x03 hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register" endif tree.end AUTOINDENT.OFF base COMP.BASE("GICR",-1.) AUTOINDENT.ON CENTER TREE tree "Redistributor Interface" tree "Control Registers" if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" NEWLINE bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" NEWLINE bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 26. " DPG1S ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes" NEWLINE bitfld.long 0x00 25. " DPG1NS ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes" bitfld.long 0x00 24. " DPG0 ,Disable Processor selection for Group 0 interrupts" "No,Yes" NEWLINE bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01) group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" NEWLINE bitfld.long 0x00 0. " ENABLE_LPIS ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICR_CTLR,Redistributor Control Register" rbitfld.long 0x00 31. " UWP ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending" bitfld.long 0x00 3. " RWP ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending" endif rgroup.long 0x0004++0x03 line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "GIC-500,?,GIC-600,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" NEWLINE bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" rgroup.quad 0x0008++0x07 line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register" hexmask.quad.byte 0x00 56.--63. 1. " AFF3 ,Affinity level 3 value for the Redistributor" hexmask.quad.byte 0x00 48.--55. 1. " AFF2 ,Affinity level 2 value for the Redistributor" NEWLINE hexmask.quad.byte 0x00 40.--47. 1. " AFF1 ,Affinity level 1 value for the Redistributor" hexmask.quad.byte 0x00 32.--39. 1. " AFF0 ,Affinity level 0 value for the Redistributor" NEWLINE bitfld.quad 0x00 24.--25. " COMMONLPIAFF ,The affinity level at which Redistributors share a LPI Configuration table" "Single Core CFG,Chip by AF3, Chip by AF2, Reserved" hexmask.quad.word 0x00 8.--23. 1. " PROCESSOR_NUMBER ,A unique identifier for the PE" NEWLINE bitfld.quad 0x00 5. " DPGS ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported" bitfld.quad 0x00 4. " LAST ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest" NEWLINE bitfld.quad 0x00 3. " DIRECTLPI ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported" bitfld.quad 0x00 0. " PLPIS ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported" if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014)))) group.long 0x0014++0x03 line.long 0x00 "GICR_WAKER,Power Management Control Register" bitfld.long 0x00 31. " QUIESCENT ,This bit shows that the GIC-600 is idle and can be powered down if required" "Not quiescent,Quiescent" bitfld.long 0x00 2. " CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent" NEWLINE bitfld.long 0x00 1. " PROCESSORASLEEP ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes" bitfld.long 0x00 0. " SLEEP ,Indicates if GIC-600 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes" NEWLINE else hgroup.long 0x0014++0x03 hide.long 0x00 "GICR_WAKER,Power Management Control Register" endif group.long 0x0020++0x03 line.long 0x00 "GICR_FCTLR,Function Control Register" bitfld.long 0x00 31. " QD ,Q Deny. Indicates if Q-Channel requests are denied." "Not denied,Denied" hexmask.long.byte 0x00 4.--6. 1. " CGO ,One bit per clock gate. Indicates if full clock gating is active." NEWLINE bitfld.long 0x00 0. " SIP ,Scrub in progress. This bit is read and written by software. When a scrub is complete, the GIC clears the bit to 0." "Completed,In Progress" group.long 0x0024++0x03 line.long 0x00 "GICR_PWRR,Power Register" hexmask.long.byte 0x00 16.--23. 1. " RDG ,RDGroup. This read-only field indicates the number of the current Redistributor. Must be packed from 0." hexmask.long.byte 0x00 8.--15. 1. " RDGO ,RDGroupOffset.This read-only field indicates the offset of the current core that is connected to the current Redistributor. Must be packed from 0 but does not necessarily map to a single cluster because the AXI4-Stream bus can be subdivided." NEWLINE rbitfld.long 0x00 3. " RDGPO ,RDGroupPoweredOff. This read-only bit indicates if group is powered and accessable or if it can be powered down" "Powered,Not powered" rbitfld.long 0x00 2. " RDGPD ,RDGroupPowerDown. This read-only bit indicates the intentional power state of the Redistributor. The Redistributor has reached its intentional power state when RDGPD = RDGPO." "Powered,Not powered" NEWLINE eventfld.long 0x00 1. " RDAG ,RDApplyGroup. This write-only bit applies the RDPD value to all Redistributors in the group. If the RDPD value cannot be applied to all cores in the group, then the GIC ignores this request." "-,Apply" bitfld.long 0x00 0. " RDPD ,RDPowerDown. Writes to 1 ignored if GICR_WAKER.ProcessorSleep != 1. Writes ignored if RDGPD != RDGPO and changing to not match RDGPD. If all other cores have RDPD == 1, then setting this bit to 1 also sets RDGPD = 1." "Powered,Not powered" group.long 0x0028++0x03 line.long 0x00 "GICR_CLASS,Class Register" bitfld.long 0x00 0. " CLASS ,Interrupt class." "0,1" group.quad 0x070++0x07 line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" hexmask.quad 0x00 12.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table" NEWLINE bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..." bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" NEWLINE bitfld.quad 0x00 0.--4. " IDBITS ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address" group.quad 0x78++0x07 line.long 0x00 "GICR_PENDBASER,LPI pending table base register" bitfld.quad 0x00 62. " PTZ ,Pending Table Zero" "Not zero,Zero" bitfld.quad 0x00 56.--58. " OUTERCACHE ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable" NEWLINE hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table" bitfld.quad 0x00 10.--11. " SHAREABILITY ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..." NEWLINE bitfld.quad 0x00 7.--9. " INNERCACHE ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable" NEWLINE tree.end tree "SGI and PPI Registers" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080)) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1" bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1" bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1" bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1" bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Secure,Non-secure Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Secure,Non-secure Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Secure,Non-secure Group 1" bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Secure,Non-secure Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Secure,Non-secure Group 1" NEWLINE bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Secure,Non-secure Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Secure,Non-secure Group 1" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000) group.long 0x10080++0x03 line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" NEWLINE bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" NEWLINE bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" NEWLINE bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" NEWLINE bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" NEWLINE bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" NEWLINE bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" NEWLINE bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" NEWLINE bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" NEWLINE bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" NEWLINE bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" NEWLINE bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" NEWLINE bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" NEWLINE bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" NEWLINE bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" NEWLINE bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" else hgroup.long 0x10080++0x03 hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0" NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE endif NEWLINE width 24. group.long 0x10100++0x03 line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" NEWLINE setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" group.long 0x10200++0x03 line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" NEWLINE setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" NEWLINE setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" NEWLINE setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" NEWLINE setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" NEWLINE setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" NEWLINE setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" NEWLINE setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" NEWLINE setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" NEWLINE setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" NEWLINE setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" NEWLINE setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" NEWLINE setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" NEWLINE setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" NEWLINE setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" NEWLINE setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" group.long 0x10300++0x03 line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" NEWLINE setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" NEWLINE setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" NEWLINE setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" NEWLINE setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" NEWLINE setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" NEWLINE setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" NEWLINE setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" NEWLINE setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" NEWLINE setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" NEWLINE setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" NEWLINE setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" NEWLINE setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" NEWLINE setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" NEWLINE setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" NEWLINE setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" NEWLINE width 18. group.long 0x10400++0x03 line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " NEWLINE hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x10404++0x03 line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " NEWLINE hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x10408++0x03 line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " NEWLINE hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x1040C++0x03 line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " NEWLINE hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x10410++0x03 line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " NEWLINE hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x10414++0x03 line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " NEWLINE hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x10418++0x03 line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " NEWLINE hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x1041C++0x03 line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " NEWLINE hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " NEWLINE rgroup.long 0x10C00++0x03 line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge" NEWLINE bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge" bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge" NEWLINE bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge" NEWLINE bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (SGI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (SGI)" "Level,Edge" NEWLINE bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (SGI)" "Level,Edge" bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (SGI)" "Level,Edge" NEWLINE bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (SGI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (SGI)" "Level,Edge" NEWLINE bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (SGI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (SGI)" "Level,Edge" group.long 0x10C04++0x03 line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge" NEWLINE bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge" bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge" NEWLINE bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge" NEWLINE bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9 (PPI)" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8 (PPI)" "Level,Edge" NEWLINE bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7 (PPI)" "Level,Edge" bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6 (PPI)" "Level,Edge" NEWLINE bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5 (PPI)" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4 (PPI)" "Level,Edge" NEWLINE bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3 (PPI)" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2 (PPI)" "Level,Edge" NEWLINE bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1 (PPI)" "Level,Edge" NEWLINE width 18. if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00)) group.long 0x10D00++0x03 line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1" bitfld.long 0x00 30. " GMB30 ,Group Modifier Bit 30" "0,1" NEWLINE bitfld.long 0x00 29. " GMB29 ,Group Modifier Bit 29" "0,1" bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1" NEWLINE bitfld.long 0x00 27. " GMB27 ,Group Modifier Bit 27" "0,1" bitfld.long 0x00 26. " GMB26 ,Group Modifier Bit 26" "0,1" NEWLINE bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1" bitfld.long 0x00 24. " GMB24 ,Group Modifier Bit 24" "0,1" NEWLINE bitfld.long 0x00 23. " GMB23 ,Group Modifier Bit 23" "0,1" bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1" NEWLINE bitfld.long 0x00 21. " GMB21 ,Group Modifier Bit 21" "0,1" bitfld.long 0x00 20. " GMB20 ,Group Modifier Bit 20" "0,1" NEWLINE bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1" bitfld.long 0x00 18. " GMB18 ,Group Modifier Bit 18" "0,1" NEWLINE bitfld.long 0x00 17. " GMB17 ,Group Modifier Bit 17" "0,1" bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1" NEWLINE bitfld.long 0x00 15. " GMB15 ,Group Modifier Bit 15" "0,1" bitfld.long 0x00 14. " GMB14 ,Group Modifier Bit 14" "0,1" NEWLINE bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1" bitfld.long 0x00 12. " GMB12 ,Group Modifier Bit 12" "0,1" NEWLINE bitfld.long 0x00 11. " GMB11 ,Group Modifier Bit 11" "0,1" bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1" NEWLINE bitfld.long 0x00 9. " GMB9 ,Group Modifier Bit 9" "0,1" bitfld.long 0x00 8. " GMB8 ,Group Modifier Bit 8" "0,1" NEWLINE bitfld.long 0x00 7. " GMB7 ,Group Modifier Bit 7" "0,1" bitfld.long 0x00 6. " GMB6 ,Group Modifier Bit 6" "0,1" NEWLINE bitfld.long 0x00 5. " GMB5 ,Group Modifier Bit 5" "0,1" bitfld.long 0x00 4. " GMB4 ,Group Modifier Bit 4" "0,1" NEWLINE bitfld.long 0x00 3. " GMB3 ,Group Modifier Bit 3" "0,1" bitfld.long 0x00 2. " GMB2 ,Group Modifier Bit 2" "0,1" NEWLINE bitfld.long 0x00 1. " GMB1 ,Group Modifier Bit 1" "0,1" bitfld.long 0x00 0. " GMB0 ,Group Modifier Bit 0" "0,1" NEWLINE else hgroup.long 0x10D00++0x03 hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0" NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE endif if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00)) group.long 0x10E00++0x03 line.long 0x00 "GICR_NSACR,Non-secure Access Control Register" bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 28.--29. " NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..." NEWLINE bitfld.long 0x00 26.--27. " NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..." NEWLINE bitfld.long 0x00 22.--23. " NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 20.--21. " NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..." NEWLINE bitfld.long 0x00 18.--19. " NS_ACCESS9 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 16.--17. " NS_ACCESS8 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..." NEWLINE bitfld.long 0x00 14.--15. " NS_ACCESS7 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 12.--13. " NS_ACCESS6 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..." NEWLINE bitfld.long 0x00 10.--11. " NS_ACCESS5 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 8.--9. " NS_ACCESS4 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..." NEWLINE bitfld.long 0x00 6.--7. " NS_ACCESS3 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 4.--5. " NS_ACCESS2 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..." NEWLINE bitfld.long 0x00 2.--3. " NS_ACCESS1 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..." bitfld.long 0x00 0.--1. " NS_ACCESS0 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..." NEWLINE else hgroup.long 0x10E00++0x03 hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register" NEWLINE NEWLINE NEWLINE NEWLINE NEWLINE endif rgroup.long 0x1C000++0x03 line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register" bitfld.long 0x00 31. " CPU_AS ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High" bitfld.long 0x00 30. " WAKEREQUEST ,This bit indicates if a wake request is active" "Not active,Active" NEWLINE bitfld.long 0x00 3. " ENABLEGRP1_S ,EnableGrp1 Secure" "0,1" bitfld.long 0x00 2. " ENABLEGRP1_S ,EnableGrp1 Secure" "0,1" NEWLINE bitfld.long 0x00 1. " ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1" bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1" NEWLINE rgroup.long 0x1C008++0x03 line.long 0x00 "GICR_IERRV,Interrupt Error Valid Register" bitfld.long 0x00 31. " VALID31 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 30. " VALID30 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 29. " VALID29 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 28. " VALID28 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 27. " VALID27 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 26. " VALID26 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 25. " VALID25 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 24. " VALID24 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 23. " VALID23 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 22. " VALID22 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 21. " VALID21 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 20. " VALID20 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 19. " VALID19 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 18. " VALID18 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 17. " VALID17 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 16. " VALID16 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 15. " VALID15 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 14. " VALID14 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 13. " VALID13 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 12. " VALID12 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 11. " VALID11 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 10. " VALID10 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 9. " VALID9 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 8. " VALID8 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 7. " VALID7 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 6. " VALID6 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 5. " VALID5 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 4. " VALID4 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 3. " VALID3 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 2. " VALID2 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE bitfld.long 0x00 1. " VALID1 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" bitfld.long 0x00 0. " VALID0 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1" NEWLINE NEWLINE if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x1C010)))) //(GICD_TYPER.SECURITYEXTN == 1 [Implemented] && Accessed address is secure) group.quad 0x1C010++0x07 line.quad 0x00 "GICR_SGIDR,SGI Default Register" bitfld.quad 0x00 62. " GRPMOD16 ,As GRPMOD register." "0,1" bitfld.quad 0x00 61. " GRP16 ,As GRP register." "0,1" bitfld.quad 0x00 60. " NSACR16 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 58. " GRPMOD15 ,As GRPMOD register." "0,1" bitfld.quad 0x00 57. " GRP15 ,As GRP register." "0,1" bitfld.quad 0x00 56. " NSACR15 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 54. " GRPMOD14 ,As GRPMOD register." "0,1" bitfld.quad 0x00 53. " GRP14 ,As GRP register." "0,1" bitfld.quad 0x00 52. " NSACR14 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 50. " GRPMOD13 ,As GRPMOD register." "0,1" bitfld.quad 0x00 49. " GRP13 ,As GRP register." "0,1" bitfld.quad 0x00 48. " NSACR13 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 46. " GRPMOD12 ,As GRPMOD register." "0,1" bitfld.quad 0x00 45. " GRP12 ,As GRP register." "0,1" bitfld.quad 0x00 44. " NSACR12 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 42. " GRPMOD11 ,As GRPMOD register." "0,1" bitfld.quad 0x00 41. " GRP11 ,As GRP register." "0,1" bitfld.quad 0x00 40. " NSACR11 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 38. " GRPMOD10 ,As GRPMOD register." "0,1" bitfld.quad 0x00 37. " GRP10 ,As GRP register." "0,1" bitfld.quad 0x00 36. " NSACR10 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 34. " GRPMOD9 ,As GRPMOD register." "0,1" bitfld.quad 0x00 33. " GRP9 ,As GRP register." "0,1" bitfld.quad 0x00 32. " NSACR9 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 30. " GRPMOD8 ,As GRPMOD register." "0,1" bitfld.quad 0x00 29. " GRP8 ,As GRP register." "0,1" bitfld.quad 0x00 28. " NSACR8 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 26. " GRPMOD7 ,As GRPMOD register." "0,1" bitfld.quad 0x00 25. " GRP7 ,As GRP register." "0,1" bitfld.quad 0x00 24. " NSACR7 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 22. " GRPMOD6 ,As GRPMOD register." "0,1" bitfld.quad 0x00 21. " GRP6 ,As GRP register." "0,1" bitfld.quad 0x00 20. " NSACR6 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 18. " GRPMOD5 ,As GRPMOD register." "0,1" bitfld.quad 0x00 17. " GRP5 ,As GRP register." "0,1" bitfld.quad 0x00 16. " NSACR5 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 14. " GRPMOD4 ,As GRPMOD register." "0,1" bitfld.quad 0x00 13. " GRP4 ,As GRP register." "0,1" bitfld.quad 0x00 12. " NSACR4 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 10. " GRPMOD3 ,As GRPMOD register." "0,1" bitfld.quad 0x00 9. " GRP3 ,As GRP register." "0,1" bitfld.quad 0x00 8. " NSACR3 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 6. " GRPMOD2 ,As GRPMOD register." "0,1" bitfld.quad 0x00 5. " GRP2 ,As GRP register." "0,1" bitfld.quad 0x00 4. " NSACR2 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE bitfld.quad 0x00 2. " GRPMOD1 ,As GRPMOD register." "0,1" bitfld.quad 0x00 1. " GRP1 ,As GRP register." "0,1" bitfld.quad 0x00 0. " NSACR1 ,Indicates if Non-secure access to interrupt is allowed." "0,1" NEWLINE else hgroup.quad 0x1C010++0x07 hide.quad 0x00 "GICR_SGIDR,SGI Default Register" endif rgroup.long 0x1C080++0x03 line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 31. " PPI31S ,Actual status of the PPI31 input signal" "Low,High" bitfld.long 0x00 30. " PPI30S ,Actual status of the PPI30 input signal" "Low,High" NEWLINE bitfld.long 0x00 29. " PPI29S ,Actual status of the PPI29 input signal" "Low,High" bitfld.long 0x00 28. " PPI28S ,Actual status of the PPI28 input signal" "Low,High" NEWLINE bitfld.long 0x00 27. " PPI27S ,Actual status of the PPI27 input signal" "Low,High" bitfld.long 0x00 26. " PPI26S ,Actual status of the PPI26 input signal" "Low,High" NEWLINE bitfld.long 0x00 25. " PPI25S ,Actual status of the PPI25 input signal" "Low,High" bitfld.long 0x00 24. " PPI24S ,Actual status of the PPI24 input signal" "Low,High" NEWLINE bitfld.long 0x00 23. " PPI23S ,Actual status of the PPI23 input signal" "Low,High" bitfld.long 0x00 22. " PPI22S ,Actual status of the PPI22 input signal" "Low,High" NEWLINE bitfld.long 0x00 21. " PPI21S ,Actual status of the PPI21 input signal" "Low,High" bitfld.long 0x00 20. " PPI20S ,Actual status of the PPI20 input signal" "Low,High" NEWLINE bitfld.long 0x00 19. " PPI19S ,Actual status of the PPI19 input signal" "Low,High" bitfld.long 0x00 18. " PPI18S ,Actual status of the PPI18 input signal" "Low,High" NEWLINE bitfld.long 0x00 17. " PPI17S ,Actual status of the PPI17 input signal" "Low,High" bitfld.long 0x00 16. " PPI16S ,Actual status of the PPI16 input signal" "Low,High" rgroup.long 0x1F000++0x03 line.long 0x00 "GICR_CFGID0,Configuration ID0 Register" bitfld.long 0x00 28.--31. " AF3WIDTH ,Affinity 3 width." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " AF2WIDTH ,Affinity 2 width." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" NEWLINE bitfld.long 0x00 20.--23. " AF1WIDTH ,Affinity 1 width." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " AF0WIDTH ,Affinity 0 width." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" NEWLINE bitfld.long 0x00 12.--15. " TGT0LISTWIDTH ,The Target0 list width - 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " ECCSUPPORT ,This bit indicates if ECC is supported." "Not supported,Supported" NEWLINE hexmask.long.word 0x00 0.--8. 1. " PPINUMBER ,RedistributorID. The ppi_id[15:0] tie-off signal sets the value of the ID. Each Redistributor must have a unique ID." rgroup.long 0x1F004++0x03 line.long 0x00 "GICR_CFGID1,Configuration ID1 Register" bitfld.long 0x00 28.--31. " VERSION ,Identifies the major and minor revisions and product quality status of the GIC-600." "?,Ver0 (r0p0),?,Ver1 (r0p1),Ver2 (r0p2),?..." hexmask.long.byte 0x00 24.--27. 1. " USERVALUE ,Modification value that you can set." NEWLINE hexmask.long.byte 0x00 16.--19. 1. " PPIPERPROC ,The number of Redistributors that each core supports - 1." bitfld.long 0x00 12. " DIRECTUPSTREAM, Indicates a direct upstream connection." "0,1" NEWLINE hexmask.long.word 0x00 4.--11. 1. " NUMCPUS ,The number of cores that are integrated in this Redistributor." tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.long 0xFFE0++0x03 line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_0 ,Part number[7:0]" rgroup.long 0xFFE4++0x03 line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " DES_1 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PART_1 , Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFE8++0x03 line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-600 complies" "Reserved,Reserved,Reserved,v3.0,?..." bitfld.long 0x00 3. " JEDEC ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High" bitfld.long 0x00 0.--2. " DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7" rgroup.long 0xFFEC++0x03 line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CMOD ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0xFFD0++0x03 line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DES_2 ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFFD4++0x03 hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register" hgroup.long 0xFFD8++0x03 hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register" hgroup.long 0xFFDC++0x03 hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register" rgroup.long 0xFFF0++0x03 line.long 0x00 "GICR_CIDR0,Component ID0 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF4++0x03 line.long 0x00 "GICR_CIDR1,Component ID1 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFF8++0x03 line.long 0x00 "GICR_CIDR2,Component ID2 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0xFFFC++0x03 line.long 0x00 "GICR_CIDR3,Component ID3 Register" hexmask.long 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" tree.end tree.end AUTOINDENT.OFF sif COMP.AVAILABLE("GICC") base COMP.BASE("GICC",-1.) width 14. tree "CPU Interface" if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.))) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 10. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 9. " EOIMODES ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" textline " " bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400) group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODENS ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 6. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 0. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled" textline " " bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 5. " FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled" bitfld.long 0x00 4. " CBPR ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both" textline " " bitfld.long 0x00 3. " FIQEN ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ" bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled" endif textline " " group.long 0x04++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" group.long 0x08++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x0C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x10++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x20++0x03 hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register" in wgroup.long 0x24++0x03 line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" rgroup.long 0x2C++0x03 line.long 0x00 "GICC_STATUSR,CPU Interface Status Register" bitfld.long 0x00 4. " ASV ,Attempted security violation" "Not detected,Detected" bitfld.long 0x00 3. " WROD ,Write to an RO location" "Not detected,Detected" bitfld.long 0x00 2. " RWOD ,Read of a WO location" "Not detected,Detected" textline " " bitfld.long 0x00 1. " WRD ,Write to a reserved location" "Not detected,Detected" bitfld.long 0x00 0. " RRD ,Read of a reserved location" "Not detected,Detected" group.long 0xD0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register 0" group.long 0xD4++0x03 line.long 0x00 "GICC_APR1,Active Priorities Register 1" group.long 0xD8++0x03 line.long 0x00 "GICC_APR2,Active Priorities Register 2" group.long 0xDC++0x03 line.long 0x00 "GICC_APR3,Active Priorities Register 3" group.long 0xE0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0" group.long 0xE4++0x03 line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1" group.long 0xE8++0x03 line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2" group.long 0xEC++0x03 line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3" rgroup.long 0xFC++0x03 line.long 0x00 "GICC_IIDR,CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..." bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" hexmask.long.tbyte 0x00 0.--23. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICH") base COMP.BASE("GICH",-1.) width 13. tree "Virtual CPU Control Interface" group.long 0x00++0x03 line.long 0x00 "GICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " NPIE ,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " LRENPIE ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " UIE ,Underflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,Virtual CPU interface Enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "GICH_VTR,Virtual Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "1,2,3,4,5,6,7,8" bitfld.long 0x00 23.--25. " IDBITS ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..." textline " " bitfld.long 0x00 22. " SEIS ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported" bitfld.long 0x00 21. " A3V ,Affinity 3 valid" "Invalid,Valid" bitfld.long 0x00 0.--4. " LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x08++0x03 line.long 0x00 "GICH_VMCR,Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. " VPMR ,Virtual priority mask" bitfld.long 0x00 21.--23. " VBPR0 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " VBPR1 ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9. " VEOIM ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" textline " " bitfld.long 0x00 4. " VCBPR ,Virtual Common Binary Point Register" "ABPR,BPR" bitfld.long 0x00 3. " VFIQEN ,Virtual FIQ enable" "Disabled,Enabled" bitfld.long 0x00 2. " VACKCTL ,Virtual AckCtl" "INTID=1022,INTID=corresponding" bitfld.long 0x00 1. " VENG1 ,Virtual interrupt enable for group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VENG0 ,Virtual interrupt enable for group 0" "Disabled,Enabled" rgroup.long 0x10++0x03 line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register" bitfld.long 0x00 7. " VGRP1D ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 6. " VGRP1E ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 5. " VGRP0D ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 4. " VGRP0E ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted" textline " " bitfld.long 0x00 3. " NP ,No Pending maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 2. " LRENP ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 1. " U ,Underflow maintenance interrupt assertion" "Not asserted,Asserted" bitfld.long 0x00 0. " EOI ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted" rgroup.long 0x20++0x03 line.long 0x00 "GICH_EISR0,End of Interrupt Status Register" bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt" rgroup.long 0x30++0x03 line.long 0x00 "GICH_ELRSR0,Empty List register Status Register" bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " STATUS9 ,Status bit for List register 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " STATUS8 ,Status bit for List register 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " STATUS7 ,Status bit for List register 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " STATUS6 ,Status bit for List register 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " STATUS5 ,Status bit for List register 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " STATUS4 ,Status bit for List register 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " STATUS3 ,Status bit for List register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " STATUS2 ,Status bit for List register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " STATUS1 ,Status bit for List register 1" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " STATUS0 ,Status bit for List register 0" "No interrupt,Interrupt" textline " " group.long 0xF0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF4++0x03 line.long 0x00 "GICH_APR1,Active Priorities Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xF8++0x03 line.long 0x00 "GICH_APR2,Active Priorities Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xFC++0x03 line.long 0x00 "GICH_APR3,Active Priorities Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " group.long 0x100++0x03 line.long 0x00 "GICH_LR0,List Register 0" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x104++0x03 line.long 0x00 "GICH_LR1,List Register 1" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x108++0x03 line.long 0x00 "GICH_LR2,List Register 2" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x10C++0x03 line.long 0x00 "GICH_LR3,List Register 3" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x110++0x03 line.long 0x00 "GICH_LR4,List Register 4" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x114++0x03 line.long 0x00 "GICH_LR5,List Register 5" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x118++0x03 line.long 0x00 "GICH_LR6,List Register 6" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x11C++0x03 line.long 0x00 "GICH_LR7,List Register 7" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x120++0x03 line.long 0x00 "GICH_LR8,List Register 8" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x124++0x03 line.long 0x00 "GICH_LR9,List Register 9" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x128++0x03 line.long 0x00 "GICH_LR10,List Register 10" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x12C++0x03 line.long 0x00 "GICH_LR11,List Register 11" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x130++0x03 line.long 0x00 "GICH_LR12,List Register 12" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x134++0x03 line.long 0x00 "GICH_LR13,List Register 13" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" group.long 0x138++0x03 line.long 0x00 "GICH_LR14,List Register 14" bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware" bitfld.long 0x00 30. " GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1" bitfld.long 0x00 28.--29. " STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending" bitfld.long 0x00 23.--27. " PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 10.--19. 1. " PINTID ,Physical interrupt ID" hexmask.long.word 0x00 0.--9. 1. " VINTID ,Virtual interrupt ID" tree.end width 0x0b endif sif COMP.AVAILABLE("GICV") base COMP.BASE("GICV",-1.) width 14. tree "Virtual CPU Interface" group.long 0x00++0x03 line.long 0x00 "GICV_CTLR,VM Control Register" bitfld.long 0x00 9. " EOIMODE ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID" bitfld.long 0x00 4. " CBPR ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both" bitfld.long 0x00 3. " FIQEN ,FIQ Enable" "Disabled,Enabled" bitfld.long 0x00 2. " ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding" textline " " bitfld.long 0x00 1. " ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled" group.long 0x04++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for the virtual CPU interface" group.long 0x08++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x0C++0x03 line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x10++0x03 line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x14++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x18++0x03 line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" group.long 0x1C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0x03 line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" wgroup.long 0x24++0x03 line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" rgroup.long 0x28++0x03 line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" textline "" group.long 0xD0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register 0" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD4++0x03 line.long 0x00 "GICV_APR1,VM Active Priority Register 1" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xD8++0x03 line.long 0x00 "GICV_APR2,VM Active Priority Register 2" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" group.long 0xDC++0x03 line.long 0x00 "GICV_APR3,VM Active Priority Register 3" bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1" bitfld.long 0x00 30. " P30 ,Active Priority 30" "0,1" bitfld.long 0x00 29. " P29 ,Active Priority 29" "0,1" bitfld.long 0x00 28. " P28 ,Active Priority 28" "0,1" textline " " bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1" bitfld.long 0x00 26. " P26 ,Active Priority 26" "0,1" bitfld.long 0x00 25. " P25 ,Active Priority 25" "0,1" bitfld.long 0x00 24. " P24 ,Active Priority 24" "0,1" textline " " bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1" bitfld.long 0x00 22. " P22 ,Active Priority 22" "0,1" bitfld.long 0x00 21. " P21 ,Active Priority 21" "0,1" bitfld.long 0x00 20. " P20 ,Active Priority 20" "0,1" textline " " bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1" bitfld.long 0x00 18. " P18 ,Active Priority 18" "0,1" bitfld.long 0x00 17. " P17 ,Active Priority 17" "0,1" bitfld.long 0x00 16. " P16 ,Active Priority 16" "0,1" textline " " bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1" bitfld.long 0x00 14. " P14 ,Active Priority 14" "0,1" bitfld.long 0x00 13. " P13 ,Active Priority 13" "0,1" bitfld.long 0x00 12. " P12 ,Active Priority 12" "0,1" textline " " bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1" bitfld.long 0x00 10. " P10 ,Active Priority 10" "0,1" bitfld.long 0x00 9. " P9 ,Active Priority 9" "0,1" bitfld.long 0x00 8. " P8 ,Active Priority 8" "0,1" textline " " bitfld.long 0x00 7. " P7 ,Active Priority 7" "0,1" bitfld.long 0x00 6. " P6 ,Active Priority 6" "0,1" bitfld.long 0x00 5. " P5 ,Active Priority 5" "0,1" bitfld.long 0x00 4. " P4 ,Active Priority 4" "0,1" textline " " bitfld.long 0x00 3. " P3 ,Active Priority 3" "0,1" bitfld.long 0x00 2. " P2 ,Active Priority 2" "0,1" bitfld.long 0x00 1. " P1 ,Active Priority 1" "0,1" bitfld.long 0x00 0. " P0 ,Active Priority 0" "0,1" textline " " rgroup.long 0xFC++0x03 line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " REV ,Revision number for the CPU interface" ",,,GICv3,?..." hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x1000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" hexmask.long 0x00 0.--24. 1. " INTID ,Interrupt ID" tree.end width 0x0b endif width 0x0B AUTOINDENT.POP tree.end tree.end endif tree "APMU" base ad:0x0 tree "APMU_Domain[0]" base ad:0xE6170000 group.long 0x0++0x7 line.long 0x0 "WPCR,This register is 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls write protect function." hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" line.long 0x4 "WPR,These registers are 32-bit readable/writable registers. This register doesn’t belong to any Group. This register controls write protect function." hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." group.long 0x10++0x13 line.long 0x0 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x4 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x8 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0xC "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x10 "PTCSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls access protect function and holds information of access protection." bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" rgroup.long 0x24++0x3 line.long 0x0 "PTERADR,This register is a 32-bit readable register. This register belongs to Group1. This register holds information of access protection." hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." group.long 0x28++0x3 line.long 0x0 "DCLSEIJTR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls error injection for APMU DCLS error." bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" group.long 0x30++0x3 line.long 0x0 "SYSMONCTRL,This register is a 32-bit readable register. This register belongs to Group2. This register is used to control SYSMON’s function." hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" rgroup.long 0x34++0x3 line.long 0x0 "SYSMONSTSR,This register is a 32-bit readable register. This register belongs to Group2. This register is used to notify SYSMON status." hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." group.long 0x40++0x7 line.long 0x0 "A3PWRCTRL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls A3 power domain." bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" line.long 0x4 "A3PWRCTRL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls A3 power domain." bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" rgroup.long 0x48++0x7 line.long 0x0 "A3FSMSTSR0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates A3 FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." line.long 0x4 "A3FSMSTSR1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates A3 FSM state." hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." group.long 0x50++0x7 line.long 0x0 "A3FSMLOCKR0,This register is a 32-bit readable/writable register. This register belongs to Group2.This register controls a safety mechanism of FSM for A3 power domain." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" line.long 0x4 "A3FSMLOCKR1,This register is a 32-bit readable/writable register. This register belongs to Group2.This register controls a safety mechanism of FSM for A3 power domain." hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" rgroup.long 0x58++0x7 line.long 0x0 "INTSTSR,This register is a 32-bit readable register. This register belongs to Group2.This register indicates a factor of interrupt request signal." hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." line.long 0x4 "ERRSTSR,This register is a 32-bit readable register. This register belongs to Group2.This register indicates whether each FSM finds fault." bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." group.long 0x60++0xB line.long 0x0 "FRSTR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register control forced reset function." hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." line.long 0x4 "FRSTD,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether forced reset sequence is completed." hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." line.long 0x8 "FRSTCTRL,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls reset function and clock control function." bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" group.long 0x80++0x7 line.long 0x0 "PADDCHKSTSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register holds error information detected by Safety mechanism for APB bus interface." eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." line.long 0x4 "PWDATACHKSTSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register holds error information detected by Safety mechanism for APB bus interface." eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." group.long 0x98++0x7 line.long 0x0 "APRTMGINTMASK,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls transaction mask function between AP-System Core and INTC-AP when NSI reset has occurred." eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." line.long 0x4 "RSCTRL,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls RS signal operation for Cortex-A76 cluster." bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" group.long 0x300++0x7 line.long 0x0 "CR52CR,This register is a 32-bit readable/writable register. This register belongs to Group0. This register controls configuration of Cortex-R52." bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." line.long 0x4 "CR52RSTCTRL,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls reset operation for Cortex-R52." bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" group.long 0x30C++0x3 line.long 0x0 "FSMLOCKRCR52,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-R52 reset control." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" rgroup.long 0x318++0x3 line.long 0x0 "FSMSTSRCR52,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-R52 FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." group.long 0x31C++0x3 line.long 0x0 "G2GPRCR52,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." group.long 0x328++0x17 line.long 0x0 "CR52CMPEN,This register is a 32-bit readable/writable register. This register belongs to Group1.This register controls Cortex-R52 DCLS comparator." bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" line.long 0x4 "GCNTERRENCR52,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-R52." bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" line.long 0x8 "CR52RVBAR,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates Vector table base address for Cortex-R52." hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." line.long 0xC "CR52BAR,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates Boot address of Cortex-R52." hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" line.long 0x10 "CR52RVBARP,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates Vector table base address for Cortex-R52." hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." line.long 0x14 "CR52BARP,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates Boot address of Cortex-R52." hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." group.long 0x400++0x3 line.long 0x0 "PWRCTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x440++0x3 line.long 0x0 "PWRCTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x480++0x3 line.long 0x0 "PWRCTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x4C0++0x3 line.long 0x0 "PWRCTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x404++0x3 line.long 0x0 "L3CTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x444++0x3 line.long 0x0 "L3CTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x484++0x3 line.long 0x0 "L3CTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x4C4++0x3 line.long 0x0 "L3CTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x40C++0x3 line.long 0x0 "FSMLOCKRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x44C++0x3 line.long 0x0 "FSMLOCKRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x48C++0x3 line.long 0x0 "FSMLOCKRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x4CC++0x3 line.long 0x0 "FSMLOCKRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x410++0x3 line.long 0x0 "PDENYSTSRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x450++0x3 line.long 0x0 "PDENYSTSRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x490++0x3 line.long 0x0 "PDENYSTSRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x4D0++0x3 line.long 0x0 "PDENYSTSRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x414++0x3 line.long 0x0 "PDENYINTRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x454++0x3 line.long 0x0 "PDENYINTRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x494++0x3 line.long 0x0 "PDENYINTRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x4D4++0x3 line.long 0x0 "PDENYINTRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" rgroup.long 0x418++0x3 line.long 0x0 "FSMSTSRCL0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x458++0x3 line.long 0x0 "FSMSTSRCL1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x498++0x3 line.long 0x0 "FSMSTSRCL2,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x4D8++0x3 line.long 0x0 "FSMSTSRCL3,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." group.long 0x41C++0x3 line.long 0x0 "G2GPRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x45C++0x3 line.long 0x0 "G2GPRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x49C++0x3 line.long 0x0 "G2GPRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x4DC++0x3 line.long 0x0 "G2GPRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x420++0x3 line.long 0x0 "SAFECTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x460++0x3 line.long 0x0 "SAFECTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x4A0++0x3 line.long 0x0 "SAFECTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x4E0++0x3 line.long 0x0 "SAFECTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." rgroup.long 0x424++0x3 line.long 0x0 "DCLSENCL0,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether Cortex-A76 cluster is in DCLS mode." bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" rgroup.long 0x4A4++0x3 line.long 0x0 "DCLSENCL2,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether Cortex-A76 cluster is in DCLS mode." bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" group.long 0x428++0x3 line.long 0x0 "DCLSCMPENCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls a DCLS comparator for Cortex-A76 cluster." bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" group.long 0x4A8++0x3 line.long 0x0 "DCLSCMPENCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls a DCLS comparator for Cortex-A76 cluster." bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" group.long 0x42C++0x3 line.long 0x0 "GCNTERRENCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-A76 cluster." bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" group.long 0x4AC++0x3 line.long 0x0 "GCNTERRENCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-A76 cluster." bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" group.long 0x800++0x3 line.long 0x0 "PWRCTRLC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x840++0x3 line.long 0x0 "PWRCTRLC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xA00++0x3 line.long 0x0 "PWRCTRLC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xA40++0x3 line.long 0x0 "PWRCTRLC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xC00++0x3 line.long 0x0 "PWRCTRLC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xC40++0x3 line.long 0x0 "PWRCTRLC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xE00++0x3 line.long 0x0 "PWRCTRLC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xE40++0x3 line.long 0x0 "PWRCTRLC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x80C++0x3 line.long 0x0 "FSMLOCKRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x84C++0x3 line.long 0x0 "FSMLOCKRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xA0C++0x3 line.long 0x0 "FSMLOCKRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xA4C++0x3 line.long 0x0 "FSMLOCKRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xC0C++0x3 line.long 0x0 "FSMLOCKRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xC4C++0x3 line.long 0x0 "FSMLOCKRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xE0C++0x3 line.long 0x0 "FSMLOCKRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xE4C++0x3 line.long 0x0 "FSMLOCKRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x810++0x3 line.long 0x0 "PDENYSTSRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x850++0x3 line.long 0x0 "PDENYSTSRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xA10++0x3 line.long 0x0 "PDENYSTSRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xA50++0x3 line.long 0x0 "PDENYSTSRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xC10++0x3 line.long 0x0 "PDENYSTSRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xC50++0x3 line.long 0x0 "PDENYSTSRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xE10++0x3 line.long 0x0 "PDENYSTSRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xE50++0x3 line.long 0x0 "PDENYSTSRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x814++0x3 line.long 0x0 "PDENYINTRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x854++0x3 line.long 0x0 "PDENYINTRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xA14++0x3 line.long 0x0 "PDENYINTRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xA54++0x3 line.long 0x0 "PDENYINTRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xC14++0x3 line.long 0x0 "PDENYINTRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xC54++0x3 line.long 0x0 "PDENYINTRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xE14++0x3 line.long 0x0 "PDENYINTRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xE54++0x3 line.long 0x0 "PDENYINTRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" rgroup.long 0x818++0x3 line.long 0x0 "FSMSTSRC0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0x858++0x3 line.long 0x0 "FSMSTSRC1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xA18++0x3 line.long 0x0 "FSMSTSRC2,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xA58++0x3 line.long 0x0 "FSMSTSRC3,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xC18++0x3 line.long 0x0 "FSMSTSRC4,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xC58++0x3 line.long 0x0 "FSMSTSRC5,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xE18++0x3 line.long 0x0 "FSMSTSRC6,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xE58++0x3 line.long 0x0 "FSMSTSRC7,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." group.long 0x81C++0x3 line.long 0x0 "G2GPRC0,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x85C++0x3 line.long 0x0 "G2GPRC1,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xA1C++0x3 line.long 0x0 "G2GPRC2,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xA5C++0x3 line.long 0x0 "G2GPRC3,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xC1C++0x3 line.long 0x0 "G2GPRC4,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xC5C++0x3 line.long 0x0 "G2GPRC5,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xE1C++0x3 line.long 0x0 "G2GPRC6,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xE5C++0x3 line.long 0x0 "G2GPRC7,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x820++0x3 line.long 0x0 "SAFECTRLC0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0x860++0x3 line.long 0x0 "SAFECTRLC1,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xA20++0x3 line.long 0x0 "SAFECTRLC2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xA60++0x3 line.long 0x0 "SAFECTRLC3,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xC20++0x3 line.long 0x0 "SAFECTRLC4,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xC60++0x3 line.long 0x0 "SAFECTRLC5,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xE20++0x3 line.long 0x0 "SAFECTRLC6,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xE60++0x3 line.long 0x0 "SAFECTRLC7,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0x830++0x3 line.long 0x0 "RVBARLC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0x870++0x3 line.long 0x0 "RVBARLC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xA30++0x3 line.long 0x0 "RVBARLC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xA70++0x3 line.long 0x0 "RVBARLC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xC30++0x3 line.long 0x0 "RVBARLC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xC70++0x3 line.long 0x0 "RVBARLC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xE30++0x3 line.long 0x0 "RVBARLC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xE70++0x3 line.long 0x0 "RVBARLC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0x834++0x3 line.long 0x0 "RVBARHC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0x874++0x3 line.long 0x0 "RVBARHC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xA34++0x3 line.long 0x0 "RVBARHC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xA74++0x3 line.long 0x0 "RVBARHC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xC34++0x3 line.long 0x0 "RVBARHC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xC74++0x3 line.long 0x0 "RVBARHC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xE34++0x3 line.long 0x0 "RVBARHC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xE74++0x3 line.long 0x0 "RVBARHC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0x838++0x3 line.long 0x0 "RVBARPLC0,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0x878++0x3 line.long 0x0 "RVBARPLC1,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xA38++0x3 line.long 0x0 "RVBARPLC2,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xA78++0x3 line.long 0x0 "RVBARPLC3,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xC38++0x3 line.long 0x0 "RVBARPLC4,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xC78++0x3 line.long 0x0 "RVBARPLC5,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xE38++0x3 line.long 0x0 "RVBARPLC6,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xE78++0x3 line.long 0x0 "RVBARPLC7,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0x83C++0x3 line.long 0x0 "RVBARPHC0,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0x87C++0x3 line.long 0x0 "RVBARPHC1,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xA3C++0x3 line.long 0x0 "RVBARPHC2,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xA7C++0x3 line.long 0x0 "RVBARPHC3,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xC3C++0x3 line.long 0x0 "RVBARPHC4,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xC7C++0x3 line.long 0x0 "RVBARPHC5,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xE3C++0x3 line.long 0x0 "RVBARPHC6,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xE7C++0x3 line.long 0x0 "RVBARPHC7,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." tree.end tree "APMU_Domain[1]" base ad:0xE6171000 group.long 0x0++0x7 line.long 0x0 "WPCR,This register is 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls write protect function." hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" line.long 0x4 "WPR,These registers are 32-bit readable/writable registers. This register doesn’t belong to any Group. This register controls write protect function." hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." group.long 0x10++0x13 line.long 0x0 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x4 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x8 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0xC "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x10 "PTCSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls access protect function and holds information of access protection." bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" rgroup.long 0x24++0x3 line.long 0x0 "PTERADR,This register is a 32-bit readable register. This register belongs to Group1. This register holds information of access protection." hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." group.long 0x28++0x3 line.long 0x0 "DCLSEIJTR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls error injection for APMU DCLS error." bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" group.long 0x30++0x3 line.long 0x0 "SYSMONCTRL,This register is a 32-bit readable register. This register belongs to Group2. This register is used to control SYSMON’s function." hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" rgroup.long 0x34++0x3 line.long 0x0 "SYSMONSTSR,This register is a 32-bit readable register. This register belongs to Group2. This register is used to notify SYSMON status." hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." group.long 0x40++0x7 line.long 0x0 "A3PWRCTRL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls A3 power domain." bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" line.long 0x4 "A3PWRCTRL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls A3 power domain." bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" rgroup.long 0x48++0x7 line.long 0x0 "A3FSMSTSR0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates A3 FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." line.long 0x4 "A3FSMSTSR1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates A3 FSM state." hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." group.long 0x50++0x7 line.long 0x0 "A3FSMLOCKR0,This register is a 32-bit readable/writable register. This register belongs to Group2.This register controls a safety mechanism of FSM for A3 power domain." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" line.long 0x4 "A3FSMLOCKR1,This register is a 32-bit readable/writable register. This register belongs to Group2.This register controls a safety mechanism of FSM for A3 power domain." hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" rgroup.long 0x58++0x7 line.long 0x0 "INTSTSR,This register is a 32-bit readable register. This register belongs to Group2.This register indicates a factor of interrupt request signal." hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." line.long 0x4 "ERRSTSR,This register is a 32-bit readable register. This register belongs to Group2.This register indicates whether each FSM finds fault." bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." group.long 0x60++0xB line.long 0x0 "FRSTR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register control forced reset function." hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." line.long 0x4 "FRSTD,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether forced reset sequence is completed." hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." line.long 0x8 "FRSTCTRL,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls reset function and clock control function." bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" group.long 0x80++0x7 line.long 0x0 "PADDCHKSTSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register holds error information detected by Safety mechanism for APB bus interface." eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." line.long 0x4 "PWDATACHKSTSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register holds error information detected by Safety mechanism for APB bus interface." eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." group.long 0x98++0x7 line.long 0x0 "APRTMGINTMASK,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls transaction mask function between AP-System Core and INTC-AP when NSI reset has occurred." eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." line.long 0x4 "RSCTRL,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls RS signal operation for Cortex-A76 cluster." bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" group.long 0x300++0x7 line.long 0x0 "CR52CR,This register is a 32-bit readable/writable register. This register belongs to Group0. This register controls configuration of Cortex-R52." bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." line.long 0x4 "CR52RSTCTRL,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls reset operation for Cortex-R52." bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" group.long 0x30C++0x3 line.long 0x0 "FSMLOCKRCR52,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-R52 reset control." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" rgroup.long 0x318++0x3 line.long 0x0 "FSMSTSRCR52,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-R52 FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." group.long 0x31C++0x3 line.long 0x0 "G2GPRCR52,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." group.long 0x328++0x17 line.long 0x0 "CR52CMPEN,This register is a 32-bit readable/writable register. This register belongs to Group1.This register controls Cortex-R52 DCLS comparator." bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" line.long 0x4 "GCNTERRENCR52,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-R52." bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" line.long 0x8 "CR52RVBAR,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates Vector table base address for Cortex-R52." hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." line.long 0xC "CR52BAR,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates Boot address of Cortex-R52." hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" line.long 0x10 "CR52RVBARP,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates Vector table base address for Cortex-R52." hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." line.long 0x14 "CR52BARP,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates Boot address of Cortex-R52." hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." group.long 0x400++0x3 line.long 0x0 "PWRCTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x440++0x3 line.long 0x0 "PWRCTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x480++0x3 line.long 0x0 "PWRCTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x4C0++0x3 line.long 0x0 "PWRCTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x404++0x3 line.long 0x0 "L3CTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x444++0x3 line.long 0x0 "L3CTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x484++0x3 line.long 0x0 "L3CTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x4C4++0x3 line.long 0x0 "L3CTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x40C++0x3 line.long 0x0 "FSMLOCKRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x44C++0x3 line.long 0x0 "FSMLOCKRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x48C++0x3 line.long 0x0 "FSMLOCKRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x4CC++0x3 line.long 0x0 "FSMLOCKRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x410++0x3 line.long 0x0 "PDENYSTSRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x450++0x3 line.long 0x0 "PDENYSTSRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x490++0x3 line.long 0x0 "PDENYSTSRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x4D0++0x3 line.long 0x0 "PDENYSTSRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x414++0x3 line.long 0x0 "PDENYINTRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x454++0x3 line.long 0x0 "PDENYINTRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x494++0x3 line.long 0x0 "PDENYINTRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x4D4++0x3 line.long 0x0 "PDENYINTRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" rgroup.long 0x418++0x3 line.long 0x0 "FSMSTSRCL0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x458++0x3 line.long 0x0 "FSMSTSRCL1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x498++0x3 line.long 0x0 "FSMSTSRCL2,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x4D8++0x3 line.long 0x0 "FSMSTSRCL3,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." group.long 0x41C++0x3 line.long 0x0 "G2GPRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x45C++0x3 line.long 0x0 "G2GPRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x49C++0x3 line.long 0x0 "G2GPRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x4DC++0x3 line.long 0x0 "G2GPRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x420++0x3 line.long 0x0 "SAFECTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x460++0x3 line.long 0x0 "SAFECTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x4A0++0x3 line.long 0x0 "SAFECTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x4E0++0x3 line.long 0x0 "SAFECTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." rgroup.long 0x424++0x3 line.long 0x0 "DCLSENCL0,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether Cortex-A76 cluster is in DCLS mode." bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" rgroup.long 0x4A4++0x3 line.long 0x0 "DCLSENCL2,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether Cortex-A76 cluster is in DCLS mode." bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" group.long 0x428++0x3 line.long 0x0 "DCLSCMPENCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls a DCLS comparator for Cortex-A76 cluster." bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" group.long 0x4A8++0x3 line.long 0x0 "DCLSCMPENCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls a DCLS comparator for Cortex-A76 cluster." bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" group.long 0x42C++0x3 line.long 0x0 "GCNTERRENCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-A76 cluster." bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" group.long 0x4AC++0x3 line.long 0x0 "GCNTERRENCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-A76 cluster." bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" group.long 0x800++0x3 line.long 0x0 "PWRCTRLC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x840++0x3 line.long 0x0 "PWRCTRLC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xA00++0x3 line.long 0x0 "PWRCTRLC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xA40++0x3 line.long 0x0 "PWRCTRLC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xC00++0x3 line.long 0x0 "PWRCTRLC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xC40++0x3 line.long 0x0 "PWRCTRLC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xE00++0x3 line.long 0x0 "PWRCTRLC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xE40++0x3 line.long 0x0 "PWRCTRLC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x80C++0x3 line.long 0x0 "FSMLOCKRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x84C++0x3 line.long 0x0 "FSMLOCKRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xA0C++0x3 line.long 0x0 "FSMLOCKRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xA4C++0x3 line.long 0x0 "FSMLOCKRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xC0C++0x3 line.long 0x0 "FSMLOCKRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xC4C++0x3 line.long 0x0 "FSMLOCKRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xE0C++0x3 line.long 0x0 "FSMLOCKRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xE4C++0x3 line.long 0x0 "FSMLOCKRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x810++0x3 line.long 0x0 "PDENYSTSRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x850++0x3 line.long 0x0 "PDENYSTSRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xA10++0x3 line.long 0x0 "PDENYSTSRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xA50++0x3 line.long 0x0 "PDENYSTSRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xC10++0x3 line.long 0x0 "PDENYSTSRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xC50++0x3 line.long 0x0 "PDENYSTSRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xE10++0x3 line.long 0x0 "PDENYSTSRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xE50++0x3 line.long 0x0 "PDENYSTSRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x814++0x3 line.long 0x0 "PDENYINTRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x854++0x3 line.long 0x0 "PDENYINTRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xA14++0x3 line.long 0x0 "PDENYINTRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xA54++0x3 line.long 0x0 "PDENYINTRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xC14++0x3 line.long 0x0 "PDENYINTRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xC54++0x3 line.long 0x0 "PDENYINTRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xE14++0x3 line.long 0x0 "PDENYINTRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xE54++0x3 line.long 0x0 "PDENYINTRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" rgroup.long 0x818++0x3 line.long 0x0 "FSMSTSRC0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0x858++0x3 line.long 0x0 "FSMSTSRC1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xA18++0x3 line.long 0x0 "FSMSTSRC2,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xA58++0x3 line.long 0x0 "FSMSTSRC3,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xC18++0x3 line.long 0x0 "FSMSTSRC4,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xC58++0x3 line.long 0x0 "FSMSTSRC5,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xE18++0x3 line.long 0x0 "FSMSTSRC6,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xE58++0x3 line.long 0x0 "FSMSTSRC7,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." group.long 0x81C++0x3 line.long 0x0 "G2GPRC0,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x85C++0x3 line.long 0x0 "G2GPRC1,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xA1C++0x3 line.long 0x0 "G2GPRC2,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xA5C++0x3 line.long 0x0 "G2GPRC3,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xC1C++0x3 line.long 0x0 "G2GPRC4,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xC5C++0x3 line.long 0x0 "G2GPRC5,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xE1C++0x3 line.long 0x0 "G2GPRC6,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xE5C++0x3 line.long 0x0 "G2GPRC7,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x820++0x3 line.long 0x0 "SAFECTRLC0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0x860++0x3 line.long 0x0 "SAFECTRLC1,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xA20++0x3 line.long 0x0 "SAFECTRLC2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xA60++0x3 line.long 0x0 "SAFECTRLC3,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xC20++0x3 line.long 0x0 "SAFECTRLC4,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xC60++0x3 line.long 0x0 "SAFECTRLC5,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xE20++0x3 line.long 0x0 "SAFECTRLC6,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xE60++0x3 line.long 0x0 "SAFECTRLC7,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0x830++0x3 line.long 0x0 "RVBARLC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0x870++0x3 line.long 0x0 "RVBARLC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xA30++0x3 line.long 0x0 "RVBARLC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xA70++0x3 line.long 0x0 "RVBARLC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xC30++0x3 line.long 0x0 "RVBARLC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xC70++0x3 line.long 0x0 "RVBARLC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xE30++0x3 line.long 0x0 "RVBARLC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xE70++0x3 line.long 0x0 "RVBARLC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0x834++0x3 line.long 0x0 "RVBARHC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0x874++0x3 line.long 0x0 "RVBARHC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xA34++0x3 line.long 0x0 "RVBARHC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xA74++0x3 line.long 0x0 "RVBARHC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xC34++0x3 line.long 0x0 "RVBARHC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xC74++0x3 line.long 0x0 "RVBARHC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xE34++0x3 line.long 0x0 "RVBARHC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xE74++0x3 line.long 0x0 "RVBARHC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0x838++0x3 line.long 0x0 "RVBARPLC0,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0x878++0x3 line.long 0x0 "RVBARPLC1,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xA38++0x3 line.long 0x0 "RVBARPLC2,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xA78++0x3 line.long 0x0 "RVBARPLC3,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xC38++0x3 line.long 0x0 "RVBARPLC4,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xC78++0x3 line.long 0x0 "RVBARPLC5,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xE38++0x3 line.long 0x0 "RVBARPLC6,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xE78++0x3 line.long 0x0 "RVBARPLC7,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0x83C++0x3 line.long 0x0 "RVBARPHC0,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0x87C++0x3 line.long 0x0 "RVBARPHC1,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xA3C++0x3 line.long 0x0 "RVBARPHC2,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xA7C++0x3 line.long 0x0 "RVBARPHC3,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xC3C++0x3 line.long 0x0 "RVBARPHC4,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xC7C++0x3 line.long 0x0 "RVBARPHC5,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xE3C++0x3 line.long 0x0 "RVBARPHC6,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xE7C++0x3 line.long 0x0 "RVBARPHC7,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." tree.end tree "APMU_Domain[2]" base ad:0xE6172000 group.long 0x0++0x7 line.long 0x0 "WPCR,This register is 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls write protect function." hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" line.long 0x4 "WPR,These registers are 32-bit readable/writable registers. This register doesn’t belong to any Group. This register controls write protect function." hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." group.long 0x10++0x13 line.long 0x0 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x4 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x8 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0xC "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x10 "PTCSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls access protect function and holds information of access protection." bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" rgroup.long 0x24++0x3 line.long 0x0 "PTERADR,This register is a 32-bit readable register. This register belongs to Group1. This register holds information of access protection." hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." group.long 0x28++0x3 line.long 0x0 "DCLSEIJTR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls error injection for APMU DCLS error." bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" group.long 0x30++0x3 line.long 0x0 "SYSMONCTRL,This register is a 32-bit readable register. This register belongs to Group2. This register is used to control SYSMON’s function." hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" rgroup.long 0x34++0x3 line.long 0x0 "SYSMONSTSR,This register is a 32-bit readable register. This register belongs to Group2. This register is used to notify SYSMON status." hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." group.long 0x40++0x7 line.long 0x0 "A3PWRCTRL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls A3 power domain." bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" line.long 0x4 "A3PWRCTRL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls A3 power domain." bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" rgroup.long 0x48++0x7 line.long 0x0 "A3FSMSTSR0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates A3 FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." line.long 0x4 "A3FSMSTSR1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates A3 FSM state." hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." group.long 0x50++0x7 line.long 0x0 "A3FSMLOCKR0,This register is a 32-bit readable/writable register. This register belongs to Group2.This register controls a safety mechanism of FSM for A3 power domain." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" line.long 0x4 "A3FSMLOCKR1,This register is a 32-bit readable/writable register. This register belongs to Group2.This register controls a safety mechanism of FSM for A3 power domain." hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" rgroup.long 0x58++0x7 line.long 0x0 "INTSTSR,This register is a 32-bit readable register. This register belongs to Group2.This register indicates a factor of interrupt request signal." hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." line.long 0x4 "ERRSTSR,This register is a 32-bit readable register. This register belongs to Group2.This register indicates whether each FSM finds fault." bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." group.long 0x60++0xB line.long 0x0 "FRSTR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register control forced reset function." hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." line.long 0x4 "FRSTD,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether forced reset sequence is completed." hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." line.long 0x8 "FRSTCTRL,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls reset function and clock control function." bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" group.long 0x80++0x7 line.long 0x0 "PADDCHKSTSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register holds error information detected by Safety mechanism for APB bus interface." eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." line.long 0x4 "PWDATACHKSTSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register holds error information detected by Safety mechanism for APB bus interface." eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." group.long 0x98++0x7 line.long 0x0 "APRTMGINTMASK,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls transaction mask function between AP-System Core and INTC-AP when NSI reset has occurred." eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." line.long 0x4 "RSCTRL,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls RS signal operation for Cortex-A76 cluster." bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" group.long 0x300++0x7 line.long 0x0 "CR52CR,This register is a 32-bit readable/writable register. This register belongs to Group0. This register controls configuration of Cortex-R52." bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." line.long 0x4 "CR52RSTCTRL,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls reset operation for Cortex-R52." bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" group.long 0x30C++0x3 line.long 0x0 "FSMLOCKRCR52,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-R52 reset control." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" rgroup.long 0x318++0x3 line.long 0x0 "FSMSTSRCR52,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-R52 FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." group.long 0x31C++0x3 line.long 0x0 "G2GPRCR52,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." group.long 0x328++0x17 line.long 0x0 "CR52CMPEN,This register is a 32-bit readable/writable register. This register belongs to Group1.This register controls Cortex-R52 DCLS comparator." bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" line.long 0x4 "GCNTERRENCR52,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-R52." bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" line.long 0x8 "CR52RVBAR,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates Vector table base address for Cortex-R52." hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." line.long 0xC "CR52BAR,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates Boot address of Cortex-R52." hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" line.long 0x10 "CR52RVBARP,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates Vector table base address for Cortex-R52." hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." line.long 0x14 "CR52BARP,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates Boot address of Cortex-R52." hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." group.long 0x400++0x3 line.long 0x0 "PWRCTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x440++0x3 line.long 0x0 "PWRCTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x480++0x3 line.long 0x0 "PWRCTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x4C0++0x3 line.long 0x0 "PWRCTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x404++0x3 line.long 0x0 "L3CTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x444++0x3 line.long 0x0 "L3CTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x484++0x3 line.long 0x0 "L3CTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x4C4++0x3 line.long 0x0 "L3CTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x40C++0x3 line.long 0x0 "FSMLOCKRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x44C++0x3 line.long 0x0 "FSMLOCKRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x48C++0x3 line.long 0x0 "FSMLOCKRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x4CC++0x3 line.long 0x0 "FSMLOCKRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x410++0x3 line.long 0x0 "PDENYSTSRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x450++0x3 line.long 0x0 "PDENYSTSRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x490++0x3 line.long 0x0 "PDENYSTSRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x4D0++0x3 line.long 0x0 "PDENYSTSRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x414++0x3 line.long 0x0 "PDENYINTRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x454++0x3 line.long 0x0 "PDENYINTRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x494++0x3 line.long 0x0 "PDENYINTRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x4D4++0x3 line.long 0x0 "PDENYINTRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" rgroup.long 0x418++0x3 line.long 0x0 "FSMSTSRCL0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x458++0x3 line.long 0x0 "FSMSTSRCL1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x498++0x3 line.long 0x0 "FSMSTSRCL2,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x4D8++0x3 line.long 0x0 "FSMSTSRCL3,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." group.long 0x41C++0x3 line.long 0x0 "G2GPRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x45C++0x3 line.long 0x0 "G2GPRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x49C++0x3 line.long 0x0 "G2GPRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x4DC++0x3 line.long 0x0 "G2GPRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x420++0x3 line.long 0x0 "SAFECTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x460++0x3 line.long 0x0 "SAFECTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x4A0++0x3 line.long 0x0 "SAFECTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x4E0++0x3 line.long 0x0 "SAFECTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." rgroup.long 0x424++0x3 line.long 0x0 "DCLSENCL0,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether Cortex-A76 cluster is in DCLS mode." bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" rgroup.long 0x4A4++0x3 line.long 0x0 "DCLSENCL2,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether Cortex-A76 cluster is in DCLS mode." bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" group.long 0x428++0x3 line.long 0x0 "DCLSCMPENCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls a DCLS comparator for Cortex-A76 cluster." bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" group.long 0x4A8++0x3 line.long 0x0 "DCLSCMPENCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls a DCLS comparator for Cortex-A76 cluster." bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" group.long 0x42C++0x3 line.long 0x0 "GCNTERRENCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-A76 cluster." bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" group.long 0x4AC++0x3 line.long 0x0 "GCNTERRENCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-A76 cluster." bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" group.long 0x800++0x3 line.long 0x0 "PWRCTRLC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x840++0x3 line.long 0x0 "PWRCTRLC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xA00++0x3 line.long 0x0 "PWRCTRLC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xA40++0x3 line.long 0x0 "PWRCTRLC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xC00++0x3 line.long 0x0 "PWRCTRLC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xC40++0x3 line.long 0x0 "PWRCTRLC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xE00++0x3 line.long 0x0 "PWRCTRLC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xE40++0x3 line.long 0x0 "PWRCTRLC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x80C++0x3 line.long 0x0 "FSMLOCKRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x84C++0x3 line.long 0x0 "FSMLOCKRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xA0C++0x3 line.long 0x0 "FSMLOCKRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xA4C++0x3 line.long 0x0 "FSMLOCKRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xC0C++0x3 line.long 0x0 "FSMLOCKRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xC4C++0x3 line.long 0x0 "FSMLOCKRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xE0C++0x3 line.long 0x0 "FSMLOCKRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xE4C++0x3 line.long 0x0 "FSMLOCKRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x810++0x3 line.long 0x0 "PDENYSTSRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x850++0x3 line.long 0x0 "PDENYSTSRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xA10++0x3 line.long 0x0 "PDENYSTSRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xA50++0x3 line.long 0x0 "PDENYSTSRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xC10++0x3 line.long 0x0 "PDENYSTSRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xC50++0x3 line.long 0x0 "PDENYSTSRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xE10++0x3 line.long 0x0 "PDENYSTSRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xE50++0x3 line.long 0x0 "PDENYSTSRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x814++0x3 line.long 0x0 "PDENYINTRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x854++0x3 line.long 0x0 "PDENYINTRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xA14++0x3 line.long 0x0 "PDENYINTRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xA54++0x3 line.long 0x0 "PDENYINTRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xC14++0x3 line.long 0x0 "PDENYINTRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xC54++0x3 line.long 0x0 "PDENYINTRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xE14++0x3 line.long 0x0 "PDENYINTRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xE54++0x3 line.long 0x0 "PDENYINTRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" rgroup.long 0x818++0x3 line.long 0x0 "FSMSTSRC0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0x858++0x3 line.long 0x0 "FSMSTSRC1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xA18++0x3 line.long 0x0 "FSMSTSRC2,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xA58++0x3 line.long 0x0 "FSMSTSRC3,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xC18++0x3 line.long 0x0 "FSMSTSRC4,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xC58++0x3 line.long 0x0 "FSMSTSRC5,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xE18++0x3 line.long 0x0 "FSMSTSRC6,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xE58++0x3 line.long 0x0 "FSMSTSRC7,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." group.long 0x81C++0x3 line.long 0x0 "G2GPRC0,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x85C++0x3 line.long 0x0 "G2GPRC1,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xA1C++0x3 line.long 0x0 "G2GPRC2,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xA5C++0x3 line.long 0x0 "G2GPRC3,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xC1C++0x3 line.long 0x0 "G2GPRC4,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xC5C++0x3 line.long 0x0 "G2GPRC5,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xE1C++0x3 line.long 0x0 "G2GPRC6,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xE5C++0x3 line.long 0x0 "G2GPRC7,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x820++0x3 line.long 0x0 "SAFECTRLC0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0x860++0x3 line.long 0x0 "SAFECTRLC1,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xA20++0x3 line.long 0x0 "SAFECTRLC2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xA60++0x3 line.long 0x0 "SAFECTRLC3,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xC20++0x3 line.long 0x0 "SAFECTRLC4,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xC60++0x3 line.long 0x0 "SAFECTRLC5,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xE20++0x3 line.long 0x0 "SAFECTRLC6,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xE60++0x3 line.long 0x0 "SAFECTRLC7,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0x830++0x3 line.long 0x0 "RVBARLC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0x870++0x3 line.long 0x0 "RVBARLC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xA30++0x3 line.long 0x0 "RVBARLC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xA70++0x3 line.long 0x0 "RVBARLC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xC30++0x3 line.long 0x0 "RVBARLC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xC70++0x3 line.long 0x0 "RVBARLC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xE30++0x3 line.long 0x0 "RVBARLC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xE70++0x3 line.long 0x0 "RVBARLC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0x834++0x3 line.long 0x0 "RVBARHC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0x874++0x3 line.long 0x0 "RVBARHC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xA34++0x3 line.long 0x0 "RVBARHC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xA74++0x3 line.long 0x0 "RVBARHC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xC34++0x3 line.long 0x0 "RVBARHC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xC74++0x3 line.long 0x0 "RVBARHC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xE34++0x3 line.long 0x0 "RVBARHC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xE74++0x3 line.long 0x0 "RVBARHC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0x838++0x3 line.long 0x0 "RVBARPLC0,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0x878++0x3 line.long 0x0 "RVBARPLC1,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xA38++0x3 line.long 0x0 "RVBARPLC2,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xA78++0x3 line.long 0x0 "RVBARPLC3,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xC38++0x3 line.long 0x0 "RVBARPLC4,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xC78++0x3 line.long 0x0 "RVBARPLC5,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xE38++0x3 line.long 0x0 "RVBARPLC6,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xE78++0x3 line.long 0x0 "RVBARPLC7,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0x83C++0x3 line.long 0x0 "RVBARPHC0,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0x87C++0x3 line.long 0x0 "RVBARPHC1,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xA3C++0x3 line.long 0x0 "RVBARPHC2,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xA7C++0x3 line.long 0x0 "RVBARPHC3,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xC3C++0x3 line.long 0x0 "RVBARPHC4,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xC7C++0x3 line.long 0x0 "RVBARPHC5,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xE3C++0x3 line.long 0x0 "RVBARPHC6,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xE7C++0x3 line.long 0x0 "RVBARPHC7,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." tree.end tree "APMU_Domain[3]" base ad:0xE6173000 group.long 0x0++0x7 line.long 0x0 "WPCR,This register is 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls write protect function." hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline hexmask.long.word 0x0 16.--31. 1. "Code value,Code Value" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" newline bitfld.long 0x0 0. "WPE,Write Protect Enable. The possible values are following." "0: Write protect is disabled,1: Write protect is enabled" line.long 0x4 "WPR,These registers are 32-bit readable/writable registers. This register doesn’t belong to any Group. This register controls write protect function." hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." newline hexmask.long 0x4 0.--31. 1. "WPRTCT,If Write Protect is enabled inverted values need to be set to this field before write access." group.long 0x10++0x13 line.long 0x0 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 20.--23. 1. "ADMNGRP0,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "RTGRP0,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 12.--15. 1. "CL3GRP0,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 8.--11. 1. "CL2GRP0,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 4.--7. 1. "CL1GRP0,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x0 0.--3. 1. "CL0GRP0,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x4 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 20.--23. 1. "ADMNGRP1,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 16.--19. 1. "RTGRP1,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 12.--15. 1. "CL3GRP1,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 8.--11. 1. "CL2GRP1,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 4.--7. 1. "CL1GRP1,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x4 0.--3. 1. "CL0GRP1,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x8 "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 20.--23. 1. "ADMNGRP2,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 16.--19. 1. "RTGRP2,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 12.--15. 1. "CL3GRP2,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 8.--11. 1. "CL2GRP2,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 4.--7. 1. "CL1GRP2,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0x8 0.--3. 1. "CL0GRP2,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0xC "DxACCENR,This register is a 32-bit readable/writable register. This register doesn’t belong to any Group. This register controls access protect function." hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 20.--23. 1. "ADMNGRP3,Register protection for Group x of admin registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 16.--19. 1. "RTGRP3,Register protection for Group x of CR52’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 12.--15. 1. "CL3GRP3,Register protection for Group x of Cortex-A76 cluster 3’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 8.--11. 1. "CL2GRP3,Register protection for Group x of Cortex-A76 cluster 2’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 4.--7. 1. "CL1GRP3,Register protection for Group x of Cortex-A76 cluster 1’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." newline hexmask.long.byte 0xC 0.--3. 1. "CL0GRP3,Register protection for Group x of Cortex-A76 cluster 0’s registers. The possible values are following." line.long 0x10 "PTCSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls access protect function and holds information of access protection." bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 1. "EIE,Error Interrupt Enable bit. The possible values are following." "0: access error detection is disabled,1: access error detection is enabled" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" newline bitfld.long 0x10 0. "ERR,Indicates whether access error has occurred. This bit is enabled when 1 is set to EIE bit in PTCSR. Permitted values are following." "0: error has not occurred,1: error has occurred" rgroup.long 0x24++0x3 line.long 0x0 "PTERADR,This register is a 32-bit readable register. This register belongs to Group1. This register holds information of access protection." hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." newline hexmask.long.word 0x0 0.--15. 1. "ADDR,Indicate address causing access error." group.long 0x28++0x3 line.long 0x0 "DCLSEIJTR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls error injection for APMU DCLS error." bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" newline bitfld.long 0x0 0. "EIJT,Error Injection enable. The possible values are:" "0: error injection is not active,1: error injection is active" group.long 0x30++0x3 line.long 0x0 "SYSMONCTRL,This register is a 32-bit readable register. This register belongs to Group2. This register is used to control SYSMON’s function." hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" newline hexmask.long.byte 0x0 0.--6. 1. "SYSMON_sel,Select FSM to be informed to SYSMON. The possible values are:" rgroup.long 0x34++0x3 line.long 0x0 "SYSMONSTSR,This register is a 32-bit readable register. This register belongs to Group2. This register is used to notify SYSMON status." hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." newline hexmask.long.byte 0x0 0.--7. 1. "SYSMON_state,This field indicates FSM state selected by SYSMON_sel bit in SYSMONCTRL." group.long 0x40++0x7 line.long 0x0 "A3PWRCTRL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls A3 power domain." bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x0 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" line.long 0x4 "A3PWRCTRL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls A3 power domain." bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 4. "A3_PDN_EN,Power down enable for A3 power domain. The possible values are following" "0: A3 power domain cannot be powered down,1: A3 power domain is powered down if all A1 and A2.." newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" newline bitfld.long 0x4 0. "A3_WUP_REQ,A3 power domain wakeup request. The possible values are following." "0: A3 power domain wakeup is not requested,1: A3 power domain wakeup is requested" rgroup.long 0x48++0x7 line.long 0x0 "A3FSMSTSR0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates A3 FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." line.long 0x4 "A3FSMSTSR1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates A3 FSM state." hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." group.long 0x50++0x7 line.long 0x0 "A3FSMLOCKR0,This register is a 32-bit readable/writable register. This register belongs to Group2.This register controls a safety mechanism of FSM for A3 power domain." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" line.long 0x4 "A3FSMLOCKR1,This register is a 32-bit readable/writable register. This register belongs to Group2.This register controls a safety mechanism of FSM for A3 power domain." hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x4 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x4 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x4 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x4 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" rgroup.long 0x58++0x7 line.long 0x0 "INTSTSR,This register is a 32-bit readable register. This register belongs to Group2.This register indicates a factor of interrupt request signal." hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 16.--19. 1. "A2Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "A1Cx_INT,Indicate whether each A2 domain FSM issues interrupt request. x means Cortex-A76 core number. Permitted values are following." line.long 0x4 "ERRSTSR,This register is a 32-bit readable register. This register belongs to Group2.This register indicates whether each FSM finds fault." bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 28. "CR52_ERR,Indicates whether error flag is set in FSMLOCKRCR52. Permitted values are following." "0: Error is not detected,1: Error is detected" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline bitfld.long 0x4 24.--25. "A3Sx_ERR,Indicates whether error flag is set in A3FSMLOCKRx. Permitted values are following." "0: Error is not detected,1: Error is detected,?,?" newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "A2Sx_ERR,Indicates whether error flag is set in FSMLOCKRCLx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "A1Cx_ERR,Indicates whether error flag is set in FSMLOCKRCx. Permitted values are following." group.long 0x60++0xB line.long 0x0 "FRSTR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register control forced reset function." hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 16.--19. 1. "FRSTRCL[0 1 2 3],Forced reset request for each Cortex-A76 cluster. x means Cortex-A76 cluster number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." newline hexmask.long.byte 0x0 0.--7. 1. "FRSTRC[0 1 2 3],Forced reset request for each Cortex-A76 core. x means Cortex-A76 core number. The possible values are following." line.long 0x4 "FRSTD,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether forced reset sequence is completed." hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 16.--19. 1. "FRSTDCL[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 cluster number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." newline hexmask.long.byte 0x4 0.--7. 1. "FRSTDC[0 1 2 3],Indicate whether forced reset is completed. x means Cortex-A76 Core number. Permitted values are following." line.long 0x8 "FRSTCTRL,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls reset function and clock control function." bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 31. "NSI_MOD_DBG,NSI reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by NSI reset,1: Only warm reset of Cortex-A76 is asserted by NSI.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 30. "FRST_MOD_DBG,Forced reset modification in debug mode. The possible values are following." "0: All reset signals are asserted by forced reset..,1: Only warm reset of Cortex-A76 is asserted by.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 29. "CLKPAUSE_EN,Clock pause enable when Cortex-A76 reset is asserting. The possible values are following." "0: Clock pause is disabled when Cortex-A76 reset is..,1: Clock pause is enabled when Cortex-A76 reset is.." newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 28. "CLKLOW_EN,Clock slow function enable when Cortex-A76 reset is asserting. This bit is enabled when 1 is set to CLKPAUSE_EN bit. The possible values are following." "0: Clock slow function is disabled,1: Clock slow function is enabled" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" newline bitfld.long 0x8 27. "CLKCHG_EN,Clock control enable. The possible values are following." "0: APMU doesn’t control Cortex-A76 clock,1: APMU controls Cortex-A76 clock" group.long 0x80++0x7 line.long 0x0 "PADDCHKSTSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register holds error information detected by Safety mechanism for APB bus interface." eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x0 31. "PADD_CHK_SID_CLR,PADD_CHK_SID clear bit. PADD_CHK_SID is cleared by writing 1 to this bit." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." newline hexmask.long.byte 0x0 0.--7. 1. "PADD_CHK_SID,Indicates Source ID of fault transaction detected PADD_CHK mechanism." line.long 0x4 "PWDATACHKSTSR,This register is a 32-bit readable/writable register. This register belongs to Group1. This register holds error information detected by Safety mechanism for APB bus interface." eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline eventfld.long 0x4 31. "PWDATA_CHK_SID_CLR,PWDATA_CHK_SID clear bit. PWDATA_CHK_SID is cleared by writing 1 to this bit." "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." newline hexmask.long.byte 0x4 0.--7. 1. "PWDATA_CHK_SID,Indicates Source ID of fault transaction detected PWDATA_CHK mechanism." group.long 0x98++0x7 line.long 0x0 "APRTMGINTMASK,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls transaction mask function between AP-System Core and INTC-AP when NSI reset has occurred." eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline eventfld.long 0x0 4. "MASK_CLR,Transaction mask clear. MASK_STS is cleared to 0 and transaction mask function is disabled by writing 0 to this bit." "0,1" newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." newline rbitfld.long 0x0 0. "MASK_STS,Indicate a status of transaction mask function between AP-System Core and INTC-AP. Permitted values are following." "0: Transaction between AP-System Core and INTC-AP..,1: Transaction between AP-System Core and INTC-AP.." line.long 0x4 "RSCTRL,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls RS signal operation for Cortex-A76 cluster." bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" newline bitfld.long 0x4 0. "RSMASK,RS signal mask. The possible values are following" "0: RS signal operation is not masked,1: RS signal operation is masked" group.long 0x300++0x7 line.long 0x0 "CR52CR,This register is a 32-bit readable/writable register. This register belongs to Group0. This register controls configuration of Cortex-R52." bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 30. "NCPUHALT,NCPUHALT means inverted value of CPUHALT defined in Cortex-R52 TRM. The possible values are following." "0: Processor halt after reset,1: No processor halt after reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 29. "CFGRAMPROTEN,CFGRAMPROTEN defined in Cortex-R52 TRM. The possible values are following." "0: RAM memory protection is disabled out of reset,1: RAM memory protection is enabled out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 28. "CFGTCMBOOT,CFGTCMBOOT defined in Cortex-R52 TRM. The possible values are following." "0: ATCM is disabled out of reset,1: ATCM is enabled and at address 0x0 out of reset" newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 27. "CFGINITREG,CFGINITREG defined in Cortex-R52 TRM. The possible values are following." "0: Program-visible registers are not initialized to..,1: Program-visible registers are initialized to.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." newline bitfld.long 0x0 26. "CFGL1CACHEINVDIS0,CFGL1CACHEINVDIS defined in Cortex-R52 TRM. The possible values are following." "0: Automatic post-reset L1 cache invalidate is..,1: Automatic post-reset L1 cache invalidate is.." line.long 0x4 "CR52RSTCTRL,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls reset operation for Cortex-R52." bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" newline bitfld.long 0x4 0. "CR52RST,Cortex-R52 reset. Indicates Cortex-R52 reset status. The initial value depends on Mode PIN configuration. Permitted values are following." "0: All Cortex-R52 resets are negated,1: All Cortex-R52 resets are asserted" group.long 0x30C++0x3 line.long 0x0 "FSMLOCKRCR52,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-R52 reset control." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" rgroup.long 0x318++0x3 line.long 0x0 "FSMSTSRCR52,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-R52 FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-R52 FSM. The permitted values are following." group.long 0x31C++0x3 line.long 0x0 "G2GPRCR52,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR,This fields are allowed to write any values and they don’t affect module operation." group.long 0x328++0x17 line.long 0x0 "CR52CMPEN,This register is a 32-bit readable/writable register. This register belongs to Group1.This register controls Cortex-R52 DCLS comparator." bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 1. "NSRCMPEN,Non-safety- related comparator enable. The possible values are following." "0: Comparator for Non-safety-related signals is..,1: Comparator for Non-safety-related signals is.." newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" newline bitfld.long 0x0 0. "CMPEN,Comparator enables. The possible values are following." "0: Comparator is disabled,1: Comparator is enabled" line.long 0x4 "GCNTERRENCR52,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-R52." bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x4 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" line.long 0x8 "CR52RVBAR,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates Vector table base address for Cortex-R52." hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x8 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." line.long 0xC "CR52BAR,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates Boot address of Cortex-R52." hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0xC 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline bitfld.long 0xC 4. "BAREN,BAR enables. The possible values are:" "0,1" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" newline rbitfld.long 0xC 0.--1. "BTMD,Boot Mode. Indicates boot area of Cortex-R52. Permitted values are following." "0: RBAR is assigned for boot address,?,?,?" line.long 0x10 "CR52RVBARP,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates Vector table base address for Cortex-R52." hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline hexmask.long 0x10 5.--31. 1. "CFGVECTABLE,CFGVECTABLE defined in Cortex-R52 TRM. Vector table base address out of reset." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." newline bitfld.long 0x10 0. "VLD,CR52RVBARP valid. The possible values are following." "0: CR52RVBAR is used to define CFGVECTABLE for..,1: CR52RVBARP is used to define CFGVECTABLE for.." line.long 0x14 "CR52BARP,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates Boot address of Cortex-R52." hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline hexmask.long.word 0x14 18.--31. 1. "RBAR,Real time CPU (Cortex-R52) Boot Address." newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 4. "BAREN,BAR enables. The possible values are following." "0: RBAR is not valid,1: RBAR is valid" newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." newline bitfld.long 0x14 0. "VLD,CR52BARP valid. The possible values are following." "0: CR52BAR is used to define Boot Address of..,1: CR52BARP is used to define Boot Address of.." group.long 0x400++0x3 line.long 0x0 "PWRCTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x440++0x3 line.long 0x0 "PWRCTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x480++0x3 line.long 0x0 "PWRCTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x4C0++0x3 line.long 0x0 "PWRCTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 cluster x." bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 21. "PCHMRETEN,MEM_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to MEM_RET mode is disabled,?" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 20. "PCHFRETEN,FUNC_RET mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to FUNC_RET mode is disabled,1: Power mode transition to FUNC_RET mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enable by P-channel protocol. The possible values are following." "0,1" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x404++0x3 line.long 0x0 "L3CTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x444++0x3 line.long 0x0 "L3CTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x484++0x3 line.long 0x0 "L3CTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x4C4++0x3 line.long 0x0 "L3CTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register is used for L3 cache partial power down/up." rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "L3STS,Indicates current L3 cache partial power down/up status. Permitted values are following." "?,1: 1/4 of L3 cache is powered on,?,?,?,?,?,?" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 9. "L3DENY,Indicates whether L3 cache partial power down/up request is denied. Permitted values are following." "0: request is not denied,1: request is denied" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 8. "L3ACCEPT,Indicates whether L3 cache partial power down/up request is accepted. Permitted values are following." "0: request is not accepted,1: request is accepted" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 4. "L3REQ,L3 cache partial power down/up request. The possible values are following." "0: L3 cache partial power down/up is not requested,1: L3 cache partial power down/up is requested" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" newline bitfld.long 0x0 0.--2. "L3CTRL,L3 cache partial power down/up control. The possible values are following." "0: All L3 cache is power-off or Cluster’s power..,1: 1/4 of L3 cache is power-on,?,?,?,?,?,?" group.long 0x40C++0x3 line.long 0x0 "FSMLOCKRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x44C++0x3 line.long 0x0 "FSMLOCKRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x48C++0x3 line.long 0x0 "FSMLOCKRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x4CC++0x3 line.long 0x0 "FSMLOCKRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 cluster." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are:" "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x410++0x3 line.long 0x0 "PDENYSTSRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x450++0x3 line.long 0x0 "PDENYSTSRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x490++0x3 line.long 0x0 "PDENYSTSRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x4D0++0x3 line.long 0x0 "PDENYSTSRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether a denied state transition has occurred." bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 22. "DNY_OFF_ON,Indicates whether a denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 21. "DNY_ON_OFF,Indicates whether a denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 20. "DNY_ON_FUNC,Indicates whether a denied state transition has occurred by power mode transition from ON mode to FUNC_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 19. "DNY_FUNC_ON,Indicates whether a denied state transition has occurred by power mode transition from FUNC_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 18. "DNY_ON_MEM,Indicates whether a denied state transition has occurred by power mode transition from ON mode to MEM_RET mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 17. "DNY_MEM_ON,Indicates whether a denied state transition has occurred by power mode transition from MEM_RET mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 16. "DNY_ON_L3CHG,Indicates whether a denied state transition has occurred by L3 cache partial power mode control. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x414++0x3 line.long 0x0 "PDENYINTRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x454++0x3 line.long 0x0 "PDENYINTRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x494++0x3 line.long 0x0 "PDENYINTRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x4D4++0x3 line.long 0x0 "PDENYINTRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 22. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 21. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 20. "INT_ON_FUNC,Issuing interrupt enable by DNY_ON_FUNC. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 19. "INT_FUNC_ON,Issuing interrupt enable by DNY_FUNC_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 18. "INT_ON_MEM,Issuing interrupt enable by DNY_ON_MEM. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 17. "INT_MEM_ON,Issuing interrupt enable by DNY_MEM_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 16. "INT_ON_L3CHG,Issuing interrupt enable by DNY_ON_L3CHG. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" rgroup.long 0x418++0x3 line.long 0x0 "FSMSTSRCL0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x458++0x3 line.long 0x0 "FSMSTSRCL1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x498++0x3 line.long 0x0 "FSMSTSRCL2,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." rgroup.long 0x4D8++0x3 line.long 0x0 "FSMSTSRCL3,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 cluster FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of Cortex-A76 cluster FSM. Permitted values are following." group.long 0x41C++0x3 line.long 0x0 "G2GPRCL0,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x45C++0x3 line.long 0x0 "G2GPRCL1,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x49C++0x3 line.long 0x0 "G2GPRCL2,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x4DC++0x3 line.long 0x0 "G2GPRCL3,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x420++0x3 line.long 0x0 "SAFECTRLCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x460++0x3 line.long 0x0 "SAFECTRLCL1,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x4A0++0x3 line.long 0x0 "SAFECTRLCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." group.long 0x4E0++0x3 line.long 0x0 "SAFECTRLCL3,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 cluster." bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 10. "A2_RTT_MRET,A2 RuntimeTEST using Pseudo OFF mode enable. The possible values are following." "0: A2 RuntimeTEST using Pseudo OFF mode is disabled,1: A2 RuntimeTEST using Pseudo OFF mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 9. "A2_RTT_POFF,A2 RuntimeTEST using MEM_RET mode enable. The possible values are following." "0: A2 RuntimeTEST using MEM_RET mode is disabled,1: A2 RuntimeTEST using MEM_RET mode is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 clusters are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76..,1: RuntimeTEST is enabled before Cortex-A76.." rgroup.long 0x424++0x3 line.long 0x0 "DCLSENCL0,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether Cortex-A76 cluster is in DCLS mode." bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" rgroup.long 0x4A4++0x3 line.long 0x0 "DCLSENCL2,This register is a 32-bit readable register. This register belongs to Group1. This register indicates whether Cortex-A76 cluster is in DCLS mode." bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" newline bitfld.long 0x0 0. "DCLSEN,Indicates Cortex-A76 cluster is DCLS mode. Permitted values are following." "0: Cortex-A76 cluster is not in DCLS mode,1: Cortex-A76 cluster is in DCLS mode" group.long 0x428++0x3 line.long 0x0 "DCLSCMPENCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls a DCLS comparator for Cortex-A76 cluster." bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" group.long 0x4A8++0x3 line.long 0x0 "DCLSCMPENCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls a DCLS comparator for Cortex-A76 cluster." bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" newline bitfld.long 0x0 0. "DCLSCMPEN,DCLS comparator enable. The possible values are following." "0: DCLS comparator is disabled,1: DCLS comparator is enabled" group.long 0x42C++0x3 line.long 0x0 "GCNTERRENCL0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-A76 cluster." bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" group.long 0x4AC++0x3 line.long 0x0 "GCNTERRENCL2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety mechanism between Generic Counter and Cortex-A76 cluster." bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" newline bitfld.long 0x0 0. "GCNTERREN,Generic Counter error detection enable. The possible values are following." "0: Error detection is disabled,1: Error detection is enabled" group.long 0x800++0x3 line.long 0x0 "PWRCTRLC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x840++0x3 line.long 0x0 "PWRCTRLC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xA00++0x3 line.long 0x0 "PWRCTRLC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xA40++0x3 line.long 0x0 "PWRCTRLC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xC00++0x3 line.long 0x0 "PWRCTRLC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xC40++0x3 line.long 0x0 "PWRCTRLC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xE00++0x3 line.long 0x0 "PWRCTRLC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0xE40++0x3 line.long 0x0 "PWRCTRLC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls power management for Cortex-A76 core x." bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 18. "PCHPDNEMUEN,OFF_EMU mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to OFF_EMU mode is disabled,1: Power mode transition to OFF_EMU mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 17. "PCHPDNEN,OFF mode transition enables by P-channel protocol. The possible values are following" "0: Power mode transition to OFF mode is disabled,1: Power mode transition to OFF mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 16. "PCHWUPEN,ON mode transition enable by P-channel protocol. The possible values are following." "0: Power mode transition to ON mode is disabled,1: Power mode transition to ON mode is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 5. "DWUP_EN,This bit enables wakeup request from Debugger. The possible values are following." "0: Wakeup request from Debugger is disabled,1: Wakeup request from Debugger is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 4. "IWUP_EN,This bit enables wakeup request from INTC-AP. The possible values are following." "0: Wakeup request from INTC-AP is disabled,1: Wakeup request from INTC-AP is enabled" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" newline bitfld.long 0x0 0. "WUP_REQ,Wake up request. The possible values are following." "0: Power on is not requested,1: Power on is requested" group.long 0x80C++0x3 line.long 0x0 "FSMLOCKRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x84C++0x3 line.long 0x0 "FSMLOCKRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xA0C++0x3 line.long 0x0 "FSMLOCKRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xA4C++0x3 line.long 0x0 "FSMLOCKRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xC0C++0x3 line.long 0x0 "FSMLOCKRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xC4C++0x3 line.long 0x0 "FSMLOCKRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xE0C++0x3 line.long 0x0 "FSMLOCKRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0xE4C++0x3 line.long 0x0 "FSMLOCKRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls a safety mechanism of FSM for Coretex-A76 core." hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline hexmask.long.word 0x0 16.--31. 1. "CNT_VALUE,Indicates count value for FSM deadlock error." newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 15. "PRTCL_ERR,This is error flag bit and it indicates whether P-channel protocol error has occurred. Permitted values are following." "0: P-channel protocol error has not occurred,1: P-channel protocol error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 14. "CRPT_ERR,This is error flag bit and it indicates whether P-channel corruption error has occurred. Permitted values are following." "0: P-channel corruption error has not occurred,1: P-channel corruption error has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline rbitfld.long 0x0 12. "LOCK_ERR,This is error flag bit and it indicates whether FSM deadlock has occurred. Permitted values are following." "0: FSM dead lock has not occurred,1: FSM dead lock has occurred" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 11. "PRTCL_EN,P-channel protocol error enable. The possible values are following." "0: P-channel protocol error is disabled,1: P-channel protocol error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 10. "CRPT_EN,P-channel corruption error enable. The possible values are following." "0: P-channel corruption error is disabled,1: P-channel corruption error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 8. "LOCK_EN,FSM deadlock error enable. The possible values are following." "0: FSM deadlock error is disabled,1: FSM deadlock error is enabled" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 7. "PRTCL_EIJT,P-channel protocol error injection. The possible values are following." "0: P-channel protocol error injection is disabled,1: P-channel protocol error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 6. "CRPT_EIJT,P-channel corruption error injection. The possible values are following." "0: P-channel corruption error injection is disabled,1: P-channel corruption error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline bitfld.long 0x0 4. "LOCK_EIJT,FSM deadlock error injection. The possible values are following." "0: FSM deadlock error injection is disabled,1: FSM deadlock error injection is active" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 3. "PRTCL_CLR,P-channel protocol error clear. If 1 is written PRTCL_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 2. "CRPT_CLR,P-channel corruption error clear. If 1 is written CRPT_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" newline eventfld.long 0x0 0. "LOCK_CLR,FSM deadlock error clear. If 1 is written LOCK_ERR bit is cleared to 0." "0,1" group.long 0x810++0x3 line.long 0x0 "PDENYSTSRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x850++0x3 line.long 0x0 "PDENYSTSRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xA10++0x3 line.long 0x0 "PDENYSTSRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xA50++0x3 line.long 0x0 "PDENYSTSRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xC10++0x3 line.long 0x0 "PDENYSTSRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xC50++0x3 line.long 0x0 "PDENYSTSRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xE10++0x3 line.long 0x0 "PDENYSTSRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0xE50++0x3 line.long 0x0 "PDENYSTSRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates whether denied state transition has occurred." bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 7. "DNY_OFF_ON,Indicates whether denied state transition has occurred by power mode transition from OFF mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 6. "DNY_ON_OFF,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 3. "DNY_ON_EMU,Indicates whether denied state transition has occurred by power mode transition from ON mode to OFF_EMU mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 2. "DNY_EMU_ON,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to ON mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" newline bitfld.long 0x0 1. "DNY_EMU_OFF,Indicates whether denied state transition has occurred by power mode transition from OFF_EMU mode to OFF mode. Permitted values are following." "0: A denied state transition has not occurred,1: A denied state transition has occurred" group.long 0x814++0x3 line.long 0x0 "PDENYINTRC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0x854++0x3 line.long 0x0 "PDENYINTRC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xA14++0x3 line.long 0x0 "PDENYINTRC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xA54++0x3 line.long 0x0 "PDENYINTRC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xC14++0x3 line.long 0x0 "PDENYINTRC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xC54++0x3 line.long 0x0 "PDENYINTRC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xE14++0x3 line.long 0x0 "PDENYINTRC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" group.long 0xE54++0x3 line.long 0x0 "PDENYINTRC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register controls whether issuing interrupt or not when a denied state transition has occurred." bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 7. "INT_OFF_ON,Issuing interrupt enable by DNY_OFF_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 6. "INT_ON_OFF,Issuing interrupt enable by DNY_ON_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 3. "INT_ON_EMU,Issuing interrupt enable by DNY_ON_EMU. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 2. "INT_EMU_ON,Issuing interrupt enable by DNY_EMU_ON. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" newline bitfld.long 0x0 1. "INT_EMU_OFF,Issuing interrupt enable by DNY_EMU_OFF. The possible values are following." "0: Issuing interrupt is disabled,1: Issuing interrupt is enabled" rgroup.long 0x818++0x3 line.long 0x0 "FSMSTSRC0,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0x858++0x3 line.long 0x0 "FSMSTSRC1,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xA18++0x3 line.long 0x0 "FSMSTSRC2,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xA58++0x3 line.long 0x0 "FSMSTSRC3,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xC18++0x3 line.long 0x0 "FSMSTSRC4,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xC58++0x3 line.long 0x0 "FSMSTSRC5,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xE18++0x3 line.long 0x0 "FSMSTSRC6,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." rgroup.long 0xE58++0x3 line.long 0x0 "FSMSTSRC7,This register is a 32-bit readable register. This register belongs to Group2. This register indicates Cortex-A76 core FSM state." hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." newline hexmask.long.byte 0x0 0.--7. 1. "STATE,Indicate current state of A3 FSM. The permitted values are following." group.long 0x81C++0x3 line.long 0x0 "G2GPRC0,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x85C++0x3 line.long 0x0 "G2GPRC1,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xA1C++0x3 line.long 0x0 "G2GPRC2,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xA5C++0x3 line.long 0x0 "G2GPRC3,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xC1C++0x3 line.long 0x0 "G2GPRC4,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xC5C++0x3 line.long 0x0 "G2GPRC5,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xE1C++0x3 line.long 0x0 "G2GPRC6,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0xE5C++0x3 line.long 0x0 "G2GPRC7,This register is a 32-bit readable/writable register. This register belongs to Group2." hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." newline hexmask.long 0x0 0.--31. 1. "GPR0,This fields are allowed to write any values and they don’t affect module operation." group.long 0x820++0x3 line.long 0x0 "SAFECTRLC0,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0x860++0x3 line.long 0x0 "SAFECTRLC1,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xA20++0x3 line.long 0x0 "SAFECTRLC2,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xA60++0x3 line.long 0x0 "SAFECTRLC3,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xC20++0x3 line.long 0x0 "SAFECTRLC4,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xC60++0x3 line.long 0x0 "SAFECTRLC5,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xE20++0x3 line.long 0x0 "SAFECTRLC6,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0xE60++0x3 line.long 0x0 "SAFECTRLC7,This register is a 32-bit readable/writable register. This register belongs to Group1. This register controls safety related function for Cortex-A76 core." bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 4. "A1_RTT,A1 RuntimeTEST enable. The possible values are following." "0: A1 RuntimeTEST is disabled,1: A1 RuntimeTEST is enabled" newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." newline bitfld.long 0x0 1. "WUP_RTT_REQ,RuntimeTEST enable before Cortex-A76 cores are booted. The possible values are following." "0: RuntimeTEST is disabled before Cortex-A76 cores..,1: RuntimeTEST is enabled before Cortex-A76 cores.." group.long 0x830++0x3 line.long 0x0 "RVBARLC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0x870++0x3 line.long 0x0 "RVBARLC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xA30++0x3 line.long 0x0 "RVBARLC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xA70++0x3 line.long 0x0 "RVBARLC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xC30++0x3 line.long 0x0 "RVBARLC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xC70++0x3 line.long 0x0 "RVBARLC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xE30++0x3 line.long 0x0 "RVBARLC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0xE70++0x3 line.long 0x0 "RVBARLC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBAR,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." group.long 0x834++0x3 line.long 0x0 "RVBARHC0,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0x874++0x3 line.long 0x0 "RVBARHC1,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xA34++0x3 line.long 0x0 "RVBARHC2,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xA74++0x3 line.long 0x0 "RVBARHC3,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xC34++0x3 line.long 0x0 "RVBARHC4,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xC74++0x3 line.long 0x0 "RVBARHC5,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xE34++0x3 line.long 0x0 "RVBARHC6,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0xE74++0x3 line.long 0x0 "RVBARHC7,This register is a 32-bit readable/writable register. This register belongs to Group2. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBAR,These bits indicate RVBARADDR[43:32]. It is defined in DSU TRM." group.long 0x838++0x3 line.long 0x0 "RVBARPLC0,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0x878++0x3 line.long 0x0 "RVBARPLC1,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xA38++0x3 line.long 0x0 "RVBARPLC2,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xA78++0x3 line.long 0x0 "RVBARPLC3,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xC38++0x3 line.long 0x0 "RVBARPLC4,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xC78++0x3 line.long 0x0 "RVBARPLC5,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xE38++0x3 line.long 0x0 "RVBARPLC6,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0xE78++0x3 line.long 0x0 "RVBARPLC7,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline hexmask.long 0x0 2.--31. 1. "RVBARP,These bits indicate RVBARADDR[31:2]. It is defined in DSU TRM." newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" newline bitfld.long 0x0 0. "VLD,RVBARP valid. The possible values are following." "0: RVBAR is used as RVBARADDR,1: RVBARP is used as RVBARADDR" group.long 0x83C++0x3 line.long 0x0 "RVBARPHC0,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0x87C++0x3 line.long 0x0 "RVBARPHC1,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xA3C++0x3 line.long 0x0 "RVBARPHC2,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xA7C++0x3 line.long 0x0 "RVBARPHC3,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xC3C++0x3 line.long 0x0 "RVBARPHC4,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xC7C++0x3 line.long 0x0 "RVBARPHC5,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xE3C++0x3 line.long 0x0 "RVBARPHC6,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." group.long 0xE7C++0x3 line.long 0x0 "RVBARPHC7,This register is a 32-bit readable/writable register. This register belongs to Group0. This register indicates reset vector base address." hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." newline hexmask.long.word 0x0 0.--11. 1. "RVBARP,These bits indicate RVBARADDR[43:31]. It is defined in DSU TRM." tree.end tree.end tree "APPA" base ad:0xFFF00000 rgroup.long 0x44++0x3 line.long 0x0 "PRR,Product Register" bitfld.long 0x0 29.--31. "CA76_11EN,Cortex-A76 Cluster 3 State" "0: The product has Cortex-A76 CPU6,1: The product does not have Cortex-A76 CPU6,?,?,?,?,?,?" bitfld.long 0x0 26.--28. "CA76_10EN,Cortex-A76 Cluster 2 State" "0: The product has Cortex-A76 CPU4,1: The product does not have Cortex-A76 CPU4,?,?,?,?,?,?" newline bitfld.long 0x0 23.--25. "CA76_01EN,Cortex-A76 Cluster 1 State" "0: The product has Cortex-A76 CPU2,1: The product does not have Cortex-A76 CPU2,?,?,?,?,?,?" bitfld.long 0x0 20.--22. "CA76_00EN,Cortex-A76 Cluster 0 State" "0: The product has Cortex-A76 CPU0,1: The product does not have Cortex-A76 CPU0,?,?,?,?,?,?" newline bitfld.long 0x0 19. "CR52EN,Cortex-R52" "0: The product has a Cortex-R52 CPU,1: The product does not have Cortex-R52 CPU" hexmask.long.byte 0x0 8.--15. 1. "PRODUCT,Product ID Number" tree.end tree "AXI_BUS" base ad:0x0 group.long 0xFFFFFFFFFF881004++0x13 line.long 0x0 "FBABUSIR0,Region ID Master Setting Register for FBABUSIR 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "FBABUSIR1,Region ID Master Setting Register for FBABUSIR 1" hexmask.long.byte 0x4 0.--3. 1. "RGID" line.long 0x8 "FBABUSIR2,Region ID Master Setting Register for FBABUSIR 2" hexmask.long.byte 0x8 0.--3. 1. "RGID" line.long 0xC "FBABUSIR3,Region ID Master Setting Register for FBABUSIR 3" hexmask.long.byte 0xC 0.--3. 1. "RGID" line.long 0x10 "FBABUSIR4,Region ID Master Setting Register for FBABUSIR 4" hexmask.long.byte 0x10 0.--3. 1. "RGID" group.long 0xFFFFFFFFFF881024++0xF line.long 0x0 "IMPD0,Region ID Master Setting Register for IMPD 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "RADSP00,Region ID Master Setting Register for RADSP 00" hexmask.long.byte 0x4 0.--3. 1. "RGID" line.long 0x8 "RADSP01,Region ID Master Setting Register for RADSP 01" hexmask.long.byte 0x8 0.--3. 1. "RGID" line.long 0xC "RADSP10,Region ID Master Setting Register for RADSP 10" hexmask.long.byte 0xC 0.--3. 1. "RGID" group.long 0xFFFFFFFFFF88104C++0x3 line.long 0x0 "RADSP11,Region ID Master Setting Register for RADSP 11" hexmask.long.byte 0x0 0.--3. 1. "RGID" group.long 0xFFFFFFFFFD811004++0x7 line.long 0x0 "FBAPVD0,Region ID Master Setting Register for FBAPVD 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "FBAPVD1,Region ID Master Setting Register for FBAPVD 1" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFFD811010++0x7 line.long 0x0 "FBAPVD2,Region ID Master Setting Register for FBAPVD 2" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "RGX0,Region ID Master Setting Register for RGX 0" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFE6621004++0x3 line.long 0x0 "CR0,Region ID Master Setting Register for CR 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" group.long 0xFFFFFFFFE662100C++0x7 line.long 0x0 "DCLS_ICUMX,Region ID Master Setting Register for DCLS_ICUMX" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "ICUMX,Region ID Master Setting Register for ICUMX" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFFFC41018++0x7 line.long 0x0 "CR52SS,Region ID Master Setting Register for CR52SS" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "CSD,Region ID Master Setting Register for CSD" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFFFC41024++0x3 line.long 0x0 "INTAP0,Region ID Master Setting Register for INTAP 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" group.long 0xFFFFFFFFFF861018++0x7 line.long 0x0 "FBABUSTOP0,Region ID Master Setting Register for FBABUSTOP 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "FBABUSTOP1,Region ID Master Setting Register for FBABUSTOP 1" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFE7751010++0x7 line.long 0x0 "FRAY,Region ID Master Setting Register for FRAY" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "IPC,Region ID Master Setting Register for IPC" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFE7751020++0x3 line.long 0x0 "SDHI0,Region ID Master Setting Register for SDHI 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" group.long 0xFFFFFFFFE6581000++0x27 line.long 0x0 "PCI0,Region ID Master Setting Register for PCI 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "PCI1,Region ID Master Setting Register for PCI 1" hexmask.long.byte 0x4 0.--3. 1. "RGID" line.long 0x8 "PCI2,Region ID Master Setting Register for PCI 2" hexmask.long.byte 0x8 0.--3. 1. "RGID" line.long 0xC "PCI3,Region ID Master Setting Register for PCI 3" hexmask.long.byte 0xC 0.--3. 1. "RGID" line.long 0x10 "AVB0,Region ID Master Setting Register for AVB 0" hexmask.long.byte 0x10 0.--3. 1. "RGID" line.long 0x14 "AVB1,Region ID Master Setting Register for AVB 1" hexmask.long.byte 0x14 0.--3. 1. "RGID" line.long 0x18 "AVB2,Region ID Master Setting Register for AVB 2" hexmask.long.byte 0x18 0.--3. 1. "RGID" line.long 0x1C "AVB3,Region ID Master Setting Register for AVB 3" hexmask.long.byte 0x1C 0.--3. 1. "RGID" line.long 0x20 "AVB4,Region ID Master Setting Register for AVB 4" hexmask.long.byte 0x20 0.--3. 1. "RGID" line.long 0x24 "AVB5,Region ID Master Setting Register for AVB 5" hexmask.long.byte 0x24 0.--3. 1. "RGID" group.long 0xFFFFFFFFFF811000++0xB line.long 0x0 "AXMM2AXSTM,Region ID Master Setting Register for AXMM2AXSTM" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "CSDE0,Region ID Master Setting Register for CSDE 0" hexmask.long.byte 0x4 0.--3. 1. "RGID" line.long 0x8 "CSDE1,Region ID Master Setting Register for CSDE 1" hexmask.long.byte 0x8 0.--3. 1. "RGID" group.long 0xFFFFFFFFFE681004++0x7 line.long 0x0 "FBABUSVC,Region ID Master Setting Register for FBABUSVC" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "FCPCS,Region ID Master Setting Register for FCPCS" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFFE681010++0x7 line.long 0x0 "IMR00,Region ID Master Setting Register for IMR 00" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "IMR01,Region ID Master Setting Register for IMR 01" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFFE681024++0x7 line.long 0x0 "IMR10,Region ID Master Setting Register for IMR 10" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "IMR11,Region ID Master Setting Register for IMR 11" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFFE681030++0x1B line.long 0x0 "IMR20,Region ID Master Setting Register for IMR 20" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "IMR21,Region ID Master Setting Register for IMR 21" hexmask.long.byte 0x4 0.--3. 1. "RGID" line.long 0x8 "IMR30,Region ID Master Setting Register for IMR 30" hexmask.long.byte 0x8 0.--3. 1. "RGID" line.long 0xC "IMR31,Region ID Master Setting Register for IMR 31" hexmask.long.byte 0xC 0.--3. 1. "RGID" line.long 0x10 "IMS0,Region ID Master Setting Register for IMS 0" hexmask.long.byte 0x10 0.--3. 1. "RGID" line.long 0x14 "IMS1,Region ID Master Setting Register for IMS 1" hexmask.long.byte 0x14 0.--3. 1. "RGID" line.long 0x18 "IV1ES,Region ID Master Setting Register for IV1ES" hexmask.long.byte 0x18 0.--3. 1. "RGID" group.long 0xFFFFFFFFFEBE1000++0x23 line.long 0x0 "DSITXLINK0,Region ID Master Setting Register for DSITXLINK 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "DSITXLINK1,Region ID Master Setting Register for DSITXLINK 1" hexmask.long.byte 0x4 0.--3. 1. "RGID" line.long 0x8 "FBABUSVIO,Region ID Master Setting Register for FBABUSVIO" hexmask.long.byte 0x8 0.--3. 1. "RGID" line.long 0xC "FCPVD0,Region ID Master Setting Register for FCPVD 0" hexmask.long.byte 0xC 0.--3. 1. "RGID" line.long 0x10 "FCPVD1,Region ID Master Setting Register for FCPVD 1" hexmask.long.byte 0x10 0.--3. 1. "RGID" line.long 0x14 "FCPVX0,Region ID Master Setting Register for FCPVX 0" hexmask.long.byte 0x14 0.--3. 1. "RGID" line.long 0x18 "FCPVX1,Region ID Master Setting Register for FCPVX 1" hexmask.long.byte 0x18 0.--3. 1. "RGID" line.long 0x1C "FCPVX2,Region ID Master Setting Register for FCPVX 2" hexmask.long.byte 0x1C 0.--3. 1. "RGID" line.long 0x20 "FCPVX3,Region ID Master Setting Register for FCPVX 3" hexmask.long.byte 0x20 0.--3. 1. "RGID" group.long 0xFFFFFFFFFEBF1000++0x2F line.long 0x0 "VIN0,Region ID Master Setting Register for VIN 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "VIN1,Region ID Master Setting Register for VIN 1" hexmask.long.byte 0x4 0.--3. 1. "RGID" line.long 0x8 "VIN2,Region ID Master Setting Register for VIN 2" hexmask.long.byte 0x8 0.--3. 1. "RGID" line.long 0xC "VIN3,Region ID Master Setting Register for VIN 3" hexmask.long.byte 0xC 0.--3. 1. "RGID" line.long 0x10 "ISP00,Region ID Master Setting Register for ISP 00" hexmask.long.byte 0x10 0.--3. 1. "RGID" line.long 0x14 "ISP01,Region ID Master Setting Register for ISP 01" hexmask.long.byte 0x14 0.--3. 1. "RGID" line.long 0x18 "ISP10,Region ID Master Setting Register for ISP 10" hexmask.long.byte 0x18 0.--3. 1. "RGID" line.long 0x1C "ISP11,Region ID Master Setting Register for ISP 11" hexmask.long.byte 0x1C 0.--3. 1. "RGID" line.long 0x20 "ISP20,Region ID Master Setting Register for ISP 20" hexmask.long.byte 0x20 0.--3. 1. "RGID" line.long 0x24 "ISP21,Region ID Master Setting Register for ISP 21" hexmask.long.byte 0x24 0.--3. 1. "RGID" line.long 0x28 "ISP30,Region ID Master Setting Register for ISP 30" hexmask.long.byte 0x28 0.--3. 1. "RGID" line.long 0x2C "ISP31,Region ID Master Setting Register for ISP 31" hexmask.long.byte 0x2C 0.--3. 1. "RGID" group.long 0xFFFFFFFFE7B11004++0x3 line.long 0x0 "FBABUSVIP0,Region ID Master Setting Register for FBABUSVIP 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" group.long 0xFFFFFFFFE7B1100C++0x7 line.long 0x0 "SMES0,Region ID Master Setting Register for SMES 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "SMPO0,Region ID Master Setting Register for SMPO 0" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFE7B11018++0x7 line.long 0x0 "SMPS0,Region ID Master Setting Register for SMPS 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "UMFL0,Region ID Master Setting Register for UMFL 0" hexmask.long.byte 0x4 0.--3. 1. "RGID" group.long 0xFFFFFFFFE7B41004++0xF line.long 0x0 "CLE0,Region ID Master Setting Register for CLE 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "CLE1,Region ID Master Setting Register for CLE 1" hexmask.long.byte 0x4 0.--3. 1. "RGID" line.long 0x8 "CLE2,Region ID Master Setting Register for CLE 2" hexmask.long.byte 0x8 0.--3. 1. "RGID" line.long 0xC "CLE3,Region ID Master Setting Register for CLE 3" hexmask.long.byte 0xC 0.--3. 1. "RGID" group.long 0xFFFFFFFFE7B41020++0xB line.long 0x0 "DISP0,Region ID Master Setting Register for DISP 0" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "DISP1,Region ID Master Setting Register for DISP 1" hexmask.long.byte 0x4 0.--3. 1. "RGID" line.long 0x8 "FBABUSVIP1,Region ID Master Setting Register for FBABUSVIP 1" hexmask.long.byte 0x8 0.--3. 1. "RGID" group.long 0xFFFFFFFFE7B41034++0xF line.long 0x0 "SMES1,Region ID Master Setting Register for SMES 1" hexmask.long.byte 0x0 0.--3. 1. "RGID" line.long 0x4 "SMPO1,Region ID Master Setting Register for SMPO 1" hexmask.long.byte 0x4 0.--3. 1. "RGID" line.long 0x8 "SMPS1,Region ID Master Setting Register for SMPS 1" hexmask.long.byte 0x8 0.--3. 1. "RGID" line.long 0xC "UMFL1,Region ID Master Setting Register for UMFL 1" hexmask.long.byte 0xC 0.--3. 1. "RGID" group.long 0xFFFFFFFFFFC41800++0xFF line.long 0x0 "RGIDMEN[RTDM[0]_CH[0]],Region ID Master Enable Setting Register for RTDM0_CH 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "RGIDMEN[RTDM[0]_CH[1]],Region ID Master Enable Setting Register for RTDM0_CH 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "RGIDMEN[RTDM[0]_CH[2]],Region ID Master Enable Setting Register for RTDM0_CH 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "RGIDMEN[RTDM[0]_CH[3]],Region ID Master Enable Setting Register for RTDM0_CH 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "RGIDMEN[RTDM[0]_CH[4]],Region ID Master Enable Setting Register for RTDM0_CH 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "RGIDMEN[RTDM[0]_CH[5]],Region ID Master Enable Setting Register for RTDM0_CH 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "RGIDMEN[RTDM[0]_CH[6]],Region ID Master Enable Setting Register for RTDM0_CH 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "RGIDMEN[RTDM[0]_CH[7]],Region ID Master Enable Setting Register for RTDM0_CH 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "RGIDMEN[RTDM[0]_CH[8]],Region ID Master Enable Setting Register for RTDM0_CH 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "RGIDMEN[RTDM[0]_CH[9]],Region ID Master Enable Setting Register for RTDM0_CH 9" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "RGIDMEN[RTDM[0]_CH[10]],Region ID Master Enable Setting Register for RTDM0_CH 10" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "RGIDMEN[RTDM[0]_CH[11]],Region ID Master Enable Setting Register for RTDM0_CH 11" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "RGIDMEN[RTDM[0]_CH[12]],Region ID Master Enable Setting Register for RTDM0_CH 12" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "RGIDMEN[RTDM[0]_CH[13]],Region ID Master Enable Setting Register for RTDM0_CH 13" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "RGIDMEN[RTDM[0]_CH[14]],Region ID Master Enable Setting Register for RTDM0_CH 14" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "RGIDMEN[RTDM[0]_CH[15]],Region ID Master Enable Setting Register for RTDM0_CH 15" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "RGIDMEN[RTDM[1]_CH[0]],Region ID Master Enable Setting Register for RTDM1_CH 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "RGIDMEN[RTDM[1]_CH[1]],Region ID Master Enable Setting Register for RTDM1_CH 1" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "RGIDMEN[RTDM[1]_CH[2]],Region ID Master Enable Setting Register for RTDM1_CH 2" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "RGIDMEN[RTDM[1]_CH[3]],Region ID Master Enable Setting Register for RTDM1_CH 3" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "RGIDMEN[RTDM[1]_CH[4]],Region ID Master Enable Setting Register for RTDM1_CH 4" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "RGIDMEN[RTDM[1]_CH[5]],Region ID Master Enable Setting Register for RTDM1_CH 5" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "RGIDMEN[RTDM[1]_CH[6]],Region ID Master Enable Setting Register for RTDM1_CH 6" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "RGIDMEN[RTDM[1]_CH[7]],Region ID Master Enable Setting Register for RTDM1_CH 7" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "RGIDMEN[RTDM[1]_CH[8]],Region ID Master Enable Setting Register for RTDM1_CH 8" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "RGIDMEN[RTDM[1]_CH[9]],Region ID Master Enable Setting Register for RTDM1_CH 9" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "RGIDMEN[RTDM[1]_CH[10]],Region ID Master Enable Setting Register for RTDM1_CH 10" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "RGIDMEN[RTDM[1]_CH[11]],Region ID Master Enable Setting Register for RTDM1_CH 11" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "RGIDMEN[RTDM[1]_CH[12]],Region ID Master Enable Setting Register for RTDM1_CH 12" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "RGIDMEN[RTDM[1]_CH[13]],Region ID Master Enable Setting Register for RTDM1_CH 13" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "RGIDMEN[RTDM[1]_CH[14]],Region ID Master Enable Setting Register for RTDM1_CH 14" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "RGIDMEN[RTDM[1]_CH[15]],Region ID Master Enable Setting Register for RTDM1_CH 15" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "RGIDMEN[RTDM[2]_CH[0]],Region ID Master Enable Setting Register for RTDM2_CH 0" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "RGIDMEN[RTDM[2]_CH[1]],Region ID Master Enable Setting Register for RTDM2_CH 1" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "RGIDMEN[RTDM[2]_CH[2]],Region ID Master Enable Setting Register for RTDM2_CH 2" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "RGIDMEN[RTDM[2]_CH[3]],Region ID Master Enable Setting Register for RTDM2_CH 3" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "RGIDMEN[RTDM[2]_CH[4]],Region ID Master Enable Setting Register for RTDM2_CH 4" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "RGIDMEN[RTDM[2]_CH[5]],Region ID Master Enable Setting Register for RTDM2_CH 5" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "RGIDMEN[RTDM[2]_CH[6]],Region ID Master Enable Setting Register for RTDM2_CH 6" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "RGIDMEN[RTDM[2]_CH[7]],Region ID Master Enable Setting Register for RTDM2_CH 7" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "RGIDMEN[RTDM[2]_CH[8]],Region ID Master Enable Setting Register for RTDM2_CH 8" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "RGIDMEN[RTDM[2]_CH[9]],Region ID Master Enable Setting Register for RTDM2_CH 9" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "RGIDMEN[RTDM[2]_CH[10]],Region ID Master Enable Setting Register for RTDM2_CH 10" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "RGIDMEN[RTDM[2]_CH[11]],Region ID Master Enable Setting Register for RTDM2_CH 11" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "RGIDMEN[RTDM[2]_CH[12]],Region ID Master Enable Setting Register for RTDM2_CH 12" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "RGIDMEN[RTDM[2]_CH[13]],Region ID Master Enable Setting Register for RTDM2_CH 13" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "RGIDMEN[RTDM[2]_CH[14]],Region ID Master Enable Setting Register for RTDM2_CH 14" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "RGIDMEN[RTDM[2]_CH[15]],Region ID Master Enable Setting Register for RTDM2_CH 15" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "RGIDMEN[RTDM[3]_CH[0]],Region ID Master Enable Setting Register for RTDM3_CH 0" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "RGIDMEN[RTDM[3]_CH[1]],Region ID Master Enable Setting Register for RTDM3_CH 1" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "RGIDMEN[RTDM[3]_CH[2]],Region ID Master Enable Setting Register for RTDM3_CH 2" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "RGIDMEN[RTDM[3]_CH[3]],Region ID Master Enable Setting Register for RTDM3_CH 3" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "RGIDMEN[RTDM[3]_CH[4]],Region ID Master Enable Setting Register for RTDM3_CH 4" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "RGIDMEN[RTDM[3]_CH[5]],Region ID Master Enable Setting Register for RTDM3_CH 5" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "RGIDMEN[RTDM[3]_CH[6]],Region ID Master Enable Setting Register for RTDM3_CH 6" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" line.long 0xDC "RGIDMEN[RTDM[3]_CH[7]],Region ID Master Enable Setting Register for RTDM3_CH 7" hexmask.long.word 0xDC 0.--15. 1. "RGIDEN" line.long 0xE0 "RGIDMEN[RTDM[3]_CH[8]],Region ID Master Enable Setting Register for RTDM3_CH 8" hexmask.long.word 0xE0 0.--15. 1. "RGIDEN" line.long 0xE4 "RGIDMEN[RTDM[3]_CH[9]],Region ID Master Enable Setting Register for RTDM3_CH 9" hexmask.long.word 0xE4 0.--15. 1. "RGIDEN" line.long 0xE8 "RGIDMEN[RTDM[3]_CH[10]],Region ID Master Enable Setting Register for RTDM3_CH 10" hexmask.long.word 0xE8 0.--15. 1. "RGIDEN" line.long 0xEC "RGIDMEN[RTDM[3]_CH[11]],Region ID Master Enable Setting Register for RTDM3_CH 11" hexmask.long.word 0xEC 0.--15. 1. "RGIDEN" line.long 0xF0 "RGIDMEN[RTDM[3]_CH[12]],Region ID Master Enable Setting Register for RTDM3_CH 12" hexmask.long.word 0xF0 0.--15. 1. "RGIDEN" line.long 0xF4 "RGIDMEN[RTDM[3]_CH[13]],Region ID Master Enable Setting Register for RTDM3_CH 13" hexmask.long.word 0xF4 0.--15. 1. "RGIDEN" line.long 0xF8 "RGIDMEN[RTDM[3]_CH[14]],Region ID Master Enable Setting Register for RTDM3_CH 14" hexmask.long.word 0xF8 0.--15. 1. "RGIDEN" line.long 0xFC "RGIDMEN[RTDM[3]_CH[15]],Region ID Master Enable Setting Register for RTDM3_CH 15" hexmask.long.word 0xFC 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7751840++0x7F line.long 0x0 "RGIDMEN[SYDM[1]_CH[0]],Region ID Master Enable Setting Register for SYDM1_CH 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "RGIDMEN[SYDM[1]_CH[1]],Region ID Master Enable Setting Register for SYDM1_CH 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "RGIDMEN[SYDM[1]_CH[2]],Region ID Master Enable Setting Register for SYDM1_CH 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "RGIDMEN[SYDM[1]_CH[3]],Region ID Master Enable Setting Register for SYDM1_CH 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "RGIDMEN[SYDM[1]_CH[4]],Region ID Master Enable Setting Register for SYDM1_CH 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "RGIDMEN[SYDM[1]_CH[5]],Region ID Master Enable Setting Register for SYDM1_CH 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "RGIDMEN[SYDM[1]_CH[6]],Region ID Master Enable Setting Register for SYDM1_CH 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "RGIDMEN[SYDM[1]_CH[7]],Region ID Master Enable Setting Register for SYDM1_CH 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "RGIDMEN[SYDM[1]_CH[8]],Region ID Master Enable Setting Register for SYDM1_CH 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "RGIDMEN[SYDM[1]_CH[9]],Region ID Master Enable Setting Register for SYDM1_CH 9" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "RGIDMEN[SYDM[1]_CH[10]],Region ID Master Enable Setting Register for SYDM1_CH 10" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "RGIDMEN[SYDM[1]_CH[11]],Region ID Master Enable Setting Register for SYDM1_CH 11" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "RGIDMEN[SYDM[1]_CH[12]],Region ID Master Enable Setting Register for SYDM1_CH 12" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "RGIDMEN[SYDM[1]_CH[13]],Region ID Master Enable Setting Register for SYDM1_CH 13" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "RGIDMEN[SYDM[1]_CH[14]],Region ID Master Enable Setting Register for SYDM1_CH 14" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "RGIDMEN[SYDM[1]_CH[15]],Region ID Master Enable Setting Register for SYDM1_CH 15" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "RGIDMEN[SYDM[2]_CH[0]],Region ID Master Enable Setting Register for SYDM2_CH 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "RGIDMEN[SYDM[2]_CH[1]],Region ID Master Enable Setting Register for SYDM2_CH 1" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "RGIDMEN[SYDM[2]_CH[2]],Region ID Master Enable Setting Register for SYDM2_CH 2" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "RGIDMEN[SYDM[2]_CH[3]],Region ID Master Enable Setting Register for SYDM2_CH 3" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "RGIDMEN[SYDM[2]_CH[4]],Region ID Master Enable Setting Register for SYDM2_CH 4" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "RGIDMEN[SYDM[2]_CH[5]],Region ID Master Enable Setting Register for SYDM2_CH 5" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "RGIDMEN[SYDM[2]_CH[6]],Region ID Master Enable Setting Register for SYDM2_CH 6" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "RGIDMEN[SYDM[2]_CH[7]],Region ID Master Enable Setting Register for SYDM2_CH 7" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "RGIDMEN[SYDM[2]_CH[8]],Region ID Master Enable Setting Register for SYDM2_CH 8" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "RGIDMEN[SYDM[2]_CH[9]],Region ID Master Enable Setting Register for SYDM2_CH 9" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "RGIDMEN[SYDM[2]_CH[10]],Region ID Master Enable Setting Register for SYDM2_CH 10" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "RGIDMEN[SYDM[2]_CH[11]],Region ID Master Enable Setting Register for SYDM2_CH 11" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "RGIDMEN[SYDM[2]_CH[12]],Region ID Master Enable Setting Register for SYDM2_CH 12" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "RGIDMEN[SYDM[2]_CH[13]],Region ID Master Enable Setting Register for SYDM2_CH 13" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "RGIDMEN[SYDM[2]_CH[14]],Region ID Master Enable Setting Register for SYDM2_CH 14" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "RGIDMEN[SYDM[2]_CH[15]],Region ID Master Enable Setting Register for SYDM2_CH 15" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC82000++0x67 line.long 0x0 "ARMGC0,Region ID Read Enable Register for ARMGC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARMGC1,Region ID Read Enable Register for ARMGC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARMGC2,Region ID Read Enable Register for ARMGC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARRT00,Region ID Read Enable Register for ARRT 00" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARRT01,Region ID Read Enable Register for ARRT 01" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARRT02,Region ID Read Enable Register for ARRT 02" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARRT03,Region ID Read Enable Register for ARRT 03" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARRT04,Region ID Read Enable Register for ARRT 04" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARRT05,Region ID Read Enable Register for ARRT 05" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARRT06,Region ID Read Enable Register for ARRT 06" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ARRT07,Region ID Read Enable Register for ARRT 07" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ARRT08,Region ID Read Enable Register for ARRT 08" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "LIFEC0,Region ID Read Enable Register for LIFEC 0" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "SWDT,Region ID Read Enable Register for SWDT" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "TMU0,Region ID Read Enable Register for TMU 0" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "WDT,Region ID Read Enable Register for WDT" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "WWDT0,Region ID Read Enable Register for WWDT 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "WWDT1,Region ID Read Enable Register for WWDT 1" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "WWDT2,Region ID Read Enable Register for WWDT 2" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "WWDT3,Region ID Read Enable Register for WWDT 3" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "WWDT4,Region ID Read Enable Register for WWDT 4" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "WWDT5,Region ID Read Enable Register for WWDT 5" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "WWDT6,Region ID Read Enable Register for WWDT 6" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "WWDT7,Region ID Read Enable Register for WWDT 7" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "WWDT8,Region ID Read Enable Register for WWDT 8" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "WWDT9,Region ID Read Enable Register for WWDT 9" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE6002000++0x77 line.long 0x0 "ADVFSC,Region ID Read Enable Register for ADVFSC" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "APMU0,Region ID Read Enable Register for APMU 0" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "APMU1,Region ID Read Enable Register for APMU 1" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "APMU10,Region ID Read Enable Register for APMU 10" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "APMU11,Region ID Read Enable Register for APMU 11" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "APMU12,Region ID Read Enable Register for APMU 12" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "APMU13,Region ID Read Enable Register for APMU 13" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "APMU14,Region ID Read Enable Register for APMU 14" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "APMU15,Region ID Read Enable Register for APMU 15" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "APMU2,Region ID Read Enable Register for APMU 2" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "APMU3,Region ID Read Enable Register for APMU 3" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "APMU4,Region ID Read Enable Register for APMU 4" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "APMU5,Region ID Read Enable Register for APMU 5" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "APMU6,Region ID Read Enable Register for APMU 6" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "APMU7,Region ID Read Enable Register for APMU 7" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "APMU8,Region ID Read Enable Register for APMU 8" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "APMU9,Region ID Read Enable Register for APMU 9" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ARS00,Region ID Read Enable Register for ARS 00" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ARS01,Region ID Read Enable Register for ARS 01" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "ARS02,Region ID Read Enable Register for ARS 02" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "ARS03,Region ID Read Enable Register for ARS 03" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "ARS04,Region ID Read Enable Register for ARS 04" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "ARS05,Region ID Read Enable Register for ARS 05" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "ARS06,Region ID Read Enable Register for ARS 06" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "ARS07,Region ID Read Enable Register for ARS 07" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "ARS08,Region ID Read Enable Register for ARS 08" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "CMT0,Region ID Read Enable Register for CMT 0" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "CMT1,Region ID Read Enable Register for CMT 1" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "CMT2,Region ID Read Enable Register for CMT 2" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "CMT3,Region ID Read Enable Register for CMT 3" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE600207C++0x7 line.long 0x0 "DBE,Region ID Read Enable Register for DBE" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "IRQC,Region ID Read Enable Register for IRQC" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE600209C++0x3 line.long 0x0 "SCMT,Region ID Read Enable Register for SCMT" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE60020A4++0x17 line.long 0x0 "TSC0,Region ID Read Enable Register for TSC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "TSC1,Region ID Read Enable Register for TSC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "TSC2,Region ID Read Enable Register for TSC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "TSC3,Region ID Read Enable Register for TSC 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "TSC4,Region ID Read Enable Register for TSC 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "UCMT,Region ID Read Enable Register for UCMT" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE6002100++0x7F line.long 0x0 "CPG0,Region ID Read Enable Register for CPG 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "CPG1,Region ID Read Enable Register for CPG 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "CPG2,Region ID Read Enable Register for CPG 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "CPG3,Region ID Read Enable Register for CPG 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "PFC00,Region ID Read Enable Register for PFC 00" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "PFC01,Region ID Read Enable Register for PFC 01" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "PFC02,Region ID Read Enable Register for PFC 02" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "PFC03,Region ID Read Enable Register for PFC 03" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "PFC10,Region ID Read Enable Register for PFC 10" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "PFC11,Region ID Read Enable Register for PFC 11" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "PFC12,Region ID Read Enable Register for PFC 12" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "PFC13,Region ID Read Enable Register for PFC 13" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "PFC20,Region ID Read Enable Register for PFC 20" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "PFC21,Region ID Read Enable Register for PFC 21" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "PFC22,Region ID Read Enable Register for PFC 22" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "PFC23,Region ID Read Enable Register for PFC 23" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "PFC30,Region ID Read Enable Register for PFC 30" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "PFC31,Region ID Read Enable Register for PFC 31" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "PFC32,Region ID Read Enable Register for PFC 32" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "PFC33,Region ID Read Enable Register for PFC 33" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "PFCS0,Region ID Read Enable Register for PFCS 0" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "PFCS1,Region ID Read Enable Register for PFCS 1" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "PFCS2,Region ID Read Enable Register for PFCS 2" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "PFCS3,Region ID Read Enable Register for PFCS 3" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "RESET0,Region ID Read Enable Register for RESET 0" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "RESET1,Region ID Read Enable Register for RESET 1" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "RESET2,Region ID Read Enable Register for RESET 2" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "RESET3,Region ID Read Enable Register for RESET 3" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "SYS0,Region ID Read Enable Register for SYS 0" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "SYS1,Region ID Read Enable Register for SYS 1" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "SYS2,Region ID Read Enable Register for SYS 2" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "SYS3,Region ID Read Enable Register for SYS 3" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7792000++0x17 line.long 0x0 "DMAMSI0,Region ID Read Enable Register for DMAMSI 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "DMAMSI1,Region ID Read Enable Register for DMAMSI 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "DMAMSI2,Region ID Read Enable Register for DMAMSI 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "DMAMSI3,Region ID Read Enable Register for DMAMSI 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "DMAMSI4,Region ID Read Enable Register for DMAMSI 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "DMAMSI5,Region ID Read Enable Register for DMAMSI 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7762000++0x5F line.long 0x0 "ARSD30,Region ID Read Enable Register for ARSD 30" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARSD31,Region ID Read Enable Register for ARSD 31" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSD32,Region ID Read Enable Register for ARSD 32" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSD33,Region ID Read Enable Register for ARSD 33" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSD34,Region ID Read Enable Register for ARSD 34" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARSD35,Region ID Read Enable Register for ARSD 35" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARSD36,Region ID Read Enable Register for ARSD 36" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARSD37,Region ID Read Enable Register for ARSD 37" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARSD38,Region ID Read Enable Register for ARSD 38" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARSP30,Region ID Read Enable Register for ARSP 30" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ARSP31,Region ID Read Enable Register for ARSP 31" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ARSP32,Region ID Read Enable Register for ARSP 32" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "ARSP33,Region ID Read Enable Register for ARSP 33" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "ARSP34,Region ID Read Enable Register for ARSP 34" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ARSP35,Region ID Read Enable Register for ARSP 35" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ARSP36,Region ID Read Enable Register for ARSP 36" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ARSP37,Region ID Read Enable Register for ARSP 37" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ARSP38,Region ID Read Enable Register for ARSP 38" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "MSI0,Region ID Read Enable Register for MSI 0" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "MSI1,Region ID Read Enable Register for MSI 1" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "MSI2,Region ID Read Enable Register for MSI 2" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "MSI3,Region ID Read Enable Register for MSI 3" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "MSI4,Region ID Read Enable Register for MSI 4" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "MSI5,Region ID Read Enable Register for MSI 5" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFF882000++0x6B line.long 0x0 "ARIMP00,Region ID Read Enable Register for ARIMP 00" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARIMP01,Region ID Read Enable Register for ARIMP 01" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARIMP02,Region ID Read Enable Register for ARIMP 02" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARIMP03,Region ID Read Enable Register for ARIMP 03" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARIMP04,Region ID Read Enable Register for ARIMP 04" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "AXIFBABUSIR0,Region ID Read Enable Register for AXIFBABUSIR 0" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "AXIFBABUSIR1,Region ID Read Enable Register for AXIFBABUSIR 1" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "AXIFBABUSIR2,Region ID Read Enable Register for AXIFBABUSIR 2" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "AXIFBABUSIR3,Region ID Read Enable Register for AXIFBABUSIR 3" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "AXIFBABUSIR4,Region ID Read Enable Register for AXIFBABUSIR 4" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "AXIIMP0,Region ID Read Enable Register for AXIIMP 0" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "AXIIMPD0,Region ID Read Enable Register for AXIIMPD 0" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "AXIIMPD1,Region ID Read Enable Register for AXIIMPD 1" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "ARIMP05,Region ID Read Enable Register for ARIMP 05" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ARIMP06,Region ID Read Enable Register for ARIMP 06" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ARIMP07,Region ID Read Enable Register for ARIMP 07" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ARIMP08,Region ID Read Enable Register for ARIMP 08" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "CKMIR,Region ID Read Enable Register for CKMIR" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ECMIR,Region ID Read Enable Register for ECMIR" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "AXIRADSP0,Region ID Read Enable Register for AXIRADSP 0" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "AXIRADSP1,Region ID Read Enable Register for AXIRADSP 1" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "IPMMUIR,Region ID Read Enable Register for IPMMUIR" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "AXIFCPRAIRMA,Region ID Read Enable Register for AXIFCPRAIRMA" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "AXIIMP0MR,Region ID Read Enable Register for AXIIMP0MR" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "AXIIMP0MW,Region ID Read Enable Register for AXIIMP0MW" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "AXIIMP1MR,Region ID Read Enable Register for AXIIMP1MR" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "AXIIMP1MW,Region ID Read Enable Register for AXIIMP1MW" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFD812000++0x47 line.long 0x0 "ARPV0,Region ID Read Enable Register for ARPV 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARPV1,Region ID Read Enable Register for ARPV 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "AXIRGXS,Region ID Read Enable Register for AXIRGXS" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARPV2,Region ID Read Enable Register for ARPV 2" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARPV3,Region ID Read Enable Register for ARPV 3" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARPV4,Region ID Read Enable Register for ARPV 4" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARPV5,Region ID Read Enable Register for ARPV 5" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARPV6,Region ID Read Enable Register for ARPV 6" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARPV7,Region ID Read Enable Register for ARPV 7" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARPV8,Region ID Read Enable Register for ARPV 8" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CKM3DG,Region ID Read Enable Register for CKM3DG" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ECMU3DG,Region ID Read Enable Register for ECMU3DG" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "FBAPVC,Region ID Read Enable Register for FBAPVC" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "FBAPVD0,Region ID Read Enable Register for FBAPVD 0" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "FBAPVD1,Region ID Read Enable Register for FBAPVD 1" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "FBAPVD2,Region ID Read Enable Register for FBAPVD 2" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "FBAPVE,Region ID Read Enable Register for FBAPVE" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "IPMMUPV0,Region ID Read Enable Register for IPMMUPV 0" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE6622000++0x2B line.long 0x0 "ARRC0,Region ID Read Enable Register for ARRC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARRC1,Region ID Read Enable Register for ARRC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARRC2,Region ID Read Enable Register for ARRC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARRC3,Region ID Read Enable Register for ARRC 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARRC4,Region ID Read Enable Register for ARRC 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARRC5,Region ID Read Enable Register for ARRC 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARRC6,Region ID Read Enable Register for ARRC 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARRC7,Region ID Read Enable Register for ARRC 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARRC8,Region ID Read Enable Register for ARRC 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "CR0,Region ID Read Enable Register for CR 0" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ICUMX,Region ID Read Enable Register for ICUMX" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC32000++0xF line.long 0x0 "AXIDMAWCRC0,Region ID Read Enable Register for AXIDMAWCRC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "AXIDMAWCRC1,Region ID Read Enable Register for AXIDMAWCRC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "AXIDMAWCRC2,Region ID Read Enable Register for AXIDMAWCRC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "AXIDMAWCRC3,Region ID Read Enable Register for AXIDMAWCRC 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC42000++0x117 line.long 0x0 "ARMREG0,Region ID Read Enable Register for ARMREG 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARMREG1,Region ID Read Enable Register for ARMREG 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARMREG10,Region ID Read Enable Register for ARMREG 10" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARMREG11,Region ID Read Enable Register for ARMREG 11" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARMREG12,Region ID Read Enable Register for ARMREG 12" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARMREG13,Region ID Read Enable Register for ARMREG 13" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARMREG14,Region ID Read Enable Register for ARMREG 14" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "AXICR52SS,Region ID Read Enable Register for AXICR52SS" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "AXICSD0,Region ID Read Enable Register for AXICSD 0" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "AXIINTAP0,Region ID Read Enable Register for AXIINTAP 0" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "AXIINTAP1,Region ID Read Enable Register for AXIINTAP 1" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "AXISECROM,Region ID Read Enable Register for AXISECROM" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "AXISYSRAM0,Region ID Read Enable Register for AXISYSRAM 0" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "AXISYSRAM1,Region ID Read Enable Register for AXISYSRAM 1" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ARMREG15,Region ID Read Enable Register for ARMREG 15" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ARMREG2,Region ID Read Enable Register for ARMREG 2" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ARMREG3,Region ID Read Enable Register for ARMREG 3" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ARMREG4,Region ID Read Enable Register for ARMREG 4" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ARMREG5,Region ID Read Enable Register for ARMREG 5" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "ARMREG6,Region ID Read Enable Register for ARMREG 6" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "ARMREG7,Region ID Read Enable Register for ARMREG 7" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "ARMREG8,Region ID Read Enable Register for ARMREG 8" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "ARMREG9,Region ID Read Enable Register for ARMREG 9" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "ARRD0,Region ID Read Enable Register for ARRD 0" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "ARRD1,Region ID Read Enable Register for ARRD 1" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "ARRD2,Region ID Read Enable Register for ARRD 2" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "ARRD3,Region ID Read Enable Register for ARRD 3" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "ARRD4,Region ID Read Enable Register for ARRD 4" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "ARRD5,Region ID Read Enable Register for ARRD 5" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "ARRD6,Region ID Read Enable Register for ARRD 6" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "ARRD7,Region ID Read Enable Register for ARRD 7" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "ARRD8,Region ID Read Enable Register for ARRD 8" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "ARRT0,Region ID Read Enable Register for ARRT 0" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "ARRT1,Region ID Read Enable Register for ARRT 1" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "ARRT2,Region ID Read Enable Register for ARRT 2" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "ARRT3,Region ID Read Enable Register for ARRT 3" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "ARRT4,Region ID Read Enable Register for ARRT 4" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "ARRT5,Region ID Read Enable Register for ARRT 5" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "ARRT6,Region ID Read Enable Register for ARRT 6" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "ARRT7,Region ID Read Enable Register for ARRT 7" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "ARRT8,Region ID Read Enable Register for ARRT 8" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "CKMRT,Region ID Read Enable Register for CKMRT" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "CRC0,Region ID Read Enable Register for CRC 0" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "CRC1,Region ID Read Enable Register for CRC 1" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "CRC2,Region ID Read Enable Register for CRC 2" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "CRC3,Region ID Read Enable Register for CRC 3" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "CSD,Region ID Read Enable Register for CSD" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "ECM,Region ID Read Enable Register for ECM" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "ECMRT,Region ID Read Enable Register for ECMRT" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "FBACR52,Region ID Read Enable Register for FBACR 52" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "FBART,Region ID Read Enable Register for FBART" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "INTTP,Region ID Read Enable Register for INTTP" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "IPMMURT0,Region ID Read Enable Register for IPMMURT 0" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "IPMMURT1,Region ID Read Enable Register for IPMMURT 1" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "KCRC4,Region ID Read Enable Register for KCRC 4" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" line.long 0xDC "KCRC5,Region ID Read Enable Register for KCRC 5" hexmask.long.word 0xDC 0.--15. 1. "RGIDEN" line.long 0xE0 "KCRC6,Region ID Read Enable Register for KCRC 6" hexmask.long.word 0xE0 0.--15. 1. "RGIDEN" line.long 0xE4 "KCRC7,Region ID Read Enable Register for KCRC 7" hexmask.long.word 0xE4 0.--15. 1. "RGIDEN" line.long 0xE8 "MFI0,Region ID Read Enable Register for MFI 0" hexmask.long.word 0xE8 0.--15. 1. "RGIDEN" line.long 0xEC "MFI1,Region ID Read Enable Register for MFI 1" hexmask.long.word 0xEC 0.--15. 1. "RGIDEN" line.long 0xF0 "MFI10,Region ID Read Enable Register for MFI 10" hexmask.long.word 0xF0 0.--15. 1. "RGIDEN" line.long 0xF4 "MFI2,Region ID Read Enable Register for MFI 2" hexmask.long.word 0xF4 0.--15. 1. "RGIDEN" line.long 0xF8 "MFI3,Region ID Read Enable Register for MFI 3" hexmask.long.word 0xF8 0.--15. 1. "RGIDEN" line.long 0xFC "MFI4,Region ID Read Enable Register for MFI 4" hexmask.long.word 0xFC 0.--15. 1. "RGIDEN" line.long 0x100 "MFI5,Region ID Read Enable Register for MFI 5" hexmask.long.word 0x100 0.--15. 1. "RGIDEN" line.long 0x104 "MFI6,Region ID Read Enable Register for MFI 6" hexmask.long.word 0x104 0.--15. 1. "RGIDEN" line.long 0x108 "MFI7,Region ID Read Enable Register for MFI 7" hexmask.long.word 0x108 0.--15. 1. "RGIDEN" line.long 0x10C "MFI8,Region ID Read Enable Register for MFI 8" hexmask.long.word 0x10C 0.--15. 1. "RGIDEN" line.long 0x110 "MFI9,Region ID Read Enable Register for MFI 9" hexmask.long.word 0x110 0.--15. 1. "RGIDEN" line.long 0x114 "PRR,Region ID Read Enable Register for PRR" hexmask.long.word 0x114 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC4211C++0x3 line.long 0x0 "RTDM0P,Region ID Read Enable Register for RTDM0P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC42124++0x3 line.long 0x0 "RTDM1P,Region ID Read Enable Register for RTDM1P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC4212C++0x3 line.long 0x0 "RTDM2P,Region ID Read Enable Register for RTDM2P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC42134++0x3F line.long 0x0 "RTDM3P,Region ID Read Enable Register for RTDM3P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "SYSRAM0,Region ID Read Enable Register for SYSRAM 0" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "TSIPL0,Region ID Read Enable Register for TSIPL 0" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "TSIPL1,Region ID Read Enable Register for TSIPL 1" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "TSIPL2,Region ID Read Enable Register for TSIPL 2" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "TSIPL3,Region ID Read Enable Register for TSIPL 3" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "TSIPL4,Region ID Read Enable Register for TSIPL 4" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "TSIPL5,Region ID Read Enable Register for TSIPL 5" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "TSIPL6,Region ID Read Enable Register for TSIPL 6" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "TSIPL7,Region ID Read Enable Register for TSIPL 7" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "WCRC0,Region ID Read Enable Register for WCRC 0" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "WCRC1,Region ID Read Enable Register for WCRC 1" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "WCRC2,Region ID Read Enable Register for WCRC 2" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "WCRC3,Region ID Read Enable Register for WCRC 3" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "AXIFCPRART0MA,Region ID Read Enable Register for AXIFCPRART0MA" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "AXIMEMRTDM0MR,Region ID Read Enable Register for AXIMEMRTDM0MR" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC42200++0xFF line.long 0x0 "RTDM000,Region ID Read Enable Register for RTDM 000" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "RTDM001,Region ID Read Enable Register for RTDM 001" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "RTDM010,Region ID Read Enable Register for RTDM 010" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "RTDM011,Region ID Read Enable Register for RTDM 011" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "RTDM012,Region ID Read Enable Register for RTDM 012" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "RTDM013,Region ID Read Enable Register for RTDM 013" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "RTDM014,Region ID Read Enable Register for RTDM 014" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "RTDM015,Region ID Read Enable Register for RTDM 015" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "RTDM002,Region ID Read Enable Register for RTDM 002" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "RTDM003,Region ID Read Enable Register for RTDM 003" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "RTDM004,Region ID Read Enable Register for RTDM 004" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "RTDM005,Region ID Read Enable Register for RTDM 005" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "RTDM006,Region ID Read Enable Register for RTDM 006" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "RTDM007,Region ID Read Enable Register for RTDM 007" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "RTDM008,Region ID Read Enable Register for RTDM 008" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "RTDM009,Region ID Read Enable Register for RTDM 009" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "RTDM100,Region ID Read Enable Register for RTDM 100" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "RTDM101,Region ID Read Enable Register for RTDM 101" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "RTDM110,Region ID Read Enable Register for RTDM 110" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "RTDM111,Region ID Read Enable Register for RTDM 111" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "RTDM112,Region ID Read Enable Register for RTDM 112" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "RTDM113,Region ID Read Enable Register for RTDM 113" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "RTDM114,Region ID Read Enable Register for RTDM 114" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "RTDM115,Region ID Read Enable Register for RTDM 115" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "RTDM102,Region ID Read Enable Register for RTDM 102" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "RTDM103,Region ID Read Enable Register for RTDM 103" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "RTDM104,Region ID Read Enable Register for RTDM 104" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "RTDM105,Region ID Read Enable Register for RTDM 105" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "RTDM106,Region ID Read Enable Register for RTDM 106" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "RTDM107,Region ID Read Enable Register for RTDM 107" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "RTDM108,Region ID Read Enable Register for RTDM 108" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "RTDM109,Region ID Read Enable Register for RTDM 109" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "RTDM200,Region ID Read Enable Register for RTDM 200" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "RTDM201,Region ID Read Enable Register for RTDM 201" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "RTDM210,Region ID Read Enable Register for RTDM 210" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "RTDM211,Region ID Read Enable Register for RTDM 211" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "RTDM212,Region ID Read Enable Register for RTDM 212" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "RTDM213,Region ID Read Enable Register for RTDM 213" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "RTDM214,Region ID Read Enable Register for RTDM 214" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "RTDM215,Region ID Read Enable Register for RTDM 215" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "RTDM202,Region ID Read Enable Register for RTDM 202" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "RTDM203,Region ID Read Enable Register for RTDM 203" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "RTDM204,Region ID Read Enable Register for RTDM 204" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "RTDM205,Region ID Read Enable Register for RTDM 205" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "RTDM206,Region ID Read Enable Register for RTDM 206" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "RTDM207,Region ID Read Enable Register for RTDM 207" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "RTDM208,Region ID Read Enable Register for RTDM 208" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "RTDM209,Region ID Read Enable Register for RTDM 209" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "RTDM300,Region ID Read Enable Register for RTDM 300" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "RTDM301,Region ID Read Enable Register for RTDM 301" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "RTDM310,Region ID Read Enable Register for RTDM 310" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "RTDM311,Region ID Read Enable Register for RTDM 311" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "RTDM312,Region ID Read Enable Register for RTDM 312" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "RTDM313,Region ID Read Enable Register for RTDM 313" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "RTDM314,Region ID Read Enable Register for RTDM 314" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" line.long 0xDC "RTDM315,Region ID Read Enable Register for RTDM 315" hexmask.long.word 0xDC 0.--15. 1. "RGIDEN" line.long 0xE0 "RTDM302,Region ID Read Enable Register for RTDM 302" hexmask.long.word 0xE0 0.--15. 1. "RGIDEN" line.long 0xE4 "RTDM303,Region ID Read Enable Register for RTDM 303" hexmask.long.word 0xE4 0.--15. 1. "RGIDEN" line.long 0xE8 "RTDM304,Region ID Read Enable Register for RTDM 304" hexmask.long.word 0xE8 0.--15. 1. "RGIDEN" line.long 0xEC "RTDM305,Region ID Read Enable Register for RTDM 305" hexmask.long.word 0xEC 0.--15. 1. "RGIDEN" line.long 0xF0 "RTDM306,Region ID Read Enable Register for RTDM 306" hexmask.long.word 0xF0 0.--15. 1. "RGIDEN" line.long 0xF4 "RTDM307,Region ID Read Enable Register for RTDM 307" hexmask.long.word 0xF4 0.--15. 1. "RGIDEN" line.long 0xF8 "RTDM308,Region ID Read Enable Register for RTDM 308" hexmask.long.word 0xF8 0.--15. 1. "RGIDEN" line.long 0xFC "RTDM309,Region ID Read Enable Register for RTDM 309" hexmask.long.word 0xFC 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFF862000++0x9F line.long 0x0 "ARSC0,Region ID Read Enable Register for ARSC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARSC1,Region ID Read Enable Register for ARSC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSC2,Region ID Read Enable Register for ARSC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSC3,Region ID Read Enable Register for ARSC 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSC4,Region ID Read Enable Register for ARSC 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARSC5,Region ID Read Enable Register for ARSC 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARSC6,Region ID Read Enable Register for ARSC 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARSC7,Region ID Read Enable Register for ARSC 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARSC8,Region ID Read Enable Register for ARSC 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARSTM0,Region ID Read Enable Register for ARSTM 0" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ARSTM1,Region ID Read Enable Register for ARSTM 1" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "AXICSD1SR,Region ID Read Enable Register for AXICSD1SR" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "AXIFBABUSTOP0,Region ID Read Enable Register for AXIFBABUSTOP 0" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "AXIFBABUSTOP1,Region ID Read Enable Register for AXIFBABUSTOP 1" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ARSTM2,Region ID Read Enable Register for ARSTM 2" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ARSTM3,Region ID Read Enable Register for ARSTM 3" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ARSTM4,Region ID Read Enable Register for ARSTM 4" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ARSTM5,Region ID Read Enable Register for ARSTM 5" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ARSTM6,Region ID Read Enable Register for ARSTM 6" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "ARSTM7,Region ID Read Enable Register for ARSTM 7" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "ARSTM8,Region ID Read Enable Register for ARSTM 8" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "ECMTOP,Region ID Read Enable Register for ECMTOP" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "FBA,Region ID Read Enable Register for FBA" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "FBC,Region ID Read Enable Register for FBC" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "AXICCIS0SRS0,Region ID Read Enable Register for AXICCIS0SRS 0" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "AXICCIS0SRS1,Region ID Read Enable Register for AXICCIS0SRS 1" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "AXICCIS0SRS10,Region ID Read Enable Register for AXICCIS0SRS 10" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "AXICCIS0SRS11,Region ID Read Enable Register for AXICCIS0SRS 11" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "AXICCIS0SRS12,Region ID Read Enable Register for AXICCIS0SRS 12" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "AXICCIS0SRS13,Region ID Read Enable Register for AXICCIS0SRS 13" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "AXICCIS0SRS14,Region ID Read Enable Register for AXICCIS0SRS 14" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "AXICCIS0SRS15,Region ID Read Enable Register for AXICCIS0SRS 15" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "AXICCIS0SRS2,Region ID Read Enable Register for AXICCIS0SRS 2" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "AXICCIS0SRS3,Region ID Read Enable Register for AXICCIS0SRS 3" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "AXICCIS0SRS4,Region ID Read Enable Register for AXICCIS0SRS 4" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "AXICCIS0SRS5,Region ID Read Enable Register for AXICCIS0SRS 5" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "AXICCIS0SRS6,Region ID Read Enable Register for AXICCIS0SRS 6" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "AXICCIS0SRS7,Region ID Read Enable Register for AXICCIS0SRS 7" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "AXICCIS0SRS8,Region ID Read Enable Register for AXICCIS0SRS 8" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "AXICCIS0SRS9,Region ID Read Enable Register for AXICCIS0SRS 9" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE67C2000++0x13 line.long 0x0 "ARMM,Region ID Read Enable Register for ARMM" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "AXIARNMM,Region ID Read Enable Register for AXIARNMM" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSM0,Region ID Read Enable Register for ARSM 0" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSM1,Region ID Read Enable Register for ARSM 1" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSM2,Region ID Read Enable Register for ARSM 2" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE67C2034++0x4B line.long 0x0 "ARSM3,Region ID Read Enable Register for ARSM 3" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARSM4,Region ID Read Enable Register for ARSM 4" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSM5,Region ID Read Enable Register for ARSM 5" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSM6,Region ID Read Enable Register for ARSM 6" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSM7,Region ID Read Enable Register for ARSM 7" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARSM8,Region ID Read Enable Register for ARSM 8" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "AXMM0,Region ID Read Enable Register for AXMM 0" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "AXMM1,Region ID Read Enable Register for AXMM 1" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "AXMMPMON,Region ID Read Enable Register for AXMMPMON" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "CKMMM,Region ID Read Enable Register for CKMMM" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ECMMM,Region ID Read Enable Register for ECMMM" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "FBADBSC0,Region ID Read Enable Register for FBADBSC 0" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "FBADBSC1,Region ID Read Enable Register for FBADBSC 1" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "FBAMM,Region ID Read Enable Register for FBAMM" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "IPMMUMM,Region ID Read Enable Register for IPMMUMM" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "AXIDBS0S0,Region ID Read Enable Register for AXIDBS0S 0" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "AXIDBS0S1,Region ID Read Enable Register for AXIDBS0S 1" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "AXIDBS1S0,Region ID Read Enable Register for AXIDBS1S 0" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "AXIDBS1S1,Region ID Read Enable Register for AXIDBS1S 1" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFF802000++0x23 line.long 0x0 "ARSN0,Region ID Read Enable Register for ARSN 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARSN1,Region ID Read Enable Register for ARSN 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSN2,Region ID Read Enable Register for ARSN 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSN3,Region ID Read Enable Register for ARSN 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSN4,Region ID Read Enable Register for ARSN 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARSN5,Region ID Read Enable Register for ARSN 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARSN6,Region ID Read Enable Register for ARSN 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARSN7,Region ID Read Enable Register for ARSN 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARSN8,Region ID Read Enable Register for ARSN 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7752000++0xEF line.long 0x0 "ARSD00,Region ID Read Enable Register for ARSD 00" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARSD01,Region ID Read Enable Register for ARSD 01" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSD02,Region ID Read Enable Register for ARSD 02" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSD03,Region ID Read Enable Register for ARSD 03" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSD04,Region ID Read Enable Register for ARSD 04" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARSD05,Region ID Read Enable Register for ARSD 05" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARSD06,Region ID Read Enable Register for ARSD 06" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "FRAY,Region ID Read Enable Register for FRAY" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "IPC_AXI,Region ID Read Enable Register for IPC AXI" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "LBSC,Region ID Read Enable Register for LBSC" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "RPC,Region ID Read Enable Register for RPC" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "SDHI0,Region ID Read Enable Register for SDHI 0" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "ARSD07,Region ID Read Enable Register for ARSD 07" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "ARSD08,Region ID Read Enable Register for ARSD 08" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ARSP00,Region ID Read Enable Register for ARSP 00" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ARSP01,Region ID Read Enable Register for ARSP 01" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ARSP02,Region ID Read Enable Register for ARSP 02" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ARSP03,Region ID Read Enable Register for ARSP 03" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ARSP04,Region ID Read Enable Register for ARSP 04" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "ARSP05,Region ID Read Enable Register for ARSP 05" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "ARSP06,Region ID Read Enable Register for ARSP 06" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "ARSP07,Region ID Read Enable Register for ARSP 07" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "ARSP08,Region ID Read Enable Register for ARSP 08" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "CANFD,Region ID Read Enable Register for CANFD" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "CKMPE0,Region ID Read Enable Register for CKMPE 0" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "ECMPER0,Region ID Read Enable Register for ECMPER 0" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "FBAPER0,Region ID Read Enable Register for FBAPER 0" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "FSO0,Region ID Read Enable Register for FSO 0" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "FSO1,Region ID Read Enable Register for FSO 1" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "FSO10,Region ID Read Enable Register for FSO 10" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "FSO2,Region ID Read Enable Register for FSO 2" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "FSO3,Region ID Read Enable Register for FSO 3" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "FSO4,Region ID Read Enable Register for FSO 4" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "FSO5,Region ID Read Enable Register for FSO 5" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "FSO6,Region ID Read Enable Register for FSO 6" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "FSO7,Region ID Read Enable Register for FSO 7" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "FSO8,Region ID Read Enable Register for FSO 8" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "FSO9,Region ID Read Enable Register for FSO 9" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "HSCIF0,Region ID Read Enable Register for HSCIF 0" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "HSCIF1,Region ID Read Enable Register for HSCIF 1" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "HSCIF2,Region ID Read Enable Register for HSCIF 2" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "HSCIF3,Region ID Read Enable Register for HSCIF 3" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "I2C0,Region ID Read Enable Register for I2C 0" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "I2C1,Region ID Read Enable Register for I2C 1" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "I2C2,Region ID Read Enable Register for I2C 2" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "I2C3,Region ID Read Enable Register for I2C 3" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "I2C4,Region ID Read Enable Register for I2C 4" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "I2C5,Region ID Read Enable Register for I2C 5" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "I2C6,Region ID Read Enable Register for I2C 6" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "IPC_APB,Region ID Read Enable Register for IPC APB" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "IPMMUDS0,Region ID Read Enable Register for IPMMUDS 0" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "PWM0,Region ID Read Enable Register for PWM 0" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "PWM1,Region ID Read Enable Register for PWM 1" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "PWM2,Region ID Read Enable Register for PWM 2" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "PWM3,Region ID Read Enable Register for PWM 3" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" line.long 0xDC "PWM4,Region ID Read Enable Register for PWM 4" hexmask.long.word 0xDC 0.--15. 1. "RGIDEN" line.long 0xE0 "SCIF0,Region ID Read Enable Register for SCIF 0" hexmask.long.word 0xE0 0.--15. 1. "RGIDEN" line.long 0xE4 "SCIF1,Region ID Read Enable Register for SCIF 1" hexmask.long.word 0xE4 0.--15. 1. "RGIDEN" line.long 0xE8 "SCIF3,Region ID Read Enable Register for SCIF 3" hexmask.long.word 0xE8 0.--15. 1. "RGIDEN" line.long 0xEC "SCIF4,Region ID Read Enable Register for SCIF 4" hexmask.long.word 0xEC 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE77520F4++0x3 line.long 0x0 "SYDM1P,Region ID Read Enable Register for SYDM1P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE77520FC++0x17 line.long 0x0 "SYDM2P,Region ID Read Enable Register for SYDM2P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "TMU1,Region ID Read Enable Register for TMU 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "TMU2,Region ID Read Enable Register for TMU 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "TMU3,Region ID Read Enable Register for TMU 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "TMU4,Region ID Read Enable Register for TMU 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "TPU0,Region ID Read Enable Register for TPU 0" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7752240++0x7F line.long 0x0 "SYDM100,Region ID Read Enable Register for SYDM 100" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "SYDM101,Region ID Read Enable Register for SYDM 101" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "SYDM110,Region ID Read Enable Register for SYDM 110" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "SYDM111,Region ID Read Enable Register for SYDM 111" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "SYDM112,Region ID Read Enable Register for SYDM 112" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "SYDM113,Region ID Read Enable Register for SYDM 113" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "SYDM114,Region ID Read Enable Register for SYDM 114" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "SYDM115,Region ID Read Enable Register for SYDM 115" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "SYDM102,Region ID Read Enable Register for SYDM 102" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "SYDM103,Region ID Read Enable Register for SYDM 103" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "SYDM104,Region ID Read Enable Register for SYDM 104" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "SYDM105,Region ID Read Enable Register for SYDM 105" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "SYDM106,Region ID Read Enable Register for SYDM 106" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "SYDM107,Region ID Read Enable Register for SYDM 107" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "SYDM108,Region ID Read Enable Register for SYDM 108" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "SYDM109,Region ID Read Enable Register for SYDM 109" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "SYDM200,Region ID Read Enable Register for SYDM 200" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "SYDM201,Region ID Read Enable Register for SYDM 201" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "SYDM210,Region ID Read Enable Register for SYDM 210" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "SYDM211,Region ID Read Enable Register for SYDM 211" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "SYDM212,Region ID Read Enable Register for SYDM 212" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "SYDM213,Region ID Read Enable Register for SYDM 213" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "SYDM214,Region ID Read Enable Register for SYDM 214" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "SYDM215,Region ID Read Enable Register for SYDM 215" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "SYDM202,Region ID Read Enable Register for SYDM 202" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "SYDM203,Region ID Read Enable Register for SYDM 203" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "SYDM204,Region ID Read Enable Register for SYDM 204" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "SYDM205,Region ID Read Enable Register for SYDM 205" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "SYDM206,Region ID Read Enable Register for SYDM 206" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "SYDM207,Region ID Read Enable Register for SYDM 207" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "SYDM208,Region ID Read Enable Register for SYDM 208" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "SYDM209,Region ID Read Enable Register for SYDM 209" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE6582000++0x15F line.long 0x0 "AXIPCI000,Region ID Read Enable Register for AXIPCI 000" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "AXIPCI001,Region ID Read Enable Register for AXIPCI 001" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "AXIPCI002,Region ID Read Enable Register for AXIPCI 002" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "AXIPCI003,Region ID Read Enable Register for AXIPCI 003" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "AXIPCI004,Region ID Read Enable Register for AXIPCI 004" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "AXIPCI005,Region ID Read Enable Register for AXIPCI 005" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "AXIPCI006,Region ID Read Enable Register for AXIPCI 006" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "AXIPCI007,Region ID Read Enable Register for AXIPCI 007" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "AXIPCI008,Region ID Read Enable Register for AXIPCI 008" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "AXIPCI009,Region ID Read Enable Register for AXIPCI 009" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "AXIPCI010,Region ID Read Enable Register for AXIPCI 010" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "AXIPCI011,Region ID Read Enable Register for AXIPCI 011" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "AXIPCI012,Region ID Read Enable Register for AXIPCI 012" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "AXIPCI013,Region ID Read Enable Register for AXIPCI 013" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "AXIPCI014,Region ID Read Enable Register for AXIPCI 014" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "AXIPCI015,Region ID Read Enable Register for AXIPCI 015" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "AXIPCI100,Region ID Read Enable Register for AXIPCI 100" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "AXIPCI101,Region ID Read Enable Register for AXIPCI 101" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "AXIPCI102,Region ID Read Enable Register for AXIPCI 102" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "AXIPCI103,Region ID Read Enable Register for AXIPCI 103" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "AXIPCI104,Region ID Read Enable Register for AXIPCI 104" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "AXIPCI105,Region ID Read Enable Register for AXIPCI 105" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "AXIPCI106,Region ID Read Enable Register for AXIPCI 106" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "AXIPCI107,Region ID Read Enable Register for AXIPCI 107" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "AXIPCI108,Region ID Read Enable Register for AXIPCI 108" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "AXIPCI109,Region ID Read Enable Register for AXIPCI 109" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "AXIPCI110,Region ID Read Enable Register for AXIPCI 110" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "AXIPCI1S11,Region ID Read Enable Register for AXIPCI1S 11" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "AXIPCI1S12,Region ID Read Enable Register for AXIPCI1S 12" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "AXIPCI1S13,Region ID Read Enable Register for AXIPCI1S 13" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "AXIPCI1S14,Region ID Read Enable Register for AXIPCI1S 14" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "AXIPCI1S15,Region ID Read Enable Register for AXIPCI1S 15" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "AXIPCI2S0,Region ID Read Enable Register for AXIPCI2S 0" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "AXIPCI2S1,Region ID Read Enable Register for AXIPCI2S 1" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "AXIPCI2S2,Region ID Read Enable Register for AXIPCI2S 2" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "AXIPCI2S3,Region ID Read Enable Register for AXIPCI2S 3" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "AXIPCI2S4,Region ID Read Enable Register for AXIPCI2S 4" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "AXIPCI2S5,Region ID Read Enable Register for AXIPCI2S 5" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "AXIPCI2S6,Region ID Read Enable Register for AXIPCI2S 6" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "AXIPCI2S7,Region ID Read Enable Register for AXIPCI2S 7" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "AXIPCI2S8,Region ID Read Enable Register for AXIPCI2S 8" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "AXIPCI2S9,Region ID Read Enable Register for AXIPCI2S 9" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "AXIPCI2S10,Region ID Read Enable Register for AXIPCI2S 10" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "AXIPCI2S11,Region ID Read Enable Register for AXIPCI2S 11" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "AXIPCI2S12,Region ID Read Enable Register for AXIPCI2S 12" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "AXIPCI2S13,Region ID Read Enable Register for AXIPCI2S 13" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "AXIPCI2S14,Region ID Read Enable Register for AXIPCI2S 14" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "AXIPCI2S15,Region ID Read Enable Register for AXIPCI2S 15" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "AXIPCI3S0,Region ID Read Enable Register for AXIPCI3S 0" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "AXIPCI3S1,Region ID Read Enable Register for AXIPCI3S 1" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "AXIPCI3S2,Region ID Read Enable Register for AXIPCI3S 2" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "AXIPCI3S3,Region ID Read Enable Register for AXIPCI3S 3" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "AXIPCI3S4,Region ID Read Enable Register for AXIPCI3S 4" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "AXIPCI3S5,Region ID Read Enable Register for AXIPCI3S 5" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "AXIPCI3S6,Region ID Read Enable Register for AXIPCI3S 6" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" line.long 0xDC "AXIPCI3S7,Region ID Read Enable Register for AXIPCI3S 7" hexmask.long.word 0xDC 0.--15. 1. "RGIDEN" line.long 0xE0 "AXIPCI3S8,Region ID Read Enable Register for AXIPCI3S 8" hexmask.long.word 0xE0 0.--15. 1. "RGIDEN" line.long 0xE4 "AXIPCI3S9,Region ID Read Enable Register for AXIPCI3S 9" hexmask.long.word 0xE4 0.--15. 1. "RGIDEN" line.long 0xE8 "AXIPCI3S10,Region ID Read Enable Register for AXIPCI3S 10" hexmask.long.word 0xE8 0.--15. 1. "RGIDEN" line.long 0xEC "AXIPCI3S11,Region ID Read Enable Register for AXIPCI3S 11" hexmask.long.word 0xEC 0.--15. 1. "RGIDEN" line.long 0xF0 "AXIPCI3S12,Region ID Read Enable Register for AXIPCI3S 12" hexmask.long.word 0xF0 0.--15. 1. "RGIDEN" line.long 0xF4 "AXIPCI3S13,Region ID Read Enable Register for AXIPCI3S 13" hexmask.long.word 0xF4 0.--15. 1. "RGIDEN" line.long 0xF8 "AXIPCI3S14,Region ID Read Enable Register for AXIPCI3S 14" hexmask.long.word 0xF8 0.--15. 1. "RGIDEN" line.long 0xFC "AXIPCI3S15,Region ID Read Enable Register for AXIPCI3S 15" hexmask.long.word 0xFC 0.--15. 1. "RGIDEN" line.long 0x100 "AVB0,Region ID Read Enable Register for AVB 0" hexmask.long.word 0x100 0.--15. 1. "RGIDEN" line.long 0x104 "AVB1,Region ID Read Enable Register for AVB 1" hexmask.long.word 0x104 0.--15. 1. "RGIDEN" line.long 0x108 "AVB2,Region ID Read Enable Register for AVB 2" hexmask.long.word 0x108 0.--15. 1. "RGIDEN" line.long 0x10C "AVB3,Region ID Read Enable Register for AVB 3" hexmask.long.word 0x10C 0.--15. 1. "RGIDEN" line.long 0x110 "AVB4,Region ID Read Enable Register for AVB 4" hexmask.long.word 0x110 0.--15. 1. "RGIDEN" line.long 0x114 "AVB5,Region ID Read Enable Register for AVB 5" hexmask.long.word 0x114 0.--15. 1. "RGIDEN" line.long 0x118 "ADG,Region ID Read Enable Register for ADG" hexmask.long.word 0x118 0.--15. 1. "RGIDEN" line.long 0x11C "PPHY0,Region ID Read Enable Register for PPHY 0" hexmask.long.word 0x11C 0.--15. 1. "RGIDEN" line.long 0x120 "PPHY1,Region ID Read Enable Register for PPHY 1" hexmask.long.word 0x120 0.--15. 1. "RGIDEN" line.long 0x124 "PPHY2,Region ID Read Enable Register for PPHY 2" hexmask.long.word 0x124 0.--15. 1. "RGIDEN" line.long 0x128 "PPHY3,Region ID Read Enable Register for PPHY 3" hexmask.long.word 0x128 0.--15. 1. "RGIDEN" line.long 0x12C "FBAPER1,Region ID Read Enable Register for FBAPER 1" hexmask.long.word 0x12C 0.--15. 1. "RGIDEN" line.long 0x130 "IPMMUDS1,Region ID Read Enable Register for IPMMUDS 1" hexmask.long.word 0x130 0.--15. 1. "RGIDEN" line.long 0x134 "CKMPE1,Region ID Read Enable Register for CKMPE 1" hexmask.long.word 0x134 0.--15. 1. "RGIDEN" line.long 0x138 "ECMPER1,Region ID Read Enable Register for ECMPER 1" hexmask.long.word 0x138 0.--15. 1. "RGIDEN" line.long 0x13C "ARSP10,Region ID Read Enable Register for ARSP 10" hexmask.long.word 0x13C 0.--15. 1. "RGIDEN" line.long 0x140 "ARSP11,Region ID Read Enable Register for ARSP 11" hexmask.long.word 0x140 0.--15. 1. "RGIDEN" line.long 0x144 "ARSP12,Region ID Read Enable Register for ARSP 12" hexmask.long.word 0x144 0.--15. 1. "RGIDEN" line.long 0x148 "ARSP13,Region ID Read Enable Register for ARSP 13" hexmask.long.word 0x148 0.--15. 1. "RGIDEN" line.long 0x14C "ARSP14,Region ID Read Enable Register for ARSP 14" hexmask.long.word 0x14C 0.--15. 1. "RGIDEN" line.long 0x150 "ARSP15,Region ID Read Enable Register for ARSP 15" hexmask.long.word 0x150 0.--15. 1. "RGIDEN" line.long 0x154 "ARSP16,Region ID Read Enable Register for ARSP 16" hexmask.long.word 0x154 0.--15. 1. "RGIDEN" line.long 0x158 "ARSP17,Region ID Read Enable Register for ARSP 17" hexmask.long.word 0x158 0.--15. 1. "RGIDEN" line.long 0x15C "ARSP18,Region ID Read Enable Register for ARSP 18" hexmask.long.word 0x15C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFE682000++0x7F line.long 0x0 "ARVC0,Region ID Read Enable Register for ARVC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARVC1,Region ID Read Enable Register for ARVC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARVC2,Region ID Read Enable Register for ARVC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARVC3,Region ID Read Enable Register for ARVC 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "AXIFBABUSVC,Region ID Read Enable Register for AXIFBABUSVC" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARVC4,Region ID Read Enable Register for ARVC 4" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARVC5,Region ID Read Enable Register for ARVC 5" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARVC6,Region ID Read Enable Register for ARVC 6" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARVC7,Region ID Read Enable Register for ARVC 7" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARVC8,Region ID Read Enable Register for ARVC 8" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CKMVC,Region ID Read Enable Register for CKMVC" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ECMVC,Region ID Read Enable Register for ECMVC" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "FCPCS,Region ID Read Enable Register for FCPCS" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "IMR0,Region ID Read Enable Register for IMR 0" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "IMR1,Region ID Read Enable Register for IMR 1" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "IMR2,Region ID Read Enable Register for IMR 2" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "IMR3,Region ID Read Enable Register for IMR 3" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "IMS0,Region ID Read Enable Register for IMS 0" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "IMS1,Region ID Read Enable Register for IMS 1" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "IPMMUVC,Region ID Read Enable Register for IPMMUVC" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "IV1ES,Region ID Read Enable Register for IV1ES" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "VCP4LC,Region ID Read Enable Register for VCP4LC" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "VCP4LV,Region ID Read Enable Register for VCP4LV" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "AXIFCPRAVC0MA,Region ID Read Enable Register for AXIFCPRAVC0MA" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "AXIIMR00MR,Region ID Read Enable Register for AXIIMR00MR" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "AXIIMR0COMXW,Region ID Read Enable Register for AXIIMR0COMXW" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "AXIIMR10MR,Region ID Read Enable Register for AXIIMR10MR" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "AXIIMR1COMXW,Region ID Read Enable Register for AXIIMR1COMXW" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "AXIIMR20MR,Region ID Read Enable Register for AXIIMR20MR" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "AXIIMR30MR,Region ID Read Enable Register for AXIIMR30MR" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "AXIIMS0MR,Region ID Read Enable Register for AXIIMS0MR" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "AXIIMS1MR,Region ID Read Enable Register for AXIIMS1MR" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFEBE2000++0x93 line.long 0x0 "AXIFBABUSVIOS,Region ID Read Enable Register for AXIFBABUSVIOS" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARVI10,Region ID Read Enable Register for ARVI 10" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARVI11,Region ID Read Enable Register for ARVI 11" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARVI12,Region ID Read Enable Register for ARVI 12" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARVI13,Region ID Read Enable Register for ARVI 13" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARVI14,Region ID Read Enable Register for ARVI 14" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARVI15,Region ID Read Enable Register for ARVI 15" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARVI16,Region ID Read Enable Register for ARVI 16" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARVI17,Region ID Read Enable Register for ARVI 17" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARVI18,Region ID Read Enable Register for ARVI 18" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CKMVIO,Region ID Read Enable Register for CKMVIO" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "DIS0,Region ID Read Enable Register for DIS 0" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "DOC2CH,Region ID Read Enable Register for DOC2CH" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "DSITXLINK0,Region ID Read Enable Register for DSITXLINK 0" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "DSITXLINK1,Region ID Read Enable Register for DSITXLINK 1" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ECMVIO,Region ID Read Enable Register for ECMVIO" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "FCPVD0,Region ID Read Enable Register for FCPVD 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "FCPVD1,Region ID Read Enable Register for FCPVD 1" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "FCPVX0,Region ID Read Enable Register for FCPVX 0" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "FCPVX1,Region ID Read Enable Register for FCPVX 1" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "FCPVX2,Region ID Read Enable Register for FCPVX 2" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "FCPVX3,Region ID Read Enable Register for FCPVX 3" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "IPMMUVI0,Region ID Read Enable Register for IPMMUVI 0" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "IPMMUVI1,Region ID Read Enable Register for IPMMUVI 1" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "VSPD0,Region ID Read Enable Register for VSPD 0" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "VSPD1,Region ID Read Enable Register for VSPD 1" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "VSPX0,Region ID Read Enable Register for VSPX 0" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "VSPX1,Region ID Read Enable Register for VSPX 1" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "VSPX2,Region ID Read Enable Register for VSPX 2" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "VSPX3,Region ID Read Enable Register for VSPX 3" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "AXIFCPRAVI1MA,Region ID Read Enable Register for AXIFCPRAVI1MA" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "AXIFCPVD0MR,Region ID Read Enable Register for AXIFCPVD0MR" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "AXIFCPVD1MR,Region ID Read Enable Register for AXIFCPVD1MR" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "AXIFCPVX0MR,Region ID Read Enable Register for AXIFCPVX0MR" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "AXIFCPVX1MR,Region ID Read Enable Register for AXIFCPVX1MR" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "AXIFCPVX2MR,Region ID Read Enable Register for AXIFCPVX2MR" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "AXIFCPVX3MR,Region ID Read Enable Register for AXIFCPVX3MR" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFEBF2000++0xDB line.long 0x0 "ARVI0,Region ID Read Enable Register for ARVI 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARVI1,Region ID Read Enable Register for ARVI 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARVI2,Region ID Read Enable Register for ARVI 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARVI3,Region ID Read Enable Register for ARVI 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARVI4,Region ID Read Enable Register for ARVI 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARVI5,Region ID Read Enable Register for ARVI 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARVI6,Region ID Read Enable Register for ARVI 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARVI7,Region ID Read Enable Register for ARVI 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARVI8,Region ID Read Enable Register for ARVI 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "CSI4LNK0,Region ID Read Enable Register for CSI4LNK 0" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CSI4LNK1,Region ID Read Enable Register for CSI4LNK 1" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "CSI4LNK2,Region ID Read Enable Register for CSI4LNK 2" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "CSI4LNK3,Region ID Read Enable Register for CSI4LNK 3" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "ISP0,Region ID Read Enable Register for ISP 0" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ISP0CORE,Region ID Read Enable Register for ISP0CORE" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ISP1,Region ID Read Enable Register for ISP 1" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ISP1CORE,Region ID Read Enable Register for ISP1CORE" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ISP2,Region ID Read Enable Register for ISP 2" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ISP2CORE,Region ID Read Enable Register for ISP2CORE" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "ISP3,Region ID Read Enable Register for ISP 3" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "ISP3CORE,Region ID Read Enable Register for ISP3CORE" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "VIN00,Region ID Read Enable Register for VIN 00" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "VIN01,Region ID Read Enable Register for VIN 01" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "VIN02,Region ID Read Enable Register for VIN 02" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "VIN03,Region ID Read Enable Register for VIN 03" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "VIN04,Region ID Read Enable Register for VIN 04" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "VIN05,Region ID Read Enable Register for VIN 05" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "VIN06,Region ID Read Enable Register for VIN 06" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "VIN07,Region ID Read Enable Register for VIN 07" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "VIN10,Region ID Read Enable Register for VIN 10" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "VIN11,Region ID Read Enable Register for VIN 11" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "VIN12,Region ID Read Enable Register for VIN 12" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "VIN13,Region ID Read Enable Register for VIN 13" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "VIN14,Region ID Read Enable Register for VIN 14" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "VIN15,Region ID Read Enable Register for VIN 15" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "VIN16,Region ID Read Enable Register for VIN 16" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "VIN17,Region ID Read Enable Register for VIN 17" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "VIN20,Region ID Read Enable Register for VIN 20" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "VIN21,Region ID Read Enable Register for VIN 21" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "VIN22,Region ID Read Enable Register for VIN 22" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "VIN23,Region ID Read Enable Register for VIN 23" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "VIN24,Region ID Read Enable Register for VIN 24" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "VIN25,Region ID Read Enable Register for VIN 25" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "VIN26,Region ID Read Enable Register for VIN 26" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "VIN27,Region ID Read Enable Register for VIN 27" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "VIN30,Region ID Read Enable Register for VIN 30" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "VIN31,Region ID Read Enable Register for VIN 31" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "VIN32,Region ID Read Enable Register for VIN 32" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "VIN33,Region ID Read Enable Register for VIN 33" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "VIN34,Region ID Read Enable Register for VIN 34" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "VIN35,Region ID Read Enable Register for VIN 35" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "VIN36,Region ID Read Enable Register for VIN 36" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "VIN37,Region ID Read Enable Register for VIN 37" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "AXIISPCOMXW,Region ID Read Enable Register for AXIISPCOMXW" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "AXIVINCOMXW,Region ID Read Enable Register for AXIVINCOMXW" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7B12000++0x53 line.long 0x0 "ARVIP00,Region ID Read Enable Register for ARVIP 00" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARVIP01,Region ID Read Enable Register for ARVIP 01" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARVIP02,Region ID Read Enable Register for ARVIP 02" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARVIP03,Region ID Read Enable Register for ARVIP 03" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "AXIFBABUSVIP0,Region ID Read Enable Register for AXIFBABUSVIP 0" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARVIP04,Region ID Read Enable Register for ARVIP 04" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARVIP05,Region ID Read Enable Register for ARVIP 05" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARVIP06,Region ID Read Enable Register for ARVIP 06" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARVIP07,Region ID Read Enable Register for ARVIP 07" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARVIP08,Region ID Read Enable Register for ARVIP 08" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CKMVIP,Region ID Read Enable Register for CKMVIP" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ECMVIP,Region ID Read Enable Register for ECMVIP" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "IPMMUVIP0,Region ID Read Enable Register for IPMMUVIP 0" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "SMES0,Region ID Read Enable Register for SMES 0" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "SMPO0,Region ID Read Enable Register for SMPO 0" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "SMPS0,Region ID Read Enable Register for SMPS 0" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "UMFL0,Region ID Read Enable Register for UMFL 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "AXIFCPRAVIP0MA,Region ID Read Enable Register for AXIFCPRAVIP0MA" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "AXISMPS0MR,Region ID Read Enable Register for AXISMPS0MR" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "AXIUMFL0MR,Region ID Read Enable Register for AXIUMFL0MR" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "AXIUMFL0MW,Region ID Read Enable Register for AXIUMFL0MW" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7B42000++0x7F line.long 0x0 "ARVIP10,Region ID Read Enable Register for ARVIP 10" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARVIP11,Region ID Read Enable Register for ARVIP 11" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARVIP12,Region ID Read Enable Register for ARVIP 12" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARVIP13,Region ID Read Enable Register for ARVIP 13" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "AXIFBABUSVIP1,Region ID Read Enable Register for AXIFBABUSVIP 1" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARVIP14,Region ID Read Enable Register for ARVIP 14" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARVIP15,Region ID Read Enable Register for ARVIP 15" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARVIP16,Region ID Read Enable Register for ARVIP 16" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARVIP17,Region ID Read Enable Register for ARVIP 17" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARVIP18,Region ID Read Enable Register for ARVIP 18" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CLE0,Region ID Read Enable Register for CLE 0" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "CLE1,Region ID Read Enable Register for CLE 1" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "CLE2,Region ID Read Enable Register for CLE 2" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "CLE3,Region ID Read Enable Register for CLE 3" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "DISP0,Region ID Read Enable Register for DISP 0" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "DISP1,Region ID Read Enable Register for DISP 1" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "IPMMUVIP1,Region ID Read Enable Register for IPMMUVIP 1" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "SMES1,Region ID Read Enable Register for SMES 1" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "SMPO1,Region ID Read Enable Register for SMPO 1" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "SMPS1,Region ID Read Enable Register for SMPS 1" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "UMFL1,Region ID Read Enable Register for UMFL 1" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "AXICLE0MR,Region ID Read Enable Register for AXICLE0MR" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "AXICLE1MR,Region ID Read Enable Register for AXICLE1MR" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "AXICLE2MR,Region ID Read Enable Register for AXICLE2MR" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "AXICLE3MR,Region ID Read Enable Register for AXICLE3MR" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "AXIDISP0MR,Region ID Read Enable Register for AXIDISP0MR" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "AXIDISP1MR,Region ID Read Enable Register for AXIDISP1MR" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "AXIFCPRAVIP1MA,Region ID Read Enable Register for AXIFCPRAVIP1MA" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "AXIFCPRAVIP2MA,Region ID Read Enable Register for AXIFCPRAVIP2MA" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "AXISMPS1MR,Region ID Read Enable Register for AXISMPS1MR" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "AXIUMFL1MR,Region ID Read Enable Register for AXIUMFL1MR" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "AXIUMFL1MW,Region ID Read Enable Register for AXIUMFL1MW" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC82400++0x67 line.long 0x0 "ARMGC0,Region ID Write Enable Register for ARMGC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARMGC1,Region ID Write Enable Register for ARMGC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARMGC2,Region ID Write Enable Register for ARMGC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARRT00,Region ID Write Enable Register for ARRT 00" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARRT01,Region ID Write Enable Register for ARRT 01" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARRT02,Region ID Write Enable Register for ARRT 02" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARRT03,Region ID Write Enable Register for ARRT 03" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARRT04,Region ID Write Enable Register for ARRT 04" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARRT05,Region ID Write Enable Register for ARRT 05" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARRT06,Region ID Write Enable Register for ARRT 06" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ARRT07,Region ID Write Enable Register for ARRT 07" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ARRT08,Region ID Write Enable Register for ARRT 08" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "LIFEC0,Region ID Write Enable Register for LIFEC 0" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "SWDT,Region ID Write Enable Register for SWDT" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "TMU0,Region ID Write Enable Register for TMU 0" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "WDT,Region ID Write Enable Register for WDT" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "WWDT0,Region ID Write Enable Register for WWDT 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "WWDT1,Region ID Write Enable Register for WWDT 1" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "WWDT2,Region ID Write Enable Register for WWDT 2" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "WWDT3,Region ID Write Enable Register for WWDT 3" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "WWDT4,Region ID Write Enable Register for WWDT 4" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "WWDT5,Region ID Write Enable Register for WWDT 5" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "WWDT6,Region ID Write Enable Register for WWDT 6" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "WWDT7,Region ID Write Enable Register for WWDT 7" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "WWDT8,Region ID Write Enable Register for WWDT 8" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "WWDT9,Region ID Write Enable Register for WWDT 9" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE6002400++0x77 line.long 0x0 "ADVFSC,Region ID Write Enable Register for ADVFSC" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "APMU0,Region ID Write Enable Register for APMU 0" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "APMU1,Region ID Write Enable Register for APMU 1" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "APMU10,Region ID Write Enable Register for APMU 10" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "APMU11,Region ID Write Enable Register for APMU 11" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "APMU12,Region ID Write Enable Register for APMU 12" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "APMU13,Region ID Write Enable Register for APMU 13" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "APMU14,Region ID Write Enable Register for APMU 14" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "APMU15,Region ID Write Enable Register for APMU 15" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "APMU2,Region ID Write Enable Register for APMU 2" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "APMU3,Region ID Write Enable Register for APMU 3" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "APMU4,Region ID Write Enable Register for APMU 4" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "APMU5,Region ID Write Enable Register for APMU 5" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "APMU6,Region ID Write Enable Register for APMU 6" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "APMU7,Region ID Write Enable Register for APMU 7" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "APMU8,Region ID Write Enable Register for APMU 8" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "APMU9,Region ID Write Enable Register for APMU 9" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ARS00,Region ID Write Enable Register for ARS 00" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ARS01,Region ID Write Enable Register for ARS 01" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "ARS02,Region ID Write Enable Register for ARS 02" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "ARS03,Region ID Write Enable Register for ARS 03" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "ARS04,Region ID Write Enable Register for ARS 04" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "ARS05,Region ID Write Enable Register for ARS 05" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "ARS06,Region ID Write Enable Register for ARS 06" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "ARS07,Region ID Write Enable Register for ARS 07" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "ARS08,Region ID Write Enable Register for ARS 08" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "CMT0,Region ID Write Enable Register for CMT 0" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "CMT1,Region ID Write Enable Register for CMT 1" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "CMT2,Region ID Write Enable Register for CMT 2" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "CMT3,Region ID Write Enable Register for CMT 3" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE600247C++0x7 line.long 0x0 "DBE,Region ID Write Enable Register for DBE" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "IRQC,Region ID Write Enable Register for IRQC" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE600249C++0x3 line.long 0x0 "SCMT,Region ID Write Enable Register for SCMT" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE60024A4++0x17 line.long 0x0 "TSC0,Region ID Write Enable Register for TSC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "TSC1,Region ID Write Enable Register for TSC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "TSC2,Region ID Write Enable Register for TSC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "TSC3,Region ID Write Enable Register for TSC 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "TSC4,Region ID Write Enable Register for TSC 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "UCMT,Region ID Write Enable Register for UCMT" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE6002500++0x7F line.long 0x0 "CPG0,Region ID Write Enable Register for CPG 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "CPG1,Region ID Write Enable Register for CPG 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "CPG2,Region ID Write Enable Register for CPG 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "CPG3,Region ID Write Enable Register for CPG 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "PFC00,Region ID Write Enable Register for PFC 00" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "PFC01,Region ID Write Enable Register for PFC 01" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "PFC02,Region ID Write Enable Register for PFC 02" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "PFC03,Region ID Write Enable Register for PFC 03" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "PFC10,Region ID Write Enable Register for PFC 10" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "PFC11,Region ID Write Enable Register for PFC 11" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "PFC12,Region ID Write Enable Register for PFC 12" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "PFC13,Region ID Write Enable Register for PFC 13" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "PFC20,Region ID Write Enable Register for PFC 20" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "PFC21,Region ID Write Enable Register for PFC 21" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "PFC22,Region ID Write Enable Register for PFC 22" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "PFC23,Region ID Write Enable Register for PFC 23" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "PFC30,Region ID Write Enable Register for PFC 30" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "PFC31,Region ID Write Enable Register for PFC 31" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "PFC32,Region ID Write Enable Register for PFC 32" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "PFC33,Region ID Write Enable Register for PFC 33" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "PFCS0,Region ID Write Enable Register for PFCS 0" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "PFCS1,Region ID Write Enable Register for PFCS 1" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "PFCS2,Region ID Write Enable Register for PFCS 2" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "PFCS3,Region ID Write Enable Register for PFCS 3" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "RESET0,Region ID Write Enable Register for RESET 0" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "RESET1,Region ID Write Enable Register for RESET 1" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "RESET2,Region ID Write Enable Register for RESET 2" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "RESET3,Region ID Write Enable Register for RESET 3" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "SYS0,Region ID Write Enable Register for SYS 0" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "SYS1,Region ID Write Enable Register for SYS 1" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "SYS2,Region ID Write Enable Register for SYS 2" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "SYS3,Region ID Write Enable Register for SYS 3" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7792400++0x17 line.long 0x0 "DMAMSI0,Region ID Write Enable Register for DMAMSI 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "DMAMSI1,Region ID Write Enable Register for DMAMSI 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "DMAMSI2,Region ID Write Enable Register for DMAMSI 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "DMAMSI3,Region ID Write Enable Register for DMAMSI 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "DMAMSI4,Region ID Write Enable Register for DMAMSI 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "DMAMSI5,Region ID Write Enable Register for DMAMSI 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7762400++0x5F line.long 0x0 "ARSD30,Region ID Write Enable Register for ARSD 30" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARSD31,Region ID Write Enable Register for ARSD 31" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSD32,Region ID Write Enable Register for ARSD 32" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSD33,Region ID Write Enable Register for ARSD 33" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSD34,Region ID Write Enable Register for ARSD 34" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARSD35,Region ID Write Enable Register for ARSD 35" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARSD36,Region ID Write Enable Register for ARSD 36" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARSD37,Region ID Write Enable Register for ARSD 37" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARSD38,Region ID Write Enable Register for ARSD 38" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARSP30,Region ID Write Enable Register for ARSP 30" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ARSP31,Region ID Write Enable Register for ARSP 31" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ARSP32,Region ID Write Enable Register for ARSP 32" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "ARSP33,Region ID Write Enable Register for ARSP 33" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "ARSP34,Region ID Write Enable Register for ARSP 34" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ARSP35,Region ID Write Enable Register for ARSP 35" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ARSP36,Region ID Write Enable Register for ARSP 36" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ARSP37,Region ID Write Enable Register for ARSP 37" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ARSP38,Region ID Write Enable Register for ARSP 38" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "MSI0,Region ID Write Enable Register for MSI 0" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "MSI1,Region ID Write Enable Register for MSI 1" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "MSI2,Region ID Write Enable Register for MSI 2" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "MSI3,Region ID Write Enable Register for MSI 3" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "MSI4,Region ID Write Enable Register for MSI 4" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "MSI5,Region ID Write Enable Register for MSI 5" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFF882400++0x6B line.long 0x0 "ARIMP00,Region ID Write Enable Register for ARIMP 00" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARIMP01,Region ID Write Enable Register for ARIMP 01" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARIMP02,Region ID Write Enable Register for ARIMP 02" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARIMP03,Region ID Write Enable Register for ARIMP 03" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARIMP04,Region ID Write Enable Register for ARIMP 04" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "AXIFBABUSIR0,Region ID Write Enable Register for AXIFBABUSIR 0" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "AXIFBABUSIR1,Region ID Write Enable Register for AXIFBABUSIR 1" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "AXIFBABUSIR2,Region ID Write Enable Register for AXIFBABUSIR 2" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "AXIFBABUSIR3,Region ID Write Enable Register for AXIFBABUSIR 3" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "AXIFBABUSIR4,Region ID Write Enable Register for AXIFBABUSIR 4" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "AXIIMP0,Region ID Write Enable Register for AXIIMP 0" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "AXIIMPD0,Region ID Write Enable Register for AXIIMPD 0" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "AXIIMPD1,Region ID Write Enable Register for AXIIMPD 1" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "ARIMP05,Region ID Write Enable Register for ARIMP 05" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ARIMP06,Region ID Write Enable Register for ARIMP 06" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ARIMP07,Region ID Write Enable Register for ARIMP 07" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ARIMP08,Region ID Write Enable Register for ARIMP 08" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "CKMIR,Region ID Write Enable Register for CKMIR" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ECMIR,Region ID Write Enable Register for ECMIR" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "AXIRADSP0,Region ID Write Enable Register for AXIRADSP 0" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "AXIRADSP1,Region ID Write Enable Register for AXIRADSP 1" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "IPMMUIR,Region ID Write Enable Register for IPMMUIR" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "AXIFCPRAIRMA,Region ID Write Enable Register for AXIFCPRAIRMA" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "AXIIMP0MR,Region ID Write Enable Register for AXIIMP0MR" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "AXIIMP0MW,Region ID Write Enable Register for AXIIMP0MW" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "AXIIMP1MR,Region ID Write Enable Register for AXIIMP1MR" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "AXIIMP1MW,Region ID Write Enable Register for AXIIMP1MW" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFD812400++0x47 line.long 0x0 "ARPV0,Region ID Write Enable Register for ARPV 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARPV1,Region ID Write Enable Register for ARPV 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "AXIRGX,Region ID Write Enable Register for AXIRGX" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARPV2,Region ID Write Enable Register for ARPV 2" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARPV3,Region ID Write Enable Register for ARPV 3" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARPV4,Region ID Write Enable Register for ARPV 4" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARPV5,Region ID Write Enable Register for ARPV 5" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARPV6,Region ID Write Enable Register for ARPV 6" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARPV7,Region ID Write Enable Register for ARPV 7" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARPV8,Region ID Write Enable Register for ARPV 8" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CKM3DG,Region ID Write Enable Register for CKM3DG" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ECMU3DG,Region ID Write Enable Register for ECMU3DG" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "FBAPVC,Region ID Write Enable Register for FBAPVC" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "FBAPVD0,Region ID Write Enable Register for FBAPVD 0" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "FBAPVD1,Region ID Write Enable Register for FBAPVD 1" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "FBAPVD2,Region ID Write Enable Register for FBAPVD 2" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "FBAPVE,Region ID Write Enable Register for FBAPVE" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "IPMMUPV0,Region ID Write Enable Register for IPMMUPV 0" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE6622400++0x2B line.long 0x0 "ARRC0,Region ID Write Enable Register for ARRC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARRC1,Region ID Write Enable Register for ARRC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARRC2,Region ID Write Enable Register for ARRC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARRC3,Region ID Write Enable Register for ARRC 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARRC4,Region ID Write Enable Register for ARRC 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARRC5,Region ID Write Enable Register for ARRC 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARRC6,Region ID Write Enable Register for ARRC 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARRC7,Region ID Write Enable Register for ARRC 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARRC8,Region ID Write Enable Register for ARRC 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "CR0,Region ID Write Enable Register for CR 0" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ICUMX,Region ID Write Enable Register for ICUMX" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC32400++0xF line.long 0x0 "AXIDMAWCRC0,Region ID Write Enable Register for AXIDMAWCRC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "AXIDMAWCRC1,Region ID Write Enable Register for AXIDMAWCRC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "AXIDMAWCRC2,Region ID Write Enable Register for AXIDMAWCRC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "AXIDMAWCRC3,Region ID Write Enable Register for AXIDMAWCRC 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC42400++0x2B line.long 0x0 "ARMREG0,Region ID Write Enable Register for ARMREG 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARMREG1,Region ID Write Enable Register for ARMREG 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARMREG10,Region ID Write Enable Register for ARMREG 10" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARMREG11,Region ID Write Enable Register for ARMREG 11" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARMREG12,Region ID Write Enable Register for ARMREG 12" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARMREG13,Region ID Write Enable Register for ARMREG 13" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARMREG14,Region ID Write Enable Register for ARMREG 14" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "AXICR52SS,Region ID Write Enable Register for AXICR52SS" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "AXICSD0,Region ID Write Enable Register for AXICSD 0" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "AXIINTAP0,Region ID Write Enable Register for AXIINTAP 0" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "AXIINTAP1,Region ID Write Enable Register for AXIINTAP 1" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC42430++0xE7 line.long 0x0 "AXISYSRAM0,Region ID Write Enable Register for AXISYSRAM 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "AXISYSRAM1,Region ID Write Enable Register for AXISYSRAM 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARMREG15,Region ID Write Enable Register for ARMREG 15" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARMREG2,Region ID Write Enable Register for ARMREG 2" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARMREG3,Region ID Write Enable Register for ARMREG 3" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARMREG4,Region ID Write Enable Register for ARMREG 4" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARMREG5,Region ID Write Enable Register for ARMREG 5" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARMREG6,Region ID Write Enable Register for ARMREG 6" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARMREG7,Region ID Write Enable Register for ARMREG 7" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARMREG8,Region ID Write Enable Register for ARMREG 8" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ARMREG9,Region ID Write Enable Register for ARMREG 9" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ARRD0,Region ID Write Enable Register for ARRD 0" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "ARRD1,Region ID Write Enable Register for ARRD 1" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "ARRD2,Region ID Write Enable Register for ARRD 2" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ARRD3,Region ID Write Enable Register for ARRD 3" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ARRD4,Region ID Write Enable Register for ARRD 4" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ARRD5,Region ID Write Enable Register for ARRD 5" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ARRD6,Region ID Write Enable Register for ARRD 6" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ARRD7,Region ID Write Enable Register for ARRD 7" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "ARRD8,Region ID Write Enable Register for ARRD 8" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "ARRT0,Region ID Write Enable Register for ARRT 0" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "ARRT1,Region ID Write Enable Register for ARRT 1" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "ARRT2,Region ID Write Enable Register for ARRT 2" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "ARRT3,Region ID Write Enable Register for ARRT 3" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "ARRT4,Region ID Write Enable Register for ARRT 4" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "ARRT5,Region ID Write Enable Register for ARRT 5" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "ARRT6,Region ID Write Enable Register for ARRT 6" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "ARRT7,Region ID Write Enable Register for ARRT 7" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "ARRT8,Region ID Write Enable Register for ARRT 8" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "CKMRT,Region ID Write Enable Register for CKMRT" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "CRC0,Region ID Write Enable Register for CRC 0" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "CRC1,Region ID Write Enable Register for CRC 1" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "CRC2,Region ID Write Enable Register for CRC 2" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "CRC3,Region ID Write Enable Register for CRC 3" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "CSD,Region ID Write Enable Register for CSD" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "ECM,Region ID Write Enable Register for ECM" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "ECMRT,Region ID Write Enable Register for ECMRT" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "FBACR52,Region ID Write Enable Register for FBACR 52" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "FBART,Region ID Write Enable Register for FBART" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "INTTP,Region ID Write Enable Register for INTTP" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "IPMMURT0,Region ID Write Enable Register for IPMMURT 0" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "IPMMURT1,Region ID Write Enable Register for IPMMURT 1" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "KCRC4,Region ID Write Enable Register for KCRC 4" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "KCRC5,Region ID Write Enable Register for KCRC 5" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "KCRC6,Region ID Write Enable Register for KCRC 6" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "KCRC7,Region ID Write Enable Register for KCRC 7" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "MFI0,Region ID Write Enable Register for MFI 0" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "MFI1,Region ID Write Enable Register for MFI 1" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "MFI10,Region ID Write Enable Register for MFI 10" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "MFI2,Region ID Write Enable Register for MFI 2" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "MFI3,Region ID Write Enable Register for MFI 3" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "MFI4,Region ID Write Enable Register for MFI 4" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "MFI5,Region ID Write Enable Register for MFI 5" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "MFI6,Region ID Write Enable Register for MFI 6" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "MFI7,Region ID Write Enable Register for MFI 7" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" line.long 0xDC "MFI8,Region ID Write Enable Register for MFI 8" hexmask.long.word 0xDC 0.--15. 1. "RGIDEN" line.long 0xE0 "MFI9,Region ID Write Enable Register for MFI 9" hexmask.long.word 0xE0 0.--15. 1. "RGIDEN" line.long 0xE4 "PRR,Region ID Write Enable Register for PRR" hexmask.long.word 0xE4 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC4251C++0x3 line.long 0x0 "RTDM0P,Region ID Write Enable Register for RTDM0P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC42524++0x3 line.long 0x0 "RTDM1P,Region ID Write Enable Register for RTDM1P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC4252C++0x3 line.long 0x0 "RTDM2P,Region ID Write Enable Register for RTDM2P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC42534++0x3F line.long 0x0 "RTDM3P,Region ID Write Enable Register for RTDM3P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "SYSRAM0,Region ID Write Enable Register for SYSRAM 0" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "TSIPL0,Region ID Write Enable Register for TSIPL 0" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "TSIPL1,Region ID Write Enable Register for TSIPL 1" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "TSIPL2,Region ID Write Enable Register for TSIPL 2" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "TSIPL3,Region ID Write Enable Register for TSIPL 3" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "TSIPL4,Region ID Write Enable Register for TSIPL 4" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "TSIPL5,Region ID Write Enable Register for TSIPL 5" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "TSIPL6,Region ID Write Enable Register for TSIPL 6" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "TSIPL7,Region ID Write Enable Register for TSIPL 7" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "WCRC0,Region ID Write Enable Register for WCRC 0" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "WCRC1,Region ID Write Enable Register for WCRC 1" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "WCRC2,Region ID Write Enable Register for WCRC 2" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "WCRC3,Region ID Write Enable Register for WCRC 3" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "AXIFCPRART0MA,Region ID Write Enable Register for AXIFCPRART0MA" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "AXIMEMRTDM0MR,Region ID Write Enable Register for AXIMEMRTDM0MR" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC42600++0xFF line.long 0x0 "RTDM000,Region ID Write Enable Register for RTDM 000" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "RTDM001,Region ID Write Enable Register for RTDM 001" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "RTDM010,Region ID Write Enable Register for RTDM 010" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "RTDM011,Region ID Write Enable Register for RTDM 011" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "RTDM012,Region ID Write Enable Register for RTDM 012" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "RTDM013,Region ID Write Enable Register for RTDM 013" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "RTDM014,Region ID Write Enable Register for RTDM 014" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "RTDM015,Region ID Write Enable Register for RTDM 015" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "RTDM002,Region ID Write Enable Register for RTDM 002" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "RTDM003,Region ID Write Enable Register for RTDM 003" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "RTDM004,Region ID Write Enable Register for RTDM 004" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "RTDM005,Region ID Write Enable Register for RTDM 005" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "RTDM006,Region ID Write Enable Register for RTDM 006" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "RTDM007,Region ID Write Enable Register for RTDM 007" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "RTDM008,Region ID Write Enable Register for RTDM 008" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "RTDM009,Region ID Write Enable Register for RTDM 009" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "RTDM100,Region ID Write Enable Register for RTDM 100" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "RTDM101,Region ID Write Enable Register for RTDM 101" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "RTDM110,Region ID Write Enable Register for RTDM 110" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "RTDM111,Region ID Write Enable Register for RTDM 111" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "RTDM112,Region ID Write Enable Register for RTDM 112" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "RTDM113,Region ID Write Enable Register for RTDM 113" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "RTDM114,Region ID Write Enable Register for RTDM 114" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "RTDM115,Region ID Write Enable Register for RTDM 115" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "RTDM102,Region ID Write Enable Register for RTDM 102" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "RTDM103,Region ID Write Enable Register for RTDM 103" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "RTDM104,Region ID Write Enable Register for RTDM 104" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "RTDM105,Region ID Write Enable Register for RTDM 105" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "RTDM106,Region ID Write Enable Register for RTDM 106" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "RTDM107,Region ID Write Enable Register for RTDM 107" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "RTDM108,Region ID Write Enable Register for RTDM 108" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "RTDM109,Region ID Write Enable Register for RTDM 109" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "RTDM200,Region ID Write Enable Register for RTDM 200" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "RTDM201,Region ID Write Enable Register for RTDM 201" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "RTDM210,Region ID Write Enable Register for RTDM 210" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "RTDM211,Region ID Write Enable Register for RTDM 211" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "RTDM212,Region ID Write Enable Register for RTDM 212" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "RTDM213,Region ID Write Enable Register for RTDM 213" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "RTDM214,Region ID Write Enable Register for RTDM 214" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "RTDM215,Region ID Write Enable Register for RTDM 215" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "RTDM202,Region ID Write Enable Register for RTDM 202" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "RTDM203,Region ID Write Enable Register for RTDM 203" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "RTDM204,Region ID Write Enable Register for RTDM 204" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "RTDM205,Region ID Write Enable Register for RTDM 205" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "RTDM206,Region ID Write Enable Register for RTDM 206" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "RTDM207,Region ID Write Enable Register for RTDM 207" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "RTDM208,Region ID Write Enable Register for RTDM 208" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "RTDM209,Region ID Write Enable Register for RTDM 209" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "RTDM300,Region ID Write Enable Register for RTDM 300" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "RTDM301,Region ID Write Enable Register for RTDM 301" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "RTDM310,Region ID Write Enable Register for RTDM 310" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "RTDM311,Region ID Write Enable Register for RTDM 311" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "RTDM312,Region ID Write Enable Register for RTDM 312" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "RTDM313,Region ID Write Enable Register for RTDM 313" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "RTDM314,Region ID Write Enable Register for RTDM 314" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" line.long 0xDC "RTDM315,Region ID Write Enable Register for RTDM 315" hexmask.long.word 0xDC 0.--15. 1. "RGIDEN" line.long 0xE0 "RTDM302,Region ID Write Enable Register for RTDM 302" hexmask.long.word 0xE0 0.--15. 1. "RGIDEN" line.long 0xE4 "RTDM303,Region ID Write Enable Register for RTDM 303" hexmask.long.word 0xE4 0.--15. 1. "RGIDEN" line.long 0xE8 "RTDM304,Region ID Write Enable Register for RTDM 304" hexmask.long.word 0xE8 0.--15. 1. "RGIDEN" line.long 0xEC "RTDM305,Region ID Write Enable Register for RTDM 305" hexmask.long.word 0xEC 0.--15. 1. "RGIDEN" line.long 0xF0 "RTDM306,Region ID Write Enable Register for RTDM 306" hexmask.long.word 0xF0 0.--15. 1. "RGIDEN" line.long 0xF4 "RTDM307,Region ID Write Enable Register for RTDM 307" hexmask.long.word 0xF4 0.--15. 1. "RGIDEN" line.long 0xF8 "RTDM308,Region ID Write Enable Register for RTDM 308" hexmask.long.word 0xF8 0.--15. 1. "RGIDEN" line.long 0xFC "RTDM309,Region ID Write Enable Register for RTDM 309" hexmask.long.word 0xFC 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFF862400++0x9F line.long 0x0 "ARSC0,Region ID Write Enable Register for ARSC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARSC1,Region ID Write Enable Register for ARSC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSC2,Region ID Write Enable Register for ARSC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSC3,Region ID Write Enable Register for ARSC 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSC4,Region ID Write Enable Register for ARSC 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARSC5,Region ID Write Enable Register for ARSC 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARSC6,Region ID Write Enable Register for ARSC 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARSC7,Region ID Write Enable Register for ARSC 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARSC8,Region ID Write Enable Register for ARSC 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARSTM0,Region ID Write Enable Register for ARSTM 0" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ARSTM1,Region ID Write Enable Register for ARSTM 1" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "AXICSD1SRS,Region ID Write Enable Register for AXICSD1SRS" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "AXIFBABUSTOP0S,Region ID Write Enable Register for AXIFBABUSTOP0S" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "AXIFBABUSTOP1S,Region ID Write Enable Register for AXIFBABUSTOP1S" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ARSTM2,Region ID Write Enable Register for ARSTM 2" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ARSTM3,Region ID Write Enable Register for ARSTM 3" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ARSTM4,Region ID Write Enable Register for ARSTM 4" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ARSTM5,Region ID Write Enable Register for ARSTM 5" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ARSTM6,Region ID Write Enable Register for ARSTM 6" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "ARSTM7,Region ID Write Enable Register for ARSTM 7" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "ARSTM8,Region ID Write Enable Register for ARSTM 8" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "ECMTOP,Region ID Write Enable Register for ECMTOP" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "FBA,Region ID Write Enable Register for FBA" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "FBC,Region ID Write Enable Register for FBC" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "AXICCIS0SRS0,Region ID Write Enable Register for AXICCIS0SRS 0" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "AXICCIS0SRS1,Region ID Write Enable Register for AXICCIS0SRS 1" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "AXICCIS0SRS10,Region ID Write Enable Register for AXICCIS0SRS 10" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "AXICCIS0SRS11,Region ID Write Enable Register for AXICCIS0SRS 11" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "AXICCIS0SRS12,Region ID Write Enable Register for AXICCIS0SRS 12" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "AXICCIS0SRS13,Region ID Write Enable Register for AXICCIS0SRS 13" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "AXICCIS0SRS14,Region ID Write Enable Register for AXICCIS0SRS 14" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "AXICCIS0SRS15,Region ID Write Enable Register for AXICCIS0SRS 15" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "AXICCIS0SRS2,Region ID Write Enable Register for AXICCIS0SRS 2" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "AXICCIS0SRS3,Region ID Write Enable Register for AXICCIS0SRS 3" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "AXICCIS0SRS4,Region ID Write Enable Register for AXICCIS0SRS 4" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "AXICCIS0SRS5,Region ID Write Enable Register for AXICCIS0SRS 5" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "AXICCIS0SRS6,Region ID Write Enable Register for AXICCIS0SRS 6" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "AXICCIS0SRS7,Region ID Write Enable Register for AXICCIS0SRS 7" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "AXICCIS0SRS8,Region ID Write Enable Register for AXICCIS0SRS 8" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "AXICCIS0SRS9,Region ID Write Enable Register for AXICCIS0SRS 9" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7782000++0x43 line.long 0x0 "RGIDRDMACANFD,Region ID Write Enable Register for RGIDRDMACANFD" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "RGIDRDMAHSCIF0,Region ID Write Enable Register for RGIDRDMAHSCIF 0" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "RGIDRDMAHSCIF1,Region ID Write Enable Register for RGIDRDMAHSCIF 1" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "RGIDRDMAHSCIF2,Region ID Write Enable Register for RGIDRDMAHSCIF 2" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "RGIDRDMAHSCIF3,Region ID Write Enable Register for RGIDRDMAHSCIF 3" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "RGIDRDMAI2C0,Region ID Write Enable Register for RGIDRDMAI2C 0" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "RGIDRDMAI2C1,Region ID Write Enable Register for RGIDRDMAI2C 1" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "RGIDRDMAI2C2,Region ID Write Enable Register for RGIDRDMAI2C 2" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "RGIDRDMAI2C3,Region ID Write Enable Register for RGIDRDMAI2C 3" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "RGIDRDMAI2C4,Region ID Write Enable Register for RGIDRDMAI2C 4" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "RGIDRDMAI2C5,Region ID Write Enable Register for RGIDRDMAI2C 5" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "RGIDRDMAI2C6,Region ID Write Enable Register for RGIDRDMAI2C 6" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "RGIDRDMASCIF0,Region ID Write Enable Register for RGIDRDMASCIF 0" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "RGIDRDMASCIF1,Region ID Write Enable Register for RGIDRDMASCIF 1" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "RGIDRDMASCIF3,Region ID Write Enable Register for RGIDRDMASCIF 3" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "RGIDRDMASCIF4,Region ID Write Enable Register for RGIDRDMASCIF 4" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "RGIDRDMATPU0,Region ID Write Enable Register for RGIDRDMATPU 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7782400++0x43 line.long 0x0 "DMACANFD,Region ID Write Enable Register for DMACANFD" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "DMAHSCIF0,Region ID Write Enable Register for DMAHSCIF 0" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "DMAHSCIF1,Region ID Write Enable Register for DMAHSCIF 1" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "DMAHSCIF2,Region ID Write Enable Register for DMAHSCIF 2" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "DMAHSCIF3,Region ID Write Enable Register for DMAHSCIF 3" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "DMAI2C0,Region ID Write Enable Register for DMAI2C 0" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "DMAI2C1,Region ID Write Enable Register for DMAI2C 1" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "DMAI2C2,Region ID Write Enable Register for DMAI2C 2" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "DMAI2C3,Region ID Write Enable Register for DMAI2C 3" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "DMAI2C4,Region ID Write Enable Register for DMAI2C 4" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "DMAI2C5,Region ID Write Enable Register for DMAI2C 5" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "DMAI2C6,Region ID Write Enable Register for DMAI2C 6" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "DMASCIF0,Region ID Write Enable Register for DMASCIF 0" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "DMASCIF1,Region ID Write Enable Register for DMASCIF 1" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "DMASCIF3,Region ID Write Enable Register for DMASCIF 3" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "DMASCIF4,Region ID Write Enable Register for DMASCIF 4" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "DMATPU0,Region ID Write Enable Register for DMATPU 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE67C2400++0x13 line.long 0x0 "ARMM,Region ID Write Enable Register for ARMM" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "AXIARNMMS,Region ID Write Enable Register for AXIARNMMS" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSM0,Region ID Write Enable Register for ARSM 0" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSM1,Region ID Write Enable Register for ARSM 1" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSM2,Region ID Write Enable Register for ARSM 2" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE67C2434++0x4B line.long 0x0 "ARSM3,Region ID Write Enable Register for ARSM 3" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARSM4,Region ID Write Enable Register for ARSM 4" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSM5,Region ID Write Enable Register for ARSM 5" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSM6,Region ID Write Enable Register for ARSM 6" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSM7,Region ID Write Enable Register for ARSM 7" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARSM8,Region ID Write Enable Register for ARSM 8" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "AXMM0,Region ID Write Enable Register for AXMM 0" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "AXMM1,Region ID Write Enable Register for AXMM 1" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "AXMMPMON,Region ID Write Enable Register for AXMMPMON" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "CKMMM,Region ID Write Enable Register for CKMMM" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "ECMMM,Region ID Write Enable Register for ECMMM" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "FBADBSC0,Region ID Write Enable Register for FBADBSC 0" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "FBADBSC1,Region ID Write Enable Register for FBADBSC 1" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "FBAMM,Region ID Write Enable Register for FBAMM" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "IPMMUMM,Region ID Write Enable Register for IPMMUMM" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "AXIDBS0S0,Region ID Write Enable Register for AXIDBS0S 0" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "AXIDBS0S1,Region ID Write Enable Register for AXIDBS0S 1" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "AXIDBS1S0,Region ID Write Enable Register for AXIDBS1S 0" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "AXIDBS1S1,Region ID Write Enable Register for AXIDBS1S 1" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFF802400++0x23 line.long 0x0 "ARSN0,Region ID Write Enable Register for ARSN 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARSN1,Region ID Write Enable Register for ARSN 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSN2,Region ID Write Enable Register for ARSN 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSN3,Region ID Write Enable Register for ARSN 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSN4,Region ID Write Enable Register for ARSN 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARSN5,Region ID Write Enable Register for ARSN 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARSN6,Region ID Write Enable Register for ARSN 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARSN7,Region ID Write Enable Register for ARSN 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARSN8,Region ID Write Enable Register for ARSN 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7752400++0xEF line.long 0x0 "ARSD00,Region ID Write Enable Register for ARSD 00" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARSD01,Region ID Write Enable Register for ARSD 01" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARSD02,Region ID Write Enable Register for ARSD 02" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARSD03,Region ID Write Enable Register for ARSD 03" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARSD04,Region ID Write Enable Register for ARSD 04" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARSD05,Region ID Write Enable Register for ARSD 05" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARSD06,Region ID Write Enable Register for ARSD 06" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "AXIFRAYS,Region ID Write Enable Register for AXIFRAYS" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "AXIIPCS,Region ID Write Enable Register for AXIIPCS" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "AXILBSS,Region ID Write Enable Register for AXILBSS" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "AXIRPCS,Region ID Write Enable Register for AXIRPCS" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "AXISDHI0S,Region ID Write Enable Register for AXISDHI0S" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "ARSD07,Region ID Write Enable Register for ARSD 07" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "ARSD08,Region ID Write Enable Register for ARSD 08" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ARSP00,Region ID Write Enable Register for ARSP 00" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ARSP01,Region ID Write Enable Register for ARSP 01" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ARSP02,Region ID Write Enable Register for ARSP 02" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ARSP03,Region ID Write Enable Register for ARSP 03" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ARSP04,Region ID Write Enable Register for ARSP 04" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "ARSP05,Region ID Write Enable Register for ARSP 05" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "ARSP06,Region ID Write Enable Register for ARSP 06" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "ARSP07,Region ID Write Enable Register for ARSP 07" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "ARSP08,Region ID Write Enable Register for ARSP 08" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "CANFD,Region ID Write Enable Register for CANFD" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "CKMPE0,Region ID Write Enable Register for CKMPE 0" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "ECMPER0,Region ID Write Enable Register for ECMPER 0" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "FBAPER0,Region ID Write Enable Register for FBAPER 0" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "FSO0,Region ID Write Enable Register for FSO 0" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "FSO1,Region ID Write Enable Register for FSO 1" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "FSO10,Region ID Write Enable Register for FSO 10" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "FSO2,Region ID Write Enable Register for FSO 2" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "FSO3,Region ID Write Enable Register for FSO 3" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "FSO4,Region ID Write Enable Register for FSO 4" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "FSO5,Region ID Write Enable Register for FSO 5" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "FSO6,Region ID Write Enable Register for FSO 6" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "FSO7,Region ID Write Enable Register for FSO 7" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "FSO8,Region ID Write Enable Register for FSO 8" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "FSO9,Region ID Write Enable Register for FSO 9" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "HSCIF0,Region ID Write Enable Register for HSCIF 0" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "HSCIF1,Region ID Write Enable Register for HSCIF 1" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "HSCIF2,Region ID Write Enable Register for HSCIF 2" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "HSCIF3,Region ID Write Enable Register for HSCIF 3" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "I2C0,Region ID Write Enable Register for I2C 0" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "I2C1,Region ID Write Enable Register for I2C 1" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "I2C2,Region ID Write Enable Register for I2C 2" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "I2C3,Region ID Write Enable Register for I2C 3" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "I2C4,Region ID Write Enable Register for I2C 4" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "I2C5,Region ID Write Enable Register for I2C 5" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "I2C6,Region ID Write Enable Register for I2C 6" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "IPC,Region ID Write Enable Register for IPC" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "IPMMUDS0,Region ID Write Enable Register for IPMMUDS 0" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "PWM0,Region ID Write Enable Register for PWM 0" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "PWM1,Region ID Write Enable Register for PWM 1" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "PWM2,Region ID Write Enable Register for PWM 2" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "PWM3,Region ID Write Enable Register for PWM 3" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" line.long 0xDC "PWM4,Region ID Write Enable Register for PWM 4" hexmask.long.word 0xDC 0.--15. 1. "RGIDEN" line.long 0xE0 "SCIF0,Region ID Write Enable Register for SCIF 0" hexmask.long.word 0xE0 0.--15. 1. "RGIDEN" line.long 0xE4 "SCIF1,Region ID Write Enable Register for SCIF 1" hexmask.long.word 0xE4 0.--15. 1. "RGIDEN" line.long 0xE8 "SCIF3,Region ID Write Enable Register for SCIF 3" hexmask.long.word 0xE8 0.--15. 1. "RGIDEN" line.long 0xEC "SCIF4,Region ID Write Enable Register for SCIF 4" hexmask.long.word 0xEC 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE77524F4++0x3 line.long 0x0 "SYDM1P,Region ID Write Enable Register for SYDM1P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE77524FC++0x17 line.long 0x0 "SYDM2P,Region ID Write Enable Register for SYDM2P" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "TMU1,Region ID Write Enable Register for TMU 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "TMU2,Region ID Write Enable Register for TMU 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "TMU3,Region ID Write Enable Register for TMU 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "TMU4,Region ID Write Enable Register for TMU 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "TPU0,Region ID Write Enable Register for TPU 0" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7752640++0x7F line.long 0x0 "SYDM100,Region ID Write Enable Register for SYDM 100" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "SYDM101,Region ID Write Enable Register for SYDM 101" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "SYDM110,Region ID Write Enable Register for SYDM 110" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "SYDM111,Region ID Write Enable Register for SYDM 111" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "SYDM112,Region ID Write Enable Register for SYDM 112" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "SYDM113,Region ID Write Enable Register for SYDM 113" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "SYDM114,Region ID Write Enable Register for SYDM 114" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "SYDM115,Region ID Write Enable Register for SYDM 115" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "SYDM102,Region ID Write Enable Register for SYDM 102" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "SYDM103,Region ID Write Enable Register for SYDM 103" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "SYDM104,Region ID Write Enable Register for SYDM 104" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "SYDM105,Region ID Write Enable Register for SYDM 105" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "SYDM106,Region ID Write Enable Register for SYDM 106" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "SYDM107,Region ID Write Enable Register for SYDM 107" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "SYDM108,Region ID Write Enable Register for SYDM 108" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "SYDM109,Region ID Write Enable Register for SYDM 109" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "SYDM200,Region ID Write Enable Register for SYDM 200" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "SYDM201,Region ID Write Enable Register for SYDM 201" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "SYDM210,Region ID Write Enable Register for SYDM 210" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "SYDM211,Region ID Write Enable Register for SYDM 211" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "SYDM212,Region ID Write Enable Register for SYDM 212" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "SYDM213,Region ID Write Enable Register for SYDM 213" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "SYDM214,Region ID Write Enable Register for SYDM 214" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "SYDM215,Region ID Write Enable Register for SYDM 215" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "SYDM202,Region ID Write Enable Register for SYDM 202" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "SYDM203,Region ID Write Enable Register for SYDM 203" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "SYDM204,Region ID Write Enable Register for SYDM 204" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "SYDM205,Region ID Write Enable Register for SYDM 205" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "SYDM206,Region ID Write Enable Register for SYDM 206" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "SYDM207,Region ID Write Enable Register for SYDM 207" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "SYDM208,Region ID Write Enable Register for SYDM 208" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "SYDM209,Region ID Write Enable Register for SYDM 209" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE6582400++0x15F line.long 0x0 "AXIPCI0S0,Region ID Write Enable Register for AXIPCI0S 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "AXIPCI0S1,Region ID Write Enable Register for AXIPCI0S 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "AXIPCI0S2,Region ID Write Enable Register for AXIPCI0S 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "AXIPCI0S3,Region ID Write Enable Register for AXIPCI0S 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "AXIPCI0S4,Region ID Write Enable Register for AXIPCI0S 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "AXIPCI0S5,Region ID Write Enable Register for AXIPCI0S 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "AXIPCI0S6,Region ID Write Enable Register for AXIPCI0S 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "AXIPCI0S7,Region ID Write Enable Register for AXIPCI0S 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "AXIPCI0S8,Region ID Write Enable Register for AXIPCI0S 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "AXIPCI0S9,Region ID Write Enable Register for AXIPCI0S 9" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "AXIPCI0S10,Region ID Write Enable Register for AXIPCI0S 10" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "AXIPCI0S11,Region ID Write Enable Register for AXIPCI0S 11" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "AXIPCI0S12,Region ID Write Enable Register for AXIPCI0S 12" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "AXIPCI0S13,Region ID Write Enable Register for AXIPCI0S 13" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "AXIPCI0S14,Region ID Write Enable Register for AXIPCI0S 14" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "AXIPCI0S15,Region ID Write Enable Register for AXIPCI0S 15" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "AXIPCI1S0,Region ID Write Enable Register for AXIPCI1S 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "AXIPCI1S1,Region ID Write Enable Register for AXIPCI1S 1" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "AXIPCI1S2,Region ID Write Enable Register for AXIPCI1S 2" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "AXIPCI1S3,Region ID Write Enable Register for AXIPCI1S 3" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "AXIPCI1S4,Region ID Write Enable Register for AXIPCI1S 4" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "AXIPCI1S5,Region ID Write Enable Register for AXIPCI1S 5" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "AXIPCI1S6,Region ID Write Enable Register for AXIPCI1S 6" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "AXIPCI1S7,Region ID Write Enable Register for AXIPCI1S 7" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "AXIPCI1S8,Region ID Write Enable Register for AXIPCI1S 8" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "AXIPCI1S9,Region ID Write Enable Register for AXIPCI1S 9" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "AXIPCI1S10,Region ID Write Enable Register for AXIPCI1S 10" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "AXIPCI1S11,Region ID Write Enable Register for AXIPCI1S 11" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "AXIPCI1S12,Region ID Write Enable Register for AXIPCI1S 12" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "AXIPCI1S13,Region ID Write Enable Register for AXIPCI1S 13" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "AXIPCI1S14,Region ID Write Enable Register for AXIPCI1S 14" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "AXIPCI1S15,Region ID Write Enable Register for AXIPCI1S 15" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "AXIPCI2S0,Region ID Write Enable Register for AXIPCI2S 0" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "AXIPCI2S1,Region ID Write Enable Register for AXIPCI2S 1" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "AXIPCI2S2,Region ID Write Enable Register for AXIPCI2S 2" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "AXIPCI2S3,Region ID Write Enable Register for AXIPCI2S 3" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "AXIPCI2S4,Region ID Write Enable Register for AXIPCI2S 4" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "AXIPCI2S5,Region ID Write Enable Register for AXIPCI2S 5" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "AXIPCI2S6,Region ID Write Enable Register for AXIPCI2S 6" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "AXIPCI2S7,Region ID Write Enable Register for AXIPCI2S 7" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "AXIPCI2S8,Region ID Write Enable Register for AXIPCI2S 8" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "AXIPCI2S9,Region ID Write Enable Register for AXIPCI2S 9" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "AXIPCI2S10,Region ID Write Enable Register for AXIPCI2S 10" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "AXIPCI2S11,Region ID Write Enable Register for AXIPCI2S 11" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "AXIPCI2S12,Region ID Write Enable Register for AXIPCI2S 12" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "AXIPCI2S13,Region ID Write Enable Register for AXIPCI2S 13" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "AXIPCI2S14,Region ID Write Enable Register for AXIPCI2S 14" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "AXIPCI2S15,Region ID Write Enable Register for AXIPCI2S 15" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "AXIPCI3S0,Region ID Write Enable Register for AXIPCI3S 0" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "AXIPCI3S1,Region ID Write Enable Register for AXIPCI3S 1" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "AXIPCI3S2,Region ID Write Enable Register for AXIPCI3S 2" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "AXIPCI3S3,Region ID Write Enable Register for AXIPCI3S 3" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "AXIPCI3S4,Region ID Write Enable Register for AXIPCI3S 4" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "AXIPCI3S5,Region ID Write Enable Register for AXIPCI3S 5" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "AXIPCI3S6,Region ID Write Enable Register for AXIPCI3S 6" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" line.long 0xDC "AXIPCI3S7,Region ID Write Enable Register for AXIPCI3S 7" hexmask.long.word 0xDC 0.--15. 1. "RGIDEN" line.long 0xE0 "AXIPCI3S8,Region ID Write Enable Register for AXIPCI3S 8" hexmask.long.word 0xE0 0.--15. 1. "RGIDEN" line.long 0xE4 "AXIPCI3S9,Region ID Write Enable Register for AXIPCI3S 9" hexmask.long.word 0xE4 0.--15. 1. "RGIDEN" line.long 0xE8 "AXIPCI3S10,Region ID Write Enable Register for AXIPCI3S 10" hexmask.long.word 0xE8 0.--15. 1. "RGIDEN" line.long 0xEC "AXIPCI3S11,Region ID Write Enable Register for AXIPCI3S 11" hexmask.long.word 0xEC 0.--15. 1. "RGIDEN" line.long 0xF0 "AXIPCI3S12,Region ID Write Enable Register for AXIPCI3S 12" hexmask.long.word 0xF0 0.--15. 1. "RGIDEN" line.long 0xF4 "AXIPCI3S13,Region ID Write Enable Register for AXIPCI3S 13" hexmask.long.word 0xF4 0.--15. 1. "RGIDEN" line.long 0xF8 "AXIPCI3S14,Region ID Write Enable Register for AXIPCI3S 14" hexmask.long.word 0xF8 0.--15. 1. "RGIDEN" line.long 0xFC "AXIPCI3S15,Region ID Write Enable Register for AXIPCI3S 15" hexmask.long.word 0xFC 0.--15. 1. "RGIDEN" line.long 0x100 "AVB0,Region ID Write Enable Register for AVB 0" hexmask.long.word 0x100 0.--15. 1. "RGIDEN" line.long 0x104 "AVB1,Region ID Write Enable Register for AVB 1" hexmask.long.word 0x104 0.--15. 1. "RGIDEN" line.long 0x108 "AVB2,Region ID Write Enable Register for AVB 2" hexmask.long.word 0x108 0.--15. 1. "RGIDEN" line.long 0x10C "AVB3,Region ID Write Enable Register for AVB 3" hexmask.long.word 0x10C 0.--15. 1. "RGIDEN" line.long 0x110 "AVB4,Region ID Write Enable Register for AVB 4" hexmask.long.word 0x110 0.--15. 1. "RGIDEN" line.long 0x114 "AVB5,Region ID Write Enable Register for AVB 5" hexmask.long.word 0x114 0.--15. 1. "RGIDEN" line.long 0x118 "ADG,Region ID Write Enable Register for ADG" hexmask.long.word 0x118 0.--15. 1. "RGIDEN" line.long 0x11C "PPHY0,Region ID Write Enable Register for PPHY 0" hexmask.long.word 0x11C 0.--15. 1. "RGIDEN" line.long 0x120 "PPHY1,Region ID Write Enable Register for PPHY 1" hexmask.long.word 0x120 0.--15. 1. "RGIDEN" line.long 0x124 "PPHY2,Region ID Write Enable Register for PPHY 2" hexmask.long.word 0x124 0.--15. 1. "RGIDEN" line.long 0x128 "PPHY3,Region ID Write Enable Register for PPHY 3" hexmask.long.word 0x128 0.--15. 1. "RGIDEN" line.long 0x12C "FBAPER1,Region ID Write Enable Register for FBAPER 1" hexmask.long.word 0x12C 0.--15. 1. "RGIDEN" line.long 0x130 "IPMMUDS1,Region ID Write Enable Register for IPMMUDS 1" hexmask.long.word 0x130 0.--15. 1. "RGIDEN" line.long 0x134 "CKMPE1,Region ID Write Enable Register for CKMPE 1" hexmask.long.word 0x134 0.--15. 1. "RGIDEN" line.long 0x138 "ECMPER1,Region ID Write Enable Register for ECMPER 1" hexmask.long.word 0x138 0.--15. 1. "RGIDEN" line.long 0x13C "ARSP10,Region ID Write Enable Register for ARSP 10" hexmask.long.word 0x13C 0.--15. 1. "RGIDEN" line.long 0x140 "ARSP11,Region ID Write Enable Register for ARSP 11" hexmask.long.word 0x140 0.--15. 1. "RGIDEN" line.long 0x144 "ARSP12,Region ID Write Enable Register for ARSP 12" hexmask.long.word 0x144 0.--15. 1. "RGIDEN" line.long 0x148 "ARSP13,Region ID Write Enable Register for ARSP 13" hexmask.long.word 0x148 0.--15. 1. "RGIDEN" line.long 0x14C "ARSP14,Region ID Write Enable Register for ARSP 14" hexmask.long.word 0x14C 0.--15. 1. "RGIDEN" line.long 0x150 "ARSP15,Region ID Write Enable Register for ARSP 15" hexmask.long.word 0x150 0.--15. 1. "RGIDEN" line.long 0x154 "ARSP16,Region ID Write Enable Register for ARSP 16" hexmask.long.word 0x154 0.--15. 1. "RGIDEN" line.long 0x158 "ARSP17,Region ID Write Enable Register for ARSP 17" hexmask.long.word 0x158 0.--15. 1. "RGIDEN" line.long 0x15C "ARSP18,Region ID Write Enable Register for ARSP 18" hexmask.long.word 0x15C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFE682400++0x7F line.long 0x0 "ARVC0,Region ID Write Enable Register for ARVC 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARVC1,Region ID Write Enable Register for ARVC 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARVC2,Region ID Write Enable Register for ARVC 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARVC3,Region ID Write Enable Register for ARVC 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "AXIFBABUSVCS,Region ID Write Enable Register for AXIFBABUSVCS" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARVC4,Region ID Write Enable Register for ARVC 4" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARVC5,Region ID Write Enable Register for ARVC 5" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARVC6,Region ID Write Enable Register for ARVC 6" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARVC7,Region ID Write Enable Register for ARVC 7" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARVC8,Region ID Write Enable Register for ARVC 8" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CKMVC,Region ID Write Enable Register for CKMVC" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ECMVC,Region ID Write Enable Register for ECMVC" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "FCPCS,Region ID Write Enable Register for FCPCS" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "IMR0,Region ID Write Enable Register for IMR 0" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "IMR1,Region ID Write Enable Register for IMR 1" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "IMR2,Region ID Write Enable Register for IMR 2" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "IMR3,Region ID Write Enable Register for IMR 3" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "IMS0,Region ID Write Enable Register for IMS 0" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "IMS1,Region ID Write Enable Register for IMS 1" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "IPMMUVC,Region ID Write Enable Register for IPMMUVC" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "IV1ES,Region ID Write Enable Register for IV1ES" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "VCP4LC,Region ID Write Enable Register for VCP4LC" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "VCP4LV,Region ID Write Enable Register for VCP4LV" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "AXIFCPRAVC0MA,Region ID Write Enable Register for AXIFCPRAVC0MA" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "AXIIMR00MR,Region ID Write Enable Register for AXIIMR00MR" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "AXIIMR0COMXW,Region ID Write Enable Register for AXIIMR0COMXW" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "AXIIMR10MR,Region ID Write Enable Register for AXIIMR10MR" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "AXIIMR1COMXW,Region ID Write Enable Register for AXIIMR1COMXW" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "AXIIMR20MR,Region ID Write Enable Register for AXIIMR20MR" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "AXIIMR30MR,Region ID Write Enable Register for AXIIMR30MR" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "AXIIMS0MR,Region ID Write Enable Register for AXIIMS0MR" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "AXIIMS1MR,Region ID Write Enable Register for AXIIMS1MR" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFEBE2400++0x93 line.long 0x0 "AXIFBABUSVIOS,Region ID Write Enable Register for AXIFBABUSVIOS" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARVI10,Region ID Write Enable Register for ARVI 10" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARVI11,Region ID Write Enable Register for ARVI 11" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARVI12,Region ID Write Enable Register for ARVI 12" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARVI13,Region ID Write Enable Register for ARVI 13" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARVI14,Region ID Write Enable Register for ARVI 14" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARVI15,Region ID Write Enable Register for ARVI 15" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARVI16,Region ID Write Enable Register for ARVI 16" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARVI17,Region ID Write Enable Register for ARVI 17" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARVI18,Region ID Write Enable Register for ARVI 18" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CKMVIO,Region ID Write Enable Register for CKMVIO" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "DIS0,Region ID Write Enable Register for DIS 0" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "DOC2CH,Region ID Write Enable Register for DOC2CH" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "DSITXLINK0,Region ID Write Enable Register for DSITXLINK 0" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "DSITXLINK1,Region ID Write Enable Register for DSITXLINK 1" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ECMVIO,Region ID Write Enable Register for ECMVIO" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "FCPVD0,Region ID Write Enable Register for FCPVD 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "FCPVD1,Region ID Write Enable Register for FCPVD 1" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "FCPVX0,Region ID Write Enable Register for FCPVX 0" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "FCPVX1,Region ID Write Enable Register for FCPVX 1" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "FCPVX2,Region ID Write Enable Register for FCPVX 2" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "FCPVX3,Region ID Write Enable Register for FCPVX 3" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "IPMMUVI0,Region ID Write Enable Register for IPMMUVI 0" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "IPMMUVI1,Region ID Write Enable Register for IPMMUVI 1" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "VSPD0,Region ID Write Enable Register for VSPD 0" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "VSPD1,Region ID Write Enable Register for VSPD 1" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "VSPX0,Region ID Write Enable Register for VSPX 0" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "VSPX1,Region ID Write Enable Register for VSPX 1" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "VSPX2,Region ID Write Enable Register for VSPX 2" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "VSPX3,Region ID Write Enable Register for VSPX 3" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "AXIFCPRAVI1MA,Region ID Write Enable Register for AXIFCPRAVI1MA" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "AXIFCPVD0MR,Region ID Write Enable Register for AXIFCPVD0MR" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "AXIFCPVD1MR,Region ID Write Enable Register for AXIFCPVD1MR" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "AXIFCPVX0MR,Region ID Write Enable Register for AXIFCPVX0MR" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "AXIFCPVX1MR,Region ID Write Enable Register for AXIFCPVX1MR" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "AXIFCPVX2MR,Region ID Write Enable Register for AXIFCPVX2MR" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "AXIFCPVX3MR,Region ID Write Enable Register for AXIFCPVX3MR" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFEBF2400++0xDB line.long 0x0 "ARVI0,Region ID Write Enable Register for ARVI 0" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARVI1,Region ID Write Enable Register for ARVI 1" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARVI2,Region ID Write Enable Register for ARVI 2" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARVI3,Region ID Write Enable Register for ARVI 3" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "ARVI4,Region ID Write Enable Register for ARVI 4" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARVI5,Region ID Write Enable Register for ARVI 5" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARVI6,Region ID Write Enable Register for ARVI 6" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARVI7,Region ID Write Enable Register for ARVI 7" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARVI8,Region ID Write Enable Register for ARVI 8" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "CSI4LNK0,Region ID Write Enable Register for CSI4LNK 0" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CSI4LNK1,Region ID Write Enable Register for CSI4LNK 1" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "CSI4LNK2,Region ID Write Enable Register for CSI4LNK 2" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "CSI4LNK3,Region ID Write Enable Register for CSI4LNK 3" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "ISP0,Region ID Write Enable Register for ISP 0" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "ISP0CORE,Region ID Write Enable Register for ISP0CORE" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "ISP1,Region ID Write Enable Register for ISP 1" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "ISP1CORE,Region ID Write Enable Register for ISP1CORE" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "ISP2,Region ID Write Enable Register for ISP 2" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "ISP2CORE,Region ID Write Enable Register for ISP2CORE" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "ISP3,Region ID Write Enable Register for ISP 3" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "ISP3CORE,Region ID Write Enable Register for ISP3CORE" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "VIN00,Region ID Write Enable Register for VIN 00" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "VIN01,Region ID Write Enable Register for VIN 01" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "VIN02,Region ID Write Enable Register for VIN 02" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "VIN03,Region ID Write Enable Register for VIN 03" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "VIN04,Region ID Write Enable Register for VIN 04" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "VIN05,Region ID Write Enable Register for VIN 05" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "VIN06,Region ID Write Enable Register for VIN 06" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "VIN07,Region ID Write Enable Register for VIN 07" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "VIN10,Region ID Write Enable Register for VIN 10" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "VIN11,Region ID Write Enable Register for VIN 11" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "VIN12,Region ID Write Enable Register for VIN 12" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" line.long 0x80 "VIN13,Region ID Write Enable Register for VIN 13" hexmask.long.word 0x80 0.--15. 1. "RGIDEN" line.long 0x84 "VIN14,Region ID Write Enable Register for VIN 14" hexmask.long.word 0x84 0.--15. 1. "RGIDEN" line.long 0x88 "VIN15,Region ID Write Enable Register for VIN 15" hexmask.long.word 0x88 0.--15. 1. "RGIDEN" line.long 0x8C "VIN16,Region ID Write Enable Register for VIN 16" hexmask.long.word 0x8C 0.--15. 1. "RGIDEN" line.long 0x90 "VIN17,Region ID Write Enable Register for VIN 17" hexmask.long.word 0x90 0.--15. 1. "RGIDEN" line.long 0x94 "VIN20,Region ID Write Enable Register for VIN 20" hexmask.long.word 0x94 0.--15. 1. "RGIDEN" line.long 0x98 "VIN21,Region ID Write Enable Register for VIN 21" hexmask.long.word 0x98 0.--15. 1. "RGIDEN" line.long 0x9C "VIN22,Region ID Write Enable Register for VIN 22" hexmask.long.word 0x9C 0.--15. 1. "RGIDEN" line.long 0xA0 "VIN23,Region ID Write Enable Register for VIN 23" hexmask.long.word 0xA0 0.--15. 1. "RGIDEN" line.long 0xA4 "VIN24,Region ID Write Enable Register for VIN 24" hexmask.long.word 0xA4 0.--15. 1. "RGIDEN" line.long 0xA8 "VIN25,Region ID Write Enable Register for VIN 25" hexmask.long.word 0xA8 0.--15. 1. "RGIDEN" line.long 0xAC "VIN26,Region ID Write Enable Register for VIN 26" hexmask.long.word 0xAC 0.--15. 1. "RGIDEN" line.long 0xB0 "VIN27,Region ID Write Enable Register for VIN 27" hexmask.long.word 0xB0 0.--15. 1. "RGIDEN" line.long 0xB4 "VIN30,Region ID Write Enable Register for VIN 30" hexmask.long.word 0xB4 0.--15. 1. "RGIDEN" line.long 0xB8 "VIN31,Region ID Write Enable Register for VIN 31" hexmask.long.word 0xB8 0.--15. 1. "RGIDEN" line.long 0xBC "VIN32,Region ID Write Enable Register for VIN 32" hexmask.long.word 0xBC 0.--15. 1. "RGIDEN" line.long 0xC0 "VIN33,Region ID Write Enable Register for VIN 33" hexmask.long.word 0xC0 0.--15. 1. "RGIDEN" line.long 0xC4 "VIN34,Region ID Write Enable Register for VIN 34" hexmask.long.word 0xC4 0.--15. 1. "RGIDEN" line.long 0xC8 "VIN35,Region ID Write Enable Register for VIN 35" hexmask.long.word 0xC8 0.--15. 1. "RGIDEN" line.long 0xCC "VIN36,Region ID Write Enable Register for VIN 36" hexmask.long.word 0xCC 0.--15. 1. "RGIDEN" line.long 0xD0 "VIN37,Region ID Write Enable Register for VIN 37" hexmask.long.word 0xD0 0.--15. 1. "RGIDEN" line.long 0xD4 "AXIISPCOMXW,Region ID Write Enable Register for AXIISPCOMXW" hexmask.long.word 0xD4 0.--15. 1. "RGIDEN" line.long 0xD8 "AXIVINCOMXW,Region ID Write Enable Register for AXIVINCOMXW" hexmask.long.word 0xD8 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7B12400++0x53 line.long 0x0 "ARVIP00,Region ID Write Enable Register for ARVIP 00" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARVIP01,Region ID Write Enable Register for ARVIP 01" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARVIP02,Region ID Write Enable Register for ARVIP 02" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARVIP03,Region ID Write Enable Register for ARVIP 03" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "AXIFBABUSVIP0S,Region ID Write Enable Register for AXIFBABUSVIP0S" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARVIP04,Region ID Write Enable Register for ARVIP 04" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARVIP05,Region ID Write Enable Register for ARVIP 05" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARVIP06,Region ID Write Enable Register for ARVIP 06" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARVIP07,Region ID Write Enable Register for ARVIP 07" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARVIP08,Region ID Write Enable Register for ARVIP 08" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CKMVIP,Region ID Write Enable Register for CKMVIP" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "ECMVIP,Region ID Write Enable Register for ECMVIP" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "IPMMUVIP0,Region ID Write Enable Register for IPMMUVIP 0" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "SMES0,Region ID Write Enable Register for SMES 0" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "SMPO0,Region ID Write Enable Register for SMPO 0" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "SMPS0,Region ID Write Enable Register for SMPS 0" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "UMFL0,Region ID Write Enable Register for UMFL 0" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "AXIFCPRAVIP0MA,Region ID Write Enable Register for AXIFCPRAVIP0MA" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "AXISMPS0MR,Region ID Write Enable Register for AXISMPS0MR" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "AXIUMFL0MR,Region ID Write Enable Register for AXIUMFL0MR" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "AXIUMFL0MW,Region ID Write Enable Register for AXIUMFL0MW" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFE7B42400++0x7F line.long 0x0 "ARVIP10,Region ID Write Enable Register for ARVIP 10" hexmask.long.word 0x0 0.--15. 1. "RGIDEN" line.long 0x4 "ARVIP11,Region ID Write Enable Register for ARVIP 11" hexmask.long.word 0x4 0.--15. 1. "RGIDEN" line.long 0x8 "ARVIP12,Region ID Write Enable Register for ARVIP 12" hexmask.long.word 0x8 0.--15. 1. "RGIDEN" line.long 0xC "ARVIP13,Region ID Write Enable Register for ARVIP 13" hexmask.long.word 0xC 0.--15. 1. "RGIDEN" line.long 0x10 "AXIFBABUSVIP1,Region ID Write Enable Register for AXIFBABUSVIP 1" hexmask.long.word 0x10 0.--15. 1. "RGIDEN" line.long 0x14 "ARVIP14,Region ID Write Enable Register for ARVIP 14" hexmask.long.word 0x14 0.--15. 1. "RGIDEN" line.long 0x18 "ARVIP15,Region ID Write Enable Register for ARVIP 15" hexmask.long.word 0x18 0.--15. 1. "RGIDEN" line.long 0x1C "ARVIP16,Region ID Write Enable Register for ARVIP 16" hexmask.long.word 0x1C 0.--15. 1. "RGIDEN" line.long 0x20 "ARVIP17,Region ID Write Enable Register for ARVIP 17" hexmask.long.word 0x20 0.--15. 1. "RGIDEN" line.long 0x24 "ARVIP18,Region ID Write Enable Register for ARVIP 18" hexmask.long.word 0x24 0.--15. 1. "RGIDEN" line.long 0x28 "CLE0,Region ID Write Enable Register for CLE 0" hexmask.long.word 0x28 0.--15. 1. "RGIDEN" line.long 0x2C "CLE1,Region ID Write Enable Register for CLE 1" hexmask.long.word 0x2C 0.--15. 1. "RGIDEN" line.long 0x30 "CLE2,Region ID Write Enable Register for CLE 2" hexmask.long.word 0x30 0.--15. 1. "RGIDEN" line.long 0x34 "CLE3,Region ID Write Enable Register for CLE 3" hexmask.long.word 0x34 0.--15. 1. "RGIDEN" line.long 0x38 "DISP0,Region ID Write Enable Register for DISP 0" hexmask.long.word 0x38 0.--15. 1. "RGIDEN" line.long 0x3C "DISP1,Region ID Write Enable Register for DISP 1" hexmask.long.word 0x3C 0.--15. 1. "RGIDEN" line.long 0x40 "IPMMUVIP1,Region ID Write Enable Register for IPMMUVIP 1" hexmask.long.word 0x40 0.--15. 1. "RGIDEN" line.long 0x44 "SMES1,Region ID Write Enable Register for SMES 1" hexmask.long.word 0x44 0.--15. 1. "RGIDEN" line.long 0x48 "SMPO1,Region ID Write Enable Register for SMPO 1" hexmask.long.word 0x48 0.--15. 1. "RGIDEN" line.long 0x4C "SMPS1,Region ID Write Enable Register for SMPS 1" hexmask.long.word 0x4C 0.--15. 1. "RGIDEN" line.long 0x50 "UMFL1,Region ID Write Enable Register for UMFL 1" hexmask.long.word 0x50 0.--15. 1. "RGIDEN" line.long 0x54 "AXICLE0MR,Region ID Write Enable Register for AXICLE0MR" hexmask.long.word 0x54 0.--15. 1. "RGIDEN" line.long 0x58 "AXICLE1MR,Region ID Write Enable Register for AXICLE1MR" hexmask.long.word 0x58 0.--15. 1. "RGIDEN" line.long 0x5C "AXICLE2MR,Region ID Write Enable Register for AXICLE2MR" hexmask.long.word 0x5C 0.--15. 1. "RGIDEN" line.long 0x60 "AXICLE3MR,Region ID Write Enable Register for AXICLE3MR" hexmask.long.word 0x60 0.--15. 1. "RGIDEN" line.long 0x64 "AXIDISP0MR,Region ID Write Enable Register for AXIDISP0MR" hexmask.long.word 0x64 0.--15. 1. "RGIDEN" line.long 0x68 "AXIDISP1MR,Region ID Write Enable Register for AXIDISP1MR" hexmask.long.word 0x68 0.--15. 1. "RGIDEN" line.long 0x6C "AXIFCPRAVIP1MA,Region ID Write Enable Register for AXIFCPRAVIP1MA" hexmask.long.word 0x6C 0.--15. 1. "RGIDEN" line.long 0x70 "AXIFCPRAVIP2MA,Region ID Write Enable Register for AXIFCPRAVIP2MA" hexmask.long.word 0x70 0.--15. 1. "RGIDEN" line.long 0x74 "AXISMPS1MR,Region ID Write Enable Register for AXISMPS1MR" hexmask.long.word 0x74 0.--15. 1. "RGIDEN" line.long 0x78 "AXIUMFL1MR,Region ID Write Enable Register for AXIUMFL1MR" hexmask.long.word 0x78 0.--15. 1. "RGIDEN" line.long 0x7C "AXIUMFL1MW,Region ID Write Enable Register for AXIUMFL1MW" hexmask.long.word 0x7C 0.--15. 1. "RGIDEN" group.long 0xFFFFFFFFFFC84010++0x3 line.long 0x0 "SAFERR_APRT0,Safe Error Status Register for RT Domain APB" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6004010++0x3 line.long 0x0 "SAFERR_APS0,Safe Error Status Register for Top Slave Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7794010++0x3 line.long 0x0 "SAFERR_APSD3,Safe Error Status Register for PER0 Domain DMA Bus 3" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7764010++0x3 line.long 0x0 "SAFERR_APSP3,Safe Error Status Register for PER0 Domain 3" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF884010++0x3 line.long 0x0 "SAFERR_AXIMP0,Safe Error Status Register for IR Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD814010++0x3 line.long 0x0 "SAFERR_AXGFX,Safe Error Status Register for GFX Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6624010++0x3 line.long 0x0 "SAFERR_AXRC,Safe Error Status Register for RT Domain 2" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFFC34010++0x3 line.long 0x0 "SAFERR_AXRD,Safe Error Status Register for RT Domain DMA Bus" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFFC44010++0x7 line.long 0x0 "SAFERR0_AXRT,Safe Error Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "SAFERR1_AXRT,Safe Error Status Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF864010++0x3 line.long 0x0 "SAFERR_AXSC,Safe Error Status Register for Top Slave Domain 1" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7784010++0x3 line.long 0x0 "SAFERR_AXSD0,Safe Error Status Register for PER0 Domain DMA Bus" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67C4010++0x3 line.long 0x0 "SAFERR_AXSM,Safe Error Status Register for MM Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF804010++0x3 line.long 0x0 "SAFERR_AXSN,Safe Error Status Register for Top Slave Domain 2" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7754010++0x7 line.long 0x0 "SAFERR0_AXSP0,Safe Error Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "SAFERR1_AXSP0,Safe Error Status Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6584010++0x3 line.long 0x0 "SAFERR_AXSP1,Safe Error Status Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE684010++0x3 line.long 0x0 "SAFERR_AXVC,Safe Error Status Register for VC Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEBE4010++0x3 line.long 0x0 "SAFERR_AXVI1,Safe Error Status Register for VIO Domain 10" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEBF4010++0x7 line.long 0x0 "SAFERR0_AXVI,Safe Error Status Register for VIO Domain 00" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "SAFERR1_AXVI,Safe Error Status Register for VIO Domain 01" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7B14010++0x3 line.long 0x0 "SAFERR0_AXVIP0,Safe Error Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7B44010++0x3 line.long 0x0 "SAFERR0_AXVIP1,Safe Error Status Register for VIP Domain 1" hexmask.long 0x0 0.--31. 1. "STATUS" rgroup.long 0xFFFFFFFFFFC84020++0x3 line.long 0x0 "SAFID_APRT0,Safe Error ID Register for RT Domain APB" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE6004020++0x3 line.long 0x0 "SAFID_APS0,Safe Error ID Register for Top Slave Domain 0" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7794020++0x3 line.long 0x0 "SAFID_APSD3,Safe Error ID Register for PER0 Domain DMA Bus 3" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7764020++0x3 line.long 0x0 "SAFID_APSP3,Safe Error ID Register for PER0 Domain 3" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFF884020++0x3 line.long 0x0 "SAFID_AXIMP0,Safe Error ID Register for IR Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFD814020++0x3 line.long 0x0 "SAFID_AXGFX,Safe Error ID Register for GFX Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE6624020++0x3 line.long 0x0 "SAFID_AXRC,Safe Error ID Register for RT Domain 2" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFFC34020++0x3 line.long 0x0 "SAFID_AXRD,Safe Error ID Register for RT Domain DMA Bus" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFFC44020++0x3 line.long 0x0 "SAFID_AXRT,Safe Error ID Register for RT Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFF864020++0x3 line.long 0x0 "SAFID_AXSC,Safe Error ID Register for Top Slave Domain 1" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7784020++0x3 line.long 0x0 "SAFID_AXSD0,Safe Error ID Register for PER0 Domain DMA Bus" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE67C4020++0x3 line.long 0x0 "SAFID_AXSM,Safe Error ID Register for MM Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFF804020++0x3 line.long 0x0 "SAFID_AXSN,Safe Error ID Register for Top Slave Domain 2" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7754020++0x3 line.long 0x0 "SAFID_AXSP0,Safe Error ID Register for PER0 Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE6584020++0x3 line.long 0x0 "SAFID_AXSP1,Safe Error ID Register for PER1 Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFE684020++0x3 line.long 0x0 "SAFID_AXVC,Safe Error ID Register for VC Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFEBF4020++0x3 line.long 0x0 "SAFID_AXVI,Safe Error ID Register for VIO Domain 0" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFEBE4020++0x3 line.long 0x0 "SAFID_AXVI1,Safe Error ID Register for VIO Domain 1" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7B14020++0x3 line.long 0x0 "SAFID_AXVIP0,Safe Error ID Register for VIP Domain 0" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7B44020++0x3 line.long 0x0 "SAFID_AXVIP1,Safe Error ID Register for VIP Domain 1" hexmask.long.byte 0x0 0.--7. 1. "SID" group.long 0xFFFFFFFFFFC83400++0x67 line.long 0x0 "SECARMGC0,Secure Group Setting Register for ARMGC 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARMGC1,Secure Group Setting Register for ARMGC 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARMGC2,Secure Group Setting Register for ARMGC 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARRT00,Secure Group Setting Register for ARRT 00" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARRT01,Secure Group Setting Register for ARRT 01" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARRT02,Secure Group Setting Register for ARRT 02" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARRT03,Secure Group Setting Register for ARRT 03" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARRT04,Secure Group Setting Register for ARRT 04" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARRT05,Secure Group Setting Register for ARRT 05" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECARRT06,Secure Group Setting Register for ARRT 06" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECARRT07,Secure Group Setting Register for ARRT 07" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECARRT08,Secure Group Setting Register for ARRT 08" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECLIFEC0,Secure Group Setting Register for LIFEC 0" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECSWDT,Secure Group Setting Register for SWDT" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECTMU0,Secure Group Setting Register for TMU 0" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECWDT,Secure Group Setting Register for WDT" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECWWDT0,Secure Group Setting Register for WWDT 0" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECWWDT1,Secure Group Setting Register for WWDT 1" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECWWDT2,Secure Group Setting Register for WWDT 2" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECWWDT3,Secure Group Setting Register for WWDT 3" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECWWDT4,Secure Group Setting Register for WWDT 4" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECWWDT5,Secure Group Setting Register for WWDT 5" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECWWDT6,Secure Group Setting Register for WWDT 6" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECWWDT7,Secure Group Setting Register for WWDT 7" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECWWDT8,Secure Group Setting Register for WWDT 8" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECWWDT9,Secure Group Setting Register for WWDT 9" bitfld.long 0x64 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE6003400++0x77 line.long 0x0 "SECADVFSC,Secure Group Setting Register for ADVFSC" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECAPMU0,Secure Group Setting Register for APMU 0" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECAPMU1,Secure Group Setting Register for APMU 1" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECAPMU10,Secure Group Setting Register for APMU 10" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECAPMU11,Secure Group Setting Register for APMU 11" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECAPMU12,Secure Group Setting Register for APMU 12" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECAPMU13,Secure Group Setting Register for APMU 13" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECAPMU14,Secure Group Setting Register for APMU 14" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECAPMU15,Secure Group Setting Register for APMU 15" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECAPMU2,Secure Group Setting Register for APMU 2" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECAPMU3,Secure Group Setting Register for APMU 3" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECAPMU4,Secure Group Setting Register for APMU 4" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECAPMU5,Secure Group Setting Register for APMU 5" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECAPMU6,Secure Group Setting Register for APMU 6" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECAPMU7,Secure Group Setting Register for APMU 7" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECAPMU8,Secure Group Setting Register for APMU 8" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECAPMU9,Secure Group Setting Register for APMU 9" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECARS00,Secure Group Setting Register for ARS 00" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECARS01,Secure Group Setting Register for ARS 01" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECARS02,Secure Group Setting Register for ARS 02" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECARS03,Secure Group Setting Register for ARS 03" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECARS04,Secure Group Setting Register for ARS 04" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECARS05,Secure Group Setting Register for ARS 05" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECARS06,Secure Group Setting Register for ARS 06" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECARS07,Secure Group Setting Register for ARS 07" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECARS08,Secure Group Setting Register for ARS 08" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECCMT0,Secure Group Setting Register for CMT 0" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECCMT1,Secure Group Setting Register for CMT 1" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECCMT2,Secure Group Setting Register for CMT 2" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECCMT3,Secure Group Setting Register for CMT 3" bitfld.long 0x74 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE600347C++0x7 line.long 0x0 "SECDBE,Secure Group Setting Register for DBE" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECIRQC,Secure Group Setting Register for IRQC" bitfld.long 0x4 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE600349C++0x3 line.long 0x0 "SECSCMT,Secure Group Setting Register for SCMT" bitfld.long 0x0 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE60034A4++0x17 line.long 0x0 "SECTSC0,Secure Group Setting Register for TSC 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECTSC1,Secure Group Setting Register for TSC 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECTSC2,Secure Group Setting Register for TSC 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECTSC3,Secure Group Setting Register for TSC 3" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECTSC4,Secure Group Setting Register for TSC 4" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECUCMT,Secure Group Setting Register for UCMT" bitfld.long 0x14 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE6003500++0x7F line.long 0x0 "SECCPG0,Secure Group Setting Register for CPG 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECCPG1,Secure Group Setting Register for CPG 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECCPG2,Secure Group Setting Register for CPG 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECCPG3,Secure Group Setting Register for CPG 3" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECPFC00,Secure Group Setting Register for PFC 00" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECPFC01,Secure Group Setting Register for PFC 01" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECPFC02,Secure Group Setting Register for PFC 02" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECPFC03,Secure Group Setting Register for PFC 03" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECPFC10,Secure Group Setting Register for PFC 10" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECPFC11,Secure Group Setting Register for PFC 11" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECPFC12,Secure Group Setting Register for PFC 12" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECPFC13,Secure Group Setting Register for PFC 13" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECPFC20,Secure Group Setting Register for PFC 20" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECPFC21,Secure Group Setting Register for PFC 21" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECPFC22,Secure Group Setting Register for PFC 22" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECPFC23,Secure Group Setting Register for PFC 23" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECPFC30,Secure Group Setting Register for PFC 30" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECPFC31,Secure Group Setting Register for PFC 31" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECPFC32,Secure Group Setting Register for PFC 32" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECPFC33,Secure Group Setting Register for PFC 33" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECPFCS0,Secure Group Setting Register for PFCS 0" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECPFCS1,Secure Group Setting Register for PFCS 1" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECPFCS2,Secure Group Setting Register for PFCS 2" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECPFCS3,Secure Group Setting Register for PFCS 3" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECRESET0,Secure Group Setting Register for RESET 0" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECRESET1,Secure Group Setting Register for RESET 1" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECRESET2,Secure Group Setting Register for RESET 2" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECRESET3,Secure Group Setting Register for RESET 3" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECSYS0,Secure Group Setting Register for SYS 0" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECSYS1,Secure Group Setting Register for SYS 1" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECSYS2,Secure Group Setting Register for SYS 2" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECSYS3,Secure Group Setting Register for SYS 3" bitfld.long 0x7C 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE7793400++0x17 line.long 0x0 "SECDMAMSI0,Secure Group Setting Register for DMAMSI 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECDMAMSI1,Secure Group Setting Register for DMAMSI 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECDMAMSI2,Secure Group Setting Register for DMAMSI 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECDMAMSI3,Secure Group Setting Register for DMAMSI 3" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECDMAMSI4,Secure Group Setting Register for DMAMSI 4" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECDMAMSI5,Secure Group Setting Register for DMAMSI 5" bitfld.long 0x14 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE7763400++0x5F line.long 0x0 "SECARSD30,Secure Group Setting Register for ARSD 30" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARSD31,Secure Group Setting Register for ARSD 31" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARSD32,Secure Group Setting Register for ARSD 32" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARSD33,Secure Group Setting Register for ARSD 33" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARSD34,Secure Group Setting Register for ARSD 34" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARSD35,Secure Group Setting Register for ARSD 35" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARSD36,Secure Group Setting Register for ARSD 36" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARSD37,Secure Group Setting Register for ARSD 37" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARSD38,Secure Group Setting Register for ARSD 38" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECARSP30,Secure Group Setting Register for ARSP 30" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECARSP31,Secure Group Setting Register for ARSP 31" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECARSP32,Secure Group Setting Register for ARSP 32" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECARSP33,Secure Group Setting Register for ARSP 33" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECARSP34,Secure Group Setting Register for ARSP 34" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECARSP35,Secure Group Setting Register for ARSP 35" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECARSP36,Secure Group Setting Register for ARSP 36" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECARSP37,Secure Group Setting Register for ARSP 37" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECARSP38,Secure Group Setting Register for ARSP 38" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECMSI0,Secure Group Setting Register for MSI 0" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECMSI1,Secure Group Setting Register for MSI 1" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECMSI2,Secure Group Setting Register for MSI 2" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECMSI3,Secure Group Setting Register for MSI 3" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECMSI4,Secure Group Setting Register for MSI 4" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECMSI5,Secure Group Setting Register for MSI 5" bitfld.long 0x5C 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFF883400++0x6B line.long 0x0 "SECARIMP00,Secure Group Setting Register for ARIMP 00" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARIMP01,Secure Group Setting Register for ARIMP 01" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARIMP02,Secure Group Setting Register for ARIMP 02" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARIMP03,Secure Group Setting Register for ARIMP 03" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARIMP04,Secure Group Setting Register for ARIMP 04" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECFBABUSIR0,Secure Group Setting Register for FBABUSIR 0" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECFBABUSIR1,Secure Group Setting Register for FBABUSIR 1" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECFBABUSIR2,Secure Group Setting Register for FBABUSIR 2" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECFBABUSIR3,Secure Group Setting Register for FBABUSIR 3" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECFBABUSIR4,Secure Group Setting Register for FBABUSIR 4" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECIMP0,Secure Group Setting Register for IMP 0" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECIMPD0,Secure Group Setting Register for IMPD 0" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECIMPD1,Secure Group Setting Register for IMPD 1" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECARIMP05,Secure Group Setting Register for ARIMP 05" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECARIMP06,Secure Group Setting Register for ARIMP 06" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECARIMP07,Secure Group Setting Register for ARIMP 07" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECARIMP08,Secure Group Setting Register for ARIMP 08" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECCKMIR,Secure Group Setting Register for CKMIR" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECECMIR,Secure Group Setting Register for ECMIR" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECRADSP0,Secure Group Setting Register for RADSP 0" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECRADSP1,Secure Group Setting Register for RADSP 1" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECIPMMUIR,Secure Group Setting Register for IPMMUIR" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECFCPRAIR,Secure Group Setting Register for FCPRAIR" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECIMP0M_R,Secure Group Setting Register for IMP0M_R" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECIMP0M_W,Secure Group Setting Register for IMP0M_W" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECIMP1M_R,Secure Group Setting Register for IMP1M_R" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECIMP1M_W,Secure Group Setting Register for IMP1M_W" bitfld.long 0x68 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFD813400++0x47 line.long 0x0 "SECARPV0,Secure Group Setting Register for ARPV 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARPV1,Secure Group Setting Register for ARPV 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECRGX,Secure Group Setting Register for RGX" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARPV2,Secure Group Setting Register for ARPV 2" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARPV3,Secure Group Setting Register for ARPV 3" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARPV4,Secure Group Setting Register for ARPV 4" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARPV5,Secure Group Setting Register for ARPV 5" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARPV6,Secure Group Setting Register for ARPV 6" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARPV7,Secure Group Setting Register for ARPV 7" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECARPV8,Secure Group Setting Register for ARPV 8" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECCKM3DG,Secure Group Setting Register for CKM3DG" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECECMU3DG,Secure Group Setting Register for ECMU3DG" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECFBAPVC,Secure Group Setting Register for FBAPVC" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECFBAPVD0,Secure Group Setting Register for FBAPVD 0" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECFBAPVD1,Secure Group Setting Register for FBAPVD 1" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECFBAPVD2,Secure Group Setting Register for FBAPVD 2" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECFBAPVE,Secure Group Setting Register for FBAPVE" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECIPMMUPV0,Secure Group Setting Register for IPMMUPV 0" bitfld.long 0x44 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE6623400++0x2B line.long 0x0 "SECARRC0,Secure Group Setting Register for ARRC 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARRC1,Secure Group Setting Register for ARRC 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARRC2,Secure Group Setting Register for ARRC 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARRC3,Secure Group Setting Register for ARRC 3" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARRC4,Secure Group Setting Register for ARRC 4" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARRC5,Secure Group Setting Register for ARRC 5" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARRC6,Secure Group Setting Register for ARRC 6" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARRC7,Secure Group Setting Register for ARRC 7" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARRC8,Secure Group Setting Register for ARRC 8" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECCR0,Secure Group Setting Register for CR 0" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECICUMX,Secure Group Setting Register for ICUMX" bitfld.long 0x28 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFFC33400++0xF line.long 0x0 "SECDMA_WCRC0,Secure Group Setting Register for DMA_WCRC 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECDMA_WCRC1,Secure Group Setting Register for DMA_WCRC 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECDMA_WCRC2,Secure Group Setting Register for DMA_WCRC 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECDMA_WCRC3,Secure Group Setting Register for DMA_WCRC 3" bitfld.long 0xC 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFFC43018++0x3 line.long 0x0 "SECSRCAXICR52SSM,Secure Group Setting Register for SRCAXICR52SSM" bitfld.long 0x0 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFFC43400++0x117 line.long 0x0 "SECARMREG0,Secure Group Setting Register for ARMREG 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARMREG1,Secure Group Setting Register for ARMREG 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARMREG10,Secure Group Setting Register for ARMREG 10" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARMREG11,Secure Group Setting Register for ARMREG 11" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARMREG12,Secure Group Setting Register for ARMREG 12" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARMREG13,Secure Group Setting Register for ARMREG 13" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARMREG14,Secure Group Setting Register for ARMREG 14" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECCR52SS,Secure Group Setting Register for CR52SS" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECCSD0,Secure Group Setting Register for CSD 0" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECINTAP0,Secure Group Setting Register for INTAP 0" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECINTAP1,Secure Group Setting Register for INTAP 1" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECSECROM,Secure Group Setting Register for SECROM" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECSYSRAM0_AXI,Secure Group Setting Register for SYSRAM0 AXI" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECSYSRAM1,Secure Group Setting Register for SYSRAM 1" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECARMREG15,Secure Group Setting Register for ARMREG 15" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECARMREG2,Secure Group Setting Register for ARMREG 2" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECARMREG3,Secure Group Setting Register for ARMREG 3" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECARMREG4,Secure Group Setting Register for ARMREG 4" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECARMREG5,Secure Group Setting Register for ARMREG 5" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECARMREG6,Secure Group Setting Register for ARMREG 6" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECARMREG7,Secure Group Setting Register for ARMREG 7" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECARMREG8,Secure Group Setting Register for ARMREG 8" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECARMREG9,Secure Group Setting Register for ARMREG 9" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECARRD0,Secure Group Setting Register for ARRD 0" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECARRD1,Secure Group Setting Register for ARRD 1" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECARRD2,Secure Group Setting Register for ARRD 2" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECARRD3,Secure Group Setting Register for ARRD 3" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECARRD4,Secure Group Setting Register for ARRD 4" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECARRD5,Secure Group Setting Register for ARRD 5" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECARRD6,Secure Group Setting Register for ARRD 6" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECARRD7,Secure Group Setting Register for ARRD 7" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECARRD8,Secure Group Setting Register for ARRD 8" bitfld.long 0x7C 0. "SECGRP" "0,1" line.long 0x80 "SECARRT0,Secure Group Setting Register for ARRT 0" bitfld.long 0x80 0. "SECGRP" "0,1" line.long 0x84 "SECARRT1,Secure Group Setting Register for ARRT 1" bitfld.long 0x84 0. "SECGRP" "0,1" line.long 0x88 "SECARRT2,Secure Group Setting Register for ARRT 2" bitfld.long 0x88 0. "SECGRP" "0,1" line.long 0x8C "SECARRT3,Secure Group Setting Register for ARRT 3" bitfld.long 0x8C 0. "SECGRP" "0,1" line.long 0x90 "SECARRT4,Secure Group Setting Register for ARRT 4" bitfld.long 0x90 0. "SECGRP" "0,1" line.long 0x94 "SECARRT5,Secure Group Setting Register for ARRT 5" bitfld.long 0x94 0. "SECGRP" "0,1" line.long 0x98 "SECARRT6,Secure Group Setting Register for ARRT 6" bitfld.long 0x98 0. "SECGRP" "0,1" line.long 0x9C "SECARRT7,Secure Group Setting Register for ARRT 7" bitfld.long 0x9C 0. "SECGRP" "0,1" line.long 0xA0 "SECARRT8,Secure Group Setting Register for ARRT 8" bitfld.long 0xA0 0. "SECGRP" "0,1" line.long 0xA4 "SECCKMRT,Secure Group Setting Register for CKMRT" bitfld.long 0xA4 0. "SECGRP" "0,1" line.long 0xA8 "SECCRC0,Secure Group Setting Register for CRC 0" bitfld.long 0xA8 0. "SECGRP" "0,1" line.long 0xAC "SECCRC1,Secure Group Setting Register for CRC 1" bitfld.long 0xAC 0. "SECGRP" "0,1" line.long 0xB0 "SECCRC2,Secure Group Setting Register for CRC 2" bitfld.long 0xB0 0. "SECGRP" "0,1" line.long 0xB4 "SECCRC3,Secure Group Setting Register for CRC 3" bitfld.long 0xB4 0. "SECGRP" "0,1" line.long 0xB8 "SECCSD,Secure Group Setting Register for CSD" bitfld.long 0xB8 0. "SECGRP" "0,1" line.long 0xBC "SECECM,Secure Group Setting Register for ECM" bitfld.long 0xBC 0. "SECGRP" "0,1" line.long 0xC0 "SECECMRT,Secure Group Setting Register for ECMRT" bitfld.long 0xC0 0. "SECGRP" "0,1" line.long 0xC4 "SECFBACR52,Secure Group Setting Register for FBACR 52" bitfld.long 0xC4 0. "SECGRP" "0,1" line.long 0xC8 "SECFBART,Secure Group Setting Register for FBART" bitfld.long 0xC8 0. "SECGRP" "0,1" line.long 0xCC "SECINTTP,Secure Group Setting Register for INTTP" bitfld.long 0xCC 0. "SECGRP" "0,1" line.long 0xD0 "SECIPMMURT0,Secure Group Setting Register for IPMMURT 0" bitfld.long 0xD0 0. "SECGRP" "0,1" line.long 0xD4 "SECIPMMURT1,Secure Group Setting Register for IPMMURT 1" bitfld.long 0xD4 0. "SECGRP" "0,1" line.long 0xD8 "SECKCRC4,Secure Group Setting Register for KCRC 4" bitfld.long 0xD8 0. "SECGRP" "0,1" line.long 0xDC "SECKCRC5,Secure Group Setting Register for KCRC 5" bitfld.long 0xDC 0. "SECGRP" "0,1" line.long 0xE0 "SECKCRC6,Secure Group Setting Register for KCRC 6" bitfld.long 0xE0 0. "SECGRP" "0,1" line.long 0xE4 "SECKCRC7,Secure Group Setting Register for KCRC 7" bitfld.long 0xE4 0. "SECGRP" "0,1" line.long 0xE8 "SECMFI0,Secure Group Setting Register for MFI 0" bitfld.long 0xE8 0. "SECGRP" "0,1" line.long 0xEC "SECMFI1,Secure Group Setting Register for MFI 1" bitfld.long 0xEC 0. "SECGRP" "0,1" line.long 0xF0 "SECMFI10,Secure Group Setting Register for MFI 10" bitfld.long 0xF0 0. "SECGRP" "0,1" line.long 0xF4 "SECMFI2,Secure Group Setting Register for MFI 2" bitfld.long 0xF4 0. "SECGRP" "0,1" line.long 0xF8 "SECMFI3,Secure Group Setting Register for MFI 3" bitfld.long 0xF8 0. "SECGRP" "0,1" line.long 0xFC "SECMFI4,Secure Group Setting Register for MFI 4" bitfld.long 0xFC 0. "SECGRP" "0,1" line.long 0x100 "SECMFI5,Secure Group Setting Register for MFI 5" bitfld.long 0x100 0. "SECGRP" "0,1" line.long 0x104 "SECMFI6,Secure Group Setting Register for MFI 6" bitfld.long 0x104 0. "SECGRP" "0,1" line.long 0x108 "SECMFI7,Secure Group Setting Register for MFI 7" bitfld.long 0x108 0. "SECGRP" "0,1" line.long 0x10C "SECMFI8,Secure Group Setting Register for MFI 8" bitfld.long 0x10C 0. "SECGRP" "0,1" line.long 0x110 "SECMFI9,Secure Group Setting Register for MFI 9" bitfld.long 0x110 0. "SECGRP" "0,1" line.long 0x114 "SECPRR,Secure Group Setting Register for PRR" bitfld.long 0x114 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFFC4351C++0x3 line.long 0x0 "SECRTDM0P,Secure Group Setting Register for RTDM0P" bitfld.long 0x0 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFFC43524++0x3 line.long 0x0 "SECRTDM1P,Secure Group Setting Register for RTDM1P" bitfld.long 0x0 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFFC4352C++0x3 line.long 0x0 "SECRTDM2P,Secure Group Setting Register for RTDM2P" bitfld.long 0x0 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFFC43534++0x3F line.long 0x0 "SECRTDM3P,Secure Group Setting Register for RTDM3P" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECSYSRAM0_APB,Secure Group Setting Register for SYSRAM0 APB" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECTSIPL0,Secure Group Setting Register for TSIPL 0" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECTSIPL1,Secure Group Setting Register for TSIPL 1" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECTSIPL2,Secure Group Setting Register for TSIPL 2" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECTSIPL3,Secure Group Setting Register for TSIPL 3" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECTSIPL4,Secure Group Setting Register for TSIPL 4" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECTSIPL5,Secure Group Setting Register for TSIPL 5" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECTSIPL6,Secure Group Setting Register for TSIPL 6" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECTSIPL7,Secure Group Setting Register for TSIPL 7" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECWCRC0,Secure Group Setting Register for WCRC 0" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECWCRC1,Secure Group Setting Register for WCRC 1" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECWCRC2,Secure Group Setting Register for WCRC 2" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECWCRC3,Secure Group Setting Register for WCRC 3" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECFCPRART0,Secure Group Setting Register for FCPRART 0" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECMEM_RTDM0_R,Secure Group Setting Register for MEM_RTDM0_R" bitfld.long 0x3C 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFFC43600++0xFF line.long 0x0 "SECRTDM00,Secure Group Setting Register for RTDM 00" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECRTDM01,Secure Group Setting Register for RTDM 01" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECRTDM010,Secure Group Setting Register for RTDM 010" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECRTDM011,Secure Group Setting Register for RTDM 011" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECRTDM012,Secure Group Setting Register for RTDM 012" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECRTDM013,Secure Group Setting Register for RTDM 013" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECRTDM014,Secure Group Setting Register for RTDM 014" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECRTDM015,Secure Group Setting Register for RTDM 015" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECRTDM02,Secure Group Setting Register for RTDM 02" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECRTDM03,Secure Group Setting Register for RTDM 03" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECRTDM04,Secure Group Setting Register for RTDM 04" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECRTDM05,Secure Group Setting Register for RTDM 05" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECRTDM06,Secure Group Setting Register for RTDM 06" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECRTDM07,Secure Group Setting Register for RTDM 07" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECRTDM08,Secure Group Setting Register for RTDM 08" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECRTDM09,Secure Group Setting Register for RTDM 09" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECRTDM10,Secure Group Setting Register for RTDM 10" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECRTDM11,Secure Group Setting Register for RTDM 11" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECRTDM110,Secure Group Setting Register for RTDM 110" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECRTDM111,Secure Group Setting Register for RTDM 111" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECRTDM112,Secure Group Setting Register for RTDM 112" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECRTDM113,Secure Group Setting Register for RTDM 113" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECRTDM114,Secure Group Setting Register for RTDM 114" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECRTDM115,Secure Group Setting Register for RTDM 115" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECRTDM12,Secure Group Setting Register for RTDM 12" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECRTDM13,Secure Group Setting Register for RTDM 13" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECRTDM14,Secure Group Setting Register for RTDM 14" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECRTDM15,Secure Group Setting Register for RTDM 15" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECRTDM16,Secure Group Setting Register for RTDM 16" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECRTDM17,Secure Group Setting Register for RTDM 17" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECRTDM18,Secure Group Setting Register for RTDM 18" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECRTDM19,Secure Group Setting Register for RTDM 19" bitfld.long 0x7C 0. "SECGRP" "0,1" line.long 0x80 "SECRTDM20,Secure Group Setting Register for RTDM 20" bitfld.long 0x80 0. "SECGRP" "0,1" line.long 0x84 "SECRTDM21,Secure Group Setting Register for RTDM 21" bitfld.long 0x84 0. "SECGRP" "0,1" line.long 0x88 "SECRTDM210,Secure Group Setting Register for RTDM 210" bitfld.long 0x88 0. "SECGRP" "0,1" line.long 0x8C "SECRTDM211,Secure Group Setting Register for RTDM 211" bitfld.long 0x8C 0. "SECGRP" "0,1" line.long 0x90 "SECRTDM212,Secure Group Setting Register for RTDM 212" bitfld.long 0x90 0. "SECGRP" "0,1" line.long 0x94 "SECRTDM213,Secure Group Setting Register for RTDM 213" bitfld.long 0x94 0. "SECGRP" "0,1" line.long 0x98 "SECRTDM214,Secure Group Setting Register for RTDM 214" bitfld.long 0x98 0. "SECGRP" "0,1" line.long 0x9C "SECRTDM215,Secure Group Setting Register for RTDM 215" bitfld.long 0x9C 0. "SECGRP" "0,1" line.long 0xA0 "SECRTDM22,Secure Group Setting Register for RTDM 22" bitfld.long 0xA0 0. "SECGRP" "0,1" line.long 0xA4 "SECRTDM23,Secure Group Setting Register for RTDM 23" bitfld.long 0xA4 0. "SECGRP" "0,1" line.long 0xA8 "SECRTDM24,Secure Group Setting Register for RTDM 24" bitfld.long 0xA8 0. "SECGRP" "0,1" line.long 0xAC "SECRTDM25,Secure Group Setting Register for RTDM 25" bitfld.long 0xAC 0. "SECGRP" "0,1" line.long 0xB0 "SECRTDM26,Secure Group Setting Register for RTDM 26" bitfld.long 0xB0 0. "SECGRP" "0,1" line.long 0xB4 "SECRTDM27,Secure Group Setting Register for RTDM 27" bitfld.long 0xB4 0. "SECGRP" "0,1" line.long 0xB8 "SECRTDM28,Secure Group Setting Register for RTDM 28" bitfld.long 0xB8 0. "SECGRP" "0,1" line.long 0xBC "SECRTDM29,Secure Group Setting Register for RTDM 29" bitfld.long 0xBC 0. "SECGRP" "0,1" line.long 0xC0 "SECRTDM30,Secure Group Setting Register for RTDM 30" bitfld.long 0xC0 0. "SECGRP" "0,1" line.long 0xC4 "SECRTDM31,Secure Group Setting Register for RTDM 31" bitfld.long 0xC4 0. "SECGRP" "0,1" line.long 0xC8 "SECRTDM310,Secure Group Setting Register for RTDM 310" bitfld.long 0xC8 0. "SECGRP" "0,1" line.long 0xCC "SECRTDM311,Secure Group Setting Register for RTDM 311" bitfld.long 0xCC 0. "SECGRP" "0,1" line.long 0xD0 "SECRTDM312,Secure Group Setting Register for RTDM 312" bitfld.long 0xD0 0. "SECGRP" "0,1" line.long 0xD4 "SECRTDM313,Secure Group Setting Register for RTDM 313" bitfld.long 0xD4 0. "SECGRP" "0,1" line.long 0xD8 "SECRTDM314,Secure Group Setting Register for RTDM 314" bitfld.long 0xD8 0. "SECGRP" "0,1" line.long 0xDC "SECRTDM315,Secure Group Setting Register for RTDM 315" bitfld.long 0xDC 0. "SECGRP" "0,1" line.long 0xE0 "SECRTDM32,Secure Group Setting Register for RTDM 32" bitfld.long 0xE0 0. "SECGRP" "0,1" line.long 0xE4 "SECRTDM33,Secure Group Setting Register for RTDM 33" bitfld.long 0xE4 0. "SECGRP" "0,1" line.long 0xE8 "SECRTDM34,Secure Group Setting Register for RTDM 34" bitfld.long 0xE8 0. "SECGRP" "0,1" line.long 0xEC "SECRTDM35,Secure Group Setting Register for RTDM 35" bitfld.long 0xEC 0. "SECGRP" "0,1" line.long 0xF0 "SECRTDM36,Secure Group Setting Register for RTDM 36" bitfld.long 0xF0 0. "SECGRP" "0,1" line.long 0xF4 "SECRTDM37,Secure Group Setting Register for RTDM 37" bitfld.long 0xF4 0. "SECGRP" "0,1" line.long 0xF8 "SECRTDM38,Secure Group Setting Register for RTDM 38" bitfld.long 0xF8 0. "SECGRP" "0,1" line.long 0xFC "SECRTDM39,Secure Group Setting Register for RTDM 39" bitfld.long 0xFC 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFF863400++0x9F line.long 0x0 "SECARSC0,Secure Group Setting Register for ARSC 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARSC1,Secure Group Setting Register for ARSC 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARSC2,Secure Group Setting Register for ARSC 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARSC3,Secure Group Setting Register for ARSC 3" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARSC4,Secure Group Setting Register for ARSC 4" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARSC5,Secure Group Setting Register for ARSC 5" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARSC6,Secure Group Setting Register for ARSC 6" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARSC7,Secure Group Setting Register for ARSC 7" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARSC8,Secure Group Setting Register for ARSC 8" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECARSTM0,Secure Group Setting Register for ARSTM 0" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECARSTM1,Secure Group Setting Register for ARSTM 1" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECCSD1,Secure Group Setting Register for CSD 1" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECFBABUSTOP0,Secure Group Setting Register for FBABUSTOP 0" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECFBABUSTOP1,Secure Group Setting Register for FBABUSTOP 1" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECARSTM2,Secure Group Setting Register for ARSTM 2" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECARSTM3,Secure Group Setting Register for ARSTM 3" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECARSTM4,Secure Group Setting Register for ARSTM 4" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECARSTM5,Secure Group Setting Register for ARSTM 5" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECARSTM6,Secure Group Setting Register for ARSTM 6" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECARSTM7,Secure Group Setting Register for ARSTM 7" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECARSTM8,Secure Group Setting Register for ARSTM 8" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECECMTOP,Secure Group Setting Register for ECMTOP" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECFBA,Secure Group Setting Register for FBA" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECFBC,Secure Group Setting Register for FBC" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECCCIS0,Secure Group Setting Register for CCIS 0" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECCCIS1,Secure Group Setting Register for CCIS 1" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECCCIS10,Secure Group Setting Register for CCIS 10" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECCCIS11,Secure Group Setting Register for CCIS 11" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECCCIS12,Secure Group Setting Register for CCIS 12" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECCCIS13,Secure Group Setting Register for CCIS 13" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECCCIS14,Secure Group Setting Register for CCIS 14" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECCCIS15,Secure Group Setting Register for CCIS 15" bitfld.long 0x7C 0. "SECGRP" "0,1" line.long 0x80 "SECCCIS2,Secure Group Setting Register for CCIS 2" bitfld.long 0x80 0. "SECGRP" "0,1" line.long 0x84 "SECCCIS3,Secure Group Setting Register for CCIS 3" bitfld.long 0x84 0. "SECGRP" "0,1" line.long 0x88 "SECCCIS4,Secure Group Setting Register for CCIS 4" bitfld.long 0x88 0. "SECGRP" "0,1" line.long 0x8C "SECCCIS5,Secure Group Setting Register for CCIS 5" bitfld.long 0x8C 0. "SECGRP" "0,1" line.long 0x90 "SECCCIS6,Secure Group Setting Register for CCIS 6" bitfld.long 0x90 0. "SECGRP" "0,1" line.long 0x94 "SECCCIS7,Secure Group Setting Register for CCIS 7" bitfld.long 0x94 0. "SECGRP" "0,1" line.long 0x98 "SECCCIS8,Secure Group Setting Register for CCIS 8" bitfld.long 0x98 0. "SECGRP" "0,1" line.long 0x9C "SECCCIS9,Secure Group Setting Register for CCIS 9" bitfld.long 0x9C 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE7783400++0x43 line.long 0x0 "SECDMACANFD,Secure Group Setting Register for DMACANFD" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECDMAHSCIF0,Secure Group Setting Register for DMAHSCIF 0" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECDMAHSCIF1,Secure Group Setting Register for DMAHSCIF 1" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECDMAHSCIF2,Secure Group Setting Register for DMAHSCIF 2" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECDMAHSCIF3,Secure Group Setting Register for DMAHSCIF 3" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECDMAI2C0,Secure Group Setting Register for DMAI2C 0" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECDMAI2C1,Secure Group Setting Register for DMAI2C 1" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECDMAI2C2,Secure Group Setting Register for DMAI2C 2" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECDMAI2C3,Secure Group Setting Register for DMAI2C 3" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECDMAI2C4,Secure Group Setting Register for DMAI2C 4" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECDMAI2C5,Secure Group Setting Register for DMAI2C 5" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECDMAI2C6,Secure Group Setting Register for DMAI2C 6" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECDMASCIF0,Secure Group Setting Register for DMASCIF 0" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECDMASCIF1,Secure Group Setting Register for DMASCIF 1" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECDMASCIF3,Secure Group Setting Register for DMASCIF 3" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECDMASCIF4,Secure Group Setting Register for DMASCIF 4" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECDMATPU0,Secure Group Setting Register for DMATPU 0" bitfld.long 0x40 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE67C3400++0x13 line.long 0x0 "SECARMM,Secure Group Setting Register for ARMM" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARNMMS,Secure Group Setting Register for ARNMMS" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARSM0,Secure Group Setting Register for ARSM 0" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARSM1,Secure Group Setting Register for ARSM 1" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARSM2,Secure Group Setting Register for ARSM 2" bitfld.long 0x10 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE67C3434++0x4B line.long 0x0 "SECARSM3,Secure Group Setting Register for ARSM 3" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARSM4,Secure Group Setting Register for ARSM 4" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARSM5,Secure Group Setting Register for ARSM 5" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARSM6,Secure Group Setting Register for ARSM 6" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARSM7,Secure Group Setting Register for ARSM 7" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARSM8,Secure Group Setting Register for ARSM 8" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECAXMM0,Secure Group Setting Register for AXMM 0" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECAXMM1,Secure Group Setting Register for AXMM 1" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECAXMMPMON,Secure Group Setting Register for AXMMPMON" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECCKMMM,Secure Group Setting Register for CKMMM" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECECMMM,Secure Group Setting Register for ECMMM" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECFBADBSC0,Secure Group Setting Register for FBADBSC 0" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECFBADBSC1,Secure Group Setting Register for FBADBSC 1" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECFBAMM,Secure Group Setting Register for FBAMM" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECIPMMUMM,Secure Group Setting Register for IPMMUMM" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECDBS00,Secure Group Setting Register for DBS 00" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECDBS01,Secure Group Setting Register for DBS 01" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECDBS10,Secure Group Setting Register for DBS 10" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECDBS11,Secure Group Setting Register for DBS 11" bitfld.long 0x48 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFF803400++0x23 line.long 0x0 "SECARSN0,Secure Group Setting Register for ARSN 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARSN1,Secure Group Setting Register for ARSN 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARSN2,Secure Group Setting Register for ARSN 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARSN3,Secure Group Setting Register for ARSN 3" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARSN4,Secure Group Setting Register for ARSN 4" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARSN5,Secure Group Setting Register for ARSN 5" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARSN6,Secure Group Setting Register for ARSN 6" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARSN7,Secure Group Setting Register for ARSN 7" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARSN8,Secure Group Setting Register for ARSN 8" bitfld.long 0x20 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE7753400++0xEF line.long 0x0 "SECARSD00,Secure Group Setting Register for ARSD 00" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARSD01,Secure Group Setting Register for ARSD 01" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARSD02,Secure Group Setting Register for ARSD 02" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARSD03,Secure Group Setting Register for ARSD 03" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARSD04,Secure Group Setting Register for ARSD 04" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARSD05,Secure Group Setting Register for ARSD 05" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARSD06,Secure Group Setting Register for ARSD 06" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECFRAY,Secure Group Setting Register for FRAY" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECIPC_AXI,Secure Group Setting Register for IPC AXI" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECLBSC,Secure Group Setting Register for LBSC" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECRPC,Secure Group Setting Register for RPC" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECSDHI0,Secure Group Setting Register for SDHI 0" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECARSD07,Secure Group Setting Register for ARSD 07" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECARSD08,Secure Group Setting Register for ARSD 08" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECARSP00,Secure Group Setting Register for ARSP 00" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECARSP01,Secure Group Setting Register for ARSP 01" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECARSP02,Secure Group Setting Register for ARSP 02" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECARSP03,Secure Group Setting Register for ARSP 03" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECARSP04,Secure Group Setting Register for ARSP 04" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECARSP05,Secure Group Setting Register for ARSP 05" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECARSP06,Secure Group Setting Register for ARSP 06" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECARSP07,Secure Group Setting Register for ARSP 07" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECARSP08,Secure Group Setting Register for ARSP 08" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECCANFD,Secure Group Setting Register for CANFD" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECCKMPE0,Secure Group Setting Register for CKMPE 0" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECECMPER0,Secure Group Setting Register for ECMPER 0" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECFBAPER0,Secure Group Setting Register for FBAPER 0" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECFSO0,Secure Group Setting Register for FSO 0" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECFSO1,Secure Group Setting Register for FSO 1" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECFSO10,Secure Group Setting Register for FSO 10" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECFSO2,Secure Group Setting Register for FSO 2" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECFSO3,Secure Group Setting Register for FSO 3" bitfld.long 0x7C 0. "SECGRP" "0,1" line.long 0x80 "SECFSO4,Secure Group Setting Register for FSO 4" bitfld.long 0x80 0. "SECGRP" "0,1" line.long 0x84 "SECFSO5,Secure Group Setting Register for FSO 5" bitfld.long 0x84 0. "SECGRP" "0,1" line.long 0x88 "SECFSO6,Secure Group Setting Register for FSO 6" bitfld.long 0x88 0. "SECGRP" "0,1" line.long 0x8C "SECFSO7,Secure Group Setting Register for FSO 7" bitfld.long 0x8C 0. "SECGRP" "0,1" line.long 0x90 "SECFSO8,Secure Group Setting Register for FSO 8" bitfld.long 0x90 0. "SECGRP" "0,1" line.long 0x94 "SECFSO9,Secure Group Setting Register for FSO 9" bitfld.long 0x94 0. "SECGRP" "0,1" line.long 0x98 "SECHSCIF0,Secure Group Setting Register for HSCIF 0" bitfld.long 0x98 0. "SECGRP" "0,1" line.long 0x9C "SECHSCIF1,Secure Group Setting Register for HSCIF 1" bitfld.long 0x9C 0. "SECGRP" "0,1" line.long 0xA0 "SECHSCIF2,Secure Group Setting Register for HSCIF 2" bitfld.long 0xA0 0. "SECGRP" "0,1" line.long 0xA4 "SECHSCIF3,Secure Group Setting Register for HSCIF 3" bitfld.long 0xA4 0. "SECGRP" "0,1" line.long 0xA8 "SECI2C0,Secure Group Setting Register for I2C 0" bitfld.long 0xA8 0. "SECGRP" "0,1" line.long 0xAC "SECI2C1,Secure Group Setting Register for I2C 1" bitfld.long 0xAC 0. "SECGRP" "0,1" line.long 0xB0 "SECI2C2,Secure Group Setting Register for I2C 2" bitfld.long 0xB0 0. "SECGRP" "0,1" line.long 0xB4 "SECI2C3,Secure Group Setting Register for I2C 3" bitfld.long 0xB4 0. "SECGRP" "0,1" line.long 0xB8 "SECI2C4,Secure Group Setting Register for I2C 4" bitfld.long 0xB8 0. "SECGRP" "0,1" line.long 0xBC "SECI2C5,Secure Group Setting Register for I2C 5" bitfld.long 0xBC 0. "SECGRP" "0,1" line.long 0xC0 "SECI2C6,Secure Group Setting Register for I2C 6" bitfld.long 0xC0 0. "SECGRP" "0,1" line.long 0xC4 "SECIPC_APB,Secure Group Setting Register for IPC APB" bitfld.long 0xC4 0. "SECGRP" "0,1" line.long 0xC8 "SECIPMMUDS0,Secure Group Setting Register for IPMMUDS 0" bitfld.long 0xC8 0. "SECGRP" "0,1" line.long 0xCC "SECPWM0,Secure Group Setting Register for PWM 0" bitfld.long 0xCC 0. "SECGRP" "0,1" line.long 0xD0 "SECPWM1,Secure Group Setting Register for PWM 1" bitfld.long 0xD0 0. "SECGRP" "0,1" line.long 0xD4 "SECPWM2,Secure Group Setting Register for PWM 2" bitfld.long 0xD4 0. "SECGRP" "0,1" line.long 0xD8 "SECPWM3,Secure Group Setting Register for PWM 3" bitfld.long 0xD8 0. "SECGRP" "0,1" line.long 0xDC "SECPWM4,Secure Group Setting Register for PWM 4" bitfld.long 0xDC 0. "SECGRP" "0,1" line.long 0xE0 "SECSCIF0,Secure Group Setting Register for SCIF 0" bitfld.long 0xE0 0. "SECGRP" "0,1" line.long 0xE4 "SECSCIF1,Secure Group Setting Register for SCIF 1" bitfld.long 0xE4 0. "SECGRP" "0,1" line.long 0xE8 "SECSCIF3,Secure Group Setting Register for SCIF 3" bitfld.long 0xE8 0. "SECGRP" "0,1" line.long 0xEC "SECSCIF4,Secure Group Setting Register for SCIF 4" bitfld.long 0xEC 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE77534F4++0x3 line.long 0x0 "SECSYDM1P,Secure Group Setting Register for SYDM1P" bitfld.long 0x0 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE77534FC++0x17 line.long 0x0 "SECSYDM2P,Secure Group Setting Register for SYDM2P" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECTMU1,Secure Group Setting Register for TMU 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECTMU2,Secure Group Setting Register for TMU 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECTMU3,Secure Group Setting Register for TMU 3" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECTMU4,Secure Group Setting Register for TMU 4" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECTPU0,Secure Group Setting Register for TPU 0" bitfld.long 0x14 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE7753640++0x7F line.long 0x0 "SECSYDM10,Secure Group Setting Register for SYDM 10" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECSYDM11,Secure Group Setting Register for SYDM 11" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECSYDM110,Secure Group Setting Register for SYDM 110" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECSYDM111,Secure Group Setting Register for SYDM 111" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECSYDM112,Secure Group Setting Register for SYDM 112" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECSYDM113,Secure Group Setting Register for SYDM 113" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECSYDM114,Secure Group Setting Register for SYDM 114" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECSYDM115,Secure Group Setting Register for SYDM 115" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECSYDM12,Secure Group Setting Register for SYDM 12" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECSYDM13,Secure Group Setting Register for SYDM 13" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECSYDM14,Secure Group Setting Register for SYDM 14" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECSYDM15,Secure Group Setting Register for SYDM 15" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECSYDM16,Secure Group Setting Register for SYDM 16" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECSYDM17,Secure Group Setting Register for SYDM 17" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECSYDM18,Secure Group Setting Register for SYDM 18" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECSYDM19,Secure Group Setting Register for SYDM 19" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECSYDM20,Secure Group Setting Register for SYDM 20" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECSYDM21,Secure Group Setting Register for SYDM 21" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECSYDM210,Secure Group Setting Register for SYDM 210" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECSYDM211,Secure Group Setting Register for SYDM 211" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECSYDM212,Secure Group Setting Register for SYDM 212" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECSYDM213,Secure Group Setting Register for SYDM 213" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECSYDM214,Secure Group Setting Register for SYDM 214" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECSYDM215,Secure Group Setting Register for SYDM 215" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECSYDM22,Secure Group Setting Register for SYDM 22" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECSYDM23,Secure Group Setting Register for SYDM 23" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECSYDM24,Secure Group Setting Register for SYDM 24" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECSYDM25,Secure Group Setting Register for SYDM 25" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECSYDM26,Secure Group Setting Register for SYDM 26" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECSYDM27,Secure Group Setting Register for SYDM 27" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECSYDM28,Secure Group Setting Register for SYDM 28" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECSYDM29,Secure Group Setting Register for SYDM 29" bitfld.long 0x7C 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE6583400++0x15F line.long 0x0 "SECPCI0_00,Secure Group Setting Register for PCI0_00" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECPCI0_01,Secure Group Setting Register for PCI0_01" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECPCI0_02,Secure Group Setting Register for PCI0_02" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECPCI0_03,Secure Group Setting Register for PCI0_03" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECPCI0_04,Secure Group Setting Register for PCI0_04" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECPCI0_05,Secure Group Setting Register for PCI0_05" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECPCI0_06,Secure Group Setting Register for PCI0_06" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECPCI0_07,Secure Group Setting Register for PCI0_07" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECPCI0_08,Secure Group Setting Register for PCI0_08" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECPCI0_09,Secure Group Setting Register for PCI0_09" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECPCI0_10,Secure Group Setting Register for PCI0_10" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECPCI0_11,Secure Group Setting Register for PCI0_11" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECPCI0_12,Secure Group Setting Register for PCI0_12" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECPCI0_13,Secure Group Setting Register for PCI0_13" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECPCI0_14,Secure Group Setting Register for PCI0_14" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECPCI0_15,Secure Group Setting Register for PCI0_15" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECPCI1_00,Secure Group Setting Register for PCI1_00" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECPCI1_01,Secure Group Setting Register for PCI1_01" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECPCI1_02,Secure Group Setting Register for PCI1_02" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECPCI1_03,Secure Group Setting Register for PCI1_03" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECPCI1_04,Secure Group Setting Register for PCI1_04" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECPCI1_05,Secure Group Setting Register for PCI1_05" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECPCI1_06,Secure Group Setting Register for PCI1_06" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECPCI1_07,Secure Group Setting Register for PCI1_07" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECPCI1_08,Secure Group Setting Register for PCI1_08" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECPCI1_09,Secure Group Setting Register for PCI1_09" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECPCI1_10,Secure Group Setting Register for PCI1_10" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECPCI1_11,Secure Group Setting Register for PCI1_11" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECPCI1_12,Secure Group Setting Register for PCI1_12" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECPCI1_13,Secure Group Setting Register for PCI1_13" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECPCI1_14,Secure Group Setting Register for PCI1_14" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECPCI1_15,Secure Group Setting Register for PCI1_15" bitfld.long 0x7C 0. "SECGRP" "0,1" line.long 0x80 "SECPCI2_00,Secure Group Setting Register for PCI2_00" bitfld.long 0x80 0. "SECGRP" "0,1" line.long 0x84 "SECPCI2_01,Secure Group Setting Register for PCI2_01" bitfld.long 0x84 0. "SECGRP" "0,1" line.long 0x88 "SECPCI2_02,Secure Group Setting Register for PCI2_02" bitfld.long 0x88 0. "SECGRP" "0,1" line.long 0x8C "SECPCI2_03,Secure Group Setting Register for PCI2_03" bitfld.long 0x8C 0. "SECGRP" "0,1" line.long 0x90 "SECPCI2_04,Secure Group Setting Register for PCI2_04" bitfld.long 0x90 0. "SECGRP" "0,1" line.long 0x94 "SECPCI2_05,Secure Group Setting Register for PCI2_05" bitfld.long 0x94 0. "SECGRP" "0,1" line.long 0x98 "SECPCI2_06,Secure Group Setting Register for PCI2_06" bitfld.long 0x98 0. "SECGRP" "0,1" line.long 0x9C "SECPCI2_07,Secure Group Setting Register for PCI2_07" bitfld.long 0x9C 0. "SECGRP" "0,1" line.long 0xA0 "SECPCI2_08,Secure Group Setting Register for PCI2_08" bitfld.long 0xA0 0. "SECGRP" "0,1" line.long 0xA4 "SECPCI2_09,Secure Group Setting Register for PCI2_09" bitfld.long 0xA4 0. "SECGRP" "0,1" line.long 0xA8 "SECPCI2_10,Secure Group Setting Register for PCI2_10" bitfld.long 0xA8 0. "SECGRP" "0,1" line.long 0xAC "SECPCI2_11,Secure Group Setting Register for PCI2_11" bitfld.long 0xAC 0. "SECGRP" "0,1" line.long 0xB0 "SECPCI2_12,Secure Group Setting Register for PCI2_12" bitfld.long 0xB0 0. "SECGRP" "0,1" line.long 0xB4 "SECPCI2_13,Secure Group Setting Register for PCI2_13" bitfld.long 0xB4 0. "SECGRP" "0,1" line.long 0xB8 "SECPCI2_14,Secure Group Setting Register for PCI2_14" bitfld.long 0xB8 0. "SECGRP" "0,1" line.long 0xBC "SECPCI2_15,Secure Group Setting Register for PCI2_15" bitfld.long 0xBC 0. "SECGRP" "0,1" line.long 0xC0 "SECPCI3_00,Secure Group Setting Register for PCI3_00" bitfld.long 0xC0 0. "SECGRP" "0,1" line.long 0xC4 "SECPCI3_01,Secure Group Setting Register for PCI3_01" bitfld.long 0xC4 0. "SECGRP" "0,1" line.long 0xC8 "SECPCI3_02,Secure Group Setting Register for PCI3_02" bitfld.long 0xC8 0. "SECGRP" "0,1" line.long 0xCC "SECPCI3_03,Secure Group Setting Register for PCI3_03" bitfld.long 0xCC 0. "SECGRP" "0,1" line.long 0xD0 "SECPCI3_04,Secure Group Setting Register for PCI3_04" bitfld.long 0xD0 0. "SECGRP" "0,1" line.long 0xD4 "SECPCI3_05,Secure Group Setting Register for PCI3_05" bitfld.long 0xD4 0. "SECGRP" "0,1" line.long 0xD8 "SECPCI3_06,Secure Group Setting Register for PCI3_06" bitfld.long 0xD8 0. "SECGRP" "0,1" line.long 0xDC "SECPCI3_07,Secure Group Setting Register for PCI3_07" bitfld.long 0xDC 0. "SECGRP" "0,1" line.long 0xE0 "SECPCI3_08,Secure Group Setting Register for PCI3_08" bitfld.long 0xE0 0. "SECGRP" "0,1" line.long 0xE4 "SECPCI3_09,Secure Group Setting Register for PCI3_09" bitfld.long 0xE4 0. "SECGRP" "0,1" line.long 0xE8 "SECPCI3_10,Secure Group Setting Register for PCI3_10" bitfld.long 0xE8 0. "SECGRP" "0,1" line.long 0xEC "SECPCI3_11,Secure Group Setting Register for PCI3_11" bitfld.long 0xEC 0. "SECGRP" "0,1" line.long 0xF0 "SECPCI3_12,Secure Group Setting Register for PCI3_12" bitfld.long 0xF0 0. "SECGRP" "0,1" line.long 0xF4 "SECPCI3_13,Secure Group Setting Register for PCI3_13" bitfld.long 0xF4 0. "SECGRP" "0,1" line.long 0xF8 "SECPCI3_14,Secure Group Setting Register for PCI3_14" bitfld.long 0xF8 0. "SECGRP" "0,1" line.long 0xFC "SECPCI3_15,Secure Group Setting Register for PCI3_15" bitfld.long 0xFC 0. "SECGRP" "0,1" line.long 0x100 "SECAVB0,Secure Group Setting Register for AVB 0" bitfld.long 0x100 0. "SECGRP" "0,1" line.long 0x104 "SECAVB1,Secure Group Setting Register for AVB 1" bitfld.long 0x104 0. "SECGRP" "0,1" line.long 0x108 "SECAVB2,Secure Group Setting Register for AVB 2" bitfld.long 0x108 0. "SECGRP" "0,1" line.long 0x10C "SECAVB3,Secure Group Setting Register for AVB 3" bitfld.long 0x10C 0. "SECGRP" "0,1" line.long 0x110 "SECAVB4,Secure Group Setting Register for AVB 4" bitfld.long 0x110 0. "SECGRP" "0,1" line.long 0x114 "SECAVB5,Secure Group Setting Register for AVB 5" bitfld.long 0x114 0. "SECGRP" "0,1" line.long 0x118 "SECADG,Secure Group Setting Register for ADG" bitfld.long 0x118 0. "SECGRP" "0,1" line.long 0x11C "SECPPHY0,Secure Group Setting Register for PPHY 0" bitfld.long 0x11C 0. "SECGRP" "0,1" line.long 0x120 "SECPPHY1,Secure Group Setting Register for PPHY 1" bitfld.long 0x120 0. "SECGRP" "0,1" line.long 0x124 "SECPPHY2,Secure Group Setting Register for PPHY 2" bitfld.long 0x124 0. "SECGRP" "0,1" line.long 0x128 "SECPPHY3,Secure Group Setting Register for PPHY 3" bitfld.long 0x128 0. "SECGRP" "0,1" line.long 0x12C "SECFBAPER1,Secure Group Setting Register for FBAPER 1" bitfld.long 0x12C 0. "SECGRP" "0,1" line.long 0x130 "SECIPMMUDS1,Secure Group Setting Register for IPMMUDS 1" bitfld.long 0x130 0. "SECGRP" "0,1" line.long 0x134 "SECCKMPE1,Secure Group Setting Register for CKMPE 1" bitfld.long 0x134 0. "SECGRP" "0,1" line.long 0x138 "SECECMPER1,Secure Group Setting Register for ECMPER 1" bitfld.long 0x138 0. "SECGRP" "0,1" line.long 0x13C "SECARSP10,Secure Group Setting Register for ARSP 10" bitfld.long 0x13C 0. "SECGRP" "0,1" line.long 0x140 "SECARSP11,Secure Group Setting Register for ARSP 11" bitfld.long 0x140 0. "SECGRP" "0,1" line.long 0x144 "SECARSP12,Secure Group Setting Register for ARSP 12" bitfld.long 0x144 0. "SECGRP" "0,1" line.long 0x148 "SECARSP13,Secure Group Setting Register for ARSP 13" bitfld.long 0x148 0. "SECGRP" "0,1" line.long 0x14C "SECARSP14,Secure Group Setting Register for ARSP 14" bitfld.long 0x14C 0. "SECGRP" "0,1" line.long 0x150 "SECARSP15,Secure Group Setting Register for ARSP 15" bitfld.long 0x150 0. "SECGRP" "0,1" line.long 0x154 "SECARSP16,Secure Group Setting Register for ARSP 16" bitfld.long 0x154 0. "SECGRP" "0,1" line.long 0x158 "SECARSP17,Secure Group Setting Register for ARSP 17" bitfld.long 0x158 0. "SECGRP" "0,1" line.long 0x15C "SECARSP18,Secure Group Setting Register for ARSP 18" bitfld.long 0x15C 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFE683400++0x7F line.long 0x0 "SECARVC0,Secure Group Setting Register for ARVC 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARVC1,Secure Group Setting Register for ARVC 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARVC2,Secure Group Setting Register for ARVC 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARVC3,Secure Group Setting Register for ARVC 3" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECFBABUSVC,Secure Group Setting Register for FBABUSVC" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARVC4,Secure Group Setting Register for ARVC 4" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARVC5,Secure Group Setting Register for ARVC 5" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARVC6,Secure Group Setting Register for ARVC 6" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARVC7,Secure Group Setting Register for ARVC 7" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECARVC8,Secure Group Setting Register for ARVC 8" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECCKMVC,Secure Group Setting Register for CKMVC" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECECMVC,Secure Group Setting Register for ECMVC" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECFCPCS,Secure Group Setting Register for FCPCS" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECIMR0,Secure Group Setting Register for IMR 0" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECIMR1,Secure Group Setting Register for IMR 1" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECIMR2,Secure Group Setting Register for IMR 2" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECIMR3,Secure Group Setting Register for IMR 3" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECIMS0,Secure Group Setting Register for IMS 0" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECIMS1,Secure Group Setting Register for IMS 1" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECIPMMUVC,Secure Group Setting Register for IPMMUVC" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECIV1ES,Secure Group Setting Register for IV1ES" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECVCP4LC,Secure Group Setting Register for VCP4LC" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECVCP4LV,Secure Group Setting Register for VCP4LV" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECFCPRAVC0_A,Secure Group Setting Register for FCPRAVC0_A" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECIMR00_R,Secure Group Setting Register for IMR00_R" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECIMR0COMX_W,Secure Group Setting Register for IMR0COMX_W" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECIMR10_R,Secure Group Setting Register for IMR10_R" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECIMR1COMX_W,Secure Group Setting Register for IMR1COMX_W" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECIMR20_R,Secure Group Setting Register for IMR20_R" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECIMR30_R,Secure Group Setting Register for IMR30_R" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECIMS0_R,Secure Group Setting Register for IMS0_R" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECIMS1_R,Secure Group Setting Register for IMS1_R" bitfld.long 0x7C 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFEBE3400++0x93 line.long 0x0 "SECFBABUSVIO,Secure Group Setting Register for FBABUSVIO" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARVI10,Secure Group Setting Register for ARVI 10" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARVI11,Secure Group Setting Register for ARVI 11" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARVI12,Secure Group Setting Register for ARVI 12" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARVI13,Secure Group Setting Register for ARVI 13" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARVI14,Secure Group Setting Register for ARVI 14" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARVI15,Secure Group Setting Register for ARVI 15" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARVI16,Secure Group Setting Register for ARVI 16" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARVI17,Secure Group Setting Register for ARVI 17" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECARVI18,Secure Group Setting Register for ARVI 18" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECCKMVIO,Secure Group Setting Register for CKMVIO" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECDIS0,Secure Group Setting Register for DIS 0" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECDOC2CH,Secure Group Setting Register for DOC2CH" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECDSITXLINK0,Secure Group Setting Register for DSITXLINK 0" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECDSITXLINK1,Secure Group Setting Register for DSITXLINK 1" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECECMVIO,Secure Group Setting Register for ECMVIO" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECFCPVD0,Secure Group Setting Register for FCPVD 0" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECFCPVD1,Secure Group Setting Register for FCPVD 1" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECFCPVX0,Secure Group Setting Register for FCPVX 0" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECFCPVX1,Secure Group Setting Register for FCPVX 1" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECFCPVX2,Secure Group Setting Register for FCPVX 2" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECFCPVX3,Secure Group Setting Register for FCPVX 3" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECIPMMUVI0,Secure Group Setting Register for IPMMUVI 0" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECIPMMUVI1,Secure Group Setting Register for IPMMUVI 1" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECVSPD0,Secure Group Setting Register for VSPD 0" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECVSPD1,Secure Group Setting Register for VSPD 1" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECVSPX0,Secure Group Setting Register for VSPX 0" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECVSPX1,Secure Group Setting Register for VSPX 1" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECVSPX2,Secure Group Setting Register for VSPX 2" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECVSPX3,Secure Group Setting Register for VSPX 3" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECFCPRAVI1_A,Secure Group Setting Register for FCPRAVI1_A" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECFCPVD0_R,Secure Group Setting Register for FCPVD0_R" bitfld.long 0x7C 0. "SECGRP" "0,1" line.long 0x80 "SECFCPVD1_R,Secure Group Setting Register for FCPVD1_R" bitfld.long 0x80 0. "SECGRP" "0,1" line.long 0x84 "SECFCPVX0_R,Secure Group Setting Register for FCPVX0_R" bitfld.long 0x84 0. "SECGRP" "0,1" line.long 0x88 "SECFCPVX1_R,Secure Group Setting Register for FCPVX1_R" bitfld.long 0x88 0. "SECGRP" "0,1" line.long 0x8C "SECFCPVX2_R,Secure Group Setting Register for FCPVX2_R" bitfld.long 0x8C 0. "SECGRP" "0,1" line.long 0x90 "SECFCPVX3_R,Secure Group Setting Register for FCPVX3_R" bitfld.long 0x90 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFEBF3400++0xDB line.long 0x0 "SECARVI0,Secure Group Setting Register for ARVI 0" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARVI1,Secure Group Setting Register for ARVI 1" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARVI2,Secure Group Setting Register for ARVI 2" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARVI3,Secure Group Setting Register for ARVI 3" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECARVI4,Secure Group Setting Register for ARVI 4" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARVI5,Secure Group Setting Register for ARVI 5" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARVI6,Secure Group Setting Register for ARVI 6" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARVI7,Secure Group Setting Register for ARVI 7" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARVI8,Secure Group Setting Register for ARVI 8" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECCSI4LNK0,Secure Group Setting Register for CSI4LNK 0" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECCSI4LNK1,Secure Group Setting Register for CSI4LNK 1" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECCSI4LNK2,Secure Group Setting Register for CSI4LNK 2" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECCSI4LNK3,Secure Group Setting Register for CSI4LNK 3" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECISP0,Secure Group Setting Register for ISP 0" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECISP0CORE,Secure Group Setting Register for ISP0CORE" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECISP1,Secure Group Setting Register for ISP 1" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECISP1CORE,Secure Group Setting Register for ISP1CORE" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECISP2,Secure Group Setting Register for ISP 2" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECISP2CORE,Secure Group Setting Register for ISP2CORE" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECISP3,Secure Group Setting Register for ISP 3" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECISP3CORE,Secure Group Setting Register for ISP3CORE" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECVIN00,Secure Group Setting Register for VIN 00" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECVIN01,Secure Group Setting Register for VIN 01" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECVIN02,Secure Group Setting Register for VIN 02" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECVIN03,Secure Group Setting Register for VIN 03" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECVIN04,Secure Group Setting Register for VIN 04" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECVIN05,Secure Group Setting Register for VIN 05" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECVIN06,Secure Group Setting Register for VIN 06" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECVIN07,Secure Group Setting Register for VIN 07" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECVIN10,Secure Group Setting Register for VIN 10" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECVIN11,Secure Group Setting Register for VIN 11" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECVIN12,Secure Group Setting Register for VIN 12" bitfld.long 0x7C 0. "SECGRP" "0,1" line.long 0x80 "SECVIN13,Secure Group Setting Register for VIN 13" bitfld.long 0x80 0. "SECGRP" "0,1" line.long 0x84 "SECVIN14,Secure Group Setting Register for VIN 14" bitfld.long 0x84 0. "SECGRP" "0,1" line.long 0x88 "SECVIN15,Secure Group Setting Register for VIN 15" bitfld.long 0x88 0. "SECGRP" "0,1" line.long 0x8C "SECVIN16,Secure Group Setting Register for VIN 16" bitfld.long 0x8C 0. "SECGRP" "0,1" line.long 0x90 "SECVIN17,Secure Group Setting Register for VIN 17" bitfld.long 0x90 0. "SECGRP" "0,1" line.long 0x94 "SECVIN20,Secure Group Setting Register for VIN 20" bitfld.long 0x94 0. "SECGRP" "0,1" line.long 0x98 "SECVIN21,Secure Group Setting Register for VIN 21" bitfld.long 0x98 0. "SECGRP" "0,1" line.long 0x9C "SECVIN22,Secure Group Setting Register for VIN 22" bitfld.long 0x9C 0. "SECGRP" "0,1" line.long 0xA0 "SECVIN23,Secure Group Setting Register for VIN 23" bitfld.long 0xA0 0. "SECGRP" "0,1" line.long 0xA4 "SECVIN24,Secure Group Setting Register for VIN 24" bitfld.long 0xA4 0. "SECGRP" "0,1" line.long 0xA8 "SECVIN25,Secure Group Setting Register for VIN 25" bitfld.long 0xA8 0. "SECGRP" "0,1" line.long 0xAC "SECVIN26,Secure Group Setting Register for VIN 26" bitfld.long 0xAC 0. "SECGRP" "0,1" line.long 0xB0 "SECVIN27,Secure Group Setting Register for VIN 27" bitfld.long 0xB0 0. "SECGRP" "0,1" line.long 0xB4 "SECVIN30,Secure Group Setting Register for VIN 30" bitfld.long 0xB4 0. "SECGRP" "0,1" line.long 0xB8 "SECVIN31,Secure Group Setting Register for VIN 31" bitfld.long 0xB8 0. "SECGRP" "0,1" line.long 0xBC "SECVIN32,Secure Group Setting Register for VIN 32" bitfld.long 0xBC 0. "SECGRP" "0,1" line.long 0xC0 "SECVIN33,Secure Group Setting Register for VIN 33" bitfld.long 0xC0 0. "SECGRP" "0,1" line.long 0xC4 "SECVIN34,Secure Group Setting Register for VIN 34" bitfld.long 0xC4 0. "SECGRP" "0,1" line.long 0xC8 "SECVIN35,Secure Group Setting Register for VIN 35" bitfld.long 0xC8 0. "SECGRP" "0,1" line.long 0xCC "SECVIN36,Secure Group Setting Register for VIN 36" bitfld.long 0xCC 0. "SECGRP" "0,1" line.long 0xD0 "SECVIN37,Secure Group Setting Register for VIN 37" bitfld.long 0xD0 0. "SECGRP" "0,1" line.long 0xD4 "SECISPCOMX_W,Secure Group Setting Register for ISPCOMX_W" bitfld.long 0xD4 0. "SECGRP" "0,1" line.long 0xD8 "SECVINCOMX_W,Secure Group Setting Register for VINCOMX_W" bitfld.long 0xD8 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE7B13400++0x53 line.long 0x0 "SECARVIP00,Secure Group Setting Register for ARVIP 00" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARVIP01,Secure Group Setting Register for ARVIP 01" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARVIP02,Secure Group Setting Register for ARVIP 02" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARVIP03,Secure Group Setting Register for ARVIP 03" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECFBABUSVIP0,Secure Group Setting Register for FBABUSVIP 0" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARVIP04,Secure Group Setting Register for ARVIP 04" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARVIP05,Secure Group Setting Register for ARVIP 05" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARVIP06,Secure Group Setting Register for ARVIP 06" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARVIP07,Secure Group Setting Register for ARVIP 07" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECARVIP08,Secure Group Setting Register for ARVIP 08" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECCKMVIP,Secure Group Setting Register for CKMVIP" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECECMVIP,Secure Group Setting Register for ECMVIP" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECIPMMUVIP0,Secure Group Setting Register for IPMMUVIP 0" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECSMES0,Secure Group Setting Register for SMES 0" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECSMPO0,Secure Group Setting Register for SMPO 0" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECSMPS0,Secure Group Setting Register for SMPS 0" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECUMFL0,Secure Group Setting Register for UMFL 0" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECFCPRAVIP0_A,Secure Group Setting Register for FCPRAVIP0_A" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECSMPS0_R,Secure Group Setting Register for SMPS0_R" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECUMFL0_R,Secure Group Setting Register for UMFL0_R" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECUMFL0_W,Secure Group Setting Register for UMFL0_W" bitfld.long 0x50 0. "SECGRP" "0,1" group.long 0xFFFFFFFFE7B43400++0x7F line.long 0x0 "SECARVIP10,Secure Group Setting Register for ARVIP 10" bitfld.long 0x0 0. "SECGRP" "0,1" line.long 0x4 "SECARVIP11,Secure Group Setting Register for ARVIP 11" bitfld.long 0x4 0. "SECGRP" "0,1" line.long 0x8 "SECARVIP12,Secure Group Setting Register for ARVIP 12" bitfld.long 0x8 0. "SECGRP" "0,1" line.long 0xC "SECARVIP13,Secure Group Setting Register for ARVIP 13" bitfld.long 0xC 0. "SECGRP" "0,1" line.long 0x10 "SECFBABUSVIP1,Secure Group Setting Register for FBABUSVIP 1" bitfld.long 0x10 0. "SECGRP" "0,1" line.long 0x14 "SECARVIP14,Secure Group Setting Register for ARVIP 14" bitfld.long 0x14 0. "SECGRP" "0,1" line.long 0x18 "SECARVIP15,Secure Group Setting Register for ARVIP 15" bitfld.long 0x18 0. "SECGRP" "0,1" line.long 0x1C "SECARVIP16,Secure Group Setting Register for ARVIP 16" bitfld.long 0x1C 0. "SECGRP" "0,1" line.long 0x20 "SECARVIP17,Secure Group Setting Register for ARVIP 17" bitfld.long 0x20 0. "SECGRP" "0,1" line.long 0x24 "SECARVIP18,Secure Group Setting Register for ARVIP 18" bitfld.long 0x24 0. "SECGRP" "0,1" line.long 0x28 "SECCLE0,Secure Group Setting Register for CLE 0" bitfld.long 0x28 0. "SECGRP" "0,1" line.long 0x2C "SECCLE1,Secure Group Setting Register for CLE 1" bitfld.long 0x2C 0. "SECGRP" "0,1" line.long 0x30 "SECCLE2,Secure Group Setting Register for CLE 2" bitfld.long 0x30 0. "SECGRP" "0,1" line.long 0x34 "SECCLE3,Secure Group Setting Register for CLE 3" bitfld.long 0x34 0. "SECGRP" "0,1" line.long 0x38 "SECDISP0,Secure Group Setting Register for DISP 0" bitfld.long 0x38 0. "SECGRP" "0,1" line.long 0x3C "SECDISP1,Secure Group Setting Register for DISP 1" bitfld.long 0x3C 0. "SECGRP" "0,1" line.long 0x40 "SECIPMMUVIP1,Secure Group Setting Register for IPMMUVIP 1" bitfld.long 0x40 0. "SECGRP" "0,1" line.long 0x44 "SECSMES1,Secure Group Setting Register for SMES 1" bitfld.long 0x44 0. "SECGRP" "0,1" line.long 0x48 "SECSMPO1,Secure Group Setting Register for SMPO 1" bitfld.long 0x48 0. "SECGRP" "0,1" line.long 0x4C "SECSMPS1,Secure Group Setting Register for SMPS 1" bitfld.long 0x4C 0. "SECGRP" "0,1" line.long 0x50 "SECUMFL1,Secure Group Setting Register for UMFL 1" bitfld.long 0x50 0. "SECGRP" "0,1" line.long 0x54 "SECCLE0_R,Secure Group Setting Register for CLE0_R" bitfld.long 0x54 0. "SECGRP" "0,1" line.long 0x58 "SECCLE1_R,Secure Group Setting Register for CLE1_R" bitfld.long 0x58 0. "SECGRP" "0,1" line.long 0x5C "SECCLE2_R,Secure Group Setting Register for CLE2_R" bitfld.long 0x5C 0. "SECGRP" "0,1" line.long 0x60 "SECCLE3_R,Secure Group Setting Register for CLE3_R" bitfld.long 0x60 0. "SECGRP" "0,1" line.long 0x64 "SECDISP0_R,Secure Group Setting Register for DISP0_R" bitfld.long 0x64 0. "SECGRP" "0,1" line.long 0x68 "SECDISP1_R,Secure Group Setting Register for DISP1_R" bitfld.long 0x68 0. "SECGRP" "0,1" line.long 0x6C "SECFCPRAVIP1_A,Secure Group Setting Register for FCPRAVIP1_A" bitfld.long 0x6C 0. "SECGRP" "0,1" line.long 0x70 "SECFCPRAVIP2_A,Secure Group Setting Register for FCPRAVIP2_A" bitfld.long 0x70 0. "SECGRP" "0,1" line.long 0x74 "SECSMPS1_R,Secure Group Setting Register for SMPS1_R" bitfld.long 0x74 0. "SECGRP" "0,1" line.long 0x78 "SECUMFL1_R,Secure Group Setting Register for UMFL1_R" bitfld.long 0x78 0. "SECGRP" "0,1" line.long 0x7C "SECUMFL1_W,Secure Group Setting Register for UMFL1_W" bitfld.long 0x7C 0. "SECGRP" "0,1" group.long 0xFFFFFFFFFFC85010++0x3 line.long 0x0 "SECERR0_APRT0,Secure Error Status Register for RT Domain APB 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6005010++0x3 line.long 0x0 "SECERR0_APS0,Secure Error Status Register for Top Slave Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7795010++0x3 line.long 0x0 "SECERR0_APSD3,Secure Error Status Register for PER0 Domain DMA Bus 3" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7765010++0x3 line.long 0x0 "SECERR0_APSP3,Secure Error Status Register for PERI0 Domain 3" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF885010++0x3 line.long 0x0 "SECERR0_AXIMP0,Secure Error Status Register for IR Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD815010++0x3 line.long 0x0 "SECERR0_AXGFX,Secure Error Status Register for GFX Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6625010++0x3 line.long 0x0 "SECERR0_AXRC,Secure Error Status Register for RT Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFFC35010++0x3 line.long 0x0 "SECERR0_AXRD,Secure Error Status Register for RT Domain DMA Bus" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFFC45010++0x7 line.long 0x0 "SECERR0_AXRT,Secure Error Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "SECERR1_AXRT,Secure Error Status Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF865010++0x3 line.long 0x0 "SECERR0_AXSC,Secure Error Status Register for Top Slave Domain 1" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7785010++0x3 line.long 0x0 "SECERR0_AXSD0,Secure Error Status Register for PER0 Domain DMA Bus" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67C5010++0x3 line.long 0x0 "SECERR0_AXSM,Secure Error Status Register for MM Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF805010++0x3 line.long 0x0 "SECERR0_AXSN,Secure Error Status Register for Top Slave Domain 2" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7755010++0x7 line.long 0x0 "SECERR0_AXSP0,Secure Error Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "SECERR1_AXSP0,Secure Error Status Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6585010++0x3 line.long 0x0 "SECERR0_AXSP1,Secure Error Status Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE685010++0x3 line.long 0x0 "SECERR0_AXVC,Secure Error Status Register for VC Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEBE5010++0x3 line.long 0x0 "SECERR0_AXVI1,Secure Error Status Register for VIO Domain 10" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEBF5010++0x7 line.long 0x0 "SECERR0_AXVI,Secure Error Status Register for VIO Domain 00" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "SECERR1_AXVI,Secure Error Status Register for VIO Domain 01" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7B15010++0x3 line.long 0x0 "SECERR0_AXVIP0,Secure Error Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7B45010++0x3 line.long 0x0 "SECERR0_AXVIP1,Secure Error Status Register for VIP Domain 1" hexmask.long 0x0 0.--31. 1. "STATUS" rgroup.long 0xFFFFFFFFFFC85020++0x3 line.long 0x0 "SECID_APRT0,Secure Error ID Register for RT Domain APB 0" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE6005020++0x3 line.long 0x0 "SECID_APS0,Secure Error ID Register for Top Slave Domain 0" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7795020++0x3 line.long 0x0 "SECID_APSD3,Secure Error ID Register for PER0 Domain DMA Bus 3" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7765020++0x3 line.long 0x0 "SECID_APSP3,Secure Error ID Register for PERI0 Domain 3" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFF885020++0x3 line.long 0x0 "SECID_AXIMP0,Secure Error ID Register for IR Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFD815020++0x3 line.long 0x0 "SECID_AXGFX,Secure Error ID Register for GFX Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE6625020++0x3 line.long 0x0 "SECID_AXRC,Secure Error ID Register for RT Domain 0" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFFC35020++0x3 line.long 0x0 "SECID_AXRD,Secure Error ID Register for RT Domain DMA Bus" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFFC45020++0x3 line.long 0x0 "SECID_AXRT,Secure Error ID Register for RT Domain 1" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFF865020++0x3 line.long 0x0 "SECID_AXSC,Secure Error ID Register for Top Slave Domain 1" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7785020++0x3 line.long 0x0 "SECID_AXSD0,Secure Error ID Register for PER0 Domain DMA Bus" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE67C5020++0x3 line.long 0x0 "SECID_AXSM,Secure Error ID Register for MM Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFF805020++0x3 line.long 0x0 "SECID_AXSN,Secure Error ID Register for Top Slave Domain 2" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7755020++0x3 line.long 0x0 "SECID_AXSP0,Secure Error ID Register for PER0 Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE6585020++0x3 line.long 0x0 "SECID_AXSP1,Secure Error ID Register for PER1 Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFE685020++0x3 line.long 0x0 "SECID_AXVC,Secure Error ID Register for VC Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFEBE5020++0x3 line.long 0x0 "SECID_AXVI1,Secure Error ID Register for VIO Domain 10" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFFEBF5020++0x3 line.long 0x0 "SECID_AXVI,Secure Error ID Register for VIO Domain" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7B15020++0x3 line.long 0x0 "SECID_AXVIP0,Secure Error ID Register for VIP Domain 0" hexmask.long.byte 0x0 0.--7. 1. "SID" rgroup.long 0xFFFFFFFFE7B45020++0x3 line.long 0x0 "SECID_AXVIP1,Secure Error ID Register for VIP Domain 1" hexmask.long.byte 0x0 0.--7. 1. "SID" group.long 0xFFFFFFFFE6000700++0x3 line.long 0x0 "FDT_AXSC2APS0,Timeout Counter Setting Register for AXSC2APS 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE7790700++0x3 line.long 0x0 "FDT_AXSD02APSD3,Timeout Counter Setting Register for AXSD02APSD 3" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE7760700++0x3 line.long 0x0 "FDT_AXSP02APSP3,Timeout Counter Setting Register for AXSP02APSP 3" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFF880700++0x33 line.long 0x0 "FDT_AXSN2AXIMP0,Timeout Counter Setting Register for AXSN2AXIMP 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_FBABUSIR0,Timeout Counter Setting Register for FBABUSIR 0" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_FBABUSIR1,Timeout Counter Setting Register for FBABUSIR 1" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_FBABUSIR2,Timeout Counter Setting Register for FBABUSIR 2" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_FBABUSIR3,Timeout Counter Setting Register for FBABUSIR 3" hexmask.long.word 0x10 0.--15. 1. "COUNTER" line.long 0x14 "FDT_FBABUSIR4,Timeout Counter Setting Register for FBABUSIR 4" hexmask.long.word 0x14 0.--15. 1. "COUNTER" line.long 0x18 "FDT_FCPRAIR,Timeout Counter Setting Register for FCPRAIR" hexmask.long.word 0x18 0.--15. 1. "COUNTER" line.long 0x1C "FDT_IMP0,Timeout Counter Setting Register for IMP 0" hexmask.long.word 0x1C 0.--15. 1. "COUNTER" line.long 0x20 "FDT_IMP1,Timeout Counter Setting Register for IMP 1" hexmask.long.word 0x20 0.--15. 1. "COUNTER" line.long 0x24 "FDT_IMPD0,Timeout Counter Setting Register for IMPD 0" hexmask.long.word 0x24 0.--15. 1. "COUNTER" line.long 0x28 "FDT_RADSP00,Timeout Counter Setting Register for RADSP 00" hexmask.long.word 0x28 0.--15. 1. "COUNTER" line.long 0x2C "FDT_RADSP01,Timeout Counter Setting Register for RADSP 01" hexmask.long.word 0x2C 0.--15. 1. "COUNTER" line.long 0x30 "FDT_RADSP10,Timeout Counter Setting Register for RADSP 10" hexmask.long.word 0x30 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFF88074C++0x3 line.long 0x0 "FDT_RADSP11,Timeout Counter Setting Register for RADSP 11" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFD810700++0xB line.long 0x0 "FDT_AXSC2AXPV,Timeout Counter Setting Register for AXSC2AXPV" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_FBAPVD0,Timeout Counter Setting Register for FBAPVD 0" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_FBAPVD1,Timeout Counter Setting Register for FBAPVD 1" hexmask.long.word 0x8 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFD810710++0x7 line.long 0x0 "FDT_FBAPVD2,Timeout Counter Setting Register for FBAPVD 2" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_RGX0,Timeout Counter Setting Register for RGX 0" hexmask.long.word 0x4 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE6620204++0x3 line.long 0x0 "FDT_AXRT2AXRC,Timeout Counter Setting Register for AXRT2AXRC" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE662020C++0x7 line.long 0x0 "FDT_DCLS_ICUMX,Timeout Counter Setting Register for DCLS_ICUMX" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_ICUMX,Timeout Counter Setting Register for ICUMX" hexmask.long.word 0x4 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE6620704++0x3 line.long 0x0 "FDT_CR0,Timeout Counter Setting Register for CR 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFFC30700++0xF line.long 0x0 "FDT_PERI_RTDM0,Timeout Counter Setting Register for PERI_RTDM 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_PERI_RTDM1,Timeout Counter Setting Register for PERI_RTDM 1" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_PERI_RTDM2,Timeout Counter Setting Register for PERI_RTDM 2" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_PERI_RTDM3,Timeout Counter Setting Register for PERI_RTDM 3" hexmask.long.word 0xC 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFFC40700++0x37 line.long 0x0 "FDT_AXRC2AXRT,Timeout Counter Setting Register for AXRC2AXRT" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_AXSC2AXRT,Timeout Counter Setting Register for AXSC2AXRT" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_BUS_RTDM0,Timeout Counter Setting Register for BUS_RTDM 0" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_BUS_RTDM1,Timeout Counter Setting Register for BUS_RTDM 1" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_BUS_RTDM2,Timeout Counter Setting Register for BUS_RTDM 2" hexmask.long.word 0x10 0.--15. 1. "COUNTER" line.long 0x14 "FDT_BUS_RTDM3,Timeout Counter Setting Register for BUS_RTDM 3" hexmask.long.word 0x14 0.--15. 1. "COUNTER" line.long 0x18 "FDT_CR52SS,Timeout Counter Setting Register for CR52SS" hexmask.long.word 0x18 0.--15. 1. "COUNTER" line.long 0x1C "FDT_CSD,Timeout Counter Setting Register for CSD" hexmask.long.word 0x1C 0.--15. 1. "COUNTER" line.long 0x20 "FDT_FCPRART0,Timeout Counter Setting Register for FCPRART 0" hexmask.long.word 0x20 0.--15. 1. "COUNTER" line.long 0x24 "FDT_INTAP0,Timeout Counter Setting Register for INTAP 0" hexmask.long.word 0x24 0.--15. 1. "COUNTER" line.long 0x28 "FDT_MEM_RTDM0,Timeout Counter Setting Register for MEM_RTDM 0" hexmask.long.word 0x28 0.--15. 1. "COUNTER" line.long 0x2C "FDT_MEM_RTDM1,Timeout Counter Setting Register for MEM_RTDM 1" hexmask.long.word 0x2C 0.--15. 1. "COUNTER" line.long 0x30 "FDT_MEM_RTDM2,Timeout Counter Setting Register for MEM_RTDM 2" hexmask.long.word 0x30 0.--15. 1. "COUNTER" line.long 0x34 "FDT_MEM_RTDM3,Timeout Counter Setting Register for MEM_RTDM 3" hexmask.long.word 0x34 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFF860704++0x1B line.long 0x0 "FDT_AXRT2AXSC_RS,Timeout Counter Setting Register for AXRT2AXSC_RS" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_AXSM2AXSC_RS,Timeout Counter Setting Register for AXSM2AXSC_RS" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_AXSN2AXSC,Timeout Counter Setting Register for AXSN2AXSC" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_AXSP12AXSC_RS,Timeout Counter Setting Register for AXSP12AXSC_RS" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_CCIM_RS,Timeout Counter Setting Register for CCIM_RS" hexmask.long.word 0x10 0.--15. 1. "COUNTER" line.long 0x14 "FDT_FBABUSTOP0,Timeout Counter Setting Register for FBABUSTOP 0" hexmask.long.word 0x14 0.--15. 1. "COUNTER" line.long 0x18 "FDT_FBABUSTOP1,Timeout Counter Setting Register for FBABUSTOP 1" hexmask.long.word 0x18 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE7780704++0x7 line.long 0x0 "FDT_PERI_SYDM1,Timeout Counter Setting Register for PERI_SYDM 1" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_PERI_SYDM2,Timeout Counter Setting Register for PERI_SYDM 2" hexmask.long.word 0x4 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE67C0700++0x7 line.long 0x0 "FDT_AXMM2AXSM,Timeout Counter Setting Register for AXMM2AXSM" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_AXSC2AXSM,Timeout Counter Setting Register for AXSC2AXSM" hexmask.long.word 0x4 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFF800218++0x3 line.long 0x0 "FDT_AXIMP02AXSN_RS,Timeout Counter Setting Register for AXIMP02AXSN_RS" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFF800704++0x7 line.long 0x0 "FDT_AXSC2AXSN,Timeout Counter Setting Register for AXSC2AXSN" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_AXSP02AXSN_RS,Timeout Counter Setting Register for AXSP02AXSN_RS" hexmask.long.word 0x4 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE7750700++0x3 line.long 0x0 "FDT_AXSN2AXSP0,Timeout Counter Setting Register for AXSN2AXSP 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE7750708++0x1B line.long 0x0 "FDT_BUS_SYDM1,Timeout Counter Setting Register for BUS_SYDM 1" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_BUS_SYDM2,Timeout Counter Setting Register for BUS_SYDM 2" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_FRAYM,Timeout Counter Setting Register for FRAYM" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_IPCM,Timeout Counter Setting Register for IPCM" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_MEM_SYDM1,Timeout Counter Setting Register for MEM_SYDM 1" hexmask.long.word 0x10 0.--15. 1. "COUNTER" line.long 0x14 "FDT_MEM_SYDM2,Timeout Counter Setting Register for MEM_SYDM 2" hexmask.long.word 0x14 0.--15. 1. "COUNTER" line.long 0x18 "FDT_SDHI0,Timeout Counter Setting Register for SDHI 0" hexmask.long.word 0x18 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE6580700++0x33 line.long 0x0 "FDT_PCI0,Timeout Counter Setting Register for PCI 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_PCI1,Timeout Counter Setting Register for PCI 1" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_PCI2,Timeout Counter Setting Register for PCI 2" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_PCI3,Timeout Counter Setting Register for PCI 3" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_AVB0,Timeout Counter Setting Register for AVB 0" hexmask.long.word 0x10 0.--15. 1. "COUNTER" line.long 0x14 "FDT_AVB1,Timeout Counter Setting Register for AVB 1" hexmask.long.word 0x14 0.--15. 1. "COUNTER" line.long 0x18 "FDT_AVB2,Timeout Counter Setting Register for AVB 2" hexmask.long.word 0x18 0.--15. 1. "COUNTER" line.long 0x1C "FDT_AVB3,Timeout Counter Setting Register for AVB 3" hexmask.long.word 0x1C 0.--15. 1. "COUNTER" line.long 0x20 "FDT_AVB4,Timeout Counter Setting Register for AVB 4" hexmask.long.word 0x20 0.--15. 1. "COUNTER" line.long 0x24 "FDT_AVB5,Timeout Counter Setting Register for AVB 5" hexmask.long.word 0x24 0.--15. 1. "COUNTER" line.long 0x28 "FDT_AXSTM2AXSP10,Timeout Counter Setting Register for AXSTM2AXSP 10" hexmask.long.word 0x28 0.--15. 1. "COUNTER" line.long 0x2C "FDT_AXSTM2AXSP11,Timeout Counter Setting Register for AXSTM2AXSP 11" hexmask.long.word 0x2C 0.--15. 1. "COUNTER" line.long 0x30 "FDT_AXSC2AXSP1,Timeout Counter Setting Register for AXSC2AXSP 1" hexmask.long.word 0x30 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFF810700++0xB line.long 0x0 "FDT_AXMM2AXSTM_RS,Timeout Counter Setting Register for AXMM2AXSTM_RS" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_CSDE0M_RS,Timeout Counter Setting Register for CSDE0M_RS" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_CSDE1M_RS,Timeout Counter Setting Register for CSDE1M_RS" hexmask.long.word 0x8 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFE680700++0x1B line.long 0x0 "FDT_AXSN2AXVC,Timeout Counter Setting Register for AXSN2AXVC" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_FBABUSVC,Timeout Counter Setting Register for FBABUSVC" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_FCPCS,Timeout Counter Setting Register for FCPCS" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_FCPRAVC0,Timeout Counter Setting Register for FCPRAVC 0" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_IMR00,Timeout Counter Setting Register for IMR 00" hexmask.long.word 0x10 0.--15. 1. "COUNTER" line.long 0x14 "FDT_IMR01,Timeout Counter Setting Register for IMR 01" hexmask.long.word 0x14 0.--15. 1. "COUNTER" line.long 0x18 "FDT_IMR0COMX,Timeout Counter Setting Register for IMR0COMX" hexmask.long.word 0x18 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFE680724++0x27 line.long 0x0 "FDT_IMR10,Timeout Counter Setting Register for IMR 10" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_IMR11,Timeout Counter Setting Register for IMR 11" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_IMR1COMX,Timeout Counter Setting Register for IMR1COMX" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_IMR20,Timeout Counter Setting Register for IMR 20" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_IMR21,Timeout Counter Setting Register for IMR 21" hexmask.long.word 0x10 0.--15. 1. "COUNTER" line.long 0x14 "FDT_IMR30,Timeout Counter Setting Register for IMR 30" hexmask.long.word 0x14 0.--15. 1. "COUNTER" line.long 0x18 "FDT_IMR31,Timeout Counter Setting Register for IMR 31" hexmask.long.word 0x18 0.--15. 1. "COUNTER" line.long 0x1C "FDT_IMS0,Timeout Counter Setting Register for IMS 0" hexmask.long.word 0x1C 0.--15. 1. "COUNTER" line.long 0x20 "FDT_IMS1,Timeout Counter Setting Register for IMS 1" hexmask.long.word 0x20 0.--15. 1. "COUNTER" line.long 0x24 "FDT_IV1ES,Timeout Counter Setting Register for IV1ES" hexmask.long.word 0x24 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFEBE0700++0xF line.long 0x0 "FDT_FCPVD0,Timeout Counter Setting Register for FCPVD 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_FCPVD1,Timeout Counter Setting Register for FCPVD 1" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_FCPVX2,Timeout Counter Setting Register for FCPVX 2" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_FCPVX3,Timeout Counter Setting Register for FCPVX 3" hexmask.long.word 0xC 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFEBE0740++0xF line.long 0x0 "FDT_FBABUSVIO,Timeout Counter Setting Register for FBABUSVIO" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_DSITXLINK0,Timeout Counter Setting Register for DSITXLINK 0" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_DSITXLINK1,Timeout Counter Setting Register for DSITXLINK 1" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_FCPVX0,Timeout Counter Setting Register for FCPVX 0" hexmask.long.word 0xC 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFEBE0754++0x3 line.long 0x0 "FDT_FCPRAVI1,Timeout Counter Setting Register for FCPRAVI 1" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFEBE075C++0x7 line.long 0x0 "FDT_AXSN2AXVI1,Timeout Counter Setting Register for AXSN2AXVI 1" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_FCPVX1,Timeout Counter Setting Register for FCPVX 1" hexmask.long.word 0x4 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFEBF020C++0x3 line.long 0x0 "FDT_AXVI12AXVI,Timeout Counter Setting Register for AXVI12AXVI" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFEBF0224++0x3 line.long 0x0 "FDT_ISPCOMX,Timeout Counter Setting Register for ISPCOMX" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFEBF0238++0x3 line.long 0x0 "FDT_VINCOMX,Timeout Counter Setting Register for VINCOMX" hexmask.long.word 0x0 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFEBF0710++0x2F line.long 0x0 "FDT_VIN0,Timeout Counter Setting Register for VIN 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_VIN1,Timeout Counter Setting Register for VIN 1" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_VIN2,Timeout Counter Setting Register for VIN 2" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_VIN3,Timeout Counter Setting Register for VIN 3" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_ISP00,Timeout Counter Setting Register for ISP 00" hexmask.long.word 0x10 0.--15. 1. "COUNTER" line.long 0x14 "FDT_ISP01,Timeout Counter Setting Register for ISP 01" hexmask.long.word 0x14 0.--15. 1. "COUNTER" line.long 0x18 "FDT_ISP10,Timeout Counter Setting Register for ISP 10" hexmask.long.word 0x18 0.--15. 1. "COUNTER" line.long 0x1C "FDT_ISP11,Timeout Counter Setting Register for ISP 11" hexmask.long.word 0x1C 0.--15. 1. "COUNTER" line.long 0x20 "FDT_ISP20,Timeout Counter Setting Register for ISP 20" hexmask.long.word 0x20 0.--15. 1. "COUNTER" line.long 0x24 "FDT_ISP21,Timeout Counter Setting Register for ISP 21" hexmask.long.word 0x24 0.--15. 1. "COUNTER" line.long 0x28 "FDT_ISP30,Timeout Counter Setting Register for ISP 30" hexmask.long.word 0x28 0.--15. 1. "COUNTER" line.long 0x2C "FDT_ISP31,Timeout Counter Setting Register for ISP 31" hexmask.long.word 0x2C 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE7B10700++0x13 line.long 0x0 "FDT_AXSC2AXVIP0,Timeout Counter Setting Register for AXSC2AXVIP 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_FBABUSVIP0,Timeout Counter Setting Register for FBABUSVIP 0" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_FCPRAVIP0,Timeout Counter Setting Register for FCPRAVIP 0" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_SMES0,Timeout Counter Setting Register for SMES 0" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_SMPO0,Timeout Counter Setting Register for SMPO 0" hexmask.long.word 0x10 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE7B10718++0x7 line.long 0x0 "FDT_SMPS0,Timeout Counter Setting Register for SMPS 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_UMFL0,Timeout Counter Setting Register for UMFL 0" hexmask.long.word 0x4 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE7B40700++0x13 line.long 0x0 "FDT_AXVIP02AXVIP1,Timeout Counter Setting Register for AXVIP02AXVIP 1" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_CLE0,Timeout Counter Setting Register for CLE 0" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_CLE1,Timeout Counter Setting Register for CLE 1" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_CLE2,Timeout Counter Setting Register for CLE 2" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_CLE3,Timeout Counter Setting Register for CLE 3" hexmask.long.word 0x10 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFE7B40720++0x23 line.long 0x0 "FDT_DISP0,Timeout Counter Setting Register for DISP 0" hexmask.long.word 0x0 0.--15. 1. "COUNTER" line.long 0x4 "FDT_DISP1,Timeout Counter Setting Register for DISP 1" hexmask.long.word 0x4 0.--15. 1. "COUNTER" line.long 0x8 "FDT_FBABUSVIP1,Timeout Counter Setting Register for FBABUSVIP 1" hexmask.long.word 0x8 0.--15. 1. "COUNTER" line.long 0xC "FDT_FCPRAVIP1,Timeout Counter Setting Register for FCPRAVIP 1" hexmask.long.word 0xC 0.--15. 1. "COUNTER" line.long 0x10 "FDT_FCPRAVIP2,Timeout Counter Setting Register for FCPRAVIP 2" hexmask.long.word 0x10 0.--15. 1. "COUNTER" line.long 0x14 "FDT_SMES1,Timeout Counter Setting Register for SMES 1" hexmask.long.word 0x14 0.--15. 1. "COUNTER" line.long 0x18 "FDT_SMPO1,Timeout Counter Setting Register for SMPO 1" hexmask.long.word 0x18 0.--15. 1. "COUNTER" line.long 0x1C "FDT_SMPS1,Timeout Counter Setting Register for SMPS 1" hexmask.long.word 0x1C 0.--15. 1. "COUNTER" line.long 0x20 "FDT_UMFL1,Timeout Counter Setting Register for UMFL 1" hexmask.long.word 0x20 0.--15. 1. "COUNTER" group.long 0xFFFFFFFFFF840040++0x3 line.long 0x0 "FIXSTTOP0,FIX ERROR Status Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF0040++0x7 line.long 0x0 "FIXSTVIO0,FIX ERROR Status Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "FIXSTVIO1,FIX ERROR Status Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE610040++0x7 line.long 0x0 "FIXSTVC0,FIX ERROR Status Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "FIXSTVC1,FIX ERROR Status Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC040++0x3 line.long 0x0 "FIXSTMM0,FIX ERROR Status Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E0040++0x3 line.long 0x0 "FIXSTIR0,FIX ERROR Status Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6200040++0x7 line.long 0x0 "FIXSTRT0,FIX ERROR Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "FIXSTRT1,FIX ERROR Status Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF0040++0x7 line.long 0x0 "FIXSTVIP0,FIX ERROR Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "FIXSTVIP1,FIX ERROR Status Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD840040++0x3 line.long 0x0 "FIXSTU3DG0,FIX ERROR Status Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7730040++0x3 line.long 0x0 "FIXSTPER00,FIX ERROR Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6490040++0x3 line.long 0x0 "FIXSTPER10,FIX ERROR Status Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8400C0++0x7 line.long 0x0 "EDCSTTOP0,EDC Status Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "EDCSTTOP1,EDC Status Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF00C0++0x1B line.long 0x0 "EDCSTVIO0,EDC Status Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "EDCSTVIO1,EDC Status Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "EDCSTVIO2,EDC Status Register for VIO Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "EDCSTVIO3,EDC Status Register for VIO Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" line.long 0x10 "EDCSTVIO4,EDC Status Register for VIO Domain 4" hexmask.long 0x10 0.--31. 1. "STATUS" line.long 0x14 "EDCSTVIO5,EDC Status Register for VIO Domain 5" hexmask.long 0x14 0.--31. 1. "STATUS" line.long 0x18 "EDCSTVIO6,EDC Status Register for VIO Domain 6" hexmask.long 0x18 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE6100C0++0xB line.long 0x0 "EDCSTVC0,EDC Status Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "EDCSTVC1,EDC Status Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "EDCSTVC2,EDC Status Register for VC Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC0C0++0xB line.long 0x0 "EDCSTMM0,EDC Status Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "EDCSTMM1,EDC Status Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "EDCSTMM2,EDC Status Register for MM Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E00C0++0xF line.long 0x0 "EDCSTIR0,EDC Status Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "EDCSTIR1,EDC Status Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "EDCSTIR2,EDC Status Register for IR Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "EDCSTIR3,EDC Status Register for IR Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE62000C0++0x17 line.long 0x0 "EDCSTRT0,EDC Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "EDCSTRT1,EDC Status Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "EDCSTRT2,EDC Status Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "EDCSTRT3,EDC Status Register for RT Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" line.long 0x10 "EDCSTRT4,EDC Status Register for RT Domain 4" hexmask.long 0x10 0.--31. 1. "STATUS" line.long 0x14 "EDCSTRT5,EDC Status Register for RT Domain 5" hexmask.long 0x14 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF00C0++0x13 line.long 0x0 "EDCSTVIP0,EDC Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "EDCSTVIP1,EDC Status Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "EDCSTVIP2,EDC Status Register for VIP Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "EDCSTVIP3,EDC Status Register for VIP Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" line.long 0x10 "EDCSTVIP4,EDC Status Register for VIP Domain 4" hexmask.long 0x10 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD8400C0++0x7 line.long 0x0 "EDCSTU3DG0,EDC Status Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "EDCSTU3DG1,EDC Status Register for U3DG Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE77300C0++0x13 line.long 0x0 "EDCSTPER00,EDC Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "EDCSTPER01,EDC Status Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "EDCSTPER02,EDC Status Register for PER0 Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "EDCSTPER03,EDC Status Register for PER0 Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" line.long 0x10 "EDCSTPER04,EDC Status Register for PER0 Domain 4" hexmask.long 0x10 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE64900C0++0xB line.long 0x0 "EDCSTPER10,EDC Status Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "EDCSTPER11,EDC Status Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "EDCSTPER12,EDC Status Register for PER1 Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF840300++0x3 line.long 0x0 "ICISTPSTTOP,Icistp Status Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF0300++0x3 line.long 0x0 "ICISTPSTVIO,Icistp Status Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE610300++0x3 line.long 0x0 "ICISTPSTVC,Icistp Status Register for VC Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC300++0x3 line.long 0x0 "ICISTPSTMM,Icistp Status Register for MM Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E0300++0x3 line.long 0x0 "ICISTPSTIR,Icistp Status Register for IR Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6200300++0x3 line.long 0x0 "ICISTPSTRT,Icistp Status Register for RT Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF0300++0x3 line.long 0x0 "ICISTPSTVIP,Icistp Status Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD840300++0x3 line.long 0x0 "ICISTPSTU3DG,Icistp Status Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7730300++0x3 line.long 0x0 "ICISTPSTPER0,Icistp Status Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6490300++0x3 line.long 0x0 "ICISTPSTPER1,Icistp Status Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF840200++0x7 line.long 0x0 "DCLSSTTOP0,DCLS Error Status Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "DCLSSTTOP1,DCLS Error Status Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF0200++0x3 line.long 0x0 "DCLSSTVIO0,DCLS Error Status Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE610200++0x3 line.long 0x0 "DCLSSTVC0,DCLS Error Status Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC200++0x7 line.long 0x0 "DCLSSTMM0,DCLS Error Status Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "DCLSSTMM1,DCLS Error Status Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E0200++0x3 line.long 0x0 "DCLSSTIR0,DCLS Error Status Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6200200++0x7 line.long 0x0 "DCLSSTRT0,DCLS Error Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "DCLSSTRT1,DCLS Error Status Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF0200++0x3 line.long 0x0 "DCLSSTVIP0,DCLS Error Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD840200++0x3 line.long 0x0 "DCLSSTU3DG0,DCLS Error Status Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7730200++0x3 line.long 0x0 "DCLSSTPER00,DCLS Error Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6490200++0x3 line.long 0x0 "DCLSSTPER10,DCLS Error Status Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF840100++0x7 line.long 0x0 "LSCHKSTTOP0,LSCHK Status Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "LSCHKSTTOP1,LSCHK Status Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF0100++0xB line.long 0x0 "LSCHKSTVIO0,LSCHK Status Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "LSCHKSTVIO1,LSCHK Status Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "LSCHKSTVIO2,LSCHK Status Register for VIO Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE610100++0x7 line.long 0x0 "LSCHKSTVC0,LSCHK Status Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "LSCHKSTVC1,LSCHK Status Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC100++0x7 line.long 0x0 "LSCHKSTMM0,LSCHK Status Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "LSCHKSTMM1,LSCHK Status Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E0100++0x7 line.long 0x0 "LSCHKSTIR0,LSCHK Status Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "LSCHKSTIR1,LSCHK Status Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6200100++0xB line.long 0x0 "LSCHKSTRT0,LSCHK Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "LSCHKSTRT1,LSCHK Status Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "LSCHKSTRT2,LSCHK Status Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF0100++0x7 line.long 0x0 "LSCHKSTVIP0,LSCHK Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "LSCHKSTVIP1,LSCHK Status Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD840100++0x3 line.long 0x0 "LSCHKSTU3DG0,LSCHK Status Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7730100++0x7 line.long 0x0 "LSCHKSTPER00,LSCHK Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "LSCHKSTPER01,LSCHK Status Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6490100++0x7 line.long 0x0 "LSCHKSTPER10,LSCHK Status Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "LSCHKSTPER11,LSCHK Status Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF840380++0x7 line.long 0x0 "OTHINTSTTOP0,Other Error Status Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "OTHINTSTTOP1,Other Error Status Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF0380++0x3 line.long 0x0 "OTHINTSTVIO0,Other Error Status Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE610380++0x3 line.long 0x0 "OTHINTSTVC0,Other Error Status Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC380++0x3 line.long 0x0 "OTHINTSTMM0,Other Error Status Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E0380++0x3 line.long 0x0 "OTHINTSTIR0,Other Error Status Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6200380++0x3 line.long 0x0 "OTHINTSTRT0,Other Error Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF0380++0x3 line.long 0x0 "OTHINTSTVIP0,Other Error Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD840380++0x3 line.long 0x0 "OTHINTSTU3DG0,Other Error Status Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7730380++0x3 line.long 0x0 "OTHINTSTPER00,Other Error Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6490380++0x3 line.long 0x0 "OTHINTSTPER10,Other Error Status Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF840080++0xB line.long 0x0 "ROUERRSTTOP0,Routing Error Status Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "ROUERRSTTOP1,Routing Error Status Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "ROUERRSTTOP2,Routing Error Status Register for TOP Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF0080++0x1B line.long 0x0 "ROUERRSTVIO0,Routing Error Status Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "ROUERRSTVIO1,Routing Error Status Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "ROUERRSTVIO2,Routing Error Status Register for VIO Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "ROUERRSTVIO3,Routing Error Status Register for VIO Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" line.long 0x10 "ROUERRSTVIO4,Routing Error Status Register for VIO Domain 4" hexmask.long 0x10 0.--31. 1. "STATUS" line.long 0x14 "ROUERRSTVIO5,Routing Error Status Register for VIO Domain 5" hexmask.long 0x14 0.--31. 1. "STATUS" line.long 0x18 "ROUERRSTVIO6,Routing Error Status Register for VIO Domain 6" hexmask.long 0x18 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE610080++0xF line.long 0x0 "ROUERRSTVC0,Routing Error Status Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "ROUERRSTVC1,Routing Error Status Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "ROUERRSTVC2,Routing Error Status Register for VC Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "ROUERRSTVC3,Routing Error Status Register for VC Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC080++0x7 line.long 0x0 "ROUERRSTMM0,Routing Error Status Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "ROUERRSTMM1,Routing Error Status Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E0080++0xF line.long 0x0 "ROUERRSTIR0,Routing Error Status Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "ROUERRSTIR1,Routing Error Status Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "ROUERRSTIR2,Routing Error Status Register for IR Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "ROUERRSTIR3,Routing Error Status Register for IR Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6200080++0x1B line.long 0x0 "ROUERRSTRT0,Routing Error Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "ROUERRSTRT1,Routing Error Status Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "ROUERRSTRT2,Routing Error Status Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "ROUERRSTRT3,Routing Error Status Register for RT Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" line.long 0x10 "ROUERRSTRT4,Routing Error Status Register for RT Domain 4" hexmask.long 0x10 0.--31. 1. "STATUS" line.long 0x14 "ROUERRSTRT5,Routing Error Status Register for RT Domain 5" hexmask.long 0x14 0.--31. 1. "STATUS" line.long 0x18 "ROUERRSTRT6,Routing Error Status Register for RT Domain 6" hexmask.long 0x18 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF0080++0x17 line.long 0x0 "ROUERRSTVIP0,Routing Error Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "ROUERRSTVIP1,Routing Error Status Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "ROUERRSTVIP2,Routing Error Status Register for VIP Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "ROUERRSTVIP3,Routing Error Status Register for VIP Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" line.long 0x10 "ROUERRSTVIP4,Routing Error Status Register for VIP Domain 4" hexmask.long 0x10 0.--31. 1. "STATUS" line.long 0x14 "ROUERRSTVIP5,Routing Error Status Register for VIP Domain 5" hexmask.long 0x14 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD840080++0x7 line.long 0x0 "ROUERRSTU3DG0,Routing Error Status Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "ROUERRSTU3DG1,Routing Error Status Register for U3DG Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7730080++0x13 line.long 0x0 "ROUERRSTPER00,Routing Error Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "ROUERRSTPER01,Routing Error Status Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "ROUERRSTPER02,Routing Error Status Register for PER0 Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "ROUERRSTPER03,Routing Error Status Register for PER0 Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" line.long 0x10 "ROUERRSTPER04,Routing Error Status Register for PER0 Domain 4" hexmask.long 0x10 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6490080++0xF line.long 0x0 "ROUERRSTPER10,Routing Error Status Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "ROUERRSTPER11,Routing Error Status Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "ROUERRSTPER12,Routing Error Status Register for PER1 Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" line.long 0xC "ROUERRSTPER13,Routing Error Status Register for PER1 Domain 3" hexmask.long 0xC 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF840500++0xB line.long 0x0 "RSCHKSTTOP0,RSCHK Status Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "RSCHKSTTOP1,RSCHK Status Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "RSCHKSTTOP2,RSCHK Status Register for TOP Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF0500++0x7 line.long 0x0 "RSCHKSTVIO0,RSCHK Status Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "RSCHKSTVIO1,RSCHK Status Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE610500++0x7 line.long 0x0 "RSCHKSTVC0,RSCHK Status Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "RSCHKSTVC1,RSCHK Status Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC500++0x3 line.long 0x0 "RSCHKSTMM0,RSCHK Status Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E0500++0x7 line.long 0x0 "RSCHKSTIR0,RSCHK Status Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "RSCHKSTIR1,RSCHK Status Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6200500++0xB line.long 0x0 "RSCHKSTRT0,RSCHK Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "RSCHKSTRT1,RSCHK Status Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "RSCHKSTRT2,RSCHK Status Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF0500++0xB line.long 0x0 "RSCHKSTVIP0,RSCHK Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "RSCHKSTVIP1,RSCHK Status Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "RSCHKSTVIP2,RSCHK Status Register for VIP Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD840500++0x3 line.long 0x0 "RSCHKSTU3DG0,RSCHK Status Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7730500++0xB line.long 0x0 "RSCHKSTPER00,RSCHK Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "RSCHKSTPER01,RSCHK Status Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "RSCHKSTPER02,RSCHK Status Register for PER0 Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6490500++0x7 line.long 0x0 "RSCHKSTPER10,RSCHK Status Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "RSCHKSTPER11,RSCHK Status Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8401C0++0x3 line.long 0x0 "TIDINTSTTOP0,TID Error Status Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF01C0++0x7 line.long 0x0 "TIDINTSTVIO0,TID Error Status Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "TIDINTSTVIO1,TID Error Status Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE6101C0++0x7 line.long 0x0 "TIDINTSTVC0,TID Error Status Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "TIDINTSTVC1,TID Error Status Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC1C0++0x3 line.long 0x0 "TIDINTSTMM0,TID Error Status Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E01C0++0x3 line.long 0x0 "TIDINTSTIR0,TID Error Status Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE62001C0++0x7 line.long 0x0 "TIDINTSTRT0,TID Error Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "TIDINTSTRT1,TID Error Status Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF01C0++0x7 line.long 0x0 "TIDINTSTVIP0,TID Error Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "TIDINTSTVIP1,TID Error Status Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD8401C0++0x3 line.long 0x0 "TIDINTSTU3DG0,TID Error Status Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE77301C0++0x3 line.long 0x0 "TIDINTSTPER00,TID Error Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE64901C0++0x7 line.long 0x0 "TIDINTSTPER10,TID Error Status Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "TIDINTSTPER11,TID Error Status Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8402C0++0x3 line.long 0x0 "SAFERRSTTOP,Safety Access Error Status Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF02C0++0x3 line.long 0x0 "SAFERRSTVIO,Safety Access Error Status Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE6102C0++0x3 line.long 0x0 "SAFERRSTVC,Safety Access Error Status Register for VC Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC2C0++0x3 line.long 0x0 "SAFERRSTMM,Safety Access Error Status Register for MM Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E02C0++0x3 line.long 0x0 "SAFERRSTIR,Safety Access Error Status Register for IR Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE62002C0++0x3 line.long 0x0 "SAFERRSTRT,Safety Access Error Status Register for RT Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF02C0++0x3 line.long 0x0 "SAFERRSTVIP,Safety Access Error Status Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD8402C0++0x3 line.long 0x0 "SAFERRSTU3DG,Safety Access Error Status Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE77302C0++0x3 line.long 0x0 "SAFERRSTPER0,Safety Access Error Status Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE64902C0++0x3 line.long 0x0 "SAFERRSTPER1,Safety Access Error Status Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF840600++0x3 line.long 0x0 "SECERRINTENTOP,Security Access Error Status Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF0600++0x3 line.long 0x0 "SECERRINTENVIO,Security Access Error Status Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE610600++0x3 line.long 0x0 "SECERRINTENVC,Security Access Error Status Register for VC Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC600++0x3 line.long 0x0 "SECERRINTENMM,Security Access Error Status Register for MM Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E0600++0x3 line.long 0x0 "SECERRINTENIR,Security Access Error Status Register for IR Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6200600++0x3 line.long 0x0 "SECERRINTENRT,Security Access Error Status Register for RT Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF0600++0x3 line.long 0x0 "SECERRINTENVIP,Security Access Error Status Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD840600++0x3 line.long 0x0 "SECERRINTENU3DG,Security Access Error Status Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7730600++0x3 line.long 0x0 "SECERRINTENPER0,Security Access Error Status Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6490600++0x3 line.long 0x0 "SECERRINTENPER1,Security Access Error Status Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF840140++0x7 line.long 0x0 "WCRCERRSTTOP0,Write Read Check Status Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "WCRCERRSTTOP1,Write Read Check Status Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF0140++0x7 line.long 0x0 "WCRCERRSTVIO0,Write Read Check Status Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "WCRCERRSTVIO1,Write Read Check Status Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE610140++0x3 line.long 0x0 "WCRCERRSTVC0,Write Read Check Status Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC140++0x3 line.long 0x0 "WCRCERRSTMM0,Write Read Check Status Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E0140++0x7 line.long 0x0 "WCRCERRSTIR0,Write Read Check Status Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "WCRCERRSTIR1,Write Read Check Status Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6200140++0xB line.long 0x0 "WCRCERRSTRT0,Write Read Check Status Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "WCRCERRSTRT1,Write Read Check Status Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" line.long 0x8 "WCRCERRSTRT2,Write Read Check Status Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF0140++0x7 line.long 0x0 "WCRCERRSTVIP0,Write Read Check Status Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "WCRCERRSTVIP1,Write Read Check Status Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD840140++0x3 line.long 0x0 "WCRCERRSTU3DG0,Write Read Check Status Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7730140++0x7 line.long 0x0 "WCRCERRSTPER00,Write Read Check Status Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" line.long 0x4 "WCRCERRSTPER01,Write Read Check Status Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6490140++0x3 line.long 0x0 "WCRCERRSTPER10,Write Read Check Status Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF840340++0x3 line.long 0x0 "FCPRSTTOP,FCPR Error Status Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFEAF0340++0x3 line.long 0x0 "FCPRSTVIO,FCPR Error Status Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFE610340++0x3 line.long 0x0 "FCPRSTVC,FCPR Error Status Register for VC Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE67FC340++0x3 line.long 0x0 "FCPRSTMM,FCPR Error Status Register for MM Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFF8E0340++0x3 line.long 0x0 "FCPRSTIR,FCPR Error Status Register for IR Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6200340++0x3 line.long 0x0 "FCPRSTRT,FCPR Error Status Register for RT Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7AF0340++0x3 line.long 0x0 "FCPRSTVIP,FCPR Error Status Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFFD840340++0x3 line.long 0x0 "FCPRSTU3DG,FCPR Error Status Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE7730340++0x3 line.long 0x0 "FCPRSTPER0,FCPR Error Status Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "STATUS" group.long 0xFFFFFFFFE6490340++0x3 line.long 0x0 "FCPRSTPER1,FCPR Error Status Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "STATUS" wgroup.long 0xFFFFFFFFFF8403C0++0x3 line.long 0x0 "FIXINTENTOP0,FIX ERROR INTEN Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF03C0++0x7 line.long 0x0 "FIXINTENVIO0,FIX ERROR INTEN Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "FIXINTENVIO1,FIX ERROR INTEN Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE6103C0++0x7 line.long 0x0 "FIXINTENVC0,FIX ERROR INTEN Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "FIXINTENVC1,FIX ERROR INTEN Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC3C0++0x3 line.long 0x0 "FIXINTENMM0,FIX ERROR INTEN Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E03C0++0x3 line.long 0x0 "FIXINTENIR0,FIX ERROR INTEN Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE62003C0++0x7 line.long 0x0 "FIXINTENRT0,FIX ERROR INTEN Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "FIXINTENRT1,FIX ERROR INTEN Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF03C0++0x7 line.long 0x0 "FIXINTENVIP0,FIX ERROR INTEN Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "FIXINTENVIP1,FIX ERROR INTEN Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD8403C0++0x3 line.long 0x0 "FIXINTENU3DG0,FIX ERROR INTEN Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE77303C0++0x3 line.long 0x0 "FIXINTENPER00,FIX ERROR INTEN Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE64903C0++0x7 line.long 0x0 "FIXINTENPER10,FIX ERROR INTEN Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "FIXINTENPER11,FIX ERROR INTEN Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF840440++0x7 line.long 0x0 "EDCINTENTOP0,EDC INTEN Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "EDCINTENTOP1,EDC INTEN Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF0440++0x1B line.long 0x0 "EDCINTENVIO0,EDC INTEN Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "EDCINTENVIO1,EDC INTEN Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "EDCINTENVIO2,EDC INTEN Register for VIO Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "EDCINTENVIO3,EDC INTEN Register for VIO Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" line.long 0x10 "EDCINTENVIO4,EDC INTEN Register for VIO Domain 4" hexmask.long 0x10 0.--31. 1. "INTEN" line.long 0x14 "EDCINTENVIO5,EDC INTEN Register for VIO Domain 5" hexmask.long 0x14 0.--31. 1. "INTEN" line.long 0x18 "EDCINTENVIO6,EDC INTEN Register for VIO Domain 6" hexmask.long 0x18 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE610440++0xB line.long 0x0 "EDCINTENVC0,EDC INTEN Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "EDCINTENVC1,EDC INTEN Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "EDCINTENVC2,EDC INTEN Register for VC Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC440++0xB line.long 0x0 "EDCINTENMM0,EDC INTEN Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "EDCINTENMM1,EDC INTEN Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "EDCINTENMM2,EDC INTEN Register for MM Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E0440++0xF line.long 0x0 "EDCINTENIR0,EDC INTEN Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "EDCINTENIR1,EDC INTEN Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "EDCINTENIR2,EDC INTEN Register for IR Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "EDCINTENIR3,EDC INTEN Register for IR Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6200440++0x17 line.long 0x0 "EDCINTENRT0,EDC INTEN Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "EDCINTENRT1,EDC INTEN Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "EDCINTENRT2,EDC INTEN Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "EDCINTENRT3,EDC INTEN Register for RT Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" line.long 0x10 "EDCINTENRT4,EDC INTEN Register for RT Domain 4" hexmask.long 0x10 0.--31. 1. "INTEN" line.long 0x14 "EDCINTENRT5,EDC INTEN Register for RT Domain 5" hexmask.long 0x14 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF0440++0x13 line.long 0x0 "EDCINTENVIP0,EDC INTEN Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "EDCINTENVIP1,EDC INTEN Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "EDCINTENVIP2,EDC INTEN Register for VIP Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "EDCINTENVIP3,EDC INTEN Register for VIP Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" line.long 0x10 "EDCINTENVIP4,EDC INTEN Register for VIP Domain 4" hexmask.long 0x10 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD840440++0x7 line.long 0x0 "EDCINTENU3DG0,EDC INTEN Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "EDCINTENU3DG1,EDC INTEN Register for U3DG Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7730440++0x13 line.long 0x0 "EDCINTENPER00,EDC INTEN Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "EDCINTENPER01,EDC INTEN Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "EDCINTENPER02,EDC INTEN Register for PER0 Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "EDCINTENPER03,EDC INTEN Register for PER0 Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" line.long 0x10 "EDCINTENPER04,EDC INTEN Register for PER0 Domain 4" hexmask.long 0x10 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6490440++0xB line.long 0x0 "EDCINTENPER10,EDC INTEN Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "EDCINTENPER11,EDC INTEN Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "EDCINTENPER12,EDC INTEN Register for PER1 Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF840680++0x3 line.long 0x0 "ICISTPINTENTOP,Icistp INTEN Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF0680++0x3 line.long 0x0 "ICISTPINTENVIO,Icistp INTEN Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE610680++0x3 line.long 0x0 "ICISTPINTENVC,Icistp INTEN Register for VC Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC680++0x3 line.long 0x0 "ICISTPINTENMM,Icistp INTEN Register for MM Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E0680++0x3 line.long 0x0 "ICISTPINTENIR,Icistp INTEN Register for IR Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6200680++0x3 line.long 0x0 "ICISTPINTENRT,Icistp INTEN Register for RT Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF0680++0x3 line.long 0x0 "ICISTPINTENVIP,Icistp INTEN Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD840680++0x3 line.long 0x0 "ICISTPINTENU3DG,Icistp INTEN Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7730680++0x3 line.long 0x0 "ICISTPINTENPER0,Icistp INTEN Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6490680++0x3 line.long 0x0 "ICISTPINTENPER1,Icistp INTEN Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF840580++0x7 line.long 0x0 "DCLSINTENTOP0,DCLS Error INTEN Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "DCLSINTENTOP1,DCLS Error INTEN Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF0580++0x3 line.long 0x0 "DCLSINTENVIO0,DCLS Error INTEN Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE610580++0x3 line.long 0x0 "DCLSINTENVC0,DCLS Error INTEN Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC580++0x7 line.long 0x0 "DCLSINTENMM0,DCLS Error INTEN Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "DCLSINTENMM1,DCLS Error INTEN Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E0580++0x3 line.long 0x0 "DCLSINTENIR0,DCLS Error INTEN Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6200580++0x7 line.long 0x0 "DCLSINTENRT0,DCLS Error INTEN Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "DCLSINTENRT1,DCLS Error INTEN Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF0580++0x3 line.long 0x0 "DCLSINTENVIP0,DCLS Error INTEN Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD840580++0x3 line.long 0x0 "DCLSINTENU3DG0,DCLS Error INTEN Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7730580++0x3 line.long 0x0 "DCLSINTENPER00,DCLS Error INTEN Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6490580++0x3 line.long 0x0 "DCLSINTENPER10,DCLS Error INTEN Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF840480++0x7 line.long 0x0 "LSCHKINTENTOP0,LSCHK INTEN Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "LSCHKINTENTOP1,LSCHK INTEN Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF0480++0xB line.long 0x0 "LSCHKINTENVIO0,LSCHK INTEN Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "LSCHKINTENVIO1,LSCHK INTEN Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "LSCHKINTENVIO2,LSCHK INTEN Register for VIO Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE610480++0x7 line.long 0x0 "LSCHKINTENVC0,LSCHK INTEN Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "LSCHKINTENVC1,LSCHK INTEN Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC480++0x7 line.long 0x0 "LSCHKINTENMM0,LSCHK INTEN Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "LSCHKINTENMM1,LSCHK INTEN Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E0480++0x7 line.long 0x0 "LSCHKINTENIR0,LSCHK INTEN Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "LSCHKINTENIR1,LSCHK INTEN Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6200480++0xB line.long 0x0 "LSCHKINTENRT0,LSCHK INTEN Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "LSCHKINTENRT1,LSCHK INTEN Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "LSCHKINTENRT2,LSCHK INTEN Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF0480++0x7 line.long 0x0 "LSCHKINTENVIP0,LSCHK INTEN Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "LSCHKINTENVIP1,LSCHK INTEN Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD840480++0x3 line.long 0x0 "LSCHKINTENU3DG0,LSCHK INTEN Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7730480++0x7 line.long 0x0 "LSCHKINTENPER00,LSCHK INTEN Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "LSCHKINTENPER01,LSCHK INTEN Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6490480++0x7 line.long 0x0 "LSCHKINTENPER10,LSCHK INTEN Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "LSCHKINTENPER11,LSCHK INTEN Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF840700++0x7 line.long 0x0 "OTHINTENTOP0,Other Error INTEN Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "OTHINTENTOP1,Other Error INTEN Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF0700++0x3 line.long 0x0 "OTHINTENVIO0,Other Error INTEN Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE610700++0x3 line.long 0x0 "OTHINTENVC0,Other Error INTEN Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC700++0x3 line.long 0x0 "OTHINTENMM0,Other Error INTEN Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E0700++0x3 line.long 0x0 "OTHINTENIR0,Other Error INTEN Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6200700++0x3 line.long 0x0 "OTHINTENRT0,Other Error INTEN Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF0700++0x3 line.long 0x0 "OTHINTENVIP0,Other Error INTEN Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD840700++0x3 line.long 0x0 "OTHINTENU3DG0,Other Error INTEN Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7730700++0x3 line.long 0x0 "OTHINTENPER00,Other Error INTEN Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6490700++0x3 line.long 0x0 "OTHINTENPER10,Other Error INTEN Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF840400++0xB line.long 0x0 "RERRINTENTOP0,Routing Error INTEN Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RERRINTENTOP1,Routing Error INTEN Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RERRINTENTOP2,Routing Error INTEN Register for TOP Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF0400++0x1B line.long 0x0 "RERRINTENVIO0,Routing Error INTEN Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RERRINTENVIO1,Routing Error INTEN Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RERRINTENVIO2,Routing Error INTEN Register for VIO Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "RERRINTENVIO3,Routing Error INTEN Register for VIO Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" line.long 0x10 "RERRINTENVIO4,Routing Error INTEN Register for VIO Domain 4" hexmask.long 0x10 0.--31. 1. "INTEN" line.long 0x14 "RERRINTENVIO5,Routing Error INTEN Register for VIO Domain 5" hexmask.long 0x14 0.--31. 1. "INTEN" line.long 0x18 "RERRINTENVIO6,Routing Error INTEN Register for VIO Domain 6" hexmask.long 0x18 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE610400++0xF line.long 0x0 "RERRINTENVC0,Routing Error INTEN Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RERRINTENVC1,Routing Error INTEN Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RERRINTENVC2,Routing Error INTEN Register for VC Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "RERRINTENVC3,Routing Error INTEN Register for VC Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC400++0x7 line.long 0x0 "RERRINTENMM0,Routing Error INTEN Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RERRINTENMM1,Routing Error INTEN Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E0400++0xF line.long 0x0 "RERRINTENIR0,Routing Error INTEN Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RERRINTENIR1,Routing Error INTEN Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RERRINTENIR2,Routing Error INTEN Register for IR Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "RERRINTENIR3,Routing Error INTEN Register for IR Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6200400++0x1B line.long 0x0 "RERRINTENRT0,Routing Error INTEN Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RERRINTENRT1,Routing Error INTEN Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RERRINTENRT2,Routing Error INTEN Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "RERRINTENRT3,Routing Error INTEN Register for RT Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" line.long 0x10 "RERRINTENRT4,Routing Error INTEN Register for RT Domain 4" hexmask.long 0x10 0.--31. 1. "INTEN" line.long 0x14 "RERRINTENRT5,Routing Error INTEN Register for RT Domain 5" hexmask.long 0x14 0.--31. 1. "INTEN" line.long 0x18 "RERRINTENRT6,Routing Error INTEN Register for RT Domain 6" hexmask.long 0x18 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF0400++0x17 line.long 0x0 "RERRINTENVIP0,Routing Error INTEN Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RERRINTENVIP1,Routing Error INTEN Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RERRINTENVIP2,Routing Error INTEN Register for VIP Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "RERRINTENVIP3,Routing Error INTEN Register for VIP Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" line.long 0x10 "RERRINTENVIP4,Routing Error INTEN Register for VIP Domain 4" hexmask.long 0x10 0.--31. 1. "INTEN" line.long 0x14 "RERRINTENVIP5,Routing Error INTEN Register for VIP Domain 5" hexmask.long 0x14 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD840400++0x7 line.long 0x0 "RERRINTENU3DG0,Routing Error INTEN Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RERRINTENU3DG1,Routing Error INTEN Register for U3DG Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7730400++0x13 line.long 0x0 "RERRINTENPER00,Routing Error INTEN Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RERRINTENPER01,Routing Error INTEN Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RERRINTENPER02,Routing Error INTEN Register for PER0 Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "RERRINTENPER03,Routing Error INTEN Register for PER0 Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" line.long 0x10 "RERRINTENPER04,Routing Error INTEN Register for PER0 Domain 4" hexmask.long 0x10 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6490400++0xF line.long 0x0 "RERRINTENPER10,Routing Error INTEN Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RERRINTENPER11,Routing Error INTEN Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RERRINTENPER12,Routing Error INTEN Register for PER1 Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" line.long 0xC "RERRINTENPER13,Routing Error INTEN Register for PER1 Domain 3" hexmask.long 0xC 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF840500++0xB line.long 0x0 "RSCHKINTENTOP0,RSCHK INTEN Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RSCHKINTENTOP1,RSCHK INTEN Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RSCHKINTENTOP2,RSCHK INTEN Register for TOP Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF0500++0x7 line.long 0x0 "RSCHKINTENVIO0,RSCHK INTEN Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RSCHKINTENVIO1,RSCHK INTEN Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE610500++0x7 line.long 0x0 "RSCHKINTENVC0,RSCHK INTEN Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RSCHKINTENVC1,RSCHK INTEN Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC500++0x3 line.long 0x0 "RSCHKINTENMM0,RSCHK INTEN Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E0500++0x7 line.long 0x0 "RSCHKINTENIR0,RSCHK INTEN Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RSCHKINTENIR1,RSCHK INTEN Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6200500++0xB line.long 0x0 "RSCHKINTENRT0,RSCHK INTEN Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RSCHKINTENRT1,RSCHK INTEN Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RSCHKINTENRT2,RSCHK INTEN Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF0500++0xB line.long 0x0 "RSCHKINTENVIP0,RSCHK INTEN Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RSCHKINTENVIP1,RSCHK INTEN Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RSCHKINTENVIP2,RSCHK INTEN Register for VIP Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD840500++0x3 line.long 0x0 "RSCHKINTENU3DG0,RSCHK INTEN Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7730500++0xB line.long 0x0 "RSCHKINTENPER00,RSCHK INTEN Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RSCHKINTENPER01,RSCHK INTEN Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "RSCHKINTENPER02,RSCHK INTEN Register for PER0 Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6490500++0x7 line.long 0x0 "RSCHKINTENPER10,RSCHK INTEN Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "RSCHKINTENPER11,RSCHK INTEN Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF840540++0x3 line.long 0x0 "TIDINTENTOP0,TID Error INTEN Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF0540++0x7 line.long 0x0 "TIDINTENVIO0,TID Error INTEN Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "TIDINTENVIO1,TID Error INTEN Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE610540++0x7 line.long 0x0 "TIDINTENVC0,TID Error INTEN Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "TIDINTENVC1,TID Error INTEN Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC540++0x3 line.long 0x0 "TIDINTENMM0,TID Error INTEN Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E0540++0x3 line.long 0x0 "TIDINTENIR0,TID Error INTEN Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6200540++0x7 line.long 0x0 "TIDINTENRT0,TID Error INTEN Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "TIDINTENRT1,TID Error INTEN Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF0540++0x7 line.long 0x0 "TIDINTENVIP0,TID Error INTEN Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "TIDINTENVIP1,TID Error INTEN Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD840540++0x3 line.long 0x0 "TIDINTENU3DG0,TID Error INTEN Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7730540++0x3 line.long 0x0 "TIDINTENPER00,TID Error INTEN Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6490540++0x7 line.long 0x0 "TIDINTENPER10,TID Error INTEN Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "TIDINTENPER11,TID Error INTEN Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF840640++0x3 line.long 0x0 "SAFERRINTENTOP,Safety Access Error INTEN Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF0640++0x3 line.long 0x0 "SAFERRINTENVIO,Safety Access Error INTEN Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE610640++0x3 line.long 0x0 "SAFERRINTENVC,Safety Access Error INTEN Register for VC Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC640++0x3 line.long 0x0 "SAFERRINTENMM,Safety Access Error INTEN Register for MM Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E0640++0x3 line.long 0x0 "SAFERRINTENIR,Safety Access Error INTEN Register for IR Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6200640++0x3 line.long 0x0 "SAFERRINTENRT,Safety Access Error INTEN Register for RT Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF0640++0x3 line.long 0x0 "SAFERRINTENVIP,Safety Access Error INTEN Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD840640++0x3 line.long 0x0 "SAFERRINTENU3DG,Safety Access Error INTEN Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7730640++0x3 line.long 0x0 "SAFERRINTENPER0,Safety Access Error INTEN Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6490640++0x3 line.long 0x0 "SAFERRINTENPER1,Safety Access Error INTEN Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF840600++0x3 line.long 0x0 "SECERRINTENTOP,Security Access Error INTEN Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF0600++0x3 line.long 0x0 "SECERRINTENVIO,Security Access Error INTEN Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE610600++0x3 line.long 0x0 "SECERRINTENVC,Security Access Error INTEN Register for VC Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC600++0x3 line.long 0x0 "SECERRINTENMM,Security Access Error INTEN Register for MM Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E0600++0x3 line.long 0x0 "SECERRINTENIR,Security Access Error INTEN Register for IR Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6200600++0x3 line.long 0x0 "SECERRINTENRT,Security Access Error INTEN Register for RT Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF0600++0x3 line.long 0x0 "SECERRINTENVIP,Security Access Error INTEN Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD840600++0x3 line.long 0x0 "SECERRINTENU3DG,Security Access Error INTEN Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7730600++0x3 line.long 0x0 "SECERRINTENPER0,Security Access Error INTEN Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE6490600++0x3 line.long 0x0 "SECERRINTENPER1,Security Access Error INTEN Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8404C0++0x7 line.long 0x0 "WCRCINTENTOP0,Write Read Check INTEN Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "WCRCINTENTOP1,Write Read Check INTEN Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF04C0++0x7 line.long 0x0 "WCRCINTENVIO0,Write Read Check INTEN Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "WCRCINTENVIO1,Write Read Check INTEN Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE6104C0++0x3 line.long 0x0 "WCRCINTENVC0,Write Read Check INTEN Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC4C0++0x3 line.long 0x0 "WCRCINTENMM0,Write Read Check INTEN Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E04C0++0x7 line.long 0x0 "WCRCINTENIR0,Write Read Check INTEN Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "WCRCINTENIR1,Write Read Check INTEN Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE62004C0++0xB line.long 0x0 "WCRCINTENRT0,Write Read Check INTEN Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "WCRCINTENRT1,Write Read Check INTEN Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" line.long 0x8 "WCRCINTENRT2,Write Read Check INTEN Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF04C0++0x7 line.long 0x0 "WCRCINTENVIP0,Write Read Check INTEN Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "WCRCINTENVIP1,Write Read Check INTEN Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD8404C0++0x3 line.long 0x0 "WCRCINTENU3DG0,Write Read Check INTEN Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE77304C0++0x7 line.long 0x0 "WCRCINTENPER00,Write Read Check INTEN Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" line.long 0x4 "WCRCINTENPER01,Write Read Check INTEN Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE64904C0++0x3 line.long 0x0 "WCRCINTENPER10,Write Read Check INTEN Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8406C0++0x3 line.long 0x0 "FCPRINTENTOP,FCPR Error INTEN Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFEAF06C0++0x3 line.long 0x0 "FCPRINTENVIO,FCPR Error INTEN Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFE6106C0++0x3 line.long 0x0 "FCPRINTENVC,FCPR Error INTEN Register for VC Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE67FC6C0++0x3 line.long 0x0 "FCPRINTENMM,FCPR Error INTEN Register for MM Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFF8E06C0++0x3 line.long 0x0 "FCPRINTENIR,FCPR Error INTEN Register for IR Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE62006C0++0x3 line.long 0x0 "FCPRINTENRT,FCPR Error INTEN Register for RT Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE7AF06C0++0x3 line.long 0x0 "FCPRINTENVIP,FCPR Error INTEN Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFFD8406C0++0x3 line.long 0x0 "FCPRINTENU3DG,FCPR Error INTEN Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE77306C0++0x3 line.long 0x0 "FCPRINTENPER0,FCPR Error INTEN Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "INTEN" wgroup.long 0xFFFFFFFFE64906C0++0x3 line.long 0x0 "FCPRINTENPER1,FCPR Error INTEN Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "INTEN" group.long 0xFFFFFFFFFF840740++0x3 line.long 0x0 "FIXDUMMYTOP0,FIX ERROR Dummy Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF0740++0x7 line.long 0x0 "FIXDUMMYVIO0,FIX ERROR Dummy Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "FIXDUMMYVIO1,FIX ERROR Dummy Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE610740++0x7 line.long 0x0 "FIXDUMMYVC0,FIX ERROR Dummy Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "FIXDUMMYVC1,FIX ERROR Dummy Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FC740++0x3 line.long 0x0 "FIXDUMMYMM0,FIX ERROR Dummy Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E0740++0x3 line.long 0x0 "FIXDUMMYIR0,FIX ERROR Dummy Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6200740++0x7 line.long 0x0 "FIXDUMMYRT0,FIX ERROR Dummy Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "FIXDUMMYRT1,FIX ERROR Dummy Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF0740++0x7 line.long 0x0 "FIXDUMMYVIP0,FIX ERROR Dummy Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "FIXDUMMYVIP1,FIX ERROR Dummy Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD840740++0x3 line.long 0x0 "FIXDUMMYU3DG0,FIX ERROR Dummy Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7730740++0x3 line.long 0x0 "FIXDUMMYPER00,FIX ERROR Dummy Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6490740++0x3 line.long 0x0 "FIXDUMMYPER10,FIX ERROR Dummy Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8407C0++0x7 line.long 0x0 "EDCDUMMYTOP0,EDC Dummy Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "EDCDUMMYTOP1,EDC Dummy Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF07C0++0x1B line.long 0x0 "EDCDUMMYVIO0,EDC Dummy Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "EDCDUMMYVIO1,EDC Dummy Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "EDCDUMMYVIO2,EDC Dummy Register for VIO Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "EDCDUMMYVIO3,EDC Dummy Register for VIO Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" line.long 0x10 "EDCDUMMYVIO4,EDC Dummy Register for VIO Domain 4" hexmask.long 0x10 0.--31. 1. "DUMMY" line.long 0x14 "EDCDUMMYVIO5,EDC Dummy Register for VIO Domain 5" hexmask.long 0x14 0.--31. 1. "DUMMY" line.long 0x18 "EDCDUMMYVIO6,EDC Dummy Register for VIO Domain 6" hexmask.long 0x18 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE6107C0++0xB line.long 0x0 "EDCDUMMYVC0,EDC Dummy Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "EDCDUMMYVC1,EDC Dummy Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "EDCDUMMYVC2,EDC Dummy Register for VC Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FC7C0++0xB line.long 0x0 "EDCDUMMYMM0,EDC Dummy Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "EDCDUMMYMM1,EDC Dummy Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "EDCDUMMYMM2,EDC Dummy Register for MM Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E07C0++0xF line.long 0x0 "EDCDUMMYIR0,EDC Dummy Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "EDCDUMMYIR1,EDC Dummy Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "EDCDUMMYIR2,EDC Dummy Register for IR Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "EDCDUMMYIR3,EDC Dummy Register for IR Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE62007C0++0x17 line.long 0x0 "EDCDUMMYRT0,EDC Dummy Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "EDCDUMMYRT1,EDC Dummy Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "EDCDUMMYRT2,EDC Dummy Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "EDCDUMMYRT3,EDC Dummy Register for RT Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" line.long 0x10 "EDCDUMMYRT4,EDC Dummy Register for RT Domain 4" hexmask.long 0x10 0.--31. 1. "DUMMY" line.long 0x14 "EDCDUMMYRT5,EDC Dummy Register for RT Domain 5" hexmask.long 0x14 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF07C0++0x13 line.long 0x0 "EDCDUMMYVIP0,EDC Dummy Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "EDCDUMMYVIP1,EDC Dummy Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "EDCDUMMYVIP2,EDC Dummy Register for VIP Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "EDCDUMMYVIP3,EDC Dummy Register for VIP Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" line.long 0x10 "EDCDUMMYVIP4,EDC Dummy Register for VIP Domain 4" hexmask.long 0x10 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD8407C0++0x7 line.long 0x0 "EDCDUMMYU3DG0,EDC Dummy Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "EDCDUMMYU3DG1,EDC Dummy Register for U3DG Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE77307C0++0x13 line.long 0x0 "EDCDUMMYPER00,EDC Dummy Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "EDCDUMMYPER01,EDC Dummy Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "EDCDUMMYPER02,EDC Dummy Register for PER0 Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "EDCDUMMYPER03,EDC Dummy Register for PER0 Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" line.long 0x10 "EDCDUMMYPER04,EDC Dummy Register for PER0 Domain 4" hexmask.long 0x10 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE64907C0++0xB line.long 0x0 "EDCDUMMYPER10,EDC Dummy Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "EDCDUMMYPER11,EDC Dummy Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "EDCDUMMYPER12,EDC Dummy Register for PER1 Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF840A00++0x3 line.long 0x0 "ICISTPDUMMYTOP,Icistp Dummy Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF0A00++0x3 line.long 0x0 "ICISTPDUMMYVIO,Icistp Dummy Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE610A00++0x3 line.long 0x0 "ICISTPDUMMYVC,Icistp Dummy Register for VC Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FCA00++0x3 line.long 0x0 "ICISTPDUMMYMM,Icistp Dummy Register for MM Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E0A00++0x3 line.long 0x0 "ICISTPDUMMYIR,Icistp Dummy Register for IR Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6200A00++0x3 line.long 0x0 "ICISTPDUMMYRT,Icistp Dummy Register for RT Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF0A00++0x3 line.long 0x0 "ICISTPDUMMYVIP,Icistp Dummy Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD840A00++0x3 line.long 0x0 "ICISTPDUMMYU3DG,Icistp Dummy Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7730A00++0x3 line.long 0x0 "ICISTPDUMMYPER0,Icistp Dummy Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6490A00++0x3 line.long 0x0 "ICISTPDUMMYPER1,Icistp Dummy Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF840900++0x7 line.long 0x0 "DCLSDUMMYTOP0,DCLS Error Dummy Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "DCLSDUMMYTOP1,DCLS Error Dummy Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF0900++0x3 line.long 0x0 "DCLSDUMMYVIO0,DCLS Error Dummy Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE610900++0x3 line.long 0x0 "DCLSDUMMYVC0,DCLS Error Dummy Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FC900++0x7 line.long 0x0 "DCLSDUMMYMM0,DCLS Error Dummy Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "DCLSDUMMYMM1,DCLS Error Dummy Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E0900++0x3 line.long 0x0 "DCLSDUMMYIR0,DCLS Error Dummy Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6200900++0x7 line.long 0x0 "DCLSDUMMYRT0,DCLS Error Dummy Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "DCLSDUMMYRT1,DCLS Error Dummy Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF0900++0x3 line.long 0x0 "DCLSDUMMYVIP0,DCLS Error Dummy Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD840900++0x3 line.long 0x0 "DCLSDUMMYU3DG0,DCLS Error Dummy Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7730900++0x3 line.long 0x0 "DCLSDUMMYPER00,DCLS Error Dummy Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6490900++0x3 line.long 0x0 "DCLSDUMMYPER10,DCLS Error Dummy Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF840800++0x7 line.long 0x0 "LSCHKDUMMYTOP0,LSCHK Dummy Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "LSCHKDUMMYTOP1,LSCHK Dummy Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF0800++0xB line.long 0x0 "LSCHKDUMMYVIO0,LSCHK Dummy Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "LSCHKDUMMYVIO1,LSCHK Dummy Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "LSCHKDUMMYVIO2,LSCHK Dummy Register for VIO Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE610800++0x7 line.long 0x0 "LSCHKDUMMYVC0,LSCHK Dummy Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "LSCHKDUMMYVC1,LSCHK Dummy Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FC800++0x7 line.long 0x0 "LSCHKDUMMYMM0,LSCHK Dummy Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "LSCHKDUMMYMM1,LSCHK Dummy Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E0800++0x7 line.long 0x0 "LSCHKDUMMYIR0,LSCHK Dummy Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "LSCHKDUMMYIR1,LSCHK Dummy Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6200800++0xB line.long 0x0 "LSCHKDUMMYRT0,LSCHK Dummy Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "LSCHKDUMMYRT1,LSCHK Dummy Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "LSCHKDUMMYRT2,LSCHK Dummy Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF0800++0x7 line.long 0x0 "LSCHKDUMMYVIP0,LSCHK Dummy Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "LSCHKDUMMYVIP1,LSCHK Dummy Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD840800++0x3 line.long 0x0 "LSCHKDUMMYU3DG0,LSCHK Dummy Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7730800++0x7 line.long 0x0 "LSCHKDUMMYPER00,LSCHK Dummy Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "LSCHKDUMMYPER01,LSCHK Dummy Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6490800++0x7 line.long 0x0 "LSCHKDUMMYPER10,LSCHK Dummy Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "LSCHKDUMMYPER11,LSCHK Dummy Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF840A80++0x7 line.long 0x0 "OTHDUMMYTOP0,Other Error Dummy Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "OTHDUMMYTOP1,Other Error Dummy Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF0A80++0x3 line.long 0x0 "OTHDUMMYVIO0,Other Error Dummy Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE610A80++0x3 line.long 0x0 "OTHDUMMYVC0,Other Error Dummy Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FCA80++0x3 line.long 0x0 "OTHDUMMYMM0,Other Error Dummy Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E0A80++0x3 line.long 0x0 "OTHDUMMYIR0,Other Error Dummy Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6200A80++0x3 line.long 0x0 "OTHDUMMYRT0,Other Error Dummy Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF0A80++0x3 line.long 0x0 "OTHDUMMYVIP0,Other Error Dummy Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD840A80++0x3 line.long 0x0 "OTHDUMMYU3DG0,Other Error Dummy Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7730A80++0x3 line.long 0x0 "OTHDUMMYPER00,Other Error Dummy Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6490A80++0x3 line.long 0x0 "OTHDUMMYPER10,Other Error Dummy Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF840780++0xB line.long 0x0 "RERRDUMMYTOP0,Routing Error Dummy Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RERRDUMMYTOP1,Routing Error Dummy Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RERRDUMMYTOP2,Routing Error Dummy Register for TOP Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF0780++0x1B line.long 0x0 "RERRDUMMYVIO0,Routing Error Dummy Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RERRDUMMYVIO1,Routing Error Dummy Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RERRDUMMYVIO2,Routing Error Dummy Register for VIO Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "RERRDUMMYVIO3,Routing Error Dummy Register for VIO Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" line.long 0x10 "RERRDUMMYVIO4,Routing Error Dummy Register for VIO Domain 4" hexmask.long 0x10 0.--31. 1. "DUMMY" line.long 0x14 "RERRDUMMYVIO5,Routing Error Dummy Register for VIO Domain 5" hexmask.long 0x14 0.--31. 1. "DUMMY" line.long 0x18 "RERRDUMMYVIO6,Routing Error Dummy Register for VIO Domain 6" hexmask.long 0x18 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE610780++0xF line.long 0x0 "RERRDUMMYVC0,Routing Error Dummy Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RERRDUMMYVC1,Routing Error Dummy Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RERRDUMMYVC2,Routing Error Dummy Register for VC Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "RERRDUMMYVC3,Routing Error Dummy Register for VC Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FC780++0x7 line.long 0x0 "RERRDUMMYMM0,Routing Error Dummy Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RERRDUMMYMM1,Routing Error Dummy Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E0780++0xF line.long 0x0 "RERRDUMMYIR0,Routing Error Dummy Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RERRDUMMYIR1,Routing Error Dummy Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RERRDUMMYIR2,Routing Error Dummy Register for IR Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "RERRDUMMYIR3,Routing Error Dummy Register for IR Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6200780++0x1B line.long 0x0 "RERRDUMMYRT0,Routing Error Dummy Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RERRDUMMYRT1,Routing Error Dummy Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RERRDUMMYRT2,Routing Error Dummy Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "RERRDUMMYRT3,Routing Error Dummy Register for RT Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" line.long 0x10 "RERRDUMMYRT4,Routing Error Dummy Register for RT Domain 4" hexmask.long 0x10 0.--31. 1. "DUMMY" line.long 0x14 "RERRDUMMYRT5,Routing Error Dummy Register for RT Domain 5" hexmask.long 0x14 0.--31. 1. "DUMMY" line.long 0x18 "RERRDUMMYRT6,Routing Error Dummy Register for RT Domain 6" hexmask.long 0x18 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF0780++0x17 line.long 0x0 "RERRDUMMYVIP0,Routing Error Dummy Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RERRDUMMYVIP1,Routing Error Dummy Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RERRDUMMYVIP2,Routing Error Dummy Register for VIP Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "RERRDUMMYVIP3,Routing Error Dummy Register for VIP Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" line.long 0x10 "RERRDUMMYVIP4,Routing Error Dummy Register for VIP Domain 4" hexmask.long 0x10 0.--31. 1. "DUMMY" line.long 0x14 "RERRDUMMYVIP5,Routing Error Dummy Register for VIP Domain 5" hexmask.long 0x14 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD840780++0x7 line.long 0x0 "RERRDUMMYU3DG0,Routing Error Dummy Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RERRDUMMYU3DG1,Routing Error Dummy Register for U3DG Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7730780++0x13 line.long 0x0 "RERRDUMMYPER00,Routing Error Dummy Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RERRDUMMYPER01,Routing Error Dummy Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RERRDUMMYPER02,Routing Error Dummy Register for PER0 Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "RERRDUMMYPER03,Routing Error Dummy Register for PER0 Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" line.long 0x10 "RERRDUMMYPER04,Routing Error Dummy Register for PER0 Domain 4" hexmask.long 0x10 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6490780++0xF line.long 0x0 "RERRDUMMYPER10,Routing Error Dummy Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RERRDUMMYPER11,Routing Error Dummy Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RERRDUMMYPER12,Routing Error Dummy Register for PER1 Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" line.long 0xC "RERRDUMMYPER13,Routing Error Dummy Register for PER1 Domain 3" hexmask.long 0xC 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF840880++0xB line.long 0x0 "RSCHKDUMMYTOP0,RSCHK Dummy Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RSCHKDUMMYTOP1,RSCHK Dummy Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RSCHKDUMMYTOP2,RSCHK Dummy Register for TOP Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF0880++0x7 line.long 0x0 "RSCHKDUMMYVIO0,RSCHK Dummy Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RSCHKDUMMYVIO1,RSCHK Dummy Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE610880++0x7 line.long 0x0 "RSCHKDUMMYVC0,RSCHK Dummy Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RSCHKDUMMYVC1,RSCHK Dummy Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FC880++0x3 line.long 0x0 "RSCHKDUMMYMM0,RSCHK Dummy Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E0880++0x7 line.long 0x0 "RSCHKDUMMYIR0,RSCHK Dummy Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RSCHKDUMMYIR1,RSCHK Dummy Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6200880++0xB line.long 0x0 "RSCHKDUMMYRT0,RSCHK Dummy Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RSCHKDUMMYRT1,RSCHK Dummy Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RSCHKDUMMYRT2,RSCHK Dummy Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF0880++0xB line.long 0x0 "RSCHKDUMMYVIP0,RSCHK Dummy Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RSCHKDUMMYVIP1,RSCHK Dummy Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RSCHKDUMMYVIP2,RSCHK Dummy Register for VIP Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD840880++0x3 line.long 0x0 "RSCHKDUMMYU3DG0,RSCHK Dummy Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7730880++0xB line.long 0x0 "RSCHKDUMMYPER00,RSCHK Dummy Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RSCHKDUMMYPER01,RSCHK Dummy Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "RSCHKDUMMYPER02,RSCHK Dummy Register for PER0 Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6490880++0x7 line.long 0x0 "RSCHKDUMMYPER10,RSCHK Dummy Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "RSCHKDUMMYPER11,RSCHK Dummy Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8408C0++0x3 line.long 0x0 "TIDDUMMYTOP0,TID Error Dummy Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF08C0++0x7 line.long 0x0 "TIDDUMMYVIO0,TID Error Dummy Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "TIDDUMMYVIO1,TID Error Dummy Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE6108C0++0x7 line.long 0x0 "TIDDUMMYVC0,TID Error Dummy Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "TIDDUMMYVC1,TID Error Dummy Register for VC Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FC8C0++0x3 line.long 0x0 "TIDDUMMYMM0,TID Error Dummy Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E08C0++0x3 line.long 0x0 "TIDDUMMYIR0,TID Error Dummy Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE62008C0++0x7 line.long 0x0 "TIDDUMMYRT0,TID Error Dummy Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "TIDDUMMYRT1,TID Error Dummy Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF08C0++0x7 line.long 0x0 "TIDDUMMYVIP0,TID Error Dummy Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "TIDDUMMYVIP1,TID Error Dummy Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD8408C0++0x3 line.long 0x0 "TIDDUMMYU3DG0,TID Error Dummy Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE77308C0++0x3 line.long 0x0 "TIDDUMMYPER00,TID Error Dummy Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE64908C0++0x7 line.long 0x0 "TIDDUMMYPER10,TID Error Dummy Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "TIDDUMMYPER11,TID Error Dummy Register for PER1 Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8409C0++0x3 line.long 0x0 "SAFERRDUMMYTOP,Safety Access Error Dummy Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF09C0++0x3 line.long 0x0 "SAFERRDUMMYVIO,Safety Access Error Dummy Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE6109C0++0x3 line.long 0x0 "SAFERRDUMMYVC,Safety Access Error Dummy Register for VC Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FC9C0++0x3 line.long 0x0 "SAFERRDUMMYMM,Safety Access Error Dummy Register for MM Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E09C0++0x3 line.long 0x0 "SAFERRDUMMYIR,Safety Access Error Dummy Register for IR Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE62009C0++0x3 line.long 0x0 "SAFERRDUMMYRT,Safety Access Error Dummy Register for RT Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF09C0++0x3 line.long 0x0 "SAFERRDUMMYVIP,Safety Access Error Dummy Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD8409C0++0x3 line.long 0x0 "SAFERRDUMMYU3DG,Safety Access Error Dummy Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE77309C0++0x3 line.long 0x0 "SAFERRDUMMYPER0,Safety Access Error Dummy Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE64909C0++0x3 line.long 0x0 "SAFERRDUMMYPER1,Safety Access Error Dummy Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF840280++0x3 line.long 0x0 "SECERRDUMMYTOP,Security Access Error Dummy Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF0280++0x3 line.long 0x0 "SECERRDUMMYVIO,Security Access Error Dummy Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE610280++0x3 line.long 0x0 "SECERRDUMMYVC,Security Access Error Dummy Register for VC Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FC280++0x3 line.long 0x0 "SECERRDUMMYMM,Security Access Error Dummy Register for MM Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E0280++0x3 line.long 0x0 "SECERRDUMMYIR,Security Access Error Dummy Register for IR Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6200280++0x3 line.long 0x0 "SECERRDUMMYRT,Security Access Error Dummy Register for RT Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF0280++0x3 line.long 0x0 "SECERRDUMMYVIP,Security Access Error Dummy Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD840280++0x3 line.long 0x0 "SECERRDUMMYU3DG,Security Access Error Dummy Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7730280++0x3 line.long 0x0 "SECERRDUMMYPER0,Security Access Error Dummy Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6490280++0x3 line.long 0x0 "SECERRDUMMYPER1,Security Access Error Dummy Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF840840++0x7 line.long 0x0 "WCRCDUMMYTOP0,Write Read Check Dummy Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "WCRCDUMMYTOP1,Write Read Check Dummy Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF0840++0x7 line.long 0x0 "WCRCDUMMYVIO0,Write Read Check Dummy Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "WCRCDUMMYVIO1,Write Read Check Dummy Register for VIO Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE610840++0x3 line.long 0x0 "WCRCDUMMYVC0,Write Read Check Dummy Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FC840++0x3 line.long 0x0 "WCRCDUMMYMM0,Write Read Check Dummy Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E0840++0x7 line.long 0x0 "WCRCDUMMYIR0,Write Read Check Dummy Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "WCRCDUMMYIR1,Write Read Check Dummy Register for IR Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6200840++0xB line.long 0x0 "WCRCDUMMYRT0,Write Read Check Dummy Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "WCRCDUMMYRT1,Write Read Check Dummy Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" line.long 0x8 "WCRCDUMMYRT2,Write Read Check Dummy Register for RT Domain 2" hexmask.long 0x8 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF0840++0x7 line.long 0x0 "WCRCDUMMYVIP0,Write Read Check Dummy Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "WCRCDUMMYVIP1,Write Read Check Dummy Register for VIP Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD840840++0x3 line.long 0x0 "WCRCDUMMYU3DG0,Write Read Check Dummy Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7730840++0x7 line.long 0x0 "WCRCDUMMYPER00,Write Read Check Dummy Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" line.long 0x4 "WCRCDUMMYPER01,Write Read Check Dummy Register for PER0 Domain 1" hexmask.long 0x4 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6490840++0x3 line.long 0x0 "WCRCDUMMYPER10,Write Read Check Dummy Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF840A40++0x3 line.long 0x0 "FCPRDUMMYTOP,FCPR Error Dummy Register for TOP Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFEAF0A40++0x3 line.long 0x0 "FCPRDUMMYVIO,FCPR Error Dummy Register for VIO Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFE610A40++0x3 line.long 0x0 "FCPRDUMMYVC,FCPR Error Dummy Register for VC Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE67FCA40++0x3 line.long 0x0 "FCPRDUMMYMM,FCPR Error Dummy Register for MM Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF8E0A40++0x3 line.long 0x0 "FCPRDUMMYIR,FCPR Error Dummy Register for IR Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6200A40++0x3 line.long 0x0 "FCPRDUMMYRT,FCPR Error Dummy Register for RT Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7AF0A40++0x3 line.long 0x0 "FCPRDUMMYVIP,FCPR Error Dummy Register for VIP Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFD840A40++0x3 line.long 0x0 "FCPRDUMMYU3DG,FCPR Error Dummy Register for U3DG Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE7730A40++0x3 line.long 0x0 "FCPRDUMMYPER0,FCPR Error Dummy Register for PER0 Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFE6490A40++0x3 line.long 0x0 "FCPRDUMMYPER1,FCPR Error Dummy Register for PER1 Domain" hexmask.long 0x0 0.--31. 1. "DUMMY" group.long 0xFFFFFFFFFF840AC0++0x7 line.long 0x0 "DCLSMONTOP0,DCLS Monitor Register for TOP Domain 0" hexmask.long 0x0 0.--31. 1. "DCLSMON" line.long 0x4 "DCLSMONTOP1,DCLS Monitor Register for TOP Domain 1" hexmask.long 0x4 0.--31. 1. "DCLSMON" group.long 0xFFFFFFFFFEAF0AC0++0x3 line.long 0x0 "DCLSMONVIO0,DCLS Monitor Register for VIO Domain 0" hexmask.long 0x0 0.--31. 1. "DCLSMON" group.long 0xFFFFFFFFFE610AC0++0x3 line.long 0x0 "DCLSMONVC0,DCLS Monitor Register for VC Domain 0" hexmask.long 0x0 0.--31. 1. "DCLSMON" group.long 0xFFFFFFFFE67FCAC0++0x7 line.long 0x0 "DCLSMONMM0,DCLS Monitor Register for MM Domain 0" hexmask.long 0x0 0.--31. 1. "DCLSMON" line.long 0x4 "DCLSMONMM1,DCLS Monitor Register for MM Domain 1" hexmask.long 0x4 0.--31. 1. "DCLSMON" group.long 0xFFFFFFFFFF8E0AC0++0x3 line.long 0x0 "DCLSMONIR0,DCLS Monitor Register for IR Domain 0" hexmask.long 0x0 0.--31. 1. "DCLSMON" group.long 0xFFFFFFFFE6200AC0++0x7 line.long 0x0 "DCLSMONRT0,DCLS Monitor Register for RT Domain 0" hexmask.long 0x0 0.--31. 1. "DCLSMON" line.long 0x4 "DCLSMONRT1,DCLS Monitor Register for RT Domain 1" hexmask.long 0x4 0.--31. 1. "DCLSMON" group.long 0xFFFFFFFFE7AF0AC0++0x3 line.long 0x0 "DCLSMONVIP0,DCLS Monitor Register for VIP Domain 0" hexmask.long 0x0 0.--31. 1. "DCLSMON" group.long 0xFFFFFFFFFD840AC0++0x3 line.long 0x0 "DCLSMONU3DG0,DCLS Monitor Register for U3DG Domain 0" hexmask.long 0x0 0.--31. 1. "DCLSMON" group.long 0xFFFFFFFFE7730AC0++0x3 line.long 0x0 "DCLSMONPER00,DCLS Monitor Register for PER0 Domain 0" hexmask.long 0x0 0.--31. 1. "DCLSMON" group.long 0xFFFFFFFFE6490AC0++0x3 line.long 0x0 "DCLSMONPER10,DCLS Monitor Register for PER1 Domain 0" hexmask.long 0x0 0.--31. 1. "DCLSMON" tree.end tree "AXMM" base ad:0xE6780000 group.long 0x4008++0xF line.long 0x0 "ADSPLCR0,Address Split Control Register 0" hexmask.long.byte 0x0 16.--23. 1. "SPLITSEL" hexmask.long.byte 0x0 8.--12. 1. "AREA" hexmask.long.byte 0x0 0.--4. 1. "SWP" line.long 0x4 "ADSPLCR1,Address Split Control Register 1" hexmask.long.byte 0x4 16.--23. 1. "SPLITSEL" hexmask.long.byte 0x4 8.--12. 1. "AREA" hexmask.long.byte 0x4 0.--4. 1. "SWP" line.long 0x8 "ADSPLCR2,Address Split Control Register 2" bitfld.long 0x8 31. "B37EOREN" "0,1" bitfld.long 0x8 28.--30. "B37EORSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x8 27. "B36EOREN" "0,1" bitfld.long 0x8 24.--26. "B36EORSEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 23. "B13EOREN" "0,1" bitfld.long 0x8 20.--22. "B13EORSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x8 19. "B12EOREN" "0,1" bitfld.long 0x8 16.--18. "B12EORSEL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--14. "B15SWPSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "B14SWPSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "B13SWPSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "B12SWPSEL" "0,1,2,3,4,5,6,7" line.long 0xC "ADSPLCR3,Address Split Control Register 3" hexmask.long.byte 0xC 16.--23. 1. "SPLITSEL" hexmask.long.byte 0xC 8.--12. 1. "AREA" hexmask.long.byte 0xC 0.--4. 1. "SWP" group.long 0x4300++0x3 line.long 0x0 "MMCR,Main Memory AXI Control Register" bitfld.long 0x0 31. "CTRL31" "0,1" bitfld.long 0x0 16. "CTRL16" "0,1" bitfld.long 0x0 5. "CTRL5" "0,1" bitfld.long 0x0 4. "CTRL4" "0,1" newline bitfld.long 0x0 3. "CTRL3" "0,1" bitfld.long 0x0 2. "CTRL2" "0,1" group.long 0x5300++0x3 line.long 0x0 "DUMMYERRCR,Dummy Error Control Register" bitfld.long 0x0 5. "RGNERRINJ" "0,1" bitfld.long 0x0 4. "SECERRINJ" "0,1" bitfld.long 0x0 3. "EDCERRINJ" "0,1" group.long 0x6000++0xFB line.long 0x0 "DPTDIVCR0,DRAM Protected Area Division Register 0" hexmask.long.tbyte 0x0 0.--21. 1. "DIVADDR" line.long 0x4 "DPTDIVCR1,DRAM Protected Area Division Register 1" hexmask.long.tbyte 0x4 0.--21. 1. "DIVADDR" line.long 0x8 "DPTDIVCR2,DRAM Protected Area Division Register 2" hexmask.long.tbyte 0x8 0.--21. 1. "DIVADDR" line.long 0xC "DPTDIVCR3,DRAM Protected Area Division Register 3" hexmask.long.tbyte 0xC 0.--21. 1. "DIVADDR" line.long 0x10 "DPTDIVCR4,DRAM Protected Area Division Register 4" hexmask.long.tbyte 0x10 0.--21. 1. "DIVADDR" line.long 0x14 "DPTDIVCR5,DRAM Protected Area Division Register 5" hexmask.long.tbyte 0x14 0.--21. 1. "DIVADDR" line.long 0x18 "DPTDIVCR6,DRAM Protected Area Division Register 6" hexmask.long.tbyte 0x18 0.--21. 1. "DIVADDR" line.long 0x1C "DPTDIVCR7,DRAM Protected Area Division Register 7" hexmask.long.tbyte 0x1C 0.--21. 1. "DIVADDR" line.long 0x20 "DPTDIVCR8,DRAM Protected Area Division Register 8" hexmask.long.tbyte 0x20 0.--21. 1. "DIVADDR" line.long 0x24 "DPTDIVCR9,DRAM Protected Area Division Register 9" hexmask.long.tbyte 0x24 0.--21. 1. "DIVADDR" line.long 0x28 "DPTDIVCR10,DRAM Protected Area Division Register 10" hexmask.long.tbyte 0x28 0.--21. 1. "DIVADDR" line.long 0x2C "DPTDIVCR11,DRAM Protected Area Division Register 11" hexmask.long.tbyte 0x2C 0.--21. 1. "DIVADDR" line.long 0x30 "DPTDIVCR12,DRAM Protected Area Division Register 12" hexmask.long.tbyte 0x30 0.--21. 1. "DIVADDR" line.long 0x34 "DPTDIVCR13,DRAM Protected Area Division Register 13" hexmask.long.tbyte 0x34 0.--21. 1. "DIVADDR" line.long 0x38 "DPTDIVCR14,DRAM Protected Area Division Register 14" hexmask.long.tbyte 0x38 0.--21. 1. "DIVADDR" line.long 0x3C "DPTDIVCR15,DRAM Protected Area Division Register 15" hexmask.long.tbyte 0x3C 0.--21. 1. "DIVADDR" line.long 0x40 "DPTDIVCR16,DRAM Protected Area Division Register 16" hexmask.long.tbyte 0x40 0.--21. 1. "DIVADDR" line.long 0x44 "DPTDIVCR17,DRAM Protected Area Division Register 17" hexmask.long.tbyte 0x44 0.--21. 1. "DIVADDR" line.long 0x48 "DPTDIVCR18,DRAM Protected Area Division Register 18" hexmask.long.tbyte 0x48 0.--21. 1. "DIVADDR" line.long 0x4C "DPTDIVCR19,DRAM Protected Area Division Register 19" hexmask.long.tbyte 0x4C 0.--21. 1. "DIVADDR" line.long 0x50 "DPTDIVCR20,DRAM Protected Area Division Register 20" hexmask.long.tbyte 0x50 0.--21. 1. "DIVADDR" line.long 0x54 "DPTDIVCR21,DRAM Protected Area Division Register 21" hexmask.long.tbyte 0x54 0.--21. 1. "DIVADDR" line.long 0x58 "DPTDIVCR22,DRAM Protected Area Division Register 22" hexmask.long.tbyte 0x58 0.--21. 1. "DIVADDR" line.long 0x5C "DPTDIVCR23,DRAM Protected Area Division Register 23" hexmask.long.tbyte 0x5C 0.--21. 1. "DIVADDR" line.long 0x60 "DPTDIVCR24,DRAM Protected Area Division Register 24" hexmask.long.tbyte 0x60 0.--21. 1. "DIVADDR" line.long 0x64 "DPTDIVCR25,DRAM Protected Area Division Register 25" hexmask.long.tbyte 0x64 0.--21. 1. "DIVADDR" line.long 0x68 "DPTDIVCR26,DRAM Protected Area Division Register 26" hexmask.long.tbyte 0x68 0.--21. 1. "DIVADDR" line.long 0x6C "DPTDIVCR27,DRAM Protected Area Division Register 27" hexmask.long.tbyte 0x6C 0.--21. 1. "DIVADDR" line.long 0x70 "DPTDIVCR28,DRAM Protected Area Division Register 28" hexmask.long.tbyte 0x70 0.--21. 1. "DIVADDR" line.long 0x74 "DPTDIVCR29,DRAM Protected Area Division Register 29" hexmask.long.tbyte 0x74 0.--21. 1. "DIVADDR" line.long 0x78 "DPTDIVCR30,DRAM Protected Area Division Register 30" hexmask.long.tbyte 0x78 0.--21. 1. "DIVADDR" line.long 0x7C "DPTDIVCR31,DRAM Protected Area Division Register 31" hexmask.long.tbyte 0x7C 0.--21. 1. "DIVADDR" line.long 0x80 "DPTDIVCR32,DRAM Protected Area Division Register 32" hexmask.long.tbyte 0x80 0.--21. 1. "DIVADDR" line.long 0x84 "DPTDIVCR33,DRAM Protected Area Division Register 33" hexmask.long.tbyte 0x84 0.--21. 1. "DIVADDR" line.long 0x88 "DPTDIVCR34,DRAM Protected Area Division Register 34" hexmask.long.tbyte 0x88 0.--21. 1. "DIVADDR" line.long 0x8C "DPTDIVCR35,DRAM Protected Area Division Register 35" hexmask.long.tbyte 0x8C 0.--21. 1. "DIVADDR" line.long 0x90 "DPTDIVCR36,DRAM Protected Area Division Register 36" hexmask.long.tbyte 0x90 0.--21. 1. "DIVADDR" line.long 0x94 "DPTDIVCR37,DRAM Protected Area Division Register 37" hexmask.long.tbyte 0x94 0.--21. 1. "DIVADDR" line.long 0x98 "DPTDIVCR38,DRAM Protected Area Division Register 38" hexmask.long.tbyte 0x98 0.--21. 1. "DIVADDR" line.long 0x9C "DPTDIVCR39,DRAM Protected Area Division Register 39" hexmask.long.tbyte 0x9C 0.--21. 1. "DIVADDR" line.long 0xA0 "DPTDIVCR40,DRAM Protected Area Division Register 40" hexmask.long.tbyte 0xA0 0.--21. 1. "DIVADDR" line.long 0xA4 "DPTDIVCR41,DRAM Protected Area Division Register 41" hexmask.long.tbyte 0xA4 0.--21. 1. "DIVADDR" line.long 0xA8 "DPTDIVCR42,DRAM Protected Area Division Register 42" hexmask.long.tbyte 0xA8 0.--21. 1. "DIVADDR" line.long 0xAC "DPTDIVCR43,DRAM Protected Area Division Register 43" hexmask.long.tbyte 0xAC 0.--21. 1. "DIVADDR" line.long 0xB0 "DPTDIVCR44,DRAM Protected Area Division Register 44" hexmask.long.tbyte 0xB0 0.--21. 1. "DIVADDR" line.long 0xB4 "DPTDIVCR45,DRAM Protected Area Division Register 45" hexmask.long.tbyte 0xB4 0.--21. 1. "DIVADDR" line.long 0xB8 "DPTDIVCR46,DRAM Protected Area Division Register 46" hexmask.long.tbyte 0xB8 0.--21. 1. "DIVADDR" line.long 0xBC "DPTDIVCR47,DRAM Protected Area Division Register 47" hexmask.long.tbyte 0xBC 0.--21. 1. "DIVADDR" line.long 0xC0 "DPTDIVCR48,DRAM Protected Area Division Register 48" hexmask.long.tbyte 0xC0 0.--21. 1. "DIVADDR" line.long 0xC4 "DPTDIVCR49,DRAM Protected Area Division Register 49" hexmask.long.tbyte 0xC4 0.--21. 1. "DIVADDR" line.long 0xC8 "DPTDIVCR50,DRAM Protected Area Division Register 50" hexmask.long.tbyte 0xC8 0.--21. 1. "DIVADDR" line.long 0xCC "DPTDIVCR51,DRAM Protected Area Division Register 51" hexmask.long.tbyte 0xCC 0.--21. 1. "DIVADDR" line.long 0xD0 "DPTDIVCR52,DRAM Protected Area Division Register 52" hexmask.long.tbyte 0xD0 0.--21. 1. "DIVADDR" line.long 0xD4 "DPTDIVCR53,DRAM Protected Area Division Register 53" hexmask.long.tbyte 0xD4 0.--21. 1. "DIVADDR" line.long 0xD8 "DPTDIVCR54,DRAM Protected Area Division Register 54" hexmask.long.tbyte 0xD8 0.--21. 1. "DIVADDR" line.long 0xDC "DPTDIVCR55,DRAM Protected Area Division Register 55" hexmask.long.tbyte 0xDC 0.--21. 1. "DIVADDR" line.long 0xE0 "DPTDIVCR56,DRAM Protected Area Division Register 56" hexmask.long.tbyte 0xE0 0.--21. 1. "DIVADDR" line.long 0xE4 "DPTDIVCR57,DRAM Protected Area Division Register 57" hexmask.long.tbyte 0xE4 0.--21. 1. "DIVADDR" line.long 0xE8 "DPTDIVCR58,DRAM Protected Area Division Register 58" hexmask.long.tbyte 0xE8 0.--21. 1. "DIVADDR" line.long 0xEC "DPTDIVCR59,DRAM Protected Area Division Register 59" hexmask.long.tbyte 0xEC 0.--21. 1. "DIVADDR" line.long 0xF0 "DPTDIVCR60,DRAM Protected Area Division Register 60" hexmask.long.tbyte 0xF0 0.--21. 1. "DIVADDR" line.long 0xF4 "DPTDIVCR61,DRAM Protected Area Division Register 61" hexmask.long.tbyte 0xF4 0.--21. 1. "DIVADDR" line.long 0xF8 "DPTDIVCR62,DRAM Protected Area Division Register 62" hexmask.long.tbyte 0xF8 0.--21. 1. "DIVADDR" group.long 0x6100++0x23B line.long 0x0 "DPTRGNCR0,DRAM Protected Area Region ID Setting Register 0" bitfld.long 0x0 31. "RGN15RP" "0,1" bitfld.long 0x0 30. "RGN14RP" "0,1" bitfld.long 0x0 29. "RGN13RP" "0,1" bitfld.long 0x0 28. "RGN12RP" "0,1" newline bitfld.long 0x0 27. "RGN11RP" "0,1" bitfld.long 0x0 26. "RGN10RP" "0,1" bitfld.long 0x0 25. "RGN9RP" "0,1" bitfld.long 0x0 24. "RGN8RP" "0,1" newline bitfld.long 0x0 23. "RGN7RP" "0,1" bitfld.long 0x0 22. "RGN6RP" "0,1" bitfld.long 0x0 21. "RGN5RP" "0,1" bitfld.long 0x0 20. "RGN4RP" "0,1" newline bitfld.long 0x0 19. "RGN3RP" "0,1" bitfld.long 0x0 18. "RGN2RP" "0,1" bitfld.long 0x0 17. "RGN1RP" "0,1" bitfld.long 0x0 16. "RGN0RP" "0,1" newline bitfld.long 0x0 15. "RGN15WP" "0,1" bitfld.long 0x0 14. "RGN14WP" "0,1" bitfld.long 0x0 13. "RGN13WP" "0,1" bitfld.long 0x0 12. "RGN12WP" "0,1" newline bitfld.long 0x0 11. "RGN11WP" "0,1" bitfld.long 0x0 10. "RGN10WP" "0,1" bitfld.long 0x0 9. "RGN9WP" "0,1" bitfld.long 0x0 8. "RGN8WP" "0,1" newline bitfld.long 0x0 7. "RGN7WP" "0,1" bitfld.long 0x0 6. "RGN6WP" "0,1" bitfld.long 0x0 5. "RGN5WP" "0,1" bitfld.long 0x0 4. "RGN4WP" "0,1" newline bitfld.long 0x0 3. "RGN3WP" "0,1" bitfld.long 0x0 2. "RGN2WP" "0,1" bitfld.long 0x0 1. "RGN1WP" "0,1" bitfld.long 0x0 0. "RGN0WP" "0,1" line.long 0x4 "DPTRGNCR1,DRAM Protected Area Region ID Setting Register 1" bitfld.long 0x4 31. "RGN15RP" "0,1" bitfld.long 0x4 30. "RGN14RP" "0,1" bitfld.long 0x4 29. "RGN13RP" "0,1" bitfld.long 0x4 28. "RGN12RP" "0,1" newline bitfld.long 0x4 27. "RGN11RP" "0,1" bitfld.long 0x4 26. "RGN10RP" "0,1" bitfld.long 0x4 25. "RGN9RP" "0,1" bitfld.long 0x4 24. "RGN8RP" "0,1" newline bitfld.long 0x4 23. "RGN7RP" "0,1" bitfld.long 0x4 22. "RGN6RP" "0,1" bitfld.long 0x4 21. "RGN5RP" "0,1" bitfld.long 0x4 20. "RGN4RP" "0,1" newline bitfld.long 0x4 19. "RGN3RP" "0,1" bitfld.long 0x4 18. "RGN2RP" "0,1" bitfld.long 0x4 17. "RGN1RP" "0,1" bitfld.long 0x4 16. "RGN0RP" "0,1" newline bitfld.long 0x4 15. "RGN15WP" "0,1" bitfld.long 0x4 14. "RGN14WP" "0,1" bitfld.long 0x4 13. "RGN13WP" "0,1" bitfld.long 0x4 12. "RGN12WP" "0,1" newline bitfld.long 0x4 11. "RGN11WP" "0,1" bitfld.long 0x4 10. "RGN10WP" "0,1" bitfld.long 0x4 9. "RGN9WP" "0,1" bitfld.long 0x4 8. "RGN8WP" "0,1" newline bitfld.long 0x4 7. "RGN7WP" "0,1" bitfld.long 0x4 6. "RGN6WP" "0,1" bitfld.long 0x4 5. "RGN5WP" "0,1" bitfld.long 0x4 4. "RGN4WP" "0,1" newline bitfld.long 0x4 3. "RGN3WP" "0,1" bitfld.long 0x4 2. "RGN2WP" "0,1" bitfld.long 0x4 1. "RGN1WP" "0,1" bitfld.long 0x4 0. "RGN0WP" "0,1" line.long 0x8 "DPTRGNCR2,DRAM Protected Area Region ID Setting Register 2" bitfld.long 0x8 31. "RGN15RP" "0,1" bitfld.long 0x8 30. "RGN14RP" "0,1" bitfld.long 0x8 29. "RGN13RP" "0,1" bitfld.long 0x8 28. "RGN12RP" "0,1" newline bitfld.long 0x8 27. "RGN11RP" "0,1" bitfld.long 0x8 26. "RGN10RP" "0,1" bitfld.long 0x8 25. "RGN9RP" "0,1" bitfld.long 0x8 24. "RGN8RP" "0,1" newline bitfld.long 0x8 23. "RGN7RP" "0,1" bitfld.long 0x8 22. "RGN6RP" "0,1" bitfld.long 0x8 21. "RGN5RP" "0,1" bitfld.long 0x8 20. "RGN4RP" "0,1" newline bitfld.long 0x8 19. "RGN3RP" "0,1" bitfld.long 0x8 18. "RGN2RP" "0,1" bitfld.long 0x8 17. "RGN1RP" "0,1" bitfld.long 0x8 16. "RGN0RP" "0,1" newline bitfld.long 0x8 15. "RGN15WP" "0,1" bitfld.long 0x8 14. "RGN14WP" "0,1" bitfld.long 0x8 13. "RGN13WP" "0,1" bitfld.long 0x8 12. "RGN12WP" "0,1" newline bitfld.long 0x8 11. "RGN11WP" "0,1" bitfld.long 0x8 10. "RGN10WP" "0,1" bitfld.long 0x8 9. "RGN9WP" "0,1" bitfld.long 0x8 8. "RGN8WP" "0,1" newline bitfld.long 0x8 7. "RGN7WP" "0,1" bitfld.long 0x8 6. "RGN6WP" "0,1" bitfld.long 0x8 5. "RGN5WP" "0,1" bitfld.long 0x8 4. "RGN4WP" "0,1" newline bitfld.long 0x8 3. "RGN3WP" "0,1" bitfld.long 0x8 2. "RGN2WP" "0,1" bitfld.long 0x8 1. "RGN1WP" "0,1" bitfld.long 0x8 0. "RGN0WP" "0,1" line.long 0xC "DPTRGNCR3,DRAM Protected Area Region ID Setting Register 3" bitfld.long 0xC 31. "RGN15RP" "0,1" bitfld.long 0xC 30. "RGN14RP" "0,1" bitfld.long 0xC 29. "RGN13RP" "0,1" bitfld.long 0xC 28. "RGN12RP" "0,1" newline bitfld.long 0xC 27. "RGN11RP" "0,1" bitfld.long 0xC 26. "RGN10RP" "0,1" bitfld.long 0xC 25. "RGN9RP" "0,1" bitfld.long 0xC 24. "RGN8RP" "0,1" newline bitfld.long 0xC 23. "RGN7RP" "0,1" bitfld.long 0xC 22. "RGN6RP" "0,1" bitfld.long 0xC 21. "RGN5RP" "0,1" bitfld.long 0xC 20. "RGN4RP" "0,1" newline bitfld.long 0xC 19. "RGN3RP" "0,1" bitfld.long 0xC 18. "RGN2RP" "0,1" bitfld.long 0xC 17. "RGN1RP" "0,1" bitfld.long 0xC 16. "RGN0RP" "0,1" newline bitfld.long 0xC 15. "RGN15WP" "0,1" bitfld.long 0xC 14. "RGN14WP" "0,1" bitfld.long 0xC 13. "RGN13WP" "0,1" bitfld.long 0xC 12. "RGN12WP" "0,1" newline bitfld.long 0xC 11. "RGN11WP" "0,1" bitfld.long 0xC 10. "RGN10WP" "0,1" bitfld.long 0xC 9. "RGN9WP" "0,1" bitfld.long 0xC 8. "RGN8WP" "0,1" newline bitfld.long 0xC 7. "RGN7WP" "0,1" bitfld.long 0xC 6. "RGN6WP" "0,1" bitfld.long 0xC 5. "RGN5WP" "0,1" bitfld.long 0xC 4. "RGN4WP" "0,1" newline bitfld.long 0xC 3. "RGN3WP" "0,1" bitfld.long 0xC 2. "RGN2WP" "0,1" bitfld.long 0xC 1. "RGN1WP" "0,1" bitfld.long 0xC 0. "RGN0WP" "0,1" line.long 0x10 "DPTRGNCR4,DRAM Protected Area Region ID Setting Register 4" bitfld.long 0x10 31. "RGN15RP" "0,1" bitfld.long 0x10 30. "RGN14RP" "0,1" bitfld.long 0x10 29. "RGN13RP" "0,1" bitfld.long 0x10 28. "RGN12RP" "0,1" newline bitfld.long 0x10 27. "RGN11RP" "0,1" bitfld.long 0x10 26. "RGN10RP" "0,1" bitfld.long 0x10 25. "RGN9RP" "0,1" bitfld.long 0x10 24. "RGN8RP" "0,1" newline bitfld.long 0x10 23. "RGN7RP" "0,1" bitfld.long 0x10 22. "RGN6RP" "0,1" bitfld.long 0x10 21. "RGN5RP" "0,1" bitfld.long 0x10 20. "RGN4RP" "0,1" newline bitfld.long 0x10 19. "RGN3RP" "0,1" bitfld.long 0x10 18. "RGN2RP" "0,1" bitfld.long 0x10 17. "RGN1RP" "0,1" bitfld.long 0x10 16. "RGN0RP" "0,1" newline bitfld.long 0x10 15. "RGN15WP" "0,1" bitfld.long 0x10 14. "RGN14WP" "0,1" bitfld.long 0x10 13. "RGN13WP" "0,1" bitfld.long 0x10 12. "RGN12WP" "0,1" newline bitfld.long 0x10 11. "RGN11WP" "0,1" bitfld.long 0x10 10. "RGN10WP" "0,1" bitfld.long 0x10 9. "RGN9WP" "0,1" bitfld.long 0x10 8. "RGN8WP" "0,1" newline bitfld.long 0x10 7. "RGN7WP" "0,1" bitfld.long 0x10 6. "RGN6WP" "0,1" bitfld.long 0x10 5. "RGN5WP" "0,1" bitfld.long 0x10 4. "RGN4WP" "0,1" newline bitfld.long 0x10 3. "RGN3WP" "0,1" bitfld.long 0x10 2. "RGN2WP" "0,1" bitfld.long 0x10 1. "RGN1WP" "0,1" bitfld.long 0x10 0. "RGN0WP" "0,1" line.long 0x14 "DPTRGNCR5,DRAM Protected Area Region ID Setting Register 5" bitfld.long 0x14 31. "RGN15RP" "0,1" bitfld.long 0x14 30. "RGN14RP" "0,1" bitfld.long 0x14 29. "RGN13RP" "0,1" bitfld.long 0x14 28. "RGN12RP" "0,1" newline bitfld.long 0x14 27. "RGN11RP" "0,1" bitfld.long 0x14 26. "RGN10RP" "0,1" bitfld.long 0x14 25. "RGN9RP" "0,1" bitfld.long 0x14 24. "RGN8RP" "0,1" newline bitfld.long 0x14 23. "RGN7RP" "0,1" bitfld.long 0x14 22. "RGN6RP" "0,1" bitfld.long 0x14 21. "RGN5RP" "0,1" bitfld.long 0x14 20. "RGN4RP" "0,1" newline bitfld.long 0x14 19. "RGN3RP" "0,1" bitfld.long 0x14 18. "RGN2RP" "0,1" bitfld.long 0x14 17. "RGN1RP" "0,1" bitfld.long 0x14 16. "RGN0RP" "0,1" newline bitfld.long 0x14 15. "RGN15WP" "0,1" bitfld.long 0x14 14. "RGN14WP" "0,1" bitfld.long 0x14 13. "RGN13WP" "0,1" bitfld.long 0x14 12. "RGN12WP" "0,1" newline bitfld.long 0x14 11. "RGN11WP" "0,1" bitfld.long 0x14 10. "RGN10WP" "0,1" bitfld.long 0x14 9. "RGN9WP" "0,1" bitfld.long 0x14 8. "RGN8WP" "0,1" newline bitfld.long 0x14 7. "RGN7WP" "0,1" bitfld.long 0x14 6. "RGN6WP" "0,1" bitfld.long 0x14 5. "RGN5WP" "0,1" bitfld.long 0x14 4. "RGN4WP" "0,1" newline bitfld.long 0x14 3. "RGN3WP" "0,1" bitfld.long 0x14 2. "RGN2WP" "0,1" bitfld.long 0x14 1. "RGN1WP" "0,1" bitfld.long 0x14 0. "RGN0WP" "0,1" line.long 0x18 "DPTRGNCR6,DRAM Protected Area Region ID Setting Register 6" bitfld.long 0x18 31. "RGN15RP" "0,1" bitfld.long 0x18 30. "RGN14RP" "0,1" bitfld.long 0x18 29. "RGN13RP" "0,1" bitfld.long 0x18 28. "RGN12RP" "0,1" newline bitfld.long 0x18 27. "RGN11RP" "0,1" bitfld.long 0x18 26. "RGN10RP" "0,1" bitfld.long 0x18 25. "RGN9RP" "0,1" bitfld.long 0x18 24. "RGN8RP" "0,1" newline bitfld.long 0x18 23. "RGN7RP" "0,1" bitfld.long 0x18 22. "RGN6RP" "0,1" bitfld.long 0x18 21. "RGN5RP" "0,1" bitfld.long 0x18 20. "RGN4RP" "0,1" newline bitfld.long 0x18 19. "RGN3RP" "0,1" bitfld.long 0x18 18. "RGN2RP" "0,1" bitfld.long 0x18 17. "RGN1RP" "0,1" bitfld.long 0x18 16. "RGN0RP" "0,1" newline bitfld.long 0x18 15. "RGN15WP" "0,1" bitfld.long 0x18 14. "RGN14WP" "0,1" bitfld.long 0x18 13. "RGN13WP" "0,1" bitfld.long 0x18 12. "RGN12WP" "0,1" newline bitfld.long 0x18 11. "RGN11WP" "0,1" bitfld.long 0x18 10. "RGN10WP" "0,1" bitfld.long 0x18 9. "RGN9WP" "0,1" bitfld.long 0x18 8. "RGN8WP" "0,1" newline bitfld.long 0x18 7. "RGN7WP" "0,1" bitfld.long 0x18 6. "RGN6WP" "0,1" bitfld.long 0x18 5. "RGN5WP" "0,1" bitfld.long 0x18 4. "RGN4WP" "0,1" newline bitfld.long 0x18 3. "RGN3WP" "0,1" bitfld.long 0x18 2. "RGN2WP" "0,1" bitfld.long 0x18 1. "RGN1WP" "0,1" bitfld.long 0x18 0. "RGN0WP" "0,1" line.long 0x1C "DPTRGNCR7,DRAM Protected Area Region ID Setting Register 7" bitfld.long 0x1C 31. "RGN15RP" "0,1" bitfld.long 0x1C 30. "RGN14RP" "0,1" bitfld.long 0x1C 29. "RGN13RP" "0,1" bitfld.long 0x1C 28. "RGN12RP" "0,1" newline bitfld.long 0x1C 27. "RGN11RP" "0,1" bitfld.long 0x1C 26. "RGN10RP" "0,1" bitfld.long 0x1C 25. "RGN9RP" "0,1" bitfld.long 0x1C 24. "RGN8RP" "0,1" newline bitfld.long 0x1C 23. "RGN7RP" "0,1" bitfld.long 0x1C 22. "RGN6RP" "0,1" bitfld.long 0x1C 21. "RGN5RP" "0,1" bitfld.long 0x1C 20. "RGN4RP" "0,1" newline bitfld.long 0x1C 19. "RGN3RP" "0,1" bitfld.long 0x1C 18. "RGN2RP" "0,1" bitfld.long 0x1C 17. "RGN1RP" "0,1" bitfld.long 0x1C 16. "RGN0RP" "0,1" newline bitfld.long 0x1C 15. "RGN15WP" "0,1" bitfld.long 0x1C 14. "RGN14WP" "0,1" bitfld.long 0x1C 13. "RGN13WP" "0,1" bitfld.long 0x1C 12. "RGN12WP" "0,1" newline bitfld.long 0x1C 11. "RGN11WP" "0,1" bitfld.long 0x1C 10. "RGN10WP" "0,1" bitfld.long 0x1C 9. "RGN9WP" "0,1" bitfld.long 0x1C 8. "RGN8WP" "0,1" newline bitfld.long 0x1C 7. "RGN7WP" "0,1" bitfld.long 0x1C 6. "RGN6WP" "0,1" bitfld.long 0x1C 5. "RGN5WP" "0,1" bitfld.long 0x1C 4. "RGN4WP" "0,1" newline bitfld.long 0x1C 3. "RGN3WP" "0,1" bitfld.long 0x1C 2. "RGN2WP" "0,1" bitfld.long 0x1C 1. "RGN1WP" "0,1" bitfld.long 0x1C 0. "RGN0WP" "0,1" line.long 0x20 "DPTRGNCR8,DRAM Protected Area Region ID Setting Register 8" bitfld.long 0x20 31. "RGN15RP" "0,1" bitfld.long 0x20 30. "RGN14RP" "0,1" bitfld.long 0x20 29. "RGN13RP" "0,1" bitfld.long 0x20 28. "RGN12RP" "0,1" newline bitfld.long 0x20 27. "RGN11RP" "0,1" bitfld.long 0x20 26. "RGN10RP" "0,1" bitfld.long 0x20 25. "RGN9RP" "0,1" bitfld.long 0x20 24. "RGN8RP" "0,1" newline bitfld.long 0x20 23. "RGN7RP" "0,1" bitfld.long 0x20 22. "RGN6RP" "0,1" bitfld.long 0x20 21. "RGN5RP" "0,1" bitfld.long 0x20 20. "RGN4RP" "0,1" newline bitfld.long 0x20 19. "RGN3RP" "0,1" bitfld.long 0x20 18. "RGN2RP" "0,1" bitfld.long 0x20 17. "RGN1RP" "0,1" bitfld.long 0x20 16. "RGN0RP" "0,1" newline bitfld.long 0x20 15. "RGN15WP" "0,1" bitfld.long 0x20 14. "RGN14WP" "0,1" bitfld.long 0x20 13. "RGN13WP" "0,1" bitfld.long 0x20 12. "RGN12WP" "0,1" newline bitfld.long 0x20 11. "RGN11WP" "0,1" bitfld.long 0x20 10. "RGN10WP" "0,1" bitfld.long 0x20 9. "RGN9WP" "0,1" bitfld.long 0x20 8. "RGN8WP" "0,1" newline bitfld.long 0x20 7. "RGN7WP" "0,1" bitfld.long 0x20 6. "RGN6WP" "0,1" bitfld.long 0x20 5. "RGN5WP" "0,1" bitfld.long 0x20 4. "RGN4WP" "0,1" newline bitfld.long 0x20 3. "RGN3WP" "0,1" bitfld.long 0x20 2. "RGN2WP" "0,1" bitfld.long 0x20 1. "RGN1WP" "0,1" bitfld.long 0x20 0. "RGN0WP" "0,1" line.long 0x24 "DPTRGNCR9,DRAM Protected Area Region ID Setting Register 9" bitfld.long 0x24 31. "RGN15RP" "0,1" bitfld.long 0x24 30. "RGN14RP" "0,1" bitfld.long 0x24 29. "RGN13RP" "0,1" bitfld.long 0x24 28. "RGN12RP" "0,1" newline bitfld.long 0x24 27. "RGN11RP" "0,1" bitfld.long 0x24 26. "RGN10RP" "0,1" bitfld.long 0x24 25. "RGN9RP" "0,1" bitfld.long 0x24 24. "RGN8RP" "0,1" newline bitfld.long 0x24 23. "RGN7RP" "0,1" bitfld.long 0x24 22. "RGN6RP" "0,1" bitfld.long 0x24 21. "RGN5RP" "0,1" bitfld.long 0x24 20. "RGN4RP" "0,1" newline bitfld.long 0x24 19. "RGN3RP" "0,1" bitfld.long 0x24 18. "RGN2RP" "0,1" bitfld.long 0x24 17. "RGN1RP" "0,1" bitfld.long 0x24 16. "RGN0RP" "0,1" newline bitfld.long 0x24 15. "RGN15WP" "0,1" bitfld.long 0x24 14. "RGN14WP" "0,1" bitfld.long 0x24 13. "RGN13WP" "0,1" bitfld.long 0x24 12. "RGN12WP" "0,1" newline bitfld.long 0x24 11. "RGN11WP" "0,1" bitfld.long 0x24 10. "RGN10WP" "0,1" bitfld.long 0x24 9. "RGN9WP" "0,1" bitfld.long 0x24 8. "RGN8WP" "0,1" newline bitfld.long 0x24 7. "RGN7WP" "0,1" bitfld.long 0x24 6. "RGN6WP" "0,1" bitfld.long 0x24 5. "RGN5WP" "0,1" bitfld.long 0x24 4. "RGN4WP" "0,1" newline bitfld.long 0x24 3. "RGN3WP" "0,1" bitfld.long 0x24 2. "RGN2WP" "0,1" bitfld.long 0x24 1. "RGN1WP" "0,1" bitfld.long 0x24 0. "RGN0WP" "0,1" line.long 0x28 "DPTRGNCR10,DRAM Protected Area Region ID Setting Register 10" bitfld.long 0x28 31. "RGN15RP" "0,1" bitfld.long 0x28 30. "RGN14RP" "0,1" bitfld.long 0x28 29. "RGN13RP" "0,1" bitfld.long 0x28 28. "RGN12RP" "0,1" newline bitfld.long 0x28 27. "RGN11RP" "0,1" bitfld.long 0x28 26. "RGN10RP" "0,1" bitfld.long 0x28 25. "RGN9RP" "0,1" bitfld.long 0x28 24. "RGN8RP" "0,1" newline bitfld.long 0x28 23. "RGN7RP" "0,1" bitfld.long 0x28 22. "RGN6RP" "0,1" bitfld.long 0x28 21. "RGN5RP" "0,1" bitfld.long 0x28 20. "RGN4RP" "0,1" newline bitfld.long 0x28 19. "RGN3RP" "0,1" bitfld.long 0x28 18. "RGN2RP" "0,1" bitfld.long 0x28 17. "RGN1RP" "0,1" bitfld.long 0x28 16. "RGN0RP" "0,1" newline bitfld.long 0x28 15. "RGN15WP" "0,1" bitfld.long 0x28 14. "RGN14WP" "0,1" bitfld.long 0x28 13. "RGN13WP" "0,1" bitfld.long 0x28 12. "RGN12WP" "0,1" newline bitfld.long 0x28 11. "RGN11WP" "0,1" bitfld.long 0x28 10. "RGN10WP" "0,1" bitfld.long 0x28 9. "RGN9WP" "0,1" bitfld.long 0x28 8. "RGN8WP" "0,1" newline bitfld.long 0x28 7. "RGN7WP" "0,1" bitfld.long 0x28 6. "RGN6WP" "0,1" bitfld.long 0x28 5. "RGN5WP" "0,1" bitfld.long 0x28 4. "RGN4WP" "0,1" newline bitfld.long 0x28 3. "RGN3WP" "0,1" bitfld.long 0x28 2. "RGN2WP" "0,1" bitfld.long 0x28 1. "RGN1WP" "0,1" bitfld.long 0x28 0. "RGN0WP" "0,1" line.long 0x2C "DPTRGNCR11,DRAM Protected Area Region ID Setting Register 11" bitfld.long 0x2C 31. "RGN15RP" "0,1" bitfld.long 0x2C 30. "RGN14RP" "0,1" bitfld.long 0x2C 29. "RGN13RP" "0,1" bitfld.long 0x2C 28. "RGN12RP" "0,1" newline bitfld.long 0x2C 27. "RGN11RP" "0,1" bitfld.long 0x2C 26. "RGN10RP" "0,1" bitfld.long 0x2C 25. "RGN9RP" "0,1" bitfld.long 0x2C 24. "RGN8RP" "0,1" newline bitfld.long 0x2C 23. "RGN7RP" "0,1" bitfld.long 0x2C 22. "RGN6RP" "0,1" bitfld.long 0x2C 21. "RGN5RP" "0,1" bitfld.long 0x2C 20. "RGN4RP" "0,1" newline bitfld.long 0x2C 19. "RGN3RP" "0,1" bitfld.long 0x2C 18. "RGN2RP" "0,1" bitfld.long 0x2C 17. "RGN1RP" "0,1" bitfld.long 0x2C 16. "RGN0RP" "0,1" newline bitfld.long 0x2C 15. "RGN15WP" "0,1" bitfld.long 0x2C 14. "RGN14WP" "0,1" bitfld.long 0x2C 13. "RGN13WP" "0,1" bitfld.long 0x2C 12. "RGN12WP" "0,1" newline bitfld.long 0x2C 11. "RGN11WP" "0,1" bitfld.long 0x2C 10. "RGN10WP" "0,1" bitfld.long 0x2C 9. "RGN9WP" "0,1" bitfld.long 0x2C 8. "RGN8WP" "0,1" newline bitfld.long 0x2C 7. "RGN7WP" "0,1" bitfld.long 0x2C 6. "RGN6WP" "0,1" bitfld.long 0x2C 5. "RGN5WP" "0,1" bitfld.long 0x2C 4. "RGN4WP" "0,1" newline bitfld.long 0x2C 3. "RGN3WP" "0,1" bitfld.long 0x2C 2. "RGN2WP" "0,1" bitfld.long 0x2C 1. "RGN1WP" "0,1" bitfld.long 0x2C 0. "RGN0WP" "0,1" line.long 0x30 "DPTRGNCR12,DRAM Protected Area Region ID Setting Register 12" bitfld.long 0x30 31. "RGN15RP" "0,1" bitfld.long 0x30 30. "RGN14RP" "0,1" bitfld.long 0x30 29. "RGN13RP" "0,1" bitfld.long 0x30 28. "RGN12RP" "0,1" newline bitfld.long 0x30 27. "RGN11RP" "0,1" bitfld.long 0x30 26. "RGN10RP" "0,1" bitfld.long 0x30 25. "RGN9RP" "0,1" bitfld.long 0x30 24. "RGN8RP" "0,1" newline bitfld.long 0x30 23. "RGN7RP" "0,1" bitfld.long 0x30 22. "RGN6RP" "0,1" bitfld.long 0x30 21. "RGN5RP" "0,1" bitfld.long 0x30 20. "RGN4RP" "0,1" newline bitfld.long 0x30 19. "RGN3RP" "0,1" bitfld.long 0x30 18. "RGN2RP" "0,1" bitfld.long 0x30 17. "RGN1RP" "0,1" bitfld.long 0x30 16. "RGN0RP" "0,1" newline bitfld.long 0x30 15. "RGN15WP" "0,1" bitfld.long 0x30 14. "RGN14WP" "0,1" bitfld.long 0x30 13. "RGN13WP" "0,1" bitfld.long 0x30 12. "RGN12WP" "0,1" newline bitfld.long 0x30 11. "RGN11WP" "0,1" bitfld.long 0x30 10. "RGN10WP" "0,1" bitfld.long 0x30 9. "RGN9WP" "0,1" bitfld.long 0x30 8. "RGN8WP" "0,1" newline bitfld.long 0x30 7. "RGN7WP" "0,1" bitfld.long 0x30 6. "RGN6WP" "0,1" bitfld.long 0x30 5. "RGN5WP" "0,1" bitfld.long 0x30 4. "RGN4WP" "0,1" newline bitfld.long 0x30 3. "RGN3WP" "0,1" bitfld.long 0x30 2. "RGN2WP" "0,1" bitfld.long 0x30 1. "RGN1WP" "0,1" bitfld.long 0x30 0. "RGN0WP" "0,1" line.long 0x34 "DPTRGNCR13,DRAM Protected Area Region ID Setting Register 13" bitfld.long 0x34 31. "RGN15RP" "0,1" bitfld.long 0x34 30. "RGN14RP" "0,1" bitfld.long 0x34 29. "RGN13RP" "0,1" bitfld.long 0x34 28. "RGN12RP" "0,1" newline bitfld.long 0x34 27. "RGN11RP" "0,1" bitfld.long 0x34 26. "RGN10RP" "0,1" bitfld.long 0x34 25. "RGN9RP" "0,1" bitfld.long 0x34 24. "RGN8RP" "0,1" newline bitfld.long 0x34 23. "RGN7RP" "0,1" bitfld.long 0x34 22. "RGN6RP" "0,1" bitfld.long 0x34 21. "RGN5RP" "0,1" bitfld.long 0x34 20. "RGN4RP" "0,1" newline bitfld.long 0x34 19. "RGN3RP" "0,1" bitfld.long 0x34 18. "RGN2RP" "0,1" bitfld.long 0x34 17. "RGN1RP" "0,1" bitfld.long 0x34 16. "RGN0RP" "0,1" newline bitfld.long 0x34 15. "RGN15WP" "0,1" bitfld.long 0x34 14. "RGN14WP" "0,1" bitfld.long 0x34 13. "RGN13WP" "0,1" bitfld.long 0x34 12. "RGN12WP" "0,1" newline bitfld.long 0x34 11. "RGN11WP" "0,1" bitfld.long 0x34 10. "RGN10WP" "0,1" bitfld.long 0x34 9. "RGN9WP" "0,1" bitfld.long 0x34 8. "RGN8WP" "0,1" newline bitfld.long 0x34 7. "RGN7WP" "0,1" bitfld.long 0x34 6. "RGN6WP" "0,1" bitfld.long 0x34 5. "RGN5WP" "0,1" bitfld.long 0x34 4. "RGN4WP" "0,1" newline bitfld.long 0x34 3. "RGN3WP" "0,1" bitfld.long 0x34 2. "RGN2WP" "0,1" bitfld.long 0x34 1. "RGN1WP" "0,1" bitfld.long 0x34 0. "RGN0WP" "0,1" line.long 0x38 "DPTRGNCR14,DRAM Protected Area Region ID Setting Register 14" bitfld.long 0x38 31. "RGN15RP" "0,1" bitfld.long 0x38 30. "RGN14RP" "0,1" bitfld.long 0x38 29. "RGN13RP" "0,1" bitfld.long 0x38 28. "RGN12RP" "0,1" newline bitfld.long 0x38 27. "RGN11RP" "0,1" bitfld.long 0x38 26. "RGN10RP" "0,1" bitfld.long 0x38 25. "RGN9RP" "0,1" bitfld.long 0x38 24. "RGN8RP" "0,1" newline bitfld.long 0x38 23. "RGN7RP" "0,1" bitfld.long 0x38 22. "RGN6RP" "0,1" bitfld.long 0x38 21. "RGN5RP" "0,1" bitfld.long 0x38 20. "RGN4RP" "0,1" newline bitfld.long 0x38 19. "RGN3RP" "0,1" bitfld.long 0x38 18. "RGN2RP" "0,1" bitfld.long 0x38 17. "RGN1RP" "0,1" bitfld.long 0x38 16. "RGN0RP" "0,1" newline bitfld.long 0x38 15. "RGN15WP" "0,1" bitfld.long 0x38 14. "RGN14WP" "0,1" bitfld.long 0x38 13. "RGN13WP" "0,1" bitfld.long 0x38 12. "RGN12WP" "0,1" newline bitfld.long 0x38 11. "RGN11WP" "0,1" bitfld.long 0x38 10. "RGN10WP" "0,1" bitfld.long 0x38 9. "RGN9WP" "0,1" bitfld.long 0x38 8. "RGN8WP" "0,1" newline bitfld.long 0x38 7. "RGN7WP" "0,1" bitfld.long 0x38 6. "RGN6WP" "0,1" bitfld.long 0x38 5. "RGN5WP" "0,1" bitfld.long 0x38 4. "RGN4WP" "0,1" newline bitfld.long 0x38 3. "RGN3WP" "0,1" bitfld.long 0x38 2. "RGN2WP" "0,1" bitfld.long 0x38 1. "RGN1WP" "0,1" bitfld.long 0x38 0. "RGN0WP" "0,1" line.long 0x3C "DPTRGNCR15,DRAM Protected Area Region ID Setting Register 15" bitfld.long 0x3C 31. "RGN15RP" "0,1" bitfld.long 0x3C 30. "RGN14RP" "0,1" bitfld.long 0x3C 29. "RGN13RP" "0,1" bitfld.long 0x3C 28. "RGN12RP" "0,1" newline bitfld.long 0x3C 27. "RGN11RP" "0,1" bitfld.long 0x3C 26. "RGN10RP" "0,1" bitfld.long 0x3C 25. "RGN9RP" "0,1" bitfld.long 0x3C 24. "RGN8RP" "0,1" newline bitfld.long 0x3C 23. "RGN7RP" "0,1" bitfld.long 0x3C 22. "RGN6RP" "0,1" bitfld.long 0x3C 21. "RGN5RP" "0,1" bitfld.long 0x3C 20. "RGN4RP" "0,1" newline bitfld.long 0x3C 19. "RGN3RP" "0,1" bitfld.long 0x3C 18. "RGN2RP" "0,1" bitfld.long 0x3C 17. "RGN1RP" "0,1" bitfld.long 0x3C 16. "RGN0RP" "0,1" newline bitfld.long 0x3C 15. "RGN15WP" "0,1" bitfld.long 0x3C 14. "RGN14WP" "0,1" bitfld.long 0x3C 13. "RGN13WP" "0,1" bitfld.long 0x3C 12. "RGN12WP" "0,1" newline bitfld.long 0x3C 11. "RGN11WP" "0,1" bitfld.long 0x3C 10. "RGN10WP" "0,1" bitfld.long 0x3C 9. "RGN9WP" "0,1" bitfld.long 0x3C 8. "RGN8WP" "0,1" newline bitfld.long 0x3C 7. "RGN7WP" "0,1" bitfld.long 0x3C 6. "RGN6WP" "0,1" bitfld.long 0x3C 5. "RGN5WP" "0,1" bitfld.long 0x3C 4. "RGN4WP" "0,1" newline bitfld.long 0x3C 3. "RGN3WP" "0,1" bitfld.long 0x3C 2. "RGN2WP" "0,1" bitfld.long 0x3C 1. "RGN1WP" "0,1" bitfld.long 0x3C 0. "RGN0WP" "0,1" line.long 0x40 "DPTRGNCR16,DRAM Protected Area Region ID Setting Register 16" bitfld.long 0x40 31. "RGN15RP" "0,1" bitfld.long 0x40 30. "RGN14RP" "0,1" bitfld.long 0x40 29. "RGN13RP" "0,1" bitfld.long 0x40 28. "RGN12RP" "0,1" newline bitfld.long 0x40 27. "RGN11RP" "0,1" bitfld.long 0x40 26. "RGN10RP" "0,1" bitfld.long 0x40 25. "RGN9RP" "0,1" bitfld.long 0x40 24. "RGN8RP" "0,1" newline bitfld.long 0x40 23. "RGN7RP" "0,1" bitfld.long 0x40 22. "RGN6RP" "0,1" bitfld.long 0x40 21. "RGN5RP" "0,1" bitfld.long 0x40 20. "RGN4RP" "0,1" newline bitfld.long 0x40 19. "RGN3RP" "0,1" bitfld.long 0x40 18. "RGN2RP" "0,1" bitfld.long 0x40 17. "RGN1RP" "0,1" bitfld.long 0x40 16. "RGN0RP" "0,1" newline bitfld.long 0x40 15. "RGN15WP" "0,1" bitfld.long 0x40 14. "RGN14WP" "0,1" bitfld.long 0x40 13. "RGN13WP" "0,1" bitfld.long 0x40 12. "RGN12WP" "0,1" newline bitfld.long 0x40 11. "RGN11WP" "0,1" bitfld.long 0x40 10. "RGN10WP" "0,1" bitfld.long 0x40 9. "RGN9WP" "0,1" bitfld.long 0x40 8. "RGN8WP" "0,1" newline bitfld.long 0x40 7. "RGN7WP" "0,1" bitfld.long 0x40 6. "RGN6WP" "0,1" bitfld.long 0x40 5. "RGN5WP" "0,1" bitfld.long 0x40 4. "RGN4WP" "0,1" newline bitfld.long 0x40 3. "RGN3WP" "0,1" bitfld.long 0x40 2. "RGN2WP" "0,1" bitfld.long 0x40 1. "RGN1WP" "0,1" bitfld.long 0x40 0. "RGN0WP" "0,1" line.long 0x44 "DPTRGNCR17,DRAM Protected Area Region ID Setting Register 17" bitfld.long 0x44 31. "RGN15RP" "0,1" bitfld.long 0x44 30. "RGN14RP" "0,1" bitfld.long 0x44 29. "RGN13RP" "0,1" bitfld.long 0x44 28. "RGN12RP" "0,1" newline bitfld.long 0x44 27. "RGN11RP" "0,1" bitfld.long 0x44 26. "RGN10RP" "0,1" bitfld.long 0x44 25. "RGN9RP" "0,1" bitfld.long 0x44 24. "RGN8RP" "0,1" newline bitfld.long 0x44 23. "RGN7RP" "0,1" bitfld.long 0x44 22. "RGN6RP" "0,1" bitfld.long 0x44 21. "RGN5RP" "0,1" bitfld.long 0x44 20. "RGN4RP" "0,1" newline bitfld.long 0x44 19. "RGN3RP" "0,1" bitfld.long 0x44 18. "RGN2RP" "0,1" bitfld.long 0x44 17. "RGN1RP" "0,1" bitfld.long 0x44 16. "RGN0RP" "0,1" newline bitfld.long 0x44 15. "RGN15WP" "0,1" bitfld.long 0x44 14. "RGN14WP" "0,1" bitfld.long 0x44 13. "RGN13WP" "0,1" bitfld.long 0x44 12. "RGN12WP" "0,1" newline bitfld.long 0x44 11. "RGN11WP" "0,1" bitfld.long 0x44 10. "RGN10WP" "0,1" bitfld.long 0x44 9. "RGN9WP" "0,1" bitfld.long 0x44 8. "RGN8WP" "0,1" newline bitfld.long 0x44 7. "RGN7WP" "0,1" bitfld.long 0x44 6. "RGN6WP" "0,1" bitfld.long 0x44 5. "RGN5WP" "0,1" bitfld.long 0x44 4. "RGN4WP" "0,1" newline bitfld.long 0x44 3. "RGN3WP" "0,1" bitfld.long 0x44 2. "RGN2WP" "0,1" bitfld.long 0x44 1. "RGN1WP" "0,1" bitfld.long 0x44 0. "RGN0WP" "0,1" line.long 0x48 "DPTRGNCR18,DRAM Protected Area Region ID Setting Register 18" bitfld.long 0x48 31. "RGN15RP" "0,1" bitfld.long 0x48 30. "RGN14RP" "0,1" bitfld.long 0x48 29. "RGN13RP" "0,1" bitfld.long 0x48 28. "RGN12RP" "0,1" newline bitfld.long 0x48 27. "RGN11RP" "0,1" bitfld.long 0x48 26. "RGN10RP" "0,1" bitfld.long 0x48 25. "RGN9RP" "0,1" bitfld.long 0x48 24. "RGN8RP" "0,1" newline bitfld.long 0x48 23. "RGN7RP" "0,1" bitfld.long 0x48 22. "RGN6RP" "0,1" bitfld.long 0x48 21. "RGN5RP" "0,1" bitfld.long 0x48 20. "RGN4RP" "0,1" newline bitfld.long 0x48 19. "RGN3RP" "0,1" bitfld.long 0x48 18. "RGN2RP" "0,1" bitfld.long 0x48 17. "RGN1RP" "0,1" bitfld.long 0x48 16. "RGN0RP" "0,1" newline bitfld.long 0x48 15. "RGN15WP" "0,1" bitfld.long 0x48 14. "RGN14WP" "0,1" bitfld.long 0x48 13. "RGN13WP" "0,1" bitfld.long 0x48 12. "RGN12WP" "0,1" newline bitfld.long 0x48 11. "RGN11WP" "0,1" bitfld.long 0x48 10. "RGN10WP" "0,1" bitfld.long 0x48 9. "RGN9WP" "0,1" bitfld.long 0x48 8. "RGN8WP" "0,1" newline bitfld.long 0x48 7. "RGN7WP" "0,1" bitfld.long 0x48 6. "RGN6WP" "0,1" bitfld.long 0x48 5. "RGN5WP" "0,1" bitfld.long 0x48 4. "RGN4WP" "0,1" newline bitfld.long 0x48 3. "RGN3WP" "0,1" bitfld.long 0x48 2. "RGN2WP" "0,1" bitfld.long 0x48 1. "RGN1WP" "0,1" bitfld.long 0x48 0. "RGN0WP" "0,1" line.long 0x4C "DPTRGNCR19,DRAM Protected Area Region ID Setting Register 19" bitfld.long 0x4C 31. "RGN15RP" "0,1" bitfld.long 0x4C 30. "RGN14RP" "0,1" bitfld.long 0x4C 29. "RGN13RP" "0,1" bitfld.long 0x4C 28. "RGN12RP" "0,1" newline bitfld.long 0x4C 27. "RGN11RP" "0,1" bitfld.long 0x4C 26. "RGN10RP" "0,1" bitfld.long 0x4C 25. "RGN9RP" "0,1" bitfld.long 0x4C 24. "RGN8RP" "0,1" newline bitfld.long 0x4C 23. "RGN7RP" "0,1" bitfld.long 0x4C 22. "RGN6RP" "0,1" bitfld.long 0x4C 21. "RGN5RP" "0,1" bitfld.long 0x4C 20. "RGN4RP" "0,1" newline bitfld.long 0x4C 19. "RGN3RP" "0,1" bitfld.long 0x4C 18. "RGN2RP" "0,1" bitfld.long 0x4C 17. "RGN1RP" "0,1" bitfld.long 0x4C 16. "RGN0RP" "0,1" newline bitfld.long 0x4C 15. "RGN15WP" "0,1" bitfld.long 0x4C 14. "RGN14WP" "0,1" bitfld.long 0x4C 13. "RGN13WP" "0,1" bitfld.long 0x4C 12. "RGN12WP" "0,1" newline bitfld.long 0x4C 11. "RGN11WP" "0,1" bitfld.long 0x4C 10. "RGN10WP" "0,1" bitfld.long 0x4C 9. "RGN9WP" "0,1" bitfld.long 0x4C 8. "RGN8WP" "0,1" newline bitfld.long 0x4C 7. "RGN7WP" "0,1" bitfld.long 0x4C 6. "RGN6WP" "0,1" bitfld.long 0x4C 5. "RGN5WP" "0,1" bitfld.long 0x4C 4. "RGN4WP" "0,1" newline bitfld.long 0x4C 3. "RGN3WP" "0,1" bitfld.long 0x4C 2. "RGN2WP" "0,1" bitfld.long 0x4C 1. "RGN1WP" "0,1" bitfld.long 0x4C 0. "RGN0WP" "0,1" line.long 0x50 "DPTRGNCR20,DRAM Protected Area Region ID Setting Register 20" bitfld.long 0x50 31. "RGN15RP" "0,1" bitfld.long 0x50 30. "RGN14RP" "0,1" bitfld.long 0x50 29. "RGN13RP" "0,1" bitfld.long 0x50 28. "RGN12RP" "0,1" newline bitfld.long 0x50 27. "RGN11RP" "0,1" bitfld.long 0x50 26. "RGN10RP" "0,1" bitfld.long 0x50 25. "RGN9RP" "0,1" bitfld.long 0x50 24. "RGN8RP" "0,1" newline bitfld.long 0x50 23. "RGN7RP" "0,1" bitfld.long 0x50 22. "RGN6RP" "0,1" bitfld.long 0x50 21. "RGN5RP" "0,1" bitfld.long 0x50 20. "RGN4RP" "0,1" newline bitfld.long 0x50 19. "RGN3RP" "0,1" bitfld.long 0x50 18. "RGN2RP" "0,1" bitfld.long 0x50 17. "RGN1RP" "0,1" bitfld.long 0x50 16. "RGN0RP" "0,1" newline bitfld.long 0x50 15. "RGN15WP" "0,1" bitfld.long 0x50 14. "RGN14WP" "0,1" bitfld.long 0x50 13. "RGN13WP" "0,1" bitfld.long 0x50 12. "RGN12WP" "0,1" newline bitfld.long 0x50 11. "RGN11WP" "0,1" bitfld.long 0x50 10. "RGN10WP" "0,1" bitfld.long 0x50 9. "RGN9WP" "0,1" bitfld.long 0x50 8. "RGN8WP" "0,1" newline bitfld.long 0x50 7. "RGN7WP" "0,1" bitfld.long 0x50 6. "RGN6WP" "0,1" bitfld.long 0x50 5. "RGN5WP" "0,1" bitfld.long 0x50 4. "RGN4WP" "0,1" newline bitfld.long 0x50 3. "RGN3WP" "0,1" bitfld.long 0x50 2. "RGN2WP" "0,1" bitfld.long 0x50 1. "RGN1WP" "0,1" bitfld.long 0x50 0. "RGN0WP" "0,1" line.long 0x54 "DPTRGNCR21,DRAM Protected Area Region ID Setting Register 21" bitfld.long 0x54 31. "RGN15RP" "0,1" bitfld.long 0x54 30. "RGN14RP" "0,1" bitfld.long 0x54 29. "RGN13RP" "0,1" bitfld.long 0x54 28. "RGN12RP" "0,1" newline bitfld.long 0x54 27. "RGN11RP" "0,1" bitfld.long 0x54 26. "RGN10RP" "0,1" bitfld.long 0x54 25. "RGN9RP" "0,1" bitfld.long 0x54 24. "RGN8RP" "0,1" newline bitfld.long 0x54 23. "RGN7RP" "0,1" bitfld.long 0x54 22. "RGN6RP" "0,1" bitfld.long 0x54 21. "RGN5RP" "0,1" bitfld.long 0x54 20. "RGN4RP" "0,1" newline bitfld.long 0x54 19. "RGN3RP" "0,1" bitfld.long 0x54 18. "RGN2RP" "0,1" bitfld.long 0x54 17. "RGN1RP" "0,1" bitfld.long 0x54 16. "RGN0RP" "0,1" newline bitfld.long 0x54 15. "RGN15WP" "0,1" bitfld.long 0x54 14. "RGN14WP" "0,1" bitfld.long 0x54 13. "RGN13WP" "0,1" bitfld.long 0x54 12. "RGN12WP" "0,1" newline bitfld.long 0x54 11. "RGN11WP" "0,1" bitfld.long 0x54 10. "RGN10WP" "0,1" bitfld.long 0x54 9. "RGN9WP" "0,1" bitfld.long 0x54 8. "RGN8WP" "0,1" newline bitfld.long 0x54 7. "RGN7WP" "0,1" bitfld.long 0x54 6. "RGN6WP" "0,1" bitfld.long 0x54 5. "RGN5WP" "0,1" bitfld.long 0x54 4. "RGN4WP" "0,1" newline bitfld.long 0x54 3. "RGN3WP" "0,1" bitfld.long 0x54 2. "RGN2WP" "0,1" bitfld.long 0x54 1. "RGN1WP" "0,1" bitfld.long 0x54 0. "RGN0WP" "0,1" line.long 0x58 "DPTRGNCR22,DRAM Protected Area Region ID Setting Register 22" bitfld.long 0x58 31. "RGN15RP" "0,1" bitfld.long 0x58 30. "RGN14RP" "0,1" bitfld.long 0x58 29. "RGN13RP" "0,1" bitfld.long 0x58 28. "RGN12RP" "0,1" newline bitfld.long 0x58 27. "RGN11RP" "0,1" bitfld.long 0x58 26. "RGN10RP" "0,1" bitfld.long 0x58 25. "RGN9RP" "0,1" bitfld.long 0x58 24. "RGN8RP" "0,1" newline bitfld.long 0x58 23. "RGN7RP" "0,1" bitfld.long 0x58 22. "RGN6RP" "0,1" bitfld.long 0x58 21. "RGN5RP" "0,1" bitfld.long 0x58 20. "RGN4RP" "0,1" newline bitfld.long 0x58 19. "RGN3RP" "0,1" bitfld.long 0x58 18. "RGN2RP" "0,1" bitfld.long 0x58 17. "RGN1RP" "0,1" bitfld.long 0x58 16. "RGN0RP" "0,1" newline bitfld.long 0x58 15. "RGN15WP" "0,1" bitfld.long 0x58 14. "RGN14WP" "0,1" bitfld.long 0x58 13. "RGN13WP" "0,1" bitfld.long 0x58 12. "RGN12WP" "0,1" newline bitfld.long 0x58 11. "RGN11WP" "0,1" bitfld.long 0x58 10. "RGN10WP" "0,1" bitfld.long 0x58 9. "RGN9WP" "0,1" bitfld.long 0x58 8. "RGN8WP" "0,1" newline bitfld.long 0x58 7. "RGN7WP" "0,1" bitfld.long 0x58 6. "RGN6WP" "0,1" bitfld.long 0x58 5. "RGN5WP" "0,1" bitfld.long 0x58 4. "RGN4WP" "0,1" newline bitfld.long 0x58 3. "RGN3WP" "0,1" bitfld.long 0x58 2. "RGN2WP" "0,1" bitfld.long 0x58 1. "RGN1WP" "0,1" bitfld.long 0x58 0. "RGN0WP" "0,1" line.long 0x5C "DPTRGNCR23,DRAM Protected Area Region ID Setting Register 23" bitfld.long 0x5C 31. "RGN15RP" "0,1" bitfld.long 0x5C 30. "RGN14RP" "0,1" bitfld.long 0x5C 29. "RGN13RP" "0,1" bitfld.long 0x5C 28. "RGN12RP" "0,1" newline bitfld.long 0x5C 27. "RGN11RP" "0,1" bitfld.long 0x5C 26. "RGN10RP" "0,1" bitfld.long 0x5C 25. "RGN9RP" "0,1" bitfld.long 0x5C 24. "RGN8RP" "0,1" newline bitfld.long 0x5C 23. "RGN7RP" "0,1" bitfld.long 0x5C 22. "RGN6RP" "0,1" bitfld.long 0x5C 21. "RGN5RP" "0,1" bitfld.long 0x5C 20. "RGN4RP" "0,1" newline bitfld.long 0x5C 19. "RGN3RP" "0,1" bitfld.long 0x5C 18. "RGN2RP" "0,1" bitfld.long 0x5C 17. "RGN1RP" "0,1" bitfld.long 0x5C 16. "RGN0RP" "0,1" newline bitfld.long 0x5C 15. "RGN15WP" "0,1" bitfld.long 0x5C 14. "RGN14WP" "0,1" bitfld.long 0x5C 13. "RGN13WP" "0,1" bitfld.long 0x5C 12. "RGN12WP" "0,1" newline bitfld.long 0x5C 11. "RGN11WP" "0,1" bitfld.long 0x5C 10. "RGN10WP" "0,1" bitfld.long 0x5C 9. "RGN9WP" "0,1" bitfld.long 0x5C 8. "RGN8WP" "0,1" newline bitfld.long 0x5C 7. "RGN7WP" "0,1" bitfld.long 0x5C 6. "RGN6WP" "0,1" bitfld.long 0x5C 5. "RGN5WP" "0,1" bitfld.long 0x5C 4. "RGN4WP" "0,1" newline bitfld.long 0x5C 3. "RGN3WP" "0,1" bitfld.long 0x5C 2. "RGN2WP" "0,1" bitfld.long 0x5C 1. "RGN1WP" "0,1" bitfld.long 0x5C 0. "RGN0WP" "0,1" line.long 0x60 "DPTRGNCR24,DRAM Protected Area Region ID Setting Register 24" bitfld.long 0x60 31. "RGN15RP" "0,1" bitfld.long 0x60 30. "RGN14RP" "0,1" bitfld.long 0x60 29. "RGN13RP" "0,1" bitfld.long 0x60 28. "RGN12RP" "0,1" newline bitfld.long 0x60 27. "RGN11RP" "0,1" bitfld.long 0x60 26. "RGN10RP" "0,1" bitfld.long 0x60 25. "RGN9RP" "0,1" bitfld.long 0x60 24. "RGN8RP" "0,1" newline bitfld.long 0x60 23. "RGN7RP" "0,1" bitfld.long 0x60 22. "RGN6RP" "0,1" bitfld.long 0x60 21. "RGN5RP" "0,1" bitfld.long 0x60 20. "RGN4RP" "0,1" newline bitfld.long 0x60 19. "RGN3RP" "0,1" bitfld.long 0x60 18. "RGN2RP" "0,1" bitfld.long 0x60 17. "RGN1RP" "0,1" bitfld.long 0x60 16. "RGN0RP" "0,1" newline bitfld.long 0x60 15. "RGN15WP" "0,1" bitfld.long 0x60 14. "RGN14WP" "0,1" bitfld.long 0x60 13. "RGN13WP" "0,1" bitfld.long 0x60 12. "RGN12WP" "0,1" newline bitfld.long 0x60 11. "RGN11WP" "0,1" bitfld.long 0x60 10. "RGN10WP" "0,1" bitfld.long 0x60 9. "RGN9WP" "0,1" bitfld.long 0x60 8. "RGN8WP" "0,1" newline bitfld.long 0x60 7. "RGN7WP" "0,1" bitfld.long 0x60 6. "RGN6WP" "0,1" bitfld.long 0x60 5. "RGN5WP" "0,1" bitfld.long 0x60 4. "RGN4WP" "0,1" newline bitfld.long 0x60 3. "RGN3WP" "0,1" bitfld.long 0x60 2. "RGN2WP" "0,1" bitfld.long 0x60 1. "RGN1WP" "0,1" bitfld.long 0x60 0. "RGN0WP" "0,1" line.long 0x64 "DPTRGNCR25,DRAM Protected Area Region ID Setting Register 25" bitfld.long 0x64 31. "RGN15RP" "0,1" bitfld.long 0x64 30. "RGN14RP" "0,1" bitfld.long 0x64 29. "RGN13RP" "0,1" bitfld.long 0x64 28. "RGN12RP" "0,1" newline bitfld.long 0x64 27. "RGN11RP" "0,1" bitfld.long 0x64 26. "RGN10RP" "0,1" bitfld.long 0x64 25. "RGN9RP" "0,1" bitfld.long 0x64 24. "RGN8RP" "0,1" newline bitfld.long 0x64 23. "RGN7RP" "0,1" bitfld.long 0x64 22. "RGN6RP" "0,1" bitfld.long 0x64 21. "RGN5RP" "0,1" bitfld.long 0x64 20. "RGN4RP" "0,1" newline bitfld.long 0x64 19. "RGN3RP" "0,1" bitfld.long 0x64 18. "RGN2RP" "0,1" bitfld.long 0x64 17. "RGN1RP" "0,1" bitfld.long 0x64 16. "RGN0RP" "0,1" newline bitfld.long 0x64 15. "RGN15WP" "0,1" bitfld.long 0x64 14. "RGN14WP" "0,1" bitfld.long 0x64 13. "RGN13WP" "0,1" bitfld.long 0x64 12. "RGN12WP" "0,1" newline bitfld.long 0x64 11. "RGN11WP" "0,1" bitfld.long 0x64 10. "RGN10WP" "0,1" bitfld.long 0x64 9. "RGN9WP" "0,1" bitfld.long 0x64 8. "RGN8WP" "0,1" newline bitfld.long 0x64 7. "RGN7WP" "0,1" bitfld.long 0x64 6. "RGN6WP" "0,1" bitfld.long 0x64 5. "RGN5WP" "0,1" bitfld.long 0x64 4. "RGN4WP" "0,1" newline bitfld.long 0x64 3. "RGN3WP" "0,1" bitfld.long 0x64 2. "RGN2WP" "0,1" bitfld.long 0x64 1. "RGN1WP" "0,1" bitfld.long 0x64 0. "RGN0WP" "0,1" line.long 0x68 "DPTRGNCR26,DRAM Protected Area Region ID Setting Register 26" bitfld.long 0x68 31. "RGN15RP" "0,1" bitfld.long 0x68 30. "RGN14RP" "0,1" bitfld.long 0x68 29. "RGN13RP" "0,1" bitfld.long 0x68 28. "RGN12RP" "0,1" newline bitfld.long 0x68 27. "RGN11RP" "0,1" bitfld.long 0x68 26. "RGN10RP" "0,1" bitfld.long 0x68 25. "RGN9RP" "0,1" bitfld.long 0x68 24. "RGN8RP" "0,1" newline bitfld.long 0x68 23. "RGN7RP" "0,1" bitfld.long 0x68 22. "RGN6RP" "0,1" bitfld.long 0x68 21. "RGN5RP" "0,1" bitfld.long 0x68 20. "RGN4RP" "0,1" newline bitfld.long 0x68 19. "RGN3RP" "0,1" bitfld.long 0x68 18. "RGN2RP" "0,1" bitfld.long 0x68 17. "RGN1RP" "0,1" bitfld.long 0x68 16. "RGN0RP" "0,1" newline bitfld.long 0x68 15. "RGN15WP" "0,1" bitfld.long 0x68 14. "RGN14WP" "0,1" bitfld.long 0x68 13. "RGN13WP" "0,1" bitfld.long 0x68 12. "RGN12WP" "0,1" newline bitfld.long 0x68 11. "RGN11WP" "0,1" bitfld.long 0x68 10. "RGN10WP" "0,1" bitfld.long 0x68 9. "RGN9WP" "0,1" bitfld.long 0x68 8. "RGN8WP" "0,1" newline bitfld.long 0x68 7. "RGN7WP" "0,1" bitfld.long 0x68 6. "RGN6WP" "0,1" bitfld.long 0x68 5. "RGN5WP" "0,1" bitfld.long 0x68 4. "RGN4WP" "0,1" newline bitfld.long 0x68 3. "RGN3WP" "0,1" bitfld.long 0x68 2. "RGN2WP" "0,1" bitfld.long 0x68 1. "RGN1WP" "0,1" bitfld.long 0x68 0. "RGN0WP" "0,1" line.long 0x6C "DPTRGNCR27,DRAM Protected Area Region ID Setting Register 27" bitfld.long 0x6C 31. "RGN15RP" "0,1" bitfld.long 0x6C 30. "RGN14RP" "0,1" bitfld.long 0x6C 29. "RGN13RP" "0,1" bitfld.long 0x6C 28. "RGN12RP" "0,1" newline bitfld.long 0x6C 27. "RGN11RP" "0,1" bitfld.long 0x6C 26. "RGN10RP" "0,1" bitfld.long 0x6C 25. "RGN9RP" "0,1" bitfld.long 0x6C 24. "RGN8RP" "0,1" newline bitfld.long 0x6C 23. "RGN7RP" "0,1" bitfld.long 0x6C 22. "RGN6RP" "0,1" bitfld.long 0x6C 21. "RGN5RP" "0,1" bitfld.long 0x6C 20. "RGN4RP" "0,1" newline bitfld.long 0x6C 19. "RGN3RP" "0,1" bitfld.long 0x6C 18. "RGN2RP" "0,1" bitfld.long 0x6C 17. "RGN1RP" "0,1" bitfld.long 0x6C 16. "RGN0RP" "0,1" newline bitfld.long 0x6C 15. "RGN15WP" "0,1" bitfld.long 0x6C 14. "RGN14WP" "0,1" bitfld.long 0x6C 13. "RGN13WP" "0,1" bitfld.long 0x6C 12. "RGN12WP" "0,1" newline bitfld.long 0x6C 11. "RGN11WP" "0,1" bitfld.long 0x6C 10. "RGN10WP" "0,1" bitfld.long 0x6C 9. "RGN9WP" "0,1" bitfld.long 0x6C 8. "RGN8WP" "0,1" newline bitfld.long 0x6C 7. "RGN7WP" "0,1" bitfld.long 0x6C 6. "RGN6WP" "0,1" bitfld.long 0x6C 5. "RGN5WP" "0,1" bitfld.long 0x6C 4. "RGN4WP" "0,1" newline bitfld.long 0x6C 3. "RGN3WP" "0,1" bitfld.long 0x6C 2. "RGN2WP" "0,1" bitfld.long 0x6C 1. "RGN1WP" "0,1" bitfld.long 0x6C 0. "RGN0WP" "0,1" line.long 0x70 "DPTRGNCR28,DRAM Protected Area Region ID Setting Register 28" bitfld.long 0x70 31. "RGN15RP" "0,1" bitfld.long 0x70 30. "RGN14RP" "0,1" bitfld.long 0x70 29. "RGN13RP" "0,1" bitfld.long 0x70 28. "RGN12RP" "0,1" newline bitfld.long 0x70 27. "RGN11RP" "0,1" bitfld.long 0x70 26. "RGN10RP" "0,1" bitfld.long 0x70 25. "RGN9RP" "0,1" bitfld.long 0x70 24. "RGN8RP" "0,1" newline bitfld.long 0x70 23. "RGN7RP" "0,1" bitfld.long 0x70 22. "RGN6RP" "0,1" bitfld.long 0x70 21. "RGN5RP" "0,1" bitfld.long 0x70 20. "RGN4RP" "0,1" newline bitfld.long 0x70 19. "RGN3RP" "0,1" bitfld.long 0x70 18. "RGN2RP" "0,1" bitfld.long 0x70 17. "RGN1RP" "0,1" bitfld.long 0x70 16. "RGN0RP" "0,1" newline bitfld.long 0x70 15. "RGN15WP" "0,1" bitfld.long 0x70 14. "RGN14WP" "0,1" bitfld.long 0x70 13. "RGN13WP" "0,1" bitfld.long 0x70 12. "RGN12WP" "0,1" newline bitfld.long 0x70 11. "RGN11WP" "0,1" bitfld.long 0x70 10. "RGN10WP" "0,1" bitfld.long 0x70 9. "RGN9WP" "0,1" bitfld.long 0x70 8. "RGN8WP" "0,1" newline bitfld.long 0x70 7. "RGN7WP" "0,1" bitfld.long 0x70 6. "RGN6WP" "0,1" bitfld.long 0x70 5. "RGN5WP" "0,1" bitfld.long 0x70 4. "RGN4WP" "0,1" newline bitfld.long 0x70 3. "RGN3WP" "0,1" bitfld.long 0x70 2. "RGN2WP" "0,1" bitfld.long 0x70 1. "RGN1WP" "0,1" bitfld.long 0x70 0. "RGN0WP" "0,1" line.long 0x74 "DPTRGNCR29,DRAM Protected Area Region ID Setting Register 29" bitfld.long 0x74 31. "RGN15RP" "0,1" bitfld.long 0x74 30. "RGN14RP" "0,1" bitfld.long 0x74 29. "RGN13RP" "0,1" bitfld.long 0x74 28. "RGN12RP" "0,1" newline bitfld.long 0x74 27. "RGN11RP" "0,1" bitfld.long 0x74 26. "RGN10RP" "0,1" bitfld.long 0x74 25. "RGN9RP" "0,1" bitfld.long 0x74 24. "RGN8RP" "0,1" newline bitfld.long 0x74 23. "RGN7RP" "0,1" bitfld.long 0x74 22. "RGN6RP" "0,1" bitfld.long 0x74 21. "RGN5RP" "0,1" bitfld.long 0x74 20. "RGN4RP" "0,1" newline bitfld.long 0x74 19. "RGN3RP" "0,1" bitfld.long 0x74 18. "RGN2RP" "0,1" bitfld.long 0x74 17. "RGN1RP" "0,1" bitfld.long 0x74 16. "RGN0RP" "0,1" newline bitfld.long 0x74 15. "RGN15WP" "0,1" bitfld.long 0x74 14. "RGN14WP" "0,1" bitfld.long 0x74 13. "RGN13WP" "0,1" bitfld.long 0x74 12. "RGN12WP" "0,1" newline bitfld.long 0x74 11. "RGN11WP" "0,1" bitfld.long 0x74 10. "RGN10WP" "0,1" bitfld.long 0x74 9. "RGN9WP" "0,1" bitfld.long 0x74 8. "RGN8WP" "0,1" newline bitfld.long 0x74 7. "RGN7WP" "0,1" bitfld.long 0x74 6. "RGN6WP" "0,1" bitfld.long 0x74 5. "RGN5WP" "0,1" bitfld.long 0x74 4. "RGN4WP" "0,1" newline bitfld.long 0x74 3. "RGN3WP" "0,1" bitfld.long 0x74 2. "RGN2WP" "0,1" bitfld.long 0x74 1. "RGN1WP" "0,1" bitfld.long 0x74 0. "RGN0WP" "0,1" line.long 0x78 "DPTRGNCR30,DRAM Protected Area Region ID Setting Register 30" bitfld.long 0x78 31. "RGN15RP" "0,1" bitfld.long 0x78 30. "RGN14RP" "0,1" bitfld.long 0x78 29. "RGN13RP" "0,1" bitfld.long 0x78 28. "RGN12RP" "0,1" newline bitfld.long 0x78 27. "RGN11RP" "0,1" bitfld.long 0x78 26. "RGN10RP" "0,1" bitfld.long 0x78 25. "RGN9RP" "0,1" bitfld.long 0x78 24. "RGN8RP" "0,1" newline bitfld.long 0x78 23. "RGN7RP" "0,1" bitfld.long 0x78 22. "RGN6RP" "0,1" bitfld.long 0x78 21. "RGN5RP" "0,1" bitfld.long 0x78 20. "RGN4RP" "0,1" newline bitfld.long 0x78 19. "RGN3RP" "0,1" bitfld.long 0x78 18. "RGN2RP" "0,1" bitfld.long 0x78 17. "RGN1RP" "0,1" bitfld.long 0x78 16. "RGN0RP" "0,1" newline bitfld.long 0x78 15. "RGN15WP" "0,1" bitfld.long 0x78 14. "RGN14WP" "0,1" bitfld.long 0x78 13. "RGN13WP" "0,1" bitfld.long 0x78 12. "RGN12WP" "0,1" newline bitfld.long 0x78 11. "RGN11WP" "0,1" bitfld.long 0x78 10. "RGN10WP" "0,1" bitfld.long 0x78 9. "RGN9WP" "0,1" bitfld.long 0x78 8. "RGN8WP" "0,1" newline bitfld.long 0x78 7. "RGN7WP" "0,1" bitfld.long 0x78 6. "RGN6WP" "0,1" bitfld.long 0x78 5. "RGN5WP" "0,1" bitfld.long 0x78 4. "RGN4WP" "0,1" newline bitfld.long 0x78 3. "RGN3WP" "0,1" bitfld.long 0x78 2. "RGN2WP" "0,1" bitfld.long 0x78 1. "RGN1WP" "0,1" bitfld.long 0x78 0. "RGN0WP" "0,1" line.long 0x7C "DPTRGNCR31,DRAM Protected Area Region ID Setting Register 31" bitfld.long 0x7C 31. "RGN15RP" "0,1" bitfld.long 0x7C 30. "RGN14RP" "0,1" bitfld.long 0x7C 29. "RGN13RP" "0,1" bitfld.long 0x7C 28. "RGN12RP" "0,1" newline bitfld.long 0x7C 27. "RGN11RP" "0,1" bitfld.long 0x7C 26. "RGN10RP" "0,1" bitfld.long 0x7C 25. "RGN9RP" "0,1" bitfld.long 0x7C 24. "RGN8RP" "0,1" newline bitfld.long 0x7C 23. "RGN7RP" "0,1" bitfld.long 0x7C 22. "RGN6RP" "0,1" bitfld.long 0x7C 21. "RGN5RP" "0,1" bitfld.long 0x7C 20. "RGN4RP" "0,1" newline bitfld.long 0x7C 19. "RGN3RP" "0,1" bitfld.long 0x7C 18. "RGN2RP" "0,1" bitfld.long 0x7C 17. "RGN1RP" "0,1" bitfld.long 0x7C 16. "RGN0RP" "0,1" newline bitfld.long 0x7C 15. "RGN15WP" "0,1" bitfld.long 0x7C 14. "RGN14WP" "0,1" bitfld.long 0x7C 13. "RGN13WP" "0,1" bitfld.long 0x7C 12. "RGN12WP" "0,1" newline bitfld.long 0x7C 11. "RGN11WP" "0,1" bitfld.long 0x7C 10. "RGN10WP" "0,1" bitfld.long 0x7C 9. "RGN9WP" "0,1" bitfld.long 0x7C 8. "RGN8WP" "0,1" newline bitfld.long 0x7C 7. "RGN7WP" "0,1" bitfld.long 0x7C 6. "RGN6WP" "0,1" bitfld.long 0x7C 5. "RGN5WP" "0,1" bitfld.long 0x7C 4. "RGN4WP" "0,1" newline bitfld.long 0x7C 3. "RGN3WP" "0,1" bitfld.long 0x7C 2. "RGN2WP" "0,1" bitfld.long 0x7C 1. "RGN1WP" "0,1" bitfld.long 0x7C 0. "RGN0WP" "0,1" line.long 0x80 "DPTRGNCR32,DRAM Protected Area Region ID Setting Register 32" bitfld.long 0x80 31. "RGN15RP" "0,1" bitfld.long 0x80 30. "RGN14RP" "0,1" bitfld.long 0x80 29. "RGN13RP" "0,1" bitfld.long 0x80 28. "RGN12RP" "0,1" newline bitfld.long 0x80 27. "RGN11RP" "0,1" bitfld.long 0x80 26. "RGN10RP" "0,1" bitfld.long 0x80 25. "RGN9RP" "0,1" bitfld.long 0x80 24. "RGN8RP" "0,1" newline bitfld.long 0x80 23. "RGN7RP" "0,1" bitfld.long 0x80 22. "RGN6RP" "0,1" bitfld.long 0x80 21. "RGN5RP" "0,1" bitfld.long 0x80 20. "RGN4RP" "0,1" newline bitfld.long 0x80 19. "RGN3RP" "0,1" bitfld.long 0x80 18. "RGN2RP" "0,1" bitfld.long 0x80 17. "RGN1RP" "0,1" bitfld.long 0x80 16. "RGN0RP" "0,1" newline bitfld.long 0x80 15. "RGN15WP" "0,1" bitfld.long 0x80 14. "RGN14WP" "0,1" bitfld.long 0x80 13. "RGN13WP" "0,1" bitfld.long 0x80 12. "RGN12WP" "0,1" newline bitfld.long 0x80 11. "RGN11WP" "0,1" bitfld.long 0x80 10. "RGN10WP" "0,1" bitfld.long 0x80 9. "RGN9WP" "0,1" bitfld.long 0x80 8. "RGN8WP" "0,1" newline bitfld.long 0x80 7. "RGN7WP" "0,1" bitfld.long 0x80 6. "RGN6WP" "0,1" bitfld.long 0x80 5. "RGN5WP" "0,1" bitfld.long 0x80 4. "RGN4WP" "0,1" newline bitfld.long 0x80 3. "RGN3WP" "0,1" bitfld.long 0x80 2. "RGN2WP" "0,1" bitfld.long 0x80 1. "RGN1WP" "0,1" bitfld.long 0x80 0. "RGN0WP" "0,1" line.long 0x84 "DPTRGNCR33,DRAM Protected Area Region ID Setting Register 33" bitfld.long 0x84 31. "RGN15RP" "0,1" bitfld.long 0x84 30. "RGN14RP" "0,1" bitfld.long 0x84 29. "RGN13RP" "0,1" bitfld.long 0x84 28. "RGN12RP" "0,1" newline bitfld.long 0x84 27. "RGN11RP" "0,1" bitfld.long 0x84 26. "RGN10RP" "0,1" bitfld.long 0x84 25. "RGN9RP" "0,1" bitfld.long 0x84 24. "RGN8RP" "0,1" newline bitfld.long 0x84 23. "RGN7RP" "0,1" bitfld.long 0x84 22. "RGN6RP" "0,1" bitfld.long 0x84 21. "RGN5RP" "0,1" bitfld.long 0x84 20. "RGN4RP" "0,1" newline bitfld.long 0x84 19. "RGN3RP" "0,1" bitfld.long 0x84 18. "RGN2RP" "0,1" bitfld.long 0x84 17. "RGN1RP" "0,1" bitfld.long 0x84 16. "RGN0RP" "0,1" newline bitfld.long 0x84 15. "RGN15WP" "0,1" bitfld.long 0x84 14. "RGN14WP" "0,1" bitfld.long 0x84 13. "RGN13WP" "0,1" bitfld.long 0x84 12. "RGN12WP" "0,1" newline bitfld.long 0x84 11. "RGN11WP" "0,1" bitfld.long 0x84 10. "RGN10WP" "0,1" bitfld.long 0x84 9. "RGN9WP" "0,1" bitfld.long 0x84 8. "RGN8WP" "0,1" newline bitfld.long 0x84 7. "RGN7WP" "0,1" bitfld.long 0x84 6. "RGN6WP" "0,1" bitfld.long 0x84 5. "RGN5WP" "0,1" bitfld.long 0x84 4. "RGN4WP" "0,1" newline bitfld.long 0x84 3. "RGN3WP" "0,1" bitfld.long 0x84 2. "RGN2WP" "0,1" bitfld.long 0x84 1. "RGN1WP" "0,1" bitfld.long 0x84 0. "RGN0WP" "0,1" line.long 0x88 "DPTRGNCR34,DRAM Protected Area Region ID Setting Register 34" bitfld.long 0x88 31. "RGN15RP" "0,1" bitfld.long 0x88 30. "RGN14RP" "0,1" bitfld.long 0x88 29. "RGN13RP" "0,1" bitfld.long 0x88 28. "RGN12RP" "0,1" newline bitfld.long 0x88 27. "RGN11RP" "0,1" bitfld.long 0x88 26. "RGN10RP" "0,1" bitfld.long 0x88 25. "RGN9RP" "0,1" bitfld.long 0x88 24. "RGN8RP" "0,1" newline bitfld.long 0x88 23. "RGN7RP" "0,1" bitfld.long 0x88 22. "RGN6RP" "0,1" bitfld.long 0x88 21. "RGN5RP" "0,1" bitfld.long 0x88 20. "RGN4RP" "0,1" newline bitfld.long 0x88 19. "RGN3RP" "0,1" bitfld.long 0x88 18. "RGN2RP" "0,1" bitfld.long 0x88 17. "RGN1RP" "0,1" bitfld.long 0x88 16. "RGN0RP" "0,1" newline bitfld.long 0x88 15. "RGN15WP" "0,1" bitfld.long 0x88 14. "RGN14WP" "0,1" bitfld.long 0x88 13. "RGN13WP" "0,1" bitfld.long 0x88 12. "RGN12WP" "0,1" newline bitfld.long 0x88 11. "RGN11WP" "0,1" bitfld.long 0x88 10. "RGN10WP" "0,1" bitfld.long 0x88 9. "RGN9WP" "0,1" bitfld.long 0x88 8. "RGN8WP" "0,1" newline bitfld.long 0x88 7. "RGN7WP" "0,1" bitfld.long 0x88 6. "RGN6WP" "0,1" bitfld.long 0x88 5. "RGN5WP" "0,1" bitfld.long 0x88 4. "RGN4WP" "0,1" newline bitfld.long 0x88 3. "RGN3WP" "0,1" bitfld.long 0x88 2. "RGN2WP" "0,1" bitfld.long 0x88 1. "RGN1WP" "0,1" bitfld.long 0x88 0. "RGN0WP" "0,1" line.long 0x8C "DPTRGNCR35,DRAM Protected Area Region ID Setting Register 35" bitfld.long 0x8C 31. "RGN15RP" "0,1" bitfld.long 0x8C 30. "RGN14RP" "0,1" bitfld.long 0x8C 29. "RGN13RP" "0,1" bitfld.long 0x8C 28. "RGN12RP" "0,1" newline bitfld.long 0x8C 27. "RGN11RP" "0,1" bitfld.long 0x8C 26. "RGN10RP" "0,1" bitfld.long 0x8C 25. "RGN9RP" "0,1" bitfld.long 0x8C 24. "RGN8RP" "0,1" newline bitfld.long 0x8C 23. "RGN7RP" "0,1" bitfld.long 0x8C 22. "RGN6RP" "0,1" bitfld.long 0x8C 21. "RGN5RP" "0,1" bitfld.long 0x8C 20. "RGN4RP" "0,1" newline bitfld.long 0x8C 19. "RGN3RP" "0,1" bitfld.long 0x8C 18. "RGN2RP" "0,1" bitfld.long 0x8C 17. "RGN1RP" "0,1" bitfld.long 0x8C 16. "RGN0RP" "0,1" newline bitfld.long 0x8C 15. "RGN15WP" "0,1" bitfld.long 0x8C 14. "RGN14WP" "0,1" bitfld.long 0x8C 13. "RGN13WP" "0,1" bitfld.long 0x8C 12. "RGN12WP" "0,1" newline bitfld.long 0x8C 11. "RGN11WP" "0,1" bitfld.long 0x8C 10. "RGN10WP" "0,1" bitfld.long 0x8C 9. "RGN9WP" "0,1" bitfld.long 0x8C 8. "RGN8WP" "0,1" newline bitfld.long 0x8C 7. "RGN7WP" "0,1" bitfld.long 0x8C 6. "RGN6WP" "0,1" bitfld.long 0x8C 5. "RGN5WP" "0,1" bitfld.long 0x8C 4. "RGN4WP" "0,1" newline bitfld.long 0x8C 3. "RGN3WP" "0,1" bitfld.long 0x8C 2. "RGN2WP" "0,1" bitfld.long 0x8C 1. "RGN1WP" "0,1" bitfld.long 0x8C 0. "RGN0WP" "0,1" line.long 0x90 "DPTRGNCR36,DRAM Protected Area Region ID Setting Register 36" bitfld.long 0x90 31. "RGN15RP" "0,1" bitfld.long 0x90 30. "RGN14RP" "0,1" bitfld.long 0x90 29. "RGN13RP" "0,1" bitfld.long 0x90 28. "RGN12RP" "0,1" newline bitfld.long 0x90 27. "RGN11RP" "0,1" bitfld.long 0x90 26. "RGN10RP" "0,1" bitfld.long 0x90 25. "RGN9RP" "0,1" bitfld.long 0x90 24. "RGN8RP" "0,1" newline bitfld.long 0x90 23. "RGN7RP" "0,1" bitfld.long 0x90 22. "RGN6RP" "0,1" bitfld.long 0x90 21. "RGN5RP" "0,1" bitfld.long 0x90 20. "RGN4RP" "0,1" newline bitfld.long 0x90 19. "RGN3RP" "0,1" bitfld.long 0x90 18. "RGN2RP" "0,1" bitfld.long 0x90 17. "RGN1RP" "0,1" bitfld.long 0x90 16. "RGN0RP" "0,1" newline bitfld.long 0x90 15. "RGN15WP" "0,1" bitfld.long 0x90 14. "RGN14WP" "0,1" bitfld.long 0x90 13. "RGN13WP" "0,1" bitfld.long 0x90 12. "RGN12WP" "0,1" newline bitfld.long 0x90 11. "RGN11WP" "0,1" bitfld.long 0x90 10. "RGN10WP" "0,1" bitfld.long 0x90 9. "RGN9WP" "0,1" bitfld.long 0x90 8. "RGN8WP" "0,1" newline bitfld.long 0x90 7. "RGN7WP" "0,1" bitfld.long 0x90 6. "RGN6WP" "0,1" bitfld.long 0x90 5. "RGN5WP" "0,1" bitfld.long 0x90 4. "RGN4WP" "0,1" newline bitfld.long 0x90 3. "RGN3WP" "0,1" bitfld.long 0x90 2. "RGN2WP" "0,1" bitfld.long 0x90 1. "RGN1WP" "0,1" bitfld.long 0x90 0. "RGN0WP" "0,1" line.long 0x94 "DPTRGNCR37,DRAM Protected Area Region ID Setting Register 37" bitfld.long 0x94 31. "RGN15RP" "0,1" bitfld.long 0x94 30. "RGN14RP" "0,1" bitfld.long 0x94 29. "RGN13RP" "0,1" bitfld.long 0x94 28. "RGN12RP" "0,1" newline bitfld.long 0x94 27. "RGN11RP" "0,1" bitfld.long 0x94 26. "RGN10RP" "0,1" bitfld.long 0x94 25. "RGN9RP" "0,1" bitfld.long 0x94 24. "RGN8RP" "0,1" newline bitfld.long 0x94 23. "RGN7RP" "0,1" bitfld.long 0x94 22. "RGN6RP" "0,1" bitfld.long 0x94 21. "RGN5RP" "0,1" bitfld.long 0x94 20. "RGN4RP" "0,1" newline bitfld.long 0x94 19. "RGN3RP" "0,1" bitfld.long 0x94 18. "RGN2RP" "0,1" bitfld.long 0x94 17. "RGN1RP" "0,1" bitfld.long 0x94 16. "RGN0RP" "0,1" newline bitfld.long 0x94 15. "RGN15WP" "0,1" bitfld.long 0x94 14. "RGN14WP" "0,1" bitfld.long 0x94 13. "RGN13WP" "0,1" bitfld.long 0x94 12. "RGN12WP" "0,1" newline bitfld.long 0x94 11. "RGN11WP" "0,1" bitfld.long 0x94 10. "RGN10WP" "0,1" bitfld.long 0x94 9. "RGN9WP" "0,1" bitfld.long 0x94 8. "RGN8WP" "0,1" newline bitfld.long 0x94 7. "RGN7WP" "0,1" bitfld.long 0x94 6. "RGN6WP" "0,1" bitfld.long 0x94 5. "RGN5WP" "0,1" bitfld.long 0x94 4. "RGN4WP" "0,1" newline bitfld.long 0x94 3. "RGN3WP" "0,1" bitfld.long 0x94 2. "RGN2WP" "0,1" bitfld.long 0x94 1. "RGN1WP" "0,1" bitfld.long 0x94 0. "RGN0WP" "0,1" line.long 0x98 "DPTRGNCR38,DRAM Protected Area Region ID Setting Register 38" bitfld.long 0x98 31. "RGN15RP" "0,1" bitfld.long 0x98 30. "RGN14RP" "0,1" bitfld.long 0x98 29. "RGN13RP" "0,1" bitfld.long 0x98 28. "RGN12RP" "0,1" newline bitfld.long 0x98 27. "RGN11RP" "0,1" bitfld.long 0x98 26. "RGN10RP" "0,1" bitfld.long 0x98 25. "RGN9RP" "0,1" bitfld.long 0x98 24. "RGN8RP" "0,1" newline bitfld.long 0x98 23. "RGN7RP" "0,1" bitfld.long 0x98 22. "RGN6RP" "0,1" bitfld.long 0x98 21. "RGN5RP" "0,1" bitfld.long 0x98 20. "RGN4RP" "0,1" newline bitfld.long 0x98 19. "RGN3RP" "0,1" bitfld.long 0x98 18. "RGN2RP" "0,1" bitfld.long 0x98 17. "RGN1RP" "0,1" bitfld.long 0x98 16. "RGN0RP" "0,1" newline bitfld.long 0x98 15. "RGN15WP" "0,1" bitfld.long 0x98 14. "RGN14WP" "0,1" bitfld.long 0x98 13. "RGN13WP" "0,1" bitfld.long 0x98 12. "RGN12WP" "0,1" newline bitfld.long 0x98 11. "RGN11WP" "0,1" bitfld.long 0x98 10. "RGN10WP" "0,1" bitfld.long 0x98 9. "RGN9WP" "0,1" bitfld.long 0x98 8. "RGN8WP" "0,1" newline bitfld.long 0x98 7. "RGN7WP" "0,1" bitfld.long 0x98 6. "RGN6WP" "0,1" bitfld.long 0x98 5. "RGN5WP" "0,1" bitfld.long 0x98 4. "RGN4WP" "0,1" newline bitfld.long 0x98 3. "RGN3WP" "0,1" bitfld.long 0x98 2. "RGN2WP" "0,1" bitfld.long 0x98 1. "RGN1WP" "0,1" bitfld.long 0x98 0. "RGN0WP" "0,1" line.long 0x9C "DPTRGNCR39,DRAM Protected Area Region ID Setting Register 39" bitfld.long 0x9C 31. "RGN15RP" "0,1" bitfld.long 0x9C 30. "RGN14RP" "0,1" bitfld.long 0x9C 29. "RGN13RP" "0,1" bitfld.long 0x9C 28. "RGN12RP" "0,1" newline bitfld.long 0x9C 27. "RGN11RP" "0,1" bitfld.long 0x9C 26. "RGN10RP" "0,1" bitfld.long 0x9C 25. "RGN9RP" "0,1" bitfld.long 0x9C 24. "RGN8RP" "0,1" newline bitfld.long 0x9C 23. "RGN7RP" "0,1" bitfld.long 0x9C 22. "RGN6RP" "0,1" bitfld.long 0x9C 21. "RGN5RP" "0,1" bitfld.long 0x9C 20. "RGN4RP" "0,1" newline bitfld.long 0x9C 19. "RGN3RP" "0,1" bitfld.long 0x9C 18. "RGN2RP" "0,1" bitfld.long 0x9C 17. "RGN1RP" "0,1" bitfld.long 0x9C 16. "RGN0RP" "0,1" newline bitfld.long 0x9C 15. "RGN15WP" "0,1" bitfld.long 0x9C 14. "RGN14WP" "0,1" bitfld.long 0x9C 13. "RGN13WP" "0,1" bitfld.long 0x9C 12. "RGN12WP" "0,1" newline bitfld.long 0x9C 11. "RGN11WP" "0,1" bitfld.long 0x9C 10. "RGN10WP" "0,1" bitfld.long 0x9C 9. "RGN9WP" "0,1" bitfld.long 0x9C 8. "RGN8WP" "0,1" newline bitfld.long 0x9C 7. "RGN7WP" "0,1" bitfld.long 0x9C 6. "RGN6WP" "0,1" bitfld.long 0x9C 5. "RGN5WP" "0,1" bitfld.long 0x9C 4. "RGN4WP" "0,1" newline bitfld.long 0x9C 3. "RGN3WP" "0,1" bitfld.long 0x9C 2. "RGN2WP" "0,1" bitfld.long 0x9C 1. "RGN1WP" "0,1" bitfld.long 0x9C 0. "RGN0WP" "0,1" line.long 0xA0 "DPTRGNCR40,DRAM Protected Area Region ID Setting Register 40" bitfld.long 0xA0 31. "RGN15RP" "0,1" bitfld.long 0xA0 30. "RGN14RP" "0,1" bitfld.long 0xA0 29. "RGN13RP" "0,1" bitfld.long 0xA0 28. "RGN12RP" "0,1" newline bitfld.long 0xA0 27. "RGN11RP" "0,1" bitfld.long 0xA0 26. "RGN10RP" "0,1" bitfld.long 0xA0 25. "RGN9RP" "0,1" bitfld.long 0xA0 24. "RGN8RP" "0,1" newline bitfld.long 0xA0 23. "RGN7RP" "0,1" bitfld.long 0xA0 22. "RGN6RP" "0,1" bitfld.long 0xA0 21. "RGN5RP" "0,1" bitfld.long 0xA0 20. "RGN4RP" "0,1" newline bitfld.long 0xA0 19. "RGN3RP" "0,1" bitfld.long 0xA0 18. "RGN2RP" "0,1" bitfld.long 0xA0 17. "RGN1RP" "0,1" bitfld.long 0xA0 16. "RGN0RP" "0,1" newline bitfld.long 0xA0 15. "RGN15WP" "0,1" bitfld.long 0xA0 14. "RGN14WP" "0,1" bitfld.long 0xA0 13. "RGN13WP" "0,1" bitfld.long 0xA0 12. "RGN12WP" "0,1" newline bitfld.long 0xA0 11. "RGN11WP" "0,1" bitfld.long 0xA0 10. "RGN10WP" "0,1" bitfld.long 0xA0 9. "RGN9WP" "0,1" bitfld.long 0xA0 8. "RGN8WP" "0,1" newline bitfld.long 0xA0 7. "RGN7WP" "0,1" bitfld.long 0xA0 6. "RGN6WP" "0,1" bitfld.long 0xA0 5. "RGN5WP" "0,1" bitfld.long 0xA0 4. "RGN4WP" "0,1" newline bitfld.long 0xA0 3. "RGN3WP" "0,1" bitfld.long 0xA0 2. "RGN2WP" "0,1" bitfld.long 0xA0 1. "RGN1WP" "0,1" bitfld.long 0xA0 0. "RGN0WP" "0,1" line.long 0xA4 "DPTRGNCR41,DRAM Protected Area Region ID Setting Register 41" bitfld.long 0xA4 31. "RGN15RP" "0,1" bitfld.long 0xA4 30. "RGN14RP" "0,1" bitfld.long 0xA4 29. "RGN13RP" "0,1" bitfld.long 0xA4 28. "RGN12RP" "0,1" newline bitfld.long 0xA4 27. "RGN11RP" "0,1" bitfld.long 0xA4 26. "RGN10RP" "0,1" bitfld.long 0xA4 25. "RGN9RP" "0,1" bitfld.long 0xA4 24. "RGN8RP" "0,1" newline bitfld.long 0xA4 23. "RGN7RP" "0,1" bitfld.long 0xA4 22. "RGN6RP" "0,1" bitfld.long 0xA4 21. "RGN5RP" "0,1" bitfld.long 0xA4 20. "RGN4RP" "0,1" newline bitfld.long 0xA4 19. "RGN3RP" "0,1" bitfld.long 0xA4 18. "RGN2RP" "0,1" bitfld.long 0xA4 17. "RGN1RP" "0,1" bitfld.long 0xA4 16. "RGN0RP" "0,1" newline bitfld.long 0xA4 15. "RGN15WP" "0,1" bitfld.long 0xA4 14. "RGN14WP" "0,1" bitfld.long 0xA4 13. "RGN13WP" "0,1" bitfld.long 0xA4 12. "RGN12WP" "0,1" newline bitfld.long 0xA4 11. "RGN11WP" "0,1" bitfld.long 0xA4 10. "RGN10WP" "0,1" bitfld.long 0xA4 9. "RGN9WP" "0,1" bitfld.long 0xA4 8. "RGN8WP" "0,1" newline bitfld.long 0xA4 7. "RGN7WP" "0,1" bitfld.long 0xA4 6. "RGN6WP" "0,1" bitfld.long 0xA4 5. "RGN5WP" "0,1" bitfld.long 0xA4 4. "RGN4WP" "0,1" newline bitfld.long 0xA4 3. "RGN3WP" "0,1" bitfld.long 0xA4 2. "RGN2WP" "0,1" bitfld.long 0xA4 1. "RGN1WP" "0,1" bitfld.long 0xA4 0. "RGN0WP" "0,1" line.long 0xA8 "DPTRGNCR42,DRAM Protected Area Region ID Setting Register 42" bitfld.long 0xA8 31. "RGN15RP" "0,1" bitfld.long 0xA8 30. "RGN14RP" "0,1" bitfld.long 0xA8 29. "RGN13RP" "0,1" bitfld.long 0xA8 28. "RGN12RP" "0,1" newline bitfld.long 0xA8 27. "RGN11RP" "0,1" bitfld.long 0xA8 26. "RGN10RP" "0,1" bitfld.long 0xA8 25. "RGN9RP" "0,1" bitfld.long 0xA8 24. "RGN8RP" "0,1" newline bitfld.long 0xA8 23. "RGN7RP" "0,1" bitfld.long 0xA8 22. "RGN6RP" "0,1" bitfld.long 0xA8 21. "RGN5RP" "0,1" bitfld.long 0xA8 20. "RGN4RP" "0,1" newline bitfld.long 0xA8 19. "RGN3RP" "0,1" bitfld.long 0xA8 18. "RGN2RP" "0,1" bitfld.long 0xA8 17. "RGN1RP" "0,1" bitfld.long 0xA8 16. "RGN0RP" "0,1" newline bitfld.long 0xA8 15. "RGN15WP" "0,1" bitfld.long 0xA8 14. "RGN14WP" "0,1" bitfld.long 0xA8 13. "RGN13WP" "0,1" bitfld.long 0xA8 12. "RGN12WP" "0,1" newline bitfld.long 0xA8 11. "RGN11WP" "0,1" bitfld.long 0xA8 10. "RGN10WP" "0,1" bitfld.long 0xA8 9. "RGN9WP" "0,1" bitfld.long 0xA8 8. "RGN8WP" "0,1" newline bitfld.long 0xA8 7. "RGN7WP" "0,1" bitfld.long 0xA8 6. "RGN6WP" "0,1" bitfld.long 0xA8 5. "RGN5WP" "0,1" bitfld.long 0xA8 4. "RGN4WP" "0,1" newline bitfld.long 0xA8 3. "RGN3WP" "0,1" bitfld.long 0xA8 2. "RGN2WP" "0,1" bitfld.long 0xA8 1. "RGN1WP" "0,1" bitfld.long 0xA8 0. "RGN0WP" "0,1" line.long 0xAC "DPTRGNCR43,DRAM Protected Area Region ID Setting Register 43" bitfld.long 0xAC 31. "RGN15RP" "0,1" bitfld.long 0xAC 30. "RGN14RP" "0,1" bitfld.long 0xAC 29. "RGN13RP" "0,1" bitfld.long 0xAC 28. "RGN12RP" "0,1" newline bitfld.long 0xAC 27. "RGN11RP" "0,1" bitfld.long 0xAC 26. "RGN10RP" "0,1" bitfld.long 0xAC 25. "RGN9RP" "0,1" bitfld.long 0xAC 24. "RGN8RP" "0,1" newline bitfld.long 0xAC 23. "RGN7RP" "0,1" bitfld.long 0xAC 22. "RGN6RP" "0,1" bitfld.long 0xAC 21. "RGN5RP" "0,1" bitfld.long 0xAC 20. "RGN4RP" "0,1" newline bitfld.long 0xAC 19. "RGN3RP" "0,1" bitfld.long 0xAC 18. "RGN2RP" "0,1" bitfld.long 0xAC 17. "RGN1RP" "0,1" bitfld.long 0xAC 16. "RGN0RP" "0,1" newline bitfld.long 0xAC 15. "RGN15WP" "0,1" bitfld.long 0xAC 14. "RGN14WP" "0,1" bitfld.long 0xAC 13. "RGN13WP" "0,1" bitfld.long 0xAC 12. "RGN12WP" "0,1" newline bitfld.long 0xAC 11. "RGN11WP" "0,1" bitfld.long 0xAC 10. "RGN10WP" "0,1" bitfld.long 0xAC 9. "RGN9WP" "0,1" bitfld.long 0xAC 8. "RGN8WP" "0,1" newline bitfld.long 0xAC 7. "RGN7WP" "0,1" bitfld.long 0xAC 6. "RGN6WP" "0,1" bitfld.long 0xAC 5. "RGN5WP" "0,1" bitfld.long 0xAC 4. "RGN4WP" "0,1" newline bitfld.long 0xAC 3. "RGN3WP" "0,1" bitfld.long 0xAC 2. "RGN2WP" "0,1" bitfld.long 0xAC 1. "RGN1WP" "0,1" bitfld.long 0xAC 0. "RGN0WP" "0,1" line.long 0xB0 "DPTRGNCR44,DRAM Protected Area Region ID Setting Register 44" bitfld.long 0xB0 31. "RGN15RP" "0,1" bitfld.long 0xB0 30. "RGN14RP" "0,1" bitfld.long 0xB0 29. "RGN13RP" "0,1" bitfld.long 0xB0 28. "RGN12RP" "0,1" newline bitfld.long 0xB0 27. "RGN11RP" "0,1" bitfld.long 0xB0 26. "RGN10RP" "0,1" bitfld.long 0xB0 25. "RGN9RP" "0,1" bitfld.long 0xB0 24. "RGN8RP" "0,1" newline bitfld.long 0xB0 23. "RGN7RP" "0,1" bitfld.long 0xB0 22. "RGN6RP" "0,1" bitfld.long 0xB0 21. "RGN5RP" "0,1" bitfld.long 0xB0 20. "RGN4RP" "0,1" newline bitfld.long 0xB0 19. "RGN3RP" "0,1" bitfld.long 0xB0 18. "RGN2RP" "0,1" bitfld.long 0xB0 17. "RGN1RP" "0,1" bitfld.long 0xB0 16. "RGN0RP" "0,1" newline bitfld.long 0xB0 15. "RGN15WP" "0,1" bitfld.long 0xB0 14. "RGN14WP" "0,1" bitfld.long 0xB0 13. "RGN13WP" "0,1" bitfld.long 0xB0 12. "RGN12WP" "0,1" newline bitfld.long 0xB0 11. "RGN11WP" "0,1" bitfld.long 0xB0 10. "RGN10WP" "0,1" bitfld.long 0xB0 9. "RGN9WP" "0,1" bitfld.long 0xB0 8. "RGN8WP" "0,1" newline bitfld.long 0xB0 7. "RGN7WP" "0,1" bitfld.long 0xB0 6. "RGN6WP" "0,1" bitfld.long 0xB0 5. "RGN5WP" "0,1" bitfld.long 0xB0 4. "RGN4WP" "0,1" newline bitfld.long 0xB0 3. "RGN3WP" "0,1" bitfld.long 0xB0 2. "RGN2WP" "0,1" bitfld.long 0xB0 1. "RGN1WP" "0,1" bitfld.long 0xB0 0. "RGN0WP" "0,1" line.long 0xB4 "DPTRGNCR45,DRAM Protected Area Region ID Setting Register 45" bitfld.long 0xB4 31. "RGN15RP" "0,1" bitfld.long 0xB4 30. "RGN14RP" "0,1" bitfld.long 0xB4 29. "RGN13RP" "0,1" bitfld.long 0xB4 28. "RGN12RP" "0,1" newline bitfld.long 0xB4 27. "RGN11RP" "0,1" bitfld.long 0xB4 26. "RGN10RP" "0,1" bitfld.long 0xB4 25. "RGN9RP" "0,1" bitfld.long 0xB4 24. "RGN8RP" "0,1" newline bitfld.long 0xB4 23. "RGN7RP" "0,1" bitfld.long 0xB4 22. "RGN6RP" "0,1" bitfld.long 0xB4 21. "RGN5RP" "0,1" bitfld.long 0xB4 20. "RGN4RP" "0,1" newline bitfld.long 0xB4 19. "RGN3RP" "0,1" bitfld.long 0xB4 18. "RGN2RP" "0,1" bitfld.long 0xB4 17. "RGN1RP" "0,1" bitfld.long 0xB4 16. "RGN0RP" "0,1" newline bitfld.long 0xB4 15. "RGN15WP" "0,1" bitfld.long 0xB4 14. "RGN14WP" "0,1" bitfld.long 0xB4 13. "RGN13WP" "0,1" bitfld.long 0xB4 12. "RGN12WP" "0,1" newline bitfld.long 0xB4 11. "RGN11WP" "0,1" bitfld.long 0xB4 10. "RGN10WP" "0,1" bitfld.long 0xB4 9. "RGN9WP" "0,1" bitfld.long 0xB4 8. "RGN8WP" "0,1" newline bitfld.long 0xB4 7. "RGN7WP" "0,1" bitfld.long 0xB4 6. "RGN6WP" "0,1" bitfld.long 0xB4 5. "RGN5WP" "0,1" bitfld.long 0xB4 4. "RGN4WP" "0,1" newline bitfld.long 0xB4 3. "RGN3WP" "0,1" bitfld.long 0xB4 2. "RGN2WP" "0,1" bitfld.long 0xB4 1. "RGN1WP" "0,1" bitfld.long 0xB4 0. "RGN0WP" "0,1" line.long 0xB8 "DPTRGNCR46,DRAM Protected Area Region ID Setting Register 46" bitfld.long 0xB8 31. "RGN15RP" "0,1" bitfld.long 0xB8 30. "RGN14RP" "0,1" bitfld.long 0xB8 29. "RGN13RP" "0,1" bitfld.long 0xB8 28. "RGN12RP" "0,1" newline bitfld.long 0xB8 27. "RGN11RP" "0,1" bitfld.long 0xB8 26. "RGN10RP" "0,1" bitfld.long 0xB8 25. "RGN9RP" "0,1" bitfld.long 0xB8 24. "RGN8RP" "0,1" newline bitfld.long 0xB8 23. "RGN7RP" "0,1" bitfld.long 0xB8 22. "RGN6RP" "0,1" bitfld.long 0xB8 21. "RGN5RP" "0,1" bitfld.long 0xB8 20. "RGN4RP" "0,1" newline bitfld.long 0xB8 19. "RGN3RP" "0,1" bitfld.long 0xB8 18. "RGN2RP" "0,1" bitfld.long 0xB8 17. "RGN1RP" "0,1" bitfld.long 0xB8 16. "RGN0RP" "0,1" newline bitfld.long 0xB8 15. "RGN15WP" "0,1" bitfld.long 0xB8 14. "RGN14WP" "0,1" bitfld.long 0xB8 13. "RGN13WP" "0,1" bitfld.long 0xB8 12. "RGN12WP" "0,1" newline bitfld.long 0xB8 11. "RGN11WP" "0,1" bitfld.long 0xB8 10. "RGN10WP" "0,1" bitfld.long 0xB8 9. "RGN9WP" "0,1" bitfld.long 0xB8 8. "RGN8WP" "0,1" newline bitfld.long 0xB8 7. "RGN7WP" "0,1" bitfld.long 0xB8 6. "RGN6WP" "0,1" bitfld.long 0xB8 5. "RGN5WP" "0,1" bitfld.long 0xB8 4. "RGN4WP" "0,1" newline bitfld.long 0xB8 3. "RGN3WP" "0,1" bitfld.long 0xB8 2. "RGN2WP" "0,1" bitfld.long 0xB8 1. "RGN1WP" "0,1" bitfld.long 0xB8 0. "RGN0WP" "0,1" line.long 0xBC "DPTRGNCR47,DRAM Protected Area Region ID Setting Register 47" bitfld.long 0xBC 31. "RGN15RP" "0,1" bitfld.long 0xBC 30. "RGN14RP" "0,1" bitfld.long 0xBC 29. "RGN13RP" "0,1" bitfld.long 0xBC 28. "RGN12RP" "0,1" newline bitfld.long 0xBC 27. "RGN11RP" "0,1" bitfld.long 0xBC 26. "RGN10RP" "0,1" bitfld.long 0xBC 25. "RGN9RP" "0,1" bitfld.long 0xBC 24. "RGN8RP" "0,1" newline bitfld.long 0xBC 23. "RGN7RP" "0,1" bitfld.long 0xBC 22. "RGN6RP" "0,1" bitfld.long 0xBC 21. "RGN5RP" "0,1" bitfld.long 0xBC 20. "RGN4RP" "0,1" newline bitfld.long 0xBC 19. "RGN3RP" "0,1" bitfld.long 0xBC 18. "RGN2RP" "0,1" bitfld.long 0xBC 17. "RGN1RP" "0,1" bitfld.long 0xBC 16. "RGN0RP" "0,1" newline bitfld.long 0xBC 15. "RGN15WP" "0,1" bitfld.long 0xBC 14. "RGN14WP" "0,1" bitfld.long 0xBC 13. "RGN13WP" "0,1" bitfld.long 0xBC 12. "RGN12WP" "0,1" newline bitfld.long 0xBC 11. "RGN11WP" "0,1" bitfld.long 0xBC 10. "RGN10WP" "0,1" bitfld.long 0xBC 9. "RGN9WP" "0,1" bitfld.long 0xBC 8. "RGN8WP" "0,1" newline bitfld.long 0xBC 7. "RGN7WP" "0,1" bitfld.long 0xBC 6. "RGN6WP" "0,1" bitfld.long 0xBC 5. "RGN5WP" "0,1" bitfld.long 0xBC 4. "RGN4WP" "0,1" newline bitfld.long 0xBC 3. "RGN3WP" "0,1" bitfld.long 0xBC 2. "RGN2WP" "0,1" bitfld.long 0xBC 1. "RGN1WP" "0,1" bitfld.long 0xBC 0. "RGN0WP" "0,1" line.long 0xC0 "DPTRGNCR48,DRAM Protected Area Region ID Setting Register 48" bitfld.long 0xC0 31. "RGN15RP" "0,1" bitfld.long 0xC0 30. "RGN14RP" "0,1" bitfld.long 0xC0 29. "RGN13RP" "0,1" bitfld.long 0xC0 28. "RGN12RP" "0,1" newline bitfld.long 0xC0 27. "RGN11RP" "0,1" bitfld.long 0xC0 26. "RGN10RP" "0,1" bitfld.long 0xC0 25. "RGN9RP" "0,1" bitfld.long 0xC0 24. "RGN8RP" "0,1" newline bitfld.long 0xC0 23. "RGN7RP" "0,1" bitfld.long 0xC0 22. "RGN6RP" "0,1" bitfld.long 0xC0 21. "RGN5RP" "0,1" bitfld.long 0xC0 20. "RGN4RP" "0,1" newline bitfld.long 0xC0 19. "RGN3RP" "0,1" bitfld.long 0xC0 18. "RGN2RP" "0,1" bitfld.long 0xC0 17. "RGN1RP" "0,1" bitfld.long 0xC0 16. "RGN0RP" "0,1" newline bitfld.long 0xC0 15. "RGN15WP" "0,1" bitfld.long 0xC0 14. "RGN14WP" "0,1" bitfld.long 0xC0 13. "RGN13WP" "0,1" bitfld.long 0xC0 12. "RGN12WP" "0,1" newline bitfld.long 0xC0 11. "RGN11WP" "0,1" bitfld.long 0xC0 10. "RGN10WP" "0,1" bitfld.long 0xC0 9. "RGN9WP" "0,1" bitfld.long 0xC0 8. "RGN8WP" "0,1" newline bitfld.long 0xC0 7. "RGN7WP" "0,1" bitfld.long 0xC0 6. "RGN6WP" "0,1" bitfld.long 0xC0 5. "RGN5WP" "0,1" bitfld.long 0xC0 4. "RGN4WP" "0,1" newline bitfld.long 0xC0 3. "RGN3WP" "0,1" bitfld.long 0xC0 2. "RGN2WP" "0,1" bitfld.long 0xC0 1. "RGN1WP" "0,1" bitfld.long 0xC0 0. "RGN0WP" "0,1" line.long 0xC4 "DPTRGNCR49,DRAM Protected Area Region ID Setting Register 49" bitfld.long 0xC4 31. "RGN15RP" "0,1" bitfld.long 0xC4 30. "RGN14RP" "0,1" bitfld.long 0xC4 29. "RGN13RP" "0,1" bitfld.long 0xC4 28. "RGN12RP" "0,1" newline bitfld.long 0xC4 27. "RGN11RP" "0,1" bitfld.long 0xC4 26. "RGN10RP" "0,1" bitfld.long 0xC4 25. "RGN9RP" "0,1" bitfld.long 0xC4 24. "RGN8RP" "0,1" newline bitfld.long 0xC4 23. "RGN7RP" "0,1" bitfld.long 0xC4 22. "RGN6RP" "0,1" bitfld.long 0xC4 21. "RGN5RP" "0,1" bitfld.long 0xC4 20. "RGN4RP" "0,1" newline bitfld.long 0xC4 19. "RGN3RP" "0,1" bitfld.long 0xC4 18. "RGN2RP" "0,1" bitfld.long 0xC4 17. "RGN1RP" "0,1" bitfld.long 0xC4 16. "RGN0RP" "0,1" newline bitfld.long 0xC4 15. "RGN15WP" "0,1" bitfld.long 0xC4 14. "RGN14WP" "0,1" bitfld.long 0xC4 13. "RGN13WP" "0,1" bitfld.long 0xC4 12. "RGN12WP" "0,1" newline bitfld.long 0xC4 11. "RGN11WP" "0,1" bitfld.long 0xC4 10. "RGN10WP" "0,1" bitfld.long 0xC4 9. "RGN9WP" "0,1" bitfld.long 0xC4 8. "RGN8WP" "0,1" newline bitfld.long 0xC4 7. "RGN7WP" "0,1" bitfld.long 0xC4 6. "RGN6WP" "0,1" bitfld.long 0xC4 5. "RGN5WP" "0,1" bitfld.long 0xC4 4. "RGN4WP" "0,1" newline bitfld.long 0xC4 3. "RGN3WP" "0,1" bitfld.long 0xC4 2. "RGN2WP" "0,1" bitfld.long 0xC4 1. "RGN1WP" "0,1" bitfld.long 0xC4 0. "RGN0WP" "0,1" line.long 0xC8 "DPTRGNCR50,DRAM Protected Area Region ID Setting Register 50" bitfld.long 0xC8 31. "RGN15RP" "0,1" bitfld.long 0xC8 30. "RGN14RP" "0,1" bitfld.long 0xC8 29. "RGN13RP" "0,1" bitfld.long 0xC8 28. "RGN12RP" "0,1" newline bitfld.long 0xC8 27. "RGN11RP" "0,1" bitfld.long 0xC8 26. "RGN10RP" "0,1" bitfld.long 0xC8 25. "RGN9RP" "0,1" bitfld.long 0xC8 24. "RGN8RP" "0,1" newline bitfld.long 0xC8 23. "RGN7RP" "0,1" bitfld.long 0xC8 22. "RGN6RP" "0,1" bitfld.long 0xC8 21. "RGN5RP" "0,1" bitfld.long 0xC8 20. "RGN4RP" "0,1" newline bitfld.long 0xC8 19. "RGN3RP" "0,1" bitfld.long 0xC8 18. "RGN2RP" "0,1" bitfld.long 0xC8 17. "RGN1RP" "0,1" bitfld.long 0xC8 16. "RGN0RP" "0,1" newline bitfld.long 0xC8 15. "RGN15WP" "0,1" bitfld.long 0xC8 14. "RGN14WP" "0,1" bitfld.long 0xC8 13. "RGN13WP" "0,1" bitfld.long 0xC8 12. "RGN12WP" "0,1" newline bitfld.long 0xC8 11. "RGN11WP" "0,1" bitfld.long 0xC8 10. "RGN10WP" "0,1" bitfld.long 0xC8 9. "RGN9WP" "0,1" bitfld.long 0xC8 8. "RGN8WP" "0,1" newline bitfld.long 0xC8 7. "RGN7WP" "0,1" bitfld.long 0xC8 6. "RGN6WP" "0,1" bitfld.long 0xC8 5. "RGN5WP" "0,1" bitfld.long 0xC8 4. "RGN4WP" "0,1" newline bitfld.long 0xC8 3. "RGN3WP" "0,1" bitfld.long 0xC8 2. "RGN2WP" "0,1" bitfld.long 0xC8 1. "RGN1WP" "0,1" bitfld.long 0xC8 0. "RGN0WP" "0,1" line.long 0xCC "DPTRGNCR51,DRAM Protected Area Region ID Setting Register 51" bitfld.long 0xCC 31. "RGN15RP" "0,1" bitfld.long 0xCC 30. "RGN14RP" "0,1" bitfld.long 0xCC 29. "RGN13RP" "0,1" bitfld.long 0xCC 28. "RGN12RP" "0,1" newline bitfld.long 0xCC 27. "RGN11RP" "0,1" bitfld.long 0xCC 26. "RGN10RP" "0,1" bitfld.long 0xCC 25. "RGN9RP" "0,1" bitfld.long 0xCC 24. "RGN8RP" "0,1" newline bitfld.long 0xCC 23. "RGN7RP" "0,1" bitfld.long 0xCC 22. "RGN6RP" "0,1" bitfld.long 0xCC 21. "RGN5RP" "0,1" bitfld.long 0xCC 20. "RGN4RP" "0,1" newline bitfld.long 0xCC 19. "RGN3RP" "0,1" bitfld.long 0xCC 18. "RGN2RP" "0,1" bitfld.long 0xCC 17. "RGN1RP" "0,1" bitfld.long 0xCC 16. "RGN0RP" "0,1" newline bitfld.long 0xCC 15. "RGN15WP" "0,1" bitfld.long 0xCC 14. "RGN14WP" "0,1" bitfld.long 0xCC 13. "RGN13WP" "0,1" bitfld.long 0xCC 12. "RGN12WP" "0,1" newline bitfld.long 0xCC 11. "RGN11WP" "0,1" bitfld.long 0xCC 10. "RGN10WP" "0,1" bitfld.long 0xCC 9. "RGN9WP" "0,1" bitfld.long 0xCC 8. "RGN8WP" "0,1" newline bitfld.long 0xCC 7. "RGN7WP" "0,1" bitfld.long 0xCC 6. "RGN6WP" "0,1" bitfld.long 0xCC 5. "RGN5WP" "0,1" bitfld.long 0xCC 4. "RGN4WP" "0,1" newline bitfld.long 0xCC 3. "RGN3WP" "0,1" bitfld.long 0xCC 2. "RGN2WP" "0,1" bitfld.long 0xCC 1. "RGN1WP" "0,1" bitfld.long 0xCC 0. "RGN0WP" "0,1" line.long 0xD0 "DPTRGNCR52,DRAM Protected Area Region ID Setting Register 52" bitfld.long 0xD0 31. "RGN15RP" "0,1" bitfld.long 0xD0 30. "RGN14RP" "0,1" bitfld.long 0xD0 29. "RGN13RP" "0,1" bitfld.long 0xD0 28. "RGN12RP" "0,1" newline bitfld.long 0xD0 27. "RGN11RP" "0,1" bitfld.long 0xD0 26. "RGN10RP" "0,1" bitfld.long 0xD0 25. "RGN9RP" "0,1" bitfld.long 0xD0 24. "RGN8RP" "0,1" newline bitfld.long 0xD0 23. "RGN7RP" "0,1" bitfld.long 0xD0 22. "RGN6RP" "0,1" bitfld.long 0xD0 21. "RGN5RP" "0,1" bitfld.long 0xD0 20. "RGN4RP" "0,1" newline bitfld.long 0xD0 19. "RGN3RP" "0,1" bitfld.long 0xD0 18. "RGN2RP" "0,1" bitfld.long 0xD0 17. "RGN1RP" "0,1" bitfld.long 0xD0 16. "RGN0RP" "0,1" newline bitfld.long 0xD0 15. "RGN15WP" "0,1" bitfld.long 0xD0 14. "RGN14WP" "0,1" bitfld.long 0xD0 13. "RGN13WP" "0,1" bitfld.long 0xD0 12. "RGN12WP" "0,1" newline bitfld.long 0xD0 11. "RGN11WP" "0,1" bitfld.long 0xD0 10. "RGN10WP" "0,1" bitfld.long 0xD0 9. "RGN9WP" "0,1" bitfld.long 0xD0 8. "RGN8WP" "0,1" newline bitfld.long 0xD0 7. "RGN7WP" "0,1" bitfld.long 0xD0 6. "RGN6WP" "0,1" bitfld.long 0xD0 5. "RGN5WP" "0,1" bitfld.long 0xD0 4. "RGN4WP" "0,1" newline bitfld.long 0xD0 3. "RGN3WP" "0,1" bitfld.long 0xD0 2. "RGN2WP" "0,1" bitfld.long 0xD0 1. "RGN1WP" "0,1" bitfld.long 0xD0 0. "RGN0WP" "0,1" line.long 0xD4 "DPTRGNCR53,DRAM Protected Area Region ID Setting Register 53" bitfld.long 0xD4 31. "RGN15RP" "0,1" bitfld.long 0xD4 30. "RGN14RP" "0,1" bitfld.long 0xD4 29. "RGN13RP" "0,1" bitfld.long 0xD4 28. "RGN12RP" "0,1" newline bitfld.long 0xD4 27. "RGN11RP" "0,1" bitfld.long 0xD4 26. "RGN10RP" "0,1" bitfld.long 0xD4 25. "RGN9RP" "0,1" bitfld.long 0xD4 24. "RGN8RP" "0,1" newline bitfld.long 0xD4 23. "RGN7RP" "0,1" bitfld.long 0xD4 22. "RGN6RP" "0,1" bitfld.long 0xD4 21. "RGN5RP" "0,1" bitfld.long 0xD4 20. "RGN4RP" "0,1" newline bitfld.long 0xD4 19. "RGN3RP" "0,1" bitfld.long 0xD4 18. "RGN2RP" "0,1" bitfld.long 0xD4 17. "RGN1RP" "0,1" bitfld.long 0xD4 16. "RGN0RP" "0,1" newline bitfld.long 0xD4 15. "RGN15WP" "0,1" bitfld.long 0xD4 14. "RGN14WP" "0,1" bitfld.long 0xD4 13. "RGN13WP" "0,1" bitfld.long 0xD4 12. "RGN12WP" "0,1" newline bitfld.long 0xD4 11. "RGN11WP" "0,1" bitfld.long 0xD4 10. "RGN10WP" "0,1" bitfld.long 0xD4 9. "RGN9WP" "0,1" bitfld.long 0xD4 8. "RGN8WP" "0,1" newline bitfld.long 0xD4 7. "RGN7WP" "0,1" bitfld.long 0xD4 6. "RGN6WP" "0,1" bitfld.long 0xD4 5. "RGN5WP" "0,1" bitfld.long 0xD4 4. "RGN4WP" "0,1" newline bitfld.long 0xD4 3. "RGN3WP" "0,1" bitfld.long 0xD4 2. "RGN2WP" "0,1" bitfld.long 0xD4 1. "RGN1WP" "0,1" bitfld.long 0xD4 0. "RGN0WP" "0,1" line.long 0xD8 "DPTRGNCR54,DRAM Protected Area Region ID Setting Register 54" bitfld.long 0xD8 31. "RGN15RP" "0,1" bitfld.long 0xD8 30. "RGN14RP" "0,1" bitfld.long 0xD8 29. "RGN13RP" "0,1" bitfld.long 0xD8 28. "RGN12RP" "0,1" newline bitfld.long 0xD8 27. "RGN11RP" "0,1" bitfld.long 0xD8 26. "RGN10RP" "0,1" bitfld.long 0xD8 25. "RGN9RP" "0,1" bitfld.long 0xD8 24. "RGN8RP" "0,1" newline bitfld.long 0xD8 23. "RGN7RP" "0,1" bitfld.long 0xD8 22. "RGN6RP" "0,1" bitfld.long 0xD8 21. "RGN5RP" "0,1" bitfld.long 0xD8 20. "RGN4RP" "0,1" newline bitfld.long 0xD8 19. "RGN3RP" "0,1" bitfld.long 0xD8 18. "RGN2RP" "0,1" bitfld.long 0xD8 17. "RGN1RP" "0,1" bitfld.long 0xD8 16. "RGN0RP" "0,1" newline bitfld.long 0xD8 15. "RGN15WP" "0,1" bitfld.long 0xD8 14. "RGN14WP" "0,1" bitfld.long 0xD8 13. "RGN13WP" "0,1" bitfld.long 0xD8 12. "RGN12WP" "0,1" newline bitfld.long 0xD8 11. "RGN11WP" "0,1" bitfld.long 0xD8 10. "RGN10WP" "0,1" bitfld.long 0xD8 9. "RGN9WP" "0,1" bitfld.long 0xD8 8. "RGN8WP" "0,1" newline bitfld.long 0xD8 7. "RGN7WP" "0,1" bitfld.long 0xD8 6. "RGN6WP" "0,1" bitfld.long 0xD8 5. "RGN5WP" "0,1" bitfld.long 0xD8 4. "RGN4WP" "0,1" newline bitfld.long 0xD8 3. "RGN3WP" "0,1" bitfld.long 0xD8 2. "RGN2WP" "0,1" bitfld.long 0xD8 1. "RGN1WP" "0,1" bitfld.long 0xD8 0. "RGN0WP" "0,1" line.long 0xDC "DPTRGNCR55,DRAM Protected Area Region ID Setting Register 55" bitfld.long 0xDC 31. "RGN15RP" "0,1" bitfld.long 0xDC 30. "RGN14RP" "0,1" bitfld.long 0xDC 29. "RGN13RP" "0,1" bitfld.long 0xDC 28. "RGN12RP" "0,1" newline bitfld.long 0xDC 27. "RGN11RP" "0,1" bitfld.long 0xDC 26. "RGN10RP" "0,1" bitfld.long 0xDC 25. "RGN9RP" "0,1" bitfld.long 0xDC 24. "RGN8RP" "0,1" newline bitfld.long 0xDC 23. "RGN7RP" "0,1" bitfld.long 0xDC 22. "RGN6RP" "0,1" bitfld.long 0xDC 21. "RGN5RP" "0,1" bitfld.long 0xDC 20. "RGN4RP" "0,1" newline bitfld.long 0xDC 19. "RGN3RP" "0,1" bitfld.long 0xDC 18. "RGN2RP" "0,1" bitfld.long 0xDC 17. "RGN1RP" "0,1" bitfld.long 0xDC 16. "RGN0RP" "0,1" newline bitfld.long 0xDC 15. "RGN15WP" "0,1" bitfld.long 0xDC 14. "RGN14WP" "0,1" bitfld.long 0xDC 13. "RGN13WP" "0,1" bitfld.long 0xDC 12. "RGN12WP" "0,1" newline bitfld.long 0xDC 11. "RGN11WP" "0,1" bitfld.long 0xDC 10. "RGN10WP" "0,1" bitfld.long 0xDC 9. "RGN9WP" "0,1" bitfld.long 0xDC 8. "RGN8WP" "0,1" newline bitfld.long 0xDC 7. "RGN7WP" "0,1" bitfld.long 0xDC 6. "RGN6WP" "0,1" bitfld.long 0xDC 5. "RGN5WP" "0,1" bitfld.long 0xDC 4. "RGN4WP" "0,1" newline bitfld.long 0xDC 3. "RGN3WP" "0,1" bitfld.long 0xDC 2. "RGN2WP" "0,1" bitfld.long 0xDC 1. "RGN1WP" "0,1" bitfld.long 0xDC 0. "RGN0WP" "0,1" line.long 0xE0 "DPTRGNCR56,DRAM Protected Area Region ID Setting Register 56" bitfld.long 0xE0 31. "RGN15RP" "0,1" bitfld.long 0xE0 30. "RGN14RP" "0,1" bitfld.long 0xE0 29. "RGN13RP" "0,1" bitfld.long 0xE0 28. "RGN12RP" "0,1" newline bitfld.long 0xE0 27. "RGN11RP" "0,1" bitfld.long 0xE0 26. "RGN10RP" "0,1" bitfld.long 0xE0 25. "RGN9RP" "0,1" bitfld.long 0xE0 24. "RGN8RP" "0,1" newline bitfld.long 0xE0 23. "RGN7RP" "0,1" bitfld.long 0xE0 22. "RGN6RP" "0,1" bitfld.long 0xE0 21. "RGN5RP" "0,1" bitfld.long 0xE0 20. "RGN4RP" "0,1" newline bitfld.long 0xE0 19. "RGN3RP" "0,1" bitfld.long 0xE0 18. "RGN2RP" "0,1" bitfld.long 0xE0 17. "RGN1RP" "0,1" bitfld.long 0xE0 16. "RGN0RP" "0,1" newline bitfld.long 0xE0 15. "RGN15WP" "0,1" bitfld.long 0xE0 14. "RGN14WP" "0,1" bitfld.long 0xE0 13. "RGN13WP" "0,1" bitfld.long 0xE0 12. "RGN12WP" "0,1" newline bitfld.long 0xE0 11. "RGN11WP" "0,1" bitfld.long 0xE0 10. "RGN10WP" "0,1" bitfld.long 0xE0 9. "RGN9WP" "0,1" bitfld.long 0xE0 8. "RGN8WP" "0,1" newline bitfld.long 0xE0 7. "RGN7WP" "0,1" bitfld.long 0xE0 6. "RGN6WP" "0,1" bitfld.long 0xE0 5. "RGN5WP" "0,1" bitfld.long 0xE0 4. "RGN4WP" "0,1" newline bitfld.long 0xE0 3. "RGN3WP" "0,1" bitfld.long 0xE0 2. "RGN2WP" "0,1" bitfld.long 0xE0 1. "RGN1WP" "0,1" bitfld.long 0xE0 0. "RGN0WP" "0,1" line.long 0xE4 "DPTRGNCR57,DRAM Protected Area Region ID Setting Register 57" bitfld.long 0xE4 31. "RGN15RP" "0,1" bitfld.long 0xE4 30. "RGN14RP" "0,1" bitfld.long 0xE4 29. "RGN13RP" "0,1" bitfld.long 0xE4 28. "RGN12RP" "0,1" newline bitfld.long 0xE4 27. "RGN11RP" "0,1" bitfld.long 0xE4 26. "RGN10RP" "0,1" bitfld.long 0xE4 25. "RGN9RP" "0,1" bitfld.long 0xE4 24. "RGN8RP" "0,1" newline bitfld.long 0xE4 23. "RGN7RP" "0,1" bitfld.long 0xE4 22. "RGN6RP" "0,1" bitfld.long 0xE4 21. "RGN5RP" "0,1" bitfld.long 0xE4 20. "RGN4RP" "0,1" newline bitfld.long 0xE4 19. "RGN3RP" "0,1" bitfld.long 0xE4 18. "RGN2RP" "0,1" bitfld.long 0xE4 17. "RGN1RP" "0,1" bitfld.long 0xE4 16. "RGN0RP" "0,1" newline bitfld.long 0xE4 15. "RGN15WP" "0,1" bitfld.long 0xE4 14. "RGN14WP" "0,1" bitfld.long 0xE4 13. "RGN13WP" "0,1" bitfld.long 0xE4 12. "RGN12WP" "0,1" newline bitfld.long 0xE4 11. "RGN11WP" "0,1" bitfld.long 0xE4 10. "RGN10WP" "0,1" bitfld.long 0xE4 9. "RGN9WP" "0,1" bitfld.long 0xE4 8. "RGN8WP" "0,1" newline bitfld.long 0xE4 7. "RGN7WP" "0,1" bitfld.long 0xE4 6. "RGN6WP" "0,1" bitfld.long 0xE4 5. "RGN5WP" "0,1" bitfld.long 0xE4 4. "RGN4WP" "0,1" newline bitfld.long 0xE4 3. "RGN3WP" "0,1" bitfld.long 0xE4 2. "RGN2WP" "0,1" bitfld.long 0xE4 1. "RGN1WP" "0,1" bitfld.long 0xE4 0. "RGN0WP" "0,1" line.long 0xE8 "DPTRGNCR58,DRAM Protected Area Region ID Setting Register 58" bitfld.long 0xE8 31. "RGN15RP" "0,1" bitfld.long 0xE8 30. "RGN14RP" "0,1" bitfld.long 0xE8 29. "RGN13RP" "0,1" bitfld.long 0xE8 28. "RGN12RP" "0,1" newline bitfld.long 0xE8 27. "RGN11RP" "0,1" bitfld.long 0xE8 26. "RGN10RP" "0,1" bitfld.long 0xE8 25. "RGN9RP" "0,1" bitfld.long 0xE8 24. "RGN8RP" "0,1" newline bitfld.long 0xE8 23. "RGN7RP" "0,1" bitfld.long 0xE8 22. "RGN6RP" "0,1" bitfld.long 0xE8 21. "RGN5RP" "0,1" bitfld.long 0xE8 20. "RGN4RP" "0,1" newline bitfld.long 0xE8 19. "RGN3RP" "0,1" bitfld.long 0xE8 18. "RGN2RP" "0,1" bitfld.long 0xE8 17. "RGN1RP" "0,1" bitfld.long 0xE8 16. "RGN0RP" "0,1" newline bitfld.long 0xE8 15. "RGN15WP" "0,1" bitfld.long 0xE8 14. "RGN14WP" "0,1" bitfld.long 0xE8 13. "RGN13WP" "0,1" bitfld.long 0xE8 12. "RGN12WP" "0,1" newline bitfld.long 0xE8 11. "RGN11WP" "0,1" bitfld.long 0xE8 10. "RGN10WP" "0,1" bitfld.long 0xE8 9. "RGN9WP" "0,1" bitfld.long 0xE8 8. "RGN8WP" "0,1" newline bitfld.long 0xE8 7. "RGN7WP" "0,1" bitfld.long 0xE8 6. "RGN6WP" "0,1" bitfld.long 0xE8 5. "RGN5WP" "0,1" bitfld.long 0xE8 4. "RGN4WP" "0,1" newline bitfld.long 0xE8 3. "RGN3WP" "0,1" bitfld.long 0xE8 2. "RGN2WP" "0,1" bitfld.long 0xE8 1. "RGN1WP" "0,1" bitfld.long 0xE8 0. "RGN0WP" "0,1" line.long 0xEC "DPTRGNCR59,DRAM Protected Area Region ID Setting Register 59" bitfld.long 0xEC 31. "RGN15RP" "0,1" bitfld.long 0xEC 30. "RGN14RP" "0,1" bitfld.long 0xEC 29. "RGN13RP" "0,1" bitfld.long 0xEC 28. "RGN12RP" "0,1" newline bitfld.long 0xEC 27. "RGN11RP" "0,1" bitfld.long 0xEC 26. "RGN10RP" "0,1" bitfld.long 0xEC 25. "RGN9RP" "0,1" bitfld.long 0xEC 24. "RGN8RP" "0,1" newline bitfld.long 0xEC 23. "RGN7RP" "0,1" bitfld.long 0xEC 22. "RGN6RP" "0,1" bitfld.long 0xEC 21. "RGN5RP" "0,1" bitfld.long 0xEC 20. "RGN4RP" "0,1" newline bitfld.long 0xEC 19. "RGN3RP" "0,1" bitfld.long 0xEC 18. "RGN2RP" "0,1" bitfld.long 0xEC 17. "RGN1RP" "0,1" bitfld.long 0xEC 16. "RGN0RP" "0,1" newline bitfld.long 0xEC 15. "RGN15WP" "0,1" bitfld.long 0xEC 14. "RGN14WP" "0,1" bitfld.long 0xEC 13. "RGN13WP" "0,1" bitfld.long 0xEC 12. "RGN12WP" "0,1" newline bitfld.long 0xEC 11. "RGN11WP" "0,1" bitfld.long 0xEC 10. "RGN10WP" "0,1" bitfld.long 0xEC 9. "RGN9WP" "0,1" bitfld.long 0xEC 8. "RGN8WP" "0,1" newline bitfld.long 0xEC 7. "RGN7WP" "0,1" bitfld.long 0xEC 6. "RGN6WP" "0,1" bitfld.long 0xEC 5. "RGN5WP" "0,1" bitfld.long 0xEC 4. "RGN4WP" "0,1" newline bitfld.long 0xEC 3. "RGN3WP" "0,1" bitfld.long 0xEC 2. "RGN2WP" "0,1" bitfld.long 0xEC 1. "RGN1WP" "0,1" bitfld.long 0xEC 0. "RGN0WP" "0,1" line.long 0xF0 "DPTRGNCR60,DRAM Protected Area Region ID Setting Register 60" bitfld.long 0xF0 31. "RGN15RP" "0,1" bitfld.long 0xF0 30. "RGN14RP" "0,1" bitfld.long 0xF0 29. "RGN13RP" "0,1" bitfld.long 0xF0 28. "RGN12RP" "0,1" newline bitfld.long 0xF0 27. "RGN11RP" "0,1" bitfld.long 0xF0 26. "RGN10RP" "0,1" bitfld.long 0xF0 25. "RGN9RP" "0,1" bitfld.long 0xF0 24. "RGN8RP" "0,1" newline bitfld.long 0xF0 23. "RGN7RP" "0,1" bitfld.long 0xF0 22. "RGN6RP" "0,1" bitfld.long 0xF0 21. "RGN5RP" "0,1" bitfld.long 0xF0 20. "RGN4RP" "0,1" newline bitfld.long 0xF0 19. "RGN3RP" "0,1" bitfld.long 0xF0 18. "RGN2RP" "0,1" bitfld.long 0xF0 17. "RGN1RP" "0,1" bitfld.long 0xF0 16. "RGN0RP" "0,1" newline bitfld.long 0xF0 15. "RGN15WP" "0,1" bitfld.long 0xF0 14. "RGN14WP" "0,1" bitfld.long 0xF0 13. "RGN13WP" "0,1" bitfld.long 0xF0 12. "RGN12WP" "0,1" newline bitfld.long 0xF0 11. "RGN11WP" "0,1" bitfld.long 0xF0 10. "RGN10WP" "0,1" bitfld.long 0xF0 9. "RGN9WP" "0,1" bitfld.long 0xF0 8. "RGN8WP" "0,1" newline bitfld.long 0xF0 7. "RGN7WP" "0,1" bitfld.long 0xF0 6. "RGN6WP" "0,1" bitfld.long 0xF0 5. "RGN5WP" "0,1" bitfld.long 0xF0 4. "RGN4WP" "0,1" newline bitfld.long 0xF0 3. "RGN3WP" "0,1" bitfld.long 0xF0 2. "RGN2WP" "0,1" bitfld.long 0xF0 1. "RGN1WP" "0,1" bitfld.long 0xF0 0. "RGN0WP" "0,1" line.long 0xF4 "DPTRGNCR61,DRAM Protected Area Region ID Setting Register 61" bitfld.long 0xF4 31. "RGN15RP" "0,1" bitfld.long 0xF4 30. "RGN14RP" "0,1" bitfld.long 0xF4 29. "RGN13RP" "0,1" bitfld.long 0xF4 28. "RGN12RP" "0,1" newline bitfld.long 0xF4 27. "RGN11RP" "0,1" bitfld.long 0xF4 26. "RGN10RP" "0,1" bitfld.long 0xF4 25. "RGN9RP" "0,1" bitfld.long 0xF4 24. "RGN8RP" "0,1" newline bitfld.long 0xF4 23. "RGN7RP" "0,1" bitfld.long 0xF4 22. "RGN6RP" "0,1" bitfld.long 0xF4 21. "RGN5RP" "0,1" bitfld.long 0xF4 20. "RGN4RP" "0,1" newline bitfld.long 0xF4 19. "RGN3RP" "0,1" bitfld.long 0xF4 18. "RGN2RP" "0,1" bitfld.long 0xF4 17. "RGN1RP" "0,1" bitfld.long 0xF4 16. "RGN0RP" "0,1" newline bitfld.long 0xF4 15. "RGN15WP" "0,1" bitfld.long 0xF4 14. "RGN14WP" "0,1" bitfld.long 0xF4 13. "RGN13WP" "0,1" bitfld.long 0xF4 12. "RGN12WP" "0,1" newline bitfld.long 0xF4 11. "RGN11WP" "0,1" bitfld.long 0xF4 10. "RGN10WP" "0,1" bitfld.long 0xF4 9. "RGN9WP" "0,1" bitfld.long 0xF4 8. "RGN8WP" "0,1" newline bitfld.long 0xF4 7. "RGN7WP" "0,1" bitfld.long 0xF4 6. "RGN6WP" "0,1" bitfld.long 0xF4 5. "RGN5WP" "0,1" bitfld.long 0xF4 4. "RGN4WP" "0,1" newline bitfld.long 0xF4 3. "RGN3WP" "0,1" bitfld.long 0xF4 2. "RGN2WP" "0,1" bitfld.long 0xF4 1. "RGN1WP" "0,1" bitfld.long 0xF4 0. "RGN0WP" "0,1" line.long 0xF8 "DPTRGNCR62,DRAM Protected Area Region ID Setting Register 62" bitfld.long 0xF8 31. "RGN15RP" "0,1" bitfld.long 0xF8 30. "RGN14RP" "0,1" bitfld.long 0xF8 29. "RGN13RP" "0,1" bitfld.long 0xF8 28. "RGN12RP" "0,1" newline bitfld.long 0xF8 27. "RGN11RP" "0,1" bitfld.long 0xF8 26. "RGN10RP" "0,1" bitfld.long 0xF8 25. "RGN9RP" "0,1" bitfld.long 0xF8 24. "RGN8RP" "0,1" newline bitfld.long 0xF8 23. "RGN7RP" "0,1" bitfld.long 0xF8 22. "RGN6RP" "0,1" bitfld.long 0xF8 21. "RGN5RP" "0,1" bitfld.long 0xF8 20. "RGN4RP" "0,1" newline bitfld.long 0xF8 19. "RGN3RP" "0,1" bitfld.long 0xF8 18. "RGN2RP" "0,1" bitfld.long 0xF8 17. "RGN1RP" "0,1" bitfld.long 0xF8 16. "RGN0RP" "0,1" newline bitfld.long 0xF8 15. "RGN15WP" "0,1" bitfld.long 0xF8 14. "RGN14WP" "0,1" bitfld.long 0xF8 13. "RGN13WP" "0,1" bitfld.long 0xF8 12. "RGN12WP" "0,1" newline bitfld.long 0xF8 11. "RGN11WP" "0,1" bitfld.long 0xF8 10. "RGN10WP" "0,1" bitfld.long 0xF8 9. "RGN9WP" "0,1" bitfld.long 0xF8 8. "RGN8WP" "0,1" newline bitfld.long 0xF8 7. "RGN7WP" "0,1" bitfld.long 0xF8 6. "RGN6WP" "0,1" bitfld.long 0xF8 5. "RGN5WP" "0,1" bitfld.long 0xF8 4. "RGN4WP" "0,1" newline bitfld.long 0xF8 3. "RGN3WP" "0,1" bitfld.long 0xF8 2. "RGN2WP" "0,1" bitfld.long 0xF8 1. "RGN1WP" "0,1" bitfld.long 0xF8 0. "RGN0WP" "0,1" line.long 0xFC "DPTRGNCR63,DRAM Protected Area Region ID Setting Register 63" bitfld.long 0xFC 31. "RGN15RP" "0,1" bitfld.long 0xFC 30. "RGN14RP" "0,1" bitfld.long 0xFC 29. "RGN13RP" "0,1" bitfld.long 0xFC 28. "RGN12RP" "0,1" newline bitfld.long 0xFC 27. "RGN11RP" "0,1" bitfld.long 0xFC 26. "RGN10RP" "0,1" bitfld.long 0xFC 25. "RGN9RP" "0,1" bitfld.long 0xFC 24. "RGN8RP" "0,1" newline bitfld.long 0xFC 23. "RGN7RP" "0,1" bitfld.long 0xFC 22. "RGN6RP" "0,1" bitfld.long 0xFC 21. "RGN5RP" "0,1" bitfld.long 0xFC 20. "RGN4RP" "0,1" newline bitfld.long 0xFC 19. "RGN3RP" "0,1" bitfld.long 0xFC 18. "RGN2RP" "0,1" bitfld.long 0xFC 17. "RGN1RP" "0,1" bitfld.long 0xFC 16. "RGN0RP" "0,1" newline bitfld.long 0xFC 15. "RGN15WP" "0,1" bitfld.long 0xFC 14. "RGN14WP" "0,1" bitfld.long 0xFC 13. "RGN13WP" "0,1" bitfld.long 0xFC 12. "RGN12WP" "0,1" newline bitfld.long 0xFC 11. "RGN11WP" "0,1" bitfld.long 0xFC 10. "RGN10WP" "0,1" bitfld.long 0xFC 9. "RGN9WP" "0,1" bitfld.long 0xFC 8. "RGN8WP" "0,1" newline bitfld.long 0xFC 7. "RGN7WP" "0,1" bitfld.long 0xFC 6. "RGN6WP" "0,1" bitfld.long 0xFC 5. "RGN5WP" "0,1" bitfld.long 0xFC 4. "RGN4WP" "0,1" newline bitfld.long 0xFC 3. "RGN3WP" "0,1" bitfld.long 0xFC 2. "RGN2WP" "0,1" bitfld.long 0xFC 1. "RGN1WP" "0,1" bitfld.long 0xFC 0. "RGN0WP" "0,1" line.long 0x100 "DPTSECCR0,DRAM Protected Area Secure Setting Register 0" hexmask.long.tbyte 0x100 12.--31. 1. "--" bitfld.long 0x100 11. "SECG0RP" "0,1" bitfld.long 0x100 10. "SECG1RP" "0,1" bitfld.long 0x100 9. "SECG2RP" "0,1" newline bitfld.long 0x100 8. "SECG3RP" "0,1" hexmask.long.byte 0x100 4.--7. 1. "--" bitfld.long 0x100 3. "SECG0WP" "0,1" bitfld.long 0x100 2. "SECG1WP" "0,1" newline bitfld.long 0x100 1. "SECG2WP" "0,1" bitfld.long 0x100 0. "SECG3WP" "0,1" line.long 0x104 "DPTSECCR1,DRAM Protected Area Secure Setting Register 1" hexmask.long.tbyte 0x104 12.--31. 1. "--" bitfld.long 0x104 11. "SECG0RP" "0,1" bitfld.long 0x104 10. "SECG1RP" "0,1" bitfld.long 0x104 9. "SECG2RP" "0,1" newline bitfld.long 0x104 8. "SECG3RP" "0,1" hexmask.long.byte 0x104 4.--7. 1. "--" bitfld.long 0x104 3. "SECG0WP" "0,1" bitfld.long 0x104 2. "SECG1WP" "0,1" newline bitfld.long 0x104 1. "SECG2WP" "0,1" bitfld.long 0x104 0. "SECG3WP" "0,1" line.long 0x108 "DPTSECCR2,DRAM Protected Area Secure Setting Register 2" hexmask.long.tbyte 0x108 12.--31. 1. "--" bitfld.long 0x108 11. "SECG0RP" "0,1" bitfld.long 0x108 10. "SECG1RP" "0,1" bitfld.long 0x108 9. "SECG2RP" "0,1" newline bitfld.long 0x108 8. "SECG3RP" "0,1" hexmask.long.byte 0x108 4.--7. 1. "--" bitfld.long 0x108 3. "SECG0WP" "0,1" bitfld.long 0x108 2. "SECG1WP" "0,1" newline bitfld.long 0x108 1. "SECG2WP" "0,1" bitfld.long 0x108 0. "SECG3WP" "0,1" line.long 0x10C "DPTSECCR3,DRAM Protected Area Secure Setting Register 3" hexmask.long.tbyte 0x10C 12.--31. 1. "--" bitfld.long 0x10C 11. "SECG0RP" "0,1" bitfld.long 0x10C 10. "SECG1RP" "0,1" bitfld.long 0x10C 9. "SECG2RP" "0,1" newline bitfld.long 0x10C 8. "SECG3RP" "0,1" hexmask.long.byte 0x10C 4.--7. 1. "--" bitfld.long 0x10C 3. "SECG0WP" "0,1" bitfld.long 0x10C 2. "SECG1WP" "0,1" newline bitfld.long 0x10C 1. "SECG2WP" "0,1" bitfld.long 0x10C 0. "SECG3WP" "0,1" line.long 0x110 "DPTSECCR4,DRAM Protected Area Secure Setting Register 4" hexmask.long.tbyte 0x110 12.--31. 1. "--" bitfld.long 0x110 11. "SECG0RP" "0,1" bitfld.long 0x110 10. "SECG1RP" "0,1" bitfld.long 0x110 9. "SECG2RP" "0,1" newline bitfld.long 0x110 8. "SECG3RP" "0,1" hexmask.long.byte 0x110 4.--7. 1. "--" bitfld.long 0x110 3. "SECG0WP" "0,1" bitfld.long 0x110 2. "SECG1WP" "0,1" newline bitfld.long 0x110 1. "SECG2WP" "0,1" bitfld.long 0x110 0. "SECG3WP" "0,1" line.long 0x114 "DPTSECCR5,DRAM Protected Area Secure Setting Register 5" hexmask.long.tbyte 0x114 12.--31. 1. "--" bitfld.long 0x114 11. "SECG0RP" "0,1" bitfld.long 0x114 10. "SECG1RP" "0,1" bitfld.long 0x114 9. "SECG2RP" "0,1" newline bitfld.long 0x114 8. "SECG3RP" "0,1" hexmask.long.byte 0x114 4.--7. 1. "--" bitfld.long 0x114 3. "SECG0WP" "0,1" bitfld.long 0x114 2. "SECG1WP" "0,1" newline bitfld.long 0x114 1. "SECG2WP" "0,1" bitfld.long 0x114 0. "SECG3WP" "0,1" line.long 0x118 "DPTSECCR6,DRAM Protected Area Secure Setting Register 6" hexmask.long.tbyte 0x118 12.--31. 1. "--" bitfld.long 0x118 11. "SECG0RP" "0,1" bitfld.long 0x118 10. "SECG1RP" "0,1" bitfld.long 0x118 9. "SECG2RP" "0,1" newline bitfld.long 0x118 8. "SECG3RP" "0,1" hexmask.long.byte 0x118 4.--7. 1. "--" bitfld.long 0x118 3. "SECG0WP" "0,1" bitfld.long 0x118 2. "SECG1WP" "0,1" newline bitfld.long 0x118 1. "SECG2WP" "0,1" bitfld.long 0x118 0. "SECG3WP" "0,1" line.long 0x11C "DPTSECCR7,DRAM Protected Area Secure Setting Register 7" hexmask.long.tbyte 0x11C 12.--31. 1. "--" bitfld.long 0x11C 11. "SECG0RP" "0,1" bitfld.long 0x11C 10. "SECG1RP" "0,1" bitfld.long 0x11C 9. "SECG2RP" "0,1" newline bitfld.long 0x11C 8. "SECG3RP" "0,1" hexmask.long.byte 0x11C 4.--7. 1. "--" bitfld.long 0x11C 3. "SECG0WP" "0,1" bitfld.long 0x11C 2. "SECG1WP" "0,1" newline bitfld.long 0x11C 1. "SECG2WP" "0,1" bitfld.long 0x11C 0. "SECG3WP" "0,1" line.long 0x120 "DPTSECCR8,DRAM Protected Area Secure Setting Register 8" hexmask.long.tbyte 0x120 12.--31. 1. "--" bitfld.long 0x120 11. "SECG0RP" "0,1" bitfld.long 0x120 10. "SECG1RP" "0,1" bitfld.long 0x120 9. "SECG2RP" "0,1" newline bitfld.long 0x120 8. "SECG3RP" "0,1" hexmask.long.byte 0x120 4.--7. 1. "--" bitfld.long 0x120 3. "SECG0WP" "0,1" bitfld.long 0x120 2. "SECG1WP" "0,1" newline bitfld.long 0x120 1. "SECG2WP" "0,1" bitfld.long 0x120 0. "SECG3WP" "0,1" line.long 0x124 "DPTSECCR9,DRAM Protected Area Secure Setting Register 9" hexmask.long.tbyte 0x124 12.--31. 1. "--" bitfld.long 0x124 11. "SECG0RP" "0,1" bitfld.long 0x124 10. "SECG1RP" "0,1" bitfld.long 0x124 9. "SECG2RP" "0,1" newline bitfld.long 0x124 8. "SECG3RP" "0,1" hexmask.long.byte 0x124 4.--7. 1. "--" bitfld.long 0x124 3. "SECG0WP" "0,1" bitfld.long 0x124 2. "SECG1WP" "0,1" newline bitfld.long 0x124 1. "SECG2WP" "0,1" bitfld.long 0x124 0. "SECG3WP" "0,1" line.long 0x128 "DPTSECCR10,DRAM Protected Area Secure Setting Register 10" hexmask.long.tbyte 0x128 12.--31. 1. "--" bitfld.long 0x128 11. "SECG0RP" "0,1" bitfld.long 0x128 10. "SECG1RP" "0,1" bitfld.long 0x128 9. "SECG2RP" "0,1" newline bitfld.long 0x128 8. "SECG3RP" "0,1" hexmask.long.byte 0x128 4.--7. 1. "--" bitfld.long 0x128 3. "SECG0WP" "0,1" bitfld.long 0x128 2. "SECG1WP" "0,1" newline bitfld.long 0x128 1. "SECG2WP" "0,1" bitfld.long 0x128 0. "SECG3WP" "0,1" line.long 0x12C "DPTSECCR11,DRAM Protected Area Secure Setting Register 11" hexmask.long.tbyte 0x12C 12.--31. 1. "--" bitfld.long 0x12C 11. "SECG0RP" "0,1" bitfld.long 0x12C 10. "SECG1RP" "0,1" bitfld.long 0x12C 9. "SECG2RP" "0,1" newline bitfld.long 0x12C 8. "SECG3RP" "0,1" hexmask.long.byte 0x12C 4.--7. 1. "--" bitfld.long 0x12C 3. "SECG0WP" "0,1" bitfld.long 0x12C 2. "SECG1WP" "0,1" newline bitfld.long 0x12C 1. "SECG2WP" "0,1" bitfld.long 0x12C 0. "SECG3WP" "0,1" line.long 0x130 "DPTSECCR12,DRAM Protected Area Secure Setting Register 12" hexmask.long.tbyte 0x130 12.--31. 1. "--" bitfld.long 0x130 11. "SECG0RP" "0,1" bitfld.long 0x130 10. "SECG1RP" "0,1" bitfld.long 0x130 9. "SECG2RP" "0,1" newline bitfld.long 0x130 8. "SECG3RP" "0,1" hexmask.long.byte 0x130 4.--7. 1. "--" bitfld.long 0x130 3. "SECG0WP" "0,1" bitfld.long 0x130 2. "SECG1WP" "0,1" newline bitfld.long 0x130 1. "SECG2WP" "0,1" bitfld.long 0x130 0. "SECG3WP" "0,1" line.long 0x134 "DPTSECCR13,DRAM Protected Area Secure Setting Register 13" hexmask.long.tbyte 0x134 12.--31. 1. "--" bitfld.long 0x134 11. "SECG0RP" "0,1" bitfld.long 0x134 10. "SECG1RP" "0,1" bitfld.long 0x134 9. "SECG2RP" "0,1" newline bitfld.long 0x134 8. "SECG3RP" "0,1" hexmask.long.byte 0x134 4.--7. 1. "--" bitfld.long 0x134 3. "SECG0WP" "0,1" bitfld.long 0x134 2. "SECG1WP" "0,1" newline bitfld.long 0x134 1. "SECG2WP" "0,1" bitfld.long 0x134 0. "SECG3WP" "0,1" line.long 0x138 "DPTSECCR14,DRAM Protected Area Secure Setting Register 14" hexmask.long.tbyte 0x138 12.--31. 1. "--" bitfld.long 0x138 11. "SECG0RP" "0,1" bitfld.long 0x138 10. "SECG1RP" "0,1" bitfld.long 0x138 9. "SECG2RP" "0,1" newline bitfld.long 0x138 8. "SECG3RP" "0,1" hexmask.long.byte 0x138 4.--7. 1. "--" bitfld.long 0x138 3. "SECG0WP" "0,1" bitfld.long 0x138 2. "SECG1WP" "0,1" newline bitfld.long 0x138 1. "SECG2WP" "0,1" bitfld.long 0x138 0. "SECG3WP" "0,1" line.long 0x13C "DPTSECCR15,DRAM Protected Area Secure Setting Register 15" hexmask.long.tbyte 0x13C 12.--31. 1. "--" bitfld.long 0x13C 11. "SECG0RP" "0,1" bitfld.long 0x13C 10. "SECG1RP" "0,1" bitfld.long 0x13C 9. "SECG2RP" "0,1" newline bitfld.long 0x13C 8. "SECG3RP" "0,1" hexmask.long.byte 0x13C 4.--7. 1. "--" bitfld.long 0x13C 3. "SECG0WP" "0,1" bitfld.long 0x13C 2. "SECG1WP" "0,1" newline bitfld.long 0x13C 1. "SECG2WP" "0,1" bitfld.long 0x13C 0. "SECG3WP" "0,1" line.long 0x140 "DPTSECCR16,DRAM Protected Area Secure Setting Register 16" hexmask.long.tbyte 0x140 12.--31. 1. "--" bitfld.long 0x140 11. "SECG0RP" "0,1" bitfld.long 0x140 10. "SECG1RP" "0,1" bitfld.long 0x140 9. "SECG2RP" "0,1" newline bitfld.long 0x140 8. "SECG3RP" "0,1" hexmask.long.byte 0x140 4.--7. 1. "--" bitfld.long 0x140 3. "SECG0WP" "0,1" bitfld.long 0x140 2. "SECG1WP" "0,1" newline bitfld.long 0x140 1. "SECG2WP" "0,1" bitfld.long 0x140 0. "SECG3WP" "0,1" line.long 0x144 "DPTSECCR17,DRAM Protected Area Secure Setting Register 17" hexmask.long.tbyte 0x144 12.--31. 1. "--" bitfld.long 0x144 11. "SECG0RP" "0,1" bitfld.long 0x144 10. "SECG1RP" "0,1" bitfld.long 0x144 9. "SECG2RP" "0,1" newline bitfld.long 0x144 8. "SECG3RP" "0,1" hexmask.long.byte 0x144 4.--7. 1. "--" bitfld.long 0x144 3. "SECG0WP" "0,1" bitfld.long 0x144 2. "SECG1WP" "0,1" newline bitfld.long 0x144 1. "SECG2WP" "0,1" bitfld.long 0x144 0. "SECG3WP" "0,1" line.long 0x148 "DPTSECCR18,DRAM Protected Area Secure Setting Register 18" hexmask.long.tbyte 0x148 12.--31. 1. "--" bitfld.long 0x148 11. "SECG0RP" "0,1" bitfld.long 0x148 10. "SECG1RP" "0,1" bitfld.long 0x148 9. "SECG2RP" "0,1" newline bitfld.long 0x148 8. "SECG3RP" "0,1" hexmask.long.byte 0x148 4.--7. 1. "--" bitfld.long 0x148 3. "SECG0WP" "0,1" bitfld.long 0x148 2. "SECG1WP" "0,1" newline bitfld.long 0x148 1. "SECG2WP" "0,1" bitfld.long 0x148 0. "SECG3WP" "0,1" line.long 0x14C "DPTSECCR19,DRAM Protected Area Secure Setting Register 19" hexmask.long.tbyte 0x14C 12.--31. 1. "--" bitfld.long 0x14C 11. "SECG0RP" "0,1" bitfld.long 0x14C 10. "SECG1RP" "0,1" bitfld.long 0x14C 9. "SECG2RP" "0,1" newline bitfld.long 0x14C 8. "SECG3RP" "0,1" hexmask.long.byte 0x14C 4.--7. 1. "--" bitfld.long 0x14C 3. "SECG0WP" "0,1" bitfld.long 0x14C 2. "SECG1WP" "0,1" newline bitfld.long 0x14C 1. "SECG2WP" "0,1" bitfld.long 0x14C 0. "SECG3WP" "0,1" line.long 0x150 "DPTSECCR20,DRAM Protected Area Secure Setting Register 20" hexmask.long.tbyte 0x150 12.--31. 1. "--" bitfld.long 0x150 11. "SECG0RP" "0,1" bitfld.long 0x150 10. "SECG1RP" "0,1" bitfld.long 0x150 9. "SECG2RP" "0,1" newline bitfld.long 0x150 8. "SECG3RP" "0,1" hexmask.long.byte 0x150 4.--7. 1. "--" bitfld.long 0x150 3. "SECG0WP" "0,1" bitfld.long 0x150 2. "SECG1WP" "0,1" newline bitfld.long 0x150 1. "SECG2WP" "0,1" bitfld.long 0x150 0. "SECG3WP" "0,1" line.long 0x154 "DPTSECCR21,DRAM Protected Area Secure Setting Register 21" hexmask.long.tbyte 0x154 12.--31. 1. "--" bitfld.long 0x154 11. "SECG0RP" "0,1" bitfld.long 0x154 10. "SECG1RP" "0,1" bitfld.long 0x154 9. "SECG2RP" "0,1" newline bitfld.long 0x154 8. "SECG3RP" "0,1" hexmask.long.byte 0x154 4.--7. 1. "--" bitfld.long 0x154 3. "SECG0WP" "0,1" bitfld.long 0x154 2. "SECG1WP" "0,1" newline bitfld.long 0x154 1. "SECG2WP" "0,1" bitfld.long 0x154 0. "SECG3WP" "0,1" line.long 0x158 "DPTSECCR22,DRAM Protected Area Secure Setting Register 22" hexmask.long.tbyte 0x158 12.--31. 1. "--" bitfld.long 0x158 11. "SECG0RP" "0,1" bitfld.long 0x158 10. "SECG1RP" "0,1" bitfld.long 0x158 9. "SECG2RP" "0,1" newline bitfld.long 0x158 8. "SECG3RP" "0,1" hexmask.long.byte 0x158 4.--7. 1. "--" bitfld.long 0x158 3. "SECG0WP" "0,1" bitfld.long 0x158 2. "SECG1WP" "0,1" newline bitfld.long 0x158 1. "SECG2WP" "0,1" bitfld.long 0x158 0. "SECG3WP" "0,1" line.long 0x15C "DPTSECCR23,DRAM Protected Area Secure Setting Register 23" hexmask.long.tbyte 0x15C 12.--31. 1. "--" bitfld.long 0x15C 11. "SECG0RP" "0,1" bitfld.long 0x15C 10. "SECG1RP" "0,1" bitfld.long 0x15C 9. "SECG2RP" "0,1" newline bitfld.long 0x15C 8. "SECG3RP" "0,1" hexmask.long.byte 0x15C 4.--7. 1. "--" bitfld.long 0x15C 3. "SECG0WP" "0,1" bitfld.long 0x15C 2. "SECG1WP" "0,1" newline bitfld.long 0x15C 1. "SECG2WP" "0,1" bitfld.long 0x15C 0. "SECG3WP" "0,1" line.long 0x160 "DPTSECCR24,DRAM Protected Area Secure Setting Register 24" hexmask.long.tbyte 0x160 12.--31. 1. "--" bitfld.long 0x160 11. "SECG0RP" "0,1" bitfld.long 0x160 10. "SECG1RP" "0,1" bitfld.long 0x160 9. "SECG2RP" "0,1" newline bitfld.long 0x160 8. "SECG3RP" "0,1" hexmask.long.byte 0x160 4.--7. 1. "--" bitfld.long 0x160 3. "SECG0WP" "0,1" bitfld.long 0x160 2. "SECG1WP" "0,1" newline bitfld.long 0x160 1. "SECG2WP" "0,1" bitfld.long 0x160 0. "SECG3WP" "0,1" line.long 0x164 "DPTSECCR25,DRAM Protected Area Secure Setting Register 25" hexmask.long.tbyte 0x164 12.--31. 1. "--" bitfld.long 0x164 11. "SECG0RP" "0,1" bitfld.long 0x164 10. "SECG1RP" "0,1" bitfld.long 0x164 9. "SECG2RP" "0,1" newline bitfld.long 0x164 8. "SECG3RP" "0,1" hexmask.long.byte 0x164 4.--7. 1. "--" bitfld.long 0x164 3. "SECG0WP" "0,1" bitfld.long 0x164 2. "SECG1WP" "0,1" newline bitfld.long 0x164 1. "SECG2WP" "0,1" bitfld.long 0x164 0. "SECG3WP" "0,1" line.long 0x168 "DPTSECCR26,DRAM Protected Area Secure Setting Register 26" hexmask.long.tbyte 0x168 12.--31. 1. "--" bitfld.long 0x168 11. "SECG0RP" "0,1" bitfld.long 0x168 10. "SECG1RP" "0,1" bitfld.long 0x168 9. "SECG2RP" "0,1" newline bitfld.long 0x168 8. "SECG3RP" "0,1" hexmask.long.byte 0x168 4.--7. 1. "--" bitfld.long 0x168 3. "SECG0WP" "0,1" bitfld.long 0x168 2. "SECG1WP" "0,1" newline bitfld.long 0x168 1. "SECG2WP" "0,1" bitfld.long 0x168 0. "SECG3WP" "0,1" line.long 0x16C "DPTSECCR27,DRAM Protected Area Secure Setting Register 27" hexmask.long.tbyte 0x16C 12.--31. 1. "--" bitfld.long 0x16C 11. "SECG0RP" "0,1" bitfld.long 0x16C 10. "SECG1RP" "0,1" bitfld.long 0x16C 9. "SECG2RP" "0,1" newline bitfld.long 0x16C 8. "SECG3RP" "0,1" hexmask.long.byte 0x16C 4.--7. 1. "--" bitfld.long 0x16C 3. "SECG0WP" "0,1" bitfld.long 0x16C 2. "SECG1WP" "0,1" newline bitfld.long 0x16C 1. "SECG2WP" "0,1" bitfld.long 0x16C 0. "SECG3WP" "0,1" line.long 0x170 "DPTSECCR28,DRAM Protected Area Secure Setting Register 28" hexmask.long.tbyte 0x170 12.--31. 1. "--" bitfld.long 0x170 11. "SECG0RP" "0,1" bitfld.long 0x170 10. "SECG1RP" "0,1" bitfld.long 0x170 9. "SECG2RP" "0,1" newline bitfld.long 0x170 8. "SECG3RP" "0,1" hexmask.long.byte 0x170 4.--7. 1. "--" bitfld.long 0x170 3. "SECG0WP" "0,1" bitfld.long 0x170 2. "SECG1WP" "0,1" newline bitfld.long 0x170 1. "SECG2WP" "0,1" bitfld.long 0x170 0. "SECG3WP" "0,1" line.long 0x174 "DPTSECCR29,DRAM Protected Area Secure Setting Register 29" hexmask.long.tbyte 0x174 12.--31. 1. "--" bitfld.long 0x174 11. "SECG0RP" "0,1" bitfld.long 0x174 10. "SECG1RP" "0,1" bitfld.long 0x174 9. "SECG2RP" "0,1" newline bitfld.long 0x174 8. "SECG3RP" "0,1" hexmask.long.byte 0x174 4.--7. 1. "--" bitfld.long 0x174 3. "SECG0WP" "0,1" bitfld.long 0x174 2. "SECG1WP" "0,1" newline bitfld.long 0x174 1. "SECG2WP" "0,1" bitfld.long 0x174 0. "SECG3WP" "0,1" line.long 0x178 "DPTSECCR30,DRAM Protected Area Secure Setting Register 30" hexmask.long.tbyte 0x178 12.--31. 1. "--" bitfld.long 0x178 11. "SECG0RP" "0,1" bitfld.long 0x178 10. "SECG1RP" "0,1" bitfld.long 0x178 9. "SECG2RP" "0,1" newline bitfld.long 0x178 8. "SECG3RP" "0,1" hexmask.long.byte 0x178 4.--7. 1. "--" bitfld.long 0x178 3. "SECG0WP" "0,1" bitfld.long 0x178 2. "SECG1WP" "0,1" newline bitfld.long 0x178 1. "SECG2WP" "0,1" bitfld.long 0x178 0. "SECG3WP" "0,1" line.long 0x17C "DPTSECCR31,DRAM Protected Area Secure Setting Register 31" hexmask.long.tbyte 0x17C 12.--31. 1. "--" bitfld.long 0x17C 11. "SECG0RP" "0,1" bitfld.long 0x17C 10. "SECG1RP" "0,1" bitfld.long 0x17C 9. "SECG2RP" "0,1" newline bitfld.long 0x17C 8. "SECG3RP" "0,1" hexmask.long.byte 0x17C 4.--7. 1. "--" bitfld.long 0x17C 3. "SECG0WP" "0,1" bitfld.long 0x17C 2. "SECG1WP" "0,1" newline bitfld.long 0x17C 1. "SECG2WP" "0,1" bitfld.long 0x17C 0. "SECG3WP" "0,1" line.long 0x180 "DPTSECCR32,DRAM Protected Area Secure Setting Register 32" hexmask.long.tbyte 0x180 12.--31. 1. "--" bitfld.long 0x180 11. "SECG0RP" "0,1" bitfld.long 0x180 10. "SECG1RP" "0,1" bitfld.long 0x180 9. "SECG2RP" "0,1" newline bitfld.long 0x180 8. "SECG3RP" "0,1" hexmask.long.byte 0x180 4.--7. 1. "--" bitfld.long 0x180 3. "SECG0WP" "0,1" bitfld.long 0x180 2. "SECG1WP" "0,1" newline bitfld.long 0x180 1. "SECG2WP" "0,1" bitfld.long 0x180 0. "SECG3WP" "0,1" line.long 0x184 "DPTSECCR33,DRAM Protected Area Secure Setting Register 33" hexmask.long.tbyte 0x184 12.--31. 1. "--" bitfld.long 0x184 11. "SECG0RP" "0,1" bitfld.long 0x184 10. "SECG1RP" "0,1" bitfld.long 0x184 9. "SECG2RP" "0,1" newline bitfld.long 0x184 8. "SECG3RP" "0,1" hexmask.long.byte 0x184 4.--7. 1. "--" bitfld.long 0x184 3. "SECG0WP" "0,1" bitfld.long 0x184 2. "SECG1WP" "0,1" newline bitfld.long 0x184 1. "SECG2WP" "0,1" bitfld.long 0x184 0. "SECG3WP" "0,1" line.long 0x188 "DPTSECCR34,DRAM Protected Area Secure Setting Register 34" hexmask.long.tbyte 0x188 12.--31. 1. "--" bitfld.long 0x188 11. "SECG0RP" "0,1" bitfld.long 0x188 10. "SECG1RP" "0,1" bitfld.long 0x188 9. "SECG2RP" "0,1" newline bitfld.long 0x188 8. "SECG3RP" "0,1" hexmask.long.byte 0x188 4.--7. 1. "--" bitfld.long 0x188 3. "SECG0WP" "0,1" bitfld.long 0x188 2. "SECG1WP" "0,1" newline bitfld.long 0x188 1. "SECG2WP" "0,1" bitfld.long 0x188 0. "SECG3WP" "0,1" line.long 0x18C "DPTSECCR35,DRAM Protected Area Secure Setting Register 35" hexmask.long.tbyte 0x18C 12.--31. 1. "--" bitfld.long 0x18C 11. "SECG0RP" "0,1" bitfld.long 0x18C 10. "SECG1RP" "0,1" bitfld.long 0x18C 9. "SECG2RP" "0,1" newline bitfld.long 0x18C 8. "SECG3RP" "0,1" hexmask.long.byte 0x18C 4.--7. 1. "--" bitfld.long 0x18C 3. "SECG0WP" "0,1" bitfld.long 0x18C 2. "SECG1WP" "0,1" newline bitfld.long 0x18C 1. "SECG2WP" "0,1" bitfld.long 0x18C 0. "SECG3WP" "0,1" line.long 0x190 "DPTSECCR36,DRAM Protected Area Secure Setting Register 36" hexmask.long.tbyte 0x190 12.--31. 1. "--" bitfld.long 0x190 11. "SECG0RP" "0,1" bitfld.long 0x190 10. "SECG1RP" "0,1" bitfld.long 0x190 9. "SECG2RP" "0,1" newline bitfld.long 0x190 8. "SECG3RP" "0,1" hexmask.long.byte 0x190 4.--7. 1. "--" bitfld.long 0x190 3. "SECG0WP" "0,1" bitfld.long 0x190 2. "SECG1WP" "0,1" newline bitfld.long 0x190 1. "SECG2WP" "0,1" bitfld.long 0x190 0. "SECG3WP" "0,1" line.long 0x194 "DPTSECCR37,DRAM Protected Area Secure Setting Register 37" hexmask.long.tbyte 0x194 12.--31. 1. "--" bitfld.long 0x194 11. "SECG0RP" "0,1" bitfld.long 0x194 10. "SECG1RP" "0,1" bitfld.long 0x194 9. "SECG2RP" "0,1" newline bitfld.long 0x194 8. "SECG3RP" "0,1" hexmask.long.byte 0x194 4.--7. 1. "--" bitfld.long 0x194 3. "SECG0WP" "0,1" bitfld.long 0x194 2. "SECG1WP" "0,1" newline bitfld.long 0x194 1. "SECG2WP" "0,1" bitfld.long 0x194 0. "SECG3WP" "0,1" line.long 0x198 "DPTSECCR38,DRAM Protected Area Secure Setting Register 38" hexmask.long.tbyte 0x198 12.--31. 1. "--" bitfld.long 0x198 11. "SECG0RP" "0,1" bitfld.long 0x198 10. "SECG1RP" "0,1" bitfld.long 0x198 9. "SECG2RP" "0,1" newline bitfld.long 0x198 8. "SECG3RP" "0,1" hexmask.long.byte 0x198 4.--7. 1. "--" bitfld.long 0x198 3. "SECG0WP" "0,1" bitfld.long 0x198 2. "SECG1WP" "0,1" newline bitfld.long 0x198 1. "SECG2WP" "0,1" bitfld.long 0x198 0. "SECG3WP" "0,1" line.long 0x19C "DPTSECCR39,DRAM Protected Area Secure Setting Register 39" hexmask.long.tbyte 0x19C 12.--31. 1. "--" bitfld.long 0x19C 11. "SECG0RP" "0,1" bitfld.long 0x19C 10. "SECG1RP" "0,1" bitfld.long 0x19C 9. "SECG2RP" "0,1" newline bitfld.long 0x19C 8. "SECG3RP" "0,1" hexmask.long.byte 0x19C 4.--7. 1. "--" bitfld.long 0x19C 3. "SECG0WP" "0,1" bitfld.long 0x19C 2. "SECG1WP" "0,1" newline bitfld.long 0x19C 1. "SECG2WP" "0,1" bitfld.long 0x19C 0. "SECG3WP" "0,1" line.long 0x1A0 "DPTSECCR40,DRAM Protected Area Secure Setting Register 40" hexmask.long.tbyte 0x1A0 12.--31. 1. "--" bitfld.long 0x1A0 11. "SECG0RP" "0,1" bitfld.long 0x1A0 10. "SECG1RP" "0,1" bitfld.long 0x1A0 9. "SECG2RP" "0,1" newline bitfld.long 0x1A0 8. "SECG3RP" "0,1" hexmask.long.byte 0x1A0 4.--7. 1. "--" bitfld.long 0x1A0 3. "SECG0WP" "0,1" bitfld.long 0x1A0 2. "SECG1WP" "0,1" newline bitfld.long 0x1A0 1. "SECG2WP" "0,1" bitfld.long 0x1A0 0. "SECG3WP" "0,1" line.long 0x1A4 "DPTSECCR41,DRAM Protected Area Secure Setting Register 41" hexmask.long.tbyte 0x1A4 12.--31. 1. "--" bitfld.long 0x1A4 11. "SECG0RP" "0,1" bitfld.long 0x1A4 10. "SECG1RP" "0,1" bitfld.long 0x1A4 9. "SECG2RP" "0,1" newline bitfld.long 0x1A4 8. "SECG3RP" "0,1" hexmask.long.byte 0x1A4 4.--7. 1. "--" bitfld.long 0x1A4 3. "SECG0WP" "0,1" bitfld.long 0x1A4 2. "SECG1WP" "0,1" newline bitfld.long 0x1A4 1. "SECG2WP" "0,1" bitfld.long 0x1A4 0. "SECG3WP" "0,1" line.long 0x1A8 "DPTSECCR42,DRAM Protected Area Secure Setting Register 42" hexmask.long.tbyte 0x1A8 12.--31. 1. "--" bitfld.long 0x1A8 11. "SECG0RP" "0,1" bitfld.long 0x1A8 10. "SECG1RP" "0,1" bitfld.long 0x1A8 9. "SECG2RP" "0,1" newline bitfld.long 0x1A8 8. "SECG3RP" "0,1" hexmask.long.byte 0x1A8 4.--7. 1. "--" bitfld.long 0x1A8 3. "SECG0WP" "0,1" bitfld.long 0x1A8 2. "SECG1WP" "0,1" newline bitfld.long 0x1A8 1. "SECG2WP" "0,1" bitfld.long 0x1A8 0. "SECG3WP" "0,1" line.long 0x1AC "DPTSECCR43,DRAM Protected Area Secure Setting Register 43" hexmask.long.tbyte 0x1AC 12.--31. 1. "--" bitfld.long 0x1AC 11. "SECG0RP" "0,1" bitfld.long 0x1AC 10. "SECG1RP" "0,1" bitfld.long 0x1AC 9. "SECG2RP" "0,1" newline bitfld.long 0x1AC 8. "SECG3RP" "0,1" hexmask.long.byte 0x1AC 4.--7. 1. "--" bitfld.long 0x1AC 3. "SECG0WP" "0,1" bitfld.long 0x1AC 2. "SECG1WP" "0,1" newline bitfld.long 0x1AC 1. "SECG2WP" "0,1" bitfld.long 0x1AC 0. "SECG3WP" "0,1" line.long 0x1B0 "DPTSECCR44,DRAM Protected Area Secure Setting Register 44" hexmask.long.tbyte 0x1B0 12.--31. 1. "--" bitfld.long 0x1B0 11. "SECG0RP" "0,1" bitfld.long 0x1B0 10. "SECG1RP" "0,1" bitfld.long 0x1B0 9. "SECG2RP" "0,1" newline bitfld.long 0x1B0 8. "SECG3RP" "0,1" hexmask.long.byte 0x1B0 4.--7. 1. "--" bitfld.long 0x1B0 3. "SECG0WP" "0,1" bitfld.long 0x1B0 2. "SECG1WP" "0,1" newline bitfld.long 0x1B0 1. "SECG2WP" "0,1" bitfld.long 0x1B0 0. "SECG3WP" "0,1" line.long 0x1B4 "DPTSECCR45,DRAM Protected Area Secure Setting Register 45" hexmask.long.tbyte 0x1B4 12.--31. 1. "--" bitfld.long 0x1B4 11. "SECG0RP" "0,1" bitfld.long 0x1B4 10. "SECG1RP" "0,1" bitfld.long 0x1B4 9. "SECG2RP" "0,1" newline bitfld.long 0x1B4 8. "SECG3RP" "0,1" hexmask.long.byte 0x1B4 4.--7. 1. "--" bitfld.long 0x1B4 3. "SECG0WP" "0,1" bitfld.long 0x1B4 2. "SECG1WP" "0,1" newline bitfld.long 0x1B4 1. "SECG2WP" "0,1" bitfld.long 0x1B4 0. "SECG3WP" "0,1" line.long 0x1B8 "DPTSECCR46,DRAM Protected Area Secure Setting Register 46" hexmask.long.tbyte 0x1B8 12.--31. 1. "--" bitfld.long 0x1B8 11. "SECG0RP" "0,1" bitfld.long 0x1B8 10. "SECG1RP" "0,1" bitfld.long 0x1B8 9. "SECG2RP" "0,1" newline bitfld.long 0x1B8 8. "SECG3RP" "0,1" hexmask.long.byte 0x1B8 4.--7. 1. "--" bitfld.long 0x1B8 3. "SECG0WP" "0,1" bitfld.long 0x1B8 2. "SECG1WP" "0,1" newline bitfld.long 0x1B8 1. "SECG2WP" "0,1" bitfld.long 0x1B8 0. "SECG3WP" "0,1" line.long 0x1BC "DPTSECCR47,DRAM Protected Area Secure Setting Register 47" hexmask.long.tbyte 0x1BC 12.--31. 1. "--" bitfld.long 0x1BC 11. "SECG0RP" "0,1" bitfld.long 0x1BC 10. "SECG1RP" "0,1" bitfld.long 0x1BC 9. "SECG2RP" "0,1" newline bitfld.long 0x1BC 8. "SECG3RP" "0,1" hexmask.long.byte 0x1BC 4.--7. 1. "--" bitfld.long 0x1BC 3. "SECG0WP" "0,1" bitfld.long 0x1BC 2. "SECG1WP" "0,1" newline bitfld.long 0x1BC 1. "SECG2WP" "0,1" bitfld.long 0x1BC 0. "SECG3WP" "0,1" line.long 0x1C0 "DPTSECCR48,DRAM Protected Area Secure Setting Register 48" hexmask.long.tbyte 0x1C0 12.--31. 1. "--" bitfld.long 0x1C0 11. "SECG0RP" "0,1" bitfld.long 0x1C0 10. "SECG1RP" "0,1" bitfld.long 0x1C0 9. "SECG2RP" "0,1" newline bitfld.long 0x1C0 8. "SECG3RP" "0,1" hexmask.long.byte 0x1C0 4.--7. 1. "--" bitfld.long 0x1C0 3. "SECG0WP" "0,1" bitfld.long 0x1C0 2. "SECG1WP" "0,1" newline bitfld.long 0x1C0 1. "SECG2WP" "0,1" bitfld.long 0x1C0 0. "SECG3WP" "0,1" line.long 0x1C4 "DPTSECCR49,DRAM Protected Area Secure Setting Register 49" hexmask.long.tbyte 0x1C4 12.--31. 1. "--" bitfld.long 0x1C4 11. "SECG0RP" "0,1" bitfld.long 0x1C4 10. "SECG1RP" "0,1" bitfld.long 0x1C4 9. "SECG2RP" "0,1" newline bitfld.long 0x1C4 8. "SECG3RP" "0,1" hexmask.long.byte 0x1C4 4.--7. 1. "--" bitfld.long 0x1C4 3. "SECG0WP" "0,1" bitfld.long 0x1C4 2. "SECG1WP" "0,1" newline bitfld.long 0x1C4 1. "SECG2WP" "0,1" bitfld.long 0x1C4 0. "SECG3WP" "0,1" line.long 0x1C8 "DPTSECCR50,DRAM Protected Area Secure Setting Register 50" hexmask.long.tbyte 0x1C8 12.--31. 1. "--" bitfld.long 0x1C8 11. "SECG0RP" "0,1" bitfld.long 0x1C8 10. "SECG1RP" "0,1" bitfld.long 0x1C8 9. "SECG2RP" "0,1" newline bitfld.long 0x1C8 8. "SECG3RP" "0,1" hexmask.long.byte 0x1C8 4.--7. 1. "--" bitfld.long 0x1C8 3. "SECG0WP" "0,1" bitfld.long 0x1C8 2. "SECG1WP" "0,1" newline bitfld.long 0x1C8 1. "SECG2WP" "0,1" bitfld.long 0x1C8 0. "SECG3WP" "0,1" line.long 0x1CC "DPTSECCR51,DRAM Protected Area Secure Setting Register 51" hexmask.long.tbyte 0x1CC 12.--31. 1. "--" bitfld.long 0x1CC 11. "SECG0RP" "0,1" bitfld.long 0x1CC 10. "SECG1RP" "0,1" bitfld.long 0x1CC 9. "SECG2RP" "0,1" newline bitfld.long 0x1CC 8. "SECG3RP" "0,1" hexmask.long.byte 0x1CC 4.--7. 1. "--" bitfld.long 0x1CC 3. "SECG0WP" "0,1" bitfld.long 0x1CC 2. "SECG1WP" "0,1" newline bitfld.long 0x1CC 1. "SECG2WP" "0,1" bitfld.long 0x1CC 0. "SECG3WP" "0,1" line.long 0x1D0 "DPTSECCR52,DRAM Protected Area Secure Setting Register 52" hexmask.long.tbyte 0x1D0 12.--31. 1. "--" bitfld.long 0x1D0 11. "SECG0RP" "0,1" bitfld.long 0x1D0 10. "SECG1RP" "0,1" bitfld.long 0x1D0 9. "SECG2RP" "0,1" newline bitfld.long 0x1D0 8. "SECG3RP" "0,1" hexmask.long.byte 0x1D0 4.--7. 1. "--" bitfld.long 0x1D0 3. "SECG0WP" "0,1" bitfld.long 0x1D0 2. "SECG1WP" "0,1" newline bitfld.long 0x1D0 1. "SECG2WP" "0,1" bitfld.long 0x1D0 0. "SECG3WP" "0,1" line.long 0x1D4 "DPTSECCR53,DRAM Protected Area Secure Setting Register 53" hexmask.long.tbyte 0x1D4 12.--31. 1. "--" bitfld.long 0x1D4 11. "SECG0RP" "0,1" bitfld.long 0x1D4 10. "SECG1RP" "0,1" bitfld.long 0x1D4 9. "SECG2RP" "0,1" newline bitfld.long 0x1D4 8. "SECG3RP" "0,1" hexmask.long.byte 0x1D4 4.--7. 1. "--" bitfld.long 0x1D4 3. "SECG0WP" "0,1" bitfld.long 0x1D4 2. "SECG1WP" "0,1" newline bitfld.long 0x1D4 1. "SECG2WP" "0,1" bitfld.long 0x1D4 0. "SECG3WP" "0,1" line.long 0x1D8 "DPTSECCR54,DRAM Protected Area Secure Setting Register 54" hexmask.long.tbyte 0x1D8 12.--31. 1. "--" bitfld.long 0x1D8 11. "SECG0RP" "0,1" bitfld.long 0x1D8 10. "SECG1RP" "0,1" bitfld.long 0x1D8 9. "SECG2RP" "0,1" newline bitfld.long 0x1D8 8. "SECG3RP" "0,1" hexmask.long.byte 0x1D8 4.--7. 1. "--" bitfld.long 0x1D8 3. "SECG0WP" "0,1" bitfld.long 0x1D8 2. "SECG1WP" "0,1" newline bitfld.long 0x1D8 1. "SECG2WP" "0,1" bitfld.long 0x1D8 0. "SECG3WP" "0,1" line.long 0x1DC "DPTSECCR55,DRAM Protected Area Secure Setting Register 55" hexmask.long.tbyte 0x1DC 12.--31. 1. "--" bitfld.long 0x1DC 11. "SECG0RP" "0,1" bitfld.long 0x1DC 10. "SECG1RP" "0,1" bitfld.long 0x1DC 9. "SECG2RP" "0,1" newline bitfld.long 0x1DC 8. "SECG3RP" "0,1" hexmask.long.byte 0x1DC 4.--7. 1. "--" bitfld.long 0x1DC 3. "SECG0WP" "0,1" bitfld.long 0x1DC 2. "SECG1WP" "0,1" newline bitfld.long 0x1DC 1. "SECG2WP" "0,1" bitfld.long 0x1DC 0. "SECG3WP" "0,1" line.long 0x1E0 "DPTSECCR56,DRAM Protected Area Secure Setting Register 56" hexmask.long.tbyte 0x1E0 12.--31. 1. "--" bitfld.long 0x1E0 11. "SECG0RP" "0,1" bitfld.long 0x1E0 10. "SECG1RP" "0,1" bitfld.long 0x1E0 9. "SECG2RP" "0,1" newline bitfld.long 0x1E0 8. "SECG3RP" "0,1" hexmask.long.byte 0x1E0 4.--7. 1. "--" bitfld.long 0x1E0 3. "SECG0WP" "0,1" bitfld.long 0x1E0 2. "SECG1WP" "0,1" newline bitfld.long 0x1E0 1. "SECG2WP" "0,1" bitfld.long 0x1E0 0. "SECG3WP" "0,1" line.long 0x1E4 "DPTSECCR57,DRAM Protected Area Secure Setting Register 57" hexmask.long.tbyte 0x1E4 12.--31. 1. "--" bitfld.long 0x1E4 11. "SECG0RP" "0,1" bitfld.long 0x1E4 10. "SECG1RP" "0,1" bitfld.long 0x1E4 9. "SECG2RP" "0,1" newline bitfld.long 0x1E4 8. "SECG3RP" "0,1" hexmask.long.byte 0x1E4 4.--7. 1. "--" bitfld.long 0x1E4 3. "SECG0WP" "0,1" bitfld.long 0x1E4 2. "SECG1WP" "0,1" newline bitfld.long 0x1E4 1. "SECG2WP" "0,1" bitfld.long 0x1E4 0. "SECG3WP" "0,1" line.long 0x1E8 "DPTSECCR58,DRAM Protected Area Secure Setting Register 58" hexmask.long.tbyte 0x1E8 12.--31. 1. "--" bitfld.long 0x1E8 11. "SECG0RP" "0,1" bitfld.long 0x1E8 10. "SECG1RP" "0,1" bitfld.long 0x1E8 9. "SECG2RP" "0,1" newline bitfld.long 0x1E8 8. "SECG3RP" "0,1" hexmask.long.byte 0x1E8 4.--7. 1. "--" bitfld.long 0x1E8 3. "SECG0WP" "0,1" bitfld.long 0x1E8 2. "SECG1WP" "0,1" newline bitfld.long 0x1E8 1. "SECG2WP" "0,1" bitfld.long 0x1E8 0. "SECG3WP" "0,1" line.long 0x1EC "DPTSECCR59,DRAM Protected Area Secure Setting Register 59" hexmask.long.tbyte 0x1EC 12.--31. 1. "--" bitfld.long 0x1EC 11. "SECG0RP" "0,1" bitfld.long 0x1EC 10. "SECG1RP" "0,1" bitfld.long 0x1EC 9. "SECG2RP" "0,1" newline bitfld.long 0x1EC 8. "SECG3RP" "0,1" hexmask.long.byte 0x1EC 4.--7. 1. "--" bitfld.long 0x1EC 3. "SECG0WP" "0,1" bitfld.long 0x1EC 2. "SECG1WP" "0,1" newline bitfld.long 0x1EC 1. "SECG2WP" "0,1" bitfld.long 0x1EC 0. "SECG3WP" "0,1" line.long 0x1F0 "DPTSECCR60,DRAM Protected Area Secure Setting Register 60" hexmask.long.tbyte 0x1F0 12.--31. 1. "--" bitfld.long 0x1F0 11. "SECG0RP" "0,1" bitfld.long 0x1F0 10. "SECG1RP" "0,1" bitfld.long 0x1F0 9. "SECG2RP" "0,1" newline bitfld.long 0x1F0 8. "SECG3RP" "0,1" hexmask.long.byte 0x1F0 4.--7. 1. "--" bitfld.long 0x1F0 3. "SECG0WP" "0,1" bitfld.long 0x1F0 2. "SECG1WP" "0,1" newline bitfld.long 0x1F0 1. "SECG2WP" "0,1" bitfld.long 0x1F0 0. "SECG3WP" "0,1" line.long 0x1F4 "DPTSECCR61,DRAM Protected Area Secure Setting Register 61" hexmask.long.tbyte 0x1F4 12.--31. 1. "--" bitfld.long 0x1F4 11. "SECG0RP" "0,1" bitfld.long 0x1F4 10. "SECG1RP" "0,1" bitfld.long 0x1F4 9. "SECG2RP" "0,1" newline bitfld.long 0x1F4 8. "SECG3RP" "0,1" hexmask.long.byte 0x1F4 4.--7. 1. "--" bitfld.long 0x1F4 3. "SECG0WP" "0,1" bitfld.long 0x1F4 2. "SECG1WP" "0,1" newline bitfld.long 0x1F4 1. "SECG2WP" "0,1" bitfld.long 0x1F4 0. "SECG3WP" "0,1" line.long 0x1F8 "DPTSECCR62,DRAM Protected Area Secure Setting Register 62" hexmask.long.tbyte 0x1F8 12.--31. 1. "--" bitfld.long 0x1F8 11. "SECG0RP" "0,1" bitfld.long 0x1F8 10. "SECG1RP" "0,1" bitfld.long 0x1F8 9. "SECG2RP" "0,1" newline bitfld.long 0x1F8 8. "SECG3RP" "0,1" hexmask.long.byte 0x1F8 4.--7. 1. "--" bitfld.long 0x1F8 3. "SECG0WP" "0,1" bitfld.long 0x1F8 2. "SECG1WP" "0,1" newline bitfld.long 0x1F8 1. "SECG2WP" "0,1" bitfld.long 0x1F8 0. "SECG3WP" "0,1" line.long 0x1FC "DPTSECCR63,DRAM Protected Area Secure Setting Register 63" hexmask.long.tbyte 0x1FC 12.--31. 1. "--" bitfld.long 0x1FC 11. "SECG0RP" "0,1" bitfld.long 0x1FC 10. "SECG1RP" "0,1" bitfld.long 0x1FC 9. "SECG2RP" "0,1" newline bitfld.long 0x1FC 8. "SECG3RP" "0,1" hexmask.long.byte 0x1FC 4.--7. 1. "--" bitfld.long 0x1FC 3. "SECG0WP" "0,1" bitfld.long 0x1FC 2. "SECG1WP" "0,1" newline bitfld.long 0x1FC 1. "SECG2WP" "0,1" bitfld.long 0x1FC 0. "SECG3WP" "0,1" line.long 0x200 "SPTDIVCR0,SystemRAM Protected Area Division Register 0" hexmask.long.tbyte 0x200 0.--19. 1. "DIVADDR" line.long 0x204 "SPTDIVCR1,SystemRAM Protected Area Division Register 1" hexmask.long.tbyte 0x204 0.--19. 1. "DIVADDR" line.long 0x208 "SPTDIVCR2,SystemRAM Protected Area Division Register 2" hexmask.long.tbyte 0x208 0.--19. 1. "DIVADDR" line.long 0x20C "SPTDIVCR3,SystemRAM Protected Area Division Register 3" hexmask.long.tbyte 0x20C 0.--19. 1. "DIVADDR" line.long 0x210 "SPTDIVCR4,SystemRAM Protected Area Division Register 4" hexmask.long.tbyte 0x210 0.--19. 1. "DIVADDR" line.long 0x214 "SPTDIVCR5,SystemRAM Protected Area Division Register 5" hexmask.long.tbyte 0x214 0.--19. 1. "DIVADDR" line.long 0x218 "SPTDIVCR6,SystemRAM Protected Area Division Register 6" hexmask.long.tbyte 0x218 0.--19. 1. "DIVADDR" line.long 0x21C "SPTDIVCR7,SystemRAM Protected Area Division Register 7" hexmask.long.tbyte 0x21C 0.--19. 1. "DIVADDR" line.long 0x220 "SPTDIVCR8,SystemRAM Protected Area Division Register 8" hexmask.long.tbyte 0x220 0.--19. 1. "DIVADDR" line.long 0x224 "SPTDIVCR9,SystemRAM Protected Area Division Register 9" hexmask.long.tbyte 0x224 0.--19. 1. "DIVADDR" line.long 0x228 "SPTDIVCR10,SystemRAM Protected Area Division Register 10" hexmask.long.tbyte 0x228 0.--19. 1. "DIVADDR" line.long 0x22C "SPTDIVCR11,SystemRAM Protected Area Division Register 11" hexmask.long.tbyte 0x22C 0.--19. 1. "DIVADDR" line.long 0x230 "SPTDIVCR12,SystemRAM Protected Area Division Register 12" hexmask.long.tbyte 0x230 0.--19. 1. "DIVADDR" line.long 0x234 "SPTDIVCR13,SystemRAM Protected Area Division Register 13" hexmask.long.tbyte 0x234 0.--19. 1. "DIVADDR" line.long 0x238 "SPTDIVCR14,SystemRAM Protected Area Division Register 14" hexmask.long.tbyte 0x238 0.--19. 1. "DIVADDR" group.long 0x6400++0x3F line.long 0x0 "SPTRGNCR0,SystemRAM Protected Area RegionID Setting Register 0" bitfld.long 0x0 31. "RGN15RP" "0,1" bitfld.long 0x0 30. "RGN14RP" "0,1" bitfld.long 0x0 29. "RGN13RP" "0,1" bitfld.long 0x0 28. "RGN12RP" "0,1" newline bitfld.long 0x0 27. "RGN11RP" "0,1" bitfld.long 0x0 26. "RGN10RP" "0,1" bitfld.long 0x0 25. "RGN9RP" "0,1" bitfld.long 0x0 24. "RGN8RP" "0,1" newline bitfld.long 0x0 23. "RGN7RP" "0,1" bitfld.long 0x0 22. "RGN6RP" "0,1" bitfld.long 0x0 21. "RGN5RP" "0,1" bitfld.long 0x0 20. "RGN4RP" "0,1" newline bitfld.long 0x0 19. "RGN3RP" "0,1" bitfld.long 0x0 18. "RGN2RP" "0,1" bitfld.long 0x0 17. "RGN1RP" "0,1" bitfld.long 0x0 16. "RGN0RP" "0,1" newline bitfld.long 0x0 15. "RGN15WP" "0,1" bitfld.long 0x0 14. "RGN14WP" "0,1" bitfld.long 0x0 13. "RGN13WP" "0,1" bitfld.long 0x0 12. "RGN12WP" "0,1" newline bitfld.long 0x0 11. "RGN11WP" "0,1" bitfld.long 0x0 10. "RGN10WP" "0,1" bitfld.long 0x0 9. "RGN9WP" "0,1" bitfld.long 0x0 8. "RGN8WP" "0,1" newline bitfld.long 0x0 7. "RGN7WP" "0,1" bitfld.long 0x0 6. "RGN6WP" "0,1" bitfld.long 0x0 5. "RGN5WP" "0,1" bitfld.long 0x0 4. "RGN4WP" "0,1" newline bitfld.long 0x0 3. "RGN3WP" "0,1" bitfld.long 0x0 2. "RGN2WP" "0,1" bitfld.long 0x0 1. "RGN1WP" "0,1" bitfld.long 0x0 0. "RGN0WP" "0,1" line.long 0x4 "SPTRGNCR1,SystemRAM Protected Area RegionID Setting Register 1" bitfld.long 0x4 31. "RGN15RP" "0,1" bitfld.long 0x4 30. "RGN14RP" "0,1" bitfld.long 0x4 29. "RGN13RP" "0,1" bitfld.long 0x4 28. "RGN12RP" "0,1" newline bitfld.long 0x4 27. "RGN11RP" "0,1" bitfld.long 0x4 26. "RGN10RP" "0,1" bitfld.long 0x4 25. "RGN9RP" "0,1" bitfld.long 0x4 24. "RGN8RP" "0,1" newline bitfld.long 0x4 23. "RGN7RP" "0,1" bitfld.long 0x4 22. "RGN6RP" "0,1" bitfld.long 0x4 21. "RGN5RP" "0,1" bitfld.long 0x4 20. "RGN4RP" "0,1" newline bitfld.long 0x4 19. "RGN3RP" "0,1" bitfld.long 0x4 18. "RGN2RP" "0,1" bitfld.long 0x4 17. "RGN1RP" "0,1" bitfld.long 0x4 16. "RGN0RP" "0,1" newline bitfld.long 0x4 15. "RGN15WP" "0,1" bitfld.long 0x4 14. "RGN14WP" "0,1" bitfld.long 0x4 13. "RGN13WP" "0,1" bitfld.long 0x4 12. "RGN12WP" "0,1" newline bitfld.long 0x4 11. "RGN11WP" "0,1" bitfld.long 0x4 10. "RGN10WP" "0,1" bitfld.long 0x4 9. "RGN9WP" "0,1" bitfld.long 0x4 8. "RGN8WP" "0,1" newline bitfld.long 0x4 7. "RGN7WP" "0,1" bitfld.long 0x4 6. "RGN6WP" "0,1" bitfld.long 0x4 5. "RGN5WP" "0,1" bitfld.long 0x4 4. "RGN4WP" "0,1" newline bitfld.long 0x4 3. "RGN3WP" "0,1" bitfld.long 0x4 2. "RGN2WP" "0,1" bitfld.long 0x4 1. "RGN1WP" "0,1" bitfld.long 0x4 0. "RGN0WP" "0,1" line.long 0x8 "SPTRGNCR2,SystemRAM Protected Area RegionID Setting Register 2" bitfld.long 0x8 31. "RGN15RP" "0,1" bitfld.long 0x8 30. "RGN14RP" "0,1" bitfld.long 0x8 29. "RGN13RP" "0,1" bitfld.long 0x8 28. "RGN12RP" "0,1" newline bitfld.long 0x8 27. "RGN11RP" "0,1" bitfld.long 0x8 26. "RGN10RP" "0,1" bitfld.long 0x8 25. "RGN9RP" "0,1" bitfld.long 0x8 24. "RGN8RP" "0,1" newline bitfld.long 0x8 23. "RGN7RP" "0,1" bitfld.long 0x8 22. "RGN6RP" "0,1" bitfld.long 0x8 21. "RGN5RP" "0,1" bitfld.long 0x8 20. "RGN4RP" "0,1" newline bitfld.long 0x8 19. "RGN3RP" "0,1" bitfld.long 0x8 18. "RGN2RP" "0,1" bitfld.long 0x8 17. "RGN1RP" "0,1" bitfld.long 0x8 16. "RGN0RP" "0,1" newline bitfld.long 0x8 15. "RGN15WP" "0,1" bitfld.long 0x8 14. "RGN14WP" "0,1" bitfld.long 0x8 13. "RGN13WP" "0,1" bitfld.long 0x8 12. "RGN12WP" "0,1" newline bitfld.long 0x8 11. "RGN11WP" "0,1" bitfld.long 0x8 10. "RGN10WP" "0,1" bitfld.long 0x8 9. "RGN9WP" "0,1" bitfld.long 0x8 8. "RGN8WP" "0,1" newline bitfld.long 0x8 7. "RGN7WP" "0,1" bitfld.long 0x8 6. "RGN6WP" "0,1" bitfld.long 0x8 5. "RGN5WP" "0,1" bitfld.long 0x8 4. "RGN4WP" "0,1" newline bitfld.long 0x8 3. "RGN3WP" "0,1" bitfld.long 0x8 2. "RGN2WP" "0,1" bitfld.long 0x8 1. "RGN1WP" "0,1" bitfld.long 0x8 0. "RGN0WP" "0,1" line.long 0xC "SPTRGNCR3,SystemRAM Protected Area RegionID Setting Register 3" bitfld.long 0xC 31. "RGN15RP" "0,1" bitfld.long 0xC 30. "RGN14RP" "0,1" bitfld.long 0xC 29. "RGN13RP" "0,1" bitfld.long 0xC 28. "RGN12RP" "0,1" newline bitfld.long 0xC 27. "RGN11RP" "0,1" bitfld.long 0xC 26. "RGN10RP" "0,1" bitfld.long 0xC 25. "RGN9RP" "0,1" bitfld.long 0xC 24. "RGN8RP" "0,1" newline bitfld.long 0xC 23. "RGN7RP" "0,1" bitfld.long 0xC 22. "RGN6RP" "0,1" bitfld.long 0xC 21. "RGN5RP" "0,1" bitfld.long 0xC 20. "RGN4RP" "0,1" newline bitfld.long 0xC 19. "RGN3RP" "0,1" bitfld.long 0xC 18. "RGN2RP" "0,1" bitfld.long 0xC 17. "RGN1RP" "0,1" bitfld.long 0xC 16. "RGN0RP" "0,1" newline bitfld.long 0xC 15. "RGN15WP" "0,1" bitfld.long 0xC 14. "RGN14WP" "0,1" bitfld.long 0xC 13. "RGN13WP" "0,1" bitfld.long 0xC 12. "RGN12WP" "0,1" newline bitfld.long 0xC 11. "RGN11WP" "0,1" bitfld.long 0xC 10. "RGN10WP" "0,1" bitfld.long 0xC 9. "RGN9WP" "0,1" bitfld.long 0xC 8. "RGN8WP" "0,1" newline bitfld.long 0xC 7. "RGN7WP" "0,1" bitfld.long 0xC 6. "RGN6WP" "0,1" bitfld.long 0xC 5. "RGN5WP" "0,1" bitfld.long 0xC 4. "RGN4WP" "0,1" newline bitfld.long 0xC 3. "RGN3WP" "0,1" bitfld.long 0xC 2. "RGN2WP" "0,1" bitfld.long 0xC 1. "RGN1WP" "0,1" bitfld.long 0xC 0. "RGN0WP" "0,1" line.long 0x10 "SPTRGNCR4,SystemRAM Protected Area RegionID Setting Register 4" bitfld.long 0x10 31. "RGN15RP" "0,1" bitfld.long 0x10 30. "RGN14RP" "0,1" bitfld.long 0x10 29. "RGN13RP" "0,1" bitfld.long 0x10 28. "RGN12RP" "0,1" newline bitfld.long 0x10 27. "RGN11RP" "0,1" bitfld.long 0x10 26. "RGN10RP" "0,1" bitfld.long 0x10 25. "RGN9RP" "0,1" bitfld.long 0x10 24. "RGN8RP" "0,1" newline bitfld.long 0x10 23. "RGN7RP" "0,1" bitfld.long 0x10 22. "RGN6RP" "0,1" bitfld.long 0x10 21. "RGN5RP" "0,1" bitfld.long 0x10 20. "RGN4RP" "0,1" newline bitfld.long 0x10 19. "RGN3RP" "0,1" bitfld.long 0x10 18. "RGN2RP" "0,1" bitfld.long 0x10 17. "RGN1RP" "0,1" bitfld.long 0x10 16. "RGN0RP" "0,1" newline bitfld.long 0x10 15. "RGN15WP" "0,1" bitfld.long 0x10 14. "RGN14WP" "0,1" bitfld.long 0x10 13. "RGN13WP" "0,1" bitfld.long 0x10 12. "RGN12WP" "0,1" newline bitfld.long 0x10 11. "RGN11WP" "0,1" bitfld.long 0x10 10. "RGN10WP" "0,1" bitfld.long 0x10 9. "RGN9WP" "0,1" bitfld.long 0x10 8. "RGN8WP" "0,1" newline bitfld.long 0x10 7. "RGN7WP" "0,1" bitfld.long 0x10 6. "RGN6WP" "0,1" bitfld.long 0x10 5. "RGN5WP" "0,1" bitfld.long 0x10 4. "RGN4WP" "0,1" newline bitfld.long 0x10 3. "RGN3WP" "0,1" bitfld.long 0x10 2. "RGN2WP" "0,1" bitfld.long 0x10 1. "RGN1WP" "0,1" bitfld.long 0x10 0. "RGN0WP" "0,1" line.long 0x14 "SPTRGNCR5,SystemRAM Protected Area RegionID Setting Register 5" bitfld.long 0x14 31. "RGN15RP" "0,1" bitfld.long 0x14 30. "RGN14RP" "0,1" bitfld.long 0x14 29. "RGN13RP" "0,1" bitfld.long 0x14 28. "RGN12RP" "0,1" newline bitfld.long 0x14 27. "RGN11RP" "0,1" bitfld.long 0x14 26. "RGN10RP" "0,1" bitfld.long 0x14 25. "RGN9RP" "0,1" bitfld.long 0x14 24. "RGN8RP" "0,1" newline bitfld.long 0x14 23. "RGN7RP" "0,1" bitfld.long 0x14 22. "RGN6RP" "0,1" bitfld.long 0x14 21. "RGN5RP" "0,1" bitfld.long 0x14 20. "RGN4RP" "0,1" newline bitfld.long 0x14 19. "RGN3RP" "0,1" bitfld.long 0x14 18. "RGN2RP" "0,1" bitfld.long 0x14 17. "RGN1RP" "0,1" bitfld.long 0x14 16. "RGN0RP" "0,1" newline bitfld.long 0x14 15. "RGN15WP" "0,1" bitfld.long 0x14 14. "RGN14WP" "0,1" bitfld.long 0x14 13. "RGN13WP" "0,1" bitfld.long 0x14 12. "RGN12WP" "0,1" newline bitfld.long 0x14 11. "RGN11WP" "0,1" bitfld.long 0x14 10. "RGN10WP" "0,1" bitfld.long 0x14 9. "RGN9WP" "0,1" bitfld.long 0x14 8. "RGN8WP" "0,1" newline bitfld.long 0x14 7. "RGN7WP" "0,1" bitfld.long 0x14 6. "RGN6WP" "0,1" bitfld.long 0x14 5. "RGN5WP" "0,1" bitfld.long 0x14 4. "RGN4WP" "0,1" newline bitfld.long 0x14 3. "RGN3WP" "0,1" bitfld.long 0x14 2. "RGN2WP" "0,1" bitfld.long 0x14 1. "RGN1WP" "0,1" bitfld.long 0x14 0. "RGN0WP" "0,1" line.long 0x18 "SPTRGNCR6,SystemRAM Protected Area RegionID Setting Register 6" bitfld.long 0x18 31. "RGN15RP" "0,1" bitfld.long 0x18 30. "RGN14RP" "0,1" bitfld.long 0x18 29. "RGN13RP" "0,1" bitfld.long 0x18 28. "RGN12RP" "0,1" newline bitfld.long 0x18 27. "RGN11RP" "0,1" bitfld.long 0x18 26. "RGN10RP" "0,1" bitfld.long 0x18 25. "RGN9RP" "0,1" bitfld.long 0x18 24. "RGN8RP" "0,1" newline bitfld.long 0x18 23. "RGN7RP" "0,1" bitfld.long 0x18 22. "RGN6RP" "0,1" bitfld.long 0x18 21. "RGN5RP" "0,1" bitfld.long 0x18 20. "RGN4RP" "0,1" newline bitfld.long 0x18 19. "RGN3RP" "0,1" bitfld.long 0x18 18. "RGN2RP" "0,1" bitfld.long 0x18 17. "RGN1RP" "0,1" bitfld.long 0x18 16. "RGN0RP" "0,1" newline bitfld.long 0x18 15. "RGN15WP" "0,1" bitfld.long 0x18 14. "RGN14WP" "0,1" bitfld.long 0x18 13. "RGN13WP" "0,1" bitfld.long 0x18 12. "RGN12WP" "0,1" newline bitfld.long 0x18 11. "RGN11WP" "0,1" bitfld.long 0x18 10. "RGN10WP" "0,1" bitfld.long 0x18 9. "RGN9WP" "0,1" bitfld.long 0x18 8. "RGN8WP" "0,1" newline bitfld.long 0x18 7. "RGN7WP" "0,1" bitfld.long 0x18 6. "RGN6WP" "0,1" bitfld.long 0x18 5. "RGN5WP" "0,1" bitfld.long 0x18 4. "RGN4WP" "0,1" newline bitfld.long 0x18 3. "RGN3WP" "0,1" bitfld.long 0x18 2. "RGN2WP" "0,1" bitfld.long 0x18 1. "RGN1WP" "0,1" bitfld.long 0x18 0. "RGN0WP" "0,1" line.long 0x1C "SPTRGNCR7,SystemRAM Protected Area RegionID Setting Register 7" bitfld.long 0x1C 31. "RGN15RP" "0,1" bitfld.long 0x1C 30. "RGN14RP" "0,1" bitfld.long 0x1C 29. "RGN13RP" "0,1" bitfld.long 0x1C 28. "RGN12RP" "0,1" newline bitfld.long 0x1C 27. "RGN11RP" "0,1" bitfld.long 0x1C 26. "RGN10RP" "0,1" bitfld.long 0x1C 25. "RGN9RP" "0,1" bitfld.long 0x1C 24. "RGN8RP" "0,1" newline bitfld.long 0x1C 23. "RGN7RP" "0,1" bitfld.long 0x1C 22. "RGN6RP" "0,1" bitfld.long 0x1C 21. "RGN5RP" "0,1" bitfld.long 0x1C 20. "RGN4RP" "0,1" newline bitfld.long 0x1C 19. "RGN3RP" "0,1" bitfld.long 0x1C 18. "RGN2RP" "0,1" bitfld.long 0x1C 17. "RGN1RP" "0,1" bitfld.long 0x1C 16. "RGN0RP" "0,1" newline bitfld.long 0x1C 15. "RGN15WP" "0,1" bitfld.long 0x1C 14. "RGN14WP" "0,1" bitfld.long 0x1C 13. "RGN13WP" "0,1" bitfld.long 0x1C 12. "RGN12WP" "0,1" newline bitfld.long 0x1C 11. "RGN11WP" "0,1" bitfld.long 0x1C 10. "RGN10WP" "0,1" bitfld.long 0x1C 9. "RGN9WP" "0,1" bitfld.long 0x1C 8. "RGN8WP" "0,1" newline bitfld.long 0x1C 7. "RGN7WP" "0,1" bitfld.long 0x1C 6. "RGN6WP" "0,1" bitfld.long 0x1C 5. "RGN5WP" "0,1" bitfld.long 0x1C 4. "RGN4WP" "0,1" newline bitfld.long 0x1C 3. "RGN3WP" "0,1" bitfld.long 0x1C 2. "RGN2WP" "0,1" bitfld.long 0x1C 1. "RGN1WP" "0,1" bitfld.long 0x1C 0. "RGN0WP" "0,1" line.long 0x20 "SPTRGNCR8,SystemRAM Protected Area RegionID Setting Register 8" bitfld.long 0x20 31. "RGN15RP" "0,1" bitfld.long 0x20 30. "RGN14RP" "0,1" bitfld.long 0x20 29. "RGN13RP" "0,1" bitfld.long 0x20 28. "RGN12RP" "0,1" newline bitfld.long 0x20 27. "RGN11RP" "0,1" bitfld.long 0x20 26. "RGN10RP" "0,1" bitfld.long 0x20 25. "RGN9RP" "0,1" bitfld.long 0x20 24. "RGN8RP" "0,1" newline bitfld.long 0x20 23. "RGN7RP" "0,1" bitfld.long 0x20 22. "RGN6RP" "0,1" bitfld.long 0x20 21. "RGN5RP" "0,1" bitfld.long 0x20 20. "RGN4RP" "0,1" newline bitfld.long 0x20 19. "RGN3RP" "0,1" bitfld.long 0x20 18. "RGN2RP" "0,1" bitfld.long 0x20 17. "RGN1RP" "0,1" bitfld.long 0x20 16. "RGN0RP" "0,1" newline bitfld.long 0x20 15. "RGN15WP" "0,1" bitfld.long 0x20 14. "RGN14WP" "0,1" bitfld.long 0x20 13. "RGN13WP" "0,1" bitfld.long 0x20 12. "RGN12WP" "0,1" newline bitfld.long 0x20 11. "RGN11WP" "0,1" bitfld.long 0x20 10. "RGN10WP" "0,1" bitfld.long 0x20 9. "RGN9WP" "0,1" bitfld.long 0x20 8. "RGN8WP" "0,1" newline bitfld.long 0x20 7. "RGN7WP" "0,1" bitfld.long 0x20 6. "RGN6WP" "0,1" bitfld.long 0x20 5. "RGN5WP" "0,1" bitfld.long 0x20 4. "RGN4WP" "0,1" newline bitfld.long 0x20 3. "RGN3WP" "0,1" bitfld.long 0x20 2. "RGN2WP" "0,1" bitfld.long 0x20 1. "RGN1WP" "0,1" bitfld.long 0x20 0. "RGN0WP" "0,1" line.long 0x24 "SPTRGNCR9,SystemRAM Protected Area RegionID Setting Register 9" bitfld.long 0x24 31. "RGN15RP" "0,1" bitfld.long 0x24 30. "RGN14RP" "0,1" bitfld.long 0x24 29. "RGN13RP" "0,1" bitfld.long 0x24 28. "RGN12RP" "0,1" newline bitfld.long 0x24 27. "RGN11RP" "0,1" bitfld.long 0x24 26. "RGN10RP" "0,1" bitfld.long 0x24 25. "RGN9RP" "0,1" bitfld.long 0x24 24. "RGN8RP" "0,1" newline bitfld.long 0x24 23. "RGN7RP" "0,1" bitfld.long 0x24 22. "RGN6RP" "0,1" bitfld.long 0x24 21. "RGN5RP" "0,1" bitfld.long 0x24 20. "RGN4RP" "0,1" newline bitfld.long 0x24 19. "RGN3RP" "0,1" bitfld.long 0x24 18. "RGN2RP" "0,1" bitfld.long 0x24 17. "RGN1RP" "0,1" bitfld.long 0x24 16. "RGN0RP" "0,1" newline bitfld.long 0x24 15. "RGN15WP" "0,1" bitfld.long 0x24 14. "RGN14WP" "0,1" bitfld.long 0x24 13. "RGN13WP" "0,1" bitfld.long 0x24 12. "RGN12WP" "0,1" newline bitfld.long 0x24 11. "RGN11WP" "0,1" bitfld.long 0x24 10. "RGN10WP" "0,1" bitfld.long 0x24 9. "RGN9WP" "0,1" bitfld.long 0x24 8. "RGN8WP" "0,1" newline bitfld.long 0x24 7. "RGN7WP" "0,1" bitfld.long 0x24 6. "RGN6WP" "0,1" bitfld.long 0x24 5. "RGN5WP" "0,1" bitfld.long 0x24 4. "RGN4WP" "0,1" newline bitfld.long 0x24 3. "RGN3WP" "0,1" bitfld.long 0x24 2. "RGN2WP" "0,1" bitfld.long 0x24 1. "RGN1WP" "0,1" bitfld.long 0x24 0. "RGN0WP" "0,1" line.long 0x28 "SPTRGNCR10,SystemRAM Protected Area RegionID Setting Register 10" bitfld.long 0x28 31. "RGN15RP" "0,1" bitfld.long 0x28 30. "RGN14RP" "0,1" bitfld.long 0x28 29. "RGN13RP" "0,1" bitfld.long 0x28 28. "RGN12RP" "0,1" newline bitfld.long 0x28 27. "RGN11RP" "0,1" bitfld.long 0x28 26. "RGN10RP" "0,1" bitfld.long 0x28 25. "RGN9RP" "0,1" bitfld.long 0x28 24. "RGN8RP" "0,1" newline bitfld.long 0x28 23. "RGN7RP" "0,1" bitfld.long 0x28 22. "RGN6RP" "0,1" bitfld.long 0x28 21. "RGN5RP" "0,1" bitfld.long 0x28 20. "RGN4RP" "0,1" newline bitfld.long 0x28 19. "RGN3RP" "0,1" bitfld.long 0x28 18. "RGN2RP" "0,1" bitfld.long 0x28 17. "RGN1RP" "0,1" bitfld.long 0x28 16. "RGN0RP" "0,1" newline bitfld.long 0x28 15. "RGN15WP" "0,1" bitfld.long 0x28 14. "RGN14WP" "0,1" bitfld.long 0x28 13. "RGN13WP" "0,1" bitfld.long 0x28 12. "RGN12WP" "0,1" newline bitfld.long 0x28 11. "RGN11WP" "0,1" bitfld.long 0x28 10. "RGN10WP" "0,1" bitfld.long 0x28 9. "RGN9WP" "0,1" bitfld.long 0x28 8. "RGN8WP" "0,1" newline bitfld.long 0x28 7. "RGN7WP" "0,1" bitfld.long 0x28 6. "RGN6WP" "0,1" bitfld.long 0x28 5. "RGN5WP" "0,1" bitfld.long 0x28 4. "RGN4WP" "0,1" newline bitfld.long 0x28 3. "RGN3WP" "0,1" bitfld.long 0x28 2. "RGN2WP" "0,1" bitfld.long 0x28 1. "RGN1WP" "0,1" bitfld.long 0x28 0. "RGN0WP" "0,1" line.long 0x2C "SPTRGNCR11,SystemRAM Protected Area RegionID Setting Register 11" bitfld.long 0x2C 31. "RGN15RP" "0,1" bitfld.long 0x2C 30. "RGN14RP" "0,1" bitfld.long 0x2C 29. "RGN13RP" "0,1" bitfld.long 0x2C 28. "RGN12RP" "0,1" newline bitfld.long 0x2C 27. "RGN11RP" "0,1" bitfld.long 0x2C 26. "RGN10RP" "0,1" bitfld.long 0x2C 25. "RGN9RP" "0,1" bitfld.long 0x2C 24. "RGN8RP" "0,1" newline bitfld.long 0x2C 23. "RGN7RP" "0,1" bitfld.long 0x2C 22. "RGN6RP" "0,1" bitfld.long 0x2C 21. "RGN5RP" "0,1" bitfld.long 0x2C 20. "RGN4RP" "0,1" newline bitfld.long 0x2C 19. "RGN3RP" "0,1" bitfld.long 0x2C 18. "RGN2RP" "0,1" bitfld.long 0x2C 17. "RGN1RP" "0,1" bitfld.long 0x2C 16. "RGN0RP" "0,1" newline bitfld.long 0x2C 15. "RGN15WP" "0,1" bitfld.long 0x2C 14. "RGN14WP" "0,1" bitfld.long 0x2C 13. "RGN13WP" "0,1" bitfld.long 0x2C 12. "RGN12WP" "0,1" newline bitfld.long 0x2C 11. "RGN11WP" "0,1" bitfld.long 0x2C 10. "RGN10WP" "0,1" bitfld.long 0x2C 9. "RGN9WP" "0,1" bitfld.long 0x2C 8. "RGN8WP" "0,1" newline bitfld.long 0x2C 7. "RGN7WP" "0,1" bitfld.long 0x2C 6. "RGN6WP" "0,1" bitfld.long 0x2C 5. "RGN5WP" "0,1" bitfld.long 0x2C 4. "RGN4WP" "0,1" newline bitfld.long 0x2C 3. "RGN3WP" "0,1" bitfld.long 0x2C 2. "RGN2WP" "0,1" bitfld.long 0x2C 1. "RGN1WP" "0,1" bitfld.long 0x2C 0. "RGN0WP" "0,1" line.long 0x30 "SPTRGNCR12,SystemRAM Protected Area RegionID Setting Register 12" bitfld.long 0x30 31. "RGN15RP" "0,1" bitfld.long 0x30 30. "RGN14RP" "0,1" bitfld.long 0x30 29. "RGN13RP" "0,1" bitfld.long 0x30 28. "RGN12RP" "0,1" newline bitfld.long 0x30 27. "RGN11RP" "0,1" bitfld.long 0x30 26. "RGN10RP" "0,1" bitfld.long 0x30 25. "RGN9RP" "0,1" bitfld.long 0x30 24. "RGN8RP" "0,1" newline bitfld.long 0x30 23. "RGN7RP" "0,1" bitfld.long 0x30 22. "RGN6RP" "0,1" bitfld.long 0x30 21. "RGN5RP" "0,1" bitfld.long 0x30 20. "RGN4RP" "0,1" newline bitfld.long 0x30 19. "RGN3RP" "0,1" bitfld.long 0x30 18. "RGN2RP" "0,1" bitfld.long 0x30 17. "RGN1RP" "0,1" bitfld.long 0x30 16. "RGN0RP" "0,1" newline bitfld.long 0x30 15. "RGN15WP" "0,1" bitfld.long 0x30 14. "RGN14WP" "0,1" bitfld.long 0x30 13. "RGN13WP" "0,1" bitfld.long 0x30 12. "RGN12WP" "0,1" newline bitfld.long 0x30 11. "RGN11WP" "0,1" bitfld.long 0x30 10. "RGN10WP" "0,1" bitfld.long 0x30 9. "RGN9WP" "0,1" bitfld.long 0x30 8. "RGN8WP" "0,1" newline bitfld.long 0x30 7. "RGN7WP" "0,1" bitfld.long 0x30 6. "RGN6WP" "0,1" bitfld.long 0x30 5. "RGN5WP" "0,1" bitfld.long 0x30 4. "RGN4WP" "0,1" newline bitfld.long 0x30 3. "RGN3WP" "0,1" bitfld.long 0x30 2. "RGN2WP" "0,1" bitfld.long 0x30 1. "RGN1WP" "0,1" bitfld.long 0x30 0. "RGN0WP" "0,1" line.long 0x34 "SPTRGNCR13,SystemRAM Protected Area RegionID Setting Register 13" bitfld.long 0x34 31. "RGN15RP" "0,1" bitfld.long 0x34 30. "RGN14RP" "0,1" bitfld.long 0x34 29. "RGN13RP" "0,1" bitfld.long 0x34 28. "RGN12RP" "0,1" newline bitfld.long 0x34 27. "RGN11RP" "0,1" bitfld.long 0x34 26. "RGN10RP" "0,1" bitfld.long 0x34 25. "RGN9RP" "0,1" bitfld.long 0x34 24. "RGN8RP" "0,1" newline bitfld.long 0x34 23. "RGN7RP" "0,1" bitfld.long 0x34 22. "RGN6RP" "0,1" bitfld.long 0x34 21. "RGN5RP" "0,1" bitfld.long 0x34 20. "RGN4RP" "0,1" newline bitfld.long 0x34 19. "RGN3RP" "0,1" bitfld.long 0x34 18. "RGN2RP" "0,1" bitfld.long 0x34 17. "RGN1RP" "0,1" bitfld.long 0x34 16. "RGN0RP" "0,1" newline bitfld.long 0x34 15. "RGN15WP" "0,1" bitfld.long 0x34 14. "RGN14WP" "0,1" bitfld.long 0x34 13. "RGN13WP" "0,1" bitfld.long 0x34 12. "RGN12WP" "0,1" newline bitfld.long 0x34 11. "RGN11WP" "0,1" bitfld.long 0x34 10. "RGN10WP" "0,1" bitfld.long 0x34 9. "RGN9WP" "0,1" bitfld.long 0x34 8. "RGN8WP" "0,1" newline bitfld.long 0x34 7. "RGN7WP" "0,1" bitfld.long 0x34 6. "RGN6WP" "0,1" bitfld.long 0x34 5. "RGN5WP" "0,1" bitfld.long 0x34 4. "RGN4WP" "0,1" newline bitfld.long 0x34 3. "RGN3WP" "0,1" bitfld.long 0x34 2. "RGN2WP" "0,1" bitfld.long 0x34 1. "RGN1WP" "0,1" bitfld.long 0x34 0. "RGN0WP" "0,1" line.long 0x38 "SPTRGNCR14,SystemRAM Protected Area RegionID Setting Register 14" bitfld.long 0x38 31. "RGN15RP" "0,1" bitfld.long 0x38 30. "RGN14RP" "0,1" bitfld.long 0x38 29. "RGN13RP" "0,1" bitfld.long 0x38 28. "RGN12RP" "0,1" newline bitfld.long 0x38 27. "RGN11RP" "0,1" bitfld.long 0x38 26. "RGN10RP" "0,1" bitfld.long 0x38 25. "RGN9RP" "0,1" bitfld.long 0x38 24. "RGN8RP" "0,1" newline bitfld.long 0x38 23. "RGN7RP" "0,1" bitfld.long 0x38 22. "RGN6RP" "0,1" bitfld.long 0x38 21. "RGN5RP" "0,1" bitfld.long 0x38 20. "RGN4RP" "0,1" newline bitfld.long 0x38 19. "RGN3RP" "0,1" bitfld.long 0x38 18. "RGN2RP" "0,1" bitfld.long 0x38 17. "RGN1RP" "0,1" bitfld.long 0x38 16. "RGN0RP" "0,1" newline bitfld.long 0x38 15. "RGN15WP" "0,1" bitfld.long 0x38 14. "RGN14WP" "0,1" bitfld.long 0x38 13. "RGN13WP" "0,1" bitfld.long 0x38 12. "RGN12WP" "0,1" newline bitfld.long 0x38 11. "RGN11WP" "0,1" bitfld.long 0x38 10. "RGN10WP" "0,1" bitfld.long 0x38 9. "RGN9WP" "0,1" bitfld.long 0x38 8. "RGN8WP" "0,1" newline bitfld.long 0x38 7. "RGN7WP" "0,1" bitfld.long 0x38 6. "RGN6WP" "0,1" bitfld.long 0x38 5. "RGN5WP" "0,1" bitfld.long 0x38 4. "RGN4WP" "0,1" newline bitfld.long 0x38 3. "RGN3WP" "0,1" bitfld.long 0x38 2. "RGN2WP" "0,1" bitfld.long 0x38 1. "RGN1WP" "0,1" bitfld.long 0x38 0. "RGN0WP" "0,1" line.long 0x3C "SPTRGNCR15,SystemRAM Protected Area RegionID Setting Register 15" bitfld.long 0x3C 31. "RGN15RP" "0,1" bitfld.long 0x3C 30. "RGN14RP" "0,1" bitfld.long 0x3C 29. "RGN13RP" "0,1" bitfld.long 0x3C 28. "RGN12RP" "0,1" newline bitfld.long 0x3C 27. "RGN11RP" "0,1" bitfld.long 0x3C 26. "RGN10RP" "0,1" bitfld.long 0x3C 25. "RGN9RP" "0,1" bitfld.long 0x3C 24. "RGN8RP" "0,1" newline bitfld.long 0x3C 23. "RGN7RP" "0,1" bitfld.long 0x3C 22. "RGN6RP" "0,1" bitfld.long 0x3C 21. "RGN5RP" "0,1" bitfld.long 0x3C 20. "RGN4RP" "0,1" newline bitfld.long 0x3C 19. "RGN3RP" "0,1" bitfld.long 0x3C 18. "RGN2RP" "0,1" bitfld.long 0x3C 17. "RGN1RP" "0,1" bitfld.long 0x3C 16. "RGN0RP" "0,1" newline bitfld.long 0x3C 15. "RGN15WP" "0,1" bitfld.long 0x3C 14. "RGN14WP" "0,1" bitfld.long 0x3C 13. "RGN13WP" "0,1" bitfld.long 0x3C 12. "RGN12WP" "0,1" newline bitfld.long 0x3C 11. "RGN11WP" "0,1" bitfld.long 0x3C 10. "RGN10WP" "0,1" bitfld.long 0x3C 9. "RGN9WP" "0,1" bitfld.long 0x3C 8. "RGN8WP" "0,1" newline bitfld.long 0x3C 7. "RGN7WP" "0,1" bitfld.long 0x3C 6. "RGN6WP" "0,1" bitfld.long 0x3C 5. "RGN5WP" "0,1" bitfld.long 0x3C 4. "RGN4WP" "0,1" newline bitfld.long 0x3C 3. "RGN3WP" "0,1" bitfld.long 0x3C 2. "RGN2WP" "0,1" bitfld.long 0x3C 1. "RGN1WP" "0,1" bitfld.long 0x3C 0. "RGN0WP" "0,1" group.long 0x6500++0x3F line.long 0x0 "SPTSECCR0,SystemRAM Protected Area Secure Setting Register 0" hexmask.long.tbyte 0x0 12.--31. 1. "--" bitfld.long 0x0 11. "SECG0RP" "0,1" bitfld.long 0x0 10. "SECG1RP" "0,1" bitfld.long 0x0 9. "SECG2RP" "0,1" newline bitfld.long 0x0 8. "SECG3RP" "0,1" hexmask.long.byte 0x0 4.--7. 1. "--" bitfld.long 0x0 3. "SECG0WP" "0,1" bitfld.long 0x0 2. "SECG1WP" "0,1" newline bitfld.long 0x0 1. "SECG2WP" "0,1" bitfld.long 0x0 0. "SECG3WP" "0,1" line.long 0x4 "SPTSECCR1,SystemRAM Protected Area Secure Setting Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "--" bitfld.long 0x4 11. "SECG0RP" "0,1" bitfld.long 0x4 10. "SECG1RP" "0,1" bitfld.long 0x4 9. "SECG2RP" "0,1" newline bitfld.long 0x4 8. "SECG3RP" "0,1" hexmask.long.byte 0x4 4.--7. 1. "--" bitfld.long 0x4 3. "SECG0WP" "0,1" bitfld.long 0x4 2. "SECG1WP" "0,1" newline bitfld.long 0x4 1. "SECG2WP" "0,1" bitfld.long 0x4 0. "SECG3WP" "0,1" line.long 0x8 "SPTSECCR2,SystemRAM Protected Area Secure Setting Register 2" hexmask.long.tbyte 0x8 12.--31. 1. "--" bitfld.long 0x8 11. "SECG0RP" "0,1" bitfld.long 0x8 10. "SECG1RP" "0,1" bitfld.long 0x8 9. "SECG2RP" "0,1" newline bitfld.long 0x8 8. "SECG3RP" "0,1" hexmask.long.byte 0x8 4.--7. 1. "--" bitfld.long 0x8 3. "SECG0WP" "0,1" bitfld.long 0x8 2. "SECG1WP" "0,1" newline bitfld.long 0x8 1. "SECG2WP" "0,1" bitfld.long 0x8 0. "SECG3WP" "0,1" line.long 0xC "SPTSECCR3,SystemRAM Protected Area Secure Setting Register 3" hexmask.long.tbyte 0xC 12.--31. 1. "--" bitfld.long 0xC 11. "SECG0RP" "0,1" bitfld.long 0xC 10. "SECG1RP" "0,1" bitfld.long 0xC 9. "SECG2RP" "0,1" newline bitfld.long 0xC 8. "SECG3RP" "0,1" hexmask.long.byte 0xC 4.--7. 1. "--" bitfld.long 0xC 3. "SECG0WP" "0,1" bitfld.long 0xC 2. "SECG1WP" "0,1" newline bitfld.long 0xC 1. "SECG2WP" "0,1" bitfld.long 0xC 0. "SECG3WP" "0,1" line.long 0x10 "SPTSECCR4,SystemRAM Protected Area Secure Setting Register 4" hexmask.long.tbyte 0x10 12.--31. 1. "--" bitfld.long 0x10 11. "SECG0RP" "0,1" bitfld.long 0x10 10. "SECG1RP" "0,1" bitfld.long 0x10 9. "SECG2RP" "0,1" newline bitfld.long 0x10 8. "SECG3RP" "0,1" hexmask.long.byte 0x10 4.--7. 1. "--" bitfld.long 0x10 3. "SECG0WP" "0,1" bitfld.long 0x10 2. "SECG1WP" "0,1" newline bitfld.long 0x10 1. "SECG2WP" "0,1" bitfld.long 0x10 0. "SECG3WP" "0,1" line.long 0x14 "SPTSECCR5,SystemRAM Protected Area Secure Setting Register 5" hexmask.long.tbyte 0x14 12.--31. 1. "--" bitfld.long 0x14 11. "SECG0RP" "0,1" bitfld.long 0x14 10. "SECG1RP" "0,1" bitfld.long 0x14 9. "SECG2RP" "0,1" newline bitfld.long 0x14 8. "SECG3RP" "0,1" hexmask.long.byte 0x14 4.--7. 1. "--" bitfld.long 0x14 3. "SECG0WP" "0,1" bitfld.long 0x14 2. "SECG1WP" "0,1" newline bitfld.long 0x14 1. "SECG2WP" "0,1" bitfld.long 0x14 0. "SECG3WP" "0,1" line.long 0x18 "SPTSECCR6,SystemRAM Protected Area Secure Setting Register 6" hexmask.long.tbyte 0x18 12.--31. 1. "--" bitfld.long 0x18 11. "SECG0RP" "0,1" bitfld.long 0x18 10. "SECG1RP" "0,1" bitfld.long 0x18 9. "SECG2RP" "0,1" newline bitfld.long 0x18 8. "SECG3RP" "0,1" hexmask.long.byte 0x18 4.--7. 1. "--" bitfld.long 0x18 3. "SECG0WP" "0,1" bitfld.long 0x18 2. "SECG1WP" "0,1" newline bitfld.long 0x18 1. "SECG2WP" "0,1" bitfld.long 0x18 0. "SECG3WP" "0,1" line.long 0x1C "SPTSECCR7,SystemRAM Protected Area Secure Setting Register 7" hexmask.long.tbyte 0x1C 12.--31. 1. "--" bitfld.long 0x1C 11. "SECG0RP" "0,1" bitfld.long 0x1C 10. "SECG1RP" "0,1" bitfld.long 0x1C 9. "SECG2RP" "0,1" newline bitfld.long 0x1C 8. "SECG3RP" "0,1" hexmask.long.byte 0x1C 4.--7. 1. "--" bitfld.long 0x1C 3. "SECG0WP" "0,1" bitfld.long 0x1C 2. "SECG1WP" "0,1" newline bitfld.long 0x1C 1. "SECG2WP" "0,1" bitfld.long 0x1C 0. "SECG3WP" "0,1" line.long 0x20 "SPTSECCR8,SystemRAM Protected Area Secure Setting Register 8" hexmask.long.tbyte 0x20 12.--31. 1. "--" bitfld.long 0x20 11. "SECG0RP" "0,1" bitfld.long 0x20 10. "SECG1RP" "0,1" bitfld.long 0x20 9. "SECG2RP" "0,1" newline bitfld.long 0x20 8. "SECG3RP" "0,1" hexmask.long.byte 0x20 4.--7. 1. "--" bitfld.long 0x20 3. "SECG0WP" "0,1" bitfld.long 0x20 2. "SECG1WP" "0,1" newline bitfld.long 0x20 1. "SECG2WP" "0,1" bitfld.long 0x20 0. "SECG3WP" "0,1" line.long 0x24 "SPTSECCR9,SystemRAM Protected Area Secure Setting Register 9" hexmask.long.tbyte 0x24 12.--31. 1. "--" bitfld.long 0x24 11. "SECG0RP" "0,1" bitfld.long 0x24 10. "SECG1RP" "0,1" bitfld.long 0x24 9. "SECG2RP" "0,1" newline bitfld.long 0x24 8. "SECG3RP" "0,1" hexmask.long.byte 0x24 4.--7. 1. "--" bitfld.long 0x24 3. "SECG0WP" "0,1" bitfld.long 0x24 2. "SECG1WP" "0,1" newline bitfld.long 0x24 1. "SECG2WP" "0,1" bitfld.long 0x24 0. "SECG3WP" "0,1" line.long 0x28 "SPTSECCR10,SystemRAM Protected Area Secure Setting Register 10" hexmask.long.tbyte 0x28 12.--31. 1. "--" bitfld.long 0x28 11. "SECG0RP" "0,1" bitfld.long 0x28 10. "SECG1RP" "0,1" bitfld.long 0x28 9. "SECG2RP" "0,1" newline bitfld.long 0x28 8. "SECG3RP" "0,1" hexmask.long.byte 0x28 4.--7. 1. "--" bitfld.long 0x28 3. "SECG0WP" "0,1" bitfld.long 0x28 2. "SECG1WP" "0,1" newline bitfld.long 0x28 1. "SECG2WP" "0,1" bitfld.long 0x28 0. "SECG3WP" "0,1" line.long 0x2C "SPTSECCR11,SystemRAM Protected Area Secure Setting Register 11" hexmask.long.tbyte 0x2C 12.--31. 1. "--" bitfld.long 0x2C 11. "SECG0RP" "0,1" bitfld.long 0x2C 10. "SECG1RP" "0,1" bitfld.long 0x2C 9. "SECG2RP" "0,1" newline bitfld.long 0x2C 8. "SECG3RP" "0,1" hexmask.long.byte 0x2C 4.--7. 1. "--" bitfld.long 0x2C 3. "SECG0WP" "0,1" bitfld.long 0x2C 2. "SECG1WP" "0,1" newline bitfld.long 0x2C 1. "SECG2WP" "0,1" bitfld.long 0x2C 0. "SECG3WP" "0,1" line.long 0x30 "SPTSECCR12,SystemRAM Protected Area Secure Setting Register 12" hexmask.long.tbyte 0x30 12.--31. 1. "--" bitfld.long 0x30 11. "SECG0RP" "0,1" bitfld.long 0x30 10. "SECG1RP" "0,1" bitfld.long 0x30 9. "SECG2RP" "0,1" newline bitfld.long 0x30 8. "SECG3RP" "0,1" hexmask.long.byte 0x30 4.--7. 1. "--" bitfld.long 0x30 3. "SECG0WP" "0,1" bitfld.long 0x30 2. "SECG1WP" "0,1" newline bitfld.long 0x30 1. "SECG2WP" "0,1" bitfld.long 0x30 0. "SECG3WP" "0,1" line.long 0x34 "SPTSECCR13,SystemRAM Protected Area Secure Setting Register 13" hexmask.long.tbyte 0x34 12.--31. 1. "--" bitfld.long 0x34 11. "SECG0RP" "0,1" bitfld.long 0x34 10. "SECG1RP" "0,1" bitfld.long 0x34 9. "SECG2RP" "0,1" newline bitfld.long 0x34 8. "SECG3RP" "0,1" hexmask.long.byte 0x34 4.--7. 1. "--" bitfld.long 0x34 3. "SECG0WP" "0,1" bitfld.long 0x34 2. "SECG1WP" "0,1" newline bitfld.long 0x34 1. "SECG2WP" "0,1" bitfld.long 0x34 0. "SECG3WP" "0,1" line.long 0x38 "SPTSECCR14,SystemRAM Protected Area Secure Setting Register 14" hexmask.long.tbyte 0x38 12.--31. 1. "--" bitfld.long 0x38 11. "SECG0RP" "0,1" bitfld.long 0x38 10. "SECG1RP" "0,1" bitfld.long 0x38 9. "SECG2RP" "0,1" newline bitfld.long 0x38 8. "SECG3RP" "0,1" hexmask.long.byte 0x38 4.--7. 1. "--" bitfld.long 0x38 3. "SECG0WP" "0,1" bitfld.long 0x38 2. "SECG1WP" "0,1" newline bitfld.long 0x38 1. "SECG2WP" "0,1" bitfld.long 0x38 0. "SECG3WP" "0,1" line.long 0x3C "SPTSECCR15,SystemRAM Protected Area Secure Setting Register 15" hexmask.long.tbyte 0x3C 12.--31. 1. "--" bitfld.long 0x3C 11. "SECG0RP" "0,1" bitfld.long 0x3C 10. "SECG1RP" "0,1" bitfld.long 0x3C 9. "SECG2RP" "0,1" newline bitfld.long 0x3C 8. "SECG3RP" "0,1" hexmask.long.byte 0x3C 4.--7. 1. "--" bitfld.long 0x3C 3. "SECG0WP" "0,1" bitfld.long 0x3C 2. "SECG1WP" "0,1" newline bitfld.long 0x3C 1. "SECG2WP" "0,1" bitfld.long 0x3C 0. "SECG3WP" "0,1" group.long 0x6600++0xF line.long 0x0 "PTRGNCAUSER,RegionID Protected Control Cause Register" bitfld.long 0x0 13. "MMU_RGNERR_R" "0,1" bitfld.long 0x0 11. "CCI_RGNERR_R" "0,1" bitfld.long 0x0 10. "CCI_RGNERR_W" "0,1" bitfld.long 0x0 9. "PERI_RGNERR_R" "0,1" newline bitfld.long 0x0 8. "PERI_RGNERR_W" "0,1" bitfld.long 0x0 7. "MDA1_RGNERR_R" "0,1" bitfld.long 0x0 6. "MDA1_RGNERR_W" "0,1" bitfld.long 0x0 5. "MDA0_RGNERR_R" "0,1" newline bitfld.long 0x0 4. "MDA0_RGNERR_W" "0,1" bitfld.long 0x0 3. "U3DG1_RGNERR_R" "0,1" bitfld.long 0x0 2. "U3DG1_RGNERR_W" "0,1" bitfld.long 0x0 1. "U3DG0_RGNERR_R" "0,1" newline bitfld.long 0x0 0. "U3DG0_RGNERR_W" "0,1" line.long 0x4 "PTSECCAUSER,Secure Protected Control Cause Register" bitfld.long 0x4 13. "MMU_SECERR_R" "0,1" bitfld.long 0x4 11. "CCI_SECERR_R" "0,1" bitfld.long 0x4 10. "CCI_SECERR_W" "0,1" bitfld.long 0x4 9. "PERI_SECERR_R" "0,1" newline bitfld.long 0x4 8. "PERI_SECERR_W" "0,1" bitfld.long 0x4 7. "MDA1_SECERR_R" "0,1" bitfld.long 0x4 6. "MDA1_SECERR_W" "0,1" bitfld.long 0x4 5. "MDA0_SECERR_R" "0,1" newline bitfld.long 0x4 4. "MDA0_SECERR_W" "0,1" bitfld.long 0x4 3. "U3DG1_SECERR_R" "0,1" bitfld.long 0x4 2. "U3DG1_SECERR_W" "0,1" bitfld.long 0x4 1. "U3DG0_SECERR_R" "0,1" newline bitfld.long 0x4 0. "U3DG0_SECERR_W" "0,1" line.long 0x8 "PTRGNERRCR,RegionID Protected Error Control Register" bitfld.long 0x8 13. "MMU_RGNERR_INJ_R" "0,1" bitfld.long 0x8 11. "CCI_RGNERR_INJ_R" "0,1" bitfld.long 0x8 10. "CCI_RGNERR_INJ_W" "0,1" bitfld.long 0x8 9. "PERI_RGNERR_INJ_R" "0,1" newline bitfld.long 0x8 8. "PERI_RGNERR_INJ_W" "0,1" bitfld.long 0x8 7. "MDA1_RGNERR_INJ_R" "0,1" bitfld.long 0x8 6. "MDA1_RGNERR_INJ_W" "0,1" bitfld.long 0x8 5. "MDA0_RGNERR_INJ_R" "0,1" newline bitfld.long 0x8 4. "MDA0_RGNERR_INJ_W" "0,1" bitfld.long 0x8 3. "U3DG1_RGNERR_INJ_R" "0,1" bitfld.long 0x8 2. "U3DG1_RGNERR_INJ_W" "0,1" bitfld.long 0x8 1. "U3DG0_RGNERR_INJ_R" "0,1" newline bitfld.long 0x8 0. "U3DG0_RGNERR_INJ_W" "0,1" line.long 0xC "PTSECERRCR,Secure Protected Error Control Register" bitfld.long 0xC 13. "MMU_SECERR_INJ_R" "0,1" bitfld.long 0xC 11. "CCI_SECERR_INJ_R" "0,1" bitfld.long 0xC 10. "CCI_SECERR_INJ_W" "0,1" bitfld.long 0xC 9. "PERI_SECERR_INJ_R" "0,1" newline bitfld.long 0xC 8. "PERI_SECERR_INJ_W" "0,1" bitfld.long 0xC 7. "MDA1_SECERR_INJ_R" "0,1" bitfld.long 0xC 6. "MDA1_SECERR_INJ_W" "0,1" bitfld.long 0xC 5. "MDA0_SECERR_INJ_R" "0,1" newline bitfld.long 0xC 4. "MDA0_SECERR_INJ_W" "0,1" bitfld.long 0xC 3. "U3DG1_SECERR_INJ_R" "0,1" bitfld.long 0xC 2. "U3DG1_SECERR_INJ_W" "0,1" bitfld.long 0xC 1. "U3DG0_SECERR_INJ_R" "0,1" newline bitfld.long 0xC 0. "U3DG0_SECERR_INJ_W" "0,1" rgroup.long 0x6610++0xDF line.long 0x0 "PTRGNINF0,RegionID Protected Error Information Register 0" hexmask.long 0x0 0.--31. 1. "ADR_W" line.long 0x4 "PTRGNINF1,RegionID Protected Error Information Register 1" hexmask.long 0x4 0.--31. 1. "ADR_W" hexmask.long 0x4 0.--31. 1. "ADR_R" hexmask.long.byte 0x4 0.--7. 1. "SRCID_R" line.long 0x8 "PTRGNINF2,RegionID Protected Error Information Register 2" hexmask.long 0x8 0.--31. 1. "ADR_W" hexmask.long.byte 0x8 0.--7. 1. "SRCID_R" line.long 0xC "PTRGNINF3,RegionID Protected Error Information Register 3" hexmask.long 0xC 0.--31. 1. "ADR_W" line.long 0x10 "PTRGNINF4,RegionID Protected Error Information Register 4" hexmask.long 0x10 0.--31. 1. "ADR_W" hexmask.long 0x10 0.--31. 1. "ADR_R" line.long 0x14 "PTRGNINF5,RegionID Protected Error Information Register 5" hexmask.long 0x14 0.--31. 1. "ADR_W" line.long 0x18 "PTRGNINF6,RegionID Protected Error Information Register 6" hexmask.long 0x18 0.--31. 1. "ADR_W" line.long 0x1C "PTRGNINF7,RegionID Protected Error Information Register 7" hexmask.long.byte 0x1C 0.--7. 1. "SRCID_W" line.long 0x20 "PTRGNINF8,RegionID Protected Error Information Register 8" hexmask.long.byte 0x20 0.--7. 1. "SRCID_W" line.long 0x24 "PTRGNINF9,RegionID Protected Error Information Register 9" hexmask.long.byte 0x24 0.--7. 1. "SRCID_W" line.long 0x28 "PTRGNINF10,RegionID Protected Error Information Register 10" hexmask.long.byte 0x28 0.--7. 1. "SRCID_W" line.long 0x2C "PTRGNINF11,RegionID Protected Error Information Register 11" hexmask.long.byte 0x2C 0.--7. 1. "SRCID_W" line.long 0x30 "PTRGNINF12,RegionID Protected Error Information Register 12" hexmask.long.byte 0x30 0.--7. 1. "SRCID_W" line.long 0x34 "PTRGNINF13,RegionID Protected Error Information Register 13" hexmask.long.byte 0x34 0.--7. 1. "SRCID_W" line.long 0x38 "PTRGNINF14,RegionID Protected Error Information Register 14" hexmask.long 0x38 0.--31. 1. "ADR_R" line.long 0x3C "PTRGNINF15,RegionID Protected Error Information Register 15" hexmask.long 0x3C 0.--31. 1. "ADR_R" line.long 0x40 "PTRGNINF16,RegionID Protected Error Information Register 16" hexmask.long 0x40 0.--31. 1. "ADR_R" line.long 0x44 "PTRGNINF17,RegionID Protected Error Information Register 17" hexmask.long 0x44 0.--31. 1. "ADR_R" line.long 0x48 "PTRGNINF18,RegionID Protected Error Information Register 18" hexmask.long 0x48 0.--31. 1. "ADR_R" line.long 0x4C "PTRGNINF19,RegionID Protected Error Information Register 19" hexmask.long 0x4C 0.--31. 1. "ADR_R" line.long 0x50 "PTRGNINF20,RegionID Protected Error Information Register 20" hexmask.long 0x50 0.--31. 1. "ADR_R" line.long 0x54 "PTRGNINF21,RegionID Protected Error Information Register 21" hexmask.long.byte 0x54 0.--7. 1. "SRCID_R" line.long 0x58 "PTRGNINF22,RegionID Protected Error Information Register 22" hexmask.long.byte 0x58 0.--7. 1. "SRCID_R" line.long 0x5C "PTRGNINF23,RegionID Protected Error Information Register 23" hexmask.long.byte 0x5C 0.--7. 1. "SRCID_R" line.long 0x60 "PTRGNINF24,RegionID Protected Error Information Register 24" hexmask.long.byte 0x60 0.--7. 1. "SRCID_R" line.long 0x64 "PTRGNINF25,RegionID Protected Error Information Register 25" hexmask.long.byte 0x64 0.--7. 1. "SRCID_R" line.long 0x68 "PTRGNINF26,RegionID Protected Error Information Register 26" hexmask.long.byte 0x68 0.--7. 1. "SRCID_R" line.long 0x6C "PTRGNINF27,RegionID Protected Error Information Register 27" hexmask.long.byte 0x6C 0.--7. 1. "SRCID_R" line.long 0x70 "PTSECINF0,Secure Protected Error Information Register 0" hexmask.long 0x70 0.--31. 1. "ADR_W" line.long 0x74 "PTSECINF1,Secure Protected Error Information Register 1" hexmask.long 0x74 0.--31. 1. "ADR_W" hexmask.long 0x74 0.--31. 1. "ADR_R" hexmask.long.byte 0x74 0.--7. 1. "SRCID_R" line.long 0x78 "PTSECINF2,Secure Protected Error Information Register 2" hexmask.long 0x78 0.--31. 1. "ADR_W" hexmask.long.byte 0x78 0.--7. 1. "SRCID_R" line.long 0x7C "PTSECINF3,Secure Protected Error Information Register 3" hexmask.long 0x7C 0.--31. 1. "ADR_W" line.long 0x80 "PTSECINF4,Secure Protected Error Information Register 4" hexmask.long 0x80 0.--31. 1. "ADR_W" hexmask.long 0x80 0.--31. 1. "ADR_R" line.long 0x84 "PTSECINF5,Secure Protected Error Information Register 5" hexmask.long 0x84 0.--31. 1. "ADR_W" line.long 0x88 "PTSECINF6,Secure Protected Error Information Register 6" hexmask.long 0x88 0.--31. 1. "ADR_W" line.long 0x8C "PTSECINF7,Secure Protected Error Information Register 7" hexmask.long.byte 0x8C 0.--7. 1. "SRCID_W" line.long 0x90 "PTSECINF8,Secure Protected Error Information Register 8" hexmask.long.byte 0x90 0.--7. 1. "SRCID_W" line.long 0x94 "PTSECINF9,Secure Protected Error Information Register 9" hexmask.long.byte 0x94 0.--7. 1. "SRCID_W" line.long 0x98 "PTSECINF10,Secure Protected Error Information Register 10" hexmask.long.byte 0x98 0.--7. 1. "SRCID_W" line.long 0x9C "PTSECINF11,Secure Protected Error Information Register 11" hexmask.long.byte 0x9C 0.--7. 1. "SRCID_W" line.long 0xA0 "PTSECINF12,Secure Protected Error Information Register 12" hexmask.long.byte 0xA0 0.--7. 1. "SRCID_W" line.long 0xA4 "PTSECINF13,Secure Protected Error Information Register 13" hexmask.long.byte 0xA4 0.--7. 1. "SRCID_W" line.long 0xA8 "PTSECINF14,Secure Protected Error Information Register 14" hexmask.long 0xA8 0.--31. 1. "ADR_R" line.long 0xAC "PTSECINF15,Secure Protected Error Information Register 15" hexmask.long 0xAC 0.--31. 1. "ADR_R" line.long 0xB0 "PTSECINF16,Secure Protected Error Information Register 16" hexmask.long 0xB0 0.--31. 1. "ADR_R" line.long 0xB4 "PTSECINF17,Secure Protected Error Information Register 17" hexmask.long 0xB4 0.--31. 1. "ADR_R" line.long 0xB8 "PTSECINF18,Secure Protected Error Information Register 18" hexmask.long 0xB8 0.--31. 1. "ADR_R" line.long 0xBC "PTSECINF19,Secure Protected Error Information Register 19" hexmask.long 0xBC 0.--31. 1. "ADR_R" line.long 0xC0 "PTSECINF20,Secure Protected Error Information Register 20" hexmask.long 0xC0 0.--31. 1. "ADR_R" line.long 0xC4 "PTSECINF21,Secure Protected Error Information Register 21" hexmask.long.byte 0xC4 0.--7. 1. "SRCID_R" line.long 0xC8 "PTSECINF22,Secure Protected Error Information Register 22" hexmask.long.byte 0xC8 0.--7. 1. "SRCID_R" line.long 0xCC "PTSECINF23,Secure Protected Error Information Register 23" hexmask.long.byte 0xCC 0.--7. 1. "SRCID_R" line.long 0xD0 "PTSECINF24,Secure Protected Error Information Register 24" hexmask.long.byte 0xD0 0.--7. 1. "SRCID_R" line.long 0xD4 "PTSECINF25,Secure Protected Error Information Register 25" hexmask.long.byte 0xD4 0.--7. 1. "SRCID_R" line.long 0xD8 "PTSECINF26,Secure Protected Error Information Register 26" hexmask.long.byte 0xD8 0.--7. 1. "SRCID_R" line.long 0xDC "PTSECINF27,Secure Protected Error Information Register 27" hexmask.long.byte 0xDC 0.--7. 1. "SRCID_R" group.long 0x6700++0xF line.long 0x0 "EDCCAUSER,EDC Error Cause Register" bitfld.long 0x0 21. "PWDATA_EDC_ERR" "0,1" bitfld.long 0x0 20. "PADD_EDC_ERR" "0,1" bitfld.long 0x0 18. "NODE_INFERR_W" "0,1" bitfld.long 0x0 17. "NODE_INFERR_R" "0,1" newline bitfld.long 0x0 15. "BSTID_ERR_R" "0,1" bitfld.long 0x0 14. "RAM_EDC_ERR" "0,1" bitfld.long 0x0 13. "MMU_EDCERR_R" "0,1" bitfld.long 0x0 11. "CCI_EDCERR_R" "0,1" newline bitfld.long 0x0 10. "CCI_EDCERR_W" "0,1" bitfld.long 0x0 9. "PERI_EDCERR_R" "0,1" bitfld.long 0x0 8. "PERI_EDCERR_W" "0,1" bitfld.long 0x0 7. "MDA1_EDCERR_R" "0,1" newline bitfld.long 0x0 6. "MDA1_EDCERR_W" "0,1" bitfld.long 0x0 5. "MDA0_EDCERR_R" "0,1" bitfld.long 0x0 4. "MDA0_EDCERR_W" "0,1" bitfld.long 0x0 3. "RGX1_EDCERR_R" "0,1" newline bitfld.long 0x0 2. "RGX1_EDCERR_W" "0,1" bitfld.long 0x0 1. "RGX0_EDCERR_R" "0,1" bitfld.long 0x0 0. "RGX0_EDCERR_W" "0,1" line.long 0x4 "EDCERRCR0,EDC Error Control Register 0" bitfld.long 0x4 27. "MMU_EDCINJ_POST_R" "0,1" bitfld.long 0x4 26. "MMU_EDCINJ_POST_R" "0,1" bitfld.long 0x4 23. "CCI_EDCINJ_POST_R" "0,1" bitfld.long 0x4 22. "CCI_EDCINJ_PRE_R" "0,1" newline bitfld.long 0x4 21. "CCI_EDCINJ_POST_W" "0,1" bitfld.long 0x4 20. "CCI_EDCINJ_PRE_W" "0,1" bitfld.long 0x4 19. "PERI_EDCINJ_POST_R" "0,1" bitfld.long 0x4 18. "PERI_EDCINJ_PRE_R" "0,1" newline bitfld.long 0x4 17. "PERI_EDCINJ_POST_W" "0,1" bitfld.long 0x4 16. "PERI_EDCINJ_PRE_W" "0,1" bitfld.long 0x4 15. "MDA1_EDCINJ_POST_R" "0,1" bitfld.long 0x4 14. "MDA1_EDCINJ_PRE_R" "0,1" newline bitfld.long 0x4 13. "MDA1_EDCINJ_POST_W" "0,1" bitfld.long 0x4 12. "MDA1_EDCINJ_PRE_W" "0,1" bitfld.long 0x4 11. "MDA0_EDCINJ_POST_R" "0,1" bitfld.long 0x4 10. "MDA0_EDCINJ_PRE_R" "0,1" newline bitfld.long 0x4 9. "MDA0_EDCINJ_POST_W" "0,1" bitfld.long 0x4 8. "MDA0_EDCINJ_PRE_W" "0,1" bitfld.long 0x4 7. "RGX1_EDCINJ_POST_R" "0,1" bitfld.long 0x4 6. "RGX1_EDCINJ_PRE_R" "0,1" newline bitfld.long 0x4 5. "RGX1_EDCINJ_POST_W" "0,1" bitfld.long 0x4 4. "RGX1_EDCINJ_PRE_W" "0,1" bitfld.long 0x4 3. "RGX0_EDCINJ_POST_R" "0,1" bitfld.long 0x4 2. "RGX0_EDCINJ_PRE_R" "0,1" newline bitfld.long 0x4 1. "RGX0_EDCINJ_POST_W" "0,1" bitfld.long 0x4 0. "RGX0_EDCINJ_PRE_W" "0,1" line.long 0x8 "EDCERRCR1,EDC Error Control Register 1" bitfld.long 0x8 4. "NODE_ERRINJ_W" "0,1" bitfld.long 0x8 3. "NODE_ERRINJ_R" "0,1" bitfld.long 0x8 1. "BSTID_ERRINJ_R" "0,1" bitfld.long 0x8 0. "RAM_EDCINJ" "0,1" line.long 0xC "EDCERRCR2,EDC Error Control Register 2" bitfld.long 0xC 3. "PWDATA_EDCINJ_POST" "0,1" bitfld.long 0xC 2. "PWDATA_EDCINJ_PRE" "0,1" bitfld.long 0xC 1. "PADD_EDCINJ_POST" "0,1" bitfld.long 0xC 0. "PADD_EDCINJ_PRE" "0,1" rgroup.long 0x6710++0x4B line.long 0x0 "EDCERRINF0,EDC Error Information Register 0" hexmask.long.byte 0x0 0.--7. 1. "SRCIF" line.long 0x4 "EDCERRINF1,EDC Error Information Register 1" hexmask.long.byte 0x4 0.--7. 1. "SRCIF" line.long 0x8 "EDCERRINF2,EDC Error Information Register 2" hexmask.long.byte 0x8 0.--7. 1. "SRCIF" line.long 0xC "EDCERRINF3,EDC Error Information Register 3" hexmask.long.byte 0xC 0.--7. 1. "SRCIF" line.long 0x10 "EDCERRINF4,EDC Error Information Register 4" hexmask.long.byte 0x10 0.--7. 1. "SRCIF" line.long 0x14 "EDCERRINF5,EDC Error Information Register 5" hexmask.long.byte 0x14 0.--7. 1. "SRCIF" line.long 0x18 "EDCERRINF6,EDC Error Information Register 6" hexmask.long.byte 0x18 0.--7. 1. "SRCIF" line.long 0x1C "EDCERRINF7,EDC Error Information Register 7" hexmask.long.byte 0x1C 0.--7. 1. "SRCIF" line.long 0x20 "EDCERRINF8,EDC Error Information Register 8" hexmask.long.byte 0x20 0.--7. 1. "SRCIF" line.long 0x24 "EDCERRINF9,EDC Error Information Register 9" hexmask.long.byte 0x24 0.--7. 1. "SRCIF" line.long 0x28 "EDCERRINF10,EDC Error Information Register 10" hexmask.long.byte 0x28 0.--7. 1. "SRCIF" line.long 0x2C "EDCERRINF11,EDC Error Information Register 11" hexmask.long.byte 0x2C 0.--7. 1. "SRCIF" line.long 0x30 "EDCERRINF12,EDC Error Information Register 12" hexmask.long.byte 0x30 0.--7. 1. "SRCIF" line.long 0x34 "EDCERRINF13,EDC Error Information Register 13" hexmask.long.byte 0x34 0.--7. 1. "SRCIF" line.long 0x38 "EDCERRINF14,EDC Error Information Register 14" hexmask.long.byte 0x38 0.--7. 1. "SRCIF" line.long 0x3C "EDCERRINF15,EDC Error Information Register 15" hexmask.long.byte 0x3C 0.--7. 1. "SRCIF" line.long 0x40 "EDCERRINF16,EDC Error Information Register 16" hexmask.long.byte 0x40 0.--7. 1. "SRCIF" line.long 0x44 "EDCERRINF17,EDC Error Information Register 17" hexmask.long.byte 0x44 0.--7. 1. "SRCIF" line.long 0x48 "EDCERRINF18,EDC Error Information Register 18" hexmask.long.byte 0x48 0.--7. 1. "SRCIF" group.long 0x6800++0x3 line.long 0x0 "DCLSERRCR,DCLS Error Control Register" bitfld.long 0x0 1. "DCLS_INJ_POST" "0,1" bitfld.long 0x0 0. "DCLS_INJ_PRE" "0,1" tree.end tree "BKBUF" base ad:0xE6150000 group.long 0x278++0x3 line.long 0x0 "BKBAPR,[Legend]" bitfld.long 0x0 1. "BKBAP,Enables or disables protection of the data storage in the back-up buffer. *1 *2" "0: Enables protection of the data storage in the..,1: Disables protection of the data storage in the.." tree.end tree "CMT_0" base ad:0xE60F0000 tree.end tree "CMT_1" base ad:0xE6130000 tree.end tree "CMT_2" base ad:0xE6140000 tree.end tree "CMT_3" base ad:0xE6148000 tree.end tree "CPG" base ad:0xE6150000 group.long 0x0++0xB line.long 0x0 "CPGWPR,CPGWPR is a 32-bit readable/writable register. CPGWPR enables/disables writing to all registers in CPG except for CPGWPCR." hexmask.long 0x0 0.--31. 1. "WPRTCT,Writing a value to CPG registers is enabled by writing the inverse of the value to this register." line.long 0x4 "CPGWPCR,CPGWPR is a 32-bit readable/writable register." bitfld.long 0x4 0. "WPE,Write protect enable" "0: Disable the write protect,1: Enable the write protect" line.long 0x8 "RSSDER,RSSDER is a 32-bit readable/writable register. RSSDE (bit 31) is used for enable or disable RS function (Resume Standby for SRAM). In addition. the programmable registers are supported to control the timing b/w module stop signal and RS signal. In.." bitfld.long 0x8 31. "RSSDE,Control for supporting RS (Resume Standby) function." "0: Disable all RS signals,1: Enable all RS signals" newline hexmask.long.byte 0x8 16.--23. 1. "HOLD_CYC,HOLD_CYC[7:0] indicates the number of cycles (CL16M: 16.66MHz) from MSTP active to RS active." newline hexmask.long.byte 0x8 0.--7. 1. "SETUP_CYC,SETUP_CYC[7:0] indicates the number of cycles (CL16M: 16.66MHz) from RS de-active to MSTP de-active." rgroup.long 0x108++0x3 line.long 0x0 "STAEMON,N/A" group.long 0x278++0xB line.long 0x0 "ATSTPOFFR,Image Recognition Engine (IMP-X6) supports a function of stopping the clock automatically (Clock gear function). ATSTPOFFR can disables the function. In detail. see the below." bitfld.long 0x0 31. "IMPRAM,This bit controls the enable or disable of clock gear function for IMPRAM.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 30. "IMPDMA1,This bit controls the enable or disable of clock gear function for IMP-DMAC1.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 29. "IMPDMA0,This bit controls the enable or disable of clock gear function for IMP-DMAC0.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 28. "IMPPSC1,This bit controls the enable or disable of clock gear function for IMP-PSC1.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 27. "IMPPSC0,This bit controls the enable or disable of clock gear function for IMP-PSC0.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 26. "CNN2,This bit controls the enable or disable of clock gear function for IMP-CNN2.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 25. "CNN1,This bit controls the enable or disable of clock gear function for IMP-CNN1.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 24. "CNN0,This bit controls the enable or disable of clock gear function for IMP-CNN0.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 23. "OCV7,This bit controls the enable or disable of clock gear function for IMP-OCV7.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 22. "OCV6,This bit controls the enable or disable of clock gear function for IMP-OCV6.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 21. "OCV5,This bit controls the enable or disable of clock gear function for IMP-OCV5.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 20. "OCV4,This bit controls the enable or disable of clock gear function for IMP-OCV4.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 19. "OCV3,This bit controls the enable or disable of clock gear function for IMP-OCV3.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 18. "OCV2,This bit controls the enable or disable of clock gear function for IMP-OCV2.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 17. "OCV1,This bit controls the enable or disable of clock gear function for IMP-OCV1.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 16. "OCV0,This bit controls the enable or disable of clock gear function for IMP-OCV0.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 15. "IMP3,This bit controls the enable or disable of clock gear function for IMP-Core3.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 14. "IMP2,This bit controls the enable or disable of clock gear function for IMP-Core2.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 13. "IMP1,This bit controls the enable or disable of clock gear function for IMP-Core1.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 12. "IMP0,This bit controls the enable or disable of clock gear function for IMP-Core0.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 11. "IMR-LX4ch5,This bit controls the enable or disable of clock gear function for IMR-LX4 ch5.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 10. "IMR-LX4ch4,This bit controls the enable or disable of clock gear function for IMR-LX4 ch4.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 9. "IMR-LX4ch3,This bit controls the enable or disable of clock gear function for IMR-LX4 ch3.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 8. "IMR-LX4ch2,This bit controls the enable or disable of clock gear function for IMR-LX4 ch2.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 7. "IMR-LX4ch1,This bit controls the enable or disable of clock gear function for IMR-LX4 ch1.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 6. "IMR-LX4ch0,This bit controls the enable or disable of clock gear function for IMR-LX4 ch0.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." newline bitfld.long 0x0 5. "LDMAC,This bit controls the enable or disable of clock gear function for IMP-LSDC-DMAC.1: Disable the function of stopping the clock automatically0: Enable of the function of stopping the clock automatically" "?,1: Disable the function of stopping the clock.." line.long 0x4 "RTSRAMCR,CPG outputs 'cl_raminit_sysram_p' signal for system memory in Real-Time domain (2MB(data)+128kB(ECC))." bitfld.long 0x4 0. "INRAM,Select running or not of RT-SRAM initialization routine when the reset for RT-SRAM is de-asserted." "0: Initialization routine doesn’t run at the..,1: Initialization routine runs at the de-assert of.." line.long 0x8 "BKBAPR,CPG outputs 'cl_bkbap_bkbuf_a' signal for Backup Buffer (u779ahbkbuf0top0) in Real-Time domain. In detail specification such as reset condition. access condition. and so on. see the below." bitfld.long 0x8 0. "BKBAPR,Enables or disables protection of the data storage in the Backup Buffer." "0: Enables protection of the data storage in the..,1: Disables protection of the data storage in the.." rgroup.long 0x400++0x3 line.long 0x0 "FSRCHKRA[n],FSRCHKRAn is a 32-bit readable register. Each bit of these registers can be set by writing 1 to the corresponding bit of FSRCHKSETRn. Each bit is cleared by the reset signal of the module assigned to each bit. Each bit can be also cleared by.." hexmask.long 0x0 0.--31. 1. "RCHK,[Set Condition]" rgroup.long 0x480++0x3 line.long 0x0 "FSRCHKRB[n],FSRCHKRBn is a 32-bit readable register. Each bit of these registers can be set by writing 1 to the corresponding bit of FSRCHKSETRn. Each bit is cleared by the reset signal of the module assigned to each bit. Each bit can be also cleared by.." hexmask.long 0x0 0.--31. 1. "RCHK,[Set Condition]" wgroup.long 0x500++0x3 line.long 0x0 "FSRCHKSETR[n],FSRCHKSETRn is a 32-bit writable register. When writing 1 to the designated bit of FSRCHKSETRn. the corresponding bits of both FSRCHKRAn and FSRCHKRBn are set to 1. Writing 0 to each bit of FSRCHKSETRn does not change the values of.." hexmask.long 0x0 0.--31. 1. "RSET,When writing 1 to RSETm of FSRCHKSETRn RCHKm bits of both FSRCHKRAn and FSRCHKRBn are set to 1. Writing 0 to each bit of FSRCHKSETRn does not change the values of FSRCHKRAn and FSRCHKRBn." wgroup.long 0x580++0x3 line.long 0x0 "FSRCHKCLRR[n],FSRCHKCLRRn is a 32-bit writable register. When writing 1 to the designated bit of FSRCHKCLRRn. the corresponding bits of both FSRCHKRAn and FSRCHKRBn are cleared to 0. Writing 0 to each bit of FSRCHKCLRRn does not change the values of.." hexmask.long 0x0 0.--31. 1. "RCLR,When writing 1 to RCLRm of FSRCHKCLRRn RCHKm bits of both FSRCHKRAn and FSRCHKRBn are cleared to 0. Writing 0 to each bit of FSRCHKCLRRn does not change the values of FSRCHKRAn and FSRCHKRBn." group.long 0x740++0x3 line.long 0x0 "ECMERRINJR,This register is prepared to meet the requirement from FuSa. . Before NSI-Reset. ECM send the request signal to CPG. To detect failure of the connection b/w ECM and CPG. Error injection function is newly implemented. Intentional error is.." bitfld.long 0x0 3. "NSIRSTMSK,NSI-Reset trigger signal can be masked. It means NSI-Reset function is disable." "0: Signal from CPG to ECM is 1'b0 even if NSI-Reset..,1: Signal from CPG to ECM is 1'b1 when NSI-Reset.." newline rbitfld.long 0x0 2. "ERRCHK,Read Error Injection value." "0,1" newline bitfld.long 0x0 1. "NSIRSTMSK,NSI-Reset trigger signal can be masked. It means NSI-Reset function is disable." "0: Signal from CPG to ECM is 1'b0 even if NSI-Reset..,1: Signal from CPG to ECM is 1'b1 when NSI-Reset.." newline rbitfld.long 0x0 0. "ERRCHKRDN,Read Error Injection value." "0,1" group.long 0x800++0x13 line.long 0x0 "FRQCRA,FRQCRA is a 32-bit readable/writable register. This registers specifies the frequency division ratios of System Clock (SGɸ. S1ɸ. and S3ɸ). In User-Case. there is no case of changing System Clock frequency after booting. in terms of security and.." hexmask.long.byte 0x0 20.--23. 1. "SGFC,System Clock (SGɸ) Frequency division ratio. In User-Case SGɸ is 1066MHz" newline hexmask.long.byte 0x0 16.--19. 1. "S1FC,System Clock (S1ɸ) Frequency division ratio. In User-Case S1ɸ is 533MHz" newline hexmask.long.byte 0x0 12.--15. 1. "S3FC,System Clock (S3ɸ) Frequency division ratio. In User-Case S3ɸ is 266MHz" line.long 0x4 "FRQCRB,FRQCRB is a 32-bit readable/writable register. This registers specifies the frequency division ratios of Debug Trace port clock (ZTRɸ). Debug Trace bus clock (ZTɸ). and Debug clock (ZSɸ). These clocks are supplied only in debugging mode. And..." bitfld.long 0x4 31. "KICK,KICK bit. Setting 1 to this register activates the FRQCRB setting." "0,1" newline hexmask.long.byte 0x4 24.--28. 1. "ZGFC,GPU Clock (ZGɸ) Frequency division ratio. Division ratio formula = (32-Setting)/32." newline hexmask.long.byte 0x4 20.--23. 1. "ZTRFC,Debug Trace port clock (ZTRɸ) Frequency division ratio." newline hexmask.long.byte 0x4 16.--19. 1. "ZTFC,Debug Trace port clock (ZTɸ) Frequency division ratio." newline hexmask.long.byte 0x4 12.--15. 1. "ZSFC,Debug Trace port clock (ZSɸ) Frequency division ratio." line.long 0x8 "FRQCRC,FRQCRC is a 32-bit readable/writable register. This registers specifies the frequency division ratios of Realtime CPU clock (ZRɸ). System CPU clock (Z0ɸ and Z1ɸ). When division ratio of these clocks is changed. any other clock division ratio.." hexmask.long.byte 0x8 16.--20. 1. "ZRFC,Realtime CPU (Cortex-R52) Clock (ZRɸ) Frequency Division Ratio." newline hexmask.long.byte 0x8 8.--12. 1. "Z1FC,System CPU (ENYO1) Clock (Z1ɸ) Frequency Division Ratio." newline hexmask.long.byte 0x8 0.--4. 1. "Z0FC,System CPU (ENYO0) Clock (Z0ɸ) Frequency Division Ratio." line.long 0xC "FRQCRD0,Frequency Control Register D 0" bitfld.long 0xC 31. "KICK,KICK bit. Setting 1 to this register activates the FRQCRD setting." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "ZB30FC,ZB30ɸ clock for DDR/DBSC frequency division ratio is set." line.long 0x10 "FRQCRD1,Frequency Control Register D 1" bitfld.long 0x10 31. "KICK,KICK bit. Setting 1 to this register activates the FRQCRD setting." "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "ZB31FC,ZB31ɸ clock for DDR/DBSC frequency division ratio is set." group.long 0x820++0x3 line.long 0x0 "PLLECR,PLL Enable Control Register" rbitfld.long 0x0 14. "PLL5ST,PLL circuit 5 status. Displays PLL circuit 5 status (on or off)." "0: PLL circuit 5 is turned off,1: PLL circuit 5 is turned on" newline rbitfld.long 0x0 13. "PLL4ST,PLL circuit 4 status. Displays PLL circuit 4 status (on or off)." "0: PLL circuit 4 is turned off,1: PLL circuit 4 is turned on" newline rbitfld.long 0x0 12. "PLL31ST,PLL circuit 31 status. Displays PLL circuit 31 status (on or off)." "0: PLL circuit 31 is turned off,1: PLL circuit 31 is turned on" newline rbitfld.long 0x0 11. "PLL30ST,PLL circuit 30 status. Displays PLL circuit 30 status (on or off)." "0: PLL circuit 30 is turned off,1: PLL circuit 30 is turned on" newline rbitfld.long 0x0 10. "PLL21ST,PLL circuit 21 status. Displays PLL circuit 21 status (on or off)." "0: PLL circuit 21 is turned off,1: PLL circuit 21 is turned on" newline rbitfld.long 0x0 9. "PLL20ST,PLL circuit 20 status. Displays PLL circuit 20 status (on or off)." "0: PLL circuit 20 is turned off,1: PLL circuit 20 is turned on" newline rbitfld.long 0x0 8. "PLL1ST,PLL circuit 1 status. Displays PLL circuit 1 status (on or off)." "0: PLL circuit 1 is turned off,1: PLL circuit 1 is turned on" newline bitfld.long 0x0 6. "PLL5E,PLL circuit 5 enable. Turns PLL circuit 5 on or off. Actual status of PLL5 is shown in PLL5ST bit." "0: Turns off PLL circuit 5,1: Turns on PLL circuit 5" newline bitfld.long 0x0 5. "PLL4E,PLL circuit 4 enable. Turns PLL circuit 4 on or off. Actual status of PLL4 is shown in PLL4ST bit." "0: Turns off PLL circuit 4,1: Turns on PLL circuit 4" newline bitfld.long 0x0 4. "PLL31E,PLL circuit 31 enable. Turns PLL circuit 31 on or off. Actual status of PLL31 is shown in PLL31ST bit." "0: Turns off PLL circuit 31,1: Turns on PLL circuit 31" newline bitfld.long 0x0 3. "PLL30E,PLL circuit 30 enable. Turns PLL circuit 30 on or off. Actual status of PLL30 is shown in PLL30ST bit." "0: Turns off PLL circuit 30,1: Turns on PLL circuit 30" newline bitfld.long 0x0 2. "PLL21E,PLL circuit 21 enable. Turns PLL circuit 21 on or off. Actual status of PLL21 is shown in PLL21ST bit." "0: Turns off PLL circuit 21,1: Turns on PLL circuit 21" newline bitfld.long 0x0 1. "PLL20E,PLL circuit 20 enable. Turns PLL circuit 20 on or off. Actual status of PLL20 is shown in PLL20ST bit." "0: Turns off PLL circuit 20,1: Turns on PLL circuit 20" newline bitfld.long 0x0 0. "PLL1E,PLL circuit 1 enable. Turns PLL circuit 1 on or off. Actual status of PLL1 is shown in PLL1ST bit." "0: Turns off PLL circuit 1,1: Turns on PLL circuit 1" group.long 0x830++0x1B line.long 0x0 "PLL1CR,PLL1 Control Register" hexmask.long.byte 0x0 24.--30. 1. "STC,PLL circuit 1 Multiplication Ratio." newline bitfld.long 0x0 7. "CKSEL,PLL circuit 1 source clock select" "0,1" line.long 0x4 "PLL20CR,PLL20 Control Register" hexmask.long.byte 0x4 24.--30. 1. "STC,PLL circuit 20 Multiplication Ratio." newline bitfld.long 0x4 7. "CKSEL,PLL circuit 20 source clock select" "0,1" line.long 0x8 "PLL21CR,PLL21 Control Register" hexmask.long.byte 0x8 24.--30. 1. "STC,PLL circuit 21 Multiplication Ratio." newline bitfld.long 0x8 7. "CKSEL,PLL circuit 20 source clock select" "0,1" line.long 0xC "PLL30CR,PLL30 Control Register" hexmask.long.byte 0xC 24.--30. 1. "STC,PLL circuit 30 Multiplication Ratio." newline bitfld.long 0xC 7. "CKSEL,PLL circuit 30 source clock select" "0,1" line.long 0x10 "PLL31CR,PLL31 Control Register" hexmask.long.byte 0x10 24.--30. 1. "STC,PLL circuit 31 Multiplication Ratio." newline bitfld.long 0x10 7. "CKSEL,PLL circuit 31 source clock select" "0,1" line.long 0x14 "PLL4CR,PLL4 Control Register" hexmask.long.byte 0x14 24.--30. 1. "STC,PLL circuit 4 Multiplication Ratio." newline bitfld.long 0x14 7. "CKSEL,PLL circuit 4 source clock select" "0,1" line.long 0x18 "PLL5CR,PLL5 Control Register" hexmask.long.byte 0x18 24.--30. 1. "STC,PLL circuit 5 Multiplication Ratio." newline bitfld.long 0x18 7. "CKSEL,PLL circuit 4 source clock select" "0,1" group.long 0x850++0x1B line.long 0x0 "PLL1STPCR,PLL1STPCR is a 32-bit readable/writable register. This register specifies the stop condition of PLL circuit 1 when PLLECR.PLL1E is set to 1. If the power supply status meets the stop condition of PLL circuit n specified by this register (all of.." bitfld.long 0x0 20. "A3IRSTP,PLL circuit 1 Stop Condition by IMP domain (A3IR) Power Status" "0,1" newline bitfld.long 0x0 14. "3DGBSTP,PLL circuit 1 Stop Condition by 3DG-B (GPU) Power Status" "0,1" newline bitfld.long 0x0 13. "A3ISP23STP,PLL circuit 1 Stop Condition by A3ISP23 (ISP3 and ISP2 core) Power Status" "0,1" newline bitfld.long 0x0 12. "A3ISP01STP,PLL circuit 1 Stop Condition by A3ISP01 (ISP1 and ISP0 core) Power Status" "0,1" newline bitfld.long 0x0 9. "A2E1D1STP,PLL circuit 1 Stop Condition by ENYOSS1 cluster 1 domain (A2E1D1) Power Status" "0,1" newline bitfld.long 0x0 8. "A2E1D0STP,PLL circuit 1 Stop Condition by ENYOSS1 cluster 0 domain (A2E1D0) Power Status" "0,1" newline bitfld.long 0x0 7. "A2E0D1STP,PLL circuit 1 Stop Condition by ENYOSS0 cluster 1 domain (A2E0D1) Power Status" "0,1" newline bitfld.long 0x0 6. "A2E0D0STP,PLL circuit 1 Stop Condition by ENYOSS0 cluster 0 domain (A2E0D0) Power Status" "0,1" newline bitfld.long 0x0 3. "A3VIP3STP,PLL circuit 1 Stop Condition by A3VIP3 Power Status" "0,1" newline bitfld.long 0x0 2. "A3VIP2STP,PLL circuit 1 Stop Condition by A3VIP2 Power Status" "0,1" newline bitfld.long 0x0 1. "A3VIP1STP,PLL circuit 1 Stop Condition by A3VIP1 Power Status" "0,1" newline bitfld.long 0x0 0. "A3VIP0STP,PLL circuit 1 Stop Condition by A3VIP0 Power Status" "0,1" line.long 0x4 "PLL20STPCR,PLL20STPCR is a 32-bit readable/writable register. This register specifies the stop condition of PLL circuit 20 when PLLECR.PLL20E is set to 1. If the power supply status meets the stop condition of PLL circuit n specified by this register.." bitfld.long 0x4 20. "A3IRSTP,PLL circuit 20 Stop Condition by IMP domain (A3IR) Power Status" "0,1" newline bitfld.long 0x4 14. "3DGBSTP,PLL circuit 20 Stop Condition by 3DG-B (GPU) Power Status" "0,1" newline bitfld.long 0x4 13. "A3ISP23STP,PLL circuit 20 Stop Condition by A3ISP23 (ISP3 and ISP2 core) Power Status" "0,1" newline bitfld.long 0x4 12. "A3ISP01STP,PLL circuit 20 Stop Condition by A3ISP01 (ISP1 and ISP0 core) Power Status" "0,1" newline bitfld.long 0x4 9. "A2E1D1STP,PLL circuit 20 Stop Condition by ENYOSS1 cluster 1 domain (A2E1D1) Power Status" "0,1" newline bitfld.long 0x4 8. "A2E1D0STP,PLL circuit 20 Stop Condition by ENYOSS1 cluster 0 domain (A2E1D0) Power Status" "0,1" newline bitfld.long 0x4 7. "A2E0D1STP,PLL circuit 20 Stop Condition by ENYOSS0 cluster 1 domain (A2E0D1) Power Status" "0,1" newline bitfld.long 0x4 6. "A2E0D0STP,PLL circuit 20 Stop Condition by ENYOSS0 cluster 0 domain (A2E0D0) Power Status" "0,1" newline bitfld.long 0x4 3. "A3VIP3STP,PLL circuit 20 Stop Condition by A3VIP3 Power Status" "0,1" newline bitfld.long 0x4 2. "A3VIP2STP,PLL circuit 20 Stop Condition by A3VIP2 Power Status" "0,1" newline bitfld.long 0x4 1. "A3VIP1STP,PLL circuit 20 Stop Condition by A3VIP1 Power Status" "0,1" newline bitfld.long 0x4 0. "A3VIP0STP,PLL circuit 20 Stop Condition by A3VIP0 Power Status" "0,1" line.long 0x8 "PLL21STPCR,PLL21STPCR is a 32-bit readable/writable register. This register specifies the stop condition of PLL circuit 21 when PLLECR.PLL21E is set to 1. If the power supply status meets the stop condition of PLL circuit n specified by this register.." bitfld.long 0x8 20. "A3IRSTP,PLL circuit 21 Stop Condition by IMP domain (A3IR) Power Status" "0,1" newline bitfld.long 0x8 14. "3DGBSTP,PLL circuit 21 Stop Condition by 3DG-B (GPU) Power Status" "0,1" newline bitfld.long 0x8 13. "A3ISP23STP,PLL circuit 21 Stop Condition by A3ISP23 (ISP3 and ISP2 core) Power Status" "0,1" newline bitfld.long 0x8 12. "A3ISP01STP,PLL circuit 21 Stop Condition by A3ISP01 (ISP1 and ISP0 core) Power Status" "0,1" newline bitfld.long 0x8 9. "A2E1D1STP,PLL circuit 21 Stop Condition by ENYOSS1 cluster 1 domain (A2E1D1) Power Status" "0,1" newline bitfld.long 0x8 8. "A2E1D0STP,PLL circuit 21 Stop Condition by ENYOSS1 cluster 0 domain (A2E1D0) Power Status" "0,1" newline bitfld.long 0x8 7. "A2E0D1STP,PLL circuit 21 Stop Condition by ENYOSS0 cluster 1 domain (A2E0D1) Power Status" "0,1" newline bitfld.long 0x8 6. "A2E0D0STP,PLL circuit 21 Stop Condition by ENYOSS0 cluster 0 domain (A2E0D0) Power Status" "0,1" newline bitfld.long 0x8 3. "A3VIP3STP,PLL circuit 21 Stop Condition by A3VIP3 Power Status" "0,1" newline bitfld.long 0x8 2. "A3VIP2STP,PLL circuit 21 Stop Condition by A3VIP2 Power Status" "0,1" newline bitfld.long 0x8 1. "A3VIP1STP,PLL circuit 21 Stop Condition by A3VIP1 Power Status" "0,1" newline bitfld.long 0x8 0. "A3VIP0STP,PLL circuit 21 Stop Condition by A3VIP0 Power Status" "0,1" line.long 0xC "PLL30STPCR,PLL30STPCR is a 32-bit readable/writable register. This register specifies the stop condition of PLL circuit 30 when PLLECR.PLL30E is set to 1. If the power supply status meets the stop condition of PLL circuit n specified by this register.." bitfld.long 0xC 20. "A3IRSTP,PLL circuit 30 Stop Condition by IMP domain (A3IR) Power Status" "0,1" newline bitfld.long 0xC 14. "3DGBSTP,PLL circuit 30 Stop Condition by 3DG-B (GPU) Power Status" "0,1" newline bitfld.long 0xC 13. "A3ISP23STP,PLL circuit 30 Stop Condition by A3ISP23 (ISP3 and ISP2 core) Power Status" "0,1" newline bitfld.long 0xC 12. "A3ISP01STP,PLL circuit 30 Stop Condition by A3ISP01 (ISP1 and ISP0 core) Power Status" "0,1" newline bitfld.long 0xC 9. "A2E1D1STP,PLL circuit 30 Stop Condition by ENYOSS1 cluster 1 domain (A2E1D1) Power Status" "0,1" newline bitfld.long 0xC 8. "A2E1D0STP,PLL circuit 30 Stop Condition by ENYOSS1 cluster 0 domain (A2E1D0) Power Status" "0,1" newline bitfld.long 0xC 7. "A2E0D1STP,PLL circuit 30 Stop Condition by ENYOSS0 cluster 1 domain (A2E0D1) Power Status" "0,1" newline bitfld.long 0xC 6. "A2E0D0STP,PLL circuit 30 Stop Condition by ENYOSS0 cluster 0 domain (A2E0D0) Power Status" "0,1" newline bitfld.long 0xC 3. "A3VIP3STP,PLL circuit 30 Stop Condition by A3VIP3 Power Status" "0,1" newline bitfld.long 0xC 2. "A3VIP2STP,PLL circuit 30 Stop Condition by A3VIP2 Power Status" "0,1" newline bitfld.long 0xC 1. "A3VIP1STP,PLL circuit 30 Stop Condition by A3VIP1 Power Status" "0,1" newline bitfld.long 0xC 0. "A3VIP0STP,PLL circuit 30 Stop Condition by A3VIP0 Power Status" "0,1" line.long 0x10 "PLL31STPCR,PLL31STPCR is a 32-bit readable/writable register. This register specifies the stop condition of PLL circuit 31 when PLLECR.PLL31E is set to 1. If the power supply status meets the stop condition of PLL circuit n specified by this register.." bitfld.long 0x10 20. "A3IRSTP,PLL circuit 31 Stop Condition by IMP domain (A3IR) Power Status" "0,1" newline bitfld.long 0x10 14. "3DGBSTP,PLL circuit 31 Stop Condition by 3DG-B (GPU) Power Status" "0,1" newline bitfld.long 0x10 13. "A3ISP23STP,PLL circuit 31 Stop Condition by A3ISP23 (ISP3 and ISP2 core) Power Status" "0,1" newline bitfld.long 0x10 12. "A3ISP01STP,PLL circuit 31 Stop Condition by A3ISP01 (ISP1 and ISP0 core) Power Status" "0,1" newline bitfld.long 0x10 9. "A2E1D1STP,PLL circuit 31 Stop Condition by ENYOSS1 cluster 1 domain (A2E1D1) Power Status" "0,1" newline bitfld.long 0x10 8. "A2E1D0STP,PLL circuit 31 Stop Condition by ENYOSS1 cluster 0 domain (A2E1D0) Power Status" "0,1" newline bitfld.long 0x10 7. "A2E0D1STP,PLL circuit 31 Stop Condition by ENYOSS0 cluster 1 domain (A2E0D1) Power Status" "0,1" newline bitfld.long 0x10 6. "A2E0D0STP,PLL circuit 31 Stop Condition by ENYOSS0 cluster 0 domain (A2E0D0) Power Status" "0,1" newline bitfld.long 0x10 3. "A3VIP3STP,PLL circuit 31 Stop Condition by A3VIP3 Power Status" "0,1" newline bitfld.long 0x10 2. "A3VIP2STP,PLL circuit 31 Stop Condition by A3VIP2 Power Status" "0,1" newline bitfld.long 0x10 1. "A3VIP1STP,PLL circuit 31 Stop Condition by A3VIP1 Power Status" "0,1" newline bitfld.long 0x10 0. "A3VIP0STP,PLL circuit 31 Stop Condition by A3VIP0 Power Status" "0,1" line.long 0x14 "PLL4STPCR,PLL4STPCR is a 32-bit readable/writable register. This register specifies the stop condition of PLL circuit 4 when PLLECR.PLL4E is set to 1. If the power supply status meets the stop condition of PLL circuit n specified by this register (all of.." bitfld.long 0x14 20. "A3IRSTP,PLL circuit 4 Stop Condition by IMP domain (A3IR) Power Status" "0,1" newline bitfld.long 0x14 14. "3DGBSTP,PLL circuit 4 Stop Condition by 3DG-B (GPU) Power Status" "0,1" newline bitfld.long 0x14 13. "A3ISP23STP,PLL circuit 4 Stop Condition by A3ISP23 (ISP3 and ISP2 core) Power Status" "0,1" newline bitfld.long 0x14 12. "A3ISP01STP,PLL circuit 4 Stop Condition by A3ISP01 (ISP1 and ISP0 core) Power Status" "0,1" newline bitfld.long 0x14 9. "A2E1D1STP,PLL circuit 4 Stop Condition by ENYOSS1 cluster 1 domain (A2E1D1) Power Status" "0,1" newline bitfld.long 0x14 8. "A2E1D0STP,PLL circuit 4 Stop Condition by ENYOSS1 cluster 0 domain (A2E1D0) Power Status" "0,1" newline bitfld.long 0x14 7. "A2E0D1STP,PLL circuit 4 Stop Condition by ENYOSS0 cluster 1 domain (A2E0D1) Power Status" "0,1" newline bitfld.long 0x14 6. "A2E0D0STP,PLL circuit 4 Stop Condition by ENYOSS0 cluster 0 domain (A2E0D0) Power Status" "0,1" newline bitfld.long 0x14 3. "A3VIP3STP,PLL circuit 4 Stop Condition by A3VIP3 Power Status" "0,1" newline bitfld.long 0x14 2. "A3VIP2STP,PLL circuit 4 Stop Condition by A3VIP2 Power Status" "0,1" newline bitfld.long 0x14 1. "A3VIP1STP,PLL circuit 4 Stop Condition by A3VIP1 Power Status" "0,1" newline bitfld.long 0x14 0. "A3VIP0STP,PLL circuit 4 Stop Condition by A3VIP0 Power Status" "0,1" line.long 0x18 "PLL5STPCR,PLL5STPCR is a 32-bit readable/writable register. This register specifies the stop condition of PLL circuit 5 when PLLECR.PLL5E is set to 1. If the power supply status meets the stop condition of PLL circuit n specified by this register (all of.." bitfld.long 0x18 20. "A3IRSTP,PLL circuit 5 Stop Condition by IMP domain (A3IR) Power Status" "0,1" newline bitfld.long 0x18 14. "3DGBSTP,PLL circuit 5 Stop Condition by 3DG-B (GPU) Power Status" "0,1" newline bitfld.long 0x18 13. "A3ISP23STP,PLL circuit 5 Stop Condition by A3ISP23 (ISP3 and ISP2 core) Power Status" "0,1" newline bitfld.long 0x18 12. "A3ISP01STP,PLL circuit 5 Stop Condition by A3ISP01 (ISP1 and ISP0 core) Power Status" "0,1" newline bitfld.long 0x18 9. "A2E1D1STP,PLL circuit 5 Stop Condition by ENYOSS1 cluster 1 domain (A2E1D1) Power Status" "0,1" newline bitfld.long 0x18 8. "A2E1D0STP,PLL circuit 5 Stop Condition by ENYOSS1 cluster 0 domain (A2E1D0) Power Status" "0,1" newline bitfld.long 0x18 7. "A2E0D1STP,PLL circuit 5 Stop Condition by ENYOSS0 cluster 1 domain (A2E0D1) Power Status" "0,1" newline bitfld.long 0x18 6. "A2E0D0STP,PLL circuit 5 Stop Condition by ENYOSS0 cluster 0 domain (A2E0D0) Power Status" "0,1" newline bitfld.long 0x18 3. "A3VIP3STP,PLL circuit 5 Stop Condition by A3VIP3 Power Status" "0,1" newline bitfld.long 0x18 2. "A3VIP2STP,PLL circuit 5 Stop Condition by A3VIP2 Power Status" "0,1" newline bitfld.long 0x18 1. "A3VIP1STP,PLL circuit 5 Stop Condition by A3VIP1 Power Status" "0,1" newline bitfld.long 0x18 0. "A3VIP0STP,PLL circuit 5 Stop Condition by A3VIP0 Power Status" "0,1" group.long 0x870++0x33 line.long 0x0 "SD0CKCR,SD0CKCR is a 32-bit readable/writable register. This register controls SD0H clock (SD0Hϕ) and SDHI0 clock (SD0ϕ) frequency. This register should be set before SD-IF0 module is operated. Do not access SD-IF0 module during changing the clock.." bitfld.long 0x0 9. "STP0HCK,Clock Stop" "0: Supplies SD0 clock,1: Stops SD0 clock" newline bitfld.long 0x0 8. "STP0CK,Clock Stop" "0: Supplies SD0 clock,1: Stops SD0 clock" newline bitfld.long 0x0 2.--4. "SD0SRCFC,SD0HΦ clock Frequency Division Ratio." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--1. "SD0FC,Select SD0ϕ division Ratio." "?,1: SD0SRCFC[2:0]=000,2: SD0SRCFC[2:0]=001,?" line.long 0x4 "RPCCKCR,RPCCKCR is a 32-bit readable/writable register. This register controls the RPC clock (RPCϕ). This register should be set before RPC module is operated. Do not access RPC module during changing the clock frequency of RPCϕ." bitfld.long 0x4 9. "CKSTP2,RPCD2ϕ Clock Stop" "0: Supplies clock to RPC,1: Stops clock to RPC" newline bitfld.long 0x4 8. "CKSTP,RPCϕ Clock Stop" "0: Supplies clock to RPC,1: Stops clock to RPC" newline hexmask.long.byte 0x4 0.--4. 1. "DIV,RPC clock (RPCϕ RPCD2ϕ) Frequency Division Ratio." line.long 0x8 "CANFDCKCR,CANFDCKCR is a 32-bit readable/writable register. This register controls the CANFD clock (CANFDϕ). This register should be set before CAN-FD module is operated. Do not access CAN-FD module during changing the clock frequency of CANFDϕ." bitfld.long 0x8 8. "CKSTP,Clock Stop" "0: Supplies clock to CANFD,1: Stops clock to CANFD" newline hexmask.long.byte 0x8 0.--5. 1. "DIV,Division Ratio" line.long 0xC "MSOCKCR,MSOCKCR is a 32-bit readable/writable register. This register controls the MSIOF clock (MSOϕ). This register should be set before MSIOF module is operated. Do not access MSIOF module during changing the clock frequency of MSOϕ." bitfld.long 0xC 8. "CKSTP,Clock Stop" "0: Supplies clock to MSIOF,1: Stops clock to MSIOF" newline hexmask.long.byte 0xC 0.--5. 1. "DIV,Division Ratio" line.long 0x10 "CSI0CKCR,CSI0CKCR is a 32-bit readable/writable register. This register controls the CSI0 clock (CSI0ϕ). This register should be set before CSI2 module is operated. Do not access CSI2 module during changing the clock frequency of CSI0ϕ" bitfld.long 0x10 8. "CKSTP,Clock Stop" "0: Supplies clock to CSI0,1: Stops clock to CSI0" newline hexmask.long.byte 0x10 0.--5. 1. "DIV,Division Ratio" line.long 0x14 "DSICKCR,According to DSI clock specification. CKSTP initial value is 1'b1. It means DSICK is stopped in initial state (just after boot)." bitfld.long 0x14 8. "CKSTP,Clock Stop" "0: Supplies clock to DSI,1: Stops clock to DSI" newline hexmask.long.byte 0x14 0.--5. 1. "DIV,Division Ratio" line.long 0x18 "IPCCKCR,IPCCKCR is a 32-bit readable/writable register. This register controls the IPC clock (IPCϕ). This register should be set before IPC module is operated. Do not access IPC module during changing the clock frequency of IPCϕ." bitfld.long 0x18 8. "CKSTP,Clock Stop" "0: Supplies clock to IPC,1: Stops clock to IPC" newline hexmask.long.byte 0x18 0.--5. 1. "DIV,Division Ratio" line.long 0x1C "FRAYCKCR,FRAYCKCR is a 32-bit readable/writable register. This register controls the FRAY clock (FRAYϕ). This register should be set before FRAY module is operated. Do not access FRAY module during changing the clock frequency of FRAYϕ." bitfld.long 0x1C 8. "CKSTP,Clock Stop" "0: Supplies clock to FRAY,1: Stops clock to FRAY" newline hexmask.long.byte 0x1C 0.--5. 1. "DIV,Division Ratio" line.long 0x20 "POSTCKCR,POSTCKCR is a 32-bit readable/writable register. This register controls the Power-On Self Test clock (POSTϕ). POST frequency is 66.66 MHz. so the initial frequency is also 66.66MHz. Run-Time Test is done at 66.66MHz. POSTCK target is any others.." bitfld.long 0x20 8. "CKSTP,Clock Stop control as the below." "0: Supplies POSTCK clock,1: Stops POSTCK clock" newline hexmask.long.byte 0x20 0.--5. 1. "DIV,Division Ratio" line.long 0x24 "POST2CKCR,POST2CKCR is a 32-bit readable/writable register. This register controls the Power-On Self Test clock (POST2ϕ). which is used for ENYO." bitfld.long 0x24 8. "CKSTP,Clock Stop control as the below." "0: Supplies POST2CK clock,1: Stops POST2CK clock" newline hexmask.long.byte 0x24 0.--5. 1. "DIV,Division Ratio" line.long 0x28 "POST3CKCR,RTT = 133.33MHz (Customer write access to POST3CKCR before RTT)." bitfld.long 0x28 8. "CKSTP,Clock Stop control as the below." "0: Supplies POST3CK clock,1: Stops POST3CK clock" newline hexmask.long.byte 0x28 0.--5. 1. "DIV,Division Ratio" line.long 0x2C "POST4CKCR,RTT = 133.33MHz (Customer write access to POST4CKCR before RTT)." bitfld.long 0x2C 8. "CKSTP,Clock Stop control as the below." "0: Supplies POST4CK clock,1: Stops POST4CK clock" newline hexmask.long.byte 0x2C 0.--5. 1. "DIV,Division Ratio" line.long 0x30 "OSCCKCR,OSCCKCR is a 32-bit readable/writable register. This register controls the clock source of SPARE3 Clock." bitfld.long 0x30 8. "CKSTP,Clock Stop control as the below." "0: Supplies SPARE3 clock,1: Stops SPARE3 clock" newline hexmask.long.byte 0x30 0.--5. 1. "DIV[5:0] & SET,Division Ratio" group.long 0xC00++0xF line.long 0x0 "PLL1FBCKMCSR,PLL1FBCKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - PLL1FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "PLL1FBCKMECR,PLL1FBCKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "PLL1FBCKMLCH,PLL1FBCKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "PLL1FBCKMLCL,PLL1FBCKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xC10++0x7 line.long 0x0 "PLL1FBCKMCNT,PLL1FBCKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "PLL1FBCKMCNTE,PLL1FBCKMCNTE is a 32-bit readable register. This register’s value is cleared when PLL1FBCKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,PLL1FBCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xC18++0x3 line.long 0x0 "PLL1FBCKMMDR,PLL1FBCKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xC20++0xF line.long 0x0 "PLL2_0FBCKMCSR,PLL2_0FBCKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - PLL2_0FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "PLL2_0FBCKMECR,PLL2_0FBCKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "PLL2_0FBCKMLCH,PLL2_0FBCKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "PLL2_0FBCKMLCL,PLL2_0FBCKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xC30++0x7 line.long 0x0 "PLL2_0FBCKMCNT,PLL2_0FBCKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "PLL2_0FBCKMCNTE,PLL2_0FBCKMCNTE is a 32-bit readable register. This register’s value is cleared when PLL2_0FBCKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,PLL2_0FBCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xC38++0x3 line.long 0x0 "PLL2_0FBCKMMDR,PLL2_0FBCKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xC40++0xF line.long 0x0 "PLL2_1FBCKMCSR,PLL2_1FBCKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - PLL2_1FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "PLL2_1FBCKMECR,PLL2_1FBCKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "PLL2_1FBCKMLCH,PLL2_1FBCKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "PLL2_1FBCKMLCL,PLL2_1FBCKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xC50++0x7 line.long 0x0 "PLL2_1FBCKMCNT,PLL2_1FBCKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "PLL2_1FBCKMCNTE,PLL2_1FBCKMCNTE is a 32-bit readable register. This register’s value is cleared when PLL2_1FBCKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,PLL2_1FBCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xC58++0x3 line.long 0x0 "PLL2_1FBCKMMDR,PLL2_1FBCKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xC60++0xF line.long 0x0 "PLL3_0FBCKMCSR,PLL3_0FBCKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - PLL3_0FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "PLL3_0FBCKMECR,PLL3_0FBCKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "PLL3_0FBCKMLCH,PLL3_0FBCKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "PLL3_0FBCKMLCL,PLL3_0FBCKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xC70++0x7 line.long 0x0 "PLL3_0FBCKMCNT,PLL3_0FBCKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "PLL3_0FBCKMCNTE,PLL3_0FBCKMCNTE is a 32-bit readable register. This register’s value is cleared when PLL3_0FBCKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,PLL3_0FBCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xC78++0x3 line.long 0x0 "PLL3_0FBCKMMDR,PLL3_0FBCKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xC80++0xF line.long 0x0 "PLL3_1FBCKMCSR,PLL3_1FBCKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - PLL3_1FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "PLL3_1FBCKMECR,PLL3_1FBCKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "PLL3_1FBCKMLCH,PLL3_1FBCKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "PLL3_1FBCKMLCL,PLL3_1FBCKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xC90++0x7 line.long 0x0 "PLL3_1FBCKMCNT,PLL3_1FBCKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "PLL3_1FBCKMCNTE,PLL3_1FBCKMCNTE is a 32-bit readable register. This register’s value is cleared when PLL3_1FBCKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,PLL3_1FBCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xC98++0x3 line.long 0x0 "PLL3_1FBCKMMDR,PLL3_1FBCKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xCA0++0xF line.long 0x0 "PLL4FBCKMCSR,PLL4FBCKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - PLL4FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "PLL4FBCKMECR,PLL4FBCKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "PLL4FBCKMLCH,PLL4FBCKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "PLL4FBCKMLCL,PLL4FBCKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xCB0++0x7 line.long 0x0 "PLL4FBCKMCNT,PLL4FBCKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "PLL4FBCKMCNTE,PLL4FBCKMCNTE is a 32-bit readable register. This register’s value is cleared when PLL4FBCKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,PLL4FBCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xCB8++0x3 line.long 0x0 "PLL4FBCKMMDR,PLL4FBCKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xCC0++0xF line.long 0x0 "PLL5FBCKMCSR,PLL5FBCKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - PLL5FBCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "PLL5FBCKMECR,PLL5FBCKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "PLL5FBCKMLCH,PLL5FBCKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "PLL5FBCKMLCL,PLL5FBCKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xCD0++0x7 line.long 0x0 "PLL5FBCKMCNT,PLL5FBCKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "PLL5FBCKMCNTE,PLL5FBCKMCNTE is a 32-bit readable register. This register’s value is cleared when PLL5FBCKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,PLL5FBCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xCD8++0x3 line.long 0x0 "PLL5FBCKMMDR,PLL5FBCKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xCE0++0xF line.long 0x0 "CPCKMCSR,CPCKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CPCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CPCKMECR,CPCKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CPCKMLCH,CPCKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CPCKMLCL,CPCKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xCF0++0x7 line.long 0x0 "CPCKMCNT,CPCKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CPCKMCNTE,CPCKMCNTE is a 32-bit readable register. This register’s value is cleared when CPCKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CPCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xCF8++0x3 line.long 0x0 "CPCKMMDR,CPCKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xD00++0xF line.long 0x0 "CBFUSACKMCSR,CBFUSACKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CBFUSACKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CBFUSACKMECR,CBFUSACKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CBFUSACKMLCH,CBFUSACKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CBFUSACKMLCL,CBFUSACKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xD10++0x7 line.long 0x0 "CBFUSACKMCNT,CBFUSACKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CBFUSACKMCNTE,CBFUSACKMCNTE is a 32-bit readable register. This register’s value is cleared when CBFUSACKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CBFUSACKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xD18++0x3 line.long 0x0 "CBFUSACKMMDR,CBFUSACKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." rgroup.long 0xD1C++0x3 line.long 0x0 "CPGACKMSR,CPGACKMSR is a 32-bit readable register." hexmask.long 0x0 0.--31. 1. "CHKRES[m],Check result of each clock monitor." group.long 0xD20++0xF line.long 0x0 "CKMDDR0ZB3D2CKMCSR,CKMDDR0ZB3D2CKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CKMDDR0ZB3D2CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMDDR0ZB3D2CKMECR,CKMDDR0ZB3D2CKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMDDR0ZB3D2CKMLCH,CKMDDR0ZB3D2CKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMDDR0ZB3D2CKMLCL,CKMDDR0ZB3D2CKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xD30++0x7 line.long 0x0 "CKMDDR0ZB3D2CKMCNT,CKMDDR0ZB3D2CKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMDDR0ZB3D2CKMCNTE,CKMDDR0ZB3D2CKMCNTE is a 32-bit readable register. This register’s value is cleared when CKMDDR0ZB3D2CKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CKMDDR0ZB3D2CKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xD38++0x3 line.long 0x0 "CKMDDR0ZB3D2CKMMDR,CKMDDR0ZB3D2CKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xD40++0xF line.long 0x0 "CKMDDR0ZB3D2DDRL0CKMCSR,CKMDDR0ZB3D2DDRL0CKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CKMDDR0ZB3D2DDRL0CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMDDR0ZB3D2DDRL0CKMECR,CKMDDR0ZB3D2DDRL0CKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMDDR0ZB3D2DDRL0CKMLCH,CKMDDR0ZB3D2DDRL0CKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMDDR0ZB3D2DDRL0CKMLCL,CKMDDR0ZB3D2DDRL0CKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xD50++0x7 line.long 0x0 "CKMDDR0ZB3D2DDRL0CKMCNT,CKMDDR0ZB3D2DDRL0CKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMDDR0ZB3D2DDRL0CKMCNTE,CKMDDR0ZB3D2DDRL0CKMCNTE is a 32-bit readable register. This register’s value is cleared when CKMDDR0ZB3D2DDRL0CKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CKMDDR0ZB3D2DDRL0CKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xD58++0x3 line.long 0x0 "CKMDDR0ZB3D2DDRL0CKMMDR,CKMDDR0ZB3D2DDRL0CKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xD60++0xF line.long 0x0 "CKMDDR0CL16MCKMCSR,CKMDDR0CL16MCKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CKMDDR0CL16MCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMDDR0CL16MCKMECR,CKMDDR0CL16MCKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMDDR0CL16MCKMLCH,CKMDDR0CL16MCKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMDDR0CL16MCKMLCL,CKMDDR0CL16MCKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xD70++0x7 line.long 0x0 "CKMDDR0CL16MCKMCNT,CKMDDR0CL16MCKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMDDR0CL16MCKMCNTE,CKMDDR0CL16MCKMCNTE is a 32-bit readable register. This register’s value is cleared when CKMDDR0CL16MCKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CKMDDR0CL16MCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xD78++0x3 line.long 0x0 "CKMDDR0CL16MCKMMDR,CKMDDR0CL16MCKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xD80++0xF line.long 0x0 "CKMDDR0ZB3D1CKMCSR,CKMDDR0ZB3D1CKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CKMDDR0ZB3D1CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMDDR0ZB3D1CKMECR,CKMDDR0ZB3D1CKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMDDR0ZB3D1CKMLCH,CKMDDR0ZB3D1CKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMDDR0ZB3D1CKMLCL,CKMDDR0ZB3D1CKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xD90++0x7 line.long 0x0 "CKMDDR0ZB3D1CKMCNT,CKMDDR0ZB3D1CKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMDDR0ZB3D1CKMCNTE,CKMDDR0ZB3D1CKMCNTE is a 32-bit readable register. This register’s value is cleared when CKMDDR0ZB3D1CKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CKMDDR0ZB3D1CKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xD98++0x3 line.long 0x0 "CKMDDR0ZB3D1CKMMDR,CKMDDR0ZB3D1CKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xDA0++0xF line.long 0x0 "CKMDDR0ZB3D4CKMCSR,CKMDDR0ZB3D4CKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CKMDDR0ZB3D4CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMDDR0ZB3D4CKMECR,CKMDDR0ZB3D4CKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMDDR0ZB3D4CKMLCH,CKMDDR0ZB3D4CKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMDDR0ZB3D4CKMLCL,CKMDDR0ZB3D4CKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xDB0++0x7 line.long 0x0 "CKMDDR0ZB3D4CKMCNT,CKMDDR0ZB3D4CKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMDDR0ZB3D4CKMCNTE,CKMDDR0ZB3D4CKMCNTE is a 32-bit readable register. This register’s value is cleared when CKMDDR0ZB3D4CKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CKMDDR0ZB3D4CKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xDB8++0x3 line.long 0x0 "CKMDDR0ZB3D4CKMMDR,CKMDDR0ZB3D4CKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." rgroup.long 0xDBC++0x3 line.long 0x0 "CKMDDR0ACKMSR,CKMDDR0ACKMSR is a 32-bit readable register." hexmask.long 0x0 0.--31. 1. "CHKRES[m],Check result of each clock monitor." group.long 0xDC0++0xF line.long 0x0 "CKMDDR1ZB3D2CKMCSR,CKMDDR1ZB3D2CKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CKMDDR1ZB3D2CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMDDR1ZB3D2CKMECR,CKMDDR1ZB3D2CKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMDDR1ZB3D2CKMLCH,CKMDDR1ZB3D2CKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMDDR1ZB3D2CKMLCL,CKMDDR1ZB3D2CKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xDD0++0x7 line.long 0x0 "CKMDDR1ZB3D2CKMCNT,CKMDDR1ZB3D2CKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMDDR1ZB3D2CKMCNTE,CKMDDR1ZB3D2CKMCNTE is a 32-bit readable register. This register’s value is cleared when CKMDDR1ZB3D2CKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CKMDDR1ZB3D2CKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xDD8++0x3 line.long 0x0 "CKMDDR1ZB3D2CKMMDR,CKMDDR1ZB3D2CKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xDE0++0xF line.long 0x0 "CKMDDR1ZB3D2DDRL0CKMCSR,CKMDDR1ZB3D2DDRL0CKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CKMDDR1ZB3D2DDRL0CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMDDR1ZB3D2DDRL0CKMECR,CKMDDR1ZB3D2DDRL0CKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMDDR1ZB3D2DDRL0CKMLCH,CKMDDR1ZB3D2DDRL0CKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMDDR1ZB3D2DDRL0CKMLCL,CKMDDR1ZB3D2DDRL0CKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xDF0++0x7 line.long 0x0 "CKMDDR1ZB3D2DDRL0CKMCNT,CKMDDR1ZB3D2DDRL0CKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMDDR1ZB3D2DDRL0CKMCNTE,CKMDDR1ZB3D2DDRL0CKMCNTE is a 32-bit readable register. This register’s value is cleared when CKMDDR1ZB3D2DDRL0CKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CKMDDR1ZB3D2DDRL0CKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xDF8++0x3 line.long 0x0 "CKMDDR1ZB3D2DDRL0CKMMDR,CKMDDR1ZB3D2DDRL0CKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xE00++0xF line.long 0x0 "CKMDDR1CL16MCKMCSR,CKMDDR1CL16MCKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CKMDDR1CL16MCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMDDR1CL16MCKMECR,CKMDDR1CL16MCKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMDDR1CL16MCKMLCH,CKMDDR1CL16MCKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMDDR1CL16MCKMLCL,CKMDDR1CL16MCKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xE10++0x7 line.long 0x0 "CKMDDR1CL16MCKMCNT,CKMDDR1CL16MCKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMDDR1CL16MCKMCNTE,CKMDDR1CL16MCKMCNTE is a 32-bit readable register. This register’s value is cleared when CKMDDR1CL16MCKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CKMDDR1CL16MCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xE18++0x3 line.long 0x0 "CKMDDR1CL16MCKMMDR,CKMDDR1CL16MCKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xE20++0xF line.long 0x0 "CKMDDR1ZB3D1CKMCSR,CKMDDR1ZB3D1CKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CKMDDR1ZB3D1CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMDDR1ZB3D1CKMECR,CKMDDR1ZB3D1CKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMDDR1ZB3D1CKMLCH,CKMDDR1ZB3D1CKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMDDR1ZB3D1CKMLCL,CKMDDR1ZB3D1CKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xE30++0x7 line.long 0x0 "CKMDDR1ZB3D1CKMCNT,CKMDDR1ZB3D1CKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMDDR1ZB3D1CKMCNTE,CKMDDR1ZB3D1CKMCNTE is a 32-bit readable register. This register’s value is cleared when CKMDDR1ZB3D1CKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CKMDDR1ZB3D1CKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xE38++0x3 line.long 0x0 "CKMDDR1ZB3D1CKMMDR,CKMDDR1ZB3D1CKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." group.long 0xE40++0xF line.long 0x0 "CKMDDR1ZB3D4CKMCSR,CKMDDR1ZB3D4CKMCSR is a 32-bit readable/writable register." rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - CKMDDR1ZB3D4CKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMDDR1ZB3D4CKMECR,CKMDDR1ZB3D4CKMECR is a 32-bit readable/writable register." bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMDDR1ZB3D4CKMLCH,CKMDDR1ZB3D4CKMLCH is a 32-bit readable/writable register." hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMDDR1ZB3D4CKMLCL,CKMDDR1ZB3D4CKMLCL is a 32-bit readable/writable register." hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The upper limit to judge as expected oscillation." rgroup.long 0xE50++0x7 line.long 0x0 "CKMDDR1ZB3D4CKMCNT,CKMDDR1ZB3D4CKMCNT is a 32-bit readable register. This register’s value is not cleared unless the clock monitor module is reset." hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMDDR1ZB3D4CKMCNTE,CKMDDR1ZB3D4CKMCNTE is a 32-bit readable register. This register’s value is cleared when CKMDDR1ZB3D4CKMECR.CLRRES is 1." bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,CKMDDR1ZB3D4CKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xE58++0x3 line.long 0x0 "CKMDDR1ZB3D4CKMMDR,CKMDDR1ZB3D4CKMMDR is a 32-bit readable/writable register." hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved." rgroup.long 0xE5C++0x3 line.long 0x0 "CKMDDR1ACKMSR,CKMDDR1ACKMSR is a 32-bit readable register." hexmask.long 0x0 0.--31. 1. "CHKRES[m],Check result of each clock monitor." group.long 0x3800++0x3 line.long 0x0 "D0WACRAm,Only accessed by Domain0" hexmask.long 0x0 0.--31. 1. "D0WACRAnm" group.long 0x3900++0x3 line.long 0x0 "D1WACRAm,Only accessed by Domain0" hexmask.long 0x0 0.--31. 1. "D1WACRAnm" group.long 0x3A00++0x3 line.long 0x0 "D2WACRAm,Only accessed by Domain0" hexmask.long 0x0 0.--31. 1. "D2WACRAnm" group.long 0x3B00++0x3 line.long 0x0 "D3WACRAm,Only accessed by Domain0" hexmask.long 0x0 0.--31. 1. "D3WACRAnm" group.long 0x3C00++0x3 line.long 0x0 "D0WACRBm,Only accessed by Domain0" hexmask.long 0x0 0.--31. 1. "D0WACRBnm" group.long 0x3D00++0x3 line.long 0x0 "D1WACRBm,Only accessed by Domain0" hexmask.long 0x0 0.--31. 1. "D1WACRBnm" group.long 0x3E00++0x3 line.long 0x0 "D2WACRBm,Only accessed by Domain0" hexmask.long 0x0 0.--31. 1. "D2WACRBnm" group.long 0x3F00++0x3 line.long 0x0 "D3WACRBm,Only accessed by Domain0" hexmask.long 0x0 0.--31. 1. "D3WACRBnm" tree.end tree "CRC" base ad:0x0 tree "CRC_0" group.long 0x0++0x7 line.long 0x0 "DCRAnCIN,DCRA0CIN is a register that sets input data." hexmask.long 0x0 0.--31. 1. "DATA_IN,Set input data" line.long 0x4 "DCRAnCOUT,DCRA0COUT is a register that obtains the CRC codes." hexmask.long 0x4 0.--31. 1. "CRC_CODE,CRC code" group.long 0x20++0x3 line.long 0x0 "DCRAnCTL,DCRAnCTL is a register that determines the valid bit width of the input data and generator polynomial for the CRC codes." bitfld.long 0x0 4.--5. "ISZ,The value written to this field determines the valid bit width of input data." "0: 32bit,1: 16bit,2: 8bit,3: Setting prohibited" hexmask.long.byte 0x0 0.--3. 1. "POL,The value written to this field determines the generator polynomial for the CRC codes." group.long 0x40++0x3 line.long 0x0 "DCRAnCTL2,DCRA0CTL2 is a register that determines the swap. exor of input data and output data." bitfld.long 0x0 7. "XORVALMODE,The value written to this field determines EXOR ON of output data." "0: data out[31:0],1: H’FFFF FFFF ^ data_out[31:0]" bitfld.long 0x0 6. "BITSWAPMODE,The value written to this field determines bit swap of output data." "0,1" bitfld.long 0x0 4.--5. "BYTESWAPMODE,The value written to this field determines byte swap of output data." "0,1,2,3" bitfld.long 0x0 3. "XORVALINMODE,The value written to this field determines EXOR ON of input data." "0: data_in[31:0],1: H’FFFF FFFF ^ data_in[31:0]" bitfld.long 0x0 2. "BITSWAPINMODE,The value written to this field determines bit swap of input data." "0,1" newline bitfld.long 0x0 0.--1. "BYTESWAPINMODE,The value written to this field determines byte swap of input data." "0,1,2,3" tree.end tree "CRC_1" group.long 0x0++0x7 line.long 0x0 "DCRAnCIN,DCRA0CIN is a register that sets input data." hexmask.long 0x0 0.--31. 1. "DATA_IN,Set input data" line.long 0x4 "DCRAnCOUT,DCRA0COUT is a register that obtains the CRC codes." hexmask.long 0x4 0.--31. 1. "CRC_CODE,CRC code" group.long 0x20++0x3 line.long 0x0 "DCRAnCTL,DCRAnCTL is a register that determines the valid bit width of the input data and generator polynomial for the CRC codes." bitfld.long 0x0 4.--5. "ISZ,The value written to this field determines the valid bit width of input data." "0: 32bit,1: 16bit,2: 8bit,3: Setting prohibited" hexmask.long.byte 0x0 0.--3. 1. "POL,The value written to this field determines the generator polynomial for the CRC codes." group.long 0x40++0x3 line.long 0x0 "DCRAnCTL2,DCRA0CTL2 is a register that determines the swap. exor of input data and output data." bitfld.long 0x0 7. "XORVALMODE,The value written to this field determines EXOR ON of output data." "0: data out[31:0],1: H’FFFF FFFF ^ data_out[31:0]" bitfld.long 0x0 6. "BITSWAPMODE,The value written to this field determines bit swap of output data." "0,1" bitfld.long 0x0 4.--5. "BYTESWAPMODE,The value written to this field determines byte swap of output data." "0,1,2,3" bitfld.long 0x0 3. "XORVALINMODE,The value written to this field determines EXOR ON of input data." "0: data_in[31:0],1: H’FFFF FFFF ^ data_in[31:0]" bitfld.long 0x0 2. "BITSWAPINMODE,The value written to this field determines bit swap of input data." "0,1" newline bitfld.long 0x0 0.--1. "BYTESWAPINMODE,The value written to this field determines byte swap of input data." "0,1,2,3" tree.end tree "CRC_2" base ad:0xE7000000 group.long 0x0++0x7 line.long 0x0 "DCRAnCIN,DCRA0CIN is a register that sets input data." hexmask.long 0x0 0.--31. 1. "DATA_IN,Set input data" line.long 0x4 "DCRAnCOUT,DCRA0COUT is a register that obtains the CRC codes." hexmask.long 0x4 0.--31. 1. "CRC_CODE,CRC code" group.long 0x20++0x3 line.long 0x0 "DCRAnCTL,DCRAnCTL is a register that determines the valid bit width of the input data and generator polynomial for the CRC codes." bitfld.long 0x0 4.--5. "ISZ,The value written to this field determines the valid bit width of input data." "0: 32bit,1: 16bit,2: 8bit,3: Setting prohibited" hexmask.long.byte 0x0 0.--3. 1. "POL,The value written to this field determines the generator polynomial for the CRC codes." group.long 0x40++0x3 line.long 0x0 "DCRAnCTL2,DCRA0CTL2 is a register that determines the swap. exor of input data and output data." bitfld.long 0x0 7. "XORVALMODE,The value written to this field determines EXOR ON of output data." "0: data out[31:0],1: H’FFFF FFFF ^ data_out[31:0]" bitfld.long 0x0 6. "BITSWAPMODE,The value written to this field determines bit swap of output data." "0,1" bitfld.long 0x0 4.--5. "BYTESWAPMODE,The value written to this field determines byte swap of output data." "0,1,2,3" bitfld.long 0x0 3. "XORVALINMODE,The value written to this field determines EXOR ON of input data." "0: data_in[31:0],1: H’FFFF FFFF ^ data_in[31:0]" bitfld.long 0x0 2. "BITSWAPINMODE,The value written to this field determines bit swap of input data." "0,1" newline bitfld.long 0x0 0.--1. "BYTESWAPINMODE,The value written to this field determines byte swap of input data." "0,1,2,3" tree.end tree "CRC_3" base ad:0xE7010000 group.long 0x0++0x7 line.long 0x0 "DCRAnCIN,DCRA0CIN is a register that sets input data." hexmask.long 0x0 0.--31. 1. "DATA_IN,Set input data" line.long 0x4 "DCRAnCOUT,DCRA0COUT is a register that obtains the CRC codes." hexmask.long 0x4 0.--31. 1. "CRC_CODE,CRC code" group.long 0x20++0x3 line.long 0x0 "DCRAnCTL,DCRAnCTL is a register that determines the valid bit width of the input data and generator polynomial for the CRC codes." bitfld.long 0x0 4.--5. "ISZ,The value written to this field determines the valid bit width of input data." "0: 32bit,1: 16bit,2: 8bit,3: Setting prohibited" hexmask.long.byte 0x0 0.--3. 1. "POL,The value written to this field determines the generator polynomial for the CRC codes." group.long 0x40++0x3 line.long 0x0 "DCRAnCTL2,DCRA0CTL2 is a register that determines the swap. exor of input data and output data." bitfld.long 0x0 7. "XORVALMODE,The value written to this field determines EXOR ON of output data." "0: data out[31:0],1: H’FFFF FFFF ^ data_out[31:0]" bitfld.long 0x0 6. "BITSWAPMODE,The value written to this field determines bit swap of output data." "0,1" bitfld.long 0x0 4.--5. "BYTESWAPMODE,The value written to this field determines byte swap of output data." "0,1,2,3" bitfld.long 0x0 3. "XORVALINMODE,The value written to this field determines EXOR ON of input data." "0: data_in[31:0],1: H’FFFF FFFF ^ data_in[31:0]" bitfld.long 0x0 2. "BITSWAPINMODE,The value written to this field determines bit swap of input data." "0,1" newline bitfld.long 0x0 0.--1. "BYTESWAPINMODE,The value written to this field determines byte swap of input data." "0,1,2,3" tree.end tree.end tree "DBSC" base ad:0x0 tree "DBSC_0" base ad:0xE6790000 group.long 0x4++0x7 line.long 0x0 "DBSYSCONF1,DBSC4 System Configuration Register1 for DFI Domain" bitfld.long 0x0 0.--1. "freqratio,Frequency Ratio Setting" "?,1: 4,?,?" line.long 0x4 "DBSYSCONF1A,DBSC4 System Configuration Register 1 for AXI Domain" bitfld.long 0x4 0.--1. "freqratioa,Frequency Ratio Setting" "?,1: 4,?,?" group.long 0x10++0x3 line.long 0x0 "DBPHYCONF0,PHY Type Configuration Register" bitfld.long 0x0 0.--1. "phytype,PHY Type" "?,1: DFI,?,?" group.long 0x20++0x7 line.long 0x0 "DBMEMKIND,Memory Type Register for DFI Domain" hexmask.long.byte 0x0 0.--3. 1. "ddcg,SDRAM Type" line.long 0x4 "DBMEMKINDA,Memory Type Register for AXI Domain" hexmask.long.byte 0x4 0.--3. 1. "ddcga,SDRAM Type" group.long 0x30++0x7 line.long 0x0 "DBMEMCONF00,DBMEMCONF00 is used to set the memory configuration to use for rank 0 on channel 0." bitfld.long 0x0 30.--31. "dens00,Channel 0 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw00,Channel 0 Rank 0 Row Address Bit width" newline bitfld.long 0x0 16.--18. "awbk00,Channel 0 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl00,Channel 0 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw00,Channel 0 Rank 0 Memory External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF01,DBMEMCONF01 is used to set the memory configuration to use for rank 1 on channel 0." bitfld.long 0x4 30.--31. "dens01,Channel 0 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw01,Channel 0 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk01,Channel 0 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl01,Channel 0 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw01,Channel 0 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x40++0x7 line.long 0x0 "DBMEMCONF10,DBMEMCONF10 is used to set the memory configuration to use for rank 0 on channel 1." bitfld.long 0x0 30.--31. "dens10,Channel 1 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw10,Channel 1 Rank 0 Row Address Bit Width" newline bitfld.long 0x0 16.--18. "awbk10,Channel 1 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl10,Channel 1 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw10,Channel 1 Rank 0 External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF11,DBMEMCONF11 is used to set the memory configuration to use for rank 1 on channel 1." bitfld.long 0x4 30.--31. "dens11,Channel 1 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw11,Channel 1 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk11,Channel 1 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl11,Channel 1 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw11,Channel 1 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x50++0x7 line.long 0x0 "DBMEMCONF20,DBMEMCONF20 is used to set the memory configuration to use for rank 0 on channel 2." bitfld.long 0x0 30.--31. "dens20,Channel 2 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw20,Channel 2 Rank 0 Row Address Bit Width" newline bitfld.long 0x0 16.--18. "awbk20,Channel 2 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl20,Channel 2 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw20,Channel 2 Rank 0 External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF21,DBMEMCONF21 is used to set the memory configuration to use for rank 1 on channel 2." bitfld.long 0x4 30.--31. "dens21,Channel 2 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw21,Channel 2 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk21,Channel 2 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl21,Channel 2 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw21,Channel 2 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x60++0x7 line.long 0x0 "DBMEMCONF30,DBMEMCONF30 is used to set the memory configuration to use for rank 0 on channel 3." bitfld.long 0x0 30.--31. "dens30,Channel 3 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw30,Channel 3 Rank 0 Row Address Bit Width" newline bitfld.long 0x0 16.--18. "awbk30,Channel 3 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl30,Channel 3 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw30,Channel 3 Rank 0 External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF31,DBMEMCONF31 is used to set the memory configuration to use for rank 1 on channel 3." bitfld.long 0x4 30.--31. "dens31,Channel 3 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw31,Channel 3 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk31,Channel 3 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl31,Channel 3 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw31,Channel 3 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x70++0x7 line.long 0x0 "DBMEMCONF00A,DBMEMCONF00 is used to set the memory configuration to use for rank 0 on channel 0." bitfld.long 0x0 30.--31. "dens00a,Channel 0 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw00a,Channel 0 Rank 0 Row Address Bit width" newline bitfld.long 0x0 16.--18. "awbk00a,Channel 0 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl00a,Channel 0 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw00a,Channel 0 Rank 0 Memory External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF01A,DBMEMCONF01 is used to set the memory configuration to use for rank 1 on channel 0." bitfld.long 0x4 30.--31. "dens01a,Channel 0 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw01a,Channel 0 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk01a,Channel 0 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl01a,Channel 0 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw01a,Channel 0 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x80++0x7 line.long 0x0 "DBMEMCONF10A,DBMEMCONF10 is used to set the memory configuration to use for rank 0 on channel 1." bitfld.long 0x0 30.--31. "dens10a,Channel 1 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw10a,Channel 1 Rank 0 Row Address Bit width" newline bitfld.long 0x0 16.--18. "awbk10a,Channel 1 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl10a,Channel 1 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw10a,Channel 1 Rank 0 Memory External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF11A,DBMEMCONF11 is used to set the memory configuration to use for rank 1 on channel 1." bitfld.long 0x4 30.--31. "dens11a,Channel 1 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw11a,Channel 1 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk11a,Channel 1 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl11a,Channel 1 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw11a,Channel 1 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x90++0x7 line.long 0x0 "DBMEMCONF20A,DBMEMCONF20 is used to set the memory configuration to use for rank 0 on channel 2." bitfld.long 0x0 30.--31. "dens20a,Channel 2 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw20a,Channel 2 Rank 0 Row Address Bit width" newline bitfld.long 0x0 16.--18. "awbk20a,Channel 2 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl20a,Channel 2 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw20a,Channel 2 Rank 0 Memory External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF21A,DBMEMCONF21 is used to set the memory configuration to use for rank 1 on channel 2." bitfld.long 0x4 30.--31. "dens21a,Channel 2 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw21a,Channel 2 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk21a,Channel 2 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl21a,Channel 2 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw21a,Channel 2 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0xA0++0x7 line.long 0x0 "DBMEMCONF30A,DBMEMCONF30 is used to set the memory configuration to use for rank 0 on channel 3." bitfld.long 0x0 30.--31. "dens30a,Channel 3 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw30a,Channel 3 Rank 0 Row Address Bit width" newline bitfld.long 0x0 16.--18. "awbk30a,Channel 3 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl30a,Channel 3 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw30a,Channel 3 Rank 0 Memory External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF31A,DBMEMCONF31 is used to set the memory configuration to use for rank 1 on channel 3." bitfld.long 0x4 30.--31. "dens31a,Channel 3 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw31a,Channel 3 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk31a,Channel 3 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl31a,Channel 3 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw31a,Channel 3 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0xC0++0x3 line.long 0x0 "DBCONFMON0A,Configuration Monitor" hexmask.long 0x0 0.--31. 1. "dbscrma,Value of scramble seed" group.long 0x100++0x3 line.long 0x0 "DBSYSCNT0,DBSC System Register 0 for DFI Domain" hexmask.long.word 0x0 0.--15. 1. "reglock,Register Write Enable Pattern" group.long 0x108++0x3 line.long 0x0 "DBSYSCNT0A,DBSC System Register 0 for AXI Domain" hexmask.long.word 0x0 0.--15. 1. "reglocka,Register Write Enable Pattern" group.long 0x200++0xB line.long 0x0 "DBACEN,SDRAM Access Enable Register" bitfld.long 0x0 0. "accen,SDRAM Access Enable" "0: Disables access to the SDRAM,1: Enables access to the SDRAM" line.long 0x4 "DBRFEN,Auto-Refresh Enable Register" bitfld.long 0x4 0. "arfen,Auto-Refresh Enable" "0: Stops the auto-refresh function,1: Starts the auto-refresh function" line.long 0x8 "DBCMD,The manual command-issuing register (DBCMD) is used to issue the required commands for the sequence of initializing the SDRAM and of transitions to and from the self-refresh mode. The command corresponding to the OPC bits is issued once as a result.." hexmask.long.byte 0x8 24.--31. 1. "opc,Operation Code" hexmask.long.byte 0x8 20.--23. 1. "ch,Channel Specification" newline bitfld.long 0x8 16.--18. "rank,Rank Specification" "0: Rank 0,1: Rank 1,?,?,?,?,?,?" hexmask.long.word 0x8 0.--15. 1. "arg,Argument" group.long 0x210++0x3 line.long 0x0 "DBWAIT,Operation Completion Waiting Register" bitfld.long 0x0 0. "busy,Operation Completion Waiting" "0: The command specified by using the DBCMD..,1: The command specified by using the DBCMD.." group.long 0x300++0x4B line.long 0x0 "DBTR0,SDRAM Timing Register 0" hexmask.long.byte 0x0 0.--7. 1. "cl,CL RL (CAS Latency Read Latency)" line.long 0x4 "DBTR1,SDRAM Timing Register 1" hexmask.long.byte 0x4 0.--7. 1. "cwl,CWL WL (CAS Write Latency Write Latency)" line.long 0x8 "DBTR2,SDRAM Timing Register 2" hexmask.long.byte 0x8 0.--7. 1. "al,AL (AditiveLatency)" line.long 0xC "DBTR3,SDRAM Timing Register 3" hexmask.long.byte 0xC 0.--7. 1. "trcd,tRCD (ACT to internal read or write delay time RAS-to-CAS delay)" line.long 0x10 "DBTR4,SDRAM Timing Register 4" hexmask.long.byte 0x10 16.--23. 1. "trpa,tRP tRPab (PRE command period Row precharge time (all banks))" hexmask.long.byte 0x10 0.--7. 1. "trp,tRP tRPpb (PRE command period Row precharge time (single bank))" line.long 0x14 "DBTR5,SDRAM Timing Register 5" hexmask.long.byte 0x14 0.--7. 1. "trc,tRC (ACT to ACT or REF command period ACTIVATE-to-ACTIVATE command period (same bank))" line.long 0x18 "DBTR6,SDRAM Timing Register 6" hexmask.long.byte 0x18 0.--7. 1. "tras,tRAS (ACT to PRE command period Row active time)" line.long 0x1C "DBTR7,SDRAM Timing Register 7" hexmask.long.byte 0x1C 16.--23. 1. "trrd_s,tRRD (ACTIVE to ACTIVE command period Active bank-A to active bank-B)" hexmask.long.byte 0x1C 0.--7. 1. "trrd,tRRD (ACTIVE to ACTIVE command period Active bank-A to active bank-B)" line.long 0x20 "DBTR8,SDRAM Timing Register 8" hexmask.long.byte 0x20 0.--7. 1. "tfaw,tFAW (Four activate window Four-bank ACTIVATE window)" line.long 0x24 "DBTR9,SDRAM Timing Register 9" hexmask.long.byte 0x24 0.--7. 1. "trdpr,tRTP nRTP (Internal READ Command to PRECHARGE Command delay Internal READ to PRECHARGE command delay)" line.long 0x28 "DBTR10,SDRAM Timing Register 10" hexmask.long.byte 0x28 0.--7. 1. "twr,WR nWR (WRITE recovery time)" line.long 0x2C "DBTR11,SDRAM Timing Register 11" hexmask.long.byte 0x2C 0.--7. 1. "trdwr,Read-to-Write Interval" line.long 0x30 "DBTR12,SDRAM Timing Register 12" hexmask.long.byte 0x30 16.--23. 1. "twrrd_s,Write-to-Read interval" hexmask.long.byte 0x30 0.--7. 1. "twrrd,Write-to-Read interval" line.long 0x34 "DBTR13,SDRAM Timing Register 13" hexmask.long.word 0x34 0.--15. 1. "trfc,tRFC tRFCab (REF command to ACT or REF command time Refresh Cycle Time (All Banks))" line.long 0x38 "DBTR14,SDRAM Timing Register 14" hexmask.long.byte 0x38 16.--23. 1. "tckehdll,tXPDLL (Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL)" hexmask.long.byte 0x38 0.--7. 1. "tckeh,tXP (Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit power- down to next valid command delay)" line.long 0x3C "DBTR15,SDRAM Timing Register 15" hexmask.long.byte 0x3C 16.--23. 1. "tckesr,tCKESR tSR (Minimum CKE low width for Self Refresh entry to exit timing Minimum Self-Refresh Time (Entry to Exit))" hexmask.long.byte 0x3C 0.--7. 1. "tckel,tCKE (CKE minimum pulse width)" line.long 0x40 "DBTR16,DBTR16 is used to set timing parameters for the SDRAM." hexmask.long.byte 0x40 24.--31. 1. "dqienltncy,dqienltncy Setting" hexmask.long.byte 0x40 16.--23. 1. "dql,dqltncy Setting" newline hexmask.long.byte 0x40 8.--15. 1. "dqenltncy,dqenltncy Setting" hexmask.long.byte 0x40 0.--7. 1. "wdql,wdqltncy Setting" line.long 0x44 "DBTR17,DBTR17 is used to set timing parameters for the SDRAM." hexmask.long.byte 0x44 24.--31. 1. "tmodrd,tMRR (MODE REGISTER READ command period)" hexmask.long.byte 0x44 16.--23. 1. "tmod,tMOD tMRD (Mode Register Set command update delay Mode register set command delay)" line.long 0x48 "DBTR18,SDRAM Timing Register 18" bitfld.long 0x48 24.--26. "rodtl,ODT Assert Period Setting in Reading" "0: BL,1: BL,?,?,?,?,?,?" bitfld.long 0x48 16.--18. "rodta,ODT Assert Start Timing Setting in Reading" "0: Simultaneous with the read command,1: 1 cycle after the read command,?,?,?,?,?,?" newline bitfld.long 0x48 8.--10. "wodtl,ODT Assert Period Setting in Writing" "0: BL,1: BL,?,?,?,?,?,?" bitfld.long 0x48 0.--2. "wodta,ODT Assert Start Timing Setting in Writing" "0: Simultaneous with the write command,1: 1 cycle after the write command,?,?,?,?,?,?" group.long 0x350++0x17 line.long 0x0 "DBTR20,DBTR20 is used to set timing parameters for the SDRAM." hexmask.long.word 0x0 16.--31. 1. "txsdll,tXSDLL (Exit Self Refresh to commands requiring a locked DLL)" hexmask.long.word 0x0 0.--15. 1. "txs,tXS tXSR (Exit Self Refresh to commands not requiring a locked DLL SELF REFRESH exit to next valid command delay)" line.long 0x4 "DBTR21,SDRAM Timing Register 21" hexmask.long.byte 0x4 16.--23. 1. "tccd_s,tCCD (CAS_N to CAS_N command delay CAS-to-CAS delay)" hexmask.long.byte 0x4 0.--7. 1. "tccd,tCCD (CAS_N to CAS_N command delay CAS-to-CAS delay)" line.long 0x8 "DBTR22,DBTR22 is used to set timing parameters for the SDRAM." hexmask.long.word 0x8 16.--31. 1. "tzqcal,tZQCAL (ZQ calibration time)" hexmask.long.byte 0x8 0.--7. 1. "tzqlat,tZQLAT (ZQCAL latch quiet time)" line.long 0xC "DBTR23,SDRAM Timing Register 23" bitfld.long 0xC 0.--1. "rrspc,RD to RD Interval Limitation" "0: No limitation,1: (TCCD_S + 1,?,?" line.long 0x10 "DBTR24,DBTR24 is used to set a timing parameter for the DFI." hexmask.long.byte 0x10 24.--31. 1. "rdcsgap,dfi_rddata_cs gap" hexmask.long.byte 0x10 16.--23. 1. "rdcslat,dfi_rddata_cs latency" newline hexmask.long.byte 0x10 8.--15. 1. "wrcsgap,dfi_wrdata_cs gap" hexmask.long.byte 0x10 0.--7. 1. "wrcslat,dfi_wrdata_cs latency" line.long 0x14 "DBTR25,SDRAM Timing Register 25" hexmask.long.byte 0x14 16.--23. 1. "twdqlvldis,DFI twdqlvl disable" hexmask.long.byte 0x14 0.--7. 1. "twdqlvlen,DFI twdqlvl enable." group.long 0x400++0x3 line.long 0x0 "DBBL,SDRAM Operation Setting Register for DFI Domain" bitfld.long 0x0 0.--1. "bl,Burst Length" "0: Fixed to 8,?,?,?" rgroup.long 0x404++0x3 line.long 0x0 "DBBLA,SDRAM Operation Setting Register for AXI Domain" bitfld.long 0x0 0.--1. "bla,Burst Length" "0: Fixed to 8,?,?,?" group.long 0x414++0x7 line.long 0x0 "DBRFCNF1,DBRFCNF1 is used to set the timing for refreshing of the SDRAM." hexmask.long.word 0x0 16.--31. 1. "refpmax,Maximum Pulling-in Number of Refresh Commands Setting" hexmask.long.word 0x0 0.--15. 1. "refint,tREFI (Average periodic refresh interval Average Refresh Interval)" line.long 0x4 "DBRFCNF2,Refresh Configuration Register 2" hexmask.long.byte 0x4 16.--19. 1. "refpmin,Minimum Pulling-in Number of Refresh Commands Setting" bitfld.long 0x4 0.--1. "refints,Average Refresh Interval Adjustment" "0: Average interval is REFINT,1: Average interval is 1,?,?" group.long 0x424++0x3 line.long 0x0 "DBCALCNF,SDRAM Calibration Configuration Register" bitfld.long 0x0 24. "calen,SDRAM Calibration Enable" "0: SDRAM calibration is disabled,1: SDRAM calibration is enabled" hexmask.long.word 0x0 0.--15. 1. "calint,SDRAM Calibration Frequency" group.long 0x438++0xF line.long 0x0 "DBRNK2,Multirank Operation Setting Register 2" hexmask.long.byte 0x0 12.--15. 1. "rkrr3,Additional Restriction on READ-READ Interval between Different Ranks for Channel 3." hexmask.long.byte 0x0 8.--11. 1. "rkrr2,Additional Restriction on READ-READ Interval between Different Ranks for Channel 2." newline hexmask.long.byte 0x0 4.--7. 1. "rkrr1,Additional Restriction on READ-READ Interval between Different Ranks for Channel 1." hexmask.long.byte 0x0 0.--3. 1. "rkrr0,Additional Restriction on READ-READ Interval between Different Ranks for Channel 0." line.long 0x4 "DBRNK3,Multirank Operation Setting Register 3" hexmask.long.byte 0x4 12.--15. 1. "rkrw3,Additional Restriction on READ-WRITE Interval between Different Ranks for Channel 3." hexmask.long.byte 0x4 8.--11. 1. "rkrw2,Additional Restriction on READ-WRITE Interval between Different Ranks for Channel 2." newline hexmask.long.byte 0x4 4.--7. 1. "rkrw1,Additional Restriction on READ-WRITE Interval between Different Ranks for Channel 1." hexmask.long.byte 0x4 0.--3. 1. "rkrw0,Additional Restriction on READ-WRITE Interval between Different Ranks for Channel 0." line.long 0x8 "DBRNK4,Multirank Operation Setting Register 4" hexmask.long.byte 0x8 12.--15. 1. "rkwr3,Additional Restriction on WRITE-READ Interval between Different Ranks for Channel 3." hexmask.long.byte 0x8 8.--11. 1. "rkwr2,Additional Restriction on WRITE-READ Interval between Different Ranks for Channel 2." newline hexmask.long.byte 0x8 4.--7. 1. "rkwr1,Additional Restriction on WRITE-READ Interval between Different Ranks for Channel 1." hexmask.long.byte 0x8 0.--3. 1. "rkwr0,Additional Restriction on WRITE-READ Interval between Different Ranks for Channel 0." line.long 0xC "DBRNK5,Multirank Operation Setting Register 5" hexmask.long.byte 0xC 12.--15. 1. "rkww3,Additional Restriction on WRITE-WRITE Interval between Different Ranks for Channel 3." hexmask.long.byte 0xC 8.--11. 1. "rkww2,Additional Restriction on WRITE-WRITE Interval between Different Ranks for Channel 2." newline hexmask.long.byte 0xC 4.--7. 1. "rkww1,Additional Restriction on WRITE-WRITE Interval between Different Ranks for Channel 1." hexmask.long.byte 0xC 0.--3. 1. "rkww0,Additional Restriction on WRITE-WRITE Interval between Different Ranks for Channel 0." group.long 0x460++0xF line.long 0x0 "DBODT0,ODT Output Setting Register 0" hexmask.long.byte 0x0 20.--23. 1. "rodtout01,ODT Output Level in Reading from Rank 1 for Channel 0 Setting" hexmask.long.byte 0x0 16.--19. 1. "rodtout00,ODT Output Level in Reading from Rank 0 for Channel 0 Setting" newline hexmask.long.byte 0x0 4.--7. 1. "wodtout01,ODT Output Level in Writing to Rank 1 for Channel 0 Setting" hexmask.long.byte 0x0 0.--3. 1. "wodtout00,ODT Output Level in Writing to Rank 0 for Channel 0 Setting" line.long 0x4 "DBODT1,ODT Output Setting Register 1" hexmask.long.byte 0x4 20.--23. 1. "rodtout11,ODT Output Level in Reading from Rank 1 for Channel 1 Setting" hexmask.long.byte 0x4 16.--19. 1. "rodtout10,ODT Output Level in Reading from Rank 0 for Channel 1 Setting" newline hexmask.long.byte 0x4 4.--7. 1. "wodtout11,ODT Output Level in Writing to Rank 1 for Channel 1 Setting" hexmask.long.byte 0x4 0.--3. 1. "wodtout10,ODT Output Level in Writing to Rank 0 for Channel 1 Setting" line.long 0x8 "DBODT2,ODT Output Setting Register 2" hexmask.long.byte 0x8 20.--23. 1. "rodtout21,ODT Output Level in Reading from Rank 1 for Channel 2 Setting" hexmask.long.byte 0x8 16.--19. 1. "rodtout20,ODT Output Level in Reading from Rank 0 for Channel 2 Setting" newline hexmask.long.byte 0x8 4.--7. 1. "wodtout21,ODT Output Level in Writing to Rank 1 for Channel 2 Setting" hexmask.long.byte 0x8 0.--3. 1. "wodtout20,ODT Output Level in Writing to Rank 0 for Channel 2 Setting" line.long 0xC "DBODT3,ODT Output Setting Register 3" hexmask.long.byte 0xC 20.--23. 1. "rodtout31,ODT Output Level in Reading from Rank 1 for Channel 3 Setting" hexmask.long.byte 0xC 16.--19. 1. "rodtout30,ODT Output Level in Reading from Rank 0 for Channel 3 Setting" newline hexmask.long.byte 0xC 4.--7. 1. "wodtout31,ODT Output Level in Writing to Rank 1 for Channel 3 Setting" hexmask.long.byte 0xC 0.--3. 1. "wodtout30,ODT Output Level in Writing to Rank 0 for Channel 3 Setting" group.long 0x518++0x3 line.long 0x0 "DBDBICNT,DBI Configuration Register" bitfld.long 0x0 1. "dbirden,Read DBI Setting" "0: Read DBI function is disabled,1: Read DBI function is enabled" bitfld.long 0x0 0. "dbiwren,Write DBI Setting" "0: Write DBI function is disabled,1: Write DBI function is enabled" group.long 0x520++0x7 line.long 0x0 "DBDFIPMSTRCNF,DFI PHY Master Control Register" bitfld.long 0x0 4.--5. "wtmode,DFI PHY Master receive mode" "0,1,2,3" bitfld.long 0x0 0. "pmstren,DFI PHY Master Control" "0,1" line.long 0x4 "DBDFIPMSTRSTAT,DBDFIPMSTRSTAT indicates whether or not CA training of each PHY unit has been completed. Any of the status bits becoming 1 indicates the completion of CA training of the corresponding PHY unit." group.long 0x52C++0x3 line.long 0x0 "DBDFICUPDCNF,DFI Control Update Configuration Register" hexmask.long.byte 0x0 24.--31. 1. "cupdreqmax,Maximum of Control Update Request Assert Period" hexmask.long.byte 0x0 16.--23. 1. "cupdreqmin,Minimum of Control Update Request Assert Period" newline bitfld.long 0x0 0. "cupden,Control Update Interface Enable." "0: Disable,1: Enable" group.long 0x600++0x7 line.long 0x0 "DBDFISTAT0,DFI Status Interface Input Register 0" bitfld.long 0x0 0. "dfiinitcompl0,DFIINITCOMPL for Channel 0" "0,1" line.long 0x4 "DBDFICNT0,DFI Status Interface Output Register 0" hexmask.long.byte 0x4 24.--28. 1. "dfifrequency0,FREQUENCY for Channel 0" hexmask.long.byte 0x4 16.--23. 1. "dfibytedis0,BYTEDIS for Channel 0" newline hexmask.long.byte 0x4 8.--11. 1. "dficlkdis0,CLKDIS for Channel 0" bitfld.long 0x4 4.--5. "dfifreqratio0,FREQRATIO for Channel 0" "?,1: 2,?,?" newline bitfld.long 0x4 0. "dfiinitstart0,INITSTART for Channel 0" "0,1" group.long 0x610++0x1B line.long 0x0 "DBPDCNT00,PHY Unit Control Register 00" hexmask.long 0x0 0.--31. 1. "cntreg00,DDR-PHY Control Signals 0 for Channel 0" line.long 0x4 "DBPDCNT01,PHY Unit Control Register 01" hexmask.long 0x4 0.--31. 1. "cntreg01,DDR-PHY Control Signals 1 for Channel 0" line.long 0x8 "DBPDCNT02,PHY Unit Control Register 02" hexmask.long 0x8 0.--31. 1. "cntreg02,DDR-PHY Control Signals 2 for Channel 0" line.long 0xC "DBPDCNT03,PHY Unit Control Register 03" hexmask.long 0xC 0.--31. 1. "cntreg03,DDR-PHY Control Signals 3 for Channel 0" line.long 0x10 "DBPDLK0,PHY Unit Lock Register 0" hexmask.long 0x10 0.--31. 1. "plock0,PHY Unit Access Lock Setting for Channel 0" line.long 0x14 "DBPDRGA0,PHY Unit Register Address 0" hexmask.long.word 0x14 0.--15. 1. "pra0,PHY Unit Register Address for Channel 0" line.long 0x18 "DBPDRGD0,PHY Unit Register Access 0" hexmask.long 0x18 0.--31. 1. "prd0,PHY Unit Registers Access for channel 0" rgroup.long 0x630++0x3 line.long 0x0 "DBPDSTAT00,PHY Status Register 00" hexmask.long.byte 0x0 8.--12. 1. "freqchgreqtype0,Frequency change request type for DDR-PHY Channel 0" bitfld.long 0x0 0. "freqchgreq0,Frequency change request for DDR-PHY Channel 0" "0,1" group.long 0x640++0x7 line.long 0x0 "DBDFISTAT1,DFI Status Interface Input Register 1" bitfld.long 0x0 0. "dfiinitcompl1,DFIINITCOMPL for Channel 1" "0,1" line.long 0x4 "DBDFICNT1,DFI Status Interface Output Register 1" hexmask.long.byte 0x4 24.--28. 1. "dfifrequency1,FREQUENCY for Channel 1" hexmask.long.byte 0x4 16.--23. 1. "dfibytedis1,BYTEDIS for Channel 1" newline hexmask.long.byte 0x4 8.--11. 1. "dficlkdis1,CLKDIS for Channel 1" bitfld.long 0x4 4.--5. "dfifreqratio1,FREQRATIO for Channel 1" "?,1: 2,?,?" newline bitfld.long 0x4 0. "dfiinitstart1,INITSTART for Channel 1" "0,1" group.long 0x650++0x1B line.long 0x0 "DBPDCNT10,PHY Unit Control Register 10" hexmask.long 0x0 0.--31. 1. "cntreg10,DDR-PHY Control Signals 0 for Channel 1" line.long 0x4 "DBPDCNT11,PHY Unit Control Register 11" hexmask.long 0x4 0.--31. 1. "cntreg11,DDR-PHY Control Signals 1 for Channel 1" line.long 0x8 "DBPDCNT12,PHY Unit Control Register 12" hexmask.long 0x8 0.--31. 1. "cntreg12,DDR-PHY Control Signals 2 for Channel 1" line.long 0xC "DBPDCNT13,PHY Unit Control Register 13" hexmask.long 0xC 0.--31. 1. "cntreg13,DDR-PHY Control Signals 3 for Channel 1" line.long 0x10 "DBPDLK1,PHY Unit Lock Register 1" hexmask.long 0x10 0.--31. 1. "plock1,PHY Unit Access Lock Setting for Channel 1" line.long 0x14 "DBPDRGA1,PHY Unit Register Address 1" hexmask.long.word 0x14 0.--15. 1. "pra1,PHY Unit Register Address for Channel 1" line.long 0x18 "DBPDRGD1,PHY Unit Register Access 1" hexmask.long 0x18 0.--31. 1. "prd1,PHY Unit Registers Access for channel 1" rgroup.long 0x670++0x3 line.long 0x0 "DBPDSTAT10,PHY Status Register 10" hexmask.long.byte 0x0 8.--12. 1. "freqchgreqtype1,Frequency change request type for DDR-PHY Channel 1" bitfld.long 0x0 0. "freqchgreq1,Frequency change request for DDR-PHY Channel 1" "0,1" group.long 0x680++0x7 line.long 0x0 "DBDFISTAT2,DFI Status Interface Input Register 2" bitfld.long 0x0 0. "dfiinitcompl2,DFIINITCOMPL for Channel 2" "0,1" line.long 0x4 "DBDFICNT2,DFI Status Interface Output Register 2" hexmask.long.byte 0x4 24.--28. 1. "dfifrequency2,FREQUENCY for Channel 2" hexmask.long.byte 0x4 16.--23. 1. "dfibytedis2,BYTEDIS for Channel 2" newline hexmask.long.byte 0x4 8.--11. 1. "dficlkdis2,CLKDIS for Channel 2" bitfld.long 0x4 4.--5. "dfifreqratio2,FREQRATIO for Channel 2" "?,1: 2,?,?" newline bitfld.long 0x4 0. "dfiinitstart2,INITSTART for Channel 2" "0,1" group.long 0x690++0x1B line.long 0x0 "DBPDCNT20,PHY Unit Control Register 20" hexmask.long 0x0 0.--31. 1. "cntreg20,DDR-PHY Control Signals 0 for Channel 2" line.long 0x4 "DBPDCNT21,PHY Unit Control Register 21" hexmask.long 0x4 0.--31. 1. "cntreg21,DDR-PHY Control Signals 1 for Channel 2" line.long 0x8 "DBPDCNT22,PHY Unit Control Register 22" hexmask.long 0x8 0.--31. 1. "cntreg22,DDR-PHY Control Signals 2 for Channel 2" line.long 0xC "DBPDCNT23,PHY Unit Control Register 23" hexmask.long 0xC 0.--31. 1. "cntreg23,DDR-PHY Control Signals 3 for Channel 2" line.long 0x10 "DBPDLK2,PHY Unit Lock Register 2" hexmask.long 0x10 0.--31. 1. "plock2,PHY Unit Access Lock Setting for Channel 2" line.long 0x14 "DBPDRGA2,PHY Unit Register Address 2" hexmask.long.word 0x14 0.--15. 1. "pra2,PHY Unit Register Address for Channel 2" line.long 0x18 "DBPDRGD2,PHY Unit Register Access 2" hexmask.long 0x18 0.--31. 1. "prd2,PHY Unit Registers Access for channel 2" rgroup.long 0x6B0++0x3 line.long 0x0 "DBPDSTAT20,PHY Status Register 20" hexmask.long.byte 0x0 8.--12. 1. "freqchgreqtype2,Frequency change request type for DDR-PHY Channel 2" bitfld.long 0x0 0. "freqchgreq2,Frequency change request for DDR-PHY Channel 2" "0,1" group.long 0x6C0++0x7 line.long 0x0 "DBDFISTAT3,DFI Status Interface Input Register 3" bitfld.long 0x0 0. "dfiinitcompl3,DFIINITCOMPL for Channel 3" "0,1" line.long 0x4 "DBDFICNT3,DFI Status Interface Output Register 3" hexmask.long.byte 0x4 24.--28. 1. "dfifrequency3,FREQUENCY for Channel 3" hexmask.long.byte 0x4 16.--23. 1. "dfibytedis3,BYTEDIS for Channel 3" newline hexmask.long.byte 0x4 8.--11. 1. "dficlkdis3,CLKDIS for Channel 3" bitfld.long 0x4 4.--5. "dfifreqratio3,FREQRATIO for Channel 3" "?,1: 2,?,?" newline bitfld.long 0x4 0. "dfiinitstart3,INITSTART for Channel 3" "0,1" group.long 0x6D0++0x1B line.long 0x0 "DBPDCNT30,PHY Unit Control Register 30" hexmask.long 0x0 0.--31. 1. "cntreg30,DDR-PHY Control Signals 0 for Channel 3" line.long 0x4 "DBPDCNT31,PHY Unit Control Register 31" hexmask.long 0x4 0.--31. 1. "cntreg31,DDR-PHY Control Signals 1 for Channel 3" line.long 0x8 "DBPDCNT32,PHY Unit Control Register 32" hexmask.long 0x8 0.--31. 1. "cntreg32,DDR-PHY Control Signals 2 for Channel 3" line.long 0xC "DBPDCNT33,PHY Unit Control Register 33" hexmask.long 0xC 0.--31. 1. "cntreg33,DDR-PHY Control Signals 3 for Channel 3" line.long 0x10 "DBPDLK3,PHY Unit Lock Register 3" hexmask.long 0x10 0.--31. 1. "plock3,PHY Unit Access Lock Setting for Channel 3" line.long 0x14 "DBPDRGA3,PHY Unit Register Address 3" hexmask.long.word 0x14 0.--15. 1. "pra3,PHY Unit Register Address for Channel 3" line.long 0x18 "DBPDRGD3,PHY Unit Register Access 3" hexmask.long 0x18 0.--31. 1. "prd3,PHY Unit Registers Access for channel 3" rgroup.long 0x6F0++0x3 line.long 0x0 "DBPDSTAT30,PHY Status Register 30" hexmask.long.byte 0x0 8.--12. 1. "freqchgreqtype3,Frequency change request type for DDR-PHY Channel 3" bitfld.long 0x0 0. "freqchgreq3,Frequency change request for DDR-PHY Channel 3" "0,1" group.long 0x804++0x3 line.long 0x0 "DBBUS0CNF1,Bus Control Unit Configuration Register 1" hexmask.long.byte 0x0 2.--7. 1. "bkadp,Bank Interleave Mode Setting." bitfld.long 0x0 0.--1. "bkadm,Bank Address Mode" "0: The whole logical address space is regarded as..,1: Setting prohibited,2: Setting prohibited,3: One for bank 0" group.long 0x904++0xB line.long 0x0 "DBCAM0CNF1,CAM Unit Configuration Register 1" hexmask.long.byte 0x0 16.--23. 1. "wbkwait,Writeback Wait" hexmask.long.byte 0x0 12.--15. 1. "swpinpri3,Swap-In Priority Threshold 3" newline hexmask.long.byte 0x0 8.--11. 1. "swpinpri2,Swap-In Priority Threshold 2" hexmask.long.byte 0x0 4.--7. 1. "swpinpri1,Swap-In Priority Threshold 1" newline hexmask.long.byte 0x0 0.--3. 1. "swpinpri1f,Swap-In Priority Threshold 1F" line.long 0x4 "DBCAM0CNF2,CAM Unit Configuration Register 2" bitfld.long 0x4 8.--9. "fillunit,Read Fill Minimum Size" "0: 64 bytes,1: 128 bytes,?,?" hexmask.long.byte 0x4 4.--7. 1. "fcdirtymax,Swap-In Threshold" newline hexmask.long.byte 0x4 0.--3. 1. "fcdirtymin,Swap-Out Threshold" line.long 0x8 "DBCAM0CNF3,CAM Unit Configuration Register 3" hexmask.long.byte 0x8 0.--7. 1. "rdfull,Read Queue Full Threshold setting" group.long 0x940++0x3 line.long 0x0 "DBCAM0CTRL0,CAM Unit Contoro Register 0" bitfld.long 0x0 0. "camflush,CAM Flush" "0: No flush,1: Flush" group.long 0x980++0x3 line.long 0x0 "DBCAM0STAT0,CAM0 Unit Status Register 0" bitfld.long 0x0 0. "camempty0,CAM0 Empty" "0: Data exists in cache 0,1: Data is empty in cache 0" group.long 0x990++0x3 line.long 0x0 "DBCAM1STAT0,CAM1 Unit Status Register 0" bitfld.long 0x0 0. "camempty1,CAM1 Empty" "0: Data exists in cache 1,1: Data is empty in cache 1" group.long 0x9A0++0x3 line.long 0x0 "DBCAM2STAT0,CAM2 Unit Status Register 0" bitfld.long 0x0 0. "camempty2,CAM2 Empty" "0: Data exists in cache 2,1: Data is empty in cache 2" group.long 0x9B0++0x3 line.long 0x0 "DBCAM3STAT0,CAM3 Unit Status Register 0" bitfld.long 0x0 0. "camempty3,CAM3 Empty" "0: Data exists in cache 3,1: Data is empty in cache 3" group.long 0x9F0++0x3 line.long 0x0 "DBBSWAP,Byte Swap Table Configuration Register" hexmask.long 0x0 0.--31. 1. "bswap,Byte Swap Table Setting" group.long 0x9FC++0x3 line.long 0x0 "DBBCAMDIS,CAM Unit Operation Setting Register" bitfld.long 0x0 0. "resrdis,Response Right Disable" "0: Control of the response right is enabled,1: Control of the response right is disabled" group.long 0x1000++0x7 line.long 0x0 "DBSCHCNT0,Scheduler Unit Operation Setting Register 0" bitfld.long 0x0 24.--25. "scqosckps,Prescaler Setting for QoS counter." "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "scqtzen,Quantization Bit Enable" newline bitfld.long 0x0 5. "scszen,Burst Size Based Scheduling Enable" "0,1" bitfld.long 0x0 4. "scbaen,Bank Miss Based Scheduling Enable" "0,1" newline bitfld.long 0x0 2. "scpgen,Page Hit Based Scheduling Enable" "0,1" bitfld.long 0x0 1. "scrwen,Read Write Based Scheduling Enable" "0,1" newline bitfld.long 0x0 0. "scqosen,QoS Level Based Scheduling Enable" "0,1" line.long 0x4 "DBSCHCNT1,Scheduler Unit Operation Setting Register 1" hexmask.long.byte 0x4 12.--15. 1. "schch3,Channel Number for Physical Channel 3 Setting" hexmask.long.byte 0x4 8.--11. 1. "schch2,Channel Number for Physical Channel 2 Setting" newline hexmask.long.byte 0x4 4.--7. 1. "schch1,Channel Number for Physical Channel 1 Setting" hexmask.long.byte 0x4 0.--3. 1. "schch0,Channel Number for Physical Channel 0 Setting" group.long 0x1010++0x3 line.long 0x0 "DBSCHSZ0,Size Miss Scheduling Setting Register 0" hexmask.long.byte 0x0 0.--7. 1. "szth,Size Miss Threshold Setting" group.long 0x1020++0x7 line.long 0x0 "DBSCHRW0,Read/Write Scheduling Setting Register 0" hexmask.long.byte 0x0 28.--31. 1. "rdstptol3,Stop Tolerance for Read Period on Quantization Leve 3" hexmask.long.byte 0x0 24.--27. 1. "rdstptol2,Stop Tolerance for Read Period on Quantization Leve 2" newline hexmask.long.byte 0x0 20.--23. 1. "rdstptol1,Stop Tolerance for Read Period on Quantization Leve 1" hexmask.long.byte 0x0 16.--19. 1. "rdstptol0,Stop Tolerance for Read Period on Quantization Leve 0" newline hexmask.long.byte 0x0 12.--15. 1. "wrstptol3,Stop Tolerance for Write Period on Quantization Leve 3" hexmask.long.byte 0x0 8.--11. 1. "wrstptol2,Stop Tolerance for Write Period on Quantization Leve 2" newline hexmask.long.byte 0x0 4.--7. 1. "wrstptol1,Stop Tolerance for Write Period on Quantization Leve 1" hexmask.long.byte 0x0 0.--3. 1. "wrstptol0,Stop Tolerance for Write Period on Quantization Leve 0" line.long 0x4 "DBSCHRW1,Read/Write Scheduling Setting Register 1" hexmask.long.byte 0x4 0.--7. 1. "sctrfcab,REF to ACT REF for All Banks Interval Setting for scheduler" group.long 0x1030++0xF line.long 0x0 "DBSCHQOS00,QoS Level Operation Setting Register 00" hexmask.long.word 0x0 0.--15. 1. "qos0ini,QoS Level 0 Counter Initial Value Setting" line.long 0x4 "DBSCHQOS01,QoS Level Operation Setting Register 01" hexmask.long.word 0x4 0.--15. 1. "qos0th0,QoS Level 0 Threshold 0 Setting" line.long 0x8 "DBSCHQOS02,QoS Level Operation Setting Register 02" hexmask.long.word 0x8 0.--15. 1. "qos0th1,QoS Level 0 Threshold 1 Setting" line.long 0xC "DBSCHQOS03,QoS Level Operation Setting Register 03" hexmask.long.word 0xC 0.--15. 1. "qos0th2,QoS Level 0 Threshold 2 Setting" group.long 0x1070++0xF line.long 0x0 "DBSCHQOS40,QoS Level Operation Setting Register 40" hexmask.long.word 0x0 0.--15. 1. "qos4ini,QoS Level 4 Counter Initial Value Setting" line.long 0x4 "DBSCHQOS41,QoS Level Operation Setting Register 41" hexmask.long.word 0x4 0.--15. 1. "qos4th0,QoS Level 4 Threshold 0 Setting" line.long 0x8 "DBSCHQOS42,QoS Level Operation Setting Register 42" hexmask.long.word 0x8 0.--15. 1. "qos4th1,QoS Level 4 Threshold 1 Setting" line.long 0xC "DBSCHQOS43,QoS Level Operation Setting Register 43" hexmask.long.word 0xC 0.--15. 1. "qos4th2,QoS Level 4 Threshold 2 Setting" group.long 0x10C0++0xF line.long 0x0 "DBSCHQOS90,QoS Level Operation Setting Register 90" hexmask.long.word 0x0 0.--15. 1. "qos9ini,QoS Level 9 Counter Initial Value Setting" line.long 0x4 "DBSCHQOS91,QoS Level Operation Setting Register 91" hexmask.long.word 0x4 0.--15. 1. "qos9th0,QoS Level 9 Threshold 0 Setting" line.long 0x8 "DBSCHQOS92,QoS Level Operation Setting Register 92" hexmask.long.word 0x8 0.--15. 1. "qos9th1,QoS Level 9 Threshold 1 Setting" line.long 0xC "DBSCHQOS93,QoS Level Operation Setting Register 93" hexmask.long.word 0xC 0.--15. 1. "qos9th2,QoS Level 9 Threshold 2 Setting" group.long 0x10F0++0x3F line.long 0x0 "DBSCHQOS120,QoS Level Operation Setting Register 120" hexmask.long.word 0x0 0.--15. 1. "qos12ini,QoS Level 12 Counter Initial Value Setting" line.long 0x4 "DBSCHQOS121,QoS Level Operation Setting Register 121" hexmask.long.word 0x4 0.--15. 1. "qos12th0,QoS Level 12 Threshold 0 Setting" line.long 0x8 "DBSCHQOS122,QoS Level Operation Setting Register 122" hexmask.long.word 0x8 0.--15. 1. "qos12th1,QoS Level 12 Threshold 1 Setting" line.long 0xC "DBSCHQOS123,QoS Level Operation Setting Register 123" hexmask.long.word 0xC 0.--15. 1. "qos12th2,QoS Level 12 Threshold 2 Setting" line.long 0x10 "DBSCHQOS130,QoS Level Operation Setting Register 130" hexmask.long.word 0x10 0.--15. 1. "qos13ini,QoS Level 13 Counter Initial Value Setting" line.long 0x14 "DBSCHQOS131,QoS Level Operation Setting Register 131" hexmask.long.word 0x14 0.--15. 1. "qos13th0,QoS Level 13 Threshold 0 Setting" line.long 0x18 "DBSCHQOS132,QoS Level Operation Setting Register 132" hexmask.long.word 0x18 0.--15. 1. "qos13th1,QoS Level 13 Threshold 1 Setting" line.long 0x1C "DBSCHQOS133,QoS Level Operation Setting Register 133" hexmask.long.word 0x1C 0.--15. 1. "qos13th2,QoS Level 13 Threshold 2 Setting" line.long 0x20 "DBSCHQOS140,QoS Level Operation Setting Register 140" hexmask.long.word 0x20 0.--15. 1. "qos14ini,QoS Level 14 Counter Initial Value Setting" line.long 0x24 "DBSCHQOS141,QoS Level Operation Setting Register 141" hexmask.long.word 0x24 0.--15. 1. "qos14th0,QoS Level 14 Threshold 0 Setting" line.long 0x28 "DBSCHQOS142,QoS Level Operation Setting Register 142" hexmask.long.word 0x28 0.--15. 1. "qos14th1,QoS Level 14 Threshold 1 Setting" line.long 0x2C "DBSCHQOS143,QoS Level Operation Setting Register 143" hexmask.long.word 0x2C 0.--15. 1. "qos14th2,QoS Level 14 Threshold 2 Setting" line.long 0x30 "DBSCHQOS150,QoS Level Operation Setting Register 150" hexmask.long.word 0x30 0.--15. 1. "qos15ini,QoS Level 15 Counter Initial Value Setting" line.long 0x34 "DBSCHQOS151,QoS Level Operation Setting Register 151" hexmask.long.word 0x34 0.--15. 1. "qos15th0,QoS Level 15 Threshold 0 Setting" line.long 0x38 "DBSCHQOS152,QoS Level Operation Setting Register 152" hexmask.long.word 0x38 0.--15. 1. "qos15th1,QoS Level 15 Threshold 1 Setting" line.long 0x3C "DBSCHQOS153,QoS Level Operation Setting Register 153" hexmask.long.word 0x3C 0.--15. 1. "qos15th2,QoS Level 15 Threshold 2 Setting" group.long 0x1700++0x3 line.long 0x0 "DBSCHFCTST0,Schedule Timing Setting Register 0" hexmask.long.byte 0x0 24.--31. 1. "scactact,ACT to ACT Interval Setting for scheduler" hexmask.long.byte 0x0 16.--23. 1. "scrdact,RD to ACT Interval Setting for scheduler" newline hexmask.long.byte 0x0 8.--15. 1. "scwract,WR to ACT Interval Setting for scheduler" hexmask.long.byte 0x0 0.--7. 1. "scpreact,PRE to ACT Interval Setting for scheduler" group.long 0x1708++0xB line.long 0x0 "DBSCHFCTST1,Schedule Timing Setting Register 1" hexmask.long.byte 0x0 24.--31. 1. "scrdwr,RD to WR Interval Setting for scheduler" hexmask.long.byte 0x0 16.--23. 1. "scwrrd,WR to RD Interval Setting for scheduler" newline hexmask.long.byte 0x0 8.--15. 1. "scactrdwr,ACT to RD WR Interval Setting for scheduler" hexmask.long.byte 0x0 0.--7. 1. "scasyncofs,Asynchronous stage offset Setting" line.long 0x4 "DBSCHFCTST2,Schedule Timing Setting Register 2" hexmask.long.byte 0x4 28.--31. 1. "wrperi3,Write Priority Period setting on Quantization Level 3" hexmask.long.byte 0x4 24.--27. 1. "wrperi2,Write Priority Period setting on Quantization Level 2" newline hexmask.long.byte 0x4 20.--23. 1. "wrperi1,Write Priority Period setting on Quantization Level 1" hexmask.long.byte 0x4 16.--19. 1. "wrperi0,Write Priority Period setting on Quantization Level 0" newline hexmask.long.byte 0x4 12.--15. 1. "rdperi3,Read Priority Period setting on Quantization Level 3" hexmask.long.byte 0x4 8.--11. 1. "rdperi2,Read Priority Period setting on Quantization Level 2" newline hexmask.long.byte 0x4 4.--7. 1. "rdperi1,Read Priority Period setting on Quantization Level 1" hexmask.long.byte 0x4 0.--3. 1. "rdperi0,Read Priority Period setting on Quantization Level 0" line.long 0x8 "DBSCHTR0,Data Transfer Cycle Setting Register 0" hexmask.long.byte 0x8 24.--31. 1. "scdt3,Data Transfer Cycle Setting for 256 Bytes Data" hexmask.long.byte 0x8 16.--23. 1. "scdt2,Data Transfer Cycle Setting for 192 Bytes Data" newline hexmask.long.byte 0x8 8.--15. 1. "scdt1,Data Transfer Cycle Setting for 128 Bytes Data" hexmask.long.byte 0x8 0.--7. 1. "scdt0,Data Transfer Cycle Setting for 64 Bytes Data" group.long 0x1800++0x1F line.long 0x0 "DBMRRDR0,Mode Register Read Data Register 0" hexmask.long.byte 0x0 8.--15. 1. "mrrdr01,MRR Read Data for Channel 0 A Rank 1" hexmask.long.byte 0x0 0.--7. 1. "mrrdr00,MRR Read Data for Channel 0 A Rank 0" line.long 0x4 "DBMRRDR1,Mode Register Read Data Register 1" hexmask.long.byte 0x4 8.--15. 1. "mrrdr11,MRR Read Data for Channel 0 B Rank 1" hexmask.long.byte 0x4 0.--7. 1. "mrrdr10,MRR Read Data for Channel 0 B Rank 0" line.long 0x8 "DBMRRDR2,Mode Register Read Data Register 2" hexmask.long.byte 0x8 8.--15. 1. "mrrdr21,MRR Read Data for Channel 1 A Rank 1" hexmask.long.byte 0x8 0.--7. 1. "mrrdr20,MRR Read Data for Channel 1 A Rank 0" line.long 0xC "DBMRRDR3,Mode Register Read Data Register 3" hexmask.long.byte 0xC 8.--15. 1. "mrrdr31,MRR Read Data for Channel 1 B Rank 1" hexmask.long.byte 0xC 0.--7. 1. "mrrdr30,MRR Read Data for Channel 1 B Rank 0" line.long 0x10 "DBMRRDR4,Mode Register Read Data Register 4" hexmask.long.byte 0x10 8.--15. 1. "mrrdr41,MRR Read Data for Channel 2 A Rank 1" hexmask.long.byte 0x10 0.--7. 1. "mrrdr40,MRR Read Data for Channel 2 A Rank 0" line.long 0x14 "DBMRRDR5,Mode Register Read Data Register 5" hexmask.long.byte 0x14 8.--15. 1. "mrrdr51,MRR Read Data for Channel 2 B Rank 1" hexmask.long.byte 0x14 0.--7. 1. "mrrdr50,MRR Read Data for Channel 2 B Rank 0" line.long 0x18 "DBMRRDR6,Mode Register Read Data Register 6" hexmask.long.byte 0x18 8.--15. 1. "mrrdr61,MRR Read Data for Channel 3 A Rank 1" hexmask.long.byte 0x18 0.--7. 1. "mrrdr60,MRR Read Data for Channel 3 A Rank 0" line.long 0x1C "DBMRRDR7,Mode Register Read Data Register 7" hexmask.long.byte 0x1C 8.--15. 1. "mrrdr71,MRR Read Data for Channel 3 B Rank 1" hexmask.long.byte 0x1C 0.--7. 1. "mrrdr70,MRR Read Data for Channel 3 B Rank 0" group.long 0x3010++0x3 line.long 0x0 "DBMONCONF4,Monitor Configuration Register 4" bitfld.long 0x0 20.--22. "mnstatsel,Monitor0 QoS level" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--19. 1. "mn0qoslv,BUFCAM status selection" group.long 0x7000++0x2B line.long 0x0 "DBFSINTXXX00A,Fusa Interrupt Indication Register 0 for AXI Domain" bitfld.long 0x0 31. "intexdclaxa,Comparator error of DCLS for clk_axi group Interrupt indication" "0,1" bitfld.long 0x0 30. "intexdclsra,Comparator error of DCLS group sram interrupt indication" "0,1" newline bitfld.long 0x0 10. "intodasbda,OrderID error in AXI64 Bch clk_dbs side Interrupt indication" "0,1" bitfld.long 0x0 9. "intodasrda,OrderID error in AXI64 Rch clk_dbs side Interrupt indication" "0,1" newline bitfld.long 0x0 8. "intodasbxa,OrderID error in AXI64 Bch clk_axi side Interrupt indication" "0,1" bitfld.long 0x0 7. "intodasrxa,OrderID error in AXI64 Rch clk_axi side Interrupt indication" "0,1" newline bitfld.long 0x0 6. "intodaswxa,OrderID error in AXI64 Wch clk_axi side Interrupt indication" "0,1" bitfld.long 0x0 5. "intodasawa,OrderID error in AXI64 AWch clk_axi side Interrupt indication" "0,1" newline bitfld.long 0x0 4. "intodasara,OrderID error in AXI64 ARch clk_axi side Interrupt indication" "0,1" bitfld.long 0x0 2. "intdxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt indication" "0,1" newline bitfld.long 0x0 1. "intdxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt indication" "0,1" bitfld.long 0x0 0. "intdxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt indication" "0,1" line.long 0x4 "DBFSINTXXX01A,Fusa Interrupt Indication Register 1 for AXI Domain" bitfld.long 0x4 22. "intnomem1a,No mem error in address decoder of dbsccore1 interrupt indication" "0,1" bitfld.long 0x4 21. "intedbccr1a,Cache RAM duplication error interrupt indication for dbsccore1" "0,1" newline bitfld.long 0x4 20. "intcxfcprd1a,CRC error in FCPRD for core1 Interrupt indication for dbsccore1" "0,1" bitfld.long 0x4 19. "intdxamawx1a,EDC error in AXMM W Ch Interrupt indication for dbsccore1" "0,1" newline bitfld.long 0x4 18. "intdxamaw1a,EDC error in AXMM AW Ch Interrupt indication for dbsccore1" "0,1" bitfld.long 0x4 17. "intdxamar1a,EDC error in AXMM AR Ch Interrupt indication for dbsccore1" "0,1" newline bitfld.long 0x4 16. "intepdvaxi1a,POST error in AXI domain interrupt indication for dbsccore1" "0,1" bitfld.long 0x4 6. "intnomem0a,No mem error in address decoder of dbsccore0 interrupt indication" "0,1" newline bitfld.long 0x4 5. "intedbccr0a,Cache RAM duplication error interrupt indication for dbsccore0" "0,1" bitfld.long 0x4 4. "intcxfcprd0a,CRC error in FCPRD for core1 Interrupt indication for dbsccore0" "0,1" newline bitfld.long 0x4 3. "intdxamawx0a,EDC error in AXMM W Ch Interrupt indication for dbsccore0" "0,1" bitfld.long 0x4 2. "intdxamaw0a,EDC error in AXMM AW Ch Interrupt indication for dbsccore0" "0,1" newline bitfld.long 0x4 1. "intdxamar0a,EDC error in AXMM AR Ch Interrupt indication for dbsccore0" "0,1" bitfld.long 0x4 0. "intepdvaxi0a,POST error in AXI domain interrupt indication for dbsccore0" "0,1" line.long 0x8 "DBFSINTXXX02A,Fusa Interrupt Indication Register 2 for AXI Domain" hexmask.long.byte 0x8 24.--31. 1. "intcmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt indication for dbsccore0" hexmask.long.byte 0x8 16.--23. 1. "intcdbcsr0a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt indication for dbsccore0" newline hexmask.long.byte 0x8 8.--15. 1. "intcmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt indication for dbsccore0" hexmask.long.byte 0x8 0.--7. 1. "intcdbcrr0a,ECC error (detect: 1bit error and correct) for read response Interrupt indication for dbsccore0" line.long 0xC "DBFSINTXXX03A,Fusa Interrupt Indication Register 3 for AXI Domain" hexmask.long 0xC 0.--31. 1. "intcdbcdr0a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt indication for dbsccore0" line.long 0x10 "DBFSINTXXX04A,Fusa Interrupt Indication Register 4 for AXI Domain" hexmask.long 0x10 0.--31. 1. "intcmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt indication for dbsccore0" line.long 0x14 "DBFSINTXXX05A,Fusa Interrupt Indication Register 5 for AXI Domain" hexmask.long.byte 0x14 24.--31. 1. "intcmbcsr1a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt indication for dbsccore1" hexmask.long.byte 0x14 16.--23. 1. "intcdbcsr1a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt indication for dbsccore1" newline hexmask.long.byte 0x14 8.--15. 1. "intcmbcrr1a,ECC error (multi: over 2bit error) for read response Interrupt indication for dbsccore1" hexmask.long.byte 0x14 0.--7. 1. "intcdbcrr1a,ECC error (detect: 1bit error and correct) for read response Interrupt indication for dbsccore1" line.long 0x18 "DBFSINTXXX06A,Fusa Interrupt Indication Register 6 for AXI Domain" hexmask.long 0x18 0.--31. 1. "intcdbcdr1a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt indication for dbsccore1" line.long 0x1C "DBFSINTXXX07A,Fusa Interrupt Indication Register 7 for AXI Domain" hexmask.long 0x1C 0.--31. 1. "intcmbcdr1a,ECC error (multi: over 2bit error) for DRAM RMW interrupt indication for dbsccore1" line.long 0x20 "DBFSINTXXX08A,Fusa Interrupt Indication Register 8 for AXI Domain" bitfld.long 0x20 18. "intexbcdr1a,ECC error injection for ECC checker for DRAM RMW interrupt indication for dbsccore1" "0,1" bitfld.long 0x20 17. "intexbcsr1a,ECC error injection for ECC checker for SystemRAM RMW Interrupt indication for dbsccore1" "0,1" newline bitfld.long 0x20 16. "intexbcrr1a,ECC error injection for ECC checker for read response Interrupt indication for dbsccore1" "0,1" bitfld.long 0x20 2. "intexbcdr0a,ECC error injection for ECC checker for DRAM RMW interrupt indication for dbsccore0" "0,1" newline bitfld.long 0x20 1. "intexbcsr0a,ECC error injection for ECC checker for SystemRAM RMW Interrupt indication for dbsccore0" "0,1" bitfld.long 0x20 0. "intexbcrr0a,ECC error injection for ECC checker for read response Interrupt indication for dbsccore0" "0,1" line.long 0x24 "DBFSINTXXX09A,Fusa Interrupt Indication Register 9 for AXI Domain" bitfld.long 0x24 25. "intoddvard3a,OrderID error of isbus async read ch. interrupt indication for memory channel 3" "0,1" bitfld.long 0x24 24. "intdxdvard3a,EDC error of isbus async read ch. interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x24 17. "intoddvard2a,OrderID error of isbus async read ch. interrupt indication for memory channel 2" "0,1" bitfld.long 0x24 16. "intdxdvard2a,EDC error of isbus async read ch. interrupt indication for memory channel 2" "0,1" newline bitfld.long 0x24 9. "intoddvard1a,OrderID error of isbus async read ch. interrupt indication for memory channel 1" "0,1" bitfld.long 0x24 8. "intdxdvard1a,EDC error of isbus async read ch. interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x24 1. "intoddvard0a,OrderID error of isbus async read ch. interrupt indication for memory channel 0" "0,1" bitfld.long 0x24 0. "intdxdvard0a,EDC error of isbus async read ch. interrupt indication for memory channel 0" "0,1" line.long 0x28 "DBFSINTXXX10A,Fusa Interrupt Indication Register 10 for AXI Domain" hexmask.long.word 0x28 0.--15. 1. "intxxasynsba,Async sideband errors in axi domain" group.long 0x7040++0x3 line.long 0x0 "DBFSINTCLR00A,Fusa Interrupt Clear Register for AXI Domain" bitfld.long 0x0 0. "icldclsa,Clear safety error interrupt signal (level) for clk_axi domain" "0,1" group.long 0x7080++0x2B line.long 0x0 "DBFSINTENB00A,Fusa Interrupt Enable Register 0 for AXI Domain" bitfld.long 0x0 31. "ienexdclaxa,Comparator error of DCLS for clk_axi group Interrupt enable bit" "0,1" bitfld.long 0x0 30. "ienexdclsra,Comparator error of DCLS group sram interrupt enable bit" "0,1" newline bitfld.long 0x0 10. "ienodasbda,OrderID error in AXI64 Bch clk_dbs side Interrupt enable bit" "0,1" bitfld.long 0x0 9. "ienodasrda,OrderID error in AXI64 Rch clk_dbs side Interrupt enable bit" "0,1" newline bitfld.long 0x0 8. "ienodasbxa,OrderID error in AXI64 Bch clk_axi side Interrupt enable bit" "0,1" bitfld.long 0x0 7. "ienodasrxa,OrderID error in AXI64 Rch clk_axi side Interrupt enable bit" "0,1" newline bitfld.long 0x0 6. "ienodaswxa,OrderID error in AXI64 Wch clk_axi side Interrupt enable bit" "0,1" bitfld.long 0x0 5. "ienodasawa,OrderID error in AXI64 AWch clk_axi side Interrupt enable bit" "0,1" newline bitfld.long 0x0 4. "ienodasara,OrderID error in AXI64 ARch clk_axi side Interrupt enable bit" "0,1" bitfld.long 0x0 2. "iendxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt enable bit" "0,1" newline bitfld.long 0x0 1. "iendxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt enable bit" "0,1" bitfld.long 0x0 0. "iendxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt enable bit." "0,1" line.long 0x4 "DBFSINTENB01A,Fusa Interrupt Enable Register 1 for AXI Domain" bitfld.long 0x4 22. "iennomem1a,No mem error in address decoder of dbsccore1 interrupt enable bit" "0,1" bitfld.long 0x4 21. "ienedbccr1a,Cache RAM duplication error interrupt enable bit for dbsccore1" "0,1" newline bitfld.long 0x4 20. "iencxfcprd1a,ECC error in FCPRD for core1 Interrupt enable bit" "0,1" bitfld.long 0x4 19. "iendxamawx1a,EDC error in AXMM W Ch Interrupt enable bit for dbsccore1" "0,1" newline bitfld.long 0x4 18. "iendxamaw1a,EDC error in AXMM AR Ch Interrupt enable bit for dbsccore1" "0,1" bitfld.long 0x4 17. "iendxamar1a,EDC error in AXMM AW Ch Interrupt enable bit for dbsccore1" "0,1" newline bitfld.long 0x4 16. "ienepdvaxi1a,POST error in AXI domain interrupt enable bit for dbsccore1" "0,1" bitfld.long 0x4 6. "iennomem0a,No mem error in address decoder of dbsccore0 interrupt enable bit" "0,1" newline bitfld.long 0x4 5. "ienedbccr0a,Cache RAM duplication error interrupt enable bit for dbsccore0" "0,1" bitfld.long 0x4 4. "iencxfcprd0a,ECC error in FCPRD for core0 Interrupt enable bit for dbsccore0" "0,1" newline bitfld.long 0x4 3. "iendxamawx0a,EDC error in AXMM W Ch Interrupt enable bit for dbsccore0" "0,1" bitfld.long 0x4 2. "iendxamaw0a,EDC error in AXMM AW Ch Interrupt enable bit for dbsccore0" "0,1" newline bitfld.long 0x4 1. "iendxamar0a,EDC error in AXMM AR Ch Interrupt enable bit for dbsccore0" "0,1" bitfld.long 0x4 0. "ienepdvaxi0a,POST error in AXI domain interrupt enable bit for dbsccore0" "0,1" line.long 0x8 "DBFSINTENB02A,Fusa Interrupt Enable Register 2 for AXI Domain" hexmask.long.byte 0x8 24.--31. 1. "iencmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt enable bit for dbsccore0" hexmask.long.byte 0x8 16.--23. 1. "iencdbcsr0a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt enable bit for dbsccore0" newline hexmask.long.byte 0x8 8.--15. 1. "iencmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt enable bit for dbsccore0" hexmask.long.byte 0x8 0.--7. 1. "iencdbcrr0a,ECC error (detect: 1bit error and correct) for read response Interrupt enable bit for dbsccore0" line.long 0xC "DBFSINTENB03A,Fusa Interrupt Enable Register 3 for AXI Domain" hexmask.long 0xC 0.--31. 1. "iencdbcdr0a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt enable bit for dbsccore0" line.long 0x10 "DBFSINTENB04A,Fusa Interrupt Enable Register 4 for AXI Domain" hexmask.long 0x10 0.--31. 1. "iencmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt enable bit for dbsccore0" line.long 0x14 "DBFSINTENB05A,Fusa Interrupt Enable Register 5 for AXI Domain" hexmask.long.byte 0x14 24.--31. 1. "iencmbcsr1a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt enable bit for dbsccore1" hexmask.long.byte 0x14 16.--23. 1. "iencdbcsr1a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt enable bit for dbsccore1" newline hexmask.long.byte 0x14 8.--15. 1. "iencmbcrr1a,ECC error (multi: over 2bit error) for read response Interrupt enable bit for dbsccore1" hexmask.long.byte 0x14 0.--7. 1. "iencdbcrr1a,ECC error (detect: 1bit error and correct) for read response Interrupt enable bit for dbsccore1" line.long 0x18 "DBFSINTENB06A,Fusa Interrupt Enable Register 6 for AXI Domain" hexmask.long 0x18 0.--31. 1. "iencdbcdr1a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt enable bit for dbsccore1" line.long 0x1C "DBFSINTENB07A,Fusa Interrupt Enable Register 7 for AXI Domain" hexmask.long 0x1C 0.--31. 1. "iencmbcdr1a,ECC error (multi: over 2bit error) for DRAM RMW interrupt enable bit for dbsccore1" line.long 0x20 "DBFSINTENB08A,Fusa Interrupt Enable Register 8 for AXI Domain" bitfld.long 0x20 18. "ienexbcdr1a,ECC error injection for ECC checker for DRAM RMW interrupt enable bit for dbsccore1" "0,1" bitfld.long 0x20 17. "ienexbcsr1a,ECC error injection for ECC checker for SystemRAM RMW Interrupt enable bit for dbsccore1" "0,1" newline bitfld.long 0x20 16. "ienexbcrr1a,ECC error injection for ECC checker for read response Interrupt enable bit for dbsccore1" "0,1" bitfld.long 0x20 2. "ienexbcdr0a,ECC error injection for ECC checker for DRAM RMW interrupt enable bit for dbsccore0" "0,1" newline bitfld.long 0x20 1. "ienexbcsr0a,ECC error injection for ECC checker for SystemRAM RMW Interrupt enable bit for dbsccore0" "0,1" bitfld.long 0x20 0. "ienexbcrr0a,ECC error injection for ECC checker for read response Interrupt enable bit for dbsccore0" "0,1" line.long 0x24 "DBFSINTENB09A,Fusa Interrupt Enable Register 9 for AXI Domain" bitfld.long 0x24 25. "ienoddvard3a,OrderID error of isbus async read ch. interrupt enable for memory channel 3" "0,1" bitfld.long 0x24 24. "iendxdvard3a,EDC error of isbus async read ch. interrupt enable for memory channel 3" "0,1" newline bitfld.long 0x24 17. "ienoddvard2a,OrderID error of isbus async read ch. interrupt enable for memory channel 2" "0,1" bitfld.long 0x24 16. "iendxdvard2a,EDC error of isbus async read ch. interrupt enable for memory channel 2" "0,1" newline bitfld.long 0x24 9. "ienoddvard1a,OrderID error of isbus async read ch. interrupt enable for memory channel 1" "0,1" bitfld.long 0x24 8. "iendxdvard1a,EDC error of isbus async read ch. interrupt enable for memory channel 1" "0,1" newline bitfld.long 0x24 1. "ienoddvard0a,OrderID error of isbus async read ch. interrupt enable for memory channel 0" "0,1" bitfld.long 0x24 0. "iendxdvard0a,EDC error of isbus async read ch. interrupt enable for memory channel 0" "0,1" line.long 0x28 "DBFSINTENB10A,Fusa Interrupt Enable Register 10 for AXI Domain" hexmask.long.word 0x28 0.--15. 1. "ienxxasynsba,Async sideband errors interrupt enable in axi domain" group.long 0x7100++0x1F line.long 0x0 "DBFSINJECT00A,Fusa Injection Mode Register 0 for AXI Domain" bitfld.long 0x0 31. "ijtexdclaxa,Comparator error of DCLS for clk_axi group Interrupt injection mode" "0,1" bitfld.long 0x0 30. "ijtexdclsra,Comparator error of DCLS for sram Interrupt injection mode" "0,1" newline bitfld.long 0x0 10. "ijtodasbda,OrderID error in AXI64 Bch clk_dbs side Interrupt injection mode" "0,1" bitfld.long 0x0 9. "ijtodasrda,OrderID error in AXI64 Rch clk_dbs side Interrupt injection mode" "0,1" newline bitfld.long 0x0 8. "ijtodasbxa,OrderID error in AXI64 Bch clk_axi side Interrupt injection mode" "0,1" bitfld.long 0x0 7. "ijtodasrxa,OrderID error in AXI64 Rch clk_axi side Interrupt injection mode" "0,1" newline bitfld.long 0x0 6. "ijtodaswxa,OrderID error in AXI64 Wch clk_axi side Interrupt injection mode" "0,1" bitfld.long 0x0 5. "ijtodasawa,OrderID error in AXI64 AWch clk_axi side Interrupt injection mode" "0,1" newline bitfld.long 0x0 4. "ijtodasara,OrderID error in AXI64 ARch clk_axi side Interrupt injection mode" "0,1" bitfld.long 0x0 2. "ijtdxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt injection mode" "0,1" newline bitfld.long 0x0 1. "ijtdxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt injection mode" "0,1" bitfld.long 0x0 0. "ijtdxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt injection mode" "0,1" line.long 0x4 "DBFSINJECT01A,Fusa Injection Mode Register 1 for AXI Domain" bitfld.long 0x4 22. "ijtnomem1a,No mem error in address decoder of dbsccore1 interrupt injection mode" "0,1" bitfld.long 0x4 21. "ijtedbccr1a,Cache RAM duplication error interrupt injection mode for dbsccore1" "0,1" newline bitfld.long 0x4 20. "ijtcxfcprd1a,CRC error in FCPRD for core1 Interrupt injection mode" "0,1" bitfld.long 0x4 19. "ijtdxamawx1a,EDC error in AXMM W Ch Interrupt injection mode for dbsccore1" "0,1" newline bitfld.long 0x4 18. "ijtdxamaw1a,EDC error in AXMM AR Ch Interrupt injection mode for dbsccore1" "0,1" bitfld.long 0x4 17. "ijtdxamar1a,EDC error in AXMM AW Ch Interrupt injection mode for dbsccore1" "0,1" newline bitfld.long 0x4 16. "ijtepdvaxi1a,POST error in AXI domain interrupt injection mode for dbsccore1" "0,1" bitfld.long 0x4 6. "ijtnomem0a,No mem error in address decoder of dbsccore0 interrupt injection mode" "0,1" newline bitfld.long 0x4 5. "ijtedbccr0a,Cache RAM duplication error interrupt injection mode for dbsccore0" "0,1" bitfld.long 0x4 4. "ijtcxfcprd0a,CRC error in FCPRD for core0 Interrupt injection mode for dbsccore0" "0,1" newline bitfld.long 0x4 3. "ijtdxamawx0a,EDC error in AXMM W Ch Interrupt injection mode for dbsccore0" "0,1" bitfld.long 0x4 2. "ijtdxamaw0a,EDC error in AXMM AW Ch Interrupt injection mode for dbsccore0" "0,1" newline bitfld.long 0x4 1. "ijtdxamar0a,EDC error in AXMM AR Ch Interrupt injection mode for dbsccore0" "0,1" bitfld.long 0x4 0. "ijtepdvaxi0a,POST error in AXI domain interrupt injection mode for dbsccore0" "0,1" line.long 0x8 "DBFSINJECT02A,Fusa Injection Mode Register 2 for AXI Domain" bitfld.long 0x8 24. "ijtcmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt injection mode for dbsccore0" "0,1" bitfld.long 0x8 16. "ijtcdbcsr0a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt injection mode for dbsccore0" "0,1" newline bitfld.long 0x8 8. "ijtcmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt injection mode for dbsccore0" "0,1" bitfld.long 0x8 0. "ijtcdbcrr0a,ECC error (detect: 1bit error and correct) for read response Interrupt injection mode for dbsccore0" "0,1" line.long 0xC "DBFSINJECT03A,Fusa Injection Mode Register 3 for AXI Domain" bitfld.long 0xC 0. "ijtcdbcdr0a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt injection mode for dbsccore0" "0,1" line.long 0x10 "DBFSINJECT04A,Fusa Injection Mode Register 4 for AXI Domain" bitfld.long 0x10 0. "ijtcmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt injection mode for dbsccore0" "0,1" line.long 0x14 "DBFSINJECT05A,Fusa Injection Mode Register 5 for AXI Domain" bitfld.long 0x14 24. "ijtcmbcsr1a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt injection mode for dbsccore1" "0,1" bitfld.long 0x14 16. "ijtcdbcsr1a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt injection mode for dbsccore1" "0,1" newline bitfld.long 0x14 8. "ijtcmbcrr1a,ECC error (multi: over 2bit error) for read response Interrupt injection mode for dbsccore1" "0,1" bitfld.long 0x14 0. "ijtcdbcrr1a,ECC error (detect: 1bit error and correct) for read response Interrupt injection mode for dbsccore1" "0,1" line.long 0x18 "DBFSINJECT06A,Fusa Injection Mode Register 6 for AXI Domain" bitfld.long 0x18 0. "ijtcdbcdr1a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt injection mode for dbsccore1" "0,1" line.long 0x1C "DBFSINJECT07A,Fusa Injection Mode Register 7 for AXI Domain" bitfld.long 0x1C 0. "ijtcmbcdr1a,ECC error (multi: over 2bit error) for DRAM RMW interrupt injection mode for dbsccore1" "0,1" group.long 0x7124++0x7 line.long 0x0 "DBFSINJECT09A,Fusa Injection Mode Register 8 for AXI Domain" bitfld.long 0x0 25. "ijtoddvard3a,OrderID error of isbus async read ch. interrupt injection mode for memory channel 3" "0,1" bitfld.long 0x0 24. "ijtdxdvard3a,EDC error of isbus async read ch. interrupt injection mode for memory channel 3" "0,1" newline bitfld.long 0x0 17. "ijtoddvard2a,OrderID error of isbus async read ch. interrupt injection mode for memory channel 2" "0,1" bitfld.long 0x0 16. "ijtdxdvard2a,EDC error of isbus async read ch. interrupt injection mode for memory channel 2" "0,1" newline bitfld.long 0x0 9. "ijtoddvard1a,OrderID error of isbus async read ch. interrupt injection mode for memory channel 1" "0,1" bitfld.long 0x0 8. "ijtdxdvard1a,EDC error of isbus async read ch. interrupt injection mode for memory channel 1" "0,1" newline bitfld.long 0x0 1. "ijtoddvard0a,OrderID error of isbus async read ch. interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x0 0. "ijtdxdvard0a,EDC error of isbus async read ch. interrupt injection mode for memory channel 0" "0,1" line.long 0x4 "DBFSINJECT10A,Fusa Injection Mode Register 9 for AXI Domain" hexmask.long.word 0x4 0.--15. 1. "ijtxxasynsba,Async sideband errors interrupt injection mode" group.long 0x7200++0x1F line.long 0x0 "DBFSINTCNT0A,Fusa Interrupt Counter Register 0 for AXI Domain" hexmask.long.byte 0x0 16.--23. 1. "cntdxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt counter mode" hexmask.long.byte 0x0 8.--15. 1. "cntdxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt counter mode" newline hexmask.long.byte 0x0 0.--7. 1. "cntdxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt counter mode" line.long 0x4 "DBFSINTCNT1A,Fusa Interrupt Counter Register 1 for AXI Domain" hexmask.long.byte 0x4 24.--31. 1. "cntcxfcprd0a,CRC error in FCPRD Interrupt counter for dbsccore0" hexmask.long.byte 0x4 16.--23. 1. "cntdxamawx0a,EDC error in AXMM W Ch Interrupt counter for dbsccore0" newline hexmask.long.byte 0x4 8.--15. 1. "cntdxamaw0a,EDC error in AXMM AW Ch Interrupt counter for dbsccore0" hexmask.long.byte 0x4 0.--7. 1. "cntdxamar0a,EDC error in AXMM AR Ch Interrupt counter for dbsccore0" line.long 0x8 "DBFSINTCNT2A,Fusa Interrupt Counter Register 2 for AXI Domain" hexmask.long.byte 0x8 24.--31. 1. "cntcxfcprd1a,CRC error in FCPRD Interrupt counter for dbsccore1" hexmask.long.byte 0x8 16.--23. 1. "cntdxamawx1a,EDC error in AXMM W Ch Interrupt counter for dbsccore1" newline hexmask.long.byte 0x8 8.--15. 1. "cntdxamaw1a,EDC error in AXMM AW Ch Interrupt counter for dbsccore1" hexmask.long.byte 0x8 0.--7. 1. "cntdxamar1a,EDC error in AXMM AR Ch Interrupt counter for dbsccore1" line.long 0xC "DBFSINTCNT3A,Fusa Interrupt Counter Register 3 for AXI Domain" hexmask.long.byte 0xC 24.--31. 1. "cntcmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt counter mode for dbsccore0" hexmask.long.byte 0xC 16.--23. 1. "cntcdbcsr0a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt counter mode for dbsccore0" newline hexmask.long.byte 0xC 8.--15. 1. "cntcmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt counter mode for dbsccore0" hexmask.long.byte 0xC 0.--7. 1. "cntcdbcrr0a,ECC error (detect: 1bit error and correct) for read response Interrupt counter mode for dbsccore0" line.long 0x10 "DBFSINTCNT04A,Fusa Interrupt Counter Register 4 for AXI Domain" hexmask.long.byte 0x10 8.--15. 1. "cntcmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt counter for dbsccore0" hexmask.long.byte 0x10 0.--7. 1. "cntcdbcdr0a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt counter for dbsccore0" line.long 0x14 "DBFSINTCNT05A,Fusa Interrupt Counter Register 5 for AXI Domain" hexmask.long.byte 0x14 24.--31. 1. "cntcmbcsr1a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt counter for dbsccore1" hexmask.long.byte 0x14 16.--23. 1. "cntcdbcsr1a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt counter for dbsccore1" newline hexmask.long.byte 0x14 8.--15. 1. "cntcmbcrr1a,ECC error (multi: over 2bit error) for read response Interrupt counter for dbsccore1" hexmask.long.byte 0x14 0.--7. 1. "cntcdbcrr1a,ECC error (detect: 1bit error and correct) for read response Interrupt counter for dbsccore1" line.long 0x18 "DBFSINTCNT06A,Fusa Interrupt Counter Register 6 for AXI Domain" hexmask.long.byte 0x18 8.--15. 1. "cntcmbcdr1a,ECC error (multi: over 2bit error) for DRAM RMW interrupt counter for dbsccore1" hexmask.long.byte 0x18 0.--7. 1. "cntcdbcdr1a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt counter for dbsccore1" line.long 0x1C "DBFSINTCNT07A,Fusa Interrupt Counter Register 7 for AXI Domain" hexmask.long.byte 0x1C 24.--31. 1. "cntdxdvard3a,EDC error of isbus async read ch. interrupt counter for memory channel3" hexmask.long.byte 0x1C 16.--23. 1. "cntdxdvard2a,EDC error of isbus async read ch. interrupt counter for memory channel2" newline hexmask.long.byte 0x1C 8.--15. 1. "cntdxdvard1a,EDC error of isbus async read ch. interrupt counter for memory channel1" hexmask.long.byte 0x1C 0.--7. 1. "cntdxdvard0a,EDC error of isbus async read ch. interrupt counter for memory channel0" group.long 0x7400++0x3 line.long 0x0 "DBFSCONFAXI0,Fusa AXI Configuration Register0 for AXI Domain" bitfld.long 0x0 13. "drameccen11,ECC protection enable for DDR access for rank1 on dbsccore1." "0,1" bitfld.long 0x0 12. "drameccen10,ECC protection enable for DDR access for rank0 on dbsccore1." "0,1" newline bitfld.long 0x0 9. "drameccen01,ECC protection enable for DDR access for rank1 on dbsccore0." "0,1" bitfld.long 0x0 8. "drameccen00,ECC protection enable for DDR access for rank0 on dbsccore0." "0,1" newline bitfld.long 0x0 4. "srameccdis,ECC protection disable for SysRAM access." "0,1" bitfld.long 0x0 0. "errcrctdis,Error correction disable." "0,1" group.long 0x7410++0xF line.long 0x0 "DBFSECCIJTCHK,Fusa ECC Injection Check Register for AXI Domain" hexmask.long.word 0x0 0.--13. 1. "eccijtchk,ECC check bits for error injection" line.long 0x4 "DBFSECCIJTERRL,Fusa ECC Injection Seeting Lowbitside Register for AXI Domain" hexmask.long 0x4 0.--31. 1. "eccijterrl,Invert any 64bit data and 14 check bits (Low bit side)" line.long 0x8 "DBFSECCIJTERRM,Fusa ECC Injection Seeting Midbitside Register for AXI Domain" hexmask.long 0x8 0.--31. 1. "eccijterrm,Invert any 64bit data and 14 check bits (Middle bit side)" line.long 0xC "DBFSECCIJTERRH,Fusa ECC Injection Seeting Hibitside Register for AXI Domain" hexmask.long.word 0xC 0.--13. 1. "eccijterrh,Invert any 64bit data and 14 check bits (High bit side)" group.long 0x7430++0xF line.long 0x0 "DBFSECCIJTADRL0,Fusa ECC Injection For Address LSBside Register for AXI Domain" hexmask.long 0x0 0.--31. 1. "eccijtadrl0,Specific address register for error injection for ECC chk.(LSB side)" line.long 0x4 "DBFSECCIJTADRH0,Fusa ECC Injection For Address MSBside Register for AXI Domain" hexmask.long.byte 0x4 0.--7. 1. "eccijtadrh0,Specific address register for error injection for ECC chk.(MSB side)" line.long 0x8 "DBFSECCIJTDATL0,Fusa ECC Injection For Data LSBside Register for AXI Domain" hexmask.long 0x8 0.--31. 1. "eccijtdatl0,Data for error injection(LSB side)" line.long 0xC "DBFSECCIJTDATH0,Fusa ECC Injection For Data MSBside Register for AXI Domain" hexmask.long 0xC 0.--31. 1. "eccijtdath0,Data for error injection(MSB side)" group.long 0x7450++0x7 line.long 0x0 "DBFSDRAMECCAREA00,Fusa ECC Protection Area Setting Rank0 Register0 for AXI Domain" hexmask.long 0x0 0.--31. 1. "drameccarea00,ECC protection area for rank0 on dbsccore0." line.long 0x4 "DBFSDRAMECCAREA01,Fusa ECC Protection Area Setting Rank1 Register0 for AXI Domain" hexmask.long 0x4 0.--31. 1. "drameccarea01,ECC protection area for rank1 on dbsccore0." group.long 0x7460++0x7 line.long 0x0 "DBFSDRAMECCAREA10,Fusa ECC Protection Area Setting Rank0 Register1 for AXI Domain" hexmask.long 0x0 0.--31. 1. "drameccarea10,ECC protection area for rank0 on dbsccore1." line.long 0x4 "DBFSDRAMECCAREA11,Fusa ECC Protection Area Setting Rank1 Register1 for AXI Domain" hexmask.long 0x4 0.--31. 1. "drameccarea11,ECC protection area for rank1 on dbsccore1." group.long 0x7480++0x3 line.long 0x0 "DBFSCTRLAXI0,Fusa AXI Contorol Register 0 for AXI Domain" bitfld.long 0x0 0. "postenaxi,Start POST for asynchronous bridge in devcnt. When this bit is asserted this bit is cleared to 0 at next cycle autmatically." "0,1" group.long 0x74A0++0x7 line.long 0x0 "DBFSCTRLBCAM0A,Fusa CAM Contorol Register 0 for AXI Domain" bitfld.long 0x0 0. "bcijtreq,Error injection for ECC of RMW. When this bit is asserted " "0,1" line.long 0x4 "DBFSCTRLBCAM1A,Fusa CAM Contorol Register 1 for AXI Domain" bitfld.long 0x4 0. "bcijtaddr,Enable of Error injection mode. If this bit is asserted error injection request is generated." "0,1" group.long 0x7510++0x1F line.long 0x0 "DBFSMNDEA0LA,Fusa Monitor Nomem Error Address LSBside Register 0 for AXI Domain" hexmask.long 0x0 0.--31. 1. "mndea0la,Nomem error (decode error) address LSB bits of dbsccore0" line.long 0x4 "DBFSMNDEA0HA,Fusa Monitor Nomem Error Address MSBside Register 0 for AXI Domain" hexmask.long.byte 0x4 0.--7. 1. "mndea0ha,Nomem error (decode error) address MSB bits of dbsccore0" line.long 0x8 "DBFSMNDESID0A,Fusa Monitor Nomem Error SrcID Register 0 for AXI Domain" hexmask.long.byte 0x8 0.--7. 1. "mndesid0a,Nomem error (decode error) source ID of dbsccore0" line.long 0xC "DBFSMNEDCSID0A,Fusa Monitor EDC Error SrcID Register 0 for AXI Domain" hexmask.long.byte 0xC 16.--23. 1. "mnedcsidwx0a,EDC error source ID for W channel of dbsccore0" hexmask.long.byte 0xC 8.--15. 1. "mnedcsidaw0a,EDC error source ID for AW channel of dbsccore0" newline hexmask.long.byte 0xC 0.--7. 1. "mnedcsidar0a,EDC error source ID for AR channel of dbsccore0" line.long 0x10 "DBFSMNDEA1LA,Fusa Monitor Nomem Error Address LSBside Register 1 for AXI Domain" hexmask.long 0x10 0.--31. 1. "mndea1la,Nomem error (decode error) address LSB bits of dbsccore1" line.long 0x14 "DBFSMNDEA1HA,Fusa Monitor Nomem Error Address MSBside Register 1 for AXI Domain" hexmask.long.byte 0x14 0.--7. 1. "mndea1ha,Nomem error (decode error) address MSB bits of dbsccore1" line.long 0x18 "DBFSMNDESID1A,Fusa Monitor Nomem Error SrcID Register 1 for AXI Domain" hexmask.long.byte 0x18 0.--7. 1. "mndesid1a,Nomem error (decode error) source ID of dbsccore1" line.long 0x1C "DBFSMNEDCSID1A,Fusa Monitor EDC Error SrcID Register 1 for AXI Domain" hexmask.long.byte 0x1C 16.--23. 1. "mnedcsidwx1a,EDC error source ID for W channel of dbsccore1" hexmask.long.byte 0x1C 8.--15. 1. "mnedcsidaw1a,EDC error source ID for AW channel of dbsccore1" newline hexmask.long.byte 0x1C 0.--7. 1. "mnedcsidar1a,EDC error source ID for AR channel of dbsccore1" group.long 0x7600++0x7 line.long 0x0 "DBFSCTRL00A,Fusa Control Register 0 for AXI Domain" bitfld.long 0x0 0. "srainidis,System-RAM initialization disable." "0,1" line.long 0x4 "DBFSCTRL01A,Fusa Control Register 1 for AXI Domain" bitfld.long 0x4 1. "ddrinistart1,DDR initialization start trigger for dbsccore1 (1-shot pulse clear right after asserting)" "0,1" bitfld.long 0x4 0. "ddrinistart0,DDR initialization start trigger for dbsccore0 (1-shot pulse clear right after asserting)" "0,1" group.long 0x7640++0xF line.long 0x0 "DBFSCONF00A,Fusa Configuration Register 0 for AXI Domain" bitfld.long 0x0 0.--1. "ddrinirank0,DDR initialization area rank address for dbsccore 0." "0,1,2,3" line.long 0x4 "DBFSCONF01A,Fusa Configuration Register 1 for AXI Domain" hexmask.long.word 0x4 16.--31. 1. "ddriniareae0,DDR initialization area end row address for dbsccore0." hexmask.long.word 0x4 0.--15. 1. "ddriniareas0,DDR initialization area start row address for dbsccore0." line.long 0x8 "DBFSCONF02A,Fusa Configuration Register 2 for AXI Domain" bitfld.long 0x8 0.--1. "ddrinirank1,DDR initialization area rank address for dbsccore 1." "0,1,2,3" line.long 0xC "DBFSCONF03A,Fusa Configuration Register 3 for AXI Domain" hexmask.long.word 0xC 16.--31. 1. "ddriniareae1,DDR initialization area end row address for dbsccore1." hexmask.long.word 0xC 0.--15. 1. "ddriniareas1,DDR initialization area start row address for dbsccore1." group.long 0x7680++0xB line.long 0x0 "DBFSSTAT00A,Fusa Status Register 0 for AXI Domain" bitfld.long 0x0 1. "srainiend1,System-RAM initialization completion of dbsccore1" "0,1" bitfld.long 0x0 0. "srainiend0,System-RAM initialization completion of dbsccore0" "0,1" line.long 0x4 "DBFSSTAT01A,Fusa Status Register 1 for AXI Domain" bitfld.long 0x4 1. "ddriniend1,DRAM initialization completion of dbsccore1" "0,1" bitfld.long 0x4 0. "ddriniend0,DRAM initialization completion of dbsccore0" "0,1" line.long 0x8 "DBFSSTAT02A,Fusa Status Register 2 for AXI Domain" bitfld.long 0x8 1. "bceccempty1,Status register for dbsccore1. mean that cache doesn't have dirty entry of ECC target." "0,1" bitfld.long 0x8 0. "bceccempty0,Status register for dbsccore0. mean that cache doesn't have dirty entry of ECC target." "0,1" group.long 0x7800++0xF line.long 0x0 "DBFSINTXXX00D,Fusa Interrupt Indication Register 0 for DFI Domain" bitfld.long 0x0 6. "intodaswxd,OrderID error in AXI64 Wch clk_axi side Interrupt indication" "0,1" bitfld.long 0x0 5. "intodasawd,OrderID error in AXI64 AWch clk_axi side Interrupt indication" "0,1" newline bitfld.long 0x0 4. "intodasard,OrderID error in AXI64 ARch clk_axi side Interrupt indication" "0,1" bitfld.long 0x0 2. "intdxaswxd,EDC error in AXSM W Ch clk_axi domain Interrupt indication" "0,1" newline bitfld.long 0x0 1. "intdxasawd,EDC error in AXSM AW Ch clk_axi domain Interrupt indication" "0,1" bitfld.long 0x0 0. "intdxasard,EDC error in AXSM AR Ch clk_axi domain Interrupt indication" "0,1" line.long 0x4 "DBFSINTXXX01D,Fusa Interrupt Indication Register 1 for DFI Domain" bitfld.long 0x4 31. "intexdcld1d,Comparator error of DCLS group dbs1 interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 30. "intpxpyrif1d,Parity error for PHY-Register I F (rdata) for memory channel1" "0,1" newline bitfld.long 0x4 25. "intoddvawr1d,OrderID error of isbus async write ch. interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 24. "intoddvacq1d,OrderID error of isbus async address (command queue) ch. interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x4 23. "intdxdvawr1d,EDC error of isbus async write ch. interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 22. "intdxdvacq1d,EDC error of isbus async address (command queue) ch. interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x4 21. "intoddvphy1d,OrderID error in DFI DDR PHY interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 20. "intoddvdbs1d,OrderID error in DFI DBSC interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x4 19. "intdxdvphy1d,EDC error in DFI DDR PHY interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 18. "intdxdvdbs1d,EDC error in DFI DBSC interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x4 17. "intepdvphy1d,POST error in ddrf interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 16. "intepdvdbs1d,POST error in DBSC domain interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x4 15. "intexdcld0d,Comparator error of DCLS group dbs0 interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 14. "intpxpyrif0d,Parity error for PHY-Register I F (rdata) for memory channel 0" "0,1" newline bitfld.long 0x4 9. "intoddvawr0d,OrderID error of isbus async write ch. interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 8. "intoddvacq0d,OrderID error of isbus async address (command queue) ch. interrupt indication for memory channel 0" "0,1" newline bitfld.long 0x4 7. "intdxdvawr0d,EDC error of isbus async write ch. interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 6. "intdxdvacq0d,EDC error of isbus async address (command queue) ch. interrupt indication for memory channel 0" "0,1" newline bitfld.long 0x4 5. "intoddvphy0d,OrderID error in DFI DDR PHY interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 4. "intoddvdbs0d,OrderID error in DFI DBSC interrupt indication for memory channel 0" "0,1" newline bitfld.long 0x4 3. "intdxdvphy0d,EDC error in DFI DDR PHY interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 2. "intdxdvdbs0d,EDC error in DFI DBSC interrupt indication for memory channel 0" "0,1" newline bitfld.long 0x4 1. "intepdvphy0d,POST error in ddrf interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 0. "intepdvdbs0d,POST error in DBSC domain interrupt indication for memory channel 0" "0,1" line.long 0x8 "DBFSINTXXX02D,Fusa Interrupt Indication Register 2 for DFI Domain" bitfld.long 0x8 31. "intexdcld3d,Comparator error of DCLS group dbs3 interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 30. "intpxpyrif3d,Parity error for PHY-Register I F (rdata) for memory channel3" "0,1" newline bitfld.long 0x8 25. "intoddvawr3d,OrderID error of isbus async write ch. interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 24. "intoddvacq3d,OrderID error of isbus async address (command queue) ch. interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x8 23. "intdxdvawr3d,EDC error of isbus async write ch. interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 22. "intdxdvacq3d,EDC error of isbus async address (command queue) ch. interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x8 21. "intoddvphy3d,OrderID error in DFI DDR PHY interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 20. "intoddvdbs3d,OrderID error in DFI DBSC interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x8 19. "intdxdvphy3d,EDC error in DFI DDR PHY interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 18. "intdxdvdbs3d,EDC error in DFI DBSC interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x8 17. "intepdvphy3d,POST error in ddrf interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 16. "intepdvdbs3d,POST error in DBSC domain interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x8 15. "intexdcld2d,Comparator error of DCLS group dbs2 interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 14. "intpxpyrif2d,Parity error for PHY-Register I F (rdata) for memory channel2" "0,1" newline bitfld.long 0x8 9. "intoddvawr2d,OrderID error of isbus async write ch. interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 8. "intoddvacq2d,OrderID error of isbus async address (command queue) ch. interrupt indication for memory channel 2" "0,1" newline bitfld.long 0x8 7. "intdxdvawr2d,EDC error of isbus async write ch. interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 6. "intdxdvacq2d,EDC error of isbus async address (command queue) ch. interrupt indication for memory channel 2" "0,1" newline bitfld.long 0x8 5. "intoddvphy2d,OrderID error in DFI DDR PHY interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 4. "intoddvdbs2d,OrderID error in DFI DBSC interrupt indication for memory channel 2" "0,1" newline bitfld.long 0x8 3. "intdxdvphy2d,EDC error in DFI DDR PHY interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 2. "intdxdvdbs2d,EDC error in DFI DBSC interrupt indication for memory channel 2" "0,1" newline bitfld.long 0x8 1. "intepdvphy2d,POST error in ddrf interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 0. "intepdvdbs2d,POST error in DBSC domain interrupt indication for memory channel 2" "0,1" line.long 0xC "DBFSINTXXX03D,Fusa Interrupt Indication Register 3 for DFI Domain" hexmask.long.word 0xC 0.--15. 1. "intxxasynsbd,Async sideband errors in dbs domain" group.long 0x7840++0x3 line.long 0x0 "DBFSINTCLR00D,Fusa Interrupt Clear Register for DFI Domain" bitfld.long 0x0 0. "icldclsd,Clear safety error interrupt signal (level) for clk_dbsc domain" "0,1" group.long 0x7880++0xF line.long 0x0 "DBFSINTENB00D,Fusa Interrupt Enable Register 0 for DFI Domain" bitfld.long 0x0 6. "ienodaswxd,OrderID error in AXI64 Wch clk_axi side interrupt enable" "0,1" bitfld.long 0x0 5. "ienodasawd,OrderID error in AXI64 AWch clk_axi side interrupt enable" "0,1" newline bitfld.long 0x0 4. "ienodasard,OrderID error in AXI64 ARch clk_axi side interrupt enable" "0,1" bitfld.long 0x0 2. "iendxaswxd,EDC error in AXSM W Ch clk_axi domain interrupt enable" "0,1" newline bitfld.long 0x0 1. "iendxasawd,EDC error in AXSM AW Ch clk_axi domain interrupt enable" "0,1" bitfld.long 0x0 0. "iendxasard,EDC error in AXSM AR Ch clk_axi domain interrupt enable" "0,1" line.long 0x4 "DBFSINTENB01D,Fusa Interrupt Enable Register 1 for DFI Domain" bitfld.long 0x4 31. "ienexdcld1d,Comparator error of DCLS group dbs1 interrupt enable" "0,1" bitfld.long 0x4 30. "ienpxpyrif1d,Parity error for PHY-Register I F (rdata) for memory channel1" "0,1" newline bitfld.long 0x4 25. "ienoddvawr1d,OrderID error of isbus async write ch. interrupt enable for memory channel 1" "0,1" bitfld.long 0x4 24. "ienoddvacq1d,OrderID error of isbus async address (command queue) ch. interrupt enable for memory channel 1" "0,1" newline bitfld.long 0x4 23. "iendxdvawr1d,EDC error of isbus async write ch. interrupt enable for memory channel 1" "0,1" bitfld.long 0x4 22. "iendxdvacq1d,EDC error of isbus async address (command queue) ch. interrupt enable for memory channel 1" "0,1" newline bitfld.long 0x4 21. "ienoddvphy1d,OrderID error in DFI DDR PHY interrupt enable bit for memory channel 1" "0,1" bitfld.long 0x4 20. "ienoddvdbs1d,OrderID error in DFI DBSC interrupt enable bit for memory channel 1" "0,1" newline bitfld.long 0x4 19. "iendxdvphy1d,EDC error in DFI DDR PHY interrupt enable bit for memory channel 1" "0,1" bitfld.long 0x4 18. "iendxdvdbs1d,EDC error in DFI DBSC interrupt enable bit for memory channel 1" "0,1" newline bitfld.long 0x4 17. "ienepdvphy1d,POST error in ddrf interrupt enable bit for memory channel 1" "0,1" bitfld.long 0x4 16. "ienepdvdbs1d,POST error in DBSC domain interrupt enable bit for memory channel 1" "0,1" newline bitfld.long 0x4 15. "ienexdcld0d,Comparator error of DCLS group dbs0 interrupt enable" "0,1" bitfld.long 0x4 14. "ienpxpyrif0d,Parity error for PHY-Register I F (rdata) for memory channel0" "0,1" newline bitfld.long 0x4 9. "ienoddvawr0d,OrderID error of isbus async write ch. interrupt enable for memory channel 0" "0,1" bitfld.long 0x4 8. "ienoddvacq0d,OrderID error of isbus async address (command queue) ch. interrupt enable for memory channel 0" "0,1" newline bitfld.long 0x4 7. "iendxdvawr0d,EDC error of isbus async write ch. interrupt enable for memory channel 0" "0,1" bitfld.long 0x4 6. "iendxdvacq0d,EDC error of isbus async address (command queue) ch. interrupt enable for memory channel 0" "0,1" newline bitfld.long 0x4 5. "ienoddvphy0d,OrderID error in DFI DDR PHY interrupt enable bit for memory channel 0" "0,1" bitfld.long 0x4 4. "ienoddvdbs0d,OrderID error in DFI DBSC interrupt enable bit for memory channel 0" "0,1" newline bitfld.long 0x4 3. "iendxdvphy0d,EDC error in DFI DDR PHY interrupt enable bit for memory channel 0" "0,1" bitfld.long 0x4 2. "iendxdvdbs0d,EDC error in DFI DBSC interrupt enable bit for memory channel 0" "0,1" newline bitfld.long 0x4 1. "ienepdvphy0d,POST error in ddrf interrupt enable bit for memory channel 0" "0,1" bitfld.long 0x4 0. "ienepdvdbs0d,POST error in DBSC domain interrupt enable bit for memory channel 0" "0,1" line.long 0x8 "DBFSINTENB02D,Fusa Interrupt Enable Register 2 for DFI Domain" bitfld.long 0x8 31. "ienexdcld3d,Comparator error of DCLS group dbs3 interrupt enable" "0,1" bitfld.long 0x8 30. "ienpxpyrif3d,Parity error for PHY-Register I F (rdata) for memory channel3" "0,1" newline bitfld.long 0x8 25. "ienoddvawr3d,OrderID error of isbus async write ch. interrupt enable for memory channel 3" "0,1" bitfld.long 0x8 24. "ienoddvacq3d,OrderID error of isbus async address (command queue) ch. interrupt enable for memory channel 3" "0,1" newline bitfld.long 0x8 23. "iendxdvawr3d,EDC error of isbus async write ch. interrupt enable for memory channel 3" "0,1" bitfld.long 0x8 22. "iendxdvacq3d,EDC error of isbus async address (command queue) ch. interrupt enable for memory channel 3" "0,1" newline bitfld.long 0x8 21. "ienoddvphy3d,OrderID error in DFI DDR PHY interrupt enable bit for memory channel 3" "0,1" bitfld.long 0x8 20. "ienoddvdbs3d,OrderID error in DFI DBSC interrupt enable bit for memory channel 3" "0,1" newline bitfld.long 0x8 19. "iendxdvphy3d,EDC error in DFI DDR PHY interrupt enable bit for memory channel 3" "0,1" bitfld.long 0x8 18. "iendxdvdbs3d,EDC error in DFI DBSC interrupt enable bit for memory channel 3" "0,1" newline bitfld.long 0x8 17. "ienepdvphy3d,POST error in ddrf interrupt enable bit for memory channel 3" "0,1" bitfld.long 0x8 16. "ienepdvdbs3d,POST error in DBSC domain interrupt enable bit for memory channel 3" "0,1" newline bitfld.long 0x8 15. "ienexdcld2d,Comparator error of DCLS group dbs2 interrupt enable" "0,1" bitfld.long 0x8 14. "ienpxpyrif2d,Parity error for PHY-Register I F (rdata) for memory channel2" "0,1" newline bitfld.long 0x8 9. "ienoddvawr2d,OrderID error of isbus async write ch. interrupt enable for memory channel 2" "0,1" bitfld.long 0x8 8. "ienoddvacq2d,OrderID error of isbus async address (command queue) ch. interrupt enable for memory channel 2" "0,1" newline bitfld.long 0x8 7. "iendxdvawr2d,EDC error of isbus async write ch. interrupt enable for memory channel 2" "0,1" bitfld.long 0x8 6. "iendxdvacq2d,EDC error of isbus async address (command queue) ch. interrupt enable for memory channel 2" "0,1" newline bitfld.long 0x8 5. "ienoddvphy2d,OrderID error in DFI DDR PHY interrupt enable bit for memory channel 2" "0,1" bitfld.long 0x8 4. "ienoddvdbs2d,OrderID error in DFI DBSC interrupt enable bit for memory channel 2" "0,1" newline bitfld.long 0x8 3. "iendxdvphy2d,EDC error in DFI DDR PHY interrupt enable bit for memory channel 2" "0,1" bitfld.long 0x8 2. "iendxdvdbs2d,EDC error in DFI DBSC interrupt enable bit for memory channel 2" "0,1" newline bitfld.long 0x8 1. "ienepdvphy2d,POST error in ddrf interrupt enable bit for memory channel 2" "0,1" bitfld.long 0x8 0. "ienepdvdbs2d,POST error in DBSC domain interrupt enable bit for memory channel 2" "0,1" line.long 0xC "DBFSINTENB03D,Fusa Interrupt Enable Register 3 for DFI Domain" hexmask.long.word 0xC 0.--15. 1. "ienxxasynsbd,Async sideband errors interrupt enable in dbs domain" group.long 0x7900++0xF line.long 0x0 "DBFSINJECT00D,Fusa Injection Mode Register 0 for DFI Domain" bitfld.long 0x0 6. "ijtodaswxd,OrderID error in AXI64 Wch clk_axi side interrupt injection mode" "0,1" bitfld.long 0x0 5. "ijtodasawd,OrderID error in AXI64 AWch clk_axi side interrupt injection mode" "0,1" newline bitfld.long 0x0 4. "ijtodasard,OrderID error in AXI64 ARch clk_axi side interrupt injection mode" "0,1" bitfld.long 0x0 2. "ijtdxaswxd,EDC error in AXSM W Ch clk_axi domain interrupt injection mode" "0,1" newline bitfld.long 0x0 1. "ijtdxasawd,EDC error in AXSM AW Ch clk_axi domain interrupt injection mode" "0,1" bitfld.long 0x0 0. "ijtdxasard,EDC error in AXSM AR Ch clk_axi domain interrupt injection mode" "0,1" line.long 0x4 "DBFSINJECT01D,Fusa Injection Mode Register 1 for DFI Domain" bitfld.long 0x4 31. "ijtexdcld1d,Comparator error of DCLS group dbs1 interrupt injection mode" "0,1" bitfld.long 0x4 30. "ijtpxpyrif1d,Parity error for PHY-Register I F (rdata) for memory channel 1" "0,1" newline bitfld.long 0x4 25. "ijtoddvawr1d,OrderID error of isbus async write ch. interrupt injection mode for memory channel 1" "0,1" bitfld.long 0x4 24. "ijtoddvacq1d,OrderID error of isbus async address (command queue) ch. interrupt injection mode for memory channel 1" "0,1" newline bitfld.long 0x4 23. "ijtdxdvawr1d,EDC error of isbus async write ch. interrupt injection mode for memory channel 1" "0,1" bitfld.long 0x4 22. "ijtdxdvacq1d,EDC error of isbus async address (command queue) ch. interrupt injection mode for memory channel 1" "0,1" newline bitfld.long 0x4 21. "ijtoddvphy1d,OrderID error in DFI DDR PHY interrupt injection for memory channel 1" "0,1" bitfld.long 0x4 20. "ijtoddvdbs1d,OrderID error in DFI DBSC interrupt injection for memory channel 1" "0,1" newline bitfld.long 0x4 19. "ijtdxdvphy1d,EDC error in DFI DDR PHY interrupt injection for memory channel 1" "0,1" bitfld.long 0x4 18. "ijtdxdvdbs1d,EDC error in DFI DBSC interrupt injection for memory channel 1" "0,1" newline bitfld.long 0x4 17. "ijtepdvphy1d,POST error in ddrf interrupt injection for memory channel 1" "0,1" bitfld.long 0x4 16. "ijtepdvdbs1d,POST error in DBSC domain interrupt injection for memory channel 1" "0,1" newline bitfld.long 0x4 15. "ijtexdcld0d,Comparator error of DCLS group dbs0 interrupt injection mode" "0,1" bitfld.long 0x4 14. "ijtpxpyrif0d,Parity error for PHY-Register I F (rdata) for memory channel 0" "0,1" newline bitfld.long 0x4 9. "ijtoddvawr0d,OrderID error of isbus async write ch. interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x4 8. "ijtoddvacq0d,OrderID error of isbus async address (command queue) ch. interrupt injection mode for memory channel 0" "0,1" newline bitfld.long 0x4 7. "ijtdxdvawr0d,EDC error of isbus async write ch. interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x4 6. "ijtdxdvacq0d,EDC error of isbus async address (command queue) ch. interrupt injection mode for memory channel 0" "0,1" newline bitfld.long 0x4 5. "ijtoddvphy0d,OrderID error in DFI DDR PHY interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x4 4. "ijtoddvdbs0d,OrderID error in DFI DBSC interrupt injection mode for memory channel 0" "0,1" newline bitfld.long 0x4 3. "ijtdxdvphy0d,EDC error in DFI DDR PHY interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x4 2. "ijtdxdvdbs0d,EDC error in DFI DBSC interrupt injection mode for memory channel 0" "0,1" newline bitfld.long 0x4 1. "ijtepdvphy0d,POST error in ddrf interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x4 0. "ijtepdvdbs0d,POST error in DBSC domain interrupt injection mode for memory channel 0" "0,1" line.long 0x8 "DBFSINJECT02D,Fusa Injection Mode Register 2 for DFI Domain" bitfld.long 0x8 31. "ijtexdcld3d,Comparator error of DCLS group dbs3 interrupt injection mode" "0,1" bitfld.long 0x8 30. "ijtpxpyrif3d,Parity error for PHY-Register I F (rdata) for memory channel3" "0,1" newline bitfld.long 0x8 25. "ijtoddvawr3d,OrderID error of isbus async write ch. interrupt injection mode for memory channel 3" "0,1" bitfld.long 0x8 24. "ijtoddvacq3d,OrderID error of isbus async address (command queue) ch. interrupt injection mode for memory channel 3" "0,1" newline bitfld.long 0x8 23. "ijtdxdvawr3d,EDC error of isbus async write ch. interrupt injection mode for memory channel 3" "0,1" bitfld.long 0x8 22. "ijtdxdvacq3d,EDC error of isbus async address (command queue) ch. interrupt injection mode for memory channel 3" "0,1" newline bitfld.long 0x8 21. "ijtoddvphy3d,OrderID error in DFI DDR PHY interrupt injection for memory channel 3" "0,1" bitfld.long 0x8 20. "ijtoddvdbs3d,OrderID error in DFI DBSC interrupt injection for memory channel 3" "0,1" newline bitfld.long 0x8 19. "ijtdxdvphy3d,EDC error in DFI DDR PHY interrupt injection for memory channel 3" "0,1" bitfld.long 0x8 18. "ijtdxdvdbs3d,EDC error in DFI DBSC interrupt injection for memory channel 3" "0,1" newline bitfld.long 0x8 17. "ijtepdvphy3d,POST error in ddrf interrupt injection for memory channel 3" "0,1" bitfld.long 0x8 16. "ijtepdvdbs3d,POST error in DBSC domain interrupt injection for memory channel 3" "0,1" newline bitfld.long 0x8 15. "ijtexdcld2d,Comparator error of DCLS group dbs2 interrupt injection mode" "0,1" bitfld.long 0x8 14. "ijtpxpyrif2d,Parity error for PHY-Register I F (rdata) for memory channel 2" "0,1" newline bitfld.long 0x8 9. "ijtoddvawr2d,OrderID error of isbus async write ch. interrupt injection mode for memory channel 2" "0,1" bitfld.long 0x8 8. "ijtoddvacq2d,OrderID error of isbus async address (command queue) ch. interrupt injection mode for memory channel 2" "0,1" newline bitfld.long 0x8 7. "ijtdxdvawr2d,EDC error of isbus async write ch. interrupt injection mode for memory channel 2" "0,1" bitfld.long 0x8 6. "ijtdxdvacq2d,EDC error of isbus async address (command queue) ch. interrupt injection mode for memory channel 2" "0,1" newline bitfld.long 0x8 5. "ijtoddvphy2d,OrderID error in DFI DDR PHY interrupt injection for memory channel 2" "0,1" bitfld.long 0x8 4. "ijtoddvdbs2d,OrderID error in DFI DBSC interrupt injection for memory channel 2" "0,1" newline bitfld.long 0x8 3. "ijtdxdvphy2d,EDC error in DFI DDR PHY interrupt injection for memory channel 2" "0,1" bitfld.long 0x8 2. "ijtdxdvdbs2d,EDC error in DFI DBSC interrupt injection for memory channel 2" "0,1" newline bitfld.long 0x8 1. "ijtepdvphy2d,POST error in ddrf interrupt injection for memory channel 2" "0,1" bitfld.long 0x8 0. "ijtepdvdbs2d,POST error in DBSC domain interrupt injection for memory channel 2" "0,1" line.long 0xC "DBFSINJECT03D,Fusa Injection Mode Register 3 for DFI Domain" hexmask.long.word 0xC 0.--15. 1. "ijtxxasynsbd,Async sideband errors interrupt injection mode in dbs domain" group.long 0x7A00++0x23 line.long 0x0 "DBFSINTCNT00D,Fusa Interrupt Counter Register 0 for DFI Domain" hexmask.long.byte 0x0 16.--23. 1. "cntdxaswxd,EDC error in AXSM W Ch clk_axi domain interrupt counter" hexmask.long.byte 0x0 8.--15. 1. "cntdxasawd,EDC error in AXSM AW Ch clk_axi domain interrupt counter" newline hexmask.long.byte 0x0 0.--7. 1. "cntdxasard,EDC error in AXSM AR Ch clk_axi domain interrupt counter" line.long 0x4 "DBFSINTCNT01D,Fusa Interrupt Counter Register 1 for DFI Domain" hexmask.long.byte 0x4 24.--31. 1. "cntdxdvawr0d,EDC error of isbus async write ch. interrupt counter for memory channel 0" hexmask.long.byte 0x4 16.--23. 1. "cntdxdvacq0d,EDC error of isbus async address (command queue) ch. interrupt counter for memory channel 0" newline hexmask.long.byte 0x4 8.--15. 1. "cntdxdvphy0d,EDC error in DFI DDR PHY interrupt counter for memory channel 0" hexmask.long.byte 0x4 0.--7. 1. "cntdxdvdbs0d,EDC error in DFI DBSC interrupt counter for memory channel 0" line.long 0x8 "DBFSINTCNT02D,Fusa Interrupt Counter Register 2 for DFI Domain" hexmask.long.byte 0x8 0.--7. 1. "cntpxpyrif0d,Parity error interrupt counter for PHY-Register I F (rdata) for memory channel0" line.long 0xC "DBFSINTCNT03D,Fusa Interrupt Counter Register 3 for DFI Domain" hexmask.long.byte 0xC 24.--31. 1. "cntdxdvawr1d,EDC error of isbus async write ch. interrupt counter for memory channel 1" hexmask.long.byte 0xC 16.--23. 1. "cntdxdvacq1d,EDC error of isbus async address (command queue) ch. interrupt counter for memory channel 1" newline hexmask.long.byte 0xC 8.--15. 1. "cntdxdvphy1d,EDC error in DFI DDR PHY interrupt counter for memory channel 1" hexmask.long.byte 0xC 0.--7. 1. "cntdxdvdbs1d,EDC error in DFI DBSC interrupt counter for memory channel 1" line.long 0x10 "DBFSINTCNT04D,Fusa Interrupt Counter Register 4 for DFI Domain" hexmask.long.byte 0x10 0.--7. 1. "cntpxpyrif1d,Parity error interrupt counter for PHY-Register I F (rdata) for memory channel1" line.long 0x14 "DBFSINTCNT05D,Fusa Interrupt Counter Register 5 for DFI Domain" hexmask.long.byte 0x14 24.--31. 1. "cntdxdvawr2d,EDC error of isbus async write ch. interrupt counter for memory channel 2" hexmask.long.byte 0x14 16.--23. 1. "cntdxdvacq2d,EDC error of isbus async address (command queue) ch. interrupt counter for memory channel 2" newline hexmask.long.byte 0x14 8.--15. 1. "cntdxdvphy2d,EDC error in DFI DDR PHY interrupt counter for memory channel 2" hexmask.long.byte 0x14 0.--7. 1. "cntdxdvdbs2d,EDC error in DFI DBSC interrupt counter for memory channel 2" line.long 0x18 "DBFSINTCNT06D,Fusa Interrupt Counter Register 6 for DFI Domain" hexmask.long.byte 0x18 0.--7. 1. "cntpxpyrif2d,Parity error interrupt counter for PHY-Register I F (rdata) for memory channel2" line.long 0x1C "DBFSINTCNT07D,Fusa Interrupt Counter Register 7 for DFI Domain" hexmask.long.byte 0x1C 24.--31. 1. "cntdxdvawr3d,EDC error of isbus async write ch. interrupt counter for memory channel 3" hexmask.long.byte 0x1C 16.--23. 1. "cntdxdvacq3d,EDC error of isbus async address (command queue) ch. interrupt counter for memory channel 3" newline hexmask.long.byte 0x1C 8.--15. 1. "cntdxdvphy3d,EDC error in DFI DDR PHY interrupt counter for memory channel 3" hexmask.long.byte 0x1C 0.--7. 1. "cntdxdvdbs3d,EDC error in DFI DBSC interrupt counter for memory channel 3" line.long 0x20 "DBFSINTCNT08D,Fusa Interrupt Counter Register 8 for DFI Domain" hexmask.long.byte 0x20 0.--7. 1. "cntpxpyrif3d,Parity error interrupt counter for PHY-Register I F (rdata) for memory channel3" group.long 0x7C00++0x3 line.long 0x0 "DBFSCONFDBS0,Fusa Configuration Register 0 for DFI Domain" bitfld.long 0x0 0. "protendbs,Enable of Protection between dbsc and DDR PHY. When this bit is set to 1 starts checking EDC and OrderID counter." "0,1" group.long 0x7C80++0x3 line.long 0x0 "DBFSCTRLDBS0,Fusa Control Register 0 for DFI Domain" bitfld.long 0x0 0. "postendbs,Start POST for asynchronous bridge in ddrf. When this bit is asserted this bit is cleared to 0 at next cycle autmatically." "0,1" tree.end tree "DBSC_1" base ad:0xE6790000 group.long 0x4++0x7 line.long 0x0 "DBSYSCONF1,DBSC4 System Configuration Register1 for DFI Domain" bitfld.long 0x0 0.--1. "freqratio,Frequency Ratio Setting" "?,1: 4,?,?" line.long 0x4 "DBSYSCONF1A,DBSC4 System Configuration Register 1 for AXI Domain" bitfld.long 0x4 0.--1. "freqratioa,Frequency Ratio Setting" "?,1: 4,?,?" group.long 0x10++0x3 line.long 0x0 "DBPHYCONF0,PHY Type Configuration Register" bitfld.long 0x0 0.--1. "phytype,PHY Type" "?,1: DFI,?,?" group.long 0x20++0x7 line.long 0x0 "DBMEMKIND,Memory Type Register for DFI Domain" hexmask.long.byte 0x0 0.--3. 1. "ddcg,SDRAM Type" line.long 0x4 "DBMEMKINDA,Memory Type Register for AXI Domain" hexmask.long.byte 0x4 0.--3. 1. "ddcga,SDRAM Type" group.long 0x30++0x7 line.long 0x0 "DBMEMCONF00,DBMEMCONF00 is used to set the memory configuration to use for rank 0 on channel 0." bitfld.long 0x0 30.--31. "dens00,Channel 0 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw00,Channel 0 Rank 0 Row Address Bit width" newline bitfld.long 0x0 16.--18. "awbk00,Channel 0 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl00,Channel 0 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw00,Channel 0 Rank 0 Memory External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF01,DBMEMCONF01 is used to set the memory configuration to use for rank 1 on channel 0." bitfld.long 0x4 30.--31. "dens01,Channel 0 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw01,Channel 0 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk01,Channel 0 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl01,Channel 0 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw01,Channel 0 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x40++0x7 line.long 0x0 "DBMEMCONF10,DBMEMCONF10 is used to set the memory configuration to use for rank 0 on channel 1." bitfld.long 0x0 30.--31. "dens10,Channel 1 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw10,Channel 1 Rank 0 Row Address Bit Width" newline bitfld.long 0x0 16.--18. "awbk10,Channel 1 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl10,Channel 1 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw10,Channel 1 Rank 0 External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF11,DBMEMCONF11 is used to set the memory configuration to use for rank 1 on channel 1." bitfld.long 0x4 30.--31. "dens11,Channel 1 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw11,Channel 1 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk11,Channel 1 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl11,Channel 1 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw11,Channel 1 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x50++0x7 line.long 0x0 "DBMEMCONF20,DBMEMCONF20 is used to set the memory configuration to use for rank 0 on channel 2." bitfld.long 0x0 30.--31. "dens20,Channel 2 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw20,Channel 2 Rank 0 Row Address Bit Width" newline bitfld.long 0x0 16.--18. "awbk20,Channel 2 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl20,Channel 2 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw20,Channel 2 Rank 0 External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF21,DBMEMCONF21 is used to set the memory configuration to use for rank 1 on channel 2." bitfld.long 0x4 30.--31. "dens21,Channel 2 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw21,Channel 2 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk21,Channel 2 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl21,Channel 2 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw21,Channel 2 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x60++0x7 line.long 0x0 "DBMEMCONF30,DBMEMCONF30 is used to set the memory configuration to use for rank 0 on channel 3." bitfld.long 0x0 30.--31. "dens30,Channel 3 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw30,Channel 3 Rank 0 Row Address Bit Width" newline bitfld.long 0x0 16.--18. "awbk30,Channel 3 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl30,Channel 3 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw30,Channel 3 Rank 0 External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF31,DBMEMCONF31 is used to set the memory configuration to use for rank 1 on channel 3." bitfld.long 0x4 30.--31. "dens31,Channel 3 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw31,Channel 3 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk31,Channel 3 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl31,Channel 3 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw31,Channel 3 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x70++0x7 line.long 0x0 "DBMEMCONF00A,DBMEMCONF00 is used to set the memory configuration to use for rank 0 on channel 0." bitfld.long 0x0 30.--31. "dens00a,Channel 0 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw00a,Channel 0 Rank 0 Row Address Bit width" newline bitfld.long 0x0 16.--18. "awbk00a,Channel 0 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl00a,Channel 0 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw00a,Channel 0 Rank 0 Memory External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF01A,DBMEMCONF01 is used to set the memory configuration to use for rank 1 on channel 0." bitfld.long 0x4 30.--31. "dens01a,Channel 0 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw01a,Channel 0 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk01a,Channel 0 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl01a,Channel 0 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw01a,Channel 0 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x80++0x7 line.long 0x0 "DBMEMCONF10A,DBMEMCONF10 is used to set the memory configuration to use for rank 0 on channel 1." bitfld.long 0x0 30.--31. "dens10a,Channel 1 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw10a,Channel 1 Rank 0 Row Address Bit width" newline bitfld.long 0x0 16.--18. "awbk10a,Channel 1 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl10a,Channel 1 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw10a,Channel 1 Rank 0 Memory External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF11A,DBMEMCONF11 is used to set the memory configuration to use for rank 1 on channel 1." bitfld.long 0x4 30.--31. "dens11a,Channel 1 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw11a,Channel 1 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk11a,Channel 1 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl11a,Channel 1 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw11a,Channel 1 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0x90++0x7 line.long 0x0 "DBMEMCONF20A,DBMEMCONF20 is used to set the memory configuration to use for rank 0 on channel 2." bitfld.long 0x0 30.--31. "dens20a,Channel 2 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw20a,Channel 2 Rank 0 Row Address Bit width" newline bitfld.long 0x0 16.--18. "awbk20a,Channel 2 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl20a,Channel 2 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw20a,Channel 2 Rank 0 Memory External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF21A,DBMEMCONF21 is used to set the memory configuration to use for rank 1 on channel 2." bitfld.long 0x4 30.--31. "dens21a,Channel 2 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw21a,Channel 2 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk21a,Channel 2 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl21a,Channel 2 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw21a,Channel 2 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0xA0++0x7 line.long 0x0 "DBMEMCONF30A,DBMEMCONF30 is used to set the memory configuration to use for rank 0 on channel 3." bitfld.long 0x0 30.--31. "dens30a,Channel 3 Rank 0 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x0 24.--28. 1. "awrw30a,Channel 3 Rank 0 Row Address Bit width" newline bitfld.long 0x0 16.--18. "awbk30a,Channel 3 Rank 0 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "awcl30a,Channel 3 Rank 0 Column Address Bit Width" newline bitfld.long 0x0 0.--1. "dw30a,Channel 3 Rank 0 Memory External Data Bus Width" "?,1: 16 bits,?,?" line.long 0x4 "DBMEMCONF31A,DBMEMCONF31 is used to set the memory configuration to use for rank 1 on channel 3." bitfld.long 0x4 30.--31. "dens31a,Channel 3 Rank 1 Memory Density Type" "0: 2^n type,1: 2^n x 3 type,?,?" hexmask.long.byte 0x4 24.--28. 1. "awrw31a,Channel 3 Rank 1 Row Address Bit Width" newline bitfld.long 0x4 16.--18. "awbk31a,Channel 3 Rank 1 Number of Banks" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--11. 1. "awcl31a,Channel 3 Rank 1 Column Address Bit Width" newline bitfld.long 0x4 0.--1. "dw31a,Channel 3 Rank 1 External Data Bus Width" "?,1: 16 bits,?,?" group.long 0xC0++0x3 line.long 0x0 "DBCONFMON0A,Configuration Monitor" hexmask.long 0x0 0.--31. 1. "dbscrma,Value of scramble seed" group.long 0x100++0x3 line.long 0x0 "DBSYSCNT0,DBSC System Register 0 for DFI Domain" hexmask.long.word 0x0 0.--15. 1. "reglock,Register Write Enable Pattern" group.long 0x108++0x3 line.long 0x0 "DBSYSCNT0A,DBSC System Register 0 for AXI Domain" hexmask.long.word 0x0 0.--15. 1. "reglocka,Register Write Enable Pattern" group.long 0x200++0xB line.long 0x0 "DBACEN,SDRAM Access Enable Register" bitfld.long 0x0 0. "accen,SDRAM Access Enable" "0: Disables access to the SDRAM,1: Enables access to the SDRAM" line.long 0x4 "DBRFEN,Auto-Refresh Enable Register" bitfld.long 0x4 0. "arfen,Auto-Refresh Enable" "0: Stops the auto-refresh function,1: Starts the auto-refresh function" line.long 0x8 "DBCMD,The manual command-issuing register (DBCMD) is used to issue the required commands for the sequence of initializing the SDRAM and of transitions to and from the self-refresh mode. The command corresponding to the OPC bits is issued once as a result.." hexmask.long.byte 0x8 24.--31. 1. "opc,Operation Code" hexmask.long.byte 0x8 20.--23. 1. "ch,Channel Specification" newline bitfld.long 0x8 16.--18. "rank,Rank Specification" "0: Rank 0,1: Rank 1,?,?,?,?,?,?" hexmask.long.word 0x8 0.--15. 1. "arg,Argument" group.long 0x210++0x3 line.long 0x0 "DBWAIT,Operation Completion Waiting Register" bitfld.long 0x0 0. "busy,Operation Completion Waiting" "0: The command specified by using the DBCMD..,1: The command specified by using the DBCMD.." group.long 0x300++0x4B line.long 0x0 "DBTR0,SDRAM Timing Register 0" hexmask.long.byte 0x0 0.--7. 1. "cl,CL RL (CAS Latency Read Latency)" line.long 0x4 "DBTR1,SDRAM Timing Register 1" hexmask.long.byte 0x4 0.--7. 1. "cwl,CWL WL (CAS Write Latency Write Latency)" line.long 0x8 "DBTR2,SDRAM Timing Register 2" hexmask.long.byte 0x8 0.--7. 1. "al,AL (AditiveLatency)" line.long 0xC "DBTR3,SDRAM Timing Register 3" hexmask.long.byte 0xC 0.--7. 1. "trcd,tRCD (ACT to internal read or write delay time RAS-to-CAS delay)" line.long 0x10 "DBTR4,SDRAM Timing Register 4" hexmask.long.byte 0x10 16.--23. 1. "trpa,tRP tRPab (PRE command period Row precharge time (all banks))" hexmask.long.byte 0x10 0.--7. 1. "trp,tRP tRPpb (PRE command period Row precharge time (single bank))" line.long 0x14 "DBTR5,SDRAM Timing Register 5" hexmask.long.byte 0x14 0.--7. 1. "trc,tRC (ACT to ACT or REF command period ACTIVATE-to-ACTIVATE command period (same bank))" line.long 0x18 "DBTR6,SDRAM Timing Register 6" hexmask.long.byte 0x18 0.--7. 1. "tras,tRAS (ACT to PRE command period Row active time)" line.long 0x1C "DBTR7,SDRAM Timing Register 7" hexmask.long.byte 0x1C 16.--23. 1. "trrd_s,tRRD (ACTIVE to ACTIVE command period Active bank-A to active bank-B)" hexmask.long.byte 0x1C 0.--7. 1. "trrd,tRRD (ACTIVE to ACTIVE command period Active bank-A to active bank-B)" line.long 0x20 "DBTR8,SDRAM Timing Register 8" hexmask.long.byte 0x20 0.--7. 1. "tfaw,tFAW (Four activate window Four-bank ACTIVATE window)" line.long 0x24 "DBTR9,SDRAM Timing Register 9" hexmask.long.byte 0x24 0.--7. 1. "trdpr,tRTP nRTP (Internal READ Command to PRECHARGE Command delay Internal READ to PRECHARGE command delay)" line.long 0x28 "DBTR10,SDRAM Timing Register 10" hexmask.long.byte 0x28 0.--7. 1. "twr,WR nWR (WRITE recovery time)" line.long 0x2C "DBTR11,SDRAM Timing Register 11" hexmask.long.byte 0x2C 0.--7. 1. "trdwr,Read-to-Write Interval" line.long 0x30 "DBTR12,SDRAM Timing Register 12" hexmask.long.byte 0x30 16.--23. 1. "twrrd_s,Write-to-Read interval" hexmask.long.byte 0x30 0.--7. 1. "twrrd,Write-to-Read interval" line.long 0x34 "DBTR13,SDRAM Timing Register 13" hexmask.long.word 0x34 0.--15. 1. "trfc,tRFC tRFCab (REF command to ACT or REF command time Refresh Cycle Time (All Banks))" line.long 0x38 "DBTR14,SDRAM Timing Register 14" hexmask.long.byte 0x38 16.--23. 1. "tckehdll,tXPDLL (Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL)" hexmask.long.byte 0x38 0.--7. 1. "tckeh,tXP (Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit power- down to next valid command delay)" line.long 0x3C "DBTR15,SDRAM Timing Register 15" hexmask.long.byte 0x3C 16.--23. 1. "tckesr,tCKESR tSR (Minimum CKE low width for Self Refresh entry to exit timing Minimum Self-Refresh Time (Entry to Exit))" hexmask.long.byte 0x3C 0.--7. 1. "tckel,tCKE (CKE minimum pulse width)" line.long 0x40 "DBTR16,DBTR16 is used to set timing parameters for the SDRAM." hexmask.long.byte 0x40 24.--31. 1. "dqienltncy,dqienltncy Setting" hexmask.long.byte 0x40 16.--23. 1. "dql,dqltncy Setting" newline hexmask.long.byte 0x40 8.--15. 1. "dqenltncy,dqenltncy Setting" hexmask.long.byte 0x40 0.--7. 1. "wdql,wdqltncy Setting" line.long 0x44 "DBTR17,DBTR17 is used to set timing parameters for the SDRAM." hexmask.long.byte 0x44 24.--31. 1. "tmodrd,tMRR (MODE REGISTER READ command period)" hexmask.long.byte 0x44 16.--23. 1. "tmod,tMOD tMRD (Mode Register Set command update delay Mode register set command delay)" line.long 0x48 "DBTR18,SDRAM Timing Register 18" bitfld.long 0x48 24.--26. "rodtl,ODT Assert Period Setting in Reading" "0: BL,1: BL,?,?,?,?,?,?" bitfld.long 0x48 16.--18. "rodta,ODT Assert Start Timing Setting in Reading" "0: Simultaneous with the read command,1: 1 cycle after the read command,?,?,?,?,?,?" newline bitfld.long 0x48 8.--10. "wodtl,ODT Assert Period Setting in Writing" "0: BL,1: BL,?,?,?,?,?,?" bitfld.long 0x48 0.--2. "wodta,ODT Assert Start Timing Setting in Writing" "0: Simultaneous with the write command,1: 1 cycle after the write command,?,?,?,?,?,?" group.long 0x350++0x17 line.long 0x0 "DBTR20,DBTR20 is used to set timing parameters for the SDRAM." hexmask.long.word 0x0 16.--31. 1. "txsdll,tXSDLL (Exit Self Refresh to commands requiring a locked DLL)" hexmask.long.word 0x0 0.--15. 1. "txs,tXS tXSR (Exit Self Refresh to commands not requiring a locked DLL SELF REFRESH exit to next valid command delay)" line.long 0x4 "DBTR21,SDRAM Timing Register 21" hexmask.long.byte 0x4 16.--23. 1. "tccd_s,tCCD (CAS_N to CAS_N command delay CAS-to-CAS delay)" hexmask.long.byte 0x4 0.--7. 1. "tccd,tCCD (CAS_N to CAS_N command delay CAS-to-CAS delay)" line.long 0x8 "DBTR22,DBTR22 is used to set timing parameters for the SDRAM." hexmask.long.word 0x8 16.--31. 1. "tzqcal,tZQCAL (ZQ calibration time)" hexmask.long.byte 0x8 0.--7. 1. "tzqlat,tZQLAT (ZQCAL latch quiet time)" line.long 0xC "DBTR23,SDRAM Timing Register 23" bitfld.long 0xC 0.--1. "rrspc,RD to RD Interval Limitation" "0: No limitation,1: (TCCD_S + 1,?,?" line.long 0x10 "DBTR24,DBTR24 is used to set a timing parameter for the DFI." hexmask.long.byte 0x10 24.--31. 1. "rdcsgap,dfi_rddata_cs gap" hexmask.long.byte 0x10 16.--23. 1. "rdcslat,dfi_rddata_cs latency" newline hexmask.long.byte 0x10 8.--15. 1. "wrcsgap,dfi_wrdata_cs gap" hexmask.long.byte 0x10 0.--7. 1. "wrcslat,dfi_wrdata_cs latency" line.long 0x14 "DBTR25,SDRAM Timing Register 25" hexmask.long.byte 0x14 16.--23. 1. "twdqlvldis,DFI twdqlvl disable" hexmask.long.byte 0x14 0.--7. 1. "twdqlvlen,DFI twdqlvl enable." group.long 0x400++0x3 line.long 0x0 "DBBL,SDRAM Operation Setting Register for DFI Domain" bitfld.long 0x0 0.--1. "bl,Burst Length" "0: Fixed to 8,?,?,?" rgroup.long 0x404++0x3 line.long 0x0 "DBBLA,SDRAM Operation Setting Register for AXI Domain" bitfld.long 0x0 0.--1. "bla,Burst Length" "0: Fixed to 8,?,?,?" group.long 0x414++0x7 line.long 0x0 "DBRFCNF1,DBRFCNF1 is used to set the timing for refreshing of the SDRAM." hexmask.long.word 0x0 16.--31. 1. "refpmax,Maximum Pulling-in Number of Refresh Commands Setting" hexmask.long.word 0x0 0.--15. 1. "refint,tREFI (Average periodic refresh interval Average Refresh Interval)" line.long 0x4 "DBRFCNF2,Refresh Configuration Register 2" hexmask.long.byte 0x4 16.--19. 1. "refpmin,Minimum Pulling-in Number of Refresh Commands Setting" bitfld.long 0x4 0.--1. "refints,Average Refresh Interval Adjustment" "0: Average interval is REFINT,1: Average interval is 1,?,?" group.long 0x424++0x3 line.long 0x0 "DBCALCNF,SDRAM Calibration Configuration Register" bitfld.long 0x0 24. "calen,SDRAM Calibration Enable" "0: SDRAM calibration is disabled,1: SDRAM calibration is enabled" hexmask.long.word 0x0 0.--15. 1. "calint,SDRAM Calibration Frequency" group.long 0x438++0xF line.long 0x0 "DBRNK2,Multirank Operation Setting Register 2" hexmask.long.byte 0x0 12.--15. 1. "rkrr3,Additional Restriction on READ-READ Interval between Different Ranks for Channel 3." hexmask.long.byte 0x0 8.--11. 1. "rkrr2,Additional Restriction on READ-READ Interval between Different Ranks for Channel 2." newline hexmask.long.byte 0x0 4.--7. 1. "rkrr1,Additional Restriction on READ-READ Interval between Different Ranks for Channel 1." hexmask.long.byte 0x0 0.--3. 1. "rkrr0,Additional Restriction on READ-READ Interval between Different Ranks for Channel 0." line.long 0x4 "DBRNK3,Multirank Operation Setting Register 3" hexmask.long.byte 0x4 12.--15. 1. "rkrw3,Additional Restriction on READ-WRITE Interval between Different Ranks for Channel 3." hexmask.long.byte 0x4 8.--11. 1. "rkrw2,Additional Restriction on READ-WRITE Interval between Different Ranks for Channel 2." newline hexmask.long.byte 0x4 4.--7. 1. "rkrw1,Additional Restriction on READ-WRITE Interval between Different Ranks for Channel 1." hexmask.long.byte 0x4 0.--3. 1. "rkrw0,Additional Restriction on READ-WRITE Interval between Different Ranks for Channel 0." line.long 0x8 "DBRNK4,Multirank Operation Setting Register 4" hexmask.long.byte 0x8 12.--15. 1. "rkwr3,Additional Restriction on WRITE-READ Interval between Different Ranks for Channel 3." hexmask.long.byte 0x8 8.--11. 1. "rkwr2,Additional Restriction on WRITE-READ Interval between Different Ranks for Channel 2." newline hexmask.long.byte 0x8 4.--7. 1. "rkwr1,Additional Restriction on WRITE-READ Interval between Different Ranks for Channel 1." hexmask.long.byte 0x8 0.--3. 1. "rkwr0,Additional Restriction on WRITE-READ Interval between Different Ranks for Channel 0." line.long 0xC "DBRNK5,Multirank Operation Setting Register 5" hexmask.long.byte 0xC 12.--15. 1. "rkww3,Additional Restriction on WRITE-WRITE Interval between Different Ranks for Channel 3." hexmask.long.byte 0xC 8.--11. 1. "rkww2,Additional Restriction on WRITE-WRITE Interval between Different Ranks for Channel 2." newline hexmask.long.byte 0xC 4.--7. 1. "rkww1,Additional Restriction on WRITE-WRITE Interval between Different Ranks for Channel 1." hexmask.long.byte 0xC 0.--3. 1. "rkww0,Additional Restriction on WRITE-WRITE Interval between Different Ranks for Channel 0." group.long 0x460++0xF line.long 0x0 "DBODT0,ODT Output Setting Register 0" hexmask.long.byte 0x0 20.--23. 1. "rodtout01,ODT Output Level in Reading from Rank 1 for Channel 0 Setting" hexmask.long.byte 0x0 16.--19. 1. "rodtout00,ODT Output Level in Reading from Rank 0 for Channel 0 Setting" newline hexmask.long.byte 0x0 4.--7. 1. "wodtout01,ODT Output Level in Writing to Rank 1 for Channel 0 Setting" hexmask.long.byte 0x0 0.--3. 1. "wodtout00,ODT Output Level in Writing to Rank 0 for Channel 0 Setting" line.long 0x4 "DBODT1,ODT Output Setting Register 1" hexmask.long.byte 0x4 20.--23. 1. "rodtout11,ODT Output Level in Reading from Rank 1 for Channel 1 Setting" hexmask.long.byte 0x4 16.--19. 1. "rodtout10,ODT Output Level in Reading from Rank 0 for Channel 1 Setting" newline hexmask.long.byte 0x4 4.--7. 1. "wodtout11,ODT Output Level in Writing to Rank 1 for Channel 1 Setting" hexmask.long.byte 0x4 0.--3. 1. "wodtout10,ODT Output Level in Writing to Rank 0 for Channel 1 Setting" line.long 0x8 "DBODT2,ODT Output Setting Register 2" hexmask.long.byte 0x8 20.--23. 1. "rodtout21,ODT Output Level in Reading from Rank 1 for Channel 2 Setting" hexmask.long.byte 0x8 16.--19. 1. "rodtout20,ODT Output Level in Reading from Rank 0 for Channel 2 Setting" newline hexmask.long.byte 0x8 4.--7. 1. "wodtout21,ODT Output Level in Writing to Rank 1 for Channel 2 Setting" hexmask.long.byte 0x8 0.--3. 1. "wodtout20,ODT Output Level in Writing to Rank 0 for Channel 2 Setting" line.long 0xC "DBODT3,ODT Output Setting Register 3" hexmask.long.byte 0xC 20.--23. 1. "rodtout31,ODT Output Level in Reading from Rank 1 for Channel 3 Setting" hexmask.long.byte 0xC 16.--19. 1. "rodtout30,ODT Output Level in Reading from Rank 0 for Channel 3 Setting" newline hexmask.long.byte 0xC 4.--7. 1. "wodtout31,ODT Output Level in Writing to Rank 1 for Channel 3 Setting" hexmask.long.byte 0xC 0.--3. 1. "wodtout30,ODT Output Level in Writing to Rank 0 for Channel 3 Setting" group.long 0x518++0x3 line.long 0x0 "DBDBICNT,DBI Configuration Register" bitfld.long 0x0 1. "dbirden,Read DBI Setting" "0: Read DBI function is disabled,1: Read DBI function is enabled" bitfld.long 0x0 0. "dbiwren,Write DBI Setting" "0: Write DBI function is disabled,1: Write DBI function is enabled" group.long 0x520++0x7 line.long 0x0 "DBDFIPMSTRCNF,DFI PHY Master Control Register" bitfld.long 0x0 4.--5. "wtmode,DFI PHY Master receive mode" "0,1,2,3" bitfld.long 0x0 0. "pmstren,DFI PHY Master Control" "0,1" line.long 0x4 "DBDFIPMSTRSTAT,DBDFIPMSTRSTAT indicates whether or not CA training of each PHY unit has been completed. Any of the status bits becoming 1 indicates the completion of CA training of the corresponding PHY unit." group.long 0x52C++0x3 line.long 0x0 "DBDFICUPDCNF,DFI Control Update Configuration Register" hexmask.long.byte 0x0 24.--31. 1. "cupdreqmax,Maximum of Control Update Request Assert Period" hexmask.long.byte 0x0 16.--23. 1. "cupdreqmin,Minimum of Control Update Request Assert Period" newline bitfld.long 0x0 0. "cupden,Control Update Interface Enable." "0: Disable,1: Enable" group.long 0x600++0x7 line.long 0x0 "DBDFISTAT0,DFI Status Interface Input Register 0" bitfld.long 0x0 0. "dfiinitcompl0,DFIINITCOMPL for Channel 0" "0,1" line.long 0x4 "DBDFICNT0,DFI Status Interface Output Register 0" hexmask.long.byte 0x4 24.--28. 1. "dfifrequency0,FREQUENCY for Channel 0" hexmask.long.byte 0x4 16.--23. 1. "dfibytedis0,BYTEDIS for Channel 0" newline hexmask.long.byte 0x4 8.--11. 1. "dficlkdis0,CLKDIS for Channel 0" bitfld.long 0x4 4.--5. "dfifreqratio0,FREQRATIO for Channel 0" "?,1: 2,?,?" newline bitfld.long 0x4 0. "dfiinitstart0,INITSTART for Channel 0" "0,1" group.long 0x610++0x1B line.long 0x0 "DBPDCNT00,PHY Unit Control Register 00" hexmask.long 0x0 0.--31. 1. "cntreg00,DDR-PHY Control Signals 0 for Channel 0" line.long 0x4 "DBPDCNT01,PHY Unit Control Register 01" hexmask.long 0x4 0.--31. 1. "cntreg01,DDR-PHY Control Signals 1 for Channel 0" line.long 0x8 "DBPDCNT02,PHY Unit Control Register 02" hexmask.long 0x8 0.--31. 1. "cntreg02,DDR-PHY Control Signals 2 for Channel 0" line.long 0xC "DBPDCNT03,PHY Unit Control Register 03" hexmask.long 0xC 0.--31. 1. "cntreg03,DDR-PHY Control Signals 3 for Channel 0" line.long 0x10 "DBPDLK0,PHY Unit Lock Register 0" hexmask.long 0x10 0.--31. 1. "plock0,PHY Unit Access Lock Setting for Channel 0" line.long 0x14 "DBPDRGA0,PHY Unit Register Address 0" hexmask.long.word 0x14 0.--15. 1. "pra0,PHY Unit Register Address for Channel 0" line.long 0x18 "DBPDRGD0,PHY Unit Register Access 0" hexmask.long 0x18 0.--31. 1. "prd0,PHY Unit Registers Access for channel 0" rgroup.long 0x630++0x3 line.long 0x0 "DBPDSTAT00,PHY Status Register 00" hexmask.long.byte 0x0 8.--12. 1. "freqchgreqtype0,Frequency change request type for DDR-PHY Channel 0" bitfld.long 0x0 0. "freqchgreq0,Frequency change request for DDR-PHY Channel 0" "0,1" group.long 0x640++0x7 line.long 0x0 "DBDFISTAT1,DFI Status Interface Input Register 1" bitfld.long 0x0 0. "dfiinitcompl1,DFIINITCOMPL for Channel 1" "0,1" line.long 0x4 "DBDFICNT1,DFI Status Interface Output Register 1" hexmask.long.byte 0x4 24.--28. 1. "dfifrequency1,FREQUENCY for Channel 1" hexmask.long.byte 0x4 16.--23. 1. "dfibytedis1,BYTEDIS for Channel 1" newline hexmask.long.byte 0x4 8.--11. 1. "dficlkdis1,CLKDIS for Channel 1" bitfld.long 0x4 4.--5. "dfifreqratio1,FREQRATIO for Channel 1" "?,1: 2,?,?" newline bitfld.long 0x4 0. "dfiinitstart1,INITSTART for Channel 1" "0,1" group.long 0x650++0x1B line.long 0x0 "DBPDCNT10,PHY Unit Control Register 10" hexmask.long 0x0 0.--31. 1. "cntreg10,DDR-PHY Control Signals 0 for Channel 1" line.long 0x4 "DBPDCNT11,PHY Unit Control Register 11" hexmask.long 0x4 0.--31. 1. "cntreg11,DDR-PHY Control Signals 1 for Channel 1" line.long 0x8 "DBPDCNT12,PHY Unit Control Register 12" hexmask.long 0x8 0.--31. 1. "cntreg12,DDR-PHY Control Signals 2 for Channel 1" line.long 0xC "DBPDCNT13,PHY Unit Control Register 13" hexmask.long 0xC 0.--31. 1. "cntreg13,DDR-PHY Control Signals 3 for Channel 1" line.long 0x10 "DBPDLK1,PHY Unit Lock Register 1" hexmask.long 0x10 0.--31. 1. "plock1,PHY Unit Access Lock Setting for Channel 1" line.long 0x14 "DBPDRGA1,PHY Unit Register Address 1" hexmask.long.word 0x14 0.--15. 1. "pra1,PHY Unit Register Address for Channel 1" line.long 0x18 "DBPDRGD1,PHY Unit Register Access 1" hexmask.long 0x18 0.--31. 1. "prd1,PHY Unit Registers Access for channel 1" rgroup.long 0x670++0x3 line.long 0x0 "DBPDSTAT10,PHY Status Register 10" hexmask.long.byte 0x0 8.--12. 1. "freqchgreqtype1,Frequency change request type for DDR-PHY Channel 1" bitfld.long 0x0 0. "freqchgreq1,Frequency change request for DDR-PHY Channel 1" "0,1" group.long 0x680++0x7 line.long 0x0 "DBDFISTAT2,DFI Status Interface Input Register 2" bitfld.long 0x0 0. "dfiinitcompl2,DFIINITCOMPL for Channel 2" "0,1" line.long 0x4 "DBDFICNT2,DFI Status Interface Output Register 2" hexmask.long.byte 0x4 24.--28. 1. "dfifrequency2,FREQUENCY for Channel 2" hexmask.long.byte 0x4 16.--23. 1. "dfibytedis2,BYTEDIS for Channel 2" newline hexmask.long.byte 0x4 8.--11. 1. "dficlkdis2,CLKDIS for Channel 2" bitfld.long 0x4 4.--5. "dfifreqratio2,FREQRATIO for Channel 2" "?,1: 2,?,?" newline bitfld.long 0x4 0. "dfiinitstart2,INITSTART for Channel 2" "0,1" group.long 0x690++0x1B line.long 0x0 "DBPDCNT20,PHY Unit Control Register 20" hexmask.long 0x0 0.--31. 1. "cntreg20,DDR-PHY Control Signals 0 for Channel 2" line.long 0x4 "DBPDCNT21,PHY Unit Control Register 21" hexmask.long 0x4 0.--31. 1. "cntreg21,DDR-PHY Control Signals 1 for Channel 2" line.long 0x8 "DBPDCNT22,PHY Unit Control Register 22" hexmask.long 0x8 0.--31. 1. "cntreg22,DDR-PHY Control Signals 2 for Channel 2" line.long 0xC "DBPDCNT23,PHY Unit Control Register 23" hexmask.long 0xC 0.--31. 1. "cntreg23,DDR-PHY Control Signals 3 for Channel 2" line.long 0x10 "DBPDLK2,PHY Unit Lock Register 2" hexmask.long 0x10 0.--31. 1. "plock2,PHY Unit Access Lock Setting for Channel 2" line.long 0x14 "DBPDRGA2,PHY Unit Register Address 2" hexmask.long.word 0x14 0.--15. 1. "pra2,PHY Unit Register Address for Channel 2" line.long 0x18 "DBPDRGD2,PHY Unit Register Access 2" hexmask.long 0x18 0.--31. 1. "prd2,PHY Unit Registers Access for channel 2" rgroup.long 0x6B0++0x3 line.long 0x0 "DBPDSTAT20,PHY Status Register 20" hexmask.long.byte 0x0 8.--12. 1. "freqchgreqtype2,Frequency change request type for DDR-PHY Channel 2" bitfld.long 0x0 0. "freqchgreq2,Frequency change request for DDR-PHY Channel 2" "0,1" group.long 0x6C0++0x7 line.long 0x0 "DBDFISTAT3,DFI Status Interface Input Register 3" bitfld.long 0x0 0. "dfiinitcompl3,DFIINITCOMPL for Channel 3" "0,1" line.long 0x4 "DBDFICNT3,DFI Status Interface Output Register 3" hexmask.long.byte 0x4 24.--28. 1. "dfifrequency3,FREQUENCY for Channel 3" hexmask.long.byte 0x4 16.--23. 1. "dfibytedis3,BYTEDIS for Channel 3" newline hexmask.long.byte 0x4 8.--11. 1. "dficlkdis3,CLKDIS for Channel 3" bitfld.long 0x4 4.--5. "dfifreqratio3,FREQRATIO for Channel 3" "?,1: 2,?,?" newline bitfld.long 0x4 0. "dfiinitstart3,INITSTART for Channel 3" "0,1" group.long 0x6D0++0x1B line.long 0x0 "DBPDCNT30,PHY Unit Control Register 30" hexmask.long 0x0 0.--31. 1. "cntreg30,DDR-PHY Control Signals 0 for Channel 3" line.long 0x4 "DBPDCNT31,PHY Unit Control Register 31" hexmask.long 0x4 0.--31. 1. "cntreg31,DDR-PHY Control Signals 1 for Channel 3" line.long 0x8 "DBPDCNT32,PHY Unit Control Register 32" hexmask.long 0x8 0.--31. 1. "cntreg32,DDR-PHY Control Signals 2 for Channel 3" line.long 0xC "DBPDCNT33,PHY Unit Control Register 33" hexmask.long 0xC 0.--31. 1. "cntreg33,DDR-PHY Control Signals 3 for Channel 3" line.long 0x10 "DBPDLK3,PHY Unit Lock Register 3" hexmask.long 0x10 0.--31. 1. "plock3,PHY Unit Access Lock Setting for Channel 3" line.long 0x14 "DBPDRGA3,PHY Unit Register Address 3" hexmask.long.word 0x14 0.--15. 1. "pra3,PHY Unit Register Address for Channel 3" line.long 0x18 "DBPDRGD3,PHY Unit Register Access 3" hexmask.long 0x18 0.--31. 1. "prd3,PHY Unit Registers Access for channel 3" rgroup.long 0x6F0++0x3 line.long 0x0 "DBPDSTAT30,PHY Status Register 30" hexmask.long.byte 0x0 8.--12. 1. "freqchgreqtype3,Frequency change request type for DDR-PHY Channel 3" bitfld.long 0x0 0. "freqchgreq3,Frequency change request for DDR-PHY Channel 3" "0,1" group.long 0x804++0x3 line.long 0x0 "DBBUS0CNF1,Bus Control Unit Configuration Register 1" hexmask.long.byte 0x0 2.--7. 1. "bkadp,Bank Interleave Mode Setting." bitfld.long 0x0 0.--1. "bkadm,Bank Address Mode" "0: The whole logical address space is regarded as..,1: Setting prohibited,2: Setting prohibited,3: One for bank 0" group.long 0x904++0xB line.long 0x0 "DBCAM0CNF1,CAM Unit Configuration Register 1" hexmask.long.byte 0x0 16.--23. 1. "wbkwait,Writeback Wait" hexmask.long.byte 0x0 12.--15. 1. "swpinpri3,Swap-In Priority Threshold 3" newline hexmask.long.byte 0x0 8.--11. 1. "swpinpri2,Swap-In Priority Threshold 2" hexmask.long.byte 0x0 4.--7. 1. "swpinpri1,Swap-In Priority Threshold 1" newline hexmask.long.byte 0x0 0.--3. 1. "swpinpri1f,Swap-In Priority Threshold 1F" line.long 0x4 "DBCAM0CNF2,CAM Unit Configuration Register 2" bitfld.long 0x4 8.--9. "fillunit,Read Fill Minimum Size" "0: 64 bytes,1: 128 bytes,?,?" hexmask.long.byte 0x4 4.--7. 1. "fcdirtymax,Swap-In Threshold" newline hexmask.long.byte 0x4 0.--3. 1. "fcdirtymin,Swap-Out Threshold" line.long 0x8 "DBCAM0CNF3,CAM Unit Configuration Register 3" hexmask.long.byte 0x8 0.--7. 1. "rdfull,Read Queue Full Threshold setting" group.long 0x940++0x3 line.long 0x0 "DBCAM0CTRL0,CAM Unit Contoro Register 0" bitfld.long 0x0 0. "camflush,CAM Flush" "0: No flush,1: Flush" group.long 0x980++0x3 line.long 0x0 "DBCAM0STAT0,CAM0 Unit Status Register 0" bitfld.long 0x0 0. "camempty0,CAM0 Empty" "0: Data exists in cache 0,1: Data is empty in cache 0" group.long 0x990++0x3 line.long 0x0 "DBCAM1STAT0,CAM1 Unit Status Register 0" bitfld.long 0x0 0. "camempty1,CAM1 Empty" "0: Data exists in cache 1,1: Data is empty in cache 1" group.long 0x9A0++0x3 line.long 0x0 "DBCAM2STAT0,CAM2 Unit Status Register 0" bitfld.long 0x0 0. "camempty2,CAM2 Empty" "0: Data exists in cache 2,1: Data is empty in cache 2" group.long 0x9B0++0x3 line.long 0x0 "DBCAM3STAT0,CAM3 Unit Status Register 0" bitfld.long 0x0 0. "camempty3,CAM3 Empty" "0: Data exists in cache 3,1: Data is empty in cache 3" group.long 0x9F0++0x3 line.long 0x0 "DBBSWAP,Byte Swap Table Configuration Register" hexmask.long 0x0 0.--31. 1. "bswap,Byte Swap Table Setting" group.long 0x9FC++0x3 line.long 0x0 "DBBCAMDIS,CAM Unit Operation Setting Register" bitfld.long 0x0 0. "resrdis,Response Right Disable" "0: Control of the response right is enabled,1: Control of the response right is disabled" group.long 0x1000++0x7 line.long 0x0 "DBSCHCNT0,Scheduler Unit Operation Setting Register 0" bitfld.long 0x0 24.--25. "scqosckps,Prescaler Setting for QoS counter." "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "scqtzen,Quantization Bit Enable" newline bitfld.long 0x0 5. "scszen,Burst Size Based Scheduling Enable" "0,1" bitfld.long 0x0 4. "scbaen,Bank Miss Based Scheduling Enable" "0,1" newline bitfld.long 0x0 2. "scpgen,Page Hit Based Scheduling Enable" "0,1" bitfld.long 0x0 1. "scrwen,Read Write Based Scheduling Enable" "0,1" newline bitfld.long 0x0 0. "scqosen,QoS Level Based Scheduling Enable" "0,1" line.long 0x4 "DBSCHCNT1,Scheduler Unit Operation Setting Register 1" hexmask.long.byte 0x4 12.--15. 1. "schch3,Channel Number for Physical Channel 3 Setting" hexmask.long.byte 0x4 8.--11. 1. "schch2,Channel Number for Physical Channel 2 Setting" newline hexmask.long.byte 0x4 4.--7. 1. "schch1,Channel Number for Physical Channel 1 Setting" hexmask.long.byte 0x4 0.--3. 1. "schch0,Channel Number for Physical Channel 0 Setting" group.long 0x1010++0x3 line.long 0x0 "DBSCHSZ0,Size Miss Scheduling Setting Register 0" hexmask.long.byte 0x0 0.--7. 1. "szth,Size Miss Threshold Setting" group.long 0x1020++0x7 line.long 0x0 "DBSCHRW0,Read/Write Scheduling Setting Register 0" hexmask.long.byte 0x0 28.--31. 1. "rdstptol3,Stop Tolerance for Read Period on Quantization Leve 3" hexmask.long.byte 0x0 24.--27. 1. "rdstptol2,Stop Tolerance for Read Period on Quantization Leve 2" newline hexmask.long.byte 0x0 20.--23. 1. "rdstptol1,Stop Tolerance for Read Period on Quantization Leve 1" hexmask.long.byte 0x0 16.--19. 1. "rdstptol0,Stop Tolerance for Read Period on Quantization Leve 0" newline hexmask.long.byte 0x0 12.--15. 1. "wrstptol3,Stop Tolerance for Write Period on Quantization Leve 3" hexmask.long.byte 0x0 8.--11. 1. "wrstptol2,Stop Tolerance for Write Period on Quantization Leve 2" newline hexmask.long.byte 0x0 4.--7. 1. "wrstptol1,Stop Tolerance for Write Period on Quantization Leve 1" hexmask.long.byte 0x0 0.--3. 1. "wrstptol0,Stop Tolerance for Write Period on Quantization Leve 0" line.long 0x4 "DBSCHRW1,Read/Write Scheduling Setting Register 1" hexmask.long.byte 0x4 0.--7. 1. "sctrfcab,REF to ACT REF for All Banks Interval Setting for scheduler" group.long 0x1030++0xF line.long 0x0 "DBSCHQOS00,QoS Level Operation Setting Register 00" hexmask.long.word 0x0 0.--15. 1. "qos0ini,QoS Level 0 Counter Initial Value Setting" line.long 0x4 "DBSCHQOS01,QoS Level Operation Setting Register 01" hexmask.long.word 0x4 0.--15. 1. "qos0th0,QoS Level 0 Threshold 0 Setting" line.long 0x8 "DBSCHQOS02,QoS Level Operation Setting Register 02" hexmask.long.word 0x8 0.--15. 1. "qos0th1,QoS Level 0 Threshold 1 Setting" line.long 0xC "DBSCHQOS03,QoS Level Operation Setting Register 03" hexmask.long.word 0xC 0.--15. 1. "qos0th2,QoS Level 0 Threshold 2 Setting" group.long 0x1070++0xF line.long 0x0 "DBSCHQOS40,QoS Level Operation Setting Register 40" hexmask.long.word 0x0 0.--15. 1. "qos4ini,QoS Level 4 Counter Initial Value Setting" line.long 0x4 "DBSCHQOS41,QoS Level Operation Setting Register 41" hexmask.long.word 0x4 0.--15. 1. "qos4th0,QoS Level 4 Threshold 0 Setting" line.long 0x8 "DBSCHQOS42,QoS Level Operation Setting Register 42" hexmask.long.word 0x8 0.--15. 1. "qos4th1,QoS Level 4 Threshold 1 Setting" line.long 0xC "DBSCHQOS43,QoS Level Operation Setting Register 43" hexmask.long.word 0xC 0.--15. 1. "qos4th2,QoS Level 4 Threshold 2 Setting" group.long 0x10C0++0xF line.long 0x0 "DBSCHQOS90,QoS Level Operation Setting Register 90" hexmask.long.word 0x0 0.--15. 1. "qos9ini,QoS Level 9 Counter Initial Value Setting" line.long 0x4 "DBSCHQOS91,QoS Level Operation Setting Register 91" hexmask.long.word 0x4 0.--15. 1. "qos9th0,QoS Level 9 Threshold 0 Setting" line.long 0x8 "DBSCHQOS92,QoS Level Operation Setting Register 92" hexmask.long.word 0x8 0.--15. 1. "qos9th1,QoS Level 9 Threshold 1 Setting" line.long 0xC "DBSCHQOS93,QoS Level Operation Setting Register 93" hexmask.long.word 0xC 0.--15. 1. "qos9th2,QoS Level 9 Threshold 2 Setting" group.long 0x10F0++0x3F line.long 0x0 "DBSCHQOS120,QoS Level Operation Setting Register 120" hexmask.long.word 0x0 0.--15. 1. "qos12ini,QoS Level 12 Counter Initial Value Setting" line.long 0x4 "DBSCHQOS121,QoS Level Operation Setting Register 121" hexmask.long.word 0x4 0.--15. 1. "qos12th0,QoS Level 12 Threshold 0 Setting" line.long 0x8 "DBSCHQOS122,QoS Level Operation Setting Register 122" hexmask.long.word 0x8 0.--15. 1. "qos12th1,QoS Level 12 Threshold 1 Setting" line.long 0xC "DBSCHQOS123,QoS Level Operation Setting Register 123" hexmask.long.word 0xC 0.--15. 1. "qos12th2,QoS Level 12 Threshold 2 Setting" line.long 0x10 "DBSCHQOS130,QoS Level Operation Setting Register 130" hexmask.long.word 0x10 0.--15. 1. "qos13ini,QoS Level 13 Counter Initial Value Setting" line.long 0x14 "DBSCHQOS131,QoS Level Operation Setting Register 131" hexmask.long.word 0x14 0.--15. 1. "qos13th0,QoS Level 13 Threshold 0 Setting" line.long 0x18 "DBSCHQOS132,QoS Level Operation Setting Register 132" hexmask.long.word 0x18 0.--15. 1. "qos13th1,QoS Level 13 Threshold 1 Setting" line.long 0x1C "DBSCHQOS133,QoS Level Operation Setting Register 133" hexmask.long.word 0x1C 0.--15. 1. "qos13th2,QoS Level 13 Threshold 2 Setting" line.long 0x20 "DBSCHQOS140,QoS Level Operation Setting Register 140" hexmask.long.word 0x20 0.--15. 1. "qos14ini,QoS Level 14 Counter Initial Value Setting" line.long 0x24 "DBSCHQOS141,QoS Level Operation Setting Register 141" hexmask.long.word 0x24 0.--15. 1. "qos14th0,QoS Level 14 Threshold 0 Setting" line.long 0x28 "DBSCHQOS142,QoS Level Operation Setting Register 142" hexmask.long.word 0x28 0.--15. 1. "qos14th1,QoS Level 14 Threshold 1 Setting" line.long 0x2C "DBSCHQOS143,QoS Level Operation Setting Register 143" hexmask.long.word 0x2C 0.--15. 1. "qos14th2,QoS Level 14 Threshold 2 Setting" line.long 0x30 "DBSCHQOS150,QoS Level Operation Setting Register 150" hexmask.long.word 0x30 0.--15. 1. "qos15ini,QoS Level 15 Counter Initial Value Setting" line.long 0x34 "DBSCHQOS151,QoS Level Operation Setting Register 151" hexmask.long.word 0x34 0.--15. 1. "qos15th0,QoS Level 15 Threshold 0 Setting" line.long 0x38 "DBSCHQOS152,QoS Level Operation Setting Register 152" hexmask.long.word 0x38 0.--15. 1. "qos15th1,QoS Level 15 Threshold 1 Setting" line.long 0x3C "DBSCHQOS153,QoS Level Operation Setting Register 153" hexmask.long.word 0x3C 0.--15. 1. "qos15th2,QoS Level 15 Threshold 2 Setting" group.long 0x1700++0x3 line.long 0x0 "DBSCHFCTST0,Schedule Timing Setting Register 0" hexmask.long.byte 0x0 24.--31. 1. "scactact,ACT to ACT Interval Setting for scheduler" hexmask.long.byte 0x0 16.--23. 1. "scrdact,RD to ACT Interval Setting for scheduler" newline hexmask.long.byte 0x0 8.--15. 1. "scwract,WR to ACT Interval Setting for scheduler" hexmask.long.byte 0x0 0.--7. 1. "scpreact,PRE to ACT Interval Setting for scheduler" group.long 0x1708++0xB line.long 0x0 "DBSCHFCTST1,Schedule Timing Setting Register 1" hexmask.long.byte 0x0 24.--31. 1. "scrdwr,RD to WR Interval Setting for scheduler" hexmask.long.byte 0x0 16.--23. 1. "scwrrd,WR to RD Interval Setting for scheduler" newline hexmask.long.byte 0x0 8.--15. 1. "scactrdwr,ACT to RD WR Interval Setting for scheduler" hexmask.long.byte 0x0 0.--7. 1. "scasyncofs,Asynchronous stage offset Setting" line.long 0x4 "DBSCHFCTST2,Schedule Timing Setting Register 2" hexmask.long.byte 0x4 28.--31. 1. "wrperi3,Write Priority Period setting on Quantization Level 3" hexmask.long.byte 0x4 24.--27. 1. "wrperi2,Write Priority Period setting on Quantization Level 2" newline hexmask.long.byte 0x4 20.--23. 1. "wrperi1,Write Priority Period setting on Quantization Level 1" hexmask.long.byte 0x4 16.--19. 1. "wrperi0,Write Priority Period setting on Quantization Level 0" newline hexmask.long.byte 0x4 12.--15. 1. "rdperi3,Read Priority Period setting on Quantization Level 3" hexmask.long.byte 0x4 8.--11. 1. "rdperi2,Read Priority Period setting on Quantization Level 2" newline hexmask.long.byte 0x4 4.--7. 1. "rdperi1,Read Priority Period setting on Quantization Level 1" hexmask.long.byte 0x4 0.--3. 1. "rdperi0,Read Priority Period setting on Quantization Level 0" line.long 0x8 "DBSCHTR0,Data Transfer Cycle Setting Register 0" hexmask.long.byte 0x8 24.--31. 1. "scdt3,Data Transfer Cycle Setting for 256 Bytes Data" hexmask.long.byte 0x8 16.--23. 1. "scdt2,Data Transfer Cycle Setting for 192 Bytes Data" newline hexmask.long.byte 0x8 8.--15. 1. "scdt1,Data Transfer Cycle Setting for 128 Bytes Data" hexmask.long.byte 0x8 0.--7. 1. "scdt0,Data Transfer Cycle Setting for 64 Bytes Data" group.long 0x1800++0x1F line.long 0x0 "DBMRRDR0,Mode Register Read Data Register 0" hexmask.long.byte 0x0 8.--15. 1. "mrrdr01,MRR Read Data for Channel 0 A Rank 1" hexmask.long.byte 0x0 0.--7. 1. "mrrdr00,MRR Read Data for Channel 0 A Rank 0" line.long 0x4 "DBMRRDR1,Mode Register Read Data Register 1" hexmask.long.byte 0x4 8.--15. 1. "mrrdr11,MRR Read Data for Channel 0 B Rank 1" hexmask.long.byte 0x4 0.--7. 1. "mrrdr10,MRR Read Data for Channel 0 B Rank 0" line.long 0x8 "DBMRRDR2,Mode Register Read Data Register 2" hexmask.long.byte 0x8 8.--15. 1. "mrrdr21,MRR Read Data for Channel 1 A Rank 1" hexmask.long.byte 0x8 0.--7. 1. "mrrdr20,MRR Read Data for Channel 1 A Rank 0" line.long 0xC "DBMRRDR3,Mode Register Read Data Register 3" hexmask.long.byte 0xC 8.--15. 1. "mrrdr31,MRR Read Data for Channel 1 B Rank 1" hexmask.long.byte 0xC 0.--7. 1. "mrrdr30,MRR Read Data for Channel 1 B Rank 0" line.long 0x10 "DBMRRDR4,Mode Register Read Data Register 4" hexmask.long.byte 0x10 8.--15. 1. "mrrdr41,MRR Read Data for Channel 2 A Rank 1" hexmask.long.byte 0x10 0.--7. 1. "mrrdr40,MRR Read Data for Channel 2 A Rank 0" line.long 0x14 "DBMRRDR5,Mode Register Read Data Register 5" hexmask.long.byte 0x14 8.--15. 1. "mrrdr51,MRR Read Data for Channel 2 B Rank 1" hexmask.long.byte 0x14 0.--7. 1. "mrrdr50,MRR Read Data for Channel 2 B Rank 0" line.long 0x18 "DBMRRDR6,Mode Register Read Data Register 6" hexmask.long.byte 0x18 8.--15. 1. "mrrdr61,MRR Read Data for Channel 3 A Rank 1" hexmask.long.byte 0x18 0.--7. 1. "mrrdr60,MRR Read Data for Channel 3 A Rank 0" line.long 0x1C "DBMRRDR7,Mode Register Read Data Register 7" hexmask.long.byte 0x1C 8.--15. 1. "mrrdr71,MRR Read Data for Channel 3 B Rank 1" hexmask.long.byte 0x1C 0.--7. 1. "mrrdr70,MRR Read Data for Channel 3 B Rank 0" group.long 0x3010++0x3 line.long 0x0 "DBMONCONF4,Monitor Configuration Register 4" bitfld.long 0x0 20.--22. "mnstatsel,Monitor0 QoS level" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--19. 1. "mn0qoslv,BUFCAM status selection" group.long 0x7000++0x2B line.long 0x0 "DBFSINTXXX00A,Fusa Interrupt Indication Register 0 for AXI Domain" bitfld.long 0x0 31. "intexdclaxa,Comparator error of DCLS for clk_axi group Interrupt indication" "0,1" bitfld.long 0x0 30. "intexdclsra,Comparator error of DCLS group sram interrupt indication" "0,1" newline bitfld.long 0x0 10. "intodasbda,OrderID error in AXI64 Bch clk_dbs side Interrupt indication" "0,1" bitfld.long 0x0 9. "intodasrda,OrderID error in AXI64 Rch clk_dbs side Interrupt indication" "0,1" newline bitfld.long 0x0 8. "intodasbxa,OrderID error in AXI64 Bch clk_axi side Interrupt indication" "0,1" bitfld.long 0x0 7. "intodasrxa,OrderID error in AXI64 Rch clk_axi side Interrupt indication" "0,1" newline bitfld.long 0x0 6. "intodaswxa,OrderID error in AXI64 Wch clk_axi side Interrupt indication" "0,1" bitfld.long 0x0 5. "intodasawa,OrderID error in AXI64 AWch clk_axi side Interrupt indication" "0,1" newline bitfld.long 0x0 4. "intodasara,OrderID error in AXI64 ARch clk_axi side Interrupt indication" "0,1" bitfld.long 0x0 2. "intdxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt indication" "0,1" newline bitfld.long 0x0 1. "intdxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt indication" "0,1" bitfld.long 0x0 0. "intdxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt indication" "0,1" line.long 0x4 "DBFSINTXXX01A,Fusa Interrupt Indication Register 1 for AXI Domain" bitfld.long 0x4 22. "intnomem1a,No mem error in address decoder of dbsccore1 interrupt indication" "0,1" bitfld.long 0x4 21. "intedbccr1a,Cache RAM duplication error interrupt indication for dbsccore1" "0,1" newline bitfld.long 0x4 20. "intcxfcprd1a,CRC error in FCPRD for core1 Interrupt indication for dbsccore1" "0,1" bitfld.long 0x4 19. "intdxamawx1a,EDC error in AXMM W Ch Interrupt indication for dbsccore1" "0,1" newline bitfld.long 0x4 18. "intdxamaw1a,EDC error in AXMM AW Ch Interrupt indication for dbsccore1" "0,1" bitfld.long 0x4 17. "intdxamar1a,EDC error in AXMM AR Ch Interrupt indication for dbsccore1" "0,1" newline bitfld.long 0x4 16. "intepdvaxi1a,POST error in AXI domain interrupt indication for dbsccore1" "0,1" bitfld.long 0x4 6. "intnomem0a,No mem error in address decoder of dbsccore0 interrupt indication" "0,1" newline bitfld.long 0x4 5. "intedbccr0a,Cache RAM duplication error interrupt indication for dbsccore0" "0,1" bitfld.long 0x4 4. "intcxfcprd0a,CRC error in FCPRD for core1 Interrupt indication for dbsccore0" "0,1" newline bitfld.long 0x4 3. "intdxamawx0a,EDC error in AXMM W Ch Interrupt indication for dbsccore0" "0,1" bitfld.long 0x4 2. "intdxamaw0a,EDC error in AXMM AW Ch Interrupt indication for dbsccore0" "0,1" newline bitfld.long 0x4 1. "intdxamar0a,EDC error in AXMM AR Ch Interrupt indication for dbsccore0" "0,1" bitfld.long 0x4 0. "intepdvaxi0a,POST error in AXI domain interrupt indication for dbsccore0" "0,1" line.long 0x8 "DBFSINTXXX02A,Fusa Interrupt Indication Register 2 for AXI Domain" hexmask.long.byte 0x8 24.--31. 1. "intcmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt indication for dbsccore0" hexmask.long.byte 0x8 16.--23. 1. "intcdbcsr0a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt indication for dbsccore0" newline hexmask.long.byte 0x8 8.--15. 1. "intcmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt indication for dbsccore0" hexmask.long.byte 0x8 0.--7. 1. "intcdbcrr0a,ECC error (detect: 1bit error and correct) for read response Interrupt indication for dbsccore0" line.long 0xC "DBFSINTXXX03A,Fusa Interrupt Indication Register 3 for AXI Domain" hexmask.long 0xC 0.--31. 1. "intcdbcdr0a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt indication for dbsccore0" line.long 0x10 "DBFSINTXXX04A,Fusa Interrupt Indication Register 4 for AXI Domain" hexmask.long 0x10 0.--31. 1. "intcmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt indication for dbsccore0" line.long 0x14 "DBFSINTXXX05A,Fusa Interrupt Indication Register 5 for AXI Domain" hexmask.long.byte 0x14 24.--31. 1. "intcmbcsr1a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt indication for dbsccore1" hexmask.long.byte 0x14 16.--23. 1. "intcdbcsr1a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt indication for dbsccore1" newline hexmask.long.byte 0x14 8.--15. 1. "intcmbcrr1a,ECC error (multi: over 2bit error) for read response Interrupt indication for dbsccore1" hexmask.long.byte 0x14 0.--7. 1. "intcdbcrr1a,ECC error (detect: 1bit error and correct) for read response Interrupt indication for dbsccore1" line.long 0x18 "DBFSINTXXX06A,Fusa Interrupt Indication Register 6 for AXI Domain" hexmask.long 0x18 0.--31. 1. "intcdbcdr1a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt indication for dbsccore1" line.long 0x1C "DBFSINTXXX07A,Fusa Interrupt Indication Register 7 for AXI Domain" hexmask.long 0x1C 0.--31. 1. "intcmbcdr1a,ECC error (multi: over 2bit error) for DRAM RMW interrupt indication for dbsccore1" line.long 0x20 "DBFSINTXXX08A,Fusa Interrupt Indication Register 8 for AXI Domain" bitfld.long 0x20 18. "intexbcdr1a,ECC error injection for ECC checker for DRAM RMW interrupt indication for dbsccore1" "0,1" bitfld.long 0x20 17. "intexbcsr1a,ECC error injection for ECC checker for SystemRAM RMW Interrupt indication for dbsccore1" "0,1" newline bitfld.long 0x20 16. "intexbcrr1a,ECC error injection for ECC checker for read response Interrupt indication for dbsccore1" "0,1" bitfld.long 0x20 2. "intexbcdr0a,ECC error injection for ECC checker for DRAM RMW interrupt indication for dbsccore0" "0,1" newline bitfld.long 0x20 1. "intexbcsr0a,ECC error injection for ECC checker for SystemRAM RMW Interrupt indication for dbsccore0" "0,1" bitfld.long 0x20 0. "intexbcrr0a,ECC error injection for ECC checker for read response Interrupt indication for dbsccore0" "0,1" line.long 0x24 "DBFSINTXXX09A,Fusa Interrupt Indication Register 9 for AXI Domain" bitfld.long 0x24 25. "intoddvard3a,OrderID error of isbus async read ch. interrupt indication for memory channel 3" "0,1" bitfld.long 0x24 24. "intdxdvard3a,EDC error of isbus async read ch. interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x24 17. "intoddvard2a,OrderID error of isbus async read ch. interrupt indication for memory channel 2" "0,1" bitfld.long 0x24 16. "intdxdvard2a,EDC error of isbus async read ch. interrupt indication for memory channel 2" "0,1" newline bitfld.long 0x24 9. "intoddvard1a,OrderID error of isbus async read ch. interrupt indication for memory channel 1" "0,1" bitfld.long 0x24 8. "intdxdvard1a,EDC error of isbus async read ch. interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x24 1. "intoddvard0a,OrderID error of isbus async read ch. interrupt indication for memory channel 0" "0,1" bitfld.long 0x24 0. "intdxdvard0a,EDC error of isbus async read ch. interrupt indication for memory channel 0" "0,1" line.long 0x28 "DBFSINTXXX10A,Fusa Interrupt Indication Register 10 for AXI Domain" hexmask.long.word 0x28 0.--15. 1. "intxxasynsba,Async sideband errors in axi domain" group.long 0x7040++0x3 line.long 0x0 "DBFSINTCLR00A,Fusa Interrupt Clear Register for AXI Domain" bitfld.long 0x0 0. "icldclsa,Clear safety error interrupt signal (level) for clk_axi domain" "0,1" group.long 0x7080++0x2B line.long 0x0 "DBFSINTENB00A,Fusa Interrupt Enable Register 0 for AXI Domain" bitfld.long 0x0 31. "ienexdclaxa,Comparator error of DCLS for clk_axi group Interrupt enable bit" "0,1" bitfld.long 0x0 30. "ienexdclsra,Comparator error of DCLS group sram interrupt enable bit" "0,1" newline bitfld.long 0x0 10. "ienodasbda,OrderID error in AXI64 Bch clk_dbs side Interrupt enable bit" "0,1" bitfld.long 0x0 9. "ienodasrda,OrderID error in AXI64 Rch clk_dbs side Interrupt enable bit" "0,1" newline bitfld.long 0x0 8. "ienodasbxa,OrderID error in AXI64 Bch clk_axi side Interrupt enable bit" "0,1" bitfld.long 0x0 7. "ienodasrxa,OrderID error in AXI64 Rch clk_axi side Interrupt enable bit" "0,1" newline bitfld.long 0x0 6. "ienodaswxa,OrderID error in AXI64 Wch clk_axi side Interrupt enable bit" "0,1" bitfld.long 0x0 5. "ienodasawa,OrderID error in AXI64 AWch clk_axi side Interrupt enable bit" "0,1" newline bitfld.long 0x0 4. "ienodasara,OrderID error in AXI64 ARch clk_axi side Interrupt enable bit" "0,1" bitfld.long 0x0 2. "iendxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt enable bit" "0,1" newline bitfld.long 0x0 1. "iendxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt enable bit" "0,1" bitfld.long 0x0 0. "iendxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt enable bit." "0,1" line.long 0x4 "DBFSINTENB01A,Fusa Interrupt Enable Register 1 for AXI Domain" bitfld.long 0x4 22. "iennomem1a,No mem error in address decoder of dbsccore1 interrupt enable bit" "0,1" bitfld.long 0x4 21. "ienedbccr1a,Cache RAM duplication error interrupt enable bit for dbsccore1" "0,1" newline bitfld.long 0x4 20. "iencxfcprd1a,ECC error in FCPRD for core1 Interrupt enable bit" "0,1" bitfld.long 0x4 19. "iendxamawx1a,EDC error in AXMM W Ch Interrupt enable bit for dbsccore1" "0,1" newline bitfld.long 0x4 18. "iendxamaw1a,EDC error in AXMM AR Ch Interrupt enable bit for dbsccore1" "0,1" bitfld.long 0x4 17. "iendxamar1a,EDC error in AXMM AW Ch Interrupt enable bit for dbsccore1" "0,1" newline bitfld.long 0x4 16. "ienepdvaxi1a,POST error in AXI domain interrupt enable bit for dbsccore1" "0,1" bitfld.long 0x4 6. "iennomem0a,No mem error in address decoder of dbsccore0 interrupt enable bit" "0,1" newline bitfld.long 0x4 5. "ienedbccr0a,Cache RAM duplication error interrupt enable bit for dbsccore0" "0,1" bitfld.long 0x4 4. "iencxfcprd0a,ECC error in FCPRD for core0 Interrupt enable bit for dbsccore0" "0,1" newline bitfld.long 0x4 3. "iendxamawx0a,EDC error in AXMM W Ch Interrupt enable bit for dbsccore0" "0,1" bitfld.long 0x4 2. "iendxamaw0a,EDC error in AXMM AW Ch Interrupt enable bit for dbsccore0" "0,1" newline bitfld.long 0x4 1. "iendxamar0a,EDC error in AXMM AR Ch Interrupt enable bit for dbsccore0" "0,1" bitfld.long 0x4 0. "ienepdvaxi0a,POST error in AXI domain interrupt enable bit for dbsccore0" "0,1" line.long 0x8 "DBFSINTENB02A,Fusa Interrupt Enable Register 2 for AXI Domain" hexmask.long.byte 0x8 24.--31. 1. "iencmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt enable bit for dbsccore0" hexmask.long.byte 0x8 16.--23. 1. "iencdbcsr0a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt enable bit for dbsccore0" newline hexmask.long.byte 0x8 8.--15. 1. "iencmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt enable bit for dbsccore0" hexmask.long.byte 0x8 0.--7. 1. "iencdbcrr0a,ECC error (detect: 1bit error and correct) for read response Interrupt enable bit for dbsccore0" line.long 0xC "DBFSINTENB03A,Fusa Interrupt Enable Register 3 for AXI Domain" hexmask.long 0xC 0.--31. 1. "iencdbcdr0a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt enable bit for dbsccore0" line.long 0x10 "DBFSINTENB04A,Fusa Interrupt Enable Register 4 for AXI Domain" hexmask.long 0x10 0.--31. 1. "iencmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt enable bit for dbsccore0" line.long 0x14 "DBFSINTENB05A,Fusa Interrupt Enable Register 5 for AXI Domain" hexmask.long.byte 0x14 24.--31. 1. "iencmbcsr1a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt enable bit for dbsccore1" hexmask.long.byte 0x14 16.--23. 1. "iencdbcsr1a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt enable bit for dbsccore1" newline hexmask.long.byte 0x14 8.--15. 1. "iencmbcrr1a,ECC error (multi: over 2bit error) for read response Interrupt enable bit for dbsccore1" hexmask.long.byte 0x14 0.--7. 1. "iencdbcrr1a,ECC error (detect: 1bit error and correct) for read response Interrupt enable bit for dbsccore1" line.long 0x18 "DBFSINTENB06A,Fusa Interrupt Enable Register 6 for AXI Domain" hexmask.long 0x18 0.--31. 1. "iencdbcdr1a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt enable bit for dbsccore1" line.long 0x1C "DBFSINTENB07A,Fusa Interrupt Enable Register 7 for AXI Domain" hexmask.long 0x1C 0.--31. 1. "iencmbcdr1a,ECC error (multi: over 2bit error) for DRAM RMW interrupt enable bit for dbsccore1" line.long 0x20 "DBFSINTENB08A,Fusa Interrupt Enable Register 8 for AXI Domain" bitfld.long 0x20 18. "ienexbcdr1a,ECC error injection for ECC checker for DRAM RMW interrupt enable bit for dbsccore1" "0,1" bitfld.long 0x20 17. "ienexbcsr1a,ECC error injection for ECC checker for SystemRAM RMW Interrupt enable bit for dbsccore1" "0,1" newline bitfld.long 0x20 16. "ienexbcrr1a,ECC error injection for ECC checker for read response Interrupt enable bit for dbsccore1" "0,1" bitfld.long 0x20 2. "ienexbcdr0a,ECC error injection for ECC checker for DRAM RMW interrupt enable bit for dbsccore0" "0,1" newline bitfld.long 0x20 1. "ienexbcsr0a,ECC error injection for ECC checker for SystemRAM RMW Interrupt enable bit for dbsccore0" "0,1" bitfld.long 0x20 0. "ienexbcrr0a,ECC error injection for ECC checker for read response Interrupt enable bit for dbsccore0" "0,1" line.long 0x24 "DBFSINTENB09A,Fusa Interrupt Enable Register 9 for AXI Domain" bitfld.long 0x24 25. "ienoddvard3a,OrderID error of isbus async read ch. interrupt enable for memory channel 3" "0,1" bitfld.long 0x24 24. "iendxdvard3a,EDC error of isbus async read ch. interrupt enable for memory channel 3" "0,1" newline bitfld.long 0x24 17. "ienoddvard2a,OrderID error of isbus async read ch. interrupt enable for memory channel 2" "0,1" bitfld.long 0x24 16. "iendxdvard2a,EDC error of isbus async read ch. interrupt enable for memory channel 2" "0,1" newline bitfld.long 0x24 9. "ienoddvard1a,OrderID error of isbus async read ch. interrupt enable for memory channel 1" "0,1" bitfld.long 0x24 8. "iendxdvard1a,EDC error of isbus async read ch. interrupt enable for memory channel 1" "0,1" newline bitfld.long 0x24 1. "ienoddvard0a,OrderID error of isbus async read ch. interrupt enable for memory channel 0" "0,1" bitfld.long 0x24 0. "iendxdvard0a,EDC error of isbus async read ch. interrupt enable for memory channel 0" "0,1" line.long 0x28 "DBFSINTENB10A,Fusa Interrupt Enable Register 10 for AXI Domain" hexmask.long.word 0x28 0.--15. 1. "ienxxasynsba,Async sideband errors interrupt enable in axi domain" group.long 0x7100++0x1F line.long 0x0 "DBFSINJECT00A,Fusa Injection Mode Register 0 for AXI Domain" bitfld.long 0x0 31. "ijtexdclaxa,Comparator error of DCLS for clk_axi group Interrupt injection mode" "0,1" bitfld.long 0x0 30. "ijtexdclsra,Comparator error of DCLS for sram Interrupt injection mode" "0,1" newline bitfld.long 0x0 10. "ijtodasbda,OrderID error in AXI64 Bch clk_dbs side Interrupt injection mode" "0,1" bitfld.long 0x0 9. "ijtodasrda,OrderID error in AXI64 Rch clk_dbs side Interrupt injection mode" "0,1" newline bitfld.long 0x0 8. "ijtodasbxa,OrderID error in AXI64 Bch clk_axi side Interrupt injection mode" "0,1" bitfld.long 0x0 7. "ijtodasrxa,OrderID error in AXI64 Rch clk_axi side Interrupt injection mode" "0,1" newline bitfld.long 0x0 6. "ijtodaswxa,OrderID error in AXI64 Wch clk_axi side Interrupt injection mode" "0,1" bitfld.long 0x0 5. "ijtodasawa,OrderID error in AXI64 AWch clk_axi side Interrupt injection mode" "0,1" newline bitfld.long 0x0 4. "ijtodasara,OrderID error in AXI64 ARch clk_axi side Interrupt injection mode" "0,1" bitfld.long 0x0 2. "ijtdxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt injection mode" "0,1" newline bitfld.long 0x0 1. "ijtdxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt injection mode" "0,1" bitfld.long 0x0 0. "ijtdxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt injection mode" "0,1" line.long 0x4 "DBFSINJECT01A,Fusa Injection Mode Register 1 for AXI Domain" bitfld.long 0x4 22. "ijtnomem1a,No mem error in address decoder of dbsccore1 interrupt injection mode" "0,1" bitfld.long 0x4 21. "ijtedbccr1a,Cache RAM duplication error interrupt injection mode for dbsccore1" "0,1" newline bitfld.long 0x4 20. "ijtcxfcprd1a,CRC error in FCPRD for core1 Interrupt injection mode" "0,1" bitfld.long 0x4 19. "ijtdxamawx1a,EDC error in AXMM W Ch Interrupt injection mode for dbsccore1" "0,1" newline bitfld.long 0x4 18. "ijtdxamaw1a,EDC error in AXMM AR Ch Interrupt injection mode for dbsccore1" "0,1" bitfld.long 0x4 17. "ijtdxamar1a,EDC error in AXMM AW Ch Interrupt injection mode for dbsccore1" "0,1" newline bitfld.long 0x4 16. "ijtepdvaxi1a,POST error in AXI domain interrupt injection mode for dbsccore1" "0,1" bitfld.long 0x4 6. "ijtnomem0a,No mem error in address decoder of dbsccore0 interrupt injection mode" "0,1" newline bitfld.long 0x4 5. "ijtedbccr0a,Cache RAM duplication error interrupt injection mode for dbsccore0" "0,1" bitfld.long 0x4 4. "ijtcxfcprd0a,CRC error in FCPRD for core0 Interrupt injection mode for dbsccore0" "0,1" newline bitfld.long 0x4 3. "ijtdxamawx0a,EDC error in AXMM W Ch Interrupt injection mode for dbsccore0" "0,1" bitfld.long 0x4 2. "ijtdxamaw0a,EDC error in AXMM AW Ch Interrupt injection mode for dbsccore0" "0,1" newline bitfld.long 0x4 1. "ijtdxamar0a,EDC error in AXMM AR Ch Interrupt injection mode for dbsccore0" "0,1" bitfld.long 0x4 0. "ijtepdvaxi0a,POST error in AXI domain interrupt injection mode for dbsccore0" "0,1" line.long 0x8 "DBFSINJECT02A,Fusa Injection Mode Register 2 for AXI Domain" bitfld.long 0x8 24. "ijtcmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt injection mode for dbsccore0" "0,1" bitfld.long 0x8 16. "ijtcdbcsr0a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt injection mode for dbsccore0" "0,1" newline bitfld.long 0x8 8. "ijtcmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt injection mode for dbsccore0" "0,1" bitfld.long 0x8 0. "ijtcdbcrr0a,ECC error (detect: 1bit error and correct) for read response Interrupt injection mode for dbsccore0" "0,1" line.long 0xC "DBFSINJECT03A,Fusa Injection Mode Register 3 for AXI Domain" bitfld.long 0xC 0. "ijtcdbcdr0a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt injection mode for dbsccore0" "0,1" line.long 0x10 "DBFSINJECT04A,Fusa Injection Mode Register 4 for AXI Domain" bitfld.long 0x10 0. "ijtcmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt injection mode for dbsccore0" "0,1" line.long 0x14 "DBFSINJECT05A,Fusa Injection Mode Register 5 for AXI Domain" bitfld.long 0x14 24. "ijtcmbcsr1a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt injection mode for dbsccore1" "0,1" bitfld.long 0x14 16. "ijtcdbcsr1a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt injection mode for dbsccore1" "0,1" newline bitfld.long 0x14 8. "ijtcmbcrr1a,ECC error (multi: over 2bit error) for read response Interrupt injection mode for dbsccore1" "0,1" bitfld.long 0x14 0. "ijtcdbcrr1a,ECC error (detect: 1bit error and correct) for read response Interrupt injection mode for dbsccore1" "0,1" line.long 0x18 "DBFSINJECT06A,Fusa Injection Mode Register 6 for AXI Domain" bitfld.long 0x18 0. "ijtcdbcdr1a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt injection mode for dbsccore1" "0,1" line.long 0x1C "DBFSINJECT07A,Fusa Injection Mode Register 7 for AXI Domain" bitfld.long 0x1C 0. "ijtcmbcdr1a,ECC error (multi: over 2bit error) for DRAM RMW interrupt injection mode for dbsccore1" "0,1" group.long 0x7124++0x7 line.long 0x0 "DBFSINJECT09A,Fusa Injection Mode Register 8 for AXI Domain" bitfld.long 0x0 25. "ijtoddvard3a,OrderID error of isbus async read ch. interrupt injection mode for memory channel 3" "0,1" bitfld.long 0x0 24. "ijtdxdvard3a,EDC error of isbus async read ch. interrupt injection mode for memory channel 3" "0,1" newline bitfld.long 0x0 17. "ijtoddvard2a,OrderID error of isbus async read ch. interrupt injection mode for memory channel 2" "0,1" bitfld.long 0x0 16. "ijtdxdvard2a,EDC error of isbus async read ch. interrupt injection mode for memory channel 2" "0,1" newline bitfld.long 0x0 9. "ijtoddvard1a,OrderID error of isbus async read ch. interrupt injection mode for memory channel 1" "0,1" bitfld.long 0x0 8. "ijtdxdvard1a,EDC error of isbus async read ch. interrupt injection mode for memory channel 1" "0,1" newline bitfld.long 0x0 1. "ijtoddvard0a,OrderID error of isbus async read ch. interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x0 0. "ijtdxdvard0a,EDC error of isbus async read ch. interrupt injection mode for memory channel 0" "0,1" line.long 0x4 "DBFSINJECT10A,Fusa Injection Mode Register 9 for AXI Domain" hexmask.long.word 0x4 0.--15. 1. "ijtxxasynsba,Async sideband errors interrupt injection mode" group.long 0x7200++0x1F line.long 0x0 "DBFSINTCNT0A,Fusa Interrupt Counter Register 0 for AXI Domain" hexmask.long.byte 0x0 16.--23. 1. "cntdxaswxa,EDC error in AXSM W Ch clk_axi domain Interrupt counter mode" hexmask.long.byte 0x0 8.--15. 1. "cntdxasawa,EDC error in AXSM AW Ch clk_axi domain Interrupt counter mode" newline hexmask.long.byte 0x0 0.--7. 1. "cntdxasara,EDC error in AXSM AR Ch clk_axi domain Interrupt counter mode" line.long 0x4 "DBFSINTCNT1A,Fusa Interrupt Counter Register 1 for AXI Domain" hexmask.long.byte 0x4 24.--31. 1. "cntcxfcprd0a,CRC error in FCPRD Interrupt counter for dbsccore0" hexmask.long.byte 0x4 16.--23. 1. "cntdxamawx0a,EDC error in AXMM W Ch Interrupt counter for dbsccore0" newline hexmask.long.byte 0x4 8.--15. 1. "cntdxamaw0a,EDC error in AXMM AW Ch Interrupt counter for dbsccore0" hexmask.long.byte 0x4 0.--7. 1. "cntdxamar0a,EDC error in AXMM AR Ch Interrupt counter for dbsccore0" line.long 0x8 "DBFSINTCNT2A,Fusa Interrupt Counter Register 2 for AXI Domain" hexmask.long.byte 0x8 24.--31. 1. "cntcxfcprd1a,CRC error in FCPRD Interrupt counter for dbsccore1" hexmask.long.byte 0x8 16.--23. 1. "cntdxamawx1a,EDC error in AXMM W Ch Interrupt counter for dbsccore1" newline hexmask.long.byte 0x8 8.--15. 1. "cntdxamaw1a,EDC error in AXMM AW Ch Interrupt counter for dbsccore1" hexmask.long.byte 0x8 0.--7. 1. "cntdxamar1a,EDC error in AXMM AR Ch Interrupt counter for dbsccore1" line.long 0xC "DBFSINTCNT3A,Fusa Interrupt Counter Register 3 for AXI Domain" hexmask.long.byte 0xC 24.--31. 1. "cntcmbcsr0a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt counter mode for dbsccore0" hexmask.long.byte 0xC 16.--23. 1. "cntcdbcsr0a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt counter mode for dbsccore0" newline hexmask.long.byte 0xC 8.--15. 1. "cntcmbcrr0a,ECC error (multi: over 2bit error) for read response Interrupt counter mode for dbsccore0" hexmask.long.byte 0xC 0.--7. 1. "cntcdbcrr0a,ECC error (detect: 1bit error and correct) for read response Interrupt counter mode for dbsccore0" line.long 0x10 "DBFSINTCNT04A,Fusa Interrupt Counter Register 4 for AXI Domain" hexmask.long.byte 0x10 8.--15. 1. "cntcmbcdr0a,ECC error (multi: over 2bit error) for DRAM RMW interrupt counter for dbsccore0" hexmask.long.byte 0x10 0.--7. 1. "cntcdbcdr0a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt counter for dbsccore0" line.long 0x14 "DBFSINTCNT05A,Fusa Interrupt Counter Register 5 for AXI Domain" hexmask.long.byte 0x14 24.--31. 1. "cntcmbcsr1a,ECC error (multi: over 2bit error) for SystemRAM RMW Interrupt counter for dbsccore1" hexmask.long.byte 0x14 16.--23. 1. "cntcdbcsr1a,ECC error (detect: 1bit error and correct) for SystemRAM RMW Interrupt counter for dbsccore1" newline hexmask.long.byte 0x14 8.--15. 1. "cntcmbcrr1a,ECC error (multi: over 2bit error) for read response Interrupt counter for dbsccore1" hexmask.long.byte 0x14 0.--7. 1. "cntcdbcrr1a,ECC error (detect: 1bit error and correct) for read response Interrupt counter for dbsccore1" line.long 0x18 "DBFSINTCNT06A,Fusa Interrupt Counter Register 6 for AXI Domain" hexmask.long.byte 0x18 8.--15. 1. "cntcmbcdr1a,ECC error (multi: over 2bit error) for DRAM RMW interrupt counter for dbsccore1" hexmask.long.byte 0x18 0.--7. 1. "cntcdbcdr1a,ECC error (detect: 1bit error and correct) for DRAM RMW interrupt counter for dbsccore1" line.long 0x1C "DBFSINTCNT07A,Fusa Interrupt Counter Register 7 for AXI Domain" hexmask.long.byte 0x1C 24.--31. 1. "cntdxdvard3a,EDC error of isbus async read ch. interrupt counter for memory channel3" hexmask.long.byte 0x1C 16.--23. 1. "cntdxdvard2a,EDC error of isbus async read ch. interrupt counter for memory channel2" newline hexmask.long.byte 0x1C 8.--15. 1. "cntdxdvard1a,EDC error of isbus async read ch. interrupt counter for memory channel1" hexmask.long.byte 0x1C 0.--7. 1. "cntdxdvard0a,EDC error of isbus async read ch. interrupt counter for memory channel0" group.long 0x7400++0x3 line.long 0x0 "DBFSCONFAXI0,Fusa AXI Configuration Register0 for AXI Domain" bitfld.long 0x0 13. "drameccen11,ECC protection enable for DDR access for rank1 on dbsccore1." "0,1" bitfld.long 0x0 12. "drameccen10,ECC protection enable for DDR access for rank0 on dbsccore1." "0,1" newline bitfld.long 0x0 9. "drameccen01,ECC protection enable for DDR access for rank1 on dbsccore0." "0,1" bitfld.long 0x0 8. "drameccen00,ECC protection enable for DDR access for rank0 on dbsccore0." "0,1" newline bitfld.long 0x0 4. "srameccdis,ECC protection disable for SysRAM access." "0,1" bitfld.long 0x0 0. "errcrctdis,Error correction disable." "0,1" group.long 0x7410++0xF line.long 0x0 "DBFSECCIJTCHK,Fusa ECC Injection Check Register for AXI Domain" hexmask.long.word 0x0 0.--13. 1. "eccijtchk,ECC check bits for error injection" line.long 0x4 "DBFSECCIJTERRL,Fusa ECC Injection Seeting Lowbitside Register for AXI Domain" hexmask.long 0x4 0.--31. 1. "eccijterrl,Invert any 64bit data and 14 check bits (Low bit side)" line.long 0x8 "DBFSECCIJTERRM,Fusa ECC Injection Seeting Midbitside Register for AXI Domain" hexmask.long 0x8 0.--31. 1. "eccijterrm,Invert any 64bit data and 14 check bits (Middle bit side)" line.long 0xC "DBFSECCIJTERRH,Fusa ECC Injection Seeting Hibitside Register for AXI Domain" hexmask.long.word 0xC 0.--13. 1. "eccijterrh,Invert any 64bit data and 14 check bits (High bit side)" group.long 0x7430++0xF line.long 0x0 "DBFSECCIJTADRL0,Fusa ECC Injection For Address LSBside Register for AXI Domain" hexmask.long 0x0 0.--31. 1. "eccijtadrl0,Specific address register for error injection for ECC chk.(LSB side)" line.long 0x4 "DBFSECCIJTADRH0,Fusa ECC Injection For Address MSBside Register for AXI Domain" hexmask.long.byte 0x4 0.--7. 1. "eccijtadrh0,Specific address register for error injection for ECC chk.(MSB side)" line.long 0x8 "DBFSECCIJTDATL0,Fusa ECC Injection For Data LSBside Register for AXI Domain" hexmask.long 0x8 0.--31. 1. "eccijtdatl0,Data for error injection(LSB side)" line.long 0xC "DBFSECCIJTDATH0,Fusa ECC Injection For Data MSBside Register for AXI Domain" hexmask.long 0xC 0.--31. 1. "eccijtdath0,Data for error injection(MSB side)" group.long 0x7450++0x7 line.long 0x0 "DBFSDRAMECCAREA00,Fusa ECC Protection Area Setting Rank0 Register0 for AXI Domain" hexmask.long 0x0 0.--31. 1. "drameccarea00,ECC protection area for rank0 on dbsccore0." line.long 0x4 "DBFSDRAMECCAREA01,Fusa ECC Protection Area Setting Rank1 Register0 for AXI Domain" hexmask.long 0x4 0.--31. 1. "drameccarea01,ECC protection area for rank1 on dbsccore0." group.long 0x7460++0x7 line.long 0x0 "DBFSDRAMECCAREA10,Fusa ECC Protection Area Setting Rank0 Register1 for AXI Domain" hexmask.long 0x0 0.--31. 1. "drameccarea10,ECC protection area for rank0 on dbsccore1." line.long 0x4 "DBFSDRAMECCAREA11,Fusa ECC Protection Area Setting Rank1 Register1 for AXI Domain" hexmask.long 0x4 0.--31. 1. "drameccarea11,ECC protection area for rank1 on dbsccore1." group.long 0x7480++0x3 line.long 0x0 "DBFSCTRLAXI0,Fusa AXI Contorol Register 0 for AXI Domain" bitfld.long 0x0 0. "postenaxi,Start POST for asynchronous bridge in devcnt. When this bit is asserted this bit is cleared to 0 at next cycle autmatically." "0,1" group.long 0x74A0++0x7 line.long 0x0 "DBFSCTRLBCAM0A,Fusa CAM Contorol Register 0 for AXI Domain" bitfld.long 0x0 0. "bcijtreq,Error injection for ECC of RMW. When this bit is asserted " "0,1" line.long 0x4 "DBFSCTRLBCAM1A,Fusa CAM Contorol Register 1 for AXI Domain" bitfld.long 0x4 0. "bcijtaddr,Enable of Error injection mode. If this bit is asserted error injection request is generated." "0,1" group.long 0x7510++0x1F line.long 0x0 "DBFSMNDEA0LA,Fusa Monitor Nomem Error Address LSBside Register 0 for AXI Domain" hexmask.long 0x0 0.--31. 1. "mndea0la,Nomem error (decode error) address LSB bits of dbsccore0" line.long 0x4 "DBFSMNDEA0HA,Fusa Monitor Nomem Error Address MSBside Register 0 for AXI Domain" hexmask.long.byte 0x4 0.--7. 1. "mndea0ha,Nomem error (decode error) address MSB bits of dbsccore0" line.long 0x8 "DBFSMNDESID0A,Fusa Monitor Nomem Error SrcID Register 0 for AXI Domain" hexmask.long.byte 0x8 0.--7. 1. "mndesid0a,Nomem error (decode error) source ID of dbsccore0" line.long 0xC "DBFSMNEDCSID0A,Fusa Monitor EDC Error SrcID Register 0 for AXI Domain" hexmask.long.byte 0xC 16.--23. 1. "mnedcsidwx0a,EDC error source ID for W channel of dbsccore0" hexmask.long.byte 0xC 8.--15. 1. "mnedcsidaw0a,EDC error source ID for AW channel of dbsccore0" newline hexmask.long.byte 0xC 0.--7. 1. "mnedcsidar0a,EDC error source ID for AR channel of dbsccore0" line.long 0x10 "DBFSMNDEA1LA,Fusa Monitor Nomem Error Address LSBside Register 1 for AXI Domain" hexmask.long 0x10 0.--31. 1. "mndea1la,Nomem error (decode error) address LSB bits of dbsccore1" line.long 0x14 "DBFSMNDEA1HA,Fusa Monitor Nomem Error Address MSBside Register 1 for AXI Domain" hexmask.long.byte 0x14 0.--7. 1. "mndea1ha,Nomem error (decode error) address MSB bits of dbsccore1" line.long 0x18 "DBFSMNDESID1A,Fusa Monitor Nomem Error SrcID Register 1 for AXI Domain" hexmask.long.byte 0x18 0.--7. 1. "mndesid1a,Nomem error (decode error) source ID of dbsccore1" line.long 0x1C "DBFSMNEDCSID1A,Fusa Monitor EDC Error SrcID Register 1 for AXI Domain" hexmask.long.byte 0x1C 16.--23. 1. "mnedcsidwx1a,EDC error source ID for W channel of dbsccore1" hexmask.long.byte 0x1C 8.--15. 1. "mnedcsidaw1a,EDC error source ID for AW channel of dbsccore1" newline hexmask.long.byte 0x1C 0.--7. 1. "mnedcsidar1a,EDC error source ID for AR channel of dbsccore1" group.long 0x7600++0x7 line.long 0x0 "DBFSCTRL00A,Fusa Control Register 0 for AXI Domain" bitfld.long 0x0 0. "srainidis,System-RAM initialization disable." "0,1" line.long 0x4 "DBFSCTRL01A,Fusa Control Register 1 for AXI Domain" bitfld.long 0x4 1. "ddrinistart1,DDR initialization start trigger for dbsccore1 (1-shot pulse clear right after asserting)" "0,1" bitfld.long 0x4 0. "ddrinistart0,DDR initialization start trigger for dbsccore0 (1-shot pulse clear right after asserting)" "0,1" group.long 0x7640++0xF line.long 0x0 "DBFSCONF00A,Fusa Configuration Register 0 for AXI Domain" bitfld.long 0x0 0.--1. "ddrinirank0,DDR initialization area rank address for dbsccore 0." "0,1,2,3" line.long 0x4 "DBFSCONF01A,Fusa Configuration Register 1 for AXI Domain" hexmask.long.word 0x4 16.--31. 1. "ddriniareae0,DDR initialization area end row address for dbsccore0." hexmask.long.word 0x4 0.--15. 1. "ddriniareas0,DDR initialization area start row address for dbsccore0." line.long 0x8 "DBFSCONF02A,Fusa Configuration Register 2 for AXI Domain" bitfld.long 0x8 0.--1. "ddrinirank1,DDR initialization area rank address for dbsccore 1." "0,1,2,3" line.long 0xC "DBFSCONF03A,Fusa Configuration Register 3 for AXI Domain" hexmask.long.word 0xC 16.--31. 1. "ddriniareae1,DDR initialization area end row address for dbsccore1." hexmask.long.word 0xC 0.--15. 1. "ddriniareas1,DDR initialization area start row address for dbsccore1." group.long 0x7680++0xB line.long 0x0 "DBFSSTAT00A,Fusa Status Register 0 for AXI Domain" bitfld.long 0x0 1. "srainiend1,System-RAM initialization completion of dbsccore1" "0,1" bitfld.long 0x0 0. "srainiend0,System-RAM initialization completion of dbsccore0" "0,1" line.long 0x4 "DBFSSTAT01A,Fusa Status Register 1 for AXI Domain" bitfld.long 0x4 1. "ddriniend1,DRAM initialization completion of dbsccore1" "0,1" bitfld.long 0x4 0. "ddriniend0,DRAM initialization completion of dbsccore0" "0,1" line.long 0x8 "DBFSSTAT02A,Fusa Status Register 2 for AXI Domain" bitfld.long 0x8 1. "bceccempty1,Status register for dbsccore1. mean that cache doesn't have dirty entry of ECC target." "0,1" bitfld.long 0x8 0. "bceccempty0,Status register for dbsccore0. mean that cache doesn't have dirty entry of ECC target." "0,1" group.long 0x7800++0xF line.long 0x0 "DBFSINTXXX00D,Fusa Interrupt Indication Register 0 for DFI Domain" bitfld.long 0x0 6. "intodaswxd,OrderID error in AXI64 Wch clk_axi side Interrupt indication" "0,1" bitfld.long 0x0 5. "intodasawd,OrderID error in AXI64 AWch clk_axi side Interrupt indication" "0,1" newline bitfld.long 0x0 4. "intodasard,OrderID error in AXI64 ARch clk_axi side Interrupt indication" "0,1" bitfld.long 0x0 2. "intdxaswxd,EDC error in AXSM W Ch clk_axi domain Interrupt indication" "0,1" newline bitfld.long 0x0 1. "intdxasawd,EDC error in AXSM AW Ch clk_axi domain Interrupt indication" "0,1" bitfld.long 0x0 0. "intdxasard,EDC error in AXSM AR Ch clk_axi domain Interrupt indication" "0,1" line.long 0x4 "DBFSINTXXX01D,Fusa Interrupt Indication Register 1 for DFI Domain" bitfld.long 0x4 31. "intexdcld1d,Comparator error of DCLS group dbs1 interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 30. "intpxpyrif1d,Parity error for PHY-Register I F (rdata) for memory channel1" "0,1" newline bitfld.long 0x4 25. "intoddvawr1d,OrderID error of isbus async write ch. interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 24. "intoddvacq1d,OrderID error of isbus async address (command queue) ch. interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x4 23. "intdxdvawr1d,EDC error of isbus async write ch. interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 22. "intdxdvacq1d,EDC error of isbus async address (command queue) ch. interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x4 21. "intoddvphy1d,OrderID error in DFI DDR PHY interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 20. "intoddvdbs1d,OrderID error in DFI DBSC interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x4 19. "intdxdvphy1d,EDC error in DFI DDR PHY interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 18. "intdxdvdbs1d,EDC error in DFI DBSC interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x4 17. "intepdvphy1d,POST error in ddrf interrupt indication for memory channel 1" "0,1" bitfld.long 0x4 16. "intepdvdbs1d,POST error in DBSC domain interrupt indication for memory channel 1" "0,1" newline bitfld.long 0x4 15. "intexdcld0d,Comparator error of DCLS group dbs0 interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 14. "intpxpyrif0d,Parity error for PHY-Register I F (rdata) for memory channel 0" "0,1" newline bitfld.long 0x4 9. "intoddvawr0d,OrderID error of isbus async write ch. interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 8. "intoddvacq0d,OrderID error of isbus async address (command queue) ch. interrupt indication for memory channel 0" "0,1" newline bitfld.long 0x4 7. "intdxdvawr0d,EDC error of isbus async write ch. interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 6. "intdxdvacq0d,EDC error of isbus async address (command queue) ch. interrupt indication for memory channel 0" "0,1" newline bitfld.long 0x4 5. "intoddvphy0d,OrderID error in DFI DDR PHY interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 4. "intoddvdbs0d,OrderID error in DFI DBSC interrupt indication for memory channel 0" "0,1" newline bitfld.long 0x4 3. "intdxdvphy0d,EDC error in DFI DDR PHY interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 2. "intdxdvdbs0d,EDC error in DFI DBSC interrupt indication for memory channel 0" "0,1" newline bitfld.long 0x4 1. "intepdvphy0d,POST error in ddrf interrupt indication for memory channel 0" "0,1" bitfld.long 0x4 0. "intepdvdbs0d,POST error in DBSC domain interrupt indication for memory channel 0" "0,1" line.long 0x8 "DBFSINTXXX02D,Fusa Interrupt Indication Register 2 for DFI Domain" bitfld.long 0x8 31. "intexdcld3d,Comparator error of DCLS group dbs3 interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 30. "intpxpyrif3d,Parity error for PHY-Register I F (rdata) for memory channel3" "0,1" newline bitfld.long 0x8 25. "intoddvawr3d,OrderID error of isbus async write ch. interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 24. "intoddvacq3d,OrderID error of isbus async address (command queue) ch. interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x8 23. "intdxdvawr3d,EDC error of isbus async write ch. interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 22. "intdxdvacq3d,EDC error of isbus async address (command queue) ch. interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x8 21. "intoddvphy3d,OrderID error in DFI DDR PHY interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 20. "intoddvdbs3d,OrderID error in DFI DBSC interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x8 19. "intdxdvphy3d,EDC error in DFI DDR PHY interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 18. "intdxdvdbs3d,EDC error in DFI DBSC interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x8 17. "intepdvphy3d,POST error in ddrf interrupt indication for memory channel 3" "0,1" bitfld.long 0x8 16. "intepdvdbs3d,POST error in DBSC domain interrupt indication for memory channel 3" "0,1" newline bitfld.long 0x8 15. "intexdcld2d,Comparator error of DCLS group dbs2 interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 14. "intpxpyrif2d,Parity error for PHY-Register I F (rdata) for memory channel2" "0,1" newline bitfld.long 0x8 9. "intoddvawr2d,OrderID error of isbus async write ch. interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 8. "intoddvacq2d,OrderID error of isbus async address (command queue) ch. interrupt indication for memory channel 2" "0,1" newline bitfld.long 0x8 7. "intdxdvawr2d,EDC error of isbus async write ch. interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 6. "intdxdvacq2d,EDC error of isbus async address (command queue) ch. interrupt indication for memory channel 2" "0,1" newline bitfld.long 0x8 5. "intoddvphy2d,OrderID error in DFI DDR PHY interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 4. "intoddvdbs2d,OrderID error in DFI DBSC interrupt indication for memory channel 2" "0,1" newline bitfld.long 0x8 3. "intdxdvphy2d,EDC error in DFI DDR PHY interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 2. "intdxdvdbs2d,EDC error in DFI DBSC interrupt indication for memory channel 2" "0,1" newline bitfld.long 0x8 1. "intepdvphy2d,POST error in ddrf interrupt indication for memory channel 2" "0,1" bitfld.long 0x8 0. "intepdvdbs2d,POST error in DBSC domain interrupt indication for memory channel 2" "0,1" line.long 0xC "DBFSINTXXX03D,Fusa Interrupt Indication Register 3 for DFI Domain" hexmask.long.word 0xC 0.--15. 1. "intxxasynsbd,Async sideband errors in dbs domain" group.long 0x7840++0x3 line.long 0x0 "DBFSINTCLR00D,Fusa Interrupt Clear Register for DFI Domain" bitfld.long 0x0 0. "icldclsd,Clear safety error interrupt signal (level) for clk_dbsc domain" "0,1" group.long 0x7880++0xF line.long 0x0 "DBFSINTENB00D,Fusa Interrupt Enable Register 0 for DFI Domain" bitfld.long 0x0 6. "ienodaswxd,OrderID error in AXI64 Wch clk_axi side interrupt enable" "0,1" bitfld.long 0x0 5. "ienodasawd,OrderID error in AXI64 AWch clk_axi side interrupt enable" "0,1" newline bitfld.long 0x0 4. "ienodasard,OrderID error in AXI64 ARch clk_axi side interrupt enable" "0,1" bitfld.long 0x0 2. "iendxaswxd,EDC error in AXSM W Ch clk_axi domain interrupt enable" "0,1" newline bitfld.long 0x0 1. "iendxasawd,EDC error in AXSM AW Ch clk_axi domain interrupt enable" "0,1" bitfld.long 0x0 0. "iendxasard,EDC error in AXSM AR Ch clk_axi domain interrupt enable" "0,1" line.long 0x4 "DBFSINTENB01D,Fusa Interrupt Enable Register 1 for DFI Domain" bitfld.long 0x4 31. "ienexdcld1d,Comparator error of DCLS group dbs1 interrupt enable" "0,1" bitfld.long 0x4 30. "ienpxpyrif1d,Parity error for PHY-Register I F (rdata) for memory channel1" "0,1" newline bitfld.long 0x4 25. "ienoddvawr1d,OrderID error of isbus async write ch. interrupt enable for memory channel 1" "0,1" bitfld.long 0x4 24. "ienoddvacq1d,OrderID error of isbus async address (command queue) ch. interrupt enable for memory channel 1" "0,1" newline bitfld.long 0x4 23. "iendxdvawr1d,EDC error of isbus async write ch. interrupt enable for memory channel 1" "0,1" bitfld.long 0x4 22. "iendxdvacq1d,EDC error of isbus async address (command queue) ch. interrupt enable for memory channel 1" "0,1" newline bitfld.long 0x4 21. "ienoddvphy1d,OrderID error in DFI DDR PHY interrupt enable bit for memory channel 1" "0,1" bitfld.long 0x4 20. "ienoddvdbs1d,OrderID error in DFI DBSC interrupt enable bit for memory channel 1" "0,1" newline bitfld.long 0x4 19. "iendxdvphy1d,EDC error in DFI DDR PHY interrupt enable bit for memory channel 1" "0,1" bitfld.long 0x4 18. "iendxdvdbs1d,EDC error in DFI DBSC interrupt enable bit for memory channel 1" "0,1" newline bitfld.long 0x4 17. "ienepdvphy1d,POST error in ddrf interrupt enable bit for memory channel 1" "0,1" bitfld.long 0x4 16. "ienepdvdbs1d,POST error in DBSC domain interrupt enable bit for memory channel 1" "0,1" newline bitfld.long 0x4 15. "ienexdcld0d,Comparator error of DCLS group dbs0 interrupt enable" "0,1" bitfld.long 0x4 14. "ienpxpyrif0d,Parity error for PHY-Register I F (rdata) for memory channel0" "0,1" newline bitfld.long 0x4 9. "ienoddvawr0d,OrderID error of isbus async write ch. interrupt enable for memory channel 0" "0,1" bitfld.long 0x4 8. "ienoddvacq0d,OrderID error of isbus async address (command queue) ch. interrupt enable for memory channel 0" "0,1" newline bitfld.long 0x4 7. "iendxdvawr0d,EDC error of isbus async write ch. interrupt enable for memory channel 0" "0,1" bitfld.long 0x4 6. "iendxdvacq0d,EDC error of isbus async address (command queue) ch. interrupt enable for memory channel 0" "0,1" newline bitfld.long 0x4 5. "ienoddvphy0d,OrderID error in DFI DDR PHY interrupt enable bit for memory channel 0" "0,1" bitfld.long 0x4 4. "ienoddvdbs0d,OrderID error in DFI DBSC interrupt enable bit for memory channel 0" "0,1" newline bitfld.long 0x4 3. "iendxdvphy0d,EDC error in DFI DDR PHY interrupt enable bit for memory channel 0" "0,1" bitfld.long 0x4 2. "iendxdvdbs0d,EDC error in DFI DBSC interrupt enable bit for memory channel 0" "0,1" newline bitfld.long 0x4 1. "ienepdvphy0d,POST error in ddrf interrupt enable bit for memory channel 0" "0,1" bitfld.long 0x4 0. "ienepdvdbs0d,POST error in DBSC domain interrupt enable bit for memory channel 0" "0,1" line.long 0x8 "DBFSINTENB02D,Fusa Interrupt Enable Register 2 for DFI Domain" bitfld.long 0x8 31. "ienexdcld3d,Comparator error of DCLS group dbs3 interrupt enable" "0,1" bitfld.long 0x8 30. "ienpxpyrif3d,Parity error for PHY-Register I F (rdata) for memory channel3" "0,1" newline bitfld.long 0x8 25. "ienoddvawr3d,OrderID error of isbus async write ch. interrupt enable for memory channel 3" "0,1" bitfld.long 0x8 24. "ienoddvacq3d,OrderID error of isbus async address (command queue) ch. interrupt enable for memory channel 3" "0,1" newline bitfld.long 0x8 23. "iendxdvawr3d,EDC error of isbus async write ch. interrupt enable for memory channel 3" "0,1" bitfld.long 0x8 22. "iendxdvacq3d,EDC error of isbus async address (command queue) ch. interrupt enable for memory channel 3" "0,1" newline bitfld.long 0x8 21. "ienoddvphy3d,OrderID error in DFI DDR PHY interrupt enable bit for memory channel 3" "0,1" bitfld.long 0x8 20. "ienoddvdbs3d,OrderID error in DFI DBSC interrupt enable bit for memory channel 3" "0,1" newline bitfld.long 0x8 19. "iendxdvphy3d,EDC error in DFI DDR PHY interrupt enable bit for memory channel 3" "0,1" bitfld.long 0x8 18. "iendxdvdbs3d,EDC error in DFI DBSC interrupt enable bit for memory channel 3" "0,1" newline bitfld.long 0x8 17. "ienepdvphy3d,POST error in ddrf interrupt enable bit for memory channel 3" "0,1" bitfld.long 0x8 16. "ienepdvdbs3d,POST error in DBSC domain interrupt enable bit for memory channel 3" "0,1" newline bitfld.long 0x8 15. "ienexdcld2d,Comparator error of DCLS group dbs2 interrupt enable" "0,1" bitfld.long 0x8 14. "ienpxpyrif2d,Parity error for PHY-Register I F (rdata) for memory channel2" "0,1" newline bitfld.long 0x8 9. "ienoddvawr2d,OrderID error of isbus async write ch. interrupt enable for memory channel 2" "0,1" bitfld.long 0x8 8. "ienoddvacq2d,OrderID error of isbus async address (command queue) ch. interrupt enable for memory channel 2" "0,1" newline bitfld.long 0x8 7. "iendxdvawr2d,EDC error of isbus async write ch. interrupt enable for memory channel 2" "0,1" bitfld.long 0x8 6. "iendxdvacq2d,EDC error of isbus async address (command queue) ch. interrupt enable for memory channel 2" "0,1" newline bitfld.long 0x8 5. "ienoddvphy2d,OrderID error in DFI DDR PHY interrupt enable bit for memory channel 2" "0,1" bitfld.long 0x8 4. "ienoddvdbs2d,OrderID error in DFI DBSC interrupt enable bit for memory channel 2" "0,1" newline bitfld.long 0x8 3. "iendxdvphy2d,EDC error in DFI DDR PHY interrupt enable bit for memory channel 2" "0,1" bitfld.long 0x8 2. "iendxdvdbs2d,EDC error in DFI DBSC interrupt enable bit for memory channel 2" "0,1" newline bitfld.long 0x8 1. "ienepdvphy2d,POST error in ddrf interrupt enable bit for memory channel 2" "0,1" bitfld.long 0x8 0. "ienepdvdbs2d,POST error in DBSC domain interrupt enable bit for memory channel 2" "0,1" line.long 0xC "DBFSINTENB03D,Fusa Interrupt Enable Register 3 for DFI Domain" hexmask.long.word 0xC 0.--15. 1. "ienxxasynsbd,Async sideband errors interrupt enable in dbs domain" group.long 0x7900++0xF line.long 0x0 "DBFSINJECT00D,Fusa Injection Mode Register 0 for DFI Domain" bitfld.long 0x0 6. "ijtodaswxd,OrderID error in AXI64 Wch clk_axi side interrupt injection mode" "0,1" bitfld.long 0x0 5. "ijtodasawd,OrderID error in AXI64 AWch clk_axi side interrupt injection mode" "0,1" newline bitfld.long 0x0 4. "ijtodasard,OrderID error in AXI64 ARch clk_axi side interrupt injection mode" "0,1" bitfld.long 0x0 2. "ijtdxaswxd,EDC error in AXSM W Ch clk_axi domain interrupt injection mode" "0,1" newline bitfld.long 0x0 1. "ijtdxasawd,EDC error in AXSM AW Ch clk_axi domain interrupt injection mode" "0,1" bitfld.long 0x0 0. "ijtdxasard,EDC error in AXSM AR Ch clk_axi domain interrupt injection mode" "0,1" line.long 0x4 "DBFSINJECT01D,Fusa Injection Mode Register 1 for DFI Domain" bitfld.long 0x4 31. "ijtexdcld1d,Comparator error of DCLS group dbs1 interrupt injection mode" "0,1" bitfld.long 0x4 30. "ijtpxpyrif1d,Parity error for PHY-Register I F (rdata) for memory channel 1" "0,1" newline bitfld.long 0x4 25. "ijtoddvawr1d,OrderID error of isbus async write ch. interrupt injection mode for memory channel 1" "0,1" bitfld.long 0x4 24. "ijtoddvacq1d,OrderID error of isbus async address (command queue) ch. interrupt injection mode for memory channel 1" "0,1" newline bitfld.long 0x4 23. "ijtdxdvawr1d,EDC error of isbus async write ch. interrupt injection mode for memory channel 1" "0,1" bitfld.long 0x4 22. "ijtdxdvacq1d,EDC error of isbus async address (command queue) ch. interrupt injection mode for memory channel 1" "0,1" newline bitfld.long 0x4 21. "ijtoddvphy1d,OrderID error in DFI DDR PHY interrupt injection for memory channel 1" "0,1" bitfld.long 0x4 20. "ijtoddvdbs1d,OrderID error in DFI DBSC interrupt injection for memory channel 1" "0,1" newline bitfld.long 0x4 19. "ijtdxdvphy1d,EDC error in DFI DDR PHY interrupt injection for memory channel 1" "0,1" bitfld.long 0x4 18. "ijtdxdvdbs1d,EDC error in DFI DBSC interrupt injection for memory channel 1" "0,1" newline bitfld.long 0x4 17. "ijtepdvphy1d,POST error in ddrf interrupt injection for memory channel 1" "0,1" bitfld.long 0x4 16. "ijtepdvdbs1d,POST error in DBSC domain interrupt injection for memory channel 1" "0,1" newline bitfld.long 0x4 15. "ijtexdcld0d,Comparator error of DCLS group dbs0 interrupt injection mode" "0,1" bitfld.long 0x4 14. "ijtpxpyrif0d,Parity error for PHY-Register I F (rdata) for memory channel 0" "0,1" newline bitfld.long 0x4 9. "ijtoddvawr0d,OrderID error of isbus async write ch. interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x4 8. "ijtoddvacq0d,OrderID error of isbus async address (command queue) ch. interrupt injection mode for memory channel 0" "0,1" newline bitfld.long 0x4 7. "ijtdxdvawr0d,EDC error of isbus async write ch. interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x4 6. "ijtdxdvacq0d,EDC error of isbus async address (command queue) ch. interrupt injection mode for memory channel 0" "0,1" newline bitfld.long 0x4 5. "ijtoddvphy0d,OrderID error in DFI DDR PHY interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x4 4. "ijtoddvdbs0d,OrderID error in DFI DBSC interrupt injection mode for memory channel 0" "0,1" newline bitfld.long 0x4 3. "ijtdxdvphy0d,EDC error in DFI DDR PHY interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x4 2. "ijtdxdvdbs0d,EDC error in DFI DBSC interrupt injection mode for memory channel 0" "0,1" newline bitfld.long 0x4 1. "ijtepdvphy0d,POST error in ddrf interrupt injection mode for memory channel 0" "0,1" bitfld.long 0x4 0. "ijtepdvdbs0d,POST error in DBSC domain interrupt injection mode for memory channel 0" "0,1" line.long 0x8 "DBFSINJECT02D,Fusa Injection Mode Register 2 for DFI Domain" bitfld.long 0x8 31. "ijtexdcld3d,Comparator error of DCLS group dbs3 interrupt injection mode" "0,1" bitfld.long 0x8 30. "ijtpxpyrif3d,Parity error for PHY-Register I F (rdata) for memory channel3" "0,1" newline bitfld.long 0x8 25. "ijtoddvawr3d,OrderID error of isbus async write ch. interrupt injection mode for memory channel 3" "0,1" bitfld.long 0x8 24. "ijtoddvacq3d,OrderID error of isbus async address (command queue) ch. interrupt injection mode for memory channel 3" "0,1" newline bitfld.long 0x8 23. "ijtdxdvawr3d,EDC error of isbus async write ch. interrupt injection mode for memory channel 3" "0,1" bitfld.long 0x8 22. "ijtdxdvacq3d,EDC error of isbus async address (command queue) ch. interrupt injection mode for memory channel 3" "0,1" newline bitfld.long 0x8 21. "ijtoddvphy3d,OrderID error in DFI DDR PHY interrupt injection for memory channel 3" "0,1" bitfld.long 0x8 20. "ijtoddvdbs3d,OrderID error in DFI DBSC interrupt injection for memory channel 3" "0,1" newline bitfld.long 0x8 19. "ijtdxdvphy3d,EDC error in DFI DDR PHY interrupt injection for memory channel 3" "0,1" bitfld.long 0x8 18. "ijtdxdvdbs3d,EDC error in DFI DBSC interrupt injection for memory channel 3" "0,1" newline bitfld.long 0x8 17. "ijtepdvphy3d,POST error in ddrf interrupt injection for memory channel 3" "0,1" bitfld.long 0x8 16. "ijtepdvdbs3d,POST error in DBSC domain interrupt injection for memory channel 3" "0,1" newline bitfld.long 0x8 15. "ijtexdcld2d,Comparator error of DCLS group dbs2 interrupt injection mode" "0,1" bitfld.long 0x8 14. "ijtpxpyrif2d,Parity error for PHY-Register I F (rdata) for memory channel 2" "0,1" newline bitfld.long 0x8 9. "ijtoddvawr2d,OrderID error of isbus async write ch. interrupt injection mode for memory channel 2" "0,1" bitfld.long 0x8 8. "ijtoddvacq2d,OrderID error of isbus async address (command queue) ch. interrupt injection mode for memory channel 2" "0,1" newline bitfld.long 0x8 7. "ijtdxdvawr2d,EDC error of isbus async write ch. interrupt injection mode for memory channel 2" "0,1" bitfld.long 0x8 6. "ijtdxdvacq2d,EDC error of isbus async address (command queue) ch. interrupt injection mode for memory channel 2" "0,1" newline bitfld.long 0x8 5. "ijtoddvphy2d,OrderID error in DFI DDR PHY interrupt injection for memory channel 2" "0,1" bitfld.long 0x8 4. "ijtoddvdbs2d,OrderID error in DFI DBSC interrupt injection for memory channel 2" "0,1" newline bitfld.long 0x8 3. "ijtdxdvphy2d,EDC error in DFI DDR PHY interrupt injection for memory channel 2" "0,1" bitfld.long 0x8 2. "ijtdxdvdbs2d,EDC error in DFI DBSC interrupt injection for memory channel 2" "0,1" newline bitfld.long 0x8 1. "ijtepdvphy2d,POST error in ddrf interrupt injection for memory channel 2" "0,1" bitfld.long 0x8 0. "ijtepdvdbs2d,POST error in DBSC domain interrupt injection for memory channel 2" "0,1" line.long 0xC "DBFSINJECT03D,Fusa Injection Mode Register 3 for DFI Domain" hexmask.long.word 0xC 0.--15. 1. "ijtxxasynsbd,Async sideband errors interrupt injection mode in dbs domain" group.long 0x7A00++0x23 line.long 0x0 "DBFSINTCNT00D,Fusa Interrupt Counter Register 0 for DFI Domain" hexmask.long.byte 0x0 16.--23. 1. "cntdxaswxd,EDC error in AXSM W Ch clk_axi domain interrupt counter" hexmask.long.byte 0x0 8.--15. 1. "cntdxasawd,EDC error in AXSM AW Ch clk_axi domain interrupt counter" newline hexmask.long.byte 0x0 0.--7. 1. "cntdxasard,EDC error in AXSM AR Ch clk_axi domain interrupt counter" line.long 0x4 "DBFSINTCNT01D,Fusa Interrupt Counter Register 1 for DFI Domain" hexmask.long.byte 0x4 24.--31. 1. "cntdxdvawr0d,EDC error of isbus async write ch. interrupt counter for memory channel 0" hexmask.long.byte 0x4 16.--23. 1. "cntdxdvacq0d,EDC error of isbus async address (command queue) ch. interrupt counter for memory channel 0" newline hexmask.long.byte 0x4 8.--15. 1. "cntdxdvphy0d,EDC error in DFI DDR PHY interrupt counter for memory channel 0" hexmask.long.byte 0x4 0.--7. 1. "cntdxdvdbs0d,EDC error in DFI DBSC interrupt counter for memory channel 0" line.long 0x8 "DBFSINTCNT02D,Fusa Interrupt Counter Register 2 for DFI Domain" hexmask.long.byte 0x8 0.--7. 1. "cntpxpyrif0d,Parity error interrupt counter for PHY-Register I F (rdata) for memory channel0" line.long 0xC "DBFSINTCNT03D,Fusa Interrupt Counter Register 3 for DFI Domain" hexmask.long.byte 0xC 24.--31. 1. "cntdxdvawr1d,EDC error of isbus async write ch. interrupt counter for memory channel 1" hexmask.long.byte 0xC 16.--23. 1. "cntdxdvacq1d,EDC error of isbus async address (command queue) ch. interrupt counter for memory channel 1" newline hexmask.long.byte 0xC 8.--15. 1. "cntdxdvphy1d,EDC error in DFI DDR PHY interrupt counter for memory channel 1" hexmask.long.byte 0xC 0.--7. 1. "cntdxdvdbs1d,EDC error in DFI DBSC interrupt counter for memory channel 1" line.long 0x10 "DBFSINTCNT04D,Fusa Interrupt Counter Register 4 for DFI Domain" hexmask.long.byte 0x10 0.--7. 1. "cntpxpyrif1d,Parity error interrupt counter for PHY-Register I F (rdata) for memory channel1" line.long 0x14 "DBFSINTCNT05D,Fusa Interrupt Counter Register 5 for DFI Domain" hexmask.long.byte 0x14 24.--31. 1. "cntdxdvawr2d,EDC error of isbus async write ch. interrupt counter for memory channel 2" hexmask.long.byte 0x14 16.--23. 1. "cntdxdvacq2d,EDC error of isbus async address (command queue) ch. interrupt counter for memory channel 2" newline hexmask.long.byte 0x14 8.--15. 1. "cntdxdvphy2d,EDC error in DFI DDR PHY interrupt counter for memory channel 2" hexmask.long.byte 0x14 0.--7. 1. "cntdxdvdbs2d,EDC error in DFI DBSC interrupt counter for memory channel 2" line.long 0x18 "DBFSINTCNT06D,Fusa Interrupt Counter Register 6 for DFI Domain" hexmask.long.byte 0x18 0.--7. 1. "cntpxpyrif2d,Parity error interrupt counter for PHY-Register I F (rdata) for memory channel2" line.long 0x1C "DBFSINTCNT07D,Fusa Interrupt Counter Register 7 for DFI Domain" hexmask.long.byte 0x1C 24.--31. 1. "cntdxdvawr3d,EDC error of isbus async write ch. interrupt counter for memory channel 3" hexmask.long.byte 0x1C 16.--23. 1. "cntdxdvacq3d,EDC error of isbus async address (command queue) ch. interrupt counter for memory channel 3" newline hexmask.long.byte 0x1C 8.--15. 1. "cntdxdvphy3d,EDC error in DFI DDR PHY interrupt counter for memory channel 3" hexmask.long.byte 0x1C 0.--7. 1. "cntdxdvdbs3d,EDC error in DFI DBSC interrupt counter for memory channel 3" line.long 0x20 "DBFSINTCNT08D,Fusa Interrupt Counter Register 8 for DFI Domain" hexmask.long.byte 0x20 0.--7. 1. "cntpxpyrif3d,Parity error interrupt counter for PHY-Register I F (rdata) for memory channel3" group.long 0x7C00++0x3 line.long 0x0 "DBFSCONFDBS0,Fusa Configuration Register 0 for DFI Domain" bitfld.long 0x0 0. "protendbs,Enable of Protection between dbsc and DDR PHY. When this bit is set to 1 starts checking EDC and OrderID counter." "0,1" group.long 0x7C80++0x3 line.long 0x0 "DBFSCTRLDBS0,Fusa Control Register 0 for DFI Domain" bitfld.long 0x0 0. "postendbs,Start POST for asynchronous bridge in ddrf. When this bit is asserted this bit is cleared to 0 at next cycle autmatically." "0,1" tree.end tree.end tree "Domain[1]:addressBlock" base ad:0xE6160000 tree.end tree "Domain[2]:addressBlock" base ad:0xE6160000 tree.end tree "Domain[3]:addressBlock" base ad:0xE6160000 tree.end tree "ECM" base ad:0xE6250000 group.long 0xB8++0x27 line.long 0x0 "ECMDYNFREQSELR,ECMDYNFREQSELR" hexmask.long.byte 0x0 0.--3. 1. "FRQSL,Frequency select bit for ERROROUT_N in dynamic mode" line.long 0x4 "ECMPSSTATCTLRM,ECMPSSTATCTLRM" bitfld.long 0x4 0. "EOR,Error output control enable" "0: keep initial value of the error output status..,1: error output enable" line.long 0x8 "ECMPSSTATCTLR0[0],This register decides the group of the port safe state to each error signal." bitfld.long 0x8 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0xC "ECMPSSTATCTLR0[1],This register decides the group of the port safe state to each error signal." bitfld.long 0xC 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x10 "ECMPSSTATCTLR0[2],This register decides the group of the port safe state to each error signal." bitfld.long 0x10 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x10 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x14 "ECMPSSTATCTLR0[3],This register decides the group of the port safe state to each error signal." bitfld.long 0x14 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x14 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x18 "ECMPSSTATCTLR0[4],This register decides the group of the port safe state to each error signal." bitfld.long 0x18 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x18 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x1C "ECMPSSTATCTLR0[5],This register decides the group of the port safe state to each error signal." bitfld.long 0x1C 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x1C 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x20 "ECMPSSTATCTLR0[6],This register decides the group of the port safe state to each error signal." bitfld.long 0x20 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x20 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x24 "ECMPSSTATCTLR0[7],This register decides the group of the port safe state to each error signal." bitfld.long 0x24 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" rgroup.long 0x168++0x7 line.long 0x0 "ECMDCLSERMON00R,ECMDCLSERMON00R" hexmask.long 0x0 0.--31. 1. "DCLS_DUPERR,DCLS duplication Error" line.long 0x4 "ECMDCLSERMON01R,ECMDCLSERMON01R" hexmask.long.word 0x4 0.--8. 1. "DCLS_DUPERR,DCLS duplication Error" group.long 0x170++0x7 line.long 0x0 "ECMEDCERRSIDPADDR,Error SID register for PADDR" bitfld.long 0x0 31. "CLR,Clear for SRC_ID captured at EDC library" "0: No effect,1: Clear SRC ID" newline hexmask.long.byte 0x0 0.--7. 1. "SRC_ID,SRC_ID after EDC error detection" line.long 0x4 "ECMEDCERRSIDPWDATAR,Error SID register for PWDATA" bitfld.long 0x4 31. "CLR,Clear for SRC_ID captured at EDC library" "0: No effect,1: Clear SRC ID" newline hexmask.long.byte 0x4 0.--7. 1. "SRC_ID,SRC_ID after EDC error detection" group.long 0x200++0x1B line.long 0x0 "ECMERRCTLR0,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x0 0.--31. 1. "Enable,Error detection enable." line.long 0x4 "ECMERRCTLR1,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x4 0.--31. 1. "Enable,Error detection enable." line.long 0x8 "ECMERRCTLR2,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x8 0.--31. 1. "Enable,Error detection enable." line.long 0xC "ECMERRCTLR3,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xC 0.--31. 1. "Enable,Error detection enable." line.long 0x10 "ECMERRCTLR4,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x10 0.--31. 1. "Enable,Error detection enable." line.long 0x14 "ECMERRCTLR5,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x14 0.--31. 1. "Enable,Error detection enable." line.long 0x18 "ECMERRCTLR6,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x18 0.--31. 1. "Enable,Error detection enable." group.long 0x240++0x37 line.long 0x0 "ECMERRSTSR0,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x0 0.--31. 1. "Status,Error detection status." line.long 0x4 "ECMERRSTSR1,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x4 0.--31. 1. "Status,Error detection status." line.long 0x8 "ECMERRSTSR2,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x8 0.--31. 1. "Status,Error detection status." line.long 0xC "ECMERRSTSR3,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xC 0.--31. 1. "Status,Error detection status." line.long 0x10 "ECMERRSTSR4,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x10 0.--31. 1. "Status,Error detection status." line.long 0x14 "ECMERRSTSR5,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x14 0.--31. 1. "Status,Error detection status." line.long 0x18 "ECMERRSTSR6,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x18 0.--31. 1. "Status,Error detection status." line.long 0x1C "ECMERRTGTR6,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x1C 0.--31. 1. "Target,Error detection target." line.long 0x20 "ECMERRCTLR7,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x20 0.--31. 1. "Enable,Error detection enable." line.long 0x24 "ECMERRSTSR7,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x24 0.--31. 1. "Status,Error detection status." line.long 0x28 "ECMERRTGTR7,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x28 0.--31. 1. "Target,Error detection target." line.long 0x2C "ECMERRCTLR8,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x2C 0.--31. 1. "Enable,Error detection enable." line.long 0x30 "ECMERRSTSR8,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x30 0.--31. 1. "Status,Error detection status." line.long 0x34 "ECMERRTGTR8,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x34 0.--31. 1. "Target,Error detection target." group.long 0x280++0x17 line.long 0x0 "ECMERRTGTR0,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x0 0.--31. 1. "Target,Error detection target." line.long 0x4 "ECMERRTGTR1,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x4 0.--31. 1. "Target,Error detection target." line.long 0x8 "ECMERRTGTR2,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x8 0.--31. 1. "Target,Error detection target." line.long 0xC "ECMERRTGTR3,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xC 0.--31. 1. "Target,Error detection target." line.long 0x10 "ECMERRTGTR4,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x10 0.--31. 1. "Target,Error detection target." line.long 0x14 "ECMERRTGTR5,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x14 0.--31. 1. "Target,Error detection target." group.long 0x2AC++0x3 line.long 0x0 "ECMCMPERRINJR,ECMCMPERRINJR" bitfld.long 0x0 0. "ERRINJ,DCLS Comparator error injection" "0: No error injection,1: Error injection to the comparator of DCLS" group.long 0x300++0x3 line.long 0x0 "SAFGPRR,SAFGPRR" hexmask.long 0x0 0.--31. 1. "GR0,These bits have no effect on operation of this LSI." wgroup.long 0x304++0x7 line.long 0x0 "SAFSTERRENR,SAFSTERRENR" hexmask.long 0x0 0.--31. 1. "SET,B’1: Set Error Insertion." line.long 0x4 "SAFCLERRENR,SAFCLERRENR" hexmask.long 0x4 0.--31. 1. "CLR,Enable Error Insertion Set." rgroup.long 0x30C++0x3 line.long 0x0 "SAFSTSR,SAFSTSR" hexmask.long 0x0 0.--31. 1. "STS,Error Insertion Enable Status." group.long 0x310++0x3 line.long 0x0 "SAFCTLR,SAFCTLR is used to enable debug function." bitfld.long 0x0 31. "DBGEN,Error Insertion Enable Status" "0: Disable debug function,1: Enable debug function" newline hexmask.long.byte 0x0 0.--4. 1. "REGSEL,Select Error status register which ECM update error status." group.long 0x460++0x1F line.long 0x0 "ECMERRCNTREG[32],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x0 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x0 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x0 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x4 "ECMERRCNTREG[33],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x4 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x4 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x4 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x8 "ECMERRCNTREG[34],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x8 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x8 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x8 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0xC "ECMERRCNTREG[35],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0xC 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0xC 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0xC 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x10 "ECMERRCNTREG[36],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x10 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x10 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x10 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x14 "ECMERRCNTREG[37],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x14 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x14 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x14 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x18 "ECMERRCNTREG[38],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x18 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x18 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x18 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x1C "ECMERRCNTREG[39],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x1C 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x1C 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x1C 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" group.long 0x500++0x7 line.long 0x0 "ECMERRCNTREG[40],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x0 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x0 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x0 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x4 "ECMERRCNTREG[41],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x4 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x4 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x4 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" group.long 0x540++0x7 line.long 0x0 "ECMERRCNTREG[42],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x0 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x0 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x0 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x4 "ECMERRCNTREG[43],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x4 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x4 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x4 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" group.long 0x5F0++0x7 line.long 0x0 "ECMECCTLR,This register is used for the security protection of the ECM registers" bitfld.long 0x0 0. "SECEN,1: Security No Protection" "0: Security Protection,1: Security No Protection" line.long 0x4 "ECMECSTSR,This register indicates the occurrence of the security error" bitfld.long 0x4 0. "SECSTS,1: Security Error Occur" "0: No Error,1: Security Error Occur" rgroup.long 0x5F8++0x7 line.long 0x0 "ECMECMIDR,This register holds the Master ID of the request which security error detected" hexmask.long 0x0 0.--31. 1. "MID,MID" line.long 0x4 "ECMECSADR,This register holds the request address which security error detected" hexmask.long 0x4 0.--31. 1. "SADR,SADR" group.long 0x700++0x1A7 line.long 0x0 "ECMERRRSTR0,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x0 0.--31. 1. "ResetEnable,Reset enable" line.long 0x4 "ECMERRRSTR1,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x4 0.--31. 1. "ResetEnable,Reset enable" line.long 0x8 "ECMERRRSTR2,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x8 0.--31. 1. "ResetEnable,Reset enable" line.long 0xC "ECMERRRSTR3,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0xC 0.--31. 1. "ResetEnable,Reset enable" line.long 0x10 "ECMERRRSTR4,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x10 0.--31. 1. "ResetEnable,Reset enable" line.long 0x14 "ECMERRRSTR5,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x14 0.--31. 1. "ResetEnable,Reset enable" line.long 0x18 "ECMERRRSTR6,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x18 0.--31. 1. "ResetEnable,Reset enable" line.long 0x1C "ECMERRRSTR7,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x1C 0.--31. 1. "ResetEnable,Reset enable" line.long 0x20 "ECMERRRSTR8,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x20 0.--31. 1. "ResetEnable,Reset enable" line.long 0x24 "ECMPSSTATCTLR0[8],This register decides the group of the port safe state to each error signal." bitfld.long 0x24 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x24 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x28 "ECMPSSTATCTLR0[9],This register decides the group of the port safe state to each error signal." bitfld.long 0x28 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x28 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x2C "ECMPSSTATCTLR0[10],This register decides the group of the port safe state to each error signal." bitfld.long 0x2C 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x2C 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x30 "ECMPSSTATCTLR0[11],This register decides the group of the port safe state to each error signal." bitfld.long 0x30 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x30 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x34 "ECMPSSTATCTLR0[12],This register decides the group of the port safe state to each error signal." bitfld.long 0x34 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x34 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x38 "ECMPSSTATCTLR0[13],This register decides the group of the port safe state to each error signal." bitfld.long 0x38 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x38 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x3C "ECMPSSTATCTLR0[14],This register decides the group of the port safe state to each error signal." bitfld.long 0x3C 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x3C 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x40 "ECMPSSTATCTLR0[15],This register decides the group of the port safe state to each error signal." bitfld.long 0x40 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x40 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x44 "ECMPSSTATCTLR0[16],This register decides the group of the port safe state to each error signal." bitfld.long 0x44 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x44 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x48 "ECMPSSTATCTLR0[17],This register decides the group of the port safe state to each error signal." bitfld.long 0x48 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x48 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x4C "ECMPSSTATCTLR0[18],This register decides the group of the port safe state to each error signal." bitfld.long 0x4C 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x4C 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x50 "ECMPSSTATCTLR0[19],This register decides the group of the port safe state to each error signal." bitfld.long 0x50 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x50 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x54 "ECMPSSTATCTLR0[20],This register decides the group of the port safe state to each error signal." bitfld.long 0x54 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x54 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x58 "ECMPSSTATCTLR0[21],This register decides the group of the port safe state to each error signal." bitfld.long 0x58 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x58 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x5C "ECMPSSTATCTLR0[22],This register decides the group of the port safe state to each error signal." bitfld.long 0x5C 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x5C 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x60 "ECMPSSTATCTLR0[23],This register decides the group of the port safe state to each error signal." bitfld.long 0x60 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x60 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x64 "ECMPSSTATCTLR0[24],This register decides the group of the port safe state to each error signal." bitfld.long 0x64 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x64 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x68 "ECMPSSTATCTLR0[25],This register decides the group of the port safe state to each error signal." bitfld.long 0x68 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x68 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x6C "ECMPSSTATCTLR0[26],This register decides the group of the port safe state to each error signal." bitfld.long 0x6C 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x6C 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x70 "ECMPSSTATCTLR0[27],This register decides the group of the port safe state to each error signal." bitfld.long 0x70 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x70 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x74 "ECMPSSTATCTLR0[28],This register decides the group of the port safe state to each error signal." bitfld.long 0x74 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x74 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x78 "ECMPSSTATCTLR0[29],This register decides the group of the port safe state to each error signal." bitfld.long 0x78 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x78 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x7C "ECMPSSTATCTLR0[30],This register decides the group of the port safe state to each error signal." bitfld.long 0x7C 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x7C 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x80 "ECMPSSTATCTLR0[31],This register decides the group of the port safe state to each error signal." bitfld.long 0x80 30.--31. "PSSG15,Post safe state group of error factor 15 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 28.--29. "PSSG14,Post safe state group of error factor 14 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 26.--27. "PSSG13,Post safe state group of error factor 13 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 24.--25. "PSSG12,Post safe state group of error factor 12 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 22.--23. "PSSG11,Post safe state group of error factor 11 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 20.--21. "PSSG10,Post safe state group of error factor 10 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 18.--19. "PSSG9,Post safe state group of error factor 9 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 16.--17. "PSSG8,Post safe state group of error factor 8 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 14.--15. "PSSG7,Post safe state group of error factor 7 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 12.--13. "PSSG6,Post safe state group of error factor 6 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 10.--11. "PSSG5,Post safe state group of error factor 5 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 8.--9. "PSSG4,Post safe state group of error factor 4 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 6.--7. "PSSG3,Post safe state group of error factor 3 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 4.--5. "PSSG2,Post safe state group of error factor 2 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 2.--3. "PSSG1,Post safe state group of error factor 1 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x80 0.--1. "PSSG0,Post safe state group of error factor 0 of MFISERRCTRLn" "0,1,2,3" line.long 0x84 "ECMPSSTATCTLR1[0],This register decides the group of the port safe state to each error signal." bitfld.long 0x84 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x84 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0x88 "ECMPSSTATCTLR1[1],This register decides the group of the port safe state to each error signal." bitfld.long 0x88 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x88 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0x8C "ECMPSSTATCTLR1[2],This register decides the group of the port safe state to each error signal." bitfld.long 0x8C 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x8C 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0x90 "ECMPSSTATCTLR1[3],This register decides the group of the port safe state to each error signal." bitfld.long 0x90 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x90 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0x94 "ECMPSSTATCTLR1[4],This register decides the group of the port safe state to each error signal." bitfld.long 0x94 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x94 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0x98 "ECMPSSTATCTLR1[5],This register decides the group of the port safe state to each error signal." bitfld.long 0x98 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x98 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0x9C "ECMPSSTATCTLR1[6],This register decides the group of the port safe state to each error signal." bitfld.long 0x9C 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x9C 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xA0 "ECMPSSTATCTLR1[7],This register decides the group of the port safe state to each error signal." bitfld.long 0xA0 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA0 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xA4 "ECMPSSTATCTLR1[8],This register decides the group of the port safe state to each error signal." bitfld.long 0xA4 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA4 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xA8 "ECMPSSTATCTLR1[9],This register decides the group of the port safe state to each error signal." bitfld.long 0xA8 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xA8 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xAC "ECMPSSTATCTLR1[10],This register decides the group of the port safe state to each error signal." bitfld.long 0xAC 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xAC 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xB0 "ECMPSSTATCTLR1[11],This register decides the group of the port safe state to each error signal." bitfld.long 0xB0 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB0 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xB4 "ECMPSSTATCTLR1[12],This register decides the group of the port safe state to each error signal." bitfld.long 0xB4 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB4 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xB8 "ECMPSSTATCTLR1[13],This register decides the group of the port safe state to each error signal." bitfld.long 0xB8 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xB8 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xBC "ECMPSSTATCTLR1[14],This register decides the group of the port safe state to each error signal." bitfld.long 0xBC 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xBC 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xC0 "ECMPSSTATCTLR1[15],This register decides the group of the port safe state to each error signal." bitfld.long 0xC0 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC0 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xC4 "ECMPSSTATCTLR1[16],This register decides the group of the port safe state to each error signal." bitfld.long 0xC4 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC4 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xC8 "ECMPSSTATCTLR1[17],This register decides the group of the port safe state to each error signal." bitfld.long 0xC8 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xC8 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xCC "ECMPSSTATCTLR1[18],This register decides the group of the port safe state to each error signal." bitfld.long 0xCC 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xCC 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xD0 "ECMPSSTATCTLR1[19],This register decides the group of the port safe state to each error signal." bitfld.long 0xD0 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD0 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xD4 "ECMPSSTATCTLR1[20],This register decides the group of the port safe state to each error signal." bitfld.long 0xD4 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD4 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xD8 "ECMPSSTATCTLR1[21],This register decides the group of the port safe state to each error signal." bitfld.long 0xD8 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xD8 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xDC "ECMPSSTATCTLR1[22],This register decides the group of the port safe state to each error signal." bitfld.long 0xDC 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xDC 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xE0 "ECMPSSTATCTLR1[23],This register decides the group of the port safe state to each error signal." bitfld.long 0xE0 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE0 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xE4 "ECMPSSTATCTLR1[24],This register decides the group of the port safe state to each error signal." bitfld.long 0xE4 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE4 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xE8 "ECMPSSTATCTLR1[25],This register decides the group of the port safe state to each error signal." bitfld.long 0xE8 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xE8 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xEC "ECMPSSTATCTLR1[26],This register decides the group of the port safe state to each error signal." bitfld.long 0xEC 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xEC 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xF0 "ECMPSSTATCTLR1[27],This register decides the group of the port safe state to each error signal." bitfld.long 0xF0 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF0 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xF4 "ECMPSSTATCTLR1[28],This register decides the group of the port safe state to each error signal." bitfld.long 0xF4 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF4 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xF8 "ECMPSSTATCTLR1[29],This register decides the group of the port safe state to each error signal." bitfld.long 0xF8 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xF8 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0xFC "ECMPSSTATCTLR1[30],This register decides the group of the port safe state to each error signal." bitfld.long 0xFC 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0xFC 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0x100 "ECMPSSTATCTLR1[31],This register decides the group of the port safe state to each error signal." bitfld.long 0x100 30.--31. "PSSG31,Post safe state group of error factor 31 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 28.--29. "PSSG30,Post safe state group of error factor 30 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 26.--27. "PSSG29,Post safe state group of error factor 29 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 24.--25. "PSSG28,Post safe state group of error factor 28 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 22.--23. "PSSG27,Post safe state group of error factor 27 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 20.--21. "PSSG26,Post safe state group of error factor 26 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 18.--19. "PSSG25,Post safe state group of error factor 25 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 16.--17. "PSSG24,Post safe state group of error factor 24 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 14.--15. "PSSG23,Post safe state group of error factor 23 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 12.--13. "PSSG22,Post safe state group of error factor 22 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 10.--11. "PSSG21,Post safe state group of error factor 21 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 8.--9. "PSSG20,Post safe state group of error factor 20 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 6.--7. "PSSG19,Post safe state group of error factor 19 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 4.--5. "PSSG18,Post safe state group of error factor 18 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 2.--3. "PSSG17,Post safe state group of error factor 17 of MFISERRCTRLn" "0,1,2,3" newline bitfld.long 0x100 0.--1. "PSSG16,Post safe state group of error factor 16 of MFISERRCTRLn" "0,1,2,3" line.long 0x104 "ECMERRCTLR9,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x104 0.--31. 1. "Enable,Error detection enable." line.long 0x108 "ECMERRCTLR10,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x108 0.--31. 1. "Enable,Error detection enable." line.long 0x10C "ECMERRCTLR11,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x10C 0.--31. 1. "Enable,Error detection enable." line.long 0x110 "ECMERRSTSR9,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x110 0.--31. 1. "Status,Error detection status." line.long 0x114 "ECMERRSTSR10,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x114 0.--31. 1. "Status,Error detection status." line.long 0x118 "ECMERRSTSR11,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x118 0.--31. 1. "Status,Error detection status." line.long 0x11C "ECMERRTGTR9,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x11C 0.--31. 1. "Target,Error detection target." line.long 0x120 "ECMERRTGTR10,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x120 0.--31. 1. "Target,Error detection target." line.long 0x124 "ECMERRTGTR11,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x124 0.--31. 1. "Target,Error detection target." line.long 0x128 "ECMERRRSTR9,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x128 0.--31. 1. "ResetEnable,Reset enable" line.long 0x12C "ECMERRRSTR10,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x12C 0.--31. 1. "ResetEnable,Reset enable" line.long 0x130 "ECMERRRSTR11,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x130 0.--31. 1. "ResetEnable,Reset enable" line.long 0x134 "ECMERRCNTREG[0],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x134 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x134 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x134 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x134 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x138 "ECMERRCNTREG[1],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x138 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x138 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x138 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x138 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x13C "ECMERRCNTREG[2],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x13C 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x13C 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x13C 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x13C 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x140 "ECMERRCNTREG[3],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x140 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x140 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x140 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x140 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x144 "ECMERRCNTREG[4],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x144 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x144 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x144 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x144 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x148 "ECMERRCNTREG[5],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x148 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x148 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x148 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x148 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x14C "ECMERRCNTREG[6],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x14C 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x14C 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x14C 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14C 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x150 "ECMERRCNTREG[7],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x150 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x150 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x150 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x150 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x154 "ECMERRCNTREG[8],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x154 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x154 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x154 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x154 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x158 "ECMERRCNTREG[9],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x158 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x158 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x158 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x158 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x15C "ECMERRCNTREG[10],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x15C 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x15C 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x15C 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x15C 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x160 "ECMERRCNTREG[11],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x160 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x160 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x160 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x160 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x164 "ECMERRCNTREG[12],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x164 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x164 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x164 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x164 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x168 "ECMERRCNTREG[13],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x168 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x168 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x168 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x168 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x16C "ECMERRCNTREG[14],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x16C 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x16C 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x16C 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x16C 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x170 "ECMERRCNTREG[15],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x170 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x170 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x170 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x170 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x174 "ECMERRCNTREG[16],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x174 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x174 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x174 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x174 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x178 "ECMERRCNTREG[17],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x178 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x178 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x178 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x178 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x17C "ECMERRCNTREG[18],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x17C 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x17C 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x17C 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x17C 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x180 "ECMERRCNTREG[19],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x180 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x180 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x180 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x180 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x184 "ECMERRCNTREG[20],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x184 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x184 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x184 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x184 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x188 "ECMERRCNTREG[21],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x188 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x188 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x188 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x188 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x18C "ECMERRCNTREG[22],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x18C 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x18C 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x18C 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18C 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x190 "ECMERRCNTREG[23],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x190 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x190 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x190 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x190 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x194 "ECMERRCNTREG[24],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x194 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x194 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x194 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x194 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x198 "ECMERRCNTREG[25],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x198 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x198 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x198 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x198 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x19C "ECMGEIIDR,ECMGEIIDR" bitfld.long 0x19C 0.--2. "SGE_ID,Software Error Interrupt ID." "0,1,2,3,4,5,6,7" line.long 0x1A0 "ECMEXTRQHLDCNTR,ECMEXTRQHLDCNTR" bitfld.long 0x1A0 31. "EN,Counter Enable" "0,1" newline hexmask.long.word 0x1A0 0.--10. 1. "CountValue,Timer count value" line.long 0x1A4 "ECMEXTRQMSKCNTR,This register is used for the mask timer control for external error request." bitfld.long 0x1A4 31. "EN,Counter Enable" "0,1" newline hexmask.long.word 0x1A4 0.--10. 1. "CountValue,Timer Count Value" rgroup.long 0x8A8++0xF line.long 0x0 "ECMEXTRQSTSR,This register indicates the status of external error request" bitfld.long 0x0 0. "STS,External Error Request status." "0,1" line.long 0x4 "ECMEXTTMHLDCNTR,This register is used to debug purpose" hexmask.long.byte 0x4 16.--23. 1. "PrescaleCountValue[,Prescale Count value" newline hexmask.long.word 0x4 0.--10. 1. "TimerCountValue,Timer Count Value" line.long 0x8 "ECMEXTTMMSKCNTR,This register is used to debug purpose" hexmask.long.byte 0x8 16.--23. 1. "PrescaleCountValue[,Prescale Count value" newline hexmask.long.word 0x8 0.--10. 1. "TimerCountValue,Timer Count Value" line.long 0xC "ECMEXTSEQMONR,This register is used to monitor the sequence state." hexmask.long.byte 0xC 0.--6. 1. "State,State" group.long 0x8B8++0x3 line.long 0x0 "ECMCMPERRSTSR,This register indicate the status of compare error of redundant logic" hexmask.long.word 0x0 0.--9. 1. "CompareErrorStatus" group.long 0x900++0x173 line.long 0x0 "ECMWPCNTR,This register is used to control write protection for all registers in ECM" hexmask.long.word 0x0 16.--31. 1. "CodeValue,Code Value(H'ACCE)" newline bitfld.long 0x0 0. "WPD,Write Protection Disable" "0,1" line.long 0x4 "ECMWACNTR,This register is used when write access for the target register is executed. Unless the target register address is written in this register. the contents of the target register cannot not be updated." hexmask.long.word 0x4 16.--31. 1. "CodeValue,Code Value(H'ACCE)" newline hexmask.long.word 0x4 0.--15. 1. "RegisterAddress,Target register address" line.long 0x8 "ECMERRCTLR12,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x8 0.--31. 1. "Enable,Error detection enable." line.long 0xC "ECMERRSTSR12,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xC 0.--31. 1. "Status,Error detection status." line.long 0x10 "ECMERRTGTR12,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x10 0.--31. 1. "Target,Error detection target." line.long 0x14 "ECMERRRSTR12,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x14 0.--31. 1. "ResetEnable,Reset enable" line.long 0x18 "ECMERRCTLR13,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x18 0.--31. 1. "Enable,Error detection enable." line.long 0x1C "ECMERRSTSR13,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x1C 0.--31. 1. "Status,Error detection status." line.long 0x20 "ECMERRTGTR13,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x20 0.--31. 1. "Target,Error detection target." line.long 0x24 "ECMERRRSTR13,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x24 0.--31. 1. "ResetEnable,Reset enable" line.long 0x28 "ECMERRCNTREG[26],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x28 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x28 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x28 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x2C "ECMERRCNTREG[27],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x2C 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x2C 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x2C 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x30 "ECMERRCNTREG[28],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x30 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x30 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x30 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x34 "ECMERRCNTREG[29],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x34 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x34 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x34 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x38 "ECMERRCNTREG[30],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x38 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x38 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x38 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x3C "ECMERRCNTREG[31],This register is used to enable counting the number of errors when 1-bit or multi-bit error of RAM ECC happened at the corresponding modules" hexmask.long.byte 0x3C 24.--28. 1. "MECN_1bit,Maximum Error Count Number(1-bit)" newline hexmask.long.byte 0x3C 16.--20. 1. "CECN_1bit,Current Error Count Number(1-bit)" newline bitfld.long 0x3C 8.--10. "MECN_mbit,Maximum Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 0.--2. "CECN_mbit,Current Error Count Number(multi-bit)" "0,1,2,3,4,5,6,7" line.long 0x40 "ECMERROUTCTLR,ECMERROUTCTLR" hexmask.long.word 0x40 16.--31. 1. "CodeValue,Code Value(H'ACCE)" newline bitfld.long 0x40 0. "EOR,Error output control enable" "0: keep initial value of the error output status..,1: error output enable" line.long 0x44 "ECMERRCTLR14,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x44 0.--31. 1. "Enable,Error detection enable." line.long 0x48 "ECMERRSTSR14,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x48 0.--31. 1. "Status,Error detection status." line.long 0x4C "ECMERRTGTR14,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x4C 0.--31. 1. "Target,Error detection target." line.long 0x50 "ECMERRRSTR14,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x50 0.--31. 1. "ResetEnable,Reset enable" line.long 0x54 "ECMERRCTLR15,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x54 0.--31. 1. "Enable,Error detection enable." line.long 0x58 "ECMERRSTSR15,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x58 0.--31. 1. "Status,Error detection status." line.long 0x5C "ECMERRTGTR15,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x5C 0.--31. 1. "Target,Error detection target." line.long 0x60 "ECMERRRSTR15,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x60 0.--31. 1. "ResetEnable,Reset enable" line.long 0x64 "ECMERRCTLR16,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x64 0.--31. 1. "Enable,Error detection enable." line.long 0x68 "ECMERRSTSR16,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x68 0.--31. 1. "Status,Error detection status." line.long 0x6C "ECMERRTGTR16,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x6C 0.--31. 1. "Target,Error detection target." line.long 0x70 "ECMERRRSTR16,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x70 0.--31. 1. "ResetEnable,Reset enable" line.long 0x74 "ECMERRCTLR17,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x74 0.--31. 1. "Enable,Error detection enable." line.long 0x78 "ECMERRSTSR17,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x78 0.--31. 1. "Status,Error detection status." line.long 0x7C "ECMERRTGTR17,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x7C 0.--31. 1. "Target,Error detection target." line.long 0x80 "ECMERRRSTR17,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x80 0.--31. 1. "ResetEnable,Reset enable" line.long 0x84 "ECMERRCTLR18,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x84 0.--31. 1. "Enable,Error detection enable." line.long 0x88 "ECMERRSTSR18,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x88 0.--31. 1. "Status,Error detection status." line.long 0x8C "ECMERRTGTR18,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x8C 0.--31. 1. "Target,Error detection target." line.long 0x90 "ECMERRRSTR18,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x90 0.--31. 1. "ResetEnable,Reset enable" line.long 0x94 "ECMERRCTLR19,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x94 0.--31. 1. "Enable,Error detection enable." line.long 0x98 "ECMERRSTSR19,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x98 0.--31. 1. "Status,Error detection status." line.long 0x9C "ECMERRTGTR19,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x9C 0.--31. 1. "Target,Error detection target." line.long 0xA0 "ECMERRRSTR19,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0xA0 0.--31. 1. "ResetEnable,Reset enable" line.long 0xA4 "ECMERRCTLR20,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xA4 0.--31. 1. "Enable,Error detection enable." line.long 0xA8 "ECMERRSTSR20,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xA8 0.--31. 1. "Status,Error detection status." line.long 0xAC "ECMERRTGTR20,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xAC 0.--31. 1. "Target,Error detection target." line.long 0xB0 "ECMERRRSTR20,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0xB0 0.--31. 1. "ResetEnable,Reset enable" line.long 0xB4 "ECMERRCTLR21,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xB4 0.--31. 1. "Enable,Error detection enable." line.long 0xB8 "ECMERRSTSR21,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xB8 0.--31. 1. "Status,Error detection status." line.long 0xBC "ECMERRTGTR21,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xBC 0.--31. 1. "Target,Error detection target." line.long 0xC0 "ECMERRRSTR21,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0xC0 0.--31. 1. "ResetEnable,Reset enable" line.long 0xC4 "ECMERRCTLR22,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xC4 0.--31. 1. "Enable,Error detection enable." line.long 0xC8 "ECMERRSTSR22,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xC8 0.--31. 1. "Status,Error detection status." line.long 0xCC "ECMERRTGTR22,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xCC 0.--31. 1. "Target,Error detection target." line.long 0xD0 "ECMERRRSTR22,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0xD0 0.--31. 1. "ResetEnable,Reset enable" line.long 0xD4 "ECMERRCTLR23,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xD4 0.--31. 1. "Enable,Error detection enable." line.long 0xD8 "ECMERRSTSR23,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xD8 0.--31. 1. "Status,Error detection status." line.long 0xDC "ECMERRTGTR23,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xDC 0.--31. 1. "Target,Error detection target." line.long 0xE0 "ECMERRRSTR23,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0xE0 0.--31. 1. "ResetEnable,Reset enable" line.long 0xE4 "ECMERRCTLR24,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xE4 0.--31. 1. "Enable,Error detection enable." line.long 0xE8 "ECMERRSTSR24,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xE8 0.--31. 1. "Status,Error detection status." line.long 0xEC "ECMERRTGTR24,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xEC 0.--31. 1. "Target,Error detection target." line.long 0xF0 "ECMERRRSTR24,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0xF0 0.--31. 1. "ResetEnable,Reset enable" line.long 0xF4 "ECMERRCTLR25,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xF4 0.--31. 1. "Enable,Error detection enable." line.long 0xF8 "ECMERRSTSR25,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xF8 0.--31. 1. "Status,Error detection status." line.long 0xFC "ECMERRTGTR25,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0xFC 0.--31. 1. "Target,Error detection target." line.long 0x100 "ECMERRRSTR25,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x100 0.--31. 1. "ResetEnable,Reset enable" line.long 0x104 "ECMERRCTLR26,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x104 0.--31. 1. "Enable,Error detection enable." line.long 0x108 "ECMERRSTSR26,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x108 0.--31. 1. "Status,Error detection status." line.long 0x10C "ECMERRTGTR26,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x10C 0.--31. 1. "Target,Error detection target." line.long 0x110 "ECMERRRSTR26,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x110 0.--31. 1. "ResetEnable,Reset enable" line.long 0x114 "ECMERRCTLR27,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x114 0.--31. 1. "Enable,Error detection enable." line.long 0x118 "ECMERRSTSR27,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x118 0.--31. 1. "Status,Error detection status." line.long 0x11C "ECMERRTGTR27,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x11C 0.--31. 1. "Target,Error detection target." line.long 0x120 "ECMERRRSTR27,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x120 0.--31. 1. "ResetEnable,Reset enable" line.long 0x124 "ECMERRCTLR28,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x124 0.--31. 1. "Enable,Error detection enable." line.long 0x128 "ECMERRSTSR28,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x128 0.--31. 1. "Status,Error detection status." line.long 0x12C "ECMERRTGTR28,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x12C 0.--31. 1. "Target,Error detection target." line.long 0x130 "ECMERRRSTR28,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x130 0.--31. 1. "ResetEnable,Reset enable" line.long 0x134 "ECMERRCTLR29,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x134 0.--31. 1. "Enable,Error detection enable." line.long 0x138 "ECMERRSTSR29,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x138 0.--31. 1. "Status,Error detection status." line.long 0x13C "ECMERRTGTR29,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x13C 0.--31. 1. "Target,Error detection target." line.long 0x140 "ECMERRRSTR29,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x140 0.--31. 1. "ResetEnable,Reset enable" line.long 0x144 "ECMERRCTLR30,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x144 0.--31. 1. "Enable,Error detection enable." line.long 0x148 "ECMERRSTSR30,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x148 0.--31. 1. "Status,Error detection status." line.long 0x14C "ECMERRTGTR30,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x14C 0.--31. 1. "Target,Error detection target." line.long 0x150 "ECMERRRSTR30,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x150 0.--31. 1. "ResetEnable,Reset enable" line.long 0x154 "ECMERRCTLR31,This register is used to enable error checking function. ECMMERRCTLR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x154 0.--31. 1. "Enable,Error detection enable." line.long 0x158 "ECMERRSTSR31,This register indicate the status of error checking function. ECMERRSTSR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x158 0.--31. 1. "Status,Error detection status." line.long 0x15C "ECMERRTGTR31,This register is used to choose the destination of interrupt signal which is output when error status register is set to 1’b1. ECMERRTGTR5 and 6 are used for security related errors. Each bit is assigned for one input error signal." hexmask.long 0x15C 0.--31. 1. "Target,Error detection target." line.long 0x160 "ECMERRRSTR31,This register is used to reset enable to issue the reset request to CPG. Each bit is assigned for one input error signal" hexmask.long 0x160 0.--31. 1. "ResetEnable,Reset enable" line.long 0x164 "ECMCKMCSR,ECMCKMCSR" rbitfld.long 0x164 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline rbitfld.long 0x164 24. "CLRMON,Reference for clear command signal - ECMCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x164 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x164 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x164 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x164 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x164 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x168 "ECMCKMECR,ECMCKMECR" bitfld.long 0x168 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x16C "ECMCKMLCH,ECMCKMLCH" hexmask.long.tbyte 0x16C 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0x170 "ECMCKMLCL,ECMCKMLCL" hexmask.long.tbyte 0x170 0.--23. 1. "CMPL,The lower limit to judge as expected oscillation." rgroup.long 0xA74++0x7 line.long 0x0 "ECMCKMCNT,ECMCKMCNT" hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "ECMCKMCNTE,ECMCKMCNTE" bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,ECMCKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." group.long 0xA7C++0x3 line.long 0x0 "ECMCKMMDR,ECMCKMMDR" hexmask.long.word 0x0 0.--15. 1. "MODE" rgroup.long 0xA80++0x3 line.long 0x0 "ECMCKMSR,ECMCKMSR" bitfld.long 0x0 0. "CKM_STS,STS bit[15] of Clock Monitor" "0,1" group.long 0xA84++0x3 line.long 0x0 "ECMDYNCTRLR,ECMDYNCTRLR" bitfld.long 0x0 0. "DYNEN,Dynamic Enable bit" "0: default,1: enable dynamic mode" rgroup.long 0xA88++0x3 line.long 0x0 "ECMERRSTSINR,ECMERRSTSINR" bitfld.long 0x0 0. "ERROROUT_N,ERROROUT_N status" "0,1" tree.end tree "HSCIF" base ad:0x0 tree "HSCIF_0" base ad:0xE6540000 group.word 0x0++0x1 line.word 0x0 "HSSMR,-" bitfld.word 0x0 6. "CHR,Character Length" "0: 8 bits,1: 7 bits" bitfld.word 0x0 5. "PE,Parity Enable" "0: Disables parity bit addition and check,1: Enables parity bit addition and check" newline bitfld.word 0x0 4. "O/E#,Parity Mode" "0: Even parity,1: Odd parity" bitfld.word 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit*1,1: 2 stop bits*2" newline bitfld.word 0x0 0.--1. "CKS,Clock Select 1 and 0" "0: Internal clock,1: Internal clock/4,?,?" group.byte 0x4++0x0 line.byte 0x0 "HSBRR,-" group.word 0x8++0x1 line.word 0x0 "HSSCR,HSSCR is a register that enables or disables transmission/reception by the HSCIF. enables or disables interrupt requests. and selects transmission/reception clock source for the HSCIF." bitfld.word 0x0 14.--15. "TOT,Set the time for a data ready (DR) or a timeout (TO) to be set in asynchronous mode." "0: 15 etu*,1: 31 etu,?,?" bitfld.word 0x0 11. "TEIE,Transmit End Interrupt Enable" "0: The transmit FIFO data empty,1: The transmit end" newline bitfld.word 0x0 7. "TIE,Transmit Interrupt Enable" "0: When the TEIE bit is 0,1: When the TEIE bit is 0" bitfld.word 0x0 6. "RIE,Receive Interrupt Enable" "0: Disables receive-FIFO-data-full interrupts,1: Enables receive-FIFO-data-full interrupt" newline bitfld.word 0x0 5. "TE,Transmit Enable" "0: Disables transmission,1: Enables transmission" bitfld.word 0x0 4. "RE,Receive Enable" "0: Disables reception,1: Enables reception" newline bitfld.word 0x0 3. "REIE,Receive Error Interrupt Enable" "0: Disables receive-error interrupt,1: Enables receive-error interrupt" bitfld.word 0x0 2. "TOIE,Timeout Interrupt Enable" "0: Disables timeout interrupts,1: Enables timeout interrupts" newline bitfld.word 0x0 0.--1. "CKE,Clock Enable 1 and 0" "?,?,2: Prohibited,?" wgroup.byte 0xC++0x0 line.byte 0x0 "HSFTDR,-" group.word 0x10++0x1 line.word 0x0 "HSFSR,HSFSR is a 16-bit register. The lower 8 bits are status flags that indicate the operating status of the HSCIF. and the upper 8 bits are all reserved." bitfld.word 0x0 7. "ER,Receive Error" "0: Indicates that no framing or parity error has..,1: Indicates that a framing error or a parity error.." bitfld.word 0x0 6. "TEND,Transmit End" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended" newline bitfld.word 0x0 5. "TDFE,Transmit FIFO Data Empty" "0: Indicates that the number of transmit data..,1: Indicates that the number of transmit data in.." bitfld.word 0x0 4. "BRK,Break Detect" "0: Indicates that no break signal has been received,1: Indicates that a break signal has been received" newline rbitfld.word 0x0 3. "FER,Framing Error" "0: Indicates that there is no framing error in the..,1: Indicates that there is a framing error in the.." rbitfld.word 0x0 2. "PER,Parity Error" "0: Indicates that there is no parity error in the..,1: Indicates that there is a parity error in the.." newline bitfld.word 0x0 1. "RDF,Receive FIFO Data Full" "0: Indicates that the number of receive data bytes..,1: Indicates that the number of receive data bytes.." bitfld.word 0x0 0. "DR,Receive Data Ready" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." rgroup.byte 0x14++0x0 line.byte 0x0 "HSFRDR,-" group.word 0x18++0x1 line.word 0x0 "HSFCR,HSFCR is a register that resets data counts for transmit and receive FIFO registers. It also has a modem control and a loopback test enable bit." bitfld.word 0x0 3. "MCE,Modem Control Enable" "0: Disables modem signals,1: Enables modem signals" bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" newline bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" bitfld.word 0x0 0. "LOOP,Loopback Test" "0: Disables the loopback test,1: Enables the loopback test" rgroup.word 0x1C++0x1 line.word 0x0 "HSFDR,HSFDR is a 16-bit register that indicates the number of data bytes stored in HSFTDR and that in HSFRDR." hexmask.word.byte 0x0 8.--15. 1. "T,These bits indicate the number of data bytes un-transmitted and still stored in HSFTDR." hexmask.word.byte 0x0 0.--7. 1. "R,These bits indicate the number of receive data stored in HSFRDR." group.word 0x20++0x1 line.word 0x0 "HSSPTR,HSSPTR controls multiplexed input/output and data on the high speed serial communication interface (HSCIF) ports. Bits 1 and 0 control breaks in serial transmission/reception by reading input data from the HRX pin and writing output data to the.." bitfld.word 0x0 7. "RTSIO,Serial Port – RTS Port Input/output" "0: Indicates that this bit does not output the..,1: Indicates that this bit outputs the value of the.." bitfld.word 0x0 6. "RTSDT,Serial Port – RTS Port Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 5. "CTSIO,Serial Port – CTS Port Input/output" "0: Indicates that the CTSDT bit value is not output..,1: Indicates that the CTSDT bit value is output to.." bitfld.word 0x0 4. "CTSDT,Serial Port – CTS Port Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline rbitfld.word 0x0 3. "SCKIO,Serial Port – Clock Port Input" "0,1" rbitfld.word 0x0 2. "SCKDT,Serial Port – Clock Port Data" "0,1" newline bitfld.word 0x0 1. "SPB2IO,Serial Port – Break Input/output" "0: Indicates that the SPB2DT bit value is not..,1: Indicates that the SPB2DT bit value is output to.." bitfld.word 0x0 0. "SPB2DT,Serial Port – Break Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" group.word 0x24++0x1 line.word 0x0 "HSLSR,-" bitfld.word 0x0 2. "TO,Timeout" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." bitfld.word 0x0 0. "ORER,Overrun Error" "0: Indicates that data is being received or has..,1: Indicates that an overrun error has occurred in.." group.word 0x40++0x1 line.word 0x0 "HSSRR,-" bitfld.word 0x0 15. "SRE,Sampling Rate Register Enable (SRE)" "0: Set the SRCYC [4: 0] bits to 15,1: Validates the setting of the SRCYC [4:0] bits" bitfld.word 0x0 14. "SRDE,Sampling Point Register Enable (SRDE)" "0: Invalidates the setting of the SRHP [3:0] bits..,1: Validates the setting of the SRHP [3: 0] bits" newline hexmask.word.byte 0x0 8.--11. 1. "SRHP,Sampling Point Register (SRHP)" hexmask.word.byte 0x0 0.--4. 1. "SRCYC,Bits 4 to 0: Sampling Rate Register (SRCYC)" rgroup.word 0x44++0x1 line.word 0x0 "HSRER,-" hexmask.word.byte 0x0 8.--14. 1. "PER,Parity Error Count" hexmask.word.byte 0x0 0.--6. 1. "FER,Framing Error Count" group.word 0x50++0x1 line.word 0x0 "HSRTGR,-" hexmask.word.byte 0x0 0.--6. 1. "RSTRG,RTS Output Active Trigger Count" group.word 0x54++0x1 line.word 0x0 "HSRTRGR,-" hexmask.word.byte 0x0 0.--6. 1. "RTRG,Receive FIFO Data Count Trigger" group.word 0x58++0x1 line.word 0x0 "HSTTRGR,-" hexmask.word.byte 0x0 0.--6. 1. "TTRG,Transmit FIFO Data Count Trigger" tree.end tree "HSCIF_1" base ad:0xE6550000 group.word 0x0++0x1 line.word 0x0 "HSSMR,-" bitfld.word 0x0 6. "CHR,Character Length" "0: 8 bits,1: 7 bits" bitfld.word 0x0 5. "PE,Parity Enable" "0: Disables parity bit addition and check,1: Enables parity bit addition and check" newline bitfld.word 0x0 4. "O/E#,Parity Mode" "0: Even parity,1: Odd parity" bitfld.word 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit*1,1: 2 stop bits*2" newline bitfld.word 0x0 0.--1. "CKS,Clock Select 1 and 0" "0: Internal clock,1: Internal clock/4,?,?" group.byte 0x4++0x0 line.byte 0x0 "HSBRR,-" group.word 0x8++0x1 line.word 0x0 "HSSCR,HSSCR is a register that enables or disables transmission/reception by the HSCIF. enables or disables interrupt requests. and selects transmission/reception clock source for the HSCIF." bitfld.word 0x0 14.--15. "TOT,Set the time for a data ready (DR) or a timeout (TO) to be set in asynchronous mode." "0: 15 etu*,1: 31 etu,?,?" bitfld.word 0x0 11. "TEIE,Transmit End Interrupt Enable" "0: The transmit FIFO data empty,1: The transmit end" newline bitfld.word 0x0 7. "TIE,Transmit Interrupt Enable" "0: When the TEIE bit is 0,1: When the TEIE bit is 0" bitfld.word 0x0 6. "RIE,Receive Interrupt Enable" "0: Disables receive-FIFO-data-full interrupts,1: Enables receive-FIFO-data-full interrupt" newline bitfld.word 0x0 5. "TE,Transmit Enable" "0: Disables transmission,1: Enables transmission" bitfld.word 0x0 4. "RE,Receive Enable" "0: Disables reception,1: Enables reception" newline bitfld.word 0x0 3. "REIE,Receive Error Interrupt Enable" "0: Disables receive-error interrupt,1: Enables receive-error interrupt" bitfld.word 0x0 2. "TOIE,Timeout Interrupt Enable" "0: Disables timeout interrupts,1: Enables timeout interrupts" newline bitfld.word 0x0 0.--1. "CKE,Clock Enable 1 and 0" "?,?,2: Prohibited,?" wgroup.byte 0xC++0x0 line.byte 0x0 "HSFTDR,-" group.word 0x10++0x1 line.word 0x0 "HSFSR,HSFSR is a 16-bit register. The lower 8 bits are status flags that indicate the operating status of the HSCIF. and the upper 8 bits are all reserved." bitfld.word 0x0 7. "ER,Receive Error" "0: Indicates that no framing or parity error has..,1: Indicates that a framing error or a parity error.." bitfld.word 0x0 6. "TEND,Transmit End" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended" newline bitfld.word 0x0 5. "TDFE,Transmit FIFO Data Empty" "0: Indicates that the number of transmit data..,1: Indicates that the number of transmit data in.." bitfld.word 0x0 4. "BRK,Break Detect" "0: Indicates that no break signal has been received,1: Indicates that a break signal has been received" newline rbitfld.word 0x0 3. "FER,Framing Error" "0: Indicates that there is no framing error in the..,1: Indicates that there is a framing error in the.." rbitfld.word 0x0 2. "PER,Parity Error" "0: Indicates that there is no parity error in the..,1: Indicates that there is a parity error in the.." newline bitfld.word 0x0 1. "RDF,Receive FIFO Data Full" "0: Indicates that the number of receive data bytes..,1: Indicates that the number of receive data bytes.." bitfld.word 0x0 0. "DR,Receive Data Ready" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." rgroup.byte 0x14++0x0 line.byte 0x0 "HSFRDR,-" group.word 0x18++0x1 line.word 0x0 "HSFCR,HSFCR is a register that resets data counts for transmit and receive FIFO registers. It also has a modem control and a loopback test enable bit." bitfld.word 0x0 3. "MCE,Modem Control Enable" "0: Disables modem signals,1: Enables modem signals" bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" newline bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" bitfld.word 0x0 0. "LOOP,Loopback Test" "0: Disables the loopback test,1: Enables the loopback test" rgroup.word 0x1C++0x1 line.word 0x0 "HSFDR,HSFDR is a 16-bit register that indicates the number of data bytes stored in HSFTDR and that in HSFRDR." hexmask.word.byte 0x0 8.--15. 1. "T,These bits indicate the number of data bytes un-transmitted and still stored in HSFTDR." hexmask.word.byte 0x0 0.--7. 1. "R,These bits indicate the number of receive data stored in HSFRDR." group.word 0x20++0x1 line.word 0x0 "HSSPTR,HSSPTR controls multiplexed input/output and data on the high speed serial communication interface (HSCIF) ports. Bits 1 and 0 control breaks in serial transmission/reception by reading input data from the HRX pin and writing output data to the.." bitfld.word 0x0 7. "RTSIO,Serial Port – RTS Port Input/output" "0: Indicates that this bit does not output the..,1: Indicates that this bit outputs the value of the.." bitfld.word 0x0 6. "RTSDT,Serial Port – RTS Port Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 5. "CTSIO,Serial Port – CTS Port Input/output" "0: Indicates that the CTSDT bit value is not output..,1: Indicates that the CTSDT bit value is output to.." bitfld.word 0x0 4. "CTSDT,Serial Port – CTS Port Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline rbitfld.word 0x0 3. "SCKIO,Serial Port – Clock Port Input" "0,1" rbitfld.word 0x0 2. "SCKDT,Serial Port – Clock Port Data" "0,1" newline bitfld.word 0x0 1. "SPB2IO,Serial Port – Break Input/output" "0: Indicates that the SPB2DT bit value is not..,1: Indicates that the SPB2DT bit value is output to.." bitfld.word 0x0 0. "SPB2DT,Serial Port – Break Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" group.word 0x24++0x1 line.word 0x0 "HSLSR,-" bitfld.word 0x0 2. "TO,Timeout" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." bitfld.word 0x0 0. "ORER,Overrun Error" "0: Indicates that data is being received or has..,1: Indicates that an overrun error has occurred in.." group.word 0x40++0x1 line.word 0x0 "HSSRR,-" bitfld.word 0x0 15. "SRE,Sampling Rate Register Enable (SRE)" "0: Set the SRCYC [4: 0] bits to 15,1: Validates the setting of the SRCYC [4:0] bits" bitfld.word 0x0 14. "SRDE,Sampling Point Register Enable (SRDE)" "0: Invalidates the setting of the SRHP [3:0] bits..,1: Validates the setting of the SRHP [3: 0] bits" newline hexmask.word.byte 0x0 8.--11. 1. "SRHP,Sampling Point Register (SRHP)" hexmask.word.byte 0x0 0.--4. 1. "SRCYC,Bits 4 to 0: Sampling Rate Register (SRCYC)" rgroup.word 0x44++0x1 line.word 0x0 "HSRER,-" hexmask.word.byte 0x0 8.--14. 1. "PER,Parity Error Count" hexmask.word.byte 0x0 0.--6. 1. "FER,Framing Error Count" group.word 0x50++0x1 line.word 0x0 "HSRTGR,-" hexmask.word.byte 0x0 0.--6. 1. "RSTRG,RTS Output Active Trigger Count" group.word 0x54++0x1 line.word 0x0 "HSRTRGR,-" hexmask.word.byte 0x0 0.--6. 1. "RTRG,Receive FIFO Data Count Trigger" group.word 0x58++0x1 line.word 0x0 "HSTTRGR,-" hexmask.word.byte 0x0 0.--6. 1. "TTRG,Transmit FIFO Data Count Trigger" tree.end tree "HSCIF_2" base ad:0xE6560000 group.word 0x0++0x1 line.word 0x0 "HSSMR,-" bitfld.word 0x0 6. "CHR,Character Length" "0: 8 bits,1: 7 bits" bitfld.word 0x0 5. "PE,Parity Enable" "0: Disables parity bit addition and check,1: Enables parity bit addition and check" newline bitfld.word 0x0 4. "O/E#,Parity Mode" "0: Even parity,1: Odd parity" bitfld.word 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit*1,1: 2 stop bits*2" newline bitfld.word 0x0 0.--1. "CKS,Clock Select 1 and 0" "0: Internal clock,1: Internal clock/4,?,?" group.byte 0x4++0x0 line.byte 0x0 "HSBRR,-" group.word 0x8++0x1 line.word 0x0 "HSSCR,HSSCR is a register that enables or disables transmission/reception by the HSCIF. enables or disables interrupt requests. and selects transmission/reception clock source for the HSCIF." bitfld.word 0x0 14.--15. "TOT,Set the time for a data ready (DR) or a timeout (TO) to be set in asynchronous mode." "0: 15 etu*,1: 31 etu,?,?" bitfld.word 0x0 11. "TEIE,Transmit End Interrupt Enable" "0: The transmit FIFO data empty,1: The transmit end" newline bitfld.word 0x0 7. "TIE,Transmit Interrupt Enable" "0: When the TEIE bit is 0,1: When the TEIE bit is 0" bitfld.word 0x0 6. "RIE,Receive Interrupt Enable" "0: Disables receive-FIFO-data-full interrupts,1: Enables receive-FIFO-data-full interrupt" newline bitfld.word 0x0 5. "TE,Transmit Enable" "0: Disables transmission,1: Enables transmission" bitfld.word 0x0 4. "RE,Receive Enable" "0: Disables reception,1: Enables reception" newline bitfld.word 0x0 3. "REIE,Receive Error Interrupt Enable" "0: Disables receive-error interrupt,1: Enables receive-error interrupt" bitfld.word 0x0 2. "TOIE,Timeout Interrupt Enable" "0: Disables timeout interrupts,1: Enables timeout interrupts" newline bitfld.word 0x0 0.--1. "CKE,Clock Enable 1 and 0" "?,?,2: Prohibited,?" wgroup.byte 0xC++0x0 line.byte 0x0 "HSFTDR,-" group.word 0x10++0x1 line.word 0x0 "HSFSR,HSFSR is a 16-bit register. The lower 8 bits are status flags that indicate the operating status of the HSCIF. and the upper 8 bits are all reserved." bitfld.word 0x0 7. "ER,Receive Error" "0: Indicates that no framing or parity error has..,1: Indicates that a framing error or a parity error.." bitfld.word 0x0 6. "TEND,Transmit End" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended" newline bitfld.word 0x0 5. "TDFE,Transmit FIFO Data Empty" "0: Indicates that the number of transmit data..,1: Indicates that the number of transmit data in.." bitfld.word 0x0 4. "BRK,Break Detect" "0: Indicates that no break signal has been received,1: Indicates that a break signal has been received" newline rbitfld.word 0x0 3. "FER,Framing Error" "0: Indicates that there is no framing error in the..,1: Indicates that there is a framing error in the.." rbitfld.word 0x0 2. "PER,Parity Error" "0: Indicates that there is no parity error in the..,1: Indicates that there is a parity error in the.." newline bitfld.word 0x0 1. "RDF,Receive FIFO Data Full" "0: Indicates that the number of receive data bytes..,1: Indicates that the number of receive data bytes.." bitfld.word 0x0 0. "DR,Receive Data Ready" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." rgroup.byte 0x14++0x0 line.byte 0x0 "HSFRDR,-" group.word 0x18++0x1 line.word 0x0 "HSFCR,HSFCR is a register that resets data counts for transmit and receive FIFO registers. It also has a modem control and a loopback test enable bit." bitfld.word 0x0 3. "MCE,Modem Control Enable" "0: Disables modem signals,1: Enables modem signals" bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" newline bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" bitfld.word 0x0 0. "LOOP,Loopback Test" "0: Disables the loopback test,1: Enables the loopback test" rgroup.word 0x1C++0x1 line.word 0x0 "HSFDR,HSFDR is a 16-bit register that indicates the number of data bytes stored in HSFTDR and that in HSFRDR." hexmask.word.byte 0x0 8.--15. 1. "T,These bits indicate the number of data bytes un-transmitted and still stored in HSFTDR." hexmask.word.byte 0x0 0.--7. 1. "R,These bits indicate the number of receive data stored in HSFRDR." group.word 0x20++0x1 line.word 0x0 "HSSPTR,HSSPTR controls multiplexed input/output and data on the high speed serial communication interface (HSCIF) ports. Bits 1 and 0 control breaks in serial transmission/reception by reading input data from the HRX pin and writing output data to the.." bitfld.word 0x0 7. "RTSIO,Serial Port – RTS Port Input/output" "0: Indicates that this bit does not output the..,1: Indicates that this bit outputs the value of the.." bitfld.word 0x0 6. "RTSDT,Serial Port – RTS Port Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 5. "CTSIO,Serial Port – CTS Port Input/output" "0: Indicates that the CTSDT bit value is not output..,1: Indicates that the CTSDT bit value is output to.." bitfld.word 0x0 4. "CTSDT,Serial Port – CTS Port Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline rbitfld.word 0x0 3. "SCKIO,Serial Port – Clock Port Input" "0,1" rbitfld.word 0x0 2. "SCKDT,Serial Port – Clock Port Data" "0,1" newline bitfld.word 0x0 1. "SPB2IO,Serial Port – Break Input/output" "0: Indicates that the SPB2DT bit value is not..,1: Indicates that the SPB2DT bit value is output to.." bitfld.word 0x0 0. "SPB2DT,Serial Port – Break Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" group.word 0x24++0x1 line.word 0x0 "HSLSR,-" bitfld.word 0x0 2. "TO,Timeout" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." bitfld.word 0x0 0. "ORER,Overrun Error" "0: Indicates that data is being received or has..,1: Indicates that an overrun error has occurred in.." group.word 0x40++0x1 line.word 0x0 "HSSRR,-" bitfld.word 0x0 15. "SRE,Sampling Rate Register Enable (SRE)" "0: Set the SRCYC [4: 0] bits to 15,1: Validates the setting of the SRCYC [4:0] bits" bitfld.word 0x0 14. "SRDE,Sampling Point Register Enable (SRDE)" "0: Invalidates the setting of the SRHP [3:0] bits..,1: Validates the setting of the SRHP [3: 0] bits" newline hexmask.word.byte 0x0 8.--11. 1. "SRHP,Sampling Point Register (SRHP)" hexmask.word.byte 0x0 0.--4. 1. "SRCYC,Bits 4 to 0: Sampling Rate Register (SRCYC)" rgroup.word 0x44++0x1 line.word 0x0 "HSRER,-" hexmask.word.byte 0x0 8.--14. 1. "PER,Parity Error Count" hexmask.word.byte 0x0 0.--6. 1. "FER,Framing Error Count" group.word 0x50++0x1 line.word 0x0 "HSRTGR,-" hexmask.word.byte 0x0 0.--6. 1. "RSTRG,RTS Output Active Trigger Count" group.word 0x54++0x1 line.word 0x0 "HSRTRGR,-" hexmask.word.byte 0x0 0.--6. 1. "RTRG,Receive FIFO Data Count Trigger" group.word 0x58++0x1 line.word 0x0 "HSTTRGR,-" hexmask.word.byte 0x0 0.--6. 1. "TTRG,Transmit FIFO Data Count Trigger" tree.end tree "HSCIF_3" base ad:0xE66A0000 group.word 0x0++0x1 line.word 0x0 "HSSMR,-" bitfld.word 0x0 6. "CHR,Character Length" "0: 8 bits,1: 7 bits" bitfld.word 0x0 5. "PE,Parity Enable" "0: Disables parity bit addition and check,1: Enables parity bit addition and check" newline bitfld.word 0x0 4. "O/E#,Parity Mode" "0: Even parity,1: Odd parity" bitfld.word 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit*1,1: 2 stop bits*2" newline bitfld.word 0x0 0.--1. "CKS,Clock Select 1 and 0" "0: Internal clock,1: Internal clock/4,?,?" group.byte 0x4++0x0 line.byte 0x0 "HSBRR,-" group.word 0x8++0x1 line.word 0x0 "HSSCR,HSSCR is a register that enables or disables transmission/reception by the HSCIF. enables or disables interrupt requests. and selects transmission/reception clock source for the HSCIF." bitfld.word 0x0 14.--15. "TOT,Set the time for a data ready (DR) or a timeout (TO) to be set in asynchronous mode." "0: 15 etu*,1: 31 etu,?,?" bitfld.word 0x0 11. "TEIE,Transmit End Interrupt Enable" "0: The transmit FIFO data empty,1: The transmit end" newline bitfld.word 0x0 7. "TIE,Transmit Interrupt Enable" "0: When the TEIE bit is 0,1: When the TEIE bit is 0" bitfld.word 0x0 6. "RIE,Receive Interrupt Enable" "0: Disables receive-FIFO-data-full interrupts,1: Enables receive-FIFO-data-full interrupt" newline bitfld.word 0x0 5. "TE,Transmit Enable" "0: Disables transmission,1: Enables transmission" bitfld.word 0x0 4. "RE,Receive Enable" "0: Disables reception,1: Enables reception" newline bitfld.word 0x0 3. "REIE,Receive Error Interrupt Enable" "0: Disables receive-error interrupt,1: Enables receive-error interrupt" bitfld.word 0x0 2. "TOIE,Timeout Interrupt Enable" "0: Disables timeout interrupts,1: Enables timeout interrupts" newline bitfld.word 0x0 0.--1. "CKE,Clock Enable 1 and 0" "?,?,2: Prohibited,?" wgroup.byte 0xC++0x0 line.byte 0x0 "HSFTDR,-" group.word 0x10++0x1 line.word 0x0 "HSFSR,HSFSR is a 16-bit register. The lower 8 bits are status flags that indicate the operating status of the HSCIF. and the upper 8 bits are all reserved." bitfld.word 0x0 7. "ER,Receive Error" "0: Indicates that no framing or parity error has..,1: Indicates that a framing error or a parity error.." bitfld.word 0x0 6. "TEND,Transmit End" "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended" newline bitfld.word 0x0 5. "TDFE,Transmit FIFO Data Empty" "0: Indicates that the number of transmit data..,1: Indicates that the number of transmit data in.." bitfld.word 0x0 4. "BRK,Break Detect" "0: Indicates that no break signal has been received,1: Indicates that a break signal has been received" newline rbitfld.word 0x0 3. "FER,Framing Error" "0: Indicates that there is no framing error in the..,1: Indicates that there is a framing error in the.." rbitfld.word 0x0 2. "PER,Parity Error" "0: Indicates that there is no parity error in the..,1: Indicates that there is a parity error in the.." newline bitfld.word 0x0 1. "RDF,Receive FIFO Data Full" "0: Indicates that the number of receive data bytes..,1: Indicates that the number of receive data bytes.." bitfld.word 0x0 0. "DR,Receive Data Ready" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." rgroup.byte 0x14++0x0 line.byte 0x0 "HSFRDR,-" group.word 0x18++0x1 line.word 0x0 "HSFCR,HSFCR is a register that resets data counts for transmit and receive FIFO registers. It also has a modem control and a loopback test enable bit." bitfld.word 0x0 3. "MCE,Modem Control Enable" "0: Disables modem signals,1: Enables modem signals" bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" newline bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" bitfld.word 0x0 0. "LOOP,Loopback Test" "0: Disables the loopback test,1: Enables the loopback test" rgroup.word 0x1C++0x1 line.word 0x0 "HSFDR,HSFDR is a 16-bit register that indicates the number of data bytes stored in HSFTDR and that in HSFRDR." hexmask.word.byte 0x0 8.--15. 1. "T,These bits indicate the number of data bytes un-transmitted and still stored in HSFTDR." hexmask.word.byte 0x0 0.--7. 1. "R,These bits indicate the number of receive data stored in HSFRDR." group.word 0x20++0x1 line.word 0x0 "HSSPTR,HSSPTR controls multiplexed input/output and data on the high speed serial communication interface (HSCIF) ports. Bits 1 and 0 control breaks in serial transmission/reception by reading input data from the HRX pin and writing output data to the.." bitfld.word 0x0 7. "RTSIO,Serial Port – RTS Port Input/output" "0: Indicates that this bit does not output the..,1: Indicates that this bit outputs the value of the.." bitfld.word 0x0 6. "RTSDT,Serial Port – RTS Port Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 5. "CTSIO,Serial Port – CTS Port Input/output" "0: Indicates that the CTSDT bit value is not output..,1: Indicates that the CTSDT bit value is output to.." bitfld.word 0x0 4. "CTSDT,Serial Port – CTS Port Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline rbitfld.word 0x0 3. "SCKIO,Serial Port – Clock Port Input" "0,1" rbitfld.word 0x0 2. "SCKDT,Serial Port – Clock Port Data" "0,1" newline bitfld.word 0x0 1. "SPB2IO,Serial Port – Break Input/output" "0: Indicates that the SPB2DT bit value is not..,1: Indicates that the SPB2DT bit value is output to.." bitfld.word 0x0 0. "SPB2DT,Serial Port – Break Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" group.word 0x24++0x1 line.word 0x0 "HSLSR,-" bitfld.word 0x0 2. "TO,Timeout" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." bitfld.word 0x0 0. "ORER,Overrun Error" "0: Indicates that data is being received or has..,1: Indicates that an overrun error has occurred in.." group.word 0x40++0x1 line.word 0x0 "HSSRR,-" bitfld.word 0x0 15. "SRE,Sampling Rate Register Enable (SRE)" "0: Set the SRCYC [4: 0] bits to 15,1: Validates the setting of the SRCYC [4:0] bits" bitfld.word 0x0 14. "SRDE,Sampling Point Register Enable (SRDE)" "0: Invalidates the setting of the SRHP [3:0] bits..,1: Validates the setting of the SRHP [3: 0] bits" newline hexmask.word.byte 0x0 8.--11. 1. "SRHP,Sampling Point Register (SRHP)" hexmask.word.byte 0x0 0.--4. 1. "SRCYC,Bits 4 to 0: Sampling Rate Register (SRCYC)" rgroup.word 0x44++0x1 line.word 0x0 "HSRER,-" hexmask.word.byte 0x0 8.--14. 1. "PER,Parity Error Count" hexmask.word.byte 0x0 0.--6. 1. "FER,Framing Error Count" group.word 0x50++0x1 line.word 0x0 "HSRTGR,-" hexmask.word.byte 0x0 0.--6. 1. "RSTRG,RTS Output Active Trigger Count" group.word 0x54++0x1 line.word 0x0 "HSRTRGR,-" hexmask.word.byte 0x0 0.--6. 1. "RTRG,Receive FIFO Data Count Trigger" group.word 0x58++0x1 line.word 0x0 "HSTTRGR,-" hexmask.word.byte 0x0 0.--6. 1. "TTRG,Transmit FIFO Data Count Trigger" tree.end tree.end tree "I2C" base ad:0x0 tree "I2C_0" base ad:0xE6500000 group.long 0x0++0x23 line.long 0x0 "ICSCR,Slave Control Register" bitfld.long 0x0 4. "SCSS,Slave Clock Stretch Select (V3U only)" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement" bitfld.long 0x0 3. "SDBS,Slave Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" newline bitfld.long 0x0 2. "SIE,Slave Interface Enable" "0,1" bitfld.long 0x0 1. "GCAE,General Call Acknowledgement Enable" "0,1" newline bitfld.long 0x0 0. "FNA,Forced Non Acknowledgement" "0,1" line.long 0x4 "ICMCR,Master Control Register" bitfld.long 0x4 7. "MDBS,Master Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" bitfld.long 0x4 6. "FSCL,Forced SCL" "0,1" newline bitfld.long 0x4 5. "FSDA,Forced SDA" "0,1" bitfld.long 0x4 4. "OBPC,Override Bus Pin Control" "0,1" newline bitfld.long 0x4 3. "MIE,Master Interface Enable" "0,1" bitfld.long 0x4 2. "TSBE,Start Byte Transmission Enable" "0,1" newline bitfld.long 0x4 1. "FSB,Forced Stop onto the Bus" "0,1" bitfld.long 0x4 0. "ESG,Enable Start Generation" "0,1" line.long 0x8 "ICSSR,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and STM bits)." rbitfld.long 0x8 6. "GCAR,General Call Address Received" "0,1" rbitfld.long 0x8 5. "STM,Slave Transmit Mode" "0,1" newline bitfld.long 0x8 4. "SSR,Slave Stop Received" "0,1" bitfld.long 0x8 3. "SDE,Slave Data Empty" "0,1" newline bitfld.long 0x8 2. "SDT,Slave Data Transmitted" "0,1" bitfld.long 0x8 1. "SDR,Slave Data Received" "0,1" newline bitfld.long 0x8 0. "SAR,Slave Address Received" "0,1" line.long 0xC "ICMSR,The status bits (bits 0 to 6) in the master status register are cleared by writing 0 to the respective status bit positions. The individual status bits are held 1 until a reset by writing 0 to the appropriate bit position." bitfld.long 0xC 6. "MNR,Master NACK Received" "0,1" bitfld.long 0xC 5. "MAL,Master Arbitration Lost" "0,1" newline bitfld.long 0xC 4. "MST,Master Stop Transmitted" "0,1" bitfld.long 0xC 3. "MDE,Master Data Empty" "0,1" newline bitfld.long 0xC 2. "MDT,Master Data Transmitted" "0,1" bitfld.long 0xC 1. "MDR,Master Data Received" "0,1" newline bitfld.long 0xC 0. "MAT,Master Address Transmitted" "0,1" line.long 0x10 "ICSIER,Slave Interrupt Enable Register" bitfld.long 0x10 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt" bitfld.long 0x10 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt" newline bitfld.long 0x10 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt" bitfld.long 0x10 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt" newline bitfld.long 0x10 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt" line.long 0x14 "ICMIER,Master Interrupt Enable Register" bitfld.long 0x14 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt" bitfld.long 0x14 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt" newline bitfld.long 0x14 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt" bitfld.long 0x14 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt" newline bitfld.long 0x14 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt" bitfld.long 0x14 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt" newline bitfld.long 0x14 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt" line.long 0x18 "ICCCR,Clock Control Register" hexmask.long.byte 0x18 3.--8. 1. "SCGD,SCL Clock Generation Divider" bitfld.long 0x18 0.--2. "CDF,Clock Division Factor" "?,1: I2C internal clock frequency calculation,?,?,?,?,?,?" line.long 0x1C "ICSAR,Slave Address Register" hexmask.long.byte 0x1C 0.--6. 1. "SADD0_6 to SADD0_0,Slave Address" line.long 0x20 "ICMAR,Master Address Register" hexmask.long.byte 0x20 1.--7. 1. "SADD1_6 to SADD1_0,Slave Address" bitfld.long 0x20 0. "STM1,Slave Transfer Mode" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "ICRXD,Receive Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Read Receive Data" wgroup.long 0x24++0x3 line.long 0x0 "ICTXD,Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Write Transmit Data" group.long 0x28++0x7 line.long 0x0 "ICCCR2,Clock Control Register 2" bitfld.long 0x0 7. "FMPE,FM+ Enable (V3U only)" "0: OD buffer is Standard / Fast mode,1: OD buffer is Fast mode+" bitfld.long 0x0 2. "CDFD,CDF Disable" "0,1" newline bitfld.long 0x0 1. "HLSE,HIGH/LOW Separate Control Enable" "0,1" bitfld.long 0x0 0. "SME,SCL Mask Enable" "0,1" line.long 0x4 "ICMPR,SCL Mask Control Register" hexmask.long.byte 0x4 0.--7. 1. "SMD,SCL Mask Division" group.long 0x3C++0x3 line.long 0x0 "ICDMAER,DMA Enable Register" hexmask.long.byte 0x0 24.--31. 1. "MDMACTSZ,[H3 M3-W V3M D3 M3-N]" hexmask.long.byte 0x0 16.--23. 1. "RMDMATSZ,[H3 M3-W V3M D3 M3-N]" newline hexmask.long.byte 0x0 8.--15. 1. "TMDMATSZ,[H3 M3-W V3M D3 M3-N]" bitfld.long 0x0 7. "TMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode" newline bitfld.long 0x0 6. "RMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode" bitfld.long 0x0 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode" newline bitfld.long 0x0 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode" bitfld.long 0x0 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode" newline bitfld.long 0x0 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode" group.long 0x38++0x3 line.long 0x0 "ICFBSCR,First Bit Setup Cycle Register" hexmask.long.byte 0x0 24.--28. 1. "SRFBSC_4 to SRFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." hexmask.long.byte 0x0 16.--20. 1. "STFBSC_4 to STFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." newline hexmask.long.byte 0x0 0.--4. 1. "FBSC_4 toFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL" tree.end tree "I2C_1" base ad:0xE6508000 group.long 0x0++0x23 line.long 0x0 "ICSCR,Slave Control Register" bitfld.long 0x0 4. "SCSS,Slave Clock Stretch Select (V3U only)" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement" bitfld.long 0x0 3. "SDBS,Slave Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" newline bitfld.long 0x0 2. "SIE,Slave Interface Enable" "0,1" bitfld.long 0x0 1. "GCAE,General Call Acknowledgement Enable" "0,1" newline bitfld.long 0x0 0. "FNA,Forced Non Acknowledgement" "0,1" line.long 0x4 "ICMCR,Master Control Register" bitfld.long 0x4 7. "MDBS,Master Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" bitfld.long 0x4 6. "FSCL,Forced SCL" "0,1" newline bitfld.long 0x4 5. "FSDA,Forced SDA" "0,1" bitfld.long 0x4 4. "OBPC,Override Bus Pin Control" "0,1" newline bitfld.long 0x4 3. "MIE,Master Interface Enable" "0,1" bitfld.long 0x4 2. "TSBE,Start Byte Transmission Enable" "0,1" newline bitfld.long 0x4 1. "FSB,Forced Stop onto the Bus" "0,1" bitfld.long 0x4 0. "ESG,Enable Start Generation" "0,1" line.long 0x8 "ICSSR,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and STM bits)." rbitfld.long 0x8 6. "GCAR,General Call Address Received" "0,1" rbitfld.long 0x8 5. "STM,Slave Transmit Mode" "0,1" newline bitfld.long 0x8 4. "SSR,Slave Stop Received" "0,1" bitfld.long 0x8 3. "SDE,Slave Data Empty" "0,1" newline bitfld.long 0x8 2. "SDT,Slave Data Transmitted" "0,1" bitfld.long 0x8 1. "SDR,Slave Data Received" "0,1" newline bitfld.long 0x8 0. "SAR,Slave Address Received" "0,1" line.long 0xC "ICMSR,The status bits (bits 0 to 6) in the master status register are cleared by writing 0 to the respective status bit positions. The individual status bits are held 1 until a reset by writing 0 to the appropriate bit position." bitfld.long 0xC 6. "MNR,Master NACK Received" "0,1" bitfld.long 0xC 5. "MAL,Master Arbitration Lost" "0,1" newline bitfld.long 0xC 4. "MST,Master Stop Transmitted" "0,1" bitfld.long 0xC 3. "MDE,Master Data Empty" "0,1" newline bitfld.long 0xC 2. "MDT,Master Data Transmitted" "0,1" bitfld.long 0xC 1. "MDR,Master Data Received" "0,1" newline bitfld.long 0xC 0. "MAT,Master Address Transmitted" "0,1" line.long 0x10 "ICSIER,Slave Interrupt Enable Register" bitfld.long 0x10 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt" bitfld.long 0x10 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt" newline bitfld.long 0x10 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt" bitfld.long 0x10 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt" newline bitfld.long 0x10 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt" line.long 0x14 "ICMIER,Master Interrupt Enable Register" bitfld.long 0x14 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt" bitfld.long 0x14 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt" newline bitfld.long 0x14 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt" bitfld.long 0x14 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt" newline bitfld.long 0x14 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt" bitfld.long 0x14 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt" newline bitfld.long 0x14 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt" line.long 0x18 "ICCCR,Clock Control Register" hexmask.long.byte 0x18 3.--8. 1. "SCGD,SCL Clock Generation Divider" bitfld.long 0x18 0.--2. "CDF,Clock Division Factor" "?,1: I2C internal clock frequency calculation,?,?,?,?,?,?" line.long 0x1C "ICSAR,Slave Address Register" hexmask.long.byte 0x1C 0.--6. 1. "SADD0_6 to SADD0_0,Slave Address" line.long 0x20 "ICMAR,Master Address Register" hexmask.long.byte 0x20 1.--7. 1. "SADD1_6 to SADD1_0,Slave Address" bitfld.long 0x20 0. "STM1,Slave Transfer Mode" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "ICRXD,Receive Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Read Receive Data" wgroup.long 0x24++0x3 line.long 0x0 "ICTXD,Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Write Transmit Data" group.long 0x28++0x7 line.long 0x0 "ICCCR2,Clock Control Register 2" bitfld.long 0x0 7. "FMPE,FM+ Enable (V3U only)" "0: OD buffer is Standard / Fast mode,1: OD buffer is Fast mode+" bitfld.long 0x0 2. "CDFD,CDF Disable" "0,1" newline bitfld.long 0x0 1. "HLSE,HIGH/LOW Separate Control Enable" "0,1" bitfld.long 0x0 0. "SME,SCL Mask Enable" "0,1" line.long 0x4 "ICMPR,SCL Mask Control Register" hexmask.long.byte 0x4 0.--7. 1. "SMD,SCL Mask Division" group.long 0x3C++0x3 line.long 0x0 "ICDMAER,DMA Enable Register" hexmask.long.byte 0x0 24.--31. 1. "MDMACTSZ,[H3 M3-W V3M D3 M3-N]" hexmask.long.byte 0x0 16.--23. 1. "RMDMATSZ,[H3 M3-W V3M D3 M3-N]" newline hexmask.long.byte 0x0 8.--15. 1. "TMDMATSZ,[H3 M3-W V3M D3 M3-N]" bitfld.long 0x0 7. "TMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode" newline bitfld.long 0x0 6. "RMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode" bitfld.long 0x0 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode" newline bitfld.long 0x0 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode" bitfld.long 0x0 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode" newline bitfld.long 0x0 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode" group.long 0x38++0x3 line.long 0x0 "ICFBSCR,First Bit Setup Cycle Register" hexmask.long.byte 0x0 24.--28. 1. "SRFBSC_4 to SRFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." hexmask.long.byte 0x0 16.--20. 1. "STFBSC_4 to STFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." newline hexmask.long.byte 0x0 0.--4. 1. "FBSC_4 toFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL" tree.end tree "I2C_2" base ad:0xE6510000 group.long 0x0++0x23 line.long 0x0 "ICSCR,Slave Control Register" bitfld.long 0x0 4. "SCSS,Slave Clock Stretch Select (V3U only)" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement" bitfld.long 0x0 3. "SDBS,Slave Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" newline bitfld.long 0x0 2. "SIE,Slave Interface Enable" "0,1" bitfld.long 0x0 1. "GCAE,General Call Acknowledgement Enable" "0,1" newline bitfld.long 0x0 0. "FNA,Forced Non Acknowledgement" "0,1" line.long 0x4 "ICMCR,Master Control Register" bitfld.long 0x4 7. "MDBS,Master Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" bitfld.long 0x4 6. "FSCL,Forced SCL" "0,1" newline bitfld.long 0x4 5. "FSDA,Forced SDA" "0,1" bitfld.long 0x4 4. "OBPC,Override Bus Pin Control" "0,1" newline bitfld.long 0x4 3. "MIE,Master Interface Enable" "0,1" bitfld.long 0x4 2. "TSBE,Start Byte Transmission Enable" "0,1" newline bitfld.long 0x4 1. "FSB,Forced Stop onto the Bus" "0,1" bitfld.long 0x4 0. "ESG,Enable Start Generation" "0,1" line.long 0x8 "ICSSR,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and STM bits)." rbitfld.long 0x8 6. "GCAR,General Call Address Received" "0,1" rbitfld.long 0x8 5. "STM,Slave Transmit Mode" "0,1" newline bitfld.long 0x8 4. "SSR,Slave Stop Received" "0,1" bitfld.long 0x8 3. "SDE,Slave Data Empty" "0,1" newline bitfld.long 0x8 2. "SDT,Slave Data Transmitted" "0,1" bitfld.long 0x8 1. "SDR,Slave Data Received" "0,1" newline bitfld.long 0x8 0. "SAR,Slave Address Received" "0,1" line.long 0xC "ICMSR,The status bits (bits 0 to 6) in the master status register are cleared by writing 0 to the respective status bit positions. The individual status bits are held 1 until a reset by writing 0 to the appropriate bit position." bitfld.long 0xC 6. "MNR,Master NACK Received" "0,1" bitfld.long 0xC 5. "MAL,Master Arbitration Lost" "0,1" newline bitfld.long 0xC 4. "MST,Master Stop Transmitted" "0,1" bitfld.long 0xC 3. "MDE,Master Data Empty" "0,1" newline bitfld.long 0xC 2. "MDT,Master Data Transmitted" "0,1" bitfld.long 0xC 1. "MDR,Master Data Received" "0,1" newline bitfld.long 0xC 0. "MAT,Master Address Transmitted" "0,1" line.long 0x10 "ICSIER,Slave Interrupt Enable Register" bitfld.long 0x10 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt" bitfld.long 0x10 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt" newline bitfld.long 0x10 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt" bitfld.long 0x10 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt" newline bitfld.long 0x10 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt" line.long 0x14 "ICMIER,Master Interrupt Enable Register" bitfld.long 0x14 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt" bitfld.long 0x14 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt" newline bitfld.long 0x14 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt" bitfld.long 0x14 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt" newline bitfld.long 0x14 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt" bitfld.long 0x14 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt" newline bitfld.long 0x14 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt" line.long 0x18 "ICCCR,Clock Control Register" hexmask.long.byte 0x18 3.--8. 1. "SCGD,SCL Clock Generation Divider" bitfld.long 0x18 0.--2. "CDF,Clock Division Factor" "?,1: I2C internal clock frequency calculation,?,?,?,?,?,?" line.long 0x1C "ICSAR,Slave Address Register" hexmask.long.byte 0x1C 0.--6. 1. "SADD0_6 to SADD0_0,Slave Address" line.long 0x20 "ICMAR,Master Address Register" hexmask.long.byte 0x20 1.--7. 1. "SADD1_6 to SADD1_0,Slave Address" bitfld.long 0x20 0. "STM1,Slave Transfer Mode" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "ICRXD,Receive Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Read Receive Data" wgroup.long 0x24++0x3 line.long 0x0 "ICTXD,Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Write Transmit Data" group.long 0x28++0x7 line.long 0x0 "ICCCR2,Clock Control Register 2" bitfld.long 0x0 7. "FMPE,FM+ Enable (V3U only)" "0: OD buffer is Standard / Fast mode,1: OD buffer is Fast mode+" bitfld.long 0x0 2. "CDFD,CDF Disable" "0,1" newline bitfld.long 0x0 1. "HLSE,HIGH/LOW Separate Control Enable" "0,1" bitfld.long 0x0 0. "SME,SCL Mask Enable" "0,1" line.long 0x4 "ICMPR,SCL Mask Control Register" hexmask.long.byte 0x4 0.--7. 1. "SMD,SCL Mask Division" group.long 0x3C++0x3 line.long 0x0 "ICDMAER,DMA Enable Register" hexmask.long.byte 0x0 24.--31. 1. "MDMACTSZ,[H3 M3-W V3M D3 M3-N]" hexmask.long.byte 0x0 16.--23. 1. "RMDMATSZ,[H3 M3-W V3M D3 M3-N]" newline hexmask.long.byte 0x0 8.--15. 1. "TMDMATSZ,[H3 M3-W V3M D3 M3-N]" bitfld.long 0x0 7. "TMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode" newline bitfld.long 0x0 6. "RMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode" bitfld.long 0x0 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode" newline bitfld.long 0x0 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode" bitfld.long 0x0 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode" newline bitfld.long 0x0 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode" group.long 0x38++0x3 line.long 0x0 "ICFBSCR,First Bit Setup Cycle Register" hexmask.long.byte 0x0 24.--28. 1. "SRFBSC_4 to SRFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." hexmask.long.byte 0x0 16.--20. 1. "STFBSC_4 to STFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." newline hexmask.long.byte 0x0 0.--4. 1. "FBSC_4 toFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL" tree.end tree "I2C_3" base ad:0xE66D0000 group.long 0x0++0x23 line.long 0x0 "ICSCR,Slave Control Register" bitfld.long 0x0 4. "SCSS,Slave Clock Stretch Select (V3U only)" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement" bitfld.long 0x0 3. "SDBS,Slave Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" newline bitfld.long 0x0 2. "SIE,Slave Interface Enable" "0,1" bitfld.long 0x0 1. "GCAE,General Call Acknowledgement Enable" "0,1" newline bitfld.long 0x0 0. "FNA,Forced Non Acknowledgement" "0,1" line.long 0x4 "ICMCR,Master Control Register" bitfld.long 0x4 7. "MDBS,Master Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" bitfld.long 0x4 6. "FSCL,Forced SCL" "0,1" newline bitfld.long 0x4 5. "FSDA,Forced SDA" "0,1" bitfld.long 0x4 4. "OBPC,Override Bus Pin Control" "0,1" newline bitfld.long 0x4 3. "MIE,Master Interface Enable" "0,1" bitfld.long 0x4 2. "TSBE,Start Byte Transmission Enable" "0,1" newline bitfld.long 0x4 1. "FSB,Forced Stop onto the Bus" "0,1" bitfld.long 0x4 0. "ESG,Enable Start Generation" "0,1" line.long 0x8 "ICSSR,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and STM bits)." rbitfld.long 0x8 6. "GCAR,General Call Address Received" "0,1" rbitfld.long 0x8 5. "STM,Slave Transmit Mode" "0,1" newline bitfld.long 0x8 4. "SSR,Slave Stop Received" "0,1" bitfld.long 0x8 3. "SDE,Slave Data Empty" "0,1" newline bitfld.long 0x8 2. "SDT,Slave Data Transmitted" "0,1" bitfld.long 0x8 1. "SDR,Slave Data Received" "0,1" newline bitfld.long 0x8 0. "SAR,Slave Address Received" "0,1" line.long 0xC "ICMSR,The status bits (bits 0 to 6) in the master status register are cleared by writing 0 to the respective status bit positions. The individual status bits are held 1 until a reset by writing 0 to the appropriate bit position." bitfld.long 0xC 6. "MNR,Master NACK Received" "0,1" bitfld.long 0xC 5. "MAL,Master Arbitration Lost" "0,1" newline bitfld.long 0xC 4. "MST,Master Stop Transmitted" "0,1" bitfld.long 0xC 3. "MDE,Master Data Empty" "0,1" newline bitfld.long 0xC 2. "MDT,Master Data Transmitted" "0,1" bitfld.long 0xC 1. "MDR,Master Data Received" "0,1" newline bitfld.long 0xC 0. "MAT,Master Address Transmitted" "0,1" line.long 0x10 "ICSIER,Slave Interrupt Enable Register" bitfld.long 0x10 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt" bitfld.long 0x10 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt" newline bitfld.long 0x10 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt" bitfld.long 0x10 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt" newline bitfld.long 0x10 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt" line.long 0x14 "ICMIER,Master Interrupt Enable Register" bitfld.long 0x14 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt" bitfld.long 0x14 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt" newline bitfld.long 0x14 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt" bitfld.long 0x14 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt" newline bitfld.long 0x14 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt" bitfld.long 0x14 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt" newline bitfld.long 0x14 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt" line.long 0x18 "ICCCR,Clock Control Register" hexmask.long.byte 0x18 3.--8. 1. "SCGD,SCL Clock Generation Divider" bitfld.long 0x18 0.--2. "CDF,Clock Division Factor" "?,1: I2C internal clock frequency calculation,?,?,?,?,?,?" line.long 0x1C "ICSAR,Slave Address Register" hexmask.long.byte 0x1C 0.--6. 1. "SADD0_6 to SADD0_0,Slave Address" line.long 0x20 "ICMAR,Master Address Register" hexmask.long.byte 0x20 1.--7. 1. "SADD1_6 to SADD1_0,Slave Address" bitfld.long 0x20 0. "STM1,Slave Transfer Mode" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "ICRXD,Receive Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Read Receive Data" wgroup.long 0x24++0x3 line.long 0x0 "ICTXD,Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Write Transmit Data" group.long 0x28++0x7 line.long 0x0 "ICCCR2,Clock Control Register 2" bitfld.long 0x0 7. "FMPE,FM+ Enable (V3U only)" "0: OD buffer is Standard / Fast mode,1: OD buffer is Fast mode+" bitfld.long 0x0 2. "CDFD,CDF Disable" "0,1" newline bitfld.long 0x0 1. "HLSE,HIGH/LOW Separate Control Enable" "0,1" bitfld.long 0x0 0. "SME,SCL Mask Enable" "0,1" line.long 0x4 "ICMPR,SCL Mask Control Register" hexmask.long.byte 0x4 0.--7. 1. "SMD,SCL Mask Division" group.long 0x3C++0x3 line.long 0x0 "ICDMAER,DMA Enable Register" hexmask.long.byte 0x0 24.--31. 1. "MDMACTSZ,[H3 M3-W V3M D3 M3-N]" hexmask.long.byte 0x0 16.--23. 1. "RMDMATSZ,[H3 M3-W V3M D3 M3-N]" newline hexmask.long.byte 0x0 8.--15. 1. "TMDMATSZ,[H3 M3-W V3M D3 M3-N]" bitfld.long 0x0 7. "TMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode" newline bitfld.long 0x0 6. "RMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode" bitfld.long 0x0 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode" newline bitfld.long 0x0 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode" bitfld.long 0x0 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode" newline bitfld.long 0x0 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode" group.long 0x38++0x3 line.long 0x0 "ICFBSCR,First Bit Setup Cycle Register" hexmask.long.byte 0x0 24.--28. 1. "SRFBSC_4 to SRFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." hexmask.long.byte 0x0 16.--20. 1. "STFBSC_4 to STFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." newline hexmask.long.byte 0x0 0.--4. 1. "FBSC_4 toFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL" tree.end tree "I2C_4" base ad:0xE66D8000 group.long 0x0++0x23 line.long 0x0 "ICSCR,Slave Control Register" bitfld.long 0x0 4. "SCSS,Slave Clock Stretch Select (V3U only)" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement" bitfld.long 0x0 3. "SDBS,Slave Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" newline bitfld.long 0x0 2. "SIE,Slave Interface Enable" "0,1" bitfld.long 0x0 1. "GCAE,General Call Acknowledgement Enable" "0,1" newline bitfld.long 0x0 0. "FNA,Forced Non Acknowledgement" "0,1" line.long 0x4 "ICMCR,Master Control Register" bitfld.long 0x4 7. "MDBS,Master Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" bitfld.long 0x4 6. "FSCL,Forced SCL" "0,1" newline bitfld.long 0x4 5. "FSDA,Forced SDA" "0,1" bitfld.long 0x4 4. "OBPC,Override Bus Pin Control" "0,1" newline bitfld.long 0x4 3. "MIE,Master Interface Enable" "0,1" bitfld.long 0x4 2. "TSBE,Start Byte Transmission Enable" "0,1" newline bitfld.long 0x4 1. "FSB,Forced Stop onto the Bus" "0,1" bitfld.long 0x4 0. "ESG,Enable Start Generation" "0,1" line.long 0x8 "ICSSR,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and STM bits)." rbitfld.long 0x8 6. "GCAR,General Call Address Received" "0,1" rbitfld.long 0x8 5. "STM,Slave Transmit Mode" "0,1" newline bitfld.long 0x8 4. "SSR,Slave Stop Received" "0,1" bitfld.long 0x8 3. "SDE,Slave Data Empty" "0,1" newline bitfld.long 0x8 2. "SDT,Slave Data Transmitted" "0,1" bitfld.long 0x8 1. "SDR,Slave Data Received" "0,1" newline bitfld.long 0x8 0. "SAR,Slave Address Received" "0,1" line.long 0xC "ICMSR,The status bits (bits 0 to 6) in the master status register are cleared by writing 0 to the respective status bit positions. The individual status bits are held 1 until a reset by writing 0 to the appropriate bit position." bitfld.long 0xC 6. "MNR,Master NACK Received" "0,1" bitfld.long 0xC 5. "MAL,Master Arbitration Lost" "0,1" newline bitfld.long 0xC 4. "MST,Master Stop Transmitted" "0,1" bitfld.long 0xC 3. "MDE,Master Data Empty" "0,1" newline bitfld.long 0xC 2. "MDT,Master Data Transmitted" "0,1" bitfld.long 0xC 1. "MDR,Master Data Received" "0,1" newline bitfld.long 0xC 0. "MAT,Master Address Transmitted" "0,1" line.long 0x10 "ICSIER,Slave Interrupt Enable Register" bitfld.long 0x10 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt" bitfld.long 0x10 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt" newline bitfld.long 0x10 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt" bitfld.long 0x10 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt" newline bitfld.long 0x10 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt" line.long 0x14 "ICMIER,Master Interrupt Enable Register" bitfld.long 0x14 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt" bitfld.long 0x14 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt" newline bitfld.long 0x14 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt" bitfld.long 0x14 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt" newline bitfld.long 0x14 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt" bitfld.long 0x14 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt" newline bitfld.long 0x14 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt" line.long 0x18 "ICCCR,Clock Control Register" hexmask.long.byte 0x18 3.--8. 1. "SCGD,SCL Clock Generation Divider" bitfld.long 0x18 0.--2. "CDF,Clock Division Factor" "?,1: I2C internal clock frequency calculation,?,?,?,?,?,?" line.long 0x1C "ICSAR,Slave Address Register" hexmask.long.byte 0x1C 0.--6. 1. "SADD0_6 to SADD0_0,Slave Address" line.long 0x20 "ICMAR,Master Address Register" hexmask.long.byte 0x20 1.--7. 1. "SADD1_6 to SADD1_0,Slave Address" bitfld.long 0x20 0. "STM1,Slave Transfer Mode" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "ICRXD,Receive Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Read Receive Data" wgroup.long 0x24++0x3 line.long 0x0 "ICTXD,Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Write Transmit Data" group.long 0x28++0x7 line.long 0x0 "ICCCR2,Clock Control Register 2" bitfld.long 0x0 7. "FMPE,FM+ Enable (V3U only)" "0: OD buffer is Standard / Fast mode,1: OD buffer is Fast mode+" bitfld.long 0x0 2. "CDFD,CDF Disable" "0,1" newline bitfld.long 0x0 1. "HLSE,HIGH/LOW Separate Control Enable" "0,1" bitfld.long 0x0 0. "SME,SCL Mask Enable" "0,1" line.long 0x4 "ICMPR,SCL Mask Control Register" hexmask.long.byte 0x4 0.--7. 1. "SMD,SCL Mask Division" group.long 0x3C++0x3 line.long 0x0 "ICDMAER,DMA Enable Register" hexmask.long.byte 0x0 24.--31. 1. "MDMACTSZ,[H3 M3-W V3M D3 M3-N]" hexmask.long.byte 0x0 16.--23. 1. "RMDMATSZ,[H3 M3-W V3M D3 M3-N]" newline hexmask.long.byte 0x0 8.--15. 1. "TMDMATSZ,[H3 M3-W V3M D3 M3-N]" bitfld.long 0x0 7. "TMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode" newline bitfld.long 0x0 6. "RMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode" bitfld.long 0x0 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode" newline bitfld.long 0x0 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode" bitfld.long 0x0 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode" newline bitfld.long 0x0 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode" group.long 0x38++0x3 line.long 0x0 "ICFBSCR,First Bit Setup Cycle Register" hexmask.long.byte 0x0 24.--28. 1. "SRFBSC_4 to SRFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." hexmask.long.byte 0x0 16.--20. 1. "STFBSC_4 to STFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." newline hexmask.long.byte 0x0 0.--4. 1. "FBSC_4 toFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL" tree.end tree "I2C_5" base ad:0xE66E0000 group.long 0x0++0x23 line.long 0x0 "ICSCR,Slave Control Register" bitfld.long 0x0 4. "SCSS,Slave Clock Stretch Select (V3U only)" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement" bitfld.long 0x0 3. "SDBS,Slave Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" newline bitfld.long 0x0 2. "SIE,Slave Interface Enable" "0,1" bitfld.long 0x0 1. "GCAE,General Call Acknowledgement Enable" "0,1" newline bitfld.long 0x0 0. "FNA,Forced Non Acknowledgement" "0,1" line.long 0x4 "ICMCR,Master Control Register" bitfld.long 0x4 7. "MDBS,Master Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" bitfld.long 0x4 6. "FSCL,Forced SCL" "0,1" newline bitfld.long 0x4 5. "FSDA,Forced SDA" "0,1" bitfld.long 0x4 4. "OBPC,Override Bus Pin Control" "0,1" newline bitfld.long 0x4 3. "MIE,Master Interface Enable" "0,1" bitfld.long 0x4 2. "TSBE,Start Byte Transmission Enable" "0,1" newline bitfld.long 0x4 1. "FSB,Forced Stop onto the Bus" "0,1" bitfld.long 0x4 0. "ESG,Enable Start Generation" "0,1" line.long 0x8 "ICSSR,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and STM bits)." rbitfld.long 0x8 6. "GCAR,General Call Address Received" "0,1" rbitfld.long 0x8 5. "STM,Slave Transmit Mode" "0,1" newline bitfld.long 0x8 4. "SSR,Slave Stop Received" "0,1" bitfld.long 0x8 3. "SDE,Slave Data Empty" "0,1" newline bitfld.long 0x8 2. "SDT,Slave Data Transmitted" "0,1" bitfld.long 0x8 1. "SDR,Slave Data Received" "0,1" newline bitfld.long 0x8 0. "SAR,Slave Address Received" "0,1" line.long 0xC "ICMSR,The status bits (bits 0 to 6) in the master status register are cleared by writing 0 to the respective status bit positions. The individual status bits are held 1 until a reset by writing 0 to the appropriate bit position." bitfld.long 0xC 6. "MNR,Master NACK Received" "0,1" bitfld.long 0xC 5. "MAL,Master Arbitration Lost" "0,1" newline bitfld.long 0xC 4. "MST,Master Stop Transmitted" "0,1" bitfld.long 0xC 3. "MDE,Master Data Empty" "0,1" newline bitfld.long 0xC 2. "MDT,Master Data Transmitted" "0,1" bitfld.long 0xC 1. "MDR,Master Data Received" "0,1" newline bitfld.long 0xC 0. "MAT,Master Address Transmitted" "0,1" line.long 0x10 "ICSIER,Slave Interrupt Enable Register" bitfld.long 0x10 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt" bitfld.long 0x10 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt" newline bitfld.long 0x10 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt" bitfld.long 0x10 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt" newline bitfld.long 0x10 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt" line.long 0x14 "ICMIER,Master Interrupt Enable Register" bitfld.long 0x14 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt" bitfld.long 0x14 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt" newline bitfld.long 0x14 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt" bitfld.long 0x14 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt" newline bitfld.long 0x14 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt" bitfld.long 0x14 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt" newline bitfld.long 0x14 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt" line.long 0x18 "ICCCR,Clock Control Register" hexmask.long.byte 0x18 3.--8. 1. "SCGD,SCL Clock Generation Divider" bitfld.long 0x18 0.--2. "CDF,Clock Division Factor" "?,1: I2C internal clock frequency calculation,?,?,?,?,?,?" line.long 0x1C "ICSAR,Slave Address Register" hexmask.long.byte 0x1C 0.--6. 1. "SADD0_6 to SADD0_0,Slave Address" line.long 0x20 "ICMAR,Master Address Register" hexmask.long.byte 0x20 1.--7. 1. "SADD1_6 to SADD1_0,Slave Address" bitfld.long 0x20 0. "STM1,Slave Transfer Mode" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "ICRXD,Receive Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Read Receive Data" wgroup.long 0x24++0x3 line.long 0x0 "ICTXD,Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Write Transmit Data" group.long 0x28++0x7 line.long 0x0 "ICCCR2,Clock Control Register 2" bitfld.long 0x0 7. "FMPE,FM+ Enable (V3U only)" "0: OD buffer is Standard / Fast mode,1: OD buffer is Fast mode+" bitfld.long 0x0 2. "CDFD,CDF Disable" "0,1" newline bitfld.long 0x0 1. "HLSE,HIGH/LOW Separate Control Enable" "0,1" bitfld.long 0x0 0. "SME,SCL Mask Enable" "0,1" line.long 0x4 "ICMPR,SCL Mask Control Register" hexmask.long.byte 0x4 0.--7. 1. "SMD,SCL Mask Division" group.long 0x3C++0x3 line.long 0x0 "ICDMAER,DMA Enable Register" hexmask.long.byte 0x0 24.--31. 1. "MDMACTSZ,[H3 M3-W V3M D3 M3-N]" hexmask.long.byte 0x0 16.--23. 1. "RMDMATSZ,[H3 M3-W V3M D3 M3-N]" newline hexmask.long.byte 0x0 8.--15. 1. "TMDMATSZ,[H3 M3-W V3M D3 M3-N]" bitfld.long 0x0 7. "TMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode" newline bitfld.long 0x0 6. "RMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode" bitfld.long 0x0 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode" newline bitfld.long 0x0 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode" bitfld.long 0x0 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode" newline bitfld.long 0x0 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode" group.long 0x38++0x3 line.long 0x0 "ICFBSCR,First Bit Setup Cycle Register" hexmask.long.byte 0x0 24.--28. 1. "SRFBSC_4 to SRFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." hexmask.long.byte 0x0 16.--20. 1. "STFBSC_4 to STFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." newline hexmask.long.byte 0x0 0.--4. 1. "FBSC_4 toFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL" tree.end tree "I2C_6" base ad:0xE66E8000 group.long 0x0++0x23 line.long 0x0 "ICSCR,Slave Control Register" bitfld.long 0x0 4. "SCSS,Slave Clock Stretch Select (V3U only)" "0: Clock Stretch is in front of Acknowledgement,1: Clock Stretch is next to Non Acknowledgement" bitfld.long 0x0 3. "SDBS,Slave Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" newline bitfld.long 0x0 2. "SIE,Slave Interface Enable" "0,1" bitfld.long 0x0 1. "GCAE,General Call Acknowledgement Enable" "0,1" newline bitfld.long 0x0 0. "FNA,Forced Non Acknowledgement" "0,1" line.long 0x4 "ICMCR,Master Control Register" bitfld.long 0x4 7. "MDBS,Master Data Buffer Select" "0: Setting prohibited,1: Single-buffer mode" bitfld.long 0x4 6. "FSCL,Forced SCL" "0,1" newline bitfld.long 0x4 5. "FSDA,Forced SDA" "0,1" bitfld.long 0x4 4. "OBPC,Override Bus Pin Control" "0,1" newline bitfld.long 0x4 3. "MIE,Master Interface Enable" "0,1" bitfld.long 0x4 2. "TSBE,Start Byte Transmission Enable" "0,1" newline bitfld.long 0x4 1. "FSB,Forced Stop onto the Bus" "0,1" bitfld.long 0x4 0. "ESG,Enable Start Generation" "0,1" line.long 0x8 "ICSSR,Bits 0 to 4 among the status bits in the slave status register are cleared by writing 0 to the respective status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and STM bits)." rbitfld.long 0x8 6. "GCAR,General Call Address Received" "0,1" rbitfld.long 0x8 5. "STM,Slave Transmit Mode" "0,1" newline bitfld.long 0x8 4. "SSR,Slave Stop Received" "0,1" bitfld.long 0x8 3. "SDE,Slave Data Empty" "0,1" newline bitfld.long 0x8 2. "SDT,Slave Data Transmitted" "0,1" bitfld.long 0x8 1. "SDR,Slave Data Received" "0,1" newline bitfld.long 0x8 0. "SAR,Slave Address Received" "0,1" line.long 0xC "ICMSR,The status bits (bits 0 to 6) in the master status register are cleared by writing 0 to the respective status bit positions. The individual status bits are held 1 until a reset by writing 0 to the appropriate bit position." bitfld.long 0xC 6. "MNR,Master NACK Received" "0,1" bitfld.long 0xC 5. "MAL,Master Arbitration Lost" "0,1" newline bitfld.long 0xC 4. "MST,Master Stop Transmitted" "0,1" bitfld.long 0xC 3. "MDE,Master Data Empty" "0,1" newline bitfld.long 0xC 2. "MDT,Master Data Transmitted" "0,1" bitfld.long 0xC 1. "MDR,Master Data Received" "0,1" newline bitfld.long 0xC 0. "MAT,Master Address Transmitted" "0,1" line.long 0x10 "ICSIER,Slave Interrupt Enable Register" bitfld.long 0x10 4. "SSRE,Slave Stop Received Interrupt Enable" "0: Disables the SSR interrupt,1: Enables the SSR interrupt" bitfld.long 0x10 3. "SDEE,Slave Data Empty Interrupt Enable" "0: Disables the SDE interrupt,1: Enables the SDE interrupt" newline bitfld.long 0x10 2. "SDTE,Slave Data Transmitted Interrupt Enable" "0: Disables the SDT interrupt,1: Enables the SDT interrupt" bitfld.long 0x10 1. "SDRE,Slave Data Received Interrupt Enable" "0: Disables the SDR interrupt,1: Enables the SDR interrupt" newline bitfld.long 0x10 0. "SARE,Slave Address Received Interrupt Enable" "0: Disables the SAR interrupt,1: Enables the SAR interrupt" line.long 0x14 "ICMIER,Master Interrupt Enable Register" bitfld.long 0x14 6. "MNRE,Master NACK Received Interrupt Enable" "0: Disables the MNR interrupt,1: Enables the MNR interrupt" bitfld.long 0x14 5. "MALE,Master Arbitration Lost Interrupt Enable" "0: Disables the MAL interrupt,1: Enables the MAL interrupt" newline bitfld.long 0x14 4. "MSTE,Master Stop Transmitted Interrupt Enable" "0: Disables the MST interrupt,1: Enables the MST interrupt" bitfld.long 0x14 3. "MDEE,Master Data Empty Interrupt Enable" "0: Disables the MDE interrupt,1: Enables the MDE interrupt" newline bitfld.long 0x14 2. "MDTE,Master Data Transmitted Interrupt Enable" "0: Disables the MDT interrupt,1: Enables the MDT interrupt" bitfld.long 0x14 1. "MDRE,Master Data Received Interrupt Enable" "0: Disables the MDR interrupt,1: Enables the MDR interrupt" newline bitfld.long 0x14 0. "MATE,Master Address Transmitted Interrupt Enable" "0: Disables the MAT interrupt,1: Enables the MAT interrupt" line.long 0x18 "ICCCR,Clock Control Register" hexmask.long.byte 0x18 3.--8. 1. "SCGD,SCL Clock Generation Divider" bitfld.long 0x18 0.--2. "CDF,Clock Division Factor" "?,1: I2C internal clock frequency calculation,?,?,?,?,?,?" line.long 0x1C "ICSAR,Slave Address Register" hexmask.long.byte 0x1C 0.--6. 1. "SADD0_6 to SADD0_0,Slave Address" line.long 0x20 "ICMAR,Master Address Register" hexmask.long.byte 0x20 1.--7. 1. "SADD1_6 to SADD1_0,Slave Address" bitfld.long 0x20 0. "STM1,Slave Transfer Mode" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "ICRXD,Receive Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Read Receive Data" wgroup.long 0x24++0x3 line.long 0x0 "ICTXD,Transmit Data Register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Write Transmit Data" group.long 0x28++0x7 line.long 0x0 "ICCCR2,Clock Control Register 2" bitfld.long 0x0 7. "FMPE,FM+ Enable (V3U only)" "0: OD buffer is Standard / Fast mode,1: OD buffer is Fast mode+" bitfld.long 0x0 2. "CDFD,CDF Disable" "0,1" newline bitfld.long 0x0 1. "HLSE,HIGH/LOW Separate Control Enable" "0,1" bitfld.long 0x0 0. "SME,SCL Mask Enable" "0,1" line.long 0x4 "ICMPR,SCL Mask Control Register" hexmask.long.byte 0x4 0.--7. 1. "SMD,SCL Mask Division" group.long 0x3C++0x3 line.long 0x0 "ICDMAER,DMA Enable Register" hexmask.long.byte 0x0 24.--31. 1. "MDMACTSZ,[H3 M3-W V3M D3 M3-N]" hexmask.long.byte 0x0 16.--23. 1. "RMDMATSZ,[H3 M3-W V3M D3 M3-N]" newline hexmask.long.byte 0x0 8.--15. 1. "TMDMATSZ,[H3 M3-W V3M D3 M3-N]" bitfld.long 0x0 7. "TMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Transmitted mode,1: Enables DMA Continuous Transmitted mode" newline bitfld.long 0x0 6. "RMDMACE,[H3 M3-W V3M D3 M3-N]" "0: Disables DMA Continuous Received mode,1: Enables DMA Continuous Received mode" bitfld.long 0x0 3. "RSDMAE,DMA Slave Received Enable" "0: Disables DMA Slave Received Mode,1: Enables DMA Slave Received Mode" newline bitfld.long 0x0 2. "TSDMAE,DMA Slave Transmitted Enable" "0: Disables DMA Slave Transmitted Mode,1: Enables DMA Slave Transmitted Mode" bitfld.long 0x0 1. "RMDMAE,DMA Master Received Enable" "0: Disables DMA Master Received Mode,1: Enables DMA Master Received Mode" newline bitfld.long 0x0 0. "TMDMAE,DMA Master Transmitted Enable" "0: Disables DMA Master Transmitted Mode,1: Enables DMA Master Transmitted Mode" group.long 0x38++0x3 line.long 0x0 "ICFBSCR,First Bit Setup Cycle Register" hexmask.long.byte 0x0 24.--28. 1. "SRFBSC_4 to SRFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." hexmask.long.byte 0x0 16.--20. 1. "STFBSC_4 to STFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL." newline hexmask.long.byte 0x0 0.--4. 1. "FBSC_4 toFBSC_0,Setting the delay time of the 1st data bit between SDA and SCL" tree.end tree.end tree "INTC" base ad:0xFFEA0000 wgroup.long 0x0++0x3 line.long 0x0 "IMNTRSESR,This register shows secure access error status." bitfld.long 0x0 0. "SEC_ERR,-" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "IMNTRESADDR,This register shows Slave register address when occurred secure access error." hexmask.long.word 0x0 0.--15. 1. "ERR_S_ADDR,-" group.long 0x1000++0x3 line.long 0x0 "IMNTRCCR,INTC-Monitor Counter Control Register" hexmask.long.word 0x0 16.--31. 1. "KEYCODE,-" hexmask.long.byte 0x0 0.--3. 1. "IMNTR_CLK,-" group.long 0x2000++0xF1F line.long 0x0 "IMNTRCR0,INTC-Monitor Control Register 0" hexmask.long.word 0x0 16.--31. 1. "KEYCODE,-" bitfld.long 0x0 7. "NUM1_EN,-" "0,1" bitfld.long 0x0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x0 4. "CNT_RESET,-" "0,1" bitfld.long 0x0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x0 0. "WAIT_SET,-" "0,1" line.long 0x4 "IMNTRCR1,INTC-Monitor Control Register 1" hexmask.long.word 0x4 16.--31. 1. "KEYCODE,-" bitfld.long 0x4 7. "NUM1_EN,-" "0,1" bitfld.long 0x4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4 4. "CNT_RESET,-" "0,1" bitfld.long 0x4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4 0. "WAIT_SET,-" "0,1" line.long 0x8 "IMNTRCR2,INTC-Monitor Control Register 2" hexmask.long.word 0x8 16.--31. 1. "KEYCODE,-" bitfld.long 0x8 7. "NUM1_EN,-" "0,1" bitfld.long 0x8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8 4. "CNT_RESET,-" "0,1" bitfld.long 0x8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8 0. "WAIT_SET,-" "0,1" line.long 0xC "IMNTRCR3,INTC-Monitor Control Register 3" hexmask.long.word 0xC 16.--31. 1. "KEYCODE,-" bitfld.long 0xC 7. "NUM1_EN,-" "0,1" bitfld.long 0xC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC 4. "CNT_RESET,-" "0,1" bitfld.long 0xC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC 0. "WAIT_SET,-" "0,1" line.long 0x10 "IMNTRCR4,INTC-Monitor Control Register 4" hexmask.long.word 0x10 16.--31. 1. "KEYCODE,-" bitfld.long 0x10 7. "NUM1_EN,-" "0,1" bitfld.long 0x10 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x10 4. "CNT_RESET,-" "0,1" bitfld.long 0x10 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x10 1. "IMNTR_EN,-" "0,1" bitfld.long 0x10 0. "WAIT_SET,-" "0,1" line.long 0x14 "IMNTRCR5,INTC-Monitor Control Register 5" hexmask.long.word 0x14 16.--31. 1. "KEYCODE,-" bitfld.long 0x14 7. "NUM1_EN,-" "0,1" bitfld.long 0x14 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x14 4. "CNT_RESET,-" "0,1" bitfld.long 0x14 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x14 1. "IMNTR_EN,-" "0,1" bitfld.long 0x14 0. "WAIT_SET,-" "0,1" line.long 0x18 "IMNTRCR6,INTC-Monitor Control Register 6" hexmask.long.word 0x18 16.--31. 1. "KEYCODE,-" bitfld.long 0x18 7. "NUM1_EN,-" "0,1" bitfld.long 0x18 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x18 4. "CNT_RESET,-" "0,1" bitfld.long 0x18 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x18 1. "IMNTR_EN,-" "0,1" bitfld.long 0x18 0. "WAIT_SET,-" "0,1" line.long 0x1C "IMNTRCR7,INTC-Monitor Control Register 7" hexmask.long.word 0x1C 16.--31. 1. "KEYCODE,-" bitfld.long 0x1C 7. "NUM1_EN,-" "0,1" bitfld.long 0x1C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1C 4. "CNT_RESET,-" "0,1" bitfld.long 0x1C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1C 0. "WAIT_SET,-" "0,1" line.long 0x20 "IMNTRCR8,INTC-Monitor Control Register 8" hexmask.long.word 0x20 16.--31. 1. "KEYCODE,-" bitfld.long 0x20 7. "NUM1_EN,-" "0,1" bitfld.long 0x20 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x20 4. "CNT_RESET,-" "0,1" bitfld.long 0x20 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x20 1. "IMNTR_EN,-" "0,1" bitfld.long 0x20 0. "WAIT_SET,-" "0,1" line.long 0x24 "IMNTRCR9,INTC-Monitor Control Register 9" hexmask.long.word 0x24 16.--31. 1. "KEYCODE,-" bitfld.long 0x24 7. "NUM1_EN,-" "0,1" bitfld.long 0x24 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x24 4. "CNT_RESET,-" "0,1" bitfld.long 0x24 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x24 1. "IMNTR_EN,-" "0,1" bitfld.long 0x24 0. "WAIT_SET,-" "0,1" line.long 0x28 "IMNTRCR10,INTC-Monitor Control Register 10" hexmask.long.word 0x28 16.--31. 1. "KEYCODE,-" bitfld.long 0x28 7. "NUM1_EN,-" "0,1" bitfld.long 0x28 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x28 4. "CNT_RESET,-" "0,1" bitfld.long 0x28 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x28 1. "IMNTR_EN,-" "0,1" bitfld.long 0x28 0. "WAIT_SET,-" "0,1" line.long 0x2C "IMNTRCR11,INTC-Monitor Control Register 11" hexmask.long.word 0x2C 16.--31. 1. "KEYCODE,-" bitfld.long 0x2C 7. "NUM1_EN,-" "0,1" bitfld.long 0x2C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2C 4. "CNT_RESET,-" "0,1" bitfld.long 0x2C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2C 0. "WAIT_SET,-" "0,1" line.long 0x30 "IMNTRCR12,INTC-Monitor Control Register 12" hexmask.long.word 0x30 16.--31. 1. "KEYCODE,-" bitfld.long 0x30 7. "NUM1_EN,-" "0,1" bitfld.long 0x30 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x30 4. "CNT_RESET,-" "0,1" bitfld.long 0x30 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x30 1. "IMNTR_EN,-" "0,1" bitfld.long 0x30 0. "WAIT_SET,-" "0,1" line.long 0x34 "IMNTRCR13,INTC-Monitor Control Register 13" hexmask.long.word 0x34 16.--31. 1. "KEYCODE,-" bitfld.long 0x34 7. "NUM1_EN,-" "0,1" bitfld.long 0x34 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x34 4. "CNT_RESET,-" "0,1" bitfld.long 0x34 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x34 1. "IMNTR_EN,-" "0,1" bitfld.long 0x34 0. "WAIT_SET,-" "0,1" line.long 0x38 "IMNTRCR14,INTC-Monitor Control Register 14" hexmask.long.word 0x38 16.--31. 1. "KEYCODE,-" bitfld.long 0x38 7. "NUM1_EN,-" "0,1" bitfld.long 0x38 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x38 4. "CNT_RESET,-" "0,1" bitfld.long 0x38 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x38 1. "IMNTR_EN,-" "0,1" bitfld.long 0x38 0. "WAIT_SET,-" "0,1" line.long 0x3C "IMNTRCR15,INTC-Monitor Control Register 15" hexmask.long.word 0x3C 16.--31. 1. "KEYCODE,-" bitfld.long 0x3C 7. "NUM1_EN,-" "0,1" bitfld.long 0x3C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3C 4. "CNT_RESET,-" "0,1" bitfld.long 0x3C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3C 0. "WAIT_SET,-" "0,1" line.long 0x40 "IMNTRCR16,INTC-Monitor Control Register 16" hexmask.long.word 0x40 16.--31. 1. "KEYCODE,-" bitfld.long 0x40 7. "NUM1_EN,-" "0,1" bitfld.long 0x40 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x40 4. "CNT_RESET,-" "0,1" bitfld.long 0x40 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x40 1. "IMNTR_EN,-" "0,1" bitfld.long 0x40 0. "WAIT_SET,-" "0,1" line.long 0x44 "IMNTRCR17,INTC-Monitor Control Register 17" hexmask.long.word 0x44 16.--31. 1. "KEYCODE,-" bitfld.long 0x44 7. "NUM1_EN,-" "0,1" bitfld.long 0x44 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x44 4. "CNT_RESET,-" "0,1" bitfld.long 0x44 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x44 1. "IMNTR_EN,-" "0,1" bitfld.long 0x44 0. "WAIT_SET,-" "0,1" line.long 0x48 "IMNTRCR18,INTC-Monitor Control Register 18" hexmask.long.word 0x48 16.--31. 1. "KEYCODE,-" bitfld.long 0x48 7. "NUM1_EN,-" "0,1" bitfld.long 0x48 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x48 4. "CNT_RESET,-" "0,1" bitfld.long 0x48 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x48 1. "IMNTR_EN,-" "0,1" bitfld.long 0x48 0. "WAIT_SET,-" "0,1" line.long 0x4C "IMNTRCR19,INTC-Monitor Control Register 19" hexmask.long.word 0x4C 16.--31. 1. "KEYCODE,-" bitfld.long 0x4C 7. "NUM1_EN,-" "0,1" bitfld.long 0x4C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4C 4. "CNT_RESET,-" "0,1" bitfld.long 0x4C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4C 0. "WAIT_SET,-" "0,1" line.long 0x50 "IMNTRCR20,INTC-Monitor Control Register 20" hexmask.long.word 0x50 16.--31. 1. "KEYCODE,-" bitfld.long 0x50 7. "NUM1_EN,-" "0,1" bitfld.long 0x50 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x50 4. "CNT_RESET,-" "0,1" bitfld.long 0x50 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x50 1. "IMNTR_EN,-" "0,1" bitfld.long 0x50 0. "WAIT_SET,-" "0,1" line.long 0x54 "IMNTRCR21,INTC-Monitor Control Register 21" hexmask.long.word 0x54 16.--31. 1. "KEYCODE,-" bitfld.long 0x54 7. "NUM1_EN,-" "0,1" bitfld.long 0x54 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x54 4. "CNT_RESET,-" "0,1" bitfld.long 0x54 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x54 1. "IMNTR_EN,-" "0,1" bitfld.long 0x54 0. "WAIT_SET,-" "0,1" line.long 0x58 "IMNTRCR22,INTC-Monitor Control Register 22" hexmask.long.word 0x58 16.--31. 1. "KEYCODE,-" bitfld.long 0x58 7. "NUM1_EN,-" "0,1" bitfld.long 0x58 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x58 4. "CNT_RESET,-" "0,1" bitfld.long 0x58 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x58 1. "IMNTR_EN,-" "0,1" bitfld.long 0x58 0. "WAIT_SET,-" "0,1" line.long 0x5C "IMNTRCR23,INTC-Monitor Control Register 23" hexmask.long.word 0x5C 16.--31. 1. "KEYCODE,-" bitfld.long 0x5C 7. "NUM1_EN,-" "0,1" bitfld.long 0x5C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5C 4. "CNT_RESET,-" "0,1" bitfld.long 0x5C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5C 0. "WAIT_SET,-" "0,1" line.long 0x60 "IMNTRCR24,INTC-Monitor Control Register 24" hexmask.long.word 0x60 16.--31. 1. "KEYCODE,-" bitfld.long 0x60 7. "NUM1_EN,-" "0,1" bitfld.long 0x60 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x60 4. "CNT_RESET,-" "0,1" bitfld.long 0x60 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x60 1. "IMNTR_EN,-" "0,1" bitfld.long 0x60 0. "WAIT_SET,-" "0,1" line.long 0x64 "IMNTRCR25,INTC-Monitor Control Register 25" hexmask.long.word 0x64 16.--31. 1. "KEYCODE,-" bitfld.long 0x64 7. "NUM1_EN,-" "0,1" bitfld.long 0x64 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x64 4. "CNT_RESET,-" "0,1" bitfld.long 0x64 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x64 1. "IMNTR_EN,-" "0,1" bitfld.long 0x64 0. "WAIT_SET,-" "0,1" line.long 0x68 "IMNTRCR26,INTC-Monitor Control Register 26" hexmask.long.word 0x68 16.--31. 1. "KEYCODE,-" bitfld.long 0x68 7. "NUM1_EN,-" "0,1" bitfld.long 0x68 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x68 4. "CNT_RESET,-" "0,1" bitfld.long 0x68 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x68 1. "IMNTR_EN,-" "0,1" bitfld.long 0x68 0. "WAIT_SET,-" "0,1" line.long 0x6C "IMNTRCR27,INTC-Monitor Control Register 27" hexmask.long.word 0x6C 16.--31. 1. "KEYCODE,-" bitfld.long 0x6C 7. "NUM1_EN,-" "0,1" bitfld.long 0x6C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6C 4. "CNT_RESET,-" "0,1" bitfld.long 0x6C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6C 0. "WAIT_SET,-" "0,1" line.long 0x70 "IMNTRCR28,INTC-Monitor Control Register 28" hexmask.long.word 0x70 16.--31. 1. "KEYCODE,-" bitfld.long 0x70 7. "NUM1_EN,-" "0,1" bitfld.long 0x70 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x70 4. "CNT_RESET,-" "0,1" bitfld.long 0x70 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x70 1. "IMNTR_EN,-" "0,1" bitfld.long 0x70 0. "WAIT_SET,-" "0,1" line.long 0x74 "IMNTRCR29,INTC-Monitor Control Register 29" hexmask.long.word 0x74 16.--31. 1. "KEYCODE,-" bitfld.long 0x74 7. "NUM1_EN,-" "0,1" bitfld.long 0x74 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x74 4. "CNT_RESET,-" "0,1" bitfld.long 0x74 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x74 1. "IMNTR_EN,-" "0,1" bitfld.long 0x74 0. "WAIT_SET,-" "0,1" line.long 0x78 "IMNTRCR30,INTC-Monitor Control Register 30" hexmask.long.word 0x78 16.--31. 1. "KEYCODE,-" bitfld.long 0x78 7. "NUM1_EN,-" "0,1" bitfld.long 0x78 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x78 4. "CNT_RESET,-" "0,1" bitfld.long 0x78 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x78 1. "IMNTR_EN,-" "0,1" bitfld.long 0x78 0. "WAIT_SET,-" "0,1" line.long 0x7C "IMNTRCR31,INTC-Monitor Control Register 31" hexmask.long.word 0x7C 16.--31. 1. "KEYCODE,-" bitfld.long 0x7C 7. "NUM1_EN,-" "0,1" bitfld.long 0x7C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7C 4. "CNT_RESET,-" "0,1" bitfld.long 0x7C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7C 0. "WAIT_SET,-" "0,1" line.long 0x80 "IMNTRCR32,INTC-Monitor Control Register 32" hexmask.long.word 0x80 16.--31. 1. "KEYCODE,-" bitfld.long 0x80 7. "NUM1_EN,-" "0,1" bitfld.long 0x80 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x80 4. "CNT_RESET,-" "0,1" bitfld.long 0x80 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x80 1. "IMNTR_EN,-" "0,1" bitfld.long 0x80 0. "WAIT_SET,-" "0,1" line.long 0x84 "IMNTRCR33,INTC-Monitor Control Register 33" hexmask.long.word 0x84 16.--31. 1. "KEYCODE,-" bitfld.long 0x84 7. "NUM1_EN,-" "0,1" bitfld.long 0x84 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x84 4. "CNT_RESET,-" "0,1" bitfld.long 0x84 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x84 1. "IMNTR_EN,-" "0,1" bitfld.long 0x84 0. "WAIT_SET,-" "0,1" line.long 0x88 "IMNTRCR34,INTC-Monitor Control Register 34" hexmask.long.word 0x88 16.--31. 1. "KEYCODE,-" bitfld.long 0x88 7. "NUM1_EN,-" "0,1" bitfld.long 0x88 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x88 4. "CNT_RESET,-" "0,1" bitfld.long 0x88 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x88 1. "IMNTR_EN,-" "0,1" bitfld.long 0x88 0. "WAIT_SET,-" "0,1" line.long 0x8C "IMNTRCR35,INTC-Monitor Control Register 35" hexmask.long.word 0x8C 16.--31. 1. "KEYCODE,-" bitfld.long 0x8C 7. "NUM1_EN,-" "0,1" bitfld.long 0x8C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8C 4. "CNT_RESET,-" "0,1" bitfld.long 0x8C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8C 0. "WAIT_SET,-" "0,1" line.long 0x90 "IMNTRCR36,INTC-Monitor Control Register 36" hexmask.long.word 0x90 16.--31. 1. "KEYCODE,-" bitfld.long 0x90 7. "NUM1_EN,-" "0,1" bitfld.long 0x90 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x90 4. "CNT_RESET,-" "0,1" bitfld.long 0x90 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x90 1. "IMNTR_EN,-" "0,1" bitfld.long 0x90 0. "WAIT_SET,-" "0,1" line.long 0x94 "IMNTRCR37,INTC-Monitor Control Register 37" hexmask.long.word 0x94 16.--31. 1. "KEYCODE,-" bitfld.long 0x94 7. "NUM1_EN,-" "0,1" bitfld.long 0x94 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x94 4. "CNT_RESET,-" "0,1" bitfld.long 0x94 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x94 1. "IMNTR_EN,-" "0,1" bitfld.long 0x94 0. "WAIT_SET,-" "0,1" line.long 0x98 "IMNTRCR38,INTC-Monitor Control Register 38" hexmask.long.word 0x98 16.--31. 1. "KEYCODE,-" bitfld.long 0x98 7. "NUM1_EN,-" "0,1" bitfld.long 0x98 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x98 4. "CNT_RESET,-" "0,1" bitfld.long 0x98 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x98 1. "IMNTR_EN,-" "0,1" bitfld.long 0x98 0. "WAIT_SET,-" "0,1" line.long 0x9C "IMNTRCR39,INTC-Monitor Control Register 39" hexmask.long.word 0x9C 16.--31. 1. "KEYCODE,-" bitfld.long 0x9C 7. "NUM1_EN,-" "0,1" bitfld.long 0x9C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9C 4. "CNT_RESET,-" "0,1" bitfld.long 0x9C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9C 0. "WAIT_SET,-" "0,1" line.long 0xA0 "IMNTRCR40,INTC-Monitor Control Register 40" hexmask.long.word 0xA0 16.--31. 1. "KEYCODE,-" bitfld.long 0xA0 7. "NUM1_EN,-" "0,1" bitfld.long 0xA0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA0 4. "CNT_RESET,-" "0,1" bitfld.long 0xA0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA0 0. "WAIT_SET,-" "0,1" line.long 0xA4 "IMNTRCR41,INTC-Monitor Control Register 41" hexmask.long.word 0xA4 16.--31. 1. "KEYCODE,-" bitfld.long 0xA4 7. "NUM1_EN,-" "0,1" bitfld.long 0xA4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA4 4. "CNT_RESET,-" "0,1" bitfld.long 0xA4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA4 0. "WAIT_SET,-" "0,1" line.long 0xA8 "IMNTRCR42,INTC-Monitor Control Register 42" hexmask.long.word 0xA8 16.--31. 1. "KEYCODE,-" bitfld.long 0xA8 7. "NUM1_EN,-" "0,1" bitfld.long 0xA8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA8 4. "CNT_RESET,-" "0,1" bitfld.long 0xA8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA8 0. "WAIT_SET,-" "0,1" line.long 0xAC "IMNTRCR43,INTC-Monitor Control Register 43" hexmask.long.word 0xAC 16.--31. 1. "KEYCODE,-" bitfld.long 0xAC 7. "NUM1_EN,-" "0,1" bitfld.long 0xAC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAC 4. "CNT_RESET,-" "0,1" bitfld.long 0xAC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAC 0. "WAIT_SET,-" "0,1" line.long 0xB0 "IMNTRCR44,INTC-Monitor Control Register 44" hexmask.long.word 0xB0 16.--31. 1. "KEYCODE,-" bitfld.long 0xB0 7. "NUM1_EN,-" "0,1" bitfld.long 0xB0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB0 4. "CNT_RESET,-" "0,1" bitfld.long 0xB0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB0 0. "WAIT_SET,-" "0,1" line.long 0xB4 "IMNTRCR45,INTC-Monitor Control Register 45" hexmask.long.word 0xB4 16.--31. 1. "KEYCODE,-" bitfld.long 0xB4 7. "NUM1_EN,-" "0,1" bitfld.long 0xB4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB4 4. "CNT_RESET,-" "0,1" bitfld.long 0xB4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB4 0. "WAIT_SET,-" "0,1" line.long 0xB8 "IMNTRCR46,INTC-Monitor Control Register 46" hexmask.long.word 0xB8 16.--31. 1. "KEYCODE,-" bitfld.long 0xB8 7. "NUM1_EN,-" "0,1" bitfld.long 0xB8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB8 4. "CNT_RESET,-" "0,1" bitfld.long 0xB8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB8 0. "WAIT_SET,-" "0,1" line.long 0xBC "IMNTRCR47,INTC-Monitor Control Register 47" hexmask.long.word 0xBC 16.--31. 1. "KEYCODE,-" bitfld.long 0xBC 7. "NUM1_EN,-" "0,1" bitfld.long 0xBC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBC 4. "CNT_RESET,-" "0,1" bitfld.long 0xBC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBC 0. "WAIT_SET,-" "0,1" line.long 0xC0 "IMNTRCR48,INTC-Monitor Control Register 48" hexmask.long.word 0xC0 16.--31. 1. "KEYCODE,-" bitfld.long 0xC0 7. "NUM1_EN,-" "0,1" bitfld.long 0xC0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC0 4. "CNT_RESET,-" "0,1" bitfld.long 0xC0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC0 0. "WAIT_SET,-" "0,1" line.long 0xC4 "IMNTRCR49,INTC-Monitor Control Register 49" hexmask.long.word 0xC4 16.--31. 1. "KEYCODE,-" bitfld.long 0xC4 7. "NUM1_EN,-" "0,1" bitfld.long 0xC4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC4 4. "CNT_RESET,-" "0,1" bitfld.long 0xC4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC4 0. "WAIT_SET,-" "0,1" line.long 0xC8 "IMNTRCR50,INTC-Monitor Control Register 50" hexmask.long.word 0xC8 16.--31. 1. "KEYCODE,-" bitfld.long 0xC8 7. "NUM1_EN,-" "0,1" bitfld.long 0xC8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC8 4. "CNT_RESET,-" "0,1" bitfld.long 0xC8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC8 0. "WAIT_SET,-" "0,1" line.long 0xCC "IMNTRCR51,INTC-Monitor Control Register 51" hexmask.long.word 0xCC 16.--31. 1. "KEYCODE,-" bitfld.long 0xCC 7. "NUM1_EN,-" "0,1" bitfld.long 0xCC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCC 4. "CNT_RESET,-" "0,1" bitfld.long 0xCC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCC 0. "WAIT_SET,-" "0,1" line.long 0xD0 "IMNTRCR52,INTC-Monitor Control Register 52" hexmask.long.word 0xD0 16.--31. 1. "KEYCODE,-" bitfld.long 0xD0 7. "NUM1_EN,-" "0,1" bitfld.long 0xD0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD0 4. "CNT_RESET,-" "0,1" bitfld.long 0xD0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD0 0. "WAIT_SET,-" "0,1" line.long 0xD4 "IMNTRCR53,INTC-Monitor Control Register 53" hexmask.long.word 0xD4 16.--31. 1. "KEYCODE,-" bitfld.long 0xD4 7. "NUM1_EN,-" "0,1" bitfld.long 0xD4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD4 4. "CNT_RESET,-" "0,1" bitfld.long 0xD4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD4 0. "WAIT_SET,-" "0,1" line.long 0xD8 "IMNTRCR54,INTC-Monitor Control Register 54" hexmask.long.word 0xD8 16.--31. 1. "KEYCODE,-" bitfld.long 0xD8 7. "NUM1_EN,-" "0,1" bitfld.long 0xD8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD8 4. "CNT_RESET,-" "0,1" bitfld.long 0xD8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD8 0. "WAIT_SET,-" "0,1" line.long 0xDC "IMNTRCR55,INTC-Monitor Control Register 55" hexmask.long.word 0xDC 16.--31. 1. "KEYCODE,-" bitfld.long 0xDC 7. "NUM1_EN,-" "0,1" bitfld.long 0xDC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDC 4. "CNT_RESET,-" "0,1" bitfld.long 0xDC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDC 0. "WAIT_SET,-" "0,1" line.long 0xE0 "IMNTRCR56,INTC-Monitor Control Register 56" hexmask.long.word 0xE0 16.--31. 1. "KEYCODE,-" bitfld.long 0xE0 7. "NUM1_EN,-" "0,1" bitfld.long 0xE0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE0 4. "CNT_RESET,-" "0,1" bitfld.long 0xE0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE0 0. "WAIT_SET,-" "0,1" line.long 0xE4 "IMNTRCR57,INTC-Monitor Control Register 57" hexmask.long.word 0xE4 16.--31. 1. "KEYCODE,-" bitfld.long 0xE4 7. "NUM1_EN,-" "0,1" bitfld.long 0xE4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE4 4. "CNT_RESET,-" "0,1" bitfld.long 0xE4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE4 0. "WAIT_SET,-" "0,1" line.long 0xE8 "IMNTRCR58,INTC-Monitor Control Register 58" hexmask.long.word 0xE8 16.--31. 1. "KEYCODE,-" bitfld.long 0xE8 7. "NUM1_EN,-" "0,1" bitfld.long 0xE8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE8 4. "CNT_RESET,-" "0,1" bitfld.long 0xE8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE8 0. "WAIT_SET,-" "0,1" line.long 0xEC "IMNTRCR59,INTC-Monitor Control Register 59" hexmask.long.word 0xEC 16.--31. 1. "KEYCODE,-" bitfld.long 0xEC 7. "NUM1_EN,-" "0,1" bitfld.long 0xEC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEC 4. "CNT_RESET,-" "0,1" bitfld.long 0xEC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEC 0. "WAIT_SET,-" "0,1" line.long 0xF0 "IMNTRCR60,INTC-Monitor Control Register 60" hexmask.long.word 0xF0 16.--31. 1. "KEYCODE,-" bitfld.long 0xF0 7. "NUM1_EN,-" "0,1" bitfld.long 0xF0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF0 4. "CNT_RESET,-" "0,1" bitfld.long 0xF0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF0 0. "WAIT_SET,-" "0,1" line.long 0xF4 "IMNTRCR61,INTC-Monitor Control Register 61" hexmask.long.word 0xF4 16.--31. 1. "KEYCODE,-" bitfld.long 0xF4 7. "NUM1_EN,-" "0,1" bitfld.long 0xF4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF4 4. "CNT_RESET,-" "0,1" bitfld.long 0xF4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF4 0. "WAIT_SET,-" "0,1" line.long 0xF8 "IMNTRCR62,INTC-Monitor Control Register 62" hexmask.long.word 0xF8 16.--31. 1. "KEYCODE,-" bitfld.long 0xF8 7. "NUM1_EN,-" "0,1" bitfld.long 0xF8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF8 4. "CNT_RESET,-" "0,1" bitfld.long 0xF8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF8 0. "WAIT_SET,-" "0,1" line.long 0xFC "IMNTRCR63,INTC-Monitor Control Register 63" hexmask.long.word 0xFC 16.--31. 1. "KEYCODE,-" bitfld.long 0xFC 7. "NUM1_EN,-" "0,1" bitfld.long 0xFC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xFC 4. "CNT_RESET,-" "0,1" bitfld.long 0xFC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xFC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xFC 0. "WAIT_SET,-" "0,1" line.long 0x100 "IMNTRCR64,INTC-Monitor Control Register 64" hexmask.long.word 0x100 16.--31. 1. "KEYCODE,-" bitfld.long 0x100 7. "NUM1_EN,-" "0,1" bitfld.long 0x100 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x100 4. "CNT_RESET,-" "0,1" bitfld.long 0x100 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x100 1. "IMNTR_EN,-" "0,1" bitfld.long 0x100 0. "WAIT_SET,-" "0,1" line.long 0x104 "IMNTRCR65,INTC-Monitor Control Register 65" hexmask.long.word 0x104 16.--31. 1. "KEYCODE,-" bitfld.long 0x104 7. "NUM1_EN,-" "0,1" bitfld.long 0x104 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x104 4. "CNT_RESET,-" "0,1" bitfld.long 0x104 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x104 1. "IMNTR_EN,-" "0,1" bitfld.long 0x104 0. "WAIT_SET,-" "0,1" line.long 0x108 "IMNTRCR66,INTC-Monitor Control Register 66" hexmask.long.word 0x108 16.--31. 1. "KEYCODE,-" bitfld.long 0x108 7. "NUM1_EN,-" "0,1" bitfld.long 0x108 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x108 4. "CNT_RESET,-" "0,1" bitfld.long 0x108 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x108 1. "IMNTR_EN,-" "0,1" bitfld.long 0x108 0. "WAIT_SET,-" "0,1" line.long 0x10C "IMNTRCR67,INTC-Monitor Control Register 67" hexmask.long.word 0x10C 16.--31. 1. "KEYCODE,-" bitfld.long 0x10C 7. "NUM1_EN,-" "0,1" bitfld.long 0x10C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x10C 4. "CNT_RESET,-" "0,1" bitfld.long 0x10C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x10C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x10C 0. "WAIT_SET,-" "0,1" line.long 0x110 "IMNTRCR68,INTC-Monitor Control Register 68" hexmask.long.word 0x110 16.--31. 1. "KEYCODE,-" bitfld.long 0x110 7. "NUM1_EN,-" "0,1" bitfld.long 0x110 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x110 4. "CNT_RESET,-" "0,1" bitfld.long 0x110 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x110 1. "IMNTR_EN,-" "0,1" bitfld.long 0x110 0. "WAIT_SET,-" "0,1" line.long 0x114 "IMNTRCR69,INTC-Monitor Control Register 69" hexmask.long.word 0x114 16.--31. 1. "KEYCODE,-" bitfld.long 0x114 7. "NUM1_EN,-" "0,1" bitfld.long 0x114 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x114 4. "CNT_RESET,-" "0,1" bitfld.long 0x114 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x114 1. "IMNTR_EN,-" "0,1" bitfld.long 0x114 0. "WAIT_SET,-" "0,1" line.long 0x118 "IMNTRCR70,INTC-Monitor Control Register 70" hexmask.long.word 0x118 16.--31. 1. "KEYCODE,-" bitfld.long 0x118 7. "NUM1_EN,-" "0,1" bitfld.long 0x118 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x118 4. "CNT_RESET,-" "0,1" bitfld.long 0x118 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x118 1. "IMNTR_EN,-" "0,1" bitfld.long 0x118 0. "WAIT_SET,-" "0,1" line.long 0x11C "IMNTRCR71,INTC-Monitor Control Register 71" hexmask.long.word 0x11C 16.--31. 1. "KEYCODE,-" bitfld.long 0x11C 7. "NUM1_EN,-" "0,1" bitfld.long 0x11C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x11C 4. "CNT_RESET,-" "0,1" bitfld.long 0x11C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x11C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x11C 0. "WAIT_SET,-" "0,1" line.long 0x120 "IMNTRCR72,INTC-Monitor Control Register 72" hexmask.long.word 0x120 16.--31. 1. "KEYCODE,-" bitfld.long 0x120 7. "NUM1_EN,-" "0,1" bitfld.long 0x120 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x120 4. "CNT_RESET,-" "0,1" bitfld.long 0x120 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x120 1. "IMNTR_EN,-" "0,1" bitfld.long 0x120 0. "WAIT_SET,-" "0,1" line.long 0x124 "IMNTRCR73,INTC-Monitor Control Register 73" hexmask.long.word 0x124 16.--31. 1. "KEYCODE,-" bitfld.long 0x124 7. "NUM1_EN,-" "0,1" bitfld.long 0x124 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x124 4. "CNT_RESET,-" "0,1" bitfld.long 0x124 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x124 1. "IMNTR_EN,-" "0,1" bitfld.long 0x124 0. "WAIT_SET,-" "0,1" line.long 0x128 "IMNTRCR74,INTC-Monitor Control Register 74" hexmask.long.word 0x128 16.--31. 1. "KEYCODE,-" bitfld.long 0x128 7. "NUM1_EN,-" "0,1" bitfld.long 0x128 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x128 4. "CNT_RESET,-" "0,1" bitfld.long 0x128 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x128 1. "IMNTR_EN,-" "0,1" bitfld.long 0x128 0. "WAIT_SET,-" "0,1" line.long 0x12C "IMNTRCR75,INTC-Monitor Control Register 75" hexmask.long.word 0x12C 16.--31. 1. "KEYCODE,-" bitfld.long 0x12C 7. "NUM1_EN,-" "0,1" bitfld.long 0x12C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x12C 4. "CNT_RESET,-" "0,1" bitfld.long 0x12C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x12C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x12C 0. "WAIT_SET,-" "0,1" line.long 0x130 "IMNTRCR76,INTC-Monitor Control Register 76" hexmask.long.word 0x130 16.--31. 1. "KEYCODE,-" bitfld.long 0x130 7. "NUM1_EN,-" "0,1" bitfld.long 0x130 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x130 4. "CNT_RESET,-" "0,1" bitfld.long 0x130 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x130 1. "IMNTR_EN,-" "0,1" bitfld.long 0x130 0. "WAIT_SET,-" "0,1" line.long 0x134 "IMNTRCR77,INTC-Monitor Control Register 77" hexmask.long.word 0x134 16.--31. 1. "KEYCODE,-" bitfld.long 0x134 7. "NUM1_EN,-" "0,1" bitfld.long 0x134 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x134 4. "CNT_RESET,-" "0,1" bitfld.long 0x134 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x134 1. "IMNTR_EN,-" "0,1" bitfld.long 0x134 0. "WAIT_SET,-" "0,1" line.long 0x138 "IMNTRCR78,INTC-Monitor Control Register 78" hexmask.long.word 0x138 16.--31. 1. "KEYCODE,-" bitfld.long 0x138 7. "NUM1_EN,-" "0,1" bitfld.long 0x138 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x138 4. "CNT_RESET,-" "0,1" bitfld.long 0x138 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x138 1. "IMNTR_EN,-" "0,1" bitfld.long 0x138 0. "WAIT_SET,-" "0,1" line.long 0x13C "IMNTRCR79,INTC-Monitor Control Register 79" hexmask.long.word 0x13C 16.--31. 1. "KEYCODE,-" bitfld.long 0x13C 7. "NUM1_EN,-" "0,1" bitfld.long 0x13C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x13C 4. "CNT_RESET,-" "0,1" bitfld.long 0x13C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x13C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x13C 0. "WAIT_SET,-" "0,1" line.long 0x140 "IMNTRCR80,INTC-Monitor Control Register 80" hexmask.long.word 0x140 16.--31. 1. "KEYCODE,-" bitfld.long 0x140 7. "NUM1_EN,-" "0,1" bitfld.long 0x140 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x140 4. "CNT_RESET,-" "0,1" bitfld.long 0x140 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x140 1. "IMNTR_EN,-" "0,1" bitfld.long 0x140 0. "WAIT_SET,-" "0,1" line.long 0x144 "IMNTRCR81,INTC-Monitor Control Register 81" hexmask.long.word 0x144 16.--31. 1. "KEYCODE,-" bitfld.long 0x144 7. "NUM1_EN,-" "0,1" bitfld.long 0x144 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x144 4. "CNT_RESET,-" "0,1" bitfld.long 0x144 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x144 1. "IMNTR_EN,-" "0,1" bitfld.long 0x144 0. "WAIT_SET,-" "0,1" line.long 0x148 "IMNTRCR82,INTC-Monitor Control Register 82" hexmask.long.word 0x148 16.--31. 1. "KEYCODE,-" bitfld.long 0x148 7. "NUM1_EN,-" "0,1" bitfld.long 0x148 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x148 4. "CNT_RESET,-" "0,1" bitfld.long 0x148 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x148 1. "IMNTR_EN,-" "0,1" bitfld.long 0x148 0. "WAIT_SET,-" "0,1" line.long 0x14C "IMNTRCR83,INTC-Monitor Control Register 83" hexmask.long.word 0x14C 16.--31. 1. "KEYCODE,-" bitfld.long 0x14C 7. "NUM1_EN,-" "0,1" bitfld.long 0x14C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x14C 4. "CNT_RESET,-" "0,1" bitfld.long 0x14C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x14C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x14C 0. "WAIT_SET,-" "0,1" line.long 0x150 "IMNTRCR84,INTC-Monitor Control Register 84" hexmask.long.word 0x150 16.--31. 1. "KEYCODE,-" bitfld.long 0x150 7. "NUM1_EN,-" "0,1" bitfld.long 0x150 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x150 4. "CNT_RESET,-" "0,1" bitfld.long 0x150 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x150 1. "IMNTR_EN,-" "0,1" bitfld.long 0x150 0. "WAIT_SET,-" "0,1" line.long 0x154 "IMNTRCR85,INTC-Monitor Control Register 85" hexmask.long.word 0x154 16.--31. 1. "KEYCODE,-" bitfld.long 0x154 7. "NUM1_EN,-" "0,1" bitfld.long 0x154 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x154 4. "CNT_RESET,-" "0,1" bitfld.long 0x154 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x154 1. "IMNTR_EN,-" "0,1" bitfld.long 0x154 0. "WAIT_SET,-" "0,1" line.long 0x158 "IMNTRCR86,INTC-Monitor Control Register 86" hexmask.long.word 0x158 16.--31. 1. "KEYCODE,-" bitfld.long 0x158 7. "NUM1_EN,-" "0,1" bitfld.long 0x158 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x158 4. "CNT_RESET,-" "0,1" bitfld.long 0x158 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x158 1. "IMNTR_EN,-" "0,1" bitfld.long 0x158 0. "WAIT_SET,-" "0,1" line.long 0x15C "IMNTRCR87,INTC-Monitor Control Register 87" hexmask.long.word 0x15C 16.--31. 1. "KEYCODE,-" bitfld.long 0x15C 7. "NUM1_EN,-" "0,1" bitfld.long 0x15C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x15C 4. "CNT_RESET,-" "0,1" bitfld.long 0x15C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x15C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x15C 0. "WAIT_SET,-" "0,1" line.long 0x160 "IMNTRCR88,INTC-Monitor Control Register 88" hexmask.long.word 0x160 16.--31. 1. "KEYCODE,-" bitfld.long 0x160 7. "NUM1_EN,-" "0,1" bitfld.long 0x160 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x160 4. "CNT_RESET,-" "0,1" bitfld.long 0x160 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x160 1. "IMNTR_EN,-" "0,1" bitfld.long 0x160 0. "WAIT_SET,-" "0,1" line.long 0x164 "IMNTRCR89,INTC-Monitor Control Register 89" hexmask.long.word 0x164 16.--31. 1. "KEYCODE,-" bitfld.long 0x164 7. "NUM1_EN,-" "0,1" bitfld.long 0x164 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x164 4. "CNT_RESET,-" "0,1" bitfld.long 0x164 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x164 1. "IMNTR_EN,-" "0,1" bitfld.long 0x164 0. "WAIT_SET,-" "0,1" line.long 0x168 "IMNTRCR90,INTC-Monitor Control Register 90" hexmask.long.word 0x168 16.--31. 1. "KEYCODE,-" bitfld.long 0x168 7. "NUM1_EN,-" "0,1" bitfld.long 0x168 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x168 4. "CNT_RESET,-" "0,1" bitfld.long 0x168 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x168 1. "IMNTR_EN,-" "0,1" bitfld.long 0x168 0. "WAIT_SET,-" "0,1" line.long 0x16C "IMNTRCR91,INTC-Monitor Control Register 91" hexmask.long.word 0x16C 16.--31. 1. "KEYCODE,-" bitfld.long 0x16C 7. "NUM1_EN,-" "0,1" bitfld.long 0x16C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x16C 4. "CNT_RESET,-" "0,1" bitfld.long 0x16C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x16C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x16C 0. "WAIT_SET,-" "0,1" line.long 0x170 "IMNTRCR92,INTC-Monitor Control Register 92" hexmask.long.word 0x170 16.--31. 1. "KEYCODE,-" bitfld.long 0x170 7. "NUM1_EN,-" "0,1" bitfld.long 0x170 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x170 4. "CNT_RESET,-" "0,1" bitfld.long 0x170 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x170 1. "IMNTR_EN,-" "0,1" bitfld.long 0x170 0. "WAIT_SET,-" "0,1" line.long 0x174 "IMNTRCR93,INTC-Monitor Control Register 93" hexmask.long.word 0x174 16.--31. 1. "KEYCODE,-" bitfld.long 0x174 7. "NUM1_EN,-" "0,1" bitfld.long 0x174 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x174 4. "CNT_RESET,-" "0,1" bitfld.long 0x174 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x174 1. "IMNTR_EN,-" "0,1" bitfld.long 0x174 0. "WAIT_SET,-" "0,1" line.long 0x178 "IMNTRCR94,INTC-Monitor Control Register 94" hexmask.long.word 0x178 16.--31. 1. "KEYCODE,-" bitfld.long 0x178 7. "NUM1_EN,-" "0,1" bitfld.long 0x178 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x178 4. "CNT_RESET,-" "0,1" bitfld.long 0x178 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x178 1. "IMNTR_EN,-" "0,1" bitfld.long 0x178 0. "WAIT_SET,-" "0,1" line.long 0x17C "IMNTRCR95,INTC-Monitor Control Register 95" hexmask.long.word 0x17C 16.--31. 1. "KEYCODE,-" bitfld.long 0x17C 7. "NUM1_EN,-" "0,1" bitfld.long 0x17C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x17C 4. "CNT_RESET,-" "0,1" bitfld.long 0x17C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x17C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x17C 0. "WAIT_SET,-" "0,1" line.long 0x180 "IMNTRCR96,INTC-Monitor Control Register 96" hexmask.long.word 0x180 16.--31. 1. "KEYCODE,-" bitfld.long 0x180 7. "NUM1_EN,-" "0,1" bitfld.long 0x180 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x180 4. "CNT_RESET,-" "0,1" bitfld.long 0x180 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x180 1. "IMNTR_EN,-" "0,1" bitfld.long 0x180 0. "WAIT_SET,-" "0,1" line.long 0x184 "IMNTRCR97,INTC-Monitor Control Register 97" hexmask.long.word 0x184 16.--31. 1. "KEYCODE,-" bitfld.long 0x184 7. "NUM1_EN,-" "0,1" bitfld.long 0x184 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x184 4. "CNT_RESET,-" "0,1" bitfld.long 0x184 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x184 1. "IMNTR_EN,-" "0,1" bitfld.long 0x184 0. "WAIT_SET,-" "0,1" line.long 0x188 "IMNTRCR98,INTC-Monitor Control Register 98" hexmask.long.word 0x188 16.--31. 1. "KEYCODE,-" bitfld.long 0x188 7. "NUM1_EN,-" "0,1" bitfld.long 0x188 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x188 4. "CNT_RESET,-" "0,1" bitfld.long 0x188 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x188 1. "IMNTR_EN,-" "0,1" bitfld.long 0x188 0. "WAIT_SET,-" "0,1" line.long 0x18C "IMNTRCR99,INTC-Monitor Control Register 99" hexmask.long.word 0x18C 16.--31. 1. "KEYCODE,-" bitfld.long 0x18C 7. "NUM1_EN,-" "0,1" bitfld.long 0x18C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x18C 4. "CNT_RESET,-" "0,1" bitfld.long 0x18C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x18C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x18C 0. "WAIT_SET,-" "0,1" line.long 0x190 "IMNTRCR100,INTC-Monitor Control Register 100" hexmask.long.word 0x190 16.--31. 1. "KEYCODE,-" bitfld.long 0x190 7. "NUM1_EN,-" "0,1" bitfld.long 0x190 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x190 4. "CNT_RESET,-" "0,1" bitfld.long 0x190 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x190 1. "IMNTR_EN,-" "0,1" bitfld.long 0x190 0. "WAIT_SET,-" "0,1" line.long 0x194 "IMNTRCR101,INTC-Monitor Control Register 101" hexmask.long.word 0x194 16.--31. 1. "KEYCODE,-" bitfld.long 0x194 7. "NUM1_EN,-" "0,1" bitfld.long 0x194 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x194 4. "CNT_RESET,-" "0,1" bitfld.long 0x194 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x194 1. "IMNTR_EN,-" "0,1" bitfld.long 0x194 0. "WAIT_SET,-" "0,1" line.long 0x198 "IMNTRCR102,INTC-Monitor Control Register 102" hexmask.long.word 0x198 16.--31. 1. "KEYCODE,-" bitfld.long 0x198 7. "NUM1_EN,-" "0,1" bitfld.long 0x198 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x198 4. "CNT_RESET,-" "0,1" bitfld.long 0x198 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x198 1. "IMNTR_EN,-" "0,1" bitfld.long 0x198 0. "WAIT_SET,-" "0,1" line.long 0x19C "IMNTRCR103,INTC-Monitor Control Register 103" hexmask.long.word 0x19C 16.--31. 1. "KEYCODE,-" bitfld.long 0x19C 7. "NUM1_EN,-" "0,1" bitfld.long 0x19C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x19C 4. "CNT_RESET,-" "0,1" bitfld.long 0x19C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x19C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x19C 0. "WAIT_SET,-" "0,1" line.long 0x1A0 "IMNTRCR104,INTC-Monitor Control Register 104" hexmask.long.word 0x1A0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1A0 7. "NUM1_EN,-" "0,1" bitfld.long 0x1A0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1A0 4. "CNT_RESET,-" "0,1" bitfld.long 0x1A0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1A0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1A0 0. "WAIT_SET,-" "0,1" line.long 0x1A4 "IMNTRCR105,INTC-Monitor Control Register 105" hexmask.long.word 0x1A4 16.--31. 1. "KEYCODE,-" bitfld.long 0x1A4 7. "NUM1_EN,-" "0,1" bitfld.long 0x1A4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1A4 4. "CNT_RESET,-" "0,1" bitfld.long 0x1A4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1A4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1A4 0. "WAIT_SET,-" "0,1" line.long 0x1A8 "IMNTRCR106,INTC-Monitor Control Register 106" hexmask.long.word 0x1A8 16.--31. 1. "KEYCODE,-" bitfld.long 0x1A8 7. "NUM1_EN,-" "0,1" bitfld.long 0x1A8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1A8 4. "CNT_RESET,-" "0,1" bitfld.long 0x1A8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1A8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1A8 0. "WAIT_SET,-" "0,1" line.long 0x1AC "IMNTRCR107,INTC-Monitor Control Register 107" hexmask.long.word 0x1AC 16.--31. 1. "KEYCODE,-" bitfld.long 0x1AC 7. "NUM1_EN,-" "0,1" bitfld.long 0x1AC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1AC 4. "CNT_RESET,-" "0,1" bitfld.long 0x1AC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1AC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1AC 0. "WAIT_SET,-" "0,1" line.long 0x1B0 "IMNTRCR108,INTC-Monitor Control Register 108" hexmask.long.word 0x1B0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1B0 7. "NUM1_EN,-" "0,1" bitfld.long 0x1B0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1B0 4. "CNT_RESET,-" "0,1" bitfld.long 0x1B0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1B0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1B0 0. "WAIT_SET,-" "0,1" line.long 0x1B4 "IMNTRCR109,INTC-Monitor Control Register 109" hexmask.long.word 0x1B4 16.--31. 1. "KEYCODE,-" bitfld.long 0x1B4 7. "NUM1_EN,-" "0,1" bitfld.long 0x1B4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1B4 4. "CNT_RESET,-" "0,1" bitfld.long 0x1B4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1B4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1B4 0. "WAIT_SET,-" "0,1" line.long 0x1B8 "IMNTRCR110,INTC-Monitor Control Register 110" hexmask.long.word 0x1B8 16.--31. 1. "KEYCODE,-" bitfld.long 0x1B8 7. "NUM1_EN,-" "0,1" bitfld.long 0x1B8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1B8 4. "CNT_RESET,-" "0,1" bitfld.long 0x1B8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1B8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1B8 0. "WAIT_SET,-" "0,1" line.long 0x1BC "IMNTRCR111,INTC-Monitor Control Register 111" hexmask.long.word 0x1BC 16.--31. 1. "KEYCODE,-" bitfld.long 0x1BC 7. "NUM1_EN,-" "0,1" bitfld.long 0x1BC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1BC 4. "CNT_RESET,-" "0,1" bitfld.long 0x1BC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1BC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1BC 0. "WAIT_SET,-" "0,1" line.long 0x1C0 "IMNTRCR112,INTC-Monitor Control Register 112" hexmask.long.word 0x1C0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1C0 7. "NUM1_EN,-" "0,1" bitfld.long 0x1C0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1C0 4. "CNT_RESET,-" "0,1" bitfld.long 0x1C0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1C0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1C0 0. "WAIT_SET,-" "0,1" line.long 0x1C4 "IMNTRCR113,INTC-Monitor Control Register 113" hexmask.long.word 0x1C4 16.--31. 1. "KEYCODE,-" bitfld.long 0x1C4 7. "NUM1_EN,-" "0,1" bitfld.long 0x1C4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1C4 4. "CNT_RESET,-" "0,1" bitfld.long 0x1C4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1C4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1C4 0. "WAIT_SET,-" "0,1" line.long 0x1C8 "IMNTRCR114,INTC-Monitor Control Register 114" hexmask.long.word 0x1C8 16.--31. 1. "KEYCODE,-" bitfld.long 0x1C8 7. "NUM1_EN,-" "0,1" bitfld.long 0x1C8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1C8 4. "CNT_RESET,-" "0,1" bitfld.long 0x1C8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1C8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1C8 0. "WAIT_SET,-" "0,1" line.long 0x1CC "IMNTRCR115,INTC-Monitor Control Register 115" hexmask.long.word 0x1CC 16.--31. 1. "KEYCODE,-" bitfld.long 0x1CC 7. "NUM1_EN,-" "0,1" bitfld.long 0x1CC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1CC 4. "CNT_RESET,-" "0,1" bitfld.long 0x1CC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1CC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1CC 0. "WAIT_SET,-" "0,1" line.long 0x1D0 "IMNTRCR116,INTC-Monitor Control Register 116" hexmask.long.word 0x1D0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1D0 7. "NUM1_EN,-" "0,1" bitfld.long 0x1D0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1D0 4. "CNT_RESET,-" "0,1" bitfld.long 0x1D0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1D0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1D0 0. "WAIT_SET,-" "0,1" line.long 0x1D4 "IMNTRCR117,INTC-Monitor Control Register 117" hexmask.long.word 0x1D4 16.--31. 1. "KEYCODE,-" bitfld.long 0x1D4 7. "NUM1_EN,-" "0,1" bitfld.long 0x1D4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1D4 4. "CNT_RESET,-" "0,1" bitfld.long 0x1D4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1D4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1D4 0. "WAIT_SET,-" "0,1" line.long 0x1D8 "IMNTRCR118,INTC-Monitor Control Register 118" hexmask.long.word 0x1D8 16.--31. 1. "KEYCODE,-" bitfld.long 0x1D8 7. "NUM1_EN,-" "0,1" bitfld.long 0x1D8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1D8 4. "CNT_RESET,-" "0,1" bitfld.long 0x1D8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1D8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1D8 0. "WAIT_SET,-" "0,1" line.long 0x1DC "IMNTRCR119,INTC-Monitor Control Register 119" hexmask.long.word 0x1DC 16.--31. 1. "KEYCODE,-" bitfld.long 0x1DC 7. "NUM1_EN,-" "0,1" bitfld.long 0x1DC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1DC 4. "CNT_RESET,-" "0,1" bitfld.long 0x1DC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1DC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1DC 0. "WAIT_SET,-" "0,1" line.long 0x1E0 "IMNTRCR120,INTC-Monitor Control Register 120" hexmask.long.word 0x1E0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1E0 7. "NUM1_EN,-" "0,1" bitfld.long 0x1E0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1E0 4. "CNT_RESET,-" "0,1" bitfld.long 0x1E0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1E0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1E0 0. "WAIT_SET,-" "0,1" line.long 0x1E4 "IMNTRCR121,INTC-Monitor Control Register 121" hexmask.long.word 0x1E4 16.--31. 1. "KEYCODE,-" bitfld.long 0x1E4 7. "NUM1_EN,-" "0,1" bitfld.long 0x1E4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1E4 4. "CNT_RESET,-" "0,1" bitfld.long 0x1E4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1E4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1E4 0. "WAIT_SET,-" "0,1" line.long 0x1E8 "IMNTRCR122,INTC-Monitor Control Register 122" hexmask.long.word 0x1E8 16.--31. 1. "KEYCODE,-" bitfld.long 0x1E8 7. "NUM1_EN,-" "0,1" bitfld.long 0x1E8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1E8 4. "CNT_RESET,-" "0,1" bitfld.long 0x1E8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1E8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1E8 0. "WAIT_SET,-" "0,1" line.long 0x1EC "IMNTRCR123,INTC-Monitor Control Register 123" hexmask.long.word 0x1EC 16.--31. 1. "KEYCODE,-" bitfld.long 0x1EC 7. "NUM1_EN,-" "0,1" bitfld.long 0x1EC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1EC 4. "CNT_RESET,-" "0,1" bitfld.long 0x1EC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1EC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1EC 0. "WAIT_SET,-" "0,1" line.long 0x1F0 "IMNTRCR124,INTC-Monitor Control Register 124" hexmask.long.word 0x1F0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1F0 7. "NUM1_EN,-" "0,1" bitfld.long 0x1F0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1F0 4. "CNT_RESET,-" "0,1" bitfld.long 0x1F0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1F0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1F0 0. "WAIT_SET,-" "0,1" line.long 0x1F4 "IMNTRCR125,INTC-Monitor Control Register 125" hexmask.long.word 0x1F4 16.--31. 1. "KEYCODE,-" bitfld.long 0x1F4 7. "NUM1_EN,-" "0,1" bitfld.long 0x1F4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1F4 4. "CNT_RESET,-" "0,1" bitfld.long 0x1F4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1F4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1F4 0. "WAIT_SET,-" "0,1" line.long 0x1F8 "IMNTRCR126,INTC-Monitor Control Register 126" hexmask.long.word 0x1F8 16.--31. 1. "KEYCODE,-" bitfld.long 0x1F8 7. "NUM1_EN,-" "0,1" bitfld.long 0x1F8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1F8 4. "CNT_RESET,-" "0,1" bitfld.long 0x1F8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1F8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1F8 0. "WAIT_SET,-" "0,1" line.long 0x1FC "IMNTRCR127,INTC-Monitor Control Register 127" hexmask.long.word 0x1FC 16.--31. 1. "KEYCODE,-" bitfld.long 0x1FC 7. "NUM1_EN,-" "0,1" bitfld.long 0x1FC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x1FC 4. "CNT_RESET,-" "0,1" bitfld.long 0x1FC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x1FC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x1FC 0. "WAIT_SET,-" "0,1" line.long 0x200 "IMNTRCR128,INTC-Monitor Control Register 128" hexmask.long.word 0x200 16.--31. 1. "KEYCODE,-" bitfld.long 0x200 7. "NUM1_EN,-" "0,1" bitfld.long 0x200 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x200 4. "CNT_RESET,-" "0,1" bitfld.long 0x200 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x200 1. "IMNTR_EN,-" "0,1" bitfld.long 0x200 0. "WAIT_SET,-" "0,1" line.long 0x204 "IMNTRCR129,INTC-Monitor Control Register 129" hexmask.long.word 0x204 16.--31. 1. "KEYCODE,-" bitfld.long 0x204 7. "NUM1_EN,-" "0,1" bitfld.long 0x204 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x204 4. "CNT_RESET,-" "0,1" bitfld.long 0x204 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x204 1. "IMNTR_EN,-" "0,1" bitfld.long 0x204 0. "WAIT_SET,-" "0,1" line.long 0x208 "IMNTRCR130,INTC-Monitor Control Register 130" hexmask.long.word 0x208 16.--31. 1. "KEYCODE,-" bitfld.long 0x208 7. "NUM1_EN,-" "0,1" bitfld.long 0x208 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x208 4. "CNT_RESET,-" "0,1" bitfld.long 0x208 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x208 1. "IMNTR_EN,-" "0,1" bitfld.long 0x208 0. "WAIT_SET,-" "0,1" line.long 0x20C "IMNTRCR131,INTC-Monitor Control Register 131" hexmask.long.word 0x20C 16.--31. 1. "KEYCODE,-" bitfld.long 0x20C 7. "NUM1_EN,-" "0,1" bitfld.long 0x20C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x20C 4. "CNT_RESET,-" "0,1" bitfld.long 0x20C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x20C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x20C 0. "WAIT_SET,-" "0,1" line.long 0x210 "IMNTRCR132,INTC-Monitor Control Register 132" hexmask.long.word 0x210 16.--31. 1. "KEYCODE,-" bitfld.long 0x210 7. "NUM1_EN,-" "0,1" bitfld.long 0x210 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x210 4. "CNT_RESET,-" "0,1" bitfld.long 0x210 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x210 1. "IMNTR_EN,-" "0,1" bitfld.long 0x210 0. "WAIT_SET,-" "0,1" line.long 0x214 "IMNTRCR133,INTC-Monitor Control Register 133" hexmask.long.word 0x214 16.--31. 1. "KEYCODE,-" bitfld.long 0x214 7. "NUM1_EN,-" "0,1" bitfld.long 0x214 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x214 4. "CNT_RESET,-" "0,1" bitfld.long 0x214 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x214 1. "IMNTR_EN,-" "0,1" bitfld.long 0x214 0. "WAIT_SET,-" "0,1" line.long 0x218 "IMNTRCR134,INTC-Monitor Control Register 134" hexmask.long.word 0x218 16.--31. 1. "KEYCODE,-" bitfld.long 0x218 7. "NUM1_EN,-" "0,1" bitfld.long 0x218 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x218 4. "CNT_RESET,-" "0,1" bitfld.long 0x218 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x218 1. "IMNTR_EN,-" "0,1" bitfld.long 0x218 0. "WAIT_SET,-" "0,1" line.long 0x21C "IMNTRCR135,INTC-Monitor Control Register 135" hexmask.long.word 0x21C 16.--31. 1. "KEYCODE,-" bitfld.long 0x21C 7. "NUM1_EN,-" "0,1" bitfld.long 0x21C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x21C 4. "CNT_RESET,-" "0,1" bitfld.long 0x21C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x21C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x21C 0. "WAIT_SET,-" "0,1" line.long 0x220 "IMNTRCR136,INTC-Monitor Control Register 136" hexmask.long.word 0x220 16.--31. 1. "KEYCODE,-" bitfld.long 0x220 7. "NUM1_EN,-" "0,1" bitfld.long 0x220 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x220 4. "CNT_RESET,-" "0,1" bitfld.long 0x220 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x220 1. "IMNTR_EN,-" "0,1" bitfld.long 0x220 0. "WAIT_SET,-" "0,1" line.long 0x224 "IMNTRCR137,INTC-Monitor Control Register 137" hexmask.long.word 0x224 16.--31. 1. "KEYCODE,-" bitfld.long 0x224 7. "NUM1_EN,-" "0,1" bitfld.long 0x224 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x224 4. "CNT_RESET,-" "0,1" bitfld.long 0x224 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x224 1. "IMNTR_EN,-" "0,1" bitfld.long 0x224 0. "WAIT_SET,-" "0,1" line.long 0x228 "IMNTRCR138,INTC-Monitor Control Register 138" hexmask.long.word 0x228 16.--31. 1. "KEYCODE,-" bitfld.long 0x228 7. "NUM1_EN,-" "0,1" bitfld.long 0x228 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x228 4. "CNT_RESET,-" "0,1" bitfld.long 0x228 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x228 1. "IMNTR_EN,-" "0,1" bitfld.long 0x228 0. "WAIT_SET,-" "0,1" line.long 0x22C "IMNTRCR139,INTC-Monitor Control Register 139" hexmask.long.word 0x22C 16.--31. 1. "KEYCODE,-" bitfld.long 0x22C 7. "NUM1_EN,-" "0,1" bitfld.long 0x22C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x22C 4. "CNT_RESET,-" "0,1" bitfld.long 0x22C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x22C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x22C 0. "WAIT_SET,-" "0,1" line.long 0x230 "IMNTRCR140,INTC-Monitor Control Register 140" hexmask.long.word 0x230 16.--31. 1. "KEYCODE,-" bitfld.long 0x230 7. "NUM1_EN,-" "0,1" bitfld.long 0x230 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x230 4. "CNT_RESET,-" "0,1" bitfld.long 0x230 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x230 1. "IMNTR_EN,-" "0,1" bitfld.long 0x230 0. "WAIT_SET,-" "0,1" line.long 0x234 "IMNTRCR141,INTC-Monitor Control Register 141" hexmask.long.word 0x234 16.--31. 1. "KEYCODE,-" bitfld.long 0x234 7. "NUM1_EN,-" "0,1" bitfld.long 0x234 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x234 4. "CNT_RESET,-" "0,1" bitfld.long 0x234 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x234 1. "IMNTR_EN,-" "0,1" bitfld.long 0x234 0. "WAIT_SET,-" "0,1" line.long 0x238 "IMNTRCR142,INTC-Monitor Control Register 142" hexmask.long.word 0x238 16.--31. 1. "KEYCODE,-" bitfld.long 0x238 7. "NUM1_EN,-" "0,1" bitfld.long 0x238 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x238 4. "CNT_RESET,-" "0,1" bitfld.long 0x238 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x238 1. "IMNTR_EN,-" "0,1" bitfld.long 0x238 0. "WAIT_SET,-" "0,1" line.long 0x23C "IMNTRCR143,INTC-Monitor Control Register 143" hexmask.long.word 0x23C 16.--31. 1. "KEYCODE,-" bitfld.long 0x23C 7. "NUM1_EN,-" "0,1" bitfld.long 0x23C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x23C 4. "CNT_RESET,-" "0,1" bitfld.long 0x23C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x23C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x23C 0. "WAIT_SET,-" "0,1" line.long 0x240 "IMNTRCR144,INTC-Monitor Control Register 144" hexmask.long.word 0x240 16.--31. 1. "KEYCODE,-" bitfld.long 0x240 7. "NUM1_EN,-" "0,1" bitfld.long 0x240 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x240 4. "CNT_RESET,-" "0,1" bitfld.long 0x240 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x240 1. "IMNTR_EN,-" "0,1" bitfld.long 0x240 0. "WAIT_SET,-" "0,1" line.long 0x244 "IMNTRCR145,INTC-Monitor Control Register 145" hexmask.long.word 0x244 16.--31. 1. "KEYCODE,-" bitfld.long 0x244 7. "NUM1_EN,-" "0,1" bitfld.long 0x244 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x244 4. "CNT_RESET,-" "0,1" bitfld.long 0x244 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x244 1. "IMNTR_EN,-" "0,1" bitfld.long 0x244 0. "WAIT_SET,-" "0,1" line.long 0x248 "IMNTRCR146,INTC-Monitor Control Register 146" hexmask.long.word 0x248 16.--31. 1. "KEYCODE,-" bitfld.long 0x248 7. "NUM1_EN,-" "0,1" bitfld.long 0x248 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x248 4. "CNT_RESET,-" "0,1" bitfld.long 0x248 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x248 1. "IMNTR_EN,-" "0,1" bitfld.long 0x248 0. "WAIT_SET,-" "0,1" line.long 0x24C "IMNTRCR147,INTC-Monitor Control Register 147" hexmask.long.word 0x24C 16.--31. 1. "KEYCODE,-" bitfld.long 0x24C 7. "NUM1_EN,-" "0,1" bitfld.long 0x24C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x24C 4. "CNT_RESET,-" "0,1" bitfld.long 0x24C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x24C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x24C 0. "WAIT_SET,-" "0,1" line.long 0x250 "IMNTRCR148,INTC-Monitor Control Register 148" hexmask.long.word 0x250 16.--31. 1. "KEYCODE,-" bitfld.long 0x250 7. "NUM1_EN,-" "0,1" bitfld.long 0x250 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x250 4. "CNT_RESET,-" "0,1" bitfld.long 0x250 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x250 1. "IMNTR_EN,-" "0,1" bitfld.long 0x250 0. "WAIT_SET,-" "0,1" line.long 0x254 "IMNTRCR149,INTC-Monitor Control Register 149" hexmask.long.word 0x254 16.--31. 1. "KEYCODE,-" bitfld.long 0x254 7. "NUM1_EN,-" "0,1" bitfld.long 0x254 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x254 4. "CNT_RESET,-" "0,1" bitfld.long 0x254 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x254 1. "IMNTR_EN,-" "0,1" bitfld.long 0x254 0. "WAIT_SET,-" "0,1" line.long 0x258 "IMNTRCR150,INTC-Monitor Control Register 150" hexmask.long.word 0x258 16.--31. 1. "KEYCODE,-" bitfld.long 0x258 7. "NUM1_EN,-" "0,1" bitfld.long 0x258 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x258 4. "CNT_RESET,-" "0,1" bitfld.long 0x258 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x258 1. "IMNTR_EN,-" "0,1" bitfld.long 0x258 0. "WAIT_SET,-" "0,1" line.long 0x25C "IMNTRCR151,INTC-Monitor Control Register 151" hexmask.long.word 0x25C 16.--31. 1. "KEYCODE,-" bitfld.long 0x25C 7. "NUM1_EN,-" "0,1" bitfld.long 0x25C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x25C 4. "CNT_RESET,-" "0,1" bitfld.long 0x25C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x25C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x25C 0. "WAIT_SET,-" "0,1" line.long 0x260 "IMNTRCR152,INTC-Monitor Control Register 152" hexmask.long.word 0x260 16.--31. 1. "KEYCODE,-" bitfld.long 0x260 7. "NUM1_EN,-" "0,1" bitfld.long 0x260 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x260 4. "CNT_RESET,-" "0,1" bitfld.long 0x260 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x260 1. "IMNTR_EN,-" "0,1" bitfld.long 0x260 0. "WAIT_SET,-" "0,1" line.long 0x264 "IMNTRCR153,INTC-Monitor Control Register 153" hexmask.long.word 0x264 16.--31. 1. "KEYCODE,-" bitfld.long 0x264 7. "NUM1_EN,-" "0,1" bitfld.long 0x264 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x264 4. "CNT_RESET,-" "0,1" bitfld.long 0x264 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x264 1. "IMNTR_EN,-" "0,1" bitfld.long 0x264 0. "WAIT_SET,-" "0,1" line.long 0x268 "IMNTRCR154,INTC-Monitor Control Register 154" hexmask.long.word 0x268 16.--31. 1. "KEYCODE,-" bitfld.long 0x268 7. "NUM1_EN,-" "0,1" bitfld.long 0x268 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x268 4. "CNT_RESET,-" "0,1" bitfld.long 0x268 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x268 1. "IMNTR_EN,-" "0,1" bitfld.long 0x268 0. "WAIT_SET,-" "0,1" line.long 0x26C "IMNTRCR155,INTC-Monitor Control Register 155" hexmask.long.word 0x26C 16.--31. 1. "KEYCODE,-" bitfld.long 0x26C 7. "NUM1_EN,-" "0,1" bitfld.long 0x26C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x26C 4. "CNT_RESET,-" "0,1" bitfld.long 0x26C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x26C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x26C 0. "WAIT_SET,-" "0,1" line.long 0x270 "IMNTRCR156,INTC-Monitor Control Register 156" hexmask.long.word 0x270 16.--31. 1. "KEYCODE,-" bitfld.long 0x270 7. "NUM1_EN,-" "0,1" bitfld.long 0x270 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x270 4. "CNT_RESET,-" "0,1" bitfld.long 0x270 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x270 1. "IMNTR_EN,-" "0,1" bitfld.long 0x270 0. "WAIT_SET,-" "0,1" line.long 0x274 "IMNTRCR157,INTC-Monitor Control Register 157" hexmask.long.word 0x274 16.--31. 1. "KEYCODE,-" bitfld.long 0x274 7. "NUM1_EN,-" "0,1" bitfld.long 0x274 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x274 4. "CNT_RESET,-" "0,1" bitfld.long 0x274 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x274 1. "IMNTR_EN,-" "0,1" bitfld.long 0x274 0. "WAIT_SET,-" "0,1" line.long 0x278 "IMNTRCR158,INTC-Monitor Control Register 158" hexmask.long.word 0x278 16.--31. 1. "KEYCODE,-" bitfld.long 0x278 7. "NUM1_EN,-" "0,1" bitfld.long 0x278 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x278 4. "CNT_RESET,-" "0,1" bitfld.long 0x278 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x278 1. "IMNTR_EN,-" "0,1" bitfld.long 0x278 0. "WAIT_SET,-" "0,1" line.long 0x27C "IMNTRCR159,INTC-Monitor Control Register 159" hexmask.long.word 0x27C 16.--31. 1. "KEYCODE,-" bitfld.long 0x27C 7. "NUM1_EN,-" "0,1" bitfld.long 0x27C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x27C 4. "CNT_RESET,-" "0,1" bitfld.long 0x27C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x27C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x27C 0. "WAIT_SET,-" "0,1" line.long 0x280 "IMNTRCR160,INTC-Monitor Control Register 160" hexmask.long.word 0x280 16.--31. 1. "KEYCODE,-" bitfld.long 0x280 7. "NUM1_EN,-" "0,1" bitfld.long 0x280 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x280 4. "CNT_RESET,-" "0,1" bitfld.long 0x280 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x280 1. "IMNTR_EN,-" "0,1" bitfld.long 0x280 0. "WAIT_SET,-" "0,1" line.long 0x284 "IMNTRCR161,INTC-Monitor Control Register 161" hexmask.long.word 0x284 16.--31. 1. "KEYCODE,-" bitfld.long 0x284 7. "NUM1_EN,-" "0,1" bitfld.long 0x284 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x284 4. "CNT_RESET,-" "0,1" bitfld.long 0x284 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x284 1. "IMNTR_EN,-" "0,1" bitfld.long 0x284 0. "WAIT_SET,-" "0,1" line.long 0x288 "IMNTRCR162,INTC-Monitor Control Register 162" hexmask.long.word 0x288 16.--31. 1. "KEYCODE,-" bitfld.long 0x288 7. "NUM1_EN,-" "0,1" bitfld.long 0x288 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x288 4. "CNT_RESET,-" "0,1" bitfld.long 0x288 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x288 1. "IMNTR_EN,-" "0,1" bitfld.long 0x288 0. "WAIT_SET,-" "0,1" line.long 0x28C "IMNTRCR163,INTC-Monitor Control Register 163" hexmask.long.word 0x28C 16.--31. 1. "KEYCODE,-" bitfld.long 0x28C 7. "NUM1_EN,-" "0,1" bitfld.long 0x28C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x28C 4. "CNT_RESET,-" "0,1" bitfld.long 0x28C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x28C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x28C 0. "WAIT_SET,-" "0,1" line.long 0x290 "IMNTRCR164,INTC-Monitor Control Register 164" hexmask.long.word 0x290 16.--31. 1. "KEYCODE,-" bitfld.long 0x290 7. "NUM1_EN,-" "0,1" bitfld.long 0x290 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x290 4. "CNT_RESET,-" "0,1" bitfld.long 0x290 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x290 1. "IMNTR_EN,-" "0,1" bitfld.long 0x290 0. "WAIT_SET,-" "0,1" line.long 0x294 "IMNTRCR165,INTC-Monitor Control Register 165" hexmask.long.word 0x294 16.--31. 1. "KEYCODE,-" bitfld.long 0x294 7. "NUM1_EN,-" "0,1" bitfld.long 0x294 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x294 4. "CNT_RESET,-" "0,1" bitfld.long 0x294 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x294 1. "IMNTR_EN,-" "0,1" bitfld.long 0x294 0. "WAIT_SET,-" "0,1" line.long 0x298 "IMNTRCR166,INTC-Monitor Control Register 166" hexmask.long.word 0x298 16.--31. 1. "KEYCODE,-" bitfld.long 0x298 7. "NUM1_EN,-" "0,1" bitfld.long 0x298 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x298 4. "CNT_RESET,-" "0,1" bitfld.long 0x298 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x298 1. "IMNTR_EN,-" "0,1" bitfld.long 0x298 0. "WAIT_SET,-" "0,1" line.long 0x29C "IMNTRCR167,INTC-Monitor Control Register 167" hexmask.long.word 0x29C 16.--31. 1. "KEYCODE,-" bitfld.long 0x29C 7. "NUM1_EN,-" "0,1" bitfld.long 0x29C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x29C 4. "CNT_RESET,-" "0,1" bitfld.long 0x29C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x29C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x29C 0. "WAIT_SET,-" "0,1" line.long 0x2A0 "IMNTRCR168,INTC-Monitor Control Register 168" hexmask.long.word 0x2A0 16.--31. 1. "KEYCODE,-" bitfld.long 0x2A0 7. "NUM1_EN,-" "0,1" bitfld.long 0x2A0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2A0 4. "CNT_RESET,-" "0,1" bitfld.long 0x2A0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2A0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2A0 0. "WAIT_SET,-" "0,1" line.long 0x2A4 "IMNTRCR169,INTC-Monitor Control Register 169" hexmask.long.word 0x2A4 16.--31. 1. "KEYCODE,-" bitfld.long 0x2A4 7. "NUM1_EN,-" "0,1" bitfld.long 0x2A4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2A4 4. "CNT_RESET,-" "0,1" bitfld.long 0x2A4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2A4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2A4 0. "WAIT_SET,-" "0,1" line.long 0x2A8 "IMNTRCR170,INTC-Monitor Control Register 170" hexmask.long.word 0x2A8 16.--31. 1. "KEYCODE,-" bitfld.long 0x2A8 7. "NUM1_EN,-" "0,1" bitfld.long 0x2A8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2A8 4. "CNT_RESET,-" "0,1" bitfld.long 0x2A8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2A8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2A8 0. "WAIT_SET,-" "0,1" line.long 0x2AC "IMNTRCR171,INTC-Monitor Control Register 171" hexmask.long.word 0x2AC 16.--31. 1. "KEYCODE,-" bitfld.long 0x2AC 7. "NUM1_EN,-" "0,1" bitfld.long 0x2AC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2AC 4. "CNT_RESET,-" "0,1" bitfld.long 0x2AC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2AC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2AC 0. "WAIT_SET,-" "0,1" line.long 0x2B0 "IMNTRCR172,INTC-Monitor Control Register 172" hexmask.long.word 0x2B0 16.--31. 1. "KEYCODE,-" bitfld.long 0x2B0 7. "NUM1_EN,-" "0,1" bitfld.long 0x2B0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2B0 4. "CNT_RESET,-" "0,1" bitfld.long 0x2B0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2B0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2B0 0. "WAIT_SET,-" "0,1" line.long 0x2B4 "IMNTRCR173,INTC-Monitor Control Register 173" hexmask.long.word 0x2B4 16.--31. 1. "KEYCODE,-" bitfld.long 0x2B4 7. "NUM1_EN,-" "0,1" bitfld.long 0x2B4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2B4 4. "CNT_RESET,-" "0,1" bitfld.long 0x2B4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2B4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2B4 0. "WAIT_SET,-" "0,1" line.long 0x2B8 "IMNTRCR174,INTC-Monitor Control Register 174" hexmask.long.word 0x2B8 16.--31. 1. "KEYCODE,-" bitfld.long 0x2B8 7. "NUM1_EN,-" "0,1" bitfld.long 0x2B8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2B8 4. "CNT_RESET,-" "0,1" bitfld.long 0x2B8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2B8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2B8 0. "WAIT_SET,-" "0,1" line.long 0x2BC "IMNTRCR175,INTC-Monitor Control Register 175" hexmask.long.word 0x2BC 16.--31. 1. "KEYCODE,-" bitfld.long 0x2BC 7. "NUM1_EN,-" "0,1" bitfld.long 0x2BC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2BC 4. "CNT_RESET,-" "0,1" bitfld.long 0x2BC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2BC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2BC 0. "WAIT_SET,-" "0,1" line.long 0x2C0 "IMNTRCR176,INTC-Monitor Control Register 176" hexmask.long.word 0x2C0 16.--31. 1. "KEYCODE,-" bitfld.long 0x2C0 7. "NUM1_EN,-" "0,1" bitfld.long 0x2C0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2C0 4. "CNT_RESET,-" "0,1" bitfld.long 0x2C0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2C0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2C0 0. "WAIT_SET,-" "0,1" line.long 0x2C4 "IMNTRCR177,INTC-Monitor Control Register 177" hexmask.long.word 0x2C4 16.--31. 1. "KEYCODE,-" bitfld.long 0x2C4 7. "NUM1_EN,-" "0,1" bitfld.long 0x2C4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2C4 4. "CNT_RESET,-" "0,1" bitfld.long 0x2C4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2C4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2C4 0. "WAIT_SET,-" "0,1" line.long 0x2C8 "IMNTRCR178,INTC-Monitor Control Register 178" hexmask.long.word 0x2C8 16.--31. 1. "KEYCODE,-" bitfld.long 0x2C8 7. "NUM1_EN,-" "0,1" bitfld.long 0x2C8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2C8 4. "CNT_RESET,-" "0,1" bitfld.long 0x2C8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2C8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2C8 0. "WAIT_SET,-" "0,1" line.long 0x2CC "IMNTRCR179,INTC-Monitor Control Register 179" hexmask.long.word 0x2CC 16.--31. 1. "KEYCODE,-" bitfld.long 0x2CC 7. "NUM1_EN,-" "0,1" bitfld.long 0x2CC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2CC 4. "CNT_RESET,-" "0,1" bitfld.long 0x2CC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2CC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2CC 0. "WAIT_SET,-" "0,1" line.long 0x2D0 "IMNTRCR180,INTC-Monitor Control Register 180" hexmask.long.word 0x2D0 16.--31. 1. "KEYCODE,-" bitfld.long 0x2D0 7. "NUM1_EN,-" "0,1" bitfld.long 0x2D0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2D0 4. "CNT_RESET,-" "0,1" bitfld.long 0x2D0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2D0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2D0 0. "WAIT_SET,-" "0,1" line.long 0x2D4 "IMNTRCR181,INTC-Monitor Control Register 181" hexmask.long.word 0x2D4 16.--31. 1. "KEYCODE,-" bitfld.long 0x2D4 7. "NUM1_EN,-" "0,1" bitfld.long 0x2D4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2D4 4. "CNT_RESET,-" "0,1" bitfld.long 0x2D4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2D4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2D4 0. "WAIT_SET,-" "0,1" line.long 0x2D8 "IMNTRCR182,INTC-Monitor Control Register 182" hexmask.long.word 0x2D8 16.--31. 1. "KEYCODE,-" bitfld.long 0x2D8 7. "NUM1_EN,-" "0,1" bitfld.long 0x2D8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2D8 4. "CNT_RESET,-" "0,1" bitfld.long 0x2D8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2D8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2D8 0. "WAIT_SET,-" "0,1" line.long 0x2DC "IMNTRCR183,INTC-Monitor Control Register 183" hexmask.long.word 0x2DC 16.--31. 1. "KEYCODE,-" bitfld.long 0x2DC 7. "NUM1_EN,-" "0,1" bitfld.long 0x2DC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2DC 4. "CNT_RESET,-" "0,1" bitfld.long 0x2DC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2DC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2DC 0. "WAIT_SET,-" "0,1" line.long 0x2E0 "IMNTRCR184,INTC-Monitor Control Register 184" hexmask.long.word 0x2E0 16.--31. 1. "KEYCODE,-" bitfld.long 0x2E0 7. "NUM1_EN,-" "0,1" bitfld.long 0x2E0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2E0 4. "CNT_RESET,-" "0,1" bitfld.long 0x2E0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2E0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2E0 0. "WAIT_SET,-" "0,1" line.long 0x2E4 "IMNTRCR185,INTC-Monitor Control Register 185" hexmask.long.word 0x2E4 16.--31. 1. "KEYCODE,-" bitfld.long 0x2E4 7. "NUM1_EN,-" "0,1" bitfld.long 0x2E4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2E4 4. "CNT_RESET,-" "0,1" bitfld.long 0x2E4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2E4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2E4 0. "WAIT_SET,-" "0,1" line.long 0x2E8 "IMNTRCR186,INTC-Monitor Control Register 186" hexmask.long.word 0x2E8 16.--31. 1. "KEYCODE,-" bitfld.long 0x2E8 7. "NUM1_EN,-" "0,1" bitfld.long 0x2E8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2E8 4. "CNT_RESET,-" "0,1" bitfld.long 0x2E8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2E8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2E8 0. "WAIT_SET,-" "0,1" line.long 0x2EC "IMNTRCR187,INTC-Monitor Control Register 187" hexmask.long.word 0x2EC 16.--31. 1. "KEYCODE,-" bitfld.long 0x2EC 7. "NUM1_EN,-" "0,1" bitfld.long 0x2EC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2EC 4. "CNT_RESET,-" "0,1" bitfld.long 0x2EC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2EC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2EC 0. "WAIT_SET,-" "0,1" line.long 0x2F0 "IMNTRCR188,INTC-Monitor Control Register 188" hexmask.long.word 0x2F0 16.--31. 1. "KEYCODE,-" bitfld.long 0x2F0 7. "NUM1_EN,-" "0,1" bitfld.long 0x2F0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2F0 4. "CNT_RESET,-" "0,1" bitfld.long 0x2F0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2F0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2F0 0. "WAIT_SET,-" "0,1" line.long 0x2F4 "IMNTRCR189,INTC-Monitor Control Register 189" hexmask.long.word 0x2F4 16.--31. 1. "KEYCODE,-" bitfld.long 0x2F4 7. "NUM1_EN,-" "0,1" bitfld.long 0x2F4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2F4 4. "CNT_RESET,-" "0,1" bitfld.long 0x2F4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2F4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2F4 0. "WAIT_SET,-" "0,1" line.long 0x2F8 "IMNTRCR190,INTC-Monitor Control Register 190" hexmask.long.word 0x2F8 16.--31. 1. "KEYCODE,-" bitfld.long 0x2F8 7. "NUM1_EN,-" "0,1" bitfld.long 0x2F8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2F8 4. "CNT_RESET,-" "0,1" bitfld.long 0x2F8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2F8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2F8 0. "WAIT_SET,-" "0,1" line.long 0x2FC "IMNTRCR191,INTC-Monitor Control Register 191" hexmask.long.word 0x2FC 16.--31. 1. "KEYCODE,-" bitfld.long 0x2FC 7. "NUM1_EN,-" "0,1" bitfld.long 0x2FC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x2FC 4. "CNT_RESET,-" "0,1" bitfld.long 0x2FC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x2FC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x2FC 0. "WAIT_SET,-" "0,1" line.long 0x300 "IMNTRCR192,INTC-Monitor Control Register 192" hexmask.long.word 0x300 16.--31. 1. "KEYCODE,-" bitfld.long 0x300 7. "NUM1_EN,-" "0,1" bitfld.long 0x300 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x300 4. "CNT_RESET,-" "0,1" bitfld.long 0x300 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x300 1. "IMNTR_EN,-" "0,1" bitfld.long 0x300 0. "WAIT_SET,-" "0,1" line.long 0x304 "IMNTRCR193,INTC-Monitor Control Register 193" hexmask.long.word 0x304 16.--31. 1. "KEYCODE,-" bitfld.long 0x304 7. "NUM1_EN,-" "0,1" bitfld.long 0x304 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x304 4. "CNT_RESET,-" "0,1" bitfld.long 0x304 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x304 1. "IMNTR_EN,-" "0,1" bitfld.long 0x304 0. "WAIT_SET,-" "0,1" line.long 0x308 "IMNTRCR194,INTC-Monitor Control Register 194" hexmask.long.word 0x308 16.--31. 1. "KEYCODE,-" bitfld.long 0x308 7. "NUM1_EN,-" "0,1" bitfld.long 0x308 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x308 4. "CNT_RESET,-" "0,1" bitfld.long 0x308 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x308 1. "IMNTR_EN,-" "0,1" bitfld.long 0x308 0. "WAIT_SET,-" "0,1" line.long 0x30C "IMNTRCR195,INTC-Monitor Control Register 195" hexmask.long.word 0x30C 16.--31. 1. "KEYCODE,-" bitfld.long 0x30C 7. "NUM1_EN,-" "0,1" bitfld.long 0x30C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x30C 4. "CNT_RESET,-" "0,1" bitfld.long 0x30C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x30C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x30C 0. "WAIT_SET,-" "0,1" line.long 0x310 "IMNTRCR196,INTC-Monitor Control Register 196" hexmask.long.word 0x310 16.--31. 1. "KEYCODE,-" bitfld.long 0x310 7. "NUM1_EN,-" "0,1" bitfld.long 0x310 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x310 4. "CNT_RESET,-" "0,1" bitfld.long 0x310 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x310 1. "IMNTR_EN,-" "0,1" bitfld.long 0x310 0. "WAIT_SET,-" "0,1" line.long 0x314 "IMNTRCR197,INTC-Monitor Control Register 197" hexmask.long.word 0x314 16.--31. 1. "KEYCODE,-" bitfld.long 0x314 7. "NUM1_EN,-" "0,1" bitfld.long 0x314 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x314 4. "CNT_RESET,-" "0,1" bitfld.long 0x314 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x314 1. "IMNTR_EN,-" "0,1" bitfld.long 0x314 0. "WAIT_SET,-" "0,1" line.long 0x318 "IMNTRCR198,INTC-Monitor Control Register 198" hexmask.long.word 0x318 16.--31. 1. "KEYCODE,-" bitfld.long 0x318 7. "NUM1_EN,-" "0,1" bitfld.long 0x318 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x318 4. "CNT_RESET,-" "0,1" bitfld.long 0x318 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x318 1. "IMNTR_EN,-" "0,1" bitfld.long 0x318 0. "WAIT_SET,-" "0,1" line.long 0x31C "IMNTRCR199,INTC-Monitor Control Register 199" hexmask.long.word 0x31C 16.--31. 1. "KEYCODE,-" bitfld.long 0x31C 7. "NUM1_EN,-" "0,1" bitfld.long 0x31C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x31C 4. "CNT_RESET,-" "0,1" bitfld.long 0x31C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x31C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x31C 0. "WAIT_SET,-" "0,1" line.long 0x320 "IMNTRCR200,INTC-Monitor Control Register 200" hexmask.long.word 0x320 16.--31. 1. "KEYCODE,-" bitfld.long 0x320 7. "NUM1_EN,-" "0,1" bitfld.long 0x320 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x320 4. "CNT_RESET,-" "0,1" bitfld.long 0x320 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x320 1. "IMNTR_EN,-" "0,1" bitfld.long 0x320 0. "WAIT_SET,-" "0,1" line.long 0x324 "IMNTRCR201,INTC-Monitor Control Register 201" hexmask.long.word 0x324 16.--31. 1. "KEYCODE,-" bitfld.long 0x324 7. "NUM1_EN,-" "0,1" bitfld.long 0x324 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x324 4. "CNT_RESET,-" "0,1" bitfld.long 0x324 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x324 1. "IMNTR_EN,-" "0,1" bitfld.long 0x324 0. "WAIT_SET,-" "0,1" line.long 0x328 "IMNTRCR202,INTC-Monitor Control Register 202" hexmask.long.word 0x328 16.--31. 1. "KEYCODE,-" bitfld.long 0x328 7. "NUM1_EN,-" "0,1" bitfld.long 0x328 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x328 4. "CNT_RESET,-" "0,1" bitfld.long 0x328 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x328 1. "IMNTR_EN,-" "0,1" bitfld.long 0x328 0. "WAIT_SET,-" "0,1" line.long 0x32C "IMNTRCR203,INTC-Monitor Control Register 203" hexmask.long.word 0x32C 16.--31. 1. "KEYCODE,-" bitfld.long 0x32C 7. "NUM1_EN,-" "0,1" bitfld.long 0x32C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x32C 4. "CNT_RESET,-" "0,1" bitfld.long 0x32C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x32C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x32C 0. "WAIT_SET,-" "0,1" line.long 0x330 "IMNTRCR204,INTC-Monitor Control Register 204" hexmask.long.word 0x330 16.--31. 1. "KEYCODE,-" bitfld.long 0x330 7. "NUM1_EN,-" "0,1" bitfld.long 0x330 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x330 4. "CNT_RESET,-" "0,1" bitfld.long 0x330 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x330 1. "IMNTR_EN,-" "0,1" bitfld.long 0x330 0. "WAIT_SET,-" "0,1" line.long 0x334 "IMNTRCR205,INTC-Monitor Control Register 205" hexmask.long.word 0x334 16.--31. 1. "KEYCODE,-" bitfld.long 0x334 7. "NUM1_EN,-" "0,1" bitfld.long 0x334 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x334 4. "CNT_RESET,-" "0,1" bitfld.long 0x334 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x334 1. "IMNTR_EN,-" "0,1" bitfld.long 0x334 0. "WAIT_SET,-" "0,1" line.long 0x338 "IMNTRCR206,INTC-Monitor Control Register 206" hexmask.long.word 0x338 16.--31. 1. "KEYCODE,-" bitfld.long 0x338 7. "NUM1_EN,-" "0,1" bitfld.long 0x338 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x338 4. "CNT_RESET,-" "0,1" bitfld.long 0x338 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x338 1. "IMNTR_EN,-" "0,1" bitfld.long 0x338 0. "WAIT_SET,-" "0,1" line.long 0x33C "IMNTRCR207,INTC-Monitor Control Register 207" hexmask.long.word 0x33C 16.--31. 1. "KEYCODE,-" bitfld.long 0x33C 7. "NUM1_EN,-" "0,1" bitfld.long 0x33C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x33C 4. "CNT_RESET,-" "0,1" bitfld.long 0x33C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x33C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x33C 0. "WAIT_SET,-" "0,1" line.long 0x340 "IMNTRCR208,INTC-Monitor Control Register 208" hexmask.long.word 0x340 16.--31. 1. "KEYCODE,-" bitfld.long 0x340 7. "NUM1_EN,-" "0,1" bitfld.long 0x340 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x340 4. "CNT_RESET,-" "0,1" bitfld.long 0x340 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x340 1. "IMNTR_EN,-" "0,1" bitfld.long 0x340 0. "WAIT_SET,-" "0,1" line.long 0x344 "IMNTRCR209,INTC-Monitor Control Register 209" hexmask.long.word 0x344 16.--31. 1. "KEYCODE,-" bitfld.long 0x344 7. "NUM1_EN,-" "0,1" bitfld.long 0x344 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x344 4. "CNT_RESET,-" "0,1" bitfld.long 0x344 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x344 1. "IMNTR_EN,-" "0,1" bitfld.long 0x344 0. "WAIT_SET,-" "0,1" line.long 0x348 "IMNTRCR210,INTC-Monitor Control Register 210" hexmask.long.word 0x348 16.--31. 1. "KEYCODE,-" bitfld.long 0x348 7. "NUM1_EN,-" "0,1" bitfld.long 0x348 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x348 4. "CNT_RESET,-" "0,1" bitfld.long 0x348 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x348 1. "IMNTR_EN,-" "0,1" bitfld.long 0x348 0. "WAIT_SET,-" "0,1" line.long 0x34C "IMNTRCR211,INTC-Monitor Control Register 211" hexmask.long.word 0x34C 16.--31. 1. "KEYCODE,-" bitfld.long 0x34C 7. "NUM1_EN,-" "0,1" bitfld.long 0x34C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x34C 4. "CNT_RESET,-" "0,1" bitfld.long 0x34C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x34C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x34C 0. "WAIT_SET,-" "0,1" line.long 0x350 "IMNTRCR212,INTC-Monitor Control Register 212" hexmask.long.word 0x350 16.--31. 1. "KEYCODE,-" bitfld.long 0x350 7. "NUM1_EN,-" "0,1" bitfld.long 0x350 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x350 4. "CNT_RESET,-" "0,1" bitfld.long 0x350 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x350 1. "IMNTR_EN,-" "0,1" bitfld.long 0x350 0. "WAIT_SET,-" "0,1" line.long 0x354 "IMNTRCR213,INTC-Monitor Control Register 213" hexmask.long.word 0x354 16.--31. 1. "KEYCODE,-" bitfld.long 0x354 7. "NUM1_EN,-" "0,1" bitfld.long 0x354 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x354 4. "CNT_RESET,-" "0,1" bitfld.long 0x354 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x354 1. "IMNTR_EN,-" "0,1" bitfld.long 0x354 0. "WAIT_SET,-" "0,1" line.long 0x358 "IMNTRCR214,INTC-Monitor Control Register 214" hexmask.long.word 0x358 16.--31. 1. "KEYCODE,-" bitfld.long 0x358 7. "NUM1_EN,-" "0,1" bitfld.long 0x358 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x358 4. "CNT_RESET,-" "0,1" bitfld.long 0x358 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x358 1. "IMNTR_EN,-" "0,1" bitfld.long 0x358 0. "WAIT_SET,-" "0,1" line.long 0x35C "IMNTRCR215,INTC-Monitor Control Register 215" hexmask.long.word 0x35C 16.--31. 1. "KEYCODE,-" bitfld.long 0x35C 7. "NUM1_EN,-" "0,1" bitfld.long 0x35C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x35C 4. "CNT_RESET,-" "0,1" bitfld.long 0x35C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x35C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x35C 0. "WAIT_SET,-" "0,1" line.long 0x360 "IMNTRCR216,INTC-Monitor Control Register 216" hexmask.long.word 0x360 16.--31. 1. "KEYCODE,-" bitfld.long 0x360 7. "NUM1_EN,-" "0,1" bitfld.long 0x360 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x360 4. "CNT_RESET,-" "0,1" bitfld.long 0x360 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x360 1. "IMNTR_EN,-" "0,1" bitfld.long 0x360 0. "WAIT_SET,-" "0,1" line.long 0x364 "IMNTRCR217,INTC-Monitor Control Register 217" hexmask.long.word 0x364 16.--31. 1. "KEYCODE,-" bitfld.long 0x364 7. "NUM1_EN,-" "0,1" bitfld.long 0x364 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x364 4. "CNT_RESET,-" "0,1" bitfld.long 0x364 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x364 1. "IMNTR_EN,-" "0,1" bitfld.long 0x364 0. "WAIT_SET,-" "0,1" line.long 0x368 "IMNTRCR218,INTC-Monitor Control Register 218" hexmask.long.word 0x368 16.--31. 1. "KEYCODE,-" bitfld.long 0x368 7. "NUM1_EN,-" "0,1" bitfld.long 0x368 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x368 4. "CNT_RESET,-" "0,1" bitfld.long 0x368 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x368 1. "IMNTR_EN,-" "0,1" bitfld.long 0x368 0. "WAIT_SET,-" "0,1" line.long 0x36C "IMNTRCR219,INTC-Monitor Control Register 219" hexmask.long.word 0x36C 16.--31. 1. "KEYCODE,-" bitfld.long 0x36C 7. "NUM1_EN,-" "0,1" bitfld.long 0x36C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x36C 4. "CNT_RESET,-" "0,1" bitfld.long 0x36C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x36C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x36C 0. "WAIT_SET,-" "0,1" line.long 0x370 "IMNTRCR220,INTC-Monitor Control Register 220" hexmask.long.word 0x370 16.--31. 1. "KEYCODE,-" bitfld.long 0x370 7. "NUM1_EN,-" "0,1" bitfld.long 0x370 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x370 4. "CNT_RESET,-" "0,1" bitfld.long 0x370 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x370 1. "IMNTR_EN,-" "0,1" bitfld.long 0x370 0. "WAIT_SET,-" "0,1" line.long 0x374 "IMNTRCR221,INTC-Monitor Control Register 221" hexmask.long.word 0x374 16.--31. 1. "KEYCODE,-" bitfld.long 0x374 7. "NUM1_EN,-" "0,1" bitfld.long 0x374 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x374 4. "CNT_RESET,-" "0,1" bitfld.long 0x374 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x374 1. "IMNTR_EN,-" "0,1" bitfld.long 0x374 0. "WAIT_SET,-" "0,1" line.long 0x378 "IMNTRCR222,INTC-Monitor Control Register 222" hexmask.long.word 0x378 16.--31. 1. "KEYCODE,-" bitfld.long 0x378 7. "NUM1_EN,-" "0,1" bitfld.long 0x378 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x378 4. "CNT_RESET,-" "0,1" bitfld.long 0x378 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x378 1. "IMNTR_EN,-" "0,1" bitfld.long 0x378 0. "WAIT_SET,-" "0,1" line.long 0x37C "IMNTRCR223,INTC-Monitor Control Register 223" hexmask.long.word 0x37C 16.--31. 1. "KEYCODE,-" bitfld.long 0x37C 7. "NUM1_EN,-" "0,1" bitfld.long 0x37C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x37C 4. "CNT_RESET,-" "0,1" bitfld.long 0x37C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x37C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x37C 0. "WAIT_SET,-" "0,1" line.long 0x380 "IMNTRCR224,INTC-Monitor Control Register 224" hexmask.long.word 0x380 16.--31. 1. "KEYCODE,-" bitfld.long 0x380 7. "NUM1_EN,-" "0,1" bitfld.long 0x380 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x380 4. "CNT_RESET,-" "0,1" bitfld.long 0x380 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x380 1. "IMNTR_EN,-" "0,1" bitfld.long 0x380 0. "WAIT_SET,-" "0,1" line.long 0x384 "IMNTRCR225,INTC-Monitor Control Register 225" hexmask.long.word 0x384 16.--31. 1. "KEYCODE,-" bitfld.long 0x384 7. "NUM1_EN,-" "0,1" bitfld.long 0x384 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x384 4. "CNT_RESET,-" "0,1" bitfld.long 0x384 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x384 1. "IMNTR_EN,-" "0,1" bitfld.long 0x384 0. "WAIT_SET,-" "0,1" line.long 0x388 "IMNTRCR226,INTC-Monitor Control Register 226" hexmask.long.word 0x388 16.--31. 1. "KEYCODE,-" bitfld.long 0x388 7. "NUM1_EN,-" "0,1" bitfld.long 0x388 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x388 4. "CNT_RESET,-" "0,1" bitfld.long 0x388 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x388 1. "IMNTR_EN,-" "0,1" bitfld.long 0x388 0. "WAIT_SET,-" "0,1" line.long 0x38C "IMNTRCR227,INTC-Monitor Control Register 227" hexmask.long.word 0x38C 16.--31. 1. "KEYCODE,-" bitfld.long 0x38C 7. "NUM1_EN,-" "0,1" bitfld.long 0x38C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x38C 4. "CNT_RESET,-" "0,1" bitfld.long 0x38C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x38C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x38C 0. "WAIT_SET,-" "0,1" line.long 0x390 "IMNTRCR228,INTC-Monitor Control Register 228" hexmask.long.word 0x390 16.--31. 1. "KEYCODE,-" bitfld.long 0x390 7. "NUM1_EN,-" "0,1" bitfld.long 0x390 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x390 4. "CNT_RESET,-" "0,1" bitfld.long 0x390 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x390 1. "IMNTR_EN,-" "0,1" bitfld.long 0x390 0. "WAIT_SET,-" "0,1" line.long 0x394 "IMNTRCR229,INTC-Monitor Control Register 229" hexmask.long.word 0x394 16.--31. 1. "KEYCODE,-" bitfld.long 0x394 7. "NUM1_EN,-" "0,1" bitfld.long 0x394 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x394 4. "CNT_RESET,-" "0,1" bitfld.long 0x394 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x394 1. "IMNTR_EN,-" "0,1" bitfld.long 0x394 0. "WAIT_SET,-" "0,1" line.long 0x398 "IMNTRCR230,INTC-Monitor Control Register 230" hexmask.long.word 0x398 16.--31. 1. "KEYCODE,-" bitfld.long 0x398 7. "NUM1_EN,-" "0,1" bitfld.long 0x398 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x398 4. "CNT_RESET,-" "0,1" bitfld.long 0x398 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x398 1. "IMNTR_EN,-" "0,1" bitfld.long 0x398 0. "WAIT_SET,-" "0,1" line.long 0x39C "IMNTRCR231,INTC-Monitor Control Register 231" hexmask.long.word 0x39C 16.--31. 1. "KEYCODE,-" bitfld.long 0x39C 7. "NUM1_EN,-" "0,1" bitfld.long 0x39C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x39C 4. "CNT_RESET,-" "0,1" bitfld.long 0x39C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x39C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x39C 0. "WAIT_SET,-" "0,1" line.long 0x3A0 "IMNTRCR232,INTC-Monitor Control Register 232" hexmask.long.word 0x3A0 16.--31. 1. "KEYCODE,-" bitfld.long 0x3A0 7. "NUM1_EN,-" "0,1" bitfld.long 0x3A0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3A0 4. "CNT_RESET,-" "0,1" bitfld.long 0x3A0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3A0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3A0 0. "WAIT_SET,-" "0,1" line.long 0x3A4 "IMNTRCR233,INTC-Monitor Control Register 233" hexmask.long.word 0x3A4 16.--31. 1. "KEYCODE,-" bitfld.long 0x3A4 7. "NUM1_EN,-" "0,1" bitfld.long 0x3A4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3A4 4. "CNT_RESET,-" "0,1" bitfld.long 0x3A4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3A4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3A4 0. "WAIT_SET,-" "0,1" line.long 0x3A8 "IMNTRCR234,INTC-Monitor Control Register 234" hexmask.long.word 0x3A8 16.--31. 1. "KEYCODE,-" bitfld.long 0x3A8 7. "NUM1_EN,-" "0,1" bitfld.long 0x3A8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3A8 4. "CNT_RESET,-" "0,1" bitfld.long 0x3A8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3A8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3A8 0. "WAIT_SET,-" "0,1" line.long 0x3AC "IMNTRCR235,INTC-Monitor Control Register 235" hexmask.long.word 0x3AC 16.--31. 1. "KEYCODE,-" bitfld.long 0x3AC 7. "NUM1_EN,-" "0,1" bitfld.long 0x3AC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3AC 4. "CNT_RESET,-" "0,1" bitfld.long 0x3AC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3AC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3AC 0. "WAIT_SET,-" "0,1" line.long 0x3B0 "IMNTRCR236,INTC-Monitor Control Register 236" hexmask.long.word 0x3B0 16.--31. 1. "KEYCODE,-" bitfld.long 0x3B0 7. "NUM1_EN,-" "0,1" bitfld.long 0x3B0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3B0 4. "CNT_RESET,-" "0,1" bitfld.long 0x3B0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3B0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3B0 0. "WAIT_SET,-" "0,1" line.long 0x3B4 "IMNTRCR237,INTC-Monitor Control Register 237" hexmask.long.word 0x3B4 16.--31. 1. "KEYCODE,-" bitfld.long 0x3B4 7. "NUM1_EN,-" "0,1" bitfld.long 0x3B4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3B4 4. "CNT_RESET,-" "0,1" bitfld.long 0x3B4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3B4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3B4 0. "WAIT_SET,-" "0,1" line.long 0x3B8 "IMNTRCR238,INTC-Monitor Control Register 238" hexmask.long.word 0x3B8 16.--31. 1. "KEYCODE,-" bitfld.long 0x3B8 7. "NUM1_EN,-" "0,1" bitfld.long 0x3B8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3B8 4. "CNT_RESET,-" "0,1" bitfld.long 0x3B8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3B8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3B8 0. "WAIT_SET,-" "0,1" line.long 0x3BC "IMNTRCR239,INTC-Monitor Control Register 239" hexmask.long.word 0x3BC 16.--31. 1. "KEYCODE,-" bitfld.long 0x3BC 7. "NUM1_EN,-" "0,1" bitfld.long 0x3BC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3BC 4. "CNT_RESET,-" "0,1" bitfld.long 0x3BC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3BC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3BC 0. "WAIT_SET,-" "0,1" line.long 0x3C0 "IMNTRCR240,INTC-Monitor Control Register 240" hexmask.long.word 0x3C0 16.--31. 1. "KEYCODE,-" bitfld.long 0x3C0 7. "NUM1_EN,-" "0,1" bitfld.long 0x3C0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3C0 4. "CNT_RESET,-" "0,1" bitfld.long 0x3C0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3C0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3C0 0. "WAIT_SET,-" "0,1" line.long 0x3C4 "IMNTRCR241,INTC-Monitor Control Register 241" hexmask.long.word 0x3C4 16.--31. 1. "KEYCODE,-" bitfld.long 0x3C4 7. "NUM1_EN,-" "0,1" bitfld.long 0x3C4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3C4 4. "CNT_RESET,-" "0,1" bitfld.long 0x3C4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3C4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3C4 0. "WAIT_SET,-" "0,1" line.long 0x3C8 "IMNTRCR242,INTC-Monitor Control Register 242" hexmask.long.word 0x3C8 16.--31. 1. "KEYCODE,-" bitfld.long 0x3C8 7. "NUM1_EN,-" "0,1" bitfld.long 0x3C8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3C8 4. "CNT_RESET,-" "0,1" bitfld.long 0x3C8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3C8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3C8 0. "WAIT_SET,-" "0,1" line.long 0x3CC "IMNTRCR243,INTC-Monitor Control Register 243" hexmask.long.word 0x3CC 16.--31. 1. "KEYCODE,-" bitfld.long 0x3CC 7. "NUM1_EN,-" "0,1" bitfld.long 0x3CC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3CC 4. "CNT_RESET,-" "0,1" bitfld.long 0x3CC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3CC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3CC 0. "WAIT_SET,-" "0,1" line.long 0x3D0 "IMNTRCR244,INTC-Monitor Control Register 244" hexmask.long.word 0x3D0 16.--31. 1. "KEYCODE,-" bitfld.long 0x3D0 7. "NUM1_EN,-" "0,1" bitfld.long 0x3D0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3D0 4. "CNT_RESET,-" "0,1" bitfld.long 0x3D0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3D0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3D0 0. "WAIT_SET,-" "0,1" line.long 0x3D4 "IMNTRCR245,INTC-Monitor Control Register 245" hexmask.long.word 0x3D4 16.--31. 1. "KEYCODE,-" bitfld.long 0x3D4 7. "NUM1_EN,-" "0,1" bitfld.long 0x3D4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3D4 4. "CNT_RESET,-" "0,1" bitfld.long 0x3D4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3D4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3D4 0. "WAIT_SET,-" "0,1" line.long 0x3D8 "IMNTRCR246,INTC-Monitor Control Register 246" hexmask.long.word 0x3D8 16.--31. 1. "KEYCODE,-" bitfld.long 0x3D8 7. "NUM1_EN,-" "0,1" bitfld.long 0x3D8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3D8 4. "CNT_RESET,-" "0,1" bitfld.long 0x3D8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3D8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3D8 0. "WAIT_SET,-" "0,1" line.long 0x3DC "IMNTRCR247,INTC-Monitor Control Register 247" hexmask.long.word 0x3DC 16.--31. 1. "KEYCODE,-" bitfld.long 0x3DC 7. "NUM1_EN,-" "0,1" bitfld.long 0x3DC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3DC 4. "CNT_RESET,-" "0,1" bitfld.long 0x3DC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3DC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3DC 0. "WAIT_SET,-" "0,1" line.long 0x3E0 "IMNTRCR248,INTC-Monitor Control Register 248" hexmask.long.word 0x3E0 16.--31. 1. "KEYCODE,-" bitfld.long 0x3E0 7. "NUM1_EN,-" "0,1" bitfld.long 0x3E0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3E0 4. "CNT_RESET,-" "0,1" bitfld.long 0x3E0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3E0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3E0 0. "WAIT_SET,-" "0,1" line.long 0x3E4 "IMNTRCR249,INTC-Monitor Control Register 249" hexmask.long.word 0x3E4 16.--31. 1. "KEYCODE,-" bitfld.long 0x3E4 7. "NUM1_EN,-" "0,1" bitfld.long 0x3E4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3E4 4. "CNT_RESET,-" "0,1" bitfld.long 0x3E4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3E4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3E4 0. "WAIT_SET,-" "0,1" line.long 0x3E8 "IMNTRCR250,INTC-Monitor Control Register 250" hexmask.long.word 0x3E8 16.--31. 1. "KEYCODE,-" bitfld.long 0x3E8 7. "NUM1_EN,-" "0,1" bitfld.long 0x3E8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3E8 4. "CNT_RESET,-" "0,1" bitfld.long 0x3E8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3E8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3E8 0. "WAIT_SET,-" "0,1" line.long 0x3EC "IMNTRCR251,INTC-Monitor Control Register 251" hexmask.long.word 0x3EC 16.--31. 1. "KEYCODE,-" bitfld.long 0x3EC 7. "NUM1_EN,-" "0,1" bitfld.long 0x3EC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3EC 4. "CNT_RESET,-" "0,1" bitfld.long 0x3EC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3EC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3EC 0. "WAIT_SET,-" "0,1" line.long 0x3F0 "IMNTRCR252,INTC-Monitor Control Register 252" hexmask.long.word 0x3F0 16.--31. 1. "KEYCODE,-" bitfld.long 0x3F0 7. "NUM1_EN,-" "0,1" bitfld.long 0x3F0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3F0 4. "CNT_RESET,-" "0,1" bitfld.long 0x3F0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3F0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3F0 0. "WAIT_SET,-" "0,1" line.long 0x3F4 "IMNTRCR253,INTC-Monitor Control Register 253" hexmask.long.word 0x3F4 16.--31. 1. "KEYCODE,-" bitfld.long 0x3F4 7. "NUM1_EN,-" "0,1" bitfld.long 0x3F4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3F4 4. "CNT_RESET,-" "0,1" bitfld.long 0x3F4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3F4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3F4 0. "WAIT_SET,-" "0,1" line.long 0x3F8 "IMNTRCR254,INTC-Monitor Control Register 254" hexmask.long.word 0x3F8 16.--31. 1. "KEYCODE,-" bitfld.long 0x3F8 7. "NUM1_EN,-" "0,1" bitfld.long 0x3F8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3F8 4. "CNT_RESET,-" "0,1" bitfld.long 0x3F8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3F8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3F8 0. "WAIT_SET,-" "0,1" line.long 0x3FC "IMNTRCR255,INTC-Monitor Control Register 255" hexmask.long.word 0x3FC 16.--31. 1. "KEYCODE,-" bitfld.long 0x3FC 7. "NUM1_EN,-" "0,1" bitfld.long 0x3FC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x3FC 4. "CNT_RESET,-" "0,1" bitfld.long 0x3FC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x3FC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x3FC 0. "WAIT_SET,-" "0,1" line.long 0x400 "IMNTRCR256,INTC-Monitor Control Register 256" hexmask.long.word 0x400 16.--31. 1. "KEYCODE,-" bitfld.long 0x400 7. "NUM1_EN,-" "0,1" bitfld.long 0x400 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x400 4. "CNT_RESET,-" "0,1" bitfld.long 0x400 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x400 1. "IMNTR_EN,-" "0,1" bitfld.long 0x400 0. "WAIT_SET,-" "0,1" line.long 0x404 "IMNTRCR257,INTC-Monitor Control Register 257" hexmask.long.word 0x404 16.--31. 1. "KEYCODE,-" bitfld.long 0x404 7. "NUM1_EN,-" "0,1" bitfld.long 0x404 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x404 4. "CNT_RESET,-" "0,1" bitfld.long 0x404 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x404 1. "IMNTR_EN,-" "0,1" bitfld.long 0x404 0. "WAIT_SET,-" "0,1" line.long 0x408 "IMNTRCR258,INTC-Monitor Control Register 258" hexmask.long.word 0x408 16.--31. 1. "KEYCODE,-" bitfld.long 0x408 7. "NUM1_EN,-" "0,1" bitfld.long 0x408 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x408 4. "CNT_RESET,-" "0,1" bitfld.long 0x408 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x408 1. "IMNTR_EN,-" "0,1" bitfld.long 0x408 0. "WAIT_SET,-" "0,1" line.long 0x40C "IMNTRCR259,INTC-Monitor Control Register 259" hexmask.long.word 0x40C 16.--31. 1. "KEYCODE,-" bitfld.long 0x40C 7. "NUM1_EN,-" "0,1" bitfld.long 0x40C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x40C 4. "CNT_RESET,-" "0,1" bitfld.long 0x40C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x40C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x40C 0. "WAIT_SET,-" "0,1" line.long 0x410 "IMNTRCR260,INTC-Monitor Control Register 260" hexmask.long.word 0x410 16.--31. 1. "KEYCODE,-" bitfld.long 0x410 7. "NUM1_EN,-" "0,1" bitfld.long 0x410 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x410 4. "CNT_RESET,-" "0,1" bitfld.long 0x410 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x410 1. "IMNTR_EN,-" "0,1" bitfld.long 0x410 0. "WAIT_SET,-" "0,1" line.long 0x414 "IMNTRCR261,INTC-Monitor Control Register 261" hexmask.long.word 0x414 16.--31. 1. "KEYCODE,-" bitfld.long 0x414 7. "NUM1_EN,-" "0,1" bitfld.long 0x414 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x414 4. "CNT_RESET,-" "0,1" bitfld.long 0x414 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x414 1. "IMNTR_EN,-" "0,1" bitfld.long 0x414 0. "WAIT_SET,-" "0,1" line.long 0x418 "IMNTRCR262,INTC-Monitor Control Register 262" hexmask.long.word 0x418 16.--31. 1. "KEYCODE,-" bitfld.long 0x418 7. "NUM1_EN,-" "0,1" bitfld.long 0x418 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x418 4. "CNT_RESET,-" "0,1" bitfld.long 0x418 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x418 1. "IMNTR_EN,-" "0,1" bitfld.long 0x418 0. "WAIT_SET,-" "0,1" line.long 0x41C "IMNTRCR263,INTC-Monitor Control Register 263" hexmask.long.word 0x41C 16.--31. 1. "KEYCODE,-" bitfld.long 0x41C 7. "NUM1_EN,-" "0,1" bitfld.long 0x41C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x41C 4. "CNT_RESET,-" "0,1" bitfld.long 0x41C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x41C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x41C 0. "WAIT_SET,-" "0,1" line.long 0x420 "IMNTRCR264,INTC-Monitor Control Register 264" hexmask.long.word 0x420 16.--31. 1. "KEYCODE,-" bitfld.long 0x420 7. "NUM1_EN,-" "0,1" bitfld.long 0x420 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x420 4. "CNT_RESET,-" "0,1" bitfld.long 0x420 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x420 1. "IMNTR_EN,-" "0,1" bitfld.long 0x420 0. "WAIT_SET,-" "0,1" line.long 0x424 "IMNTRCR265,INTC-Monitor Control Register 265" hexmask.long.word 0x424 16.--31. 1. "KEYCODE,-" bitfld.long 0x424 7. "NUM1_EN,-" "0,1" bitfld.long 0x424 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x424 4. "CNT_RESET,-" "0,1" bitfld.long 0x424 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x424 1. "IMNTR_EN,-" "0,1" bitfld.long 0x424 0. "WAIT_SET,-" "0,1" line.long 0x428 "IMNTRCR266,INTC-Monitor Control Register 266" hexmask.long.word 0x428 16.--31. 1. "KEYCODE,-" bitfld.long 0x428 7. "NUM1_EN,-" "0,1" bitfld.long 0x428 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x428 4. "CNT_RESET,-" "0,1" bitfld.long 0x428 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x428 1. "IMNTR_EN,-" "0,1" bitfld.long 0x428 0. "WAIT_SET,-" "0,1" line.long 0x42C "IMNTRCR267,INTC-Monitor Control Register 267" hexmask.long.word 0x42C 16.--31. 1. "KEYCODE,-" bitfld.long 0x42C 7. "NUM1_EN,-" "0,1" bitfld.long 0x42C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x42C 4. "CNT_RESET,-" "0,1" bitfld.long 0x42C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x42C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x42C 0. "WAIT_SET,-" "0,1" line.long 0x430 "IMNTRCR268,INTC-Monitor Control Register 268" hexmask.long.word 0x430 16.--31. 1. "KEYCODE,-" bitfld.long 0x430 7. "NUM1_EN,-" "0,1" bitfld.long 0x430 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x430 4. "CNT_RESET,-" "0,1" bitfld.long 0x430 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x430 1. "IMNTR_EN,-" "0,1" bitfld.long 0x430 0. "WAIT_SET,-" "0,1" line.long 0x434 "IMNTRCR269,INTC-Monitor Control Register 269" hexmask.long.word 0x434 16.--31. 1. "KEYCODE,-" bitfld.long 0x434 7. "NUM1_EN,-" "0,1" bitfld.long 0x434 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x434 4. "CNT_RESET,-" "0,1" bitfld.long 0x434 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x434 1. "IMNTR_EN,-" "0,1" bitfld.long 0x434 0. "WAIT_SET,-" "0,1" line.long 0x438 "IMNTRCR270,INTC-Monitor Control Register 270" hexmask.long.word 0x438 16.--31. 1. "KEYCODE,-" bitfld.long 0x438 7. "NUM1_EN,-" "0,1" bitfld.long 0x438 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x438 4. "CNT_RESET,-" "0,1" bitfld.long 0x438 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x438 1. "IMNTR_EN,-" "0,1" bitfld.long 0x438 0. "WAIT_SET,-" "0,1" line.long 0x43C "IMNTRCR271,INTC-Monitor Control Register 271" hexmask.long.word 0x43C 16.--31. 1. "KEYCODE,-" bitfld.long 0x43C 7. "NUM1_EN,-" "0,1" bitfld.long 0x43C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x43C 4. "CNT_RESET,-" "0,1" bitfld.long 0x43C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x43C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x43C 0. "WAIT_SET,-" "0,1" line.long 0x440 "IMNTRCR272,INTC-Monitor Control Register 272" hexmask.long.word 0x440 16.--31. 1. "KEYCODE,-" bitfld.long 0x440 7. "NUM1_EN,-" "0,1" bitfld.long 0x440 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x440 4. "CNT_RESET,-" "0,1" bitfld.long 0x440 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x440 1. "IMNTR_EN,-" "0,1" bitfld.long 0x440 0. "WAIT_SET,-" "0,1" line.long 0x444 "IMNTRCR273,INTC-Monitor Control Register 273" hexmask.long.word 0x444 16.--31. 1. "KEYCODE,-" bitfld.long 0x444 7. "NUM1_EN,-" "0,1" bitfld.long 0x444 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x444 4. "CNT_RESET,-" "0,1" bitfld.long 0x444 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x444 1. "IMNTR_EN,-" "0,1" bitfld.long 0x444 0. "WAIT_SET,-" "0,1" line.long 0x448 "IMNTRCR274,INTC-Monitor Control Register 274" hexmask.long.word 0x448 16.--31. 1. "KEYCODE,-" bitfld.long 0x448 7. "NUM1_EN,-" "0,1" bitfld.long 0x448 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x448 4. "CNT_RESET,-" "0,1" bitfld.long 0x448 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x448 1. "IMNTR_EN,-" "0,1" bitfld.long 0x448 0. "WAIT_SET,-" "0,1" line.long 0x44C "IMNTRCR275,INTC-Monitor Control Register 275" hexmask.long.word 0x44C 16.--31. 1. "KEYCODE,-" bitfld.long 0x44C 7. "NUM1_EN,-" "0,1" bitfld.long 0x44C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x44C 4. "CNT_RESET,-" "0,1" bitfld.long 0x44C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x44C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x44C 0. "WAIT_SET,-" "0,1" line.long 0x450 "IMNTRCR276,INTC-Monitor Control Register 276" hexmask.long.word 0x450 16.--31. 1. "KEYCODE,-" bitfld.long 0x450 7. "NUM1_EN,-" "0,1" bitfld.long 0x450 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x450 4. "CNT_RESET,-" "0,1" bitfld.long 0x450 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x450 1. "IMNTR_EN,-" "0,1" bitfld.long 0x450 0. "WAIT_SET,-" "0,1" line.long 0x454 "IMNTRCR277,INTC-Monitor Control Register 277" hexmask.long.word 0x454 16.--31. 1. "KEYCODE,-" bitfld.long 0x454 7. "NUM1_EN,-" "0,1" bitfld.long 0x454 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x454 4. "CNT_RESET,-" "0,1" bitfld.long 0x454 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x454 1. "IMNTR_EN,-" "0,1" bitfld.long 0x454 0. "WAIT_SET,-" "0,1" line.long 0x458 "IMNTRCR278,INTC-Monitor Control Register 278" hexmask.long.word 0x458 16.--31. 1. "KEYCODE,-" bitfld.long 0x458 7. "NUM1_EN,-" "0,1" bitfld.long 0x458 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x458 4. "CNT_RESET,-" "0,1" bitfld.long 0x458 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x458 1. "IMNTR_EN,-" "0,1" bitfld.long 0x458 0. "WAIT_SET,-" "0,1" line.long 0x45C "IMNTRCR279,INTC-Monitor Control Register 279" hexmask.long.word 0x45C 16.--31. 1. "KEYCODE,-" bitfld.long 0x45C 7. "NUM1_EN,-" "0,1" bitfld.long 0x45C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x45C 4. "CNT_RESET,-" "0,1" bitfld.long 0x45C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x45C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x45C 0. "WAIT_SET,-" "0,1" line.long 0x460 "IMNTRCR280,INTC-Monitor Control Register 280" hexmask.long.word 0x460 16.--31. 1. "KEYCODE,-" bitfld.long 0x460 7. "NUM1_EN,-" "0,1" bitfld.long 0x460 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x460 4. "CNT_RESET,-" "0,1" bitfld.long 0x460 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x460 1. "IMNTR_EN,-" "0,1" bitfld.long 0x460 0. "WAIT_SET,-" "0,1" line.long 0x464 "IMNTRCR281,INTC-Monitor Control Register 281" hexmask.long.word 0x464 16.--31. 1. "KEYCODE,-" bitfld.long 0x464 7. "NUM1_EN,-" "0,1" bitfld.long 0x464 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x464 4. "CNT_RESET,-" "0,1" bitfld.long 0x464 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x464 1. "IMNTR_EN,-" "0,1" bitfld.long 0x464 0. "WAIT_SET,-" "0,1" line.long 0x468 "IMNTRCR282,INTC-Monitor Control Register 282" hexmask.long.word 0x468 16.--31. 1. "KEYCODE,-" bitfld.long 0x468 7. "NUM1_EN,-" "0,1" bitfld.long 0x468 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x468 4. "CNT_RESET,-" "0,1" bitfld.long 0x468 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x468 1. "IMNTR_EN,-" "0,1" bitfld.long 0x468 0. "WAIT_SET,-" "0,1" line.long 0x46C "IMNTRCR283,INTC-Monitor Control Register 283" hexmask.long.word 0x46C 16.--31. 1. "KEYCODE,-" bitfld.long 0x46C 7. "NUM1_EN,-" "0,1" bitfld.long 0x46C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x46C 4. "CNT_RESET,-" "0,1" bitfld.long 0x46C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x46C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x46C 0. "WAIT_SET,-" "0,1" line.long 0x470 "IMNTRCR284,INTC-Monitor Control Register 284" hexmask.long.word 0x470 16.--31. 1. "KEYCODE,-" bitfld.long 0x470 7. "NUM1_EN,-" "0,1" bitfld.long 0x470 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x470 4. "CNT_RESET,-" "0,1" bitfld.long 0x470 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x470 1. "IMNTR_EN,-" "0,1" bitfld.long 0x470 0. "WAIT_SET,-" "0,1" line.long 0x474 "IMNTRCR285,INTC-Monitor Control Register 285" hexmask.long.word 0x474 16.--31. 1. "KEYCODE,-" bitfld.long 0x474 7. "NUM1_EN,-" "0,1" bitfld.long 0x474 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x474 4. "CNT_RESET,-" "0,1" bitfld.long 0x474 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x474 1. "IMNTR_EN,-" "0,1" bitfld.long 0x474 0. "WAIT_SET,-" "0,1" line.long 0x478 "IMNTRCR286,INTC-Monitor Control Register 286" hexmask.long.word 0x478 16.--31. 1. "KEYCODE,-" bitfld.long 0x478 7. "NUM1_EN,-" "0,1" bitfld.long 0x478 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x478 4. "CNT_RESET,-" "0,1" bitfld.long 0x478 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x478 1. "IMNTR_EN,-" "0,1" bitfld.long 0x478 0. "WAIT_SET,-" "0,1" line.long 0x47C "IMNTRCR287,INTC-Monitor Control Register 287" hexmask.long.word 0x47C 16.--31. 1. "KEYCODE,-" bitfld.long 0x47C 7. "NUM1_EN,-" "0,1" bitfld.long 0x47C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x47C 4. "CNT_RESET,-" "0,1" bitfld.long 0x47C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x47C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x47C 0. "WAIT_SET,-" "0,1" line.long 0x480 "IMNTRCR288,INTC-Monitor Control Register 288" hexmask.long.word 0x480 16.--31. 1. "KEYCODE,-" bitfld.long 0x480 7. "NUM1_EN,-" "0,1" bitfld.long 0x480 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x480 4. "CNT_RESET,-" "0,1" bitfld.long 0x480 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x480 1. "IMNTR_EN,-" "0,1" bitfld.long 0x480 0. "WAIT_SET,-" "0,1" line.long 0x484 "IMNTRCR289,INTC-Monitor Control Register 289" hexmask.long.word 0x484 16.--31. 1. "KEYCODE,-" bitfld.long 0x484 7. "NUM1_EN,-" "0,1" bitfld.long 0x484 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x484 4. "CNT_RESET,-" "0,1" bitfld.long 0x484 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x484 1. "IMNTR_EN,-" "0,1" bitfld.long 0x484 0. "WAIT_SET,-" "0,1" line.long 0x488 "IMNTRCR290,INTC-Monitor Control Register 290" hexmask.long.word 0x488 16.--31. 1. "KEYCODE,-" bitfld.long 0x488 7. "NUM1_EN,-" "0,1" bitfld.long 0x488 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x488 4. "CNT_RESET,-" "0,1" bitfld.long 0x488 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x488 1. "IMNTR_EN,-" "0,1" bitfld.long 0x488 0. "WAIT_SET,-" "0,1" line.long 0x48C "IMNTRCR291,INTC-Monitor Control Register 291" hexmask.long.word 0x48C 16.--31. 1. "KEYCODE,-" bitfld.long 0x48C 7. "NUM1_EN,-" "0,1" bitfld.long 0x48C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x48C 4. "CNT_RESET,-" "0,1" bitfld.long 0x48C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x48C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x48C 0. "WAIT_SET,-" "0,1" line.long 0x490 "IMNTRCR292,INTC-Monitor Control Register 292" hexmask.long.word 0x490 16.--31. 1. "KEYCODE,-" bitfld.long 0x490 7. "NUM1_EN,-" "0,1" bitfld.long 0x490 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x490 4. "CNT_RESET,-" "0,1" bitfld.long 0x490 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x490 1. "IMNTR_EN,-" "0,1" bitfld.long 0x490 0. "WAIT_SET,-" "0,1" line.long 0x494 "IMNTRCR293,INTC-Monitor Control Register 293" hexmask.long.word 0x494 16.--31. 1. "KEYCODE,-" bitfld.long 0x494 7. "NUM1_EN,-" "0,1" bitfld.long 0x494 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x494 4. "CNT_RESET,-" "0,1" bitfld.long 0x494 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x494 1. "IMNTR_EN,-" "0,1" bitfld.long 0x494 0. "WAIT_SET,-" "0,1" line.long 0x498 "IMNTRCR294,INTC-Monitor Control Register 294" hexmask.long.word 0x498 16.--31. 1. "KEYCODE,-" bitfld.long 0x498 7. "NUM1_EN,-" "0,1" bitfld.long 0x498 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x498 4. "CNT_RESET,-" "0,1" bitfld.long 0x498 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x498 1. "IMNTR_EN,-" "0,1" bitfld.long 0x498 0. "WAIT_SET,-" "0,1" line.long 0x49C "IMNTRCR295,INTC-Monitor Control Register 295" hexmask.long.word 0x49C 16.--31. 1. "KEYCODE,-" bitfld.long 0x49C 7. "NUM1_EN,-" "0,1" bitfld.long 0x49C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x49C 4. "CNT_RESET,-" "0,1" bitfld.long 0x49C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x49C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x49C 0. "WAIT_SET,-" "0,1" line.long 0x4A0 "IMNTRCR296,INTC-Monitor Control Register 296" hexmask.long.word 0x4A0 16.--31. 1. "KEYCODE,-" bitfld.long 0x4A0 7. "NUM1_EN,-" "0,1" bitfld.long 0x4A0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4A0 4. "CNT_RESET,-" "0,1" bitfld.long 0x4A0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4A0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4A0 0. "WAIT_SET,-" "0,1" line.long 0x4A4 "IMNTRCR297,INTC-Monitor Control Register 297" hexmask.long.word 0x4A4 16.--31. 1. "KEYCODE,-" bitfld.long 0x4A4 7. "NUM1_EN,-" "0,1" bitfld.long 0x4A4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4A4 4. "CNT_RESET,-" "0,1" bitfld.long 0x4A4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4A4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4A4 0. "WAIT_SET,-" "0,1" line.long 0x4A8 "IMNTRCR298,INTC-Monitor Control Register 298" hexmask.long.word 0x4A8 16.--31. 1. "KEYCODE,-" bitfld.long 0x4A8 7. "NUM1_EN,-" "0,1" bitfld.long 0x4A8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4A8 4. "CNT_RESET,-" "0,1" bitfld.long 0x4A8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4A8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4A8 0. "WAIT_SET,-" "0,1" line.long 0x4AC "IMNTRCR299,INTC-Monitor Control Register 299" hexmask.long.word 0x4AC 16.--31. 1. "KEYCODE,-" bitfld.long 0x4AC 7. "NUM1_EN,-" "0,1" bitfld.long 0x4AC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4AC 4. "CNT_RESET,-" "0,1" bitfld.long 0x4AC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4AC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4AC 0. "WAIT_SET,-" "0,1" line.long 0x4B0 "IMNTRCR300,INTC-Monitor Control Register 300" hexmask.long.word 0x4B0 16.--31. 1. "KEYCODE,-" bitfld.long 0x4B0 7. "NUM1_EN,-" "0,1" bitfld.long 0x4B0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4B0 4. "CNT_RESET,-" "0,1" bitfld.long 0x4B0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4B0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4B0 0. "WAIT_SET,-" "0,1" line.long 0x4B4 "IMNTRCR301,INTC-Monitor Control Register 301" hexmask.long.word 0x4B4 16.--31. 1. "KEYCODE,-" bitfld.long 0x4B4 7. "NUM1_EN,-" "0,1" bitfld.long 0x4B4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4B4 4. "CNT_RESET,-" "0,1" bitfld.long 0x4B4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4B4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4B4 0. "WAIT_SET,-" "0,1" line.long 0x4B8 "IMNTRCR302,INTC-Monitor Control Register 302" hexmask.long.word 0x4B8 16.--31. 1. "KEYCODE,-" bitfld.long 0x4B8 7. "NUM1_EN,-" "0,1" bitfld.long 0x4B8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4B8 4. "CNT_RESET,-" "0,1" bitfld.long 0x4B8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4B8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4B8 0. "WAIT_SET,-" "0,1" line.long 0x4BC "IMNTRCR303,INTC-Monitor Control Register 303" hexmask.long.word 0x4BC 16.--31. 1. "KEYCODE,-" bitfld.long 0x4BC 7. "NUM1_EN,-" "0,1" bitfld.long 0x4BC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4BC 4. "CNT_RESET,-" "0,1" bitfld.long 0x4BC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4BC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4BC 0. "WAIT_SET,-" "0,1" line.long 0x4C0 "IMNTRCR304,INTC-Monitor Control Register 304" hexmask.long.word 0x4C0 16.--31. 1. "KEYCODE,-" bitfld.long 0x4C0 7. "NUM1_EN,-" "0,1" bitfld.long 0x4C0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4C0 4. "CNT_RESET,-" "0,1" bitfld.long 0x4C0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4C0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4C0 0. "WAIT_SET,-" "0,1" line.long 0x4C4 "IMNTRCR305,INTC-Monitor Control Register 305" hexmask.long.word 0x4C4 16.--31. 1. "KEYCODE,-" bitfld.long 0x4C4 7. "NUM1_EN,-" "0,1" bitfld.long 0x4C4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4C4 4. "CNT_RESET,-" "0,1" bitfld.long 0x4C4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4C4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4C4 0. "WAIT_SET,-" "0,1" line.long 0x4C8 "IMNTRCR306,INTC-Monitor Control Register 306" hexmask.long.word 0x4C8 16.--31. 1. "KEYCODE,-" bitfld.long 0x4C8 7. "NUM1_EN,-" "0,1" bitfld.long 0x4C8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4C8 4. "CNT_RESET,-" "0,1" bitfld.long 0x4C8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4C8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4C8 0. "WAIT_SET,-" "0,1" line.long 0x4CC "IMNTRCR307,INTC-Monitor Control Register 307" hexmask.long.word 0x4CC 16.--31. 1. "KEYCODE,-" bitfld.long 0x4CC 7. "NUM1_EN,-" "0,1" bitfld.long 0x4CC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4CC 4. "CNT_RESET,-" "0,1" bitfld.long 0x4CC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4CC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4CC 0. "WAIT_SET,-" "0,1" line.long 0x4D0 "IMNTRCR308,INTC-Monitor Control Register 308" hexmask.long.word 0x4D0 16.--31. 1. "KEYCODE,-" bitfld.long 0x4D0 7. "NUM1_EN,-" "0,1" bitfld.long 0x4D0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4D0 4. "CNT_RESET,-" "0,1" bitfld.long 0x4D0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4D0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4D0 0. "WAIT_SET,-" "0,1" line.long 0x4D4 "IMNTRCR309,INTC-Monitor Control Register 309" hexmask.long.word 0x4D4 16.--31. 1. "KEYCODE,-" bitfld.long 0x4D4 7. "NUM1_EN,-" "0,1" bitfld.long 0x4D4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4D4 4. "CNT_RESET,-" "0,1" bitfld.long 0x4D4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4D4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4D4 0. "WAIT_SET,-" "0,1" line.long 0x4D8 "IMNTRCR310,INTC-Monitor Control Register 310" hexmask.long.word 0x4D8 16.--31. 1. "KEYCODE,-" bitfld.long 0x4D8 7. "NUM1_EN,-" "0,1" bitfld.long 0x4D8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4D8 4. "CNT_RESET,-" "0,1" bitfld.long 0x4D8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4D8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4D8 0. "WAIT_SET,-" "0,1" line.long 0x4DC "IMNTRCR311,INTC-Monitor Control Register 311" hexmask.long.word 0x4DC 16.--31. 1. "KEYCODE,-" bitfld.long 0x4DC 7. "NUM1_EN,-" "0,1" bitfld.long 0x4DC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4DC 4. "CNT_RESET,-" "0,1" bitfld.long 0x4DC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4DC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4DC 0. "WAIT_SET,-" "0,1" line.long 0x4E0 "IMNTRCR312,INTC-Monitor Control Register 312" hexmask.long.word 0x4E0 16.--31. 1. "KEYCODE,-" bitfld.long 0x4E0 7. "NUM1_EN,-" "0,1" bitfld.long 0x4E0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4E0 4. "CNT_RESET,-" "0,1" bitfld.long 0x4E0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4E0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4E0 0. "WAIT_SET,-" "0,1" line.long 0x4E4 "IMNTRCR313,INTC-Monitor Control Register 313" hexmask.long.word 0x4E4 16.--31. 1. "KEYCODE,-" bitfld.long 0x4E4 7. "NUM1_EN,-" "0,1" bitfld.long 0x4E4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4E4 4. "CNT_RESET,-" "0,1" bitfld.long 0x4E4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4E4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4E4 0. "WAIT_SET,-" "0,1" line.long 0x4E8 "IMNTRCR314,INTC-Monitor Control Register 314" hexmask.long.word 0x4E8 16.--31. 1. "KEYCODE,-" bitfld.long 0x4E8 7. "NUM1_EN,-" "0,1" bitfld.long 0x4E8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4E8 4. "CNT_RESET,-" "0,1" bitfld.long 0x4E8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4E8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4E8 0. "WAIT_SET,-" "0,1" line.long 0x4EC "IMNTRCR315,INTC-Monitor Control Register 315" hexmask.long.word 0x4EC 16.--31. 1. "KEYCODE,-" bitfld.long 0x4EC 7. "NUM1_EN,-" "0,1" bitfld.long 0x4EC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4EC 4. "CNT_RESET,-" "0,1" bitfld.long 0x4EC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4EC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4EC 0. "WAIT_SET,-" "0,1" line.long 0x4F0 "IMNTRCR316,INTC-Monitor Control Register 316" hexmask.long.word 0x4F0 16.--31. 1. "KEYCODE,-" bitfld.long 0x4F0 7. "NUM1_EN,-" "0,1" bitfld.long 0x4F0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4F0 4. "CNT_RESET,-" "0,1" bitfld.long 0x4F0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4F0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4F0 0. "WAIT_SET,-" "0,1" line.long 0x4F4 "IMNTRCR317,INTC-Monitor Control Register 317" hexmask.long.word 0x4F4 16.--31. 1. "KEYCODE,-" bitfld.long 0x4F4 7. "NUM1_EN,-" "0,1" bitfld.long 0x4F4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4F4 4. "CNT_RESET,-" "0,1" bitfld.long 0x4F4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4F4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4F4 0. "WAIT_SET,-" "0,1" line.long 0x4F8 "IMNTRCR318,INTC-Monitor Control Register 318" hexmask.long.word 0x4F8 16.--31. 1. "KEYCODE,-" bitfld.long 0x4F8 7. "NUM1_EN,-" "0,1" bitfld.long 0x4F8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4F8 4. "CNT_RESET,-" "0,1" bitfld.long 0x4F8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4F8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4F8 0. "WAIT_SET,-" "0,1" line.long 0x4FC "IMNTRCR319,INTC-Monitor Control Register 319" hexmask.long.word 0x4FC 16.--31. 1. "KEYCODE,-" bitfld.long 0x4FC 7. "NUM1_EN,-" "0,1" bitfld.long 0x4FC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x4FC 4. "CNT_RESET,-" "0,1" bitfld.long 0x4FC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x4FC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x4FC 0. "WAIT_SET,-" "0,1" line.long 0x500 "IMNTRCR320,INTC-Monitor Control Register 320" hexmask.long.word 0x500 16.--31. 1. "KEYCODE,-" bitfld.long 0x500 7. "NUM1_EN,-" "0,1" bitfld.long 0x500 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x500 4. "CNT_RESET,-" "0,1" bitfld.long 0x500 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x500 1. "IMNTR_EN,-" "0,1" bitfld.long 0x500 0. "WAIT_SET,-" "0,1" line.long 0x504 "IMNTRCR321,INTC-Monitor Control Register 321" hexmask.long.word 0x504 16.--31. 1. "KEYCODE,-" bitfld.long 0x504 7. "NUM1_EN,-" "0,1" bitfld.long 0x504 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x504 4. "CNT_RESET,-" "0,1" bitfld.long 0x504 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x504 1. "IMNTR_EN,-" "0,1" bitfld.long 0x504 0. "WAIT_SET,-" "0,1" line.long 0x508 "IMNTRCR322,INTC-Monitor Control Register 322" hexmask.long.word 0x508 16.--31. 1. "KEYCODE,-" bitfld.long 0x508 7. "NUM1_EN,-" "0,1" bitfld.long 0x508 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x508 4. "CNT_RESET,-" "0,1" bitfld.long 0x508 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x508 1. "IMNTR_EN,-" "0,1" bitfld.long 0x508 0. "WAIT_SET,-" "0,1" line.long 0x50C "IMNTRCR323,INTC-Monitor Control Register 323" hexmask.long.word 0x50C 16.--31. 1. "KEYCODE,-" bitfld.long 0x50C 7. "NUM1_EN,-" "0,1" bitfld.long 0x50C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x50C 4. "CNT_RESET,-" "0,1" bitfld.long 0x50C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x50C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x50C 0. "WAIT_SET,-" "0,1" line.long 0x510 "IMNTRCR324,INTC-Monitor Control Register 324" hexmask.long.word 0x510 16.--31. 1. "KEYCODE,-" bitfld.long 0x510 7. "NUM1_EN,-" "0,1" bitfld.long 0x510 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x510 4. "CNT_RESET,-" "0,1" bitfld.long 0x510 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x510 1. "IMNTR_EN,-" "0,1" bitfld.long 0x510 0. "WAIT_SET,-" "0,1" line.long 0x514 "IMNTRCR325,INTC-Monitor Control Register 325" hexmask.long.word 0x514 16.--31. 1. "KEYCODE,-" bitfld.long 0x514 7. "NUM1_EN,-" "0,1" bitfld.long 0x514 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x514 4. "CNT_RESET,-" "0,1" bitfld.long 0x514 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x514 1. "IMNTR_EN,-" "0,1" bitfld.long 0x514 0. "WAIT_SET,-" "0,1" line.long 0x518 "IMNTRCR326,INTC-Monitor Control Register 326" hexmask.long.word 0x518 16.--31. 1. "KEYCODE,-" bitfld.long 0x518 7. "NUM1_EN,-" "0,1" bitfld.long 0x518 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x518 4. "CNT_RESET,-" "0,1" bitfld.long 0x518 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x518 1. "IMNTR_EN,-" "0,1" bitfld.long 0x518 0. "WAIT_SET,-" "0,1" line.long 0x51C "IMNTRCR327,INTC-Monitor Control Register 327" hexmask.long.word 0x51C 16.--31. 1. "KEYCODE,-" bitfld.long 0x51C 7. "NUM1_EN,-" "0,1" bitfld.long 0x51C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x51C 4. "CNT_RESET,-" "0,1" bitfld.long 0x51C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x51C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x51C 0. "WAIT_SET,-" "0,1" line.long 0x520 "IMNTRCR328,INTC-Monitor Control Register 328" hexmask.long.word 0x520 16.--31. 1. "KEYCODE,-" bitfld.long 0x520 7. "NUM1_EN,-" "0,1" bitfld.long 0x520 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x520 4. "CNT_RESET,-" "0,1" bitfld.long 0x520 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x520 1. "IMNTR_EN,-" "0,1" bitfld.long 0x520 0. "WAIT_SET,-" "0,1" line.long 0x524 "IMNTRCR329,INTC-Monitor Control Register 329" hexmask.long.word 0x524 16.--31. 1. "KEYCODE,-" bitfld.long 0x524 7. "NUM1_EN,-" "0,1" bitfld.long 0x524 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x524 4. "CNT_RESET,-" "0,1" bitfld.long 0x524 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x524 1. "IMNTR_EN,-" "0,1" bitfld.long 0x524 0. "WAIT_SET,-" "0,1" line.long 0x528 "IMNTRCR330,INTC-Monitor Control Register 330" hexmask.long.word 0x528 16.--31. 1. "KEYCODE,-" bitfld.long 0x528 7. "NUM1_EN,-" "0,1" bitfld.long 0x528 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x528 4. "CNT_RESET,-" "0,1" bitfld.long 0x528 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x528 1. "IMNTR_EN,-" "0,1" bitfld.long 0x528 0. "WAIT_SET,-" "0,1" line.long 0x52C "IMNTRCR331,INTC-Monitor Control Register 331" hexmask.long.word 0x52C 16.--31. 1. "KEYCODE,-" bitfld.long 0x52C 7. "NUM1_EN,-" "0,1" bitfld.long 0x52C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x52C 4. "CNT_RESET,-" "0,1" bitfld.long 0x52C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x52C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x52C 0. "WAIT_SET,-" "0,1" line.long 0x530 "IMNTRCR332,INTC-Monitor Control Register 332" hexmask.long.word 0x530 16.--31. 1. "KEYCODE,-" bitfld.long 0x530 7. "NUM1_EN,-" "0,1" bitfld.long 0x530 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x530 4. "CNT_RESET,-" "0,1" bitfld.long 0x530 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x530 1. "IMNTR_EN,-" "0,1" bitfld.long 0x530 0. "WAIT_SET,-" "0,1" line.long 0x534 "IMNTRCR333,INTC-Monitor Control Register 333" hexmask.long.word 0x534 16.--31. 1. "KEYCODE,-" bitfld.long 0x534 7. "NUM1_EN,-" "0,1" bitfld.long 0x534 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x534 4. "CNT_RESET,-" "0,1" bitfld.long 0x534 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x534 1. "IMNTR_EN,-" "0,1" bitfld.long 0x534 0. "WAIT_SET,-" "0,1" line.long 0x538 "IMNTRCR334,INTC-Monitor Control Register 334" hexmask.long.word 0x538 16.--31. 1. "KEYCODE,-" bitfld.long 0x538 7. "NUM1_EN,-" "0,1" bitfld.long 0x538 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x538 4. "CNT_RESET,-" "0,1" bitfld.long 0x538 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x538 1. "IMNTR_EN,-" "0,1" bitfld.long 0x538 0. "WAIT_SET,-" "0,1" line.long 0x53C "IMNTRCR335,INTC-Monitor Control Register 335" hexmask.long.word 0x53C 16.--31. 1. "KEYCODE,-" bitfld.long 0x53C 7. "NUM1_EN,-" "0,1" bitfld.long 0x53C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x53C 4. "CNT_RESET,-" "0,1" bitfld.long 0x53C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x53C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x53C 0. "WAIT_SET,-" "0,1" line.long 0x540 "IMNTRCR336,INTC-Monitor Control Register 336" hexmask.long.word 0x540 16.--31. 1. "KEYCODE,-" bitfld.long 0x540 7. "NUM1_EN,-" "0,1" bitfld.long 0x540 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x540 4. "CNT_RESET,-" "0,1" bitfld.long 0x540 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x540 1. "IMNTR_EN,-" "0,1" bitfld.long 0x540 0. "WAIT_SET,-" "0,1" line.long 0x544 "IMNTRCR337,INTC-Monitor Control Register 337" hexmask.long.word 0x544 16.--31. 1. "KEYCODE,-" bitfld.long 0x544 7. "NUM1_EN,-" "0,1" bitfld.long 0x544 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x544 4. "CNT_RESET,-" "0,1" bitfld.long 0x544 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x544 1. "IMNTR_EN,-" "0,1" bitfld.long 0x544 0. "WAIT_SET,-" "0,1" line.long 0x548 "IMNTRCR338,INTC-Monitor Control Register 338" hexmask.long.word 0x548 16.--31. 1. "KEYCODE,-" bitfld.long 0x548 7. "NUM1_EN,-" "0,1" bitfld.long 0x548 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x548 4. "CNT_RESET,-" "0,1" bitfld.long 0x548 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x548 1. "IMNTR_EN,-" "0,1" bitfld.long 0x548 0. "WAIT_SET,-" "0,1" line.long 0x54C "IMNTRCR339,INTC-Monitor Control Register 339" hexmask.long.word 0x54C 16.--31. 1. "KEYCODE,-" bitfld.long 0x54C 7. "NUM1_EN,-" "0,1" bitfld.long 0x54C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x54C 4. "CNT_RESET,-" "0,1" bitfld.long 0x54C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x54C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x54C 0. "WAIT_SET,-" "0,1" line.long 0x550 "IMNTRCR340,INTC-Monitor Control Register 340" hexmask.long.word 0x550 16.--31. 1. "KEYCODE,-" bitfld.long 0x550 7. "NUM1_EN,-" "0,1" bitfld.long 0x550 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x550 4. "CNT_RESET,-" "0,1" bitfld.long 0x550 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x550 1. "IMNTR_EN,-" "0,1" bitfld.long 0x550 0. "WAIT_SET,-" "0,1" line.long 0x554 "IMNTRCR341,INTC-Monitor Control Register 341" hexmask.long.word 0x554 16.--31. 1. "KEYCODE,-" bitfld.long 0x554 7. "NUM1_EN,-" "0,1" bitfld.long 0x554 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x554 4. "CNT_RESET,-" "0,1" bitfld.long 0x554 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x554 1. "IMNTR_EN,-" "0,1" bitfld.long 0x554 0. "WAIT_SET,-" "0,1" line.long 0x558 "IMNTRCR342,INTC-Monitor Control Register 342" hexmask.long.word 0x558 16.--31. 1. "KEYCODE,-" bitfld.long 0x558 7. "NUM1_EN,-" "0,1" bitfld.long 0x558 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x558 4. "CNT_RESET,-" "0,1" bitfld.long 0x558 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x558 1. "IMNTR_EN,-" "0,1" bitfld.long 0x558 0. "WAIT_SET,-" "0,1" line.long 0x55C "IMNTRCR343,INTC-Monitor Control Register 343" hexmask.long.word 0x55C 16.--31. 1. "KEYCODE,-" bitfld.long 0x55C 7. "NUM1_EN,-" "0,1" bitfld.long 0x55C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x55C 4. "CNT_RESET,-" "0,1" bitfld.long 0x55C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x55C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x55C 0. "WAIT_SET,-" "0,1" line.long 0x560 "IMNTRCR344,INTC-Monitor Control Register 344" hexmask.long.word 0x560 16.--31. 1. "KEYCODE,-" bitfld.long 0x560 7. "NUM1_EN,-" "0,1" bitfld.long 0x560 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x560 4. "CNT_RESET,-" "0,1" bitfld.long 0x560 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x560 1. "IMNTR_EN,-" "0,1" bitfld.long 0x560 0. "WAIT_SET,-" "0,1" line.long 0x564 "IMNTRCR345,INTC-Monitor Control Register 345" hexmask.long.word 0x564 16.--31. 1. "KEYCODE,-" bitfld.long 0x564 7. "NUM1_EN,-" "0,1" bitfld.long 0x564 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x564 4. "CNT_RESET,-" "0,1" bitfld.long 0x564 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x564 1. "IMNTR_EN,-" "0,1" bitfld.long 0x564 0. "WAIT_SET,-" "0,1" line.long 0x568 "IMNTRCR346,INTC-Monitor Control Register 346" hexmask.long.word 0x568 16.--31. 1. "KEYCODE,-" bitfld.long 0x568 7. "NUM1_EN,-" "0,1" bitfld.long 0x568 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x568 4. "CNT_RESET,-" "0,1" bitfld.long 0x568 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x568 1. "IMNTR_EN,-" "0,1" bitfld.long 0x568 0. "WAIT_SET,-" "0,1" line.long 0x56C "IMNTRCR347,INTC-Monitor Control Register 347" hexmask.long.word 0x56C 16.--31. 1. "KEYCODE,-" bitfld.long 0x56C 7. "NUM1_EN,-" "0,1" bitfld.long 0x56C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x56C 4. "CNT_RESET,-" "0,1" bitfld.long 0x56C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x56C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x56C 0. "WAIT_SET,-" "0,1" line.long 0x570 "IMNTRCR348,INTC-Monitor Control Register 348" hexmask.long.word 0x570 16.--31. 1. "KEYCODE,-" bitfld.long 0x570 7. "NUM1_EN,-" "0,1" bitfld.long 0x570 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x570 4. "CNT_RESET,-" "0,1" bitfld.long 0x570 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x570 1. "IMNTR_EN,-" "0,1" bitfld.long 0x570 0. "WAIT_SET,-" "0,1" line.long 0x574 "IMNTRCR349,INTC-Monitor Control Register 349" hexmask.long.word 0x574 16.--31. 1. "KEYCODE,-" bitfld.long 0x574 7. "NUM1_EN,-" "0,1" bitfld.long 0x574 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x574 4. "CNT_RESET,-" "0,1" bitfld.long 0x574 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x574 1. "IMNTR_EN,-" "0,1" bitfld.long 0x574 0. "WAIT_SET,-" "0,1" line.long 0x578 "IMNTRCR350,INTC-Monitor Control Register 350" hexmask.long.word 0x578 16.--31. 1. "KEYCODE,-" bitfld.long 0x578 7. "NUM1_EN,-" "0,1" bitfld.long 0x578 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x578 4. "CNT_RESET,-" "0,1" bitfld.long 0x578 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x578 1. "IMNTR_EN,-" "0,1" bitfld.long 0x578 0. "WAIT_SET,-" "0,1" line.long 0x57C "IMNTRCR351,INTC-Monitor Control Register 351" hexmask.long.word 0x57C 16.--31. 1. "KEYCODE,-" bitfld.long 0x57C 7. "NUM1_EN,-" "0,1" bitfld.long 0x57C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x57C 4. "CNT_RESET,-" "0,1" bitfld.long 0x57C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x57C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x57C 0. "WAIT_SET,-" "0,1" line.long 0x580 "IMNTRCR352,INTC-Monitor Control Register 352" hexmask.long.word 0x580 16.--31. 1. "KEYCODE,-" bitfld.long 0x580 7. "NUM1_EN,-" "0,1" bitfld.long 0x580 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x580 4. "CNT_RESET,-" "0,1" bitfld.long 0x580 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x580 1. "IMNTR_EN,-" "0,1" bitfld.long 0x580 0. "WAIT_SET,-" "0,1" line.long 0x584 "IMNTRCR353,INTC-Monitor Control Register 353" hexmask.long.word 0x584 16.--31. 1. "KEYCODE,-" bitfld.long 0x584 7. "NUM1_EN,-" "0,1" bitfld.long 0x584 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x584 4. "CNT_RESET,-" "0,1" bitfld.long 0x584 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x584 1. "IMNTR_EN,-" "0,1" bitfld.long 0x584 0. "WAIT_SET,-" "0,1" line.long 0x588 "IMNTRCR354,INTC-Monitor Control Register 354" hexmask.long.word 0x588 16.--31. 1. "KEYCODE,-" bitfld.long 0x588 7. "NUM1_EN,-" "0,1" bitfld.long 0x588 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x588 4. "CNT_RESET,-" "0,1" bitfld.long 0x588 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x588 1. "IMNTR_EN,-" "0,1" bitfld.long 0x588 0. "WAIT_SET,-" "0,1" line.long 0x58C "IMNTRCR355,INTC-Monitor Control Register 355" hexmask.long.word 0x58C 16.--31. 1. "KEYCODE,-" bitfld.long 0x58C 7. "NUM1_EN,-" "0,1" bitfld.long 0x58C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x58C 4. "CNT_RESET,-" "0,1" bitfld.long 0x58C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x58C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x58C 0. "WAIT_SET,-" "0,1" line.long 0x590 "IMNTRCR356,INTC-Monitor Control Register 356" hexmask.long.word 0x590 16.--31. 1. "KEYCODE,-" bitfld.long 0x590 7. "NUM1_EN,-" "0,1" bitfld.long 0x590 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x590 4. "CNT_RESET,-" "0,1" bitfld.long 0x590 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x590 1. "IMNTR_EN,-" "0,1" bitfld.long 0x590 0. "WAIT_SET,-" "0,1" line.long 0x594 "IMNTRCR357,INTC-Monitor Control Register 357" hexmask.long.word 0x594 16.--31. 1. "KEYCODE,-" bitfld.long 0x594 7. "NUM1_EN,-" "0,1" bitfld.long 0x594 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x594 4. "CNT_RESET,-" "0,1" bitfld.long 0x594 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x594 1. "IMNTR_EN,-" "0,1" bitfld.long 0x594 0. "WAIT_SET,-" "0,1" line.long 0x598 "IMNTRCR358,INTC-Monitor Control Register 358" hexmask.long.word 0x598 16.--31. 1. "KEYCODE,-" bitfld.long 0x598 7. "NUM1_EN,-" "0,1" bitfld.long 0x598 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x598 4. "CNT_RESET,-" "0,1" bitfld.long 0x598 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x598 1. "IMNTR_EN,-" "0,1" bitfld.long 0x598 0. "WAIT_SET,-" "0,1" line.long 0x59C "IMNTRCR359,INTC-Monitor Control Register 359" hexmask.long.word 0x59C 16.--31. 1. "KEYCODE,-" bitfld.long 0x59C 7. "NUM1_EN,-" "0,1" bitfld.long 0x59C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x59C 4. "CNT_RESET,-" "0,1" bitfld.long 0x59C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x59C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x59C 0. "WAIT_SET,-" "0,1" line.long 0x5A0 "IMNTRCR360,INTC-Monitor Control Register 360" hexmask.long.word 0x5A0 16.--31. 1. "KEYCODE,-" bitfld.long 0x5A0 7. "NUM1_EN,-" "0,1" bitfld.long 0x5A0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5A0 4. "CNT_RESET,-" "0,1" bitfld.long 0x5A0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5A0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5A0 0. "WAIT_SET,-" "0,1" line.long 0x5A4 "IMNTRCR361,INTC-Monitor Control Register 361" hexmask.long.word 0x5A4 16.--31. 1. "KEYCODE,-" bitfld.long 0x5A4 7. "NUM1_EN,-" "0,1" bitfld.long 0x5A4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5A4 4. "CNT_RESET,-" "0,1" bitfld.long 0x5A4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5A4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5A4 0. "WAIT_SET,-" "0,1" line.long 0x5A8 "IMNTRCR362,INTC-Monitor Control Register 362" hexmask.long.word 0x5A8 16.--31. 1. "KEYCODE,-" bitfld.long 0x5A8 7. "NUM1_EN,-" "0,1" bitfld.long 0x5A8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5A8 4. "CNT_RESET,-" "0,1" bitfld.long 0x5A8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5A8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5A8 0. "WAIT_SET,-" "0,1" line.long 0x5AC "IMNTRCR363,INTC-Monitor Control Register 363" hexmask.long.word 0x5AC 16.--31. 1. "KEYCODE,-" bitfld.long 0x5AC 7. "NUM1_EN,-" "0,1" bitfld.long 0x5AC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5AC 4. "CNT_RESET,-" "0,1" bitfld.long 0x5AC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5AC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5AC 0. "WAIT_SET,-" "0,1" line.long 0x5B0 "IMNTRCR364,INTC-Monitor Control Register 364" hexmask.long.word 0x5B0 16.--31. 1. "KEYCODE,-" bitfld.long 0x5B0 7. "NUM1_EN,-" "0,1" bitfld.long 0x5B0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5B0 4. "CNT_RESET,-" "0,1" bitfld.long 0x5B0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5B0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5B0 0. "WAIT_SET,-" "0,1" line.long 0x5B4 "IMNTRCR365,INTC-Monitor Control Register 365" hexmask.long.word 0x5B4 16.--31. 1. "KEYCODE,-" bitfld.long 0x5B4 7. "NUM1_EN,-" "0,1" bitfld.long 0x5B4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5B4 4. "CNT_RESET,-" "0,1" bitfld.long 0x5B4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5B4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5B4 0. "WAIT_SET,-" "0,1" line.long 0x5B8 "IMNTRCR366,INTC-Monitor Control Register 366" hexmask.long.word 0x5B8 16.--31. 1. "KEYCODE,-" bitfld.long 0x5B8 7. "NUM1_EN,-" "0,1" bitfld.long 0x5B8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5B8 4. "CNT_RESET,-" "0,1" bitfld.long 0x5B8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5B8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5B8 0. "WAIT_SET,-" "0,1" line.long 0x5BC "IMNTRCR367,INTC-Monitor Control Register 367" hexmask.long.word 0x5BC 16.--31. 1. "KEYCODE,-" bitfld.long 0x5BC 7. "NUM1_EN,-" "0,1" bitfld.long 0x5BC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5BC 4. "CNT_RESET,-" "0,1" bitfld.long 0x5BC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5BC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5BC 0. "WAIT_SET,-" "0,1" line.long 0x5C0 "IMNTRCR368,INTC-Monitor Control Register 368" hexmask.long.word 0x5C0 16.--31. 1. "KEYCODE,-" bitfld.long 0x5C0 7. "NUM1_EN,-" "0,1" bitfld.long 0x5C0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5C0 4. "CNT_RESET,-" "0,1" bitfld.long 0x5C0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5C0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5C0 0. "WAIT_SET,-" "0,1" line.long 0x5C4 "IMNTRCR369,INTC-Monitor Control Register 369" hexmask.long.word 0x5C4 16.--31. 1. "KEYCODE,-" bitfld.long 0x5C4 7. "NUM1_EN,-" "0,1" bitfld.long 0x5C4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5C4 4. "CNT_RESET,-" "0,1" bitfld.long 0x5C4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5C4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5C4 0. "WAIT_SET,-" "0,1" line.long 0x5C8 "IMNTRCR370,INTC-Monitor Control Register 370" hexmask.long.word 0x5C8 16.--31. 1. "KEYCODE,-" bitfld.long 0x5C8 7. "NUM1_EN,-" "0,1" bitfld.long 0x5C8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5C8 4. "CNT_RESET,-" "0,1" bitfld.long 0x5C8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5C8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5C8 0. "WAIT_SET,-" "0,1" line.long 0x5CC "IMNTRCR371,INTC-Monitor Control Register 371" hexmask.long.word 0x5CC 16.--31. 1. "KEYCODE,-" bitfld.long 0x5CC 7. "NUM1_EN,-" "0,1" bitfld.long 0x5CC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5CC 4. "CNT_RESET,-" "0,1" bitfld.long 0x5CC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5CC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5CC 0. "WAIT_SET,-" "0,1" line.long 0x5D0 "IMNTRCR372,INTC-Monitor Control Register 372" hexmask.long.word 0x5D0 16.--31. 1. "KEYCODE,-" bitfld.long 0x5D0 7. "NUM1_EN,-" "0,1" bitfld.long 0x5D0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5D0 4. "CNT_RESET,-" "0,1" bitfld.long 0x5D0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5D0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5D0 0. "WAIT_SET,-" "0,1" line.long 0x5D4 "IMNTRCR373,INTC-Monitor Control Register 373" hexmask.long.word 0x5D4 16.--31. 1. "KEYCODE,-" bitfld.long 0x5D4 7. "NUM1_EN,-" "0,1" bitfld.long 0x5D4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5D4 4. "CNT_RESET,-" "0,1" bitfld.long 0x5D4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5D4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5D4 0. "WAIT_SET,-" "0,1" line.long 0x5D8 "IMNTRCR374,INTC-Monitor Control Register 374" hexmask.long.word 0x5D8 16.--31. 1. "KEYCODE,-" bitfld.long 0x5D8 7. "NUM1_EN,-" "0,1" bitfld.long 0x5D8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5D8 4. "CNT_RESET,-" "0,1" bitfld.long 0x5D8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5D8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5D8 0. "WAIT_SET,-" "0,1" line.long 0x5DC "IMNTRCR375,INTC-Monitor Control Register 375" hexmask.long.word 0x5DC 16.--31. 1. "KEYCODE,-" bitfld.long 0x5DC 7. "NUM1_EN,-" "0,1" bitfld.long 0x5DC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5DC 4. "CNT_RESET,-" "0,1" bitfld.long 0x5DC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5DC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5DC 0. "WAIT_SET,-" "0,1" line.long 0x5E0 "IMNTRCR376,INTC-Monitor Control Register 376" hexmask.long.word 0x5E0 16.--31. 1. "KEYCODE,-" bitfld.long 0x5E0 7. "NUM1_EN,-" "0,1" bitfld.long 0x5E0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5E0 4. "CNT_RESET,-" "0,1" bitfld.long 0x5E0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5E0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5E0 0. "WAIT_SET,-" "0,1" line.long 0x5E4 "IMNTRCR377,INTC-Monitor Control Register 377" hexmask.long.word 0x5E4 16.--31. 1. "KEYCODE,-" bitfld.long 0x5E4 7. "NUM1_EN,-" "0,1" bitfld.long 0x5E4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5E4 4. "CNT_RESET,-" "0,1" bitfld.long 0x5E4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5E4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5E4 0. "WAIT_SET,-" "0,1" line.long 0x5E8 "IMNTRCR378,INTC-Monitor Control Register 378" hexmask.long.word 0x5E8 16.--31. 1. "KEYCODE,-" bitfld.long 0x5E8 7. "NUM1_EN,-" "0,1" bitfld.long 0x5E8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5E8 4. "CNT_RESET,-" "0,1" bitfld.long 0x5E8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5E8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5E8 0. "WAIT_SET,-" "0,1" line.long 0x5EC "IMNTRCR379,INTC-Monitor Control Register 379" hexmask.long.word 0x5EC 16.--31. 1. "KEYCODE,-" bitfld.long 0x5EC 7. "NUM1_EN,-" "0,1" bitfld.long 0x5EC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5EC 4. "CNT_RESET,-" "0,1" bitfld.long 0x5EC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5EC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5EC 0. "WAIT_SET,-" "0,1" line.long 0x5F0 "IMNTRCR380,INTC-Monitor Control Register 380" hexmask.long.word 0x5F0 16.--31. 1. "KEYCODE,-" bitfld.long 0x5F0 7. "NUM1_EN,-" "0,1" bitfld.long 0x5F0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5F0 4. "CNT_RESET,-" "0,1" bitfld.long 0x5F0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5F0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5F0 0. "WAIT_SET,-" "0,1" line.long 0x5F4 "IMNTRCR381,INTC-Monitor Control Register 381" hexmask.long.word 0x5F4 16.--31. 1. "KEYCODE,-" bitfld.long 0x5F4 7. "NUM1_EN,-" "0,1" bitfld.long 0x5F4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5F4 4. "CNT_RESET,-" "0,1" bitfld.long 0x5F4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5F4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5F4 0. "WAIT_SET,-" "0,1" line.long 0x5F8 "IMNTRCR382,INTC-Monitor Control Register 382" hexmask.long.word 0x5F8 16.--31. 1. "KEYCODE,-" bitfld.long 0x5F8 7. "NUM1_EN,-" "0,1" bitfld.long 0x5F8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5F8 4. "CNT_RESET,-" "0,1" bitfld.long 0x5F8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5F8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5F8 0. "WAIT_SET,-" "0,1" line.long 0x5FC "IMNTRCR383,INTC-Monitor Control Register 383" hexmask.long.word 0x5FC 16.--31. 1. "KEYCODE,-" bitfld.long 0x5FC 7. "NUM1_EN,-" "0,1" bitfld.long 0x5FC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x5FC 4. "CNT_RESET,-" "0,1" bitfld.long 0x5FC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x5FC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x5FC 0. "WAIT_SET,-" "0,1" line.long 0x600 "IMNTRCR384,INTC-Monitor Control Register 384" hexmask.long.word 0x600 16.--31. 1. "KEYCODE,-" bitfld.long 0x600 7. "NUM1_EN,-" "0,1" bitfld.long 0x600 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x600 4. "CNT_RESET,-" "0,1" bitfld.long 0x600 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x600 1. "IMNTR_EN,-" "0,1" bitfld.long 0x600 0. "WAIT_SET,-" "0,1" line.long 0x604 "IMNTRCR385,INTC-Monitor Control Register 385" hexmask.long.word 0x604 16.--31. 1. "KEYCODE,-" bitfld.long 0x604 7. "NUM1_EN,-" "0,1" bitfld.long 0x604 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x604 4. "CNT_RESET,-" "0,1" bitfld.long 0x604 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x604 1. "IMNTR_EN,-" "0,1" bitfld.long 0x604 0. "WAIT_SET,-" "0,1" line.long 0x608 "IMNTRCR386,INTC-Monitor Control Register 386" hexmask.long.word 0x608 16.--31. 1. "KEYCODE,-" bitfld.long 0x608 7. "NUM1_EN,-" "0,1" bitfld.long 0x608 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x608 4. "CNT_RESET,-" "0,1" bitfld.long 0x608 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x608 1. "IMNTR_EN,-" "0,1" bitfld.long 0x608 0. "WAIT_SET,-" "0,1" line.long 0x60C "IMNTRCR387,INTC-Monitor Control Register 387" hexmask.long.word 0x60C 16.--31. 1. "KEYCODE,-" bitfld.long 0x60C 7. "NUM1_EN,-" "0,1" bitfld.long 0x60C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x60C 4. "CNT_RESET,-" "0,1" bitfld.long 0x60C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x60C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x60C 0. "WAIT_SET,-" "0,1" line.long 0x610 "IMNTRCR388,INTC-Monitor Control Register 388" hexmask.long.word 0x610 16.--31. 1. "KEYCODE,-" bitfld.long 0x610 7. "NUM1_EN,-" "0,1" bitfld.long 0x610 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x610 4. "CNT_RESET,-" "0,1" bitfld.long 0x610 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x610 1. "IMNTR_EN,-" "0,1" bitfld.long 0x610 0. "WAIT_SET,-" "0,1" line.long 0x614 "IMNTRCR389,INTC-Monitor Control Register 389" hexmask.long.word 0x614 16.--31. 1. "KEYCODE,-" bitfld.long 0x614 7. "NUM1_EN,-" "0,1" bitfld.long 0x614 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x614 4. "CNT_RESET,-" "0,1" bitfld.long 0x614 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x614 1. "IMNTR_EN,-" "0,1" bitfld.long 0x614 0. "WAIT_SET,-" "0,1" line.long 0x618 "IMNTRCR390,INTC-Monitor Control Register 390" hexmask.long.word 0x618 16.--31. 1. "KEYCODE,-" bitfld.long 0x618 7. "NUM1_EN,-" "0,1" bitfld.long 0x618 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x618 4. "CNT_RESET,-" "0,1" bitfld.long 0x618 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x618 1. "IMNTR_EN,-" "0,1" bitfld.long 0x618 0. "WAIT_SET,-" "0,1" line.long 0x61C "IMNTRCR391,INTC-Monitor Control Register 391" hexmask.long.word 0x61C 16.--31. 1. "KEYCODE,-" bitfld.long 0x61C 7. "NUM1_EN,-" "0,1" bitfld.long 0x61C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x61C 4. "CNT_RESET,-" "0,1" bitfld.long 0x61C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x61C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x61C 0. "WAIT_SET,-" "0,1" line.long 0x620 "IMNTRCR392,INTC-Monitor Control Register 392" hexmask.long.word 0x620 16.--31. 1. "KEYCODE,-" bitfld.long 0x620 7. "NUM1_EN,-" "0,1" bitfld.long 0x620 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x620 4. "CNT_RESET,-" "0,1" bitfld.long 0x620 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x620 1. "IMNTR_EN,-" "0,1" bitfld.long 0x620 0. "WAIT_SET,-" "0,1" line.long 0x624 "IMNTRCR393,INTC-Monitor Control Register 393" hexmask.long.word 0x624 16.--31. 1. "KEYCODE,-" bitfld.long 0x624 7. "NUM1_EN,-" "0,1" bitfld.long 0x624 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x624 4. "CNT_RESET,-" "0,1" bitfld.long 0x624 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x624 1. "IMNTR_EN,-" "0,1" bitfld.long 0x624 0. "WAIT_SET,-" "0,1" line.long 0x628 "IMNTRCR394,INTC-Monitor Control Register 394" hexmask.long.word 0x628 16.--31. 1. "KEYCODE,-" bitfld.long 0x628 7. "NUM1_EN,-" "0,1" bitfld.long 0x628 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x628 4. "CNT_RESET,-" "0,1" bitfld.long 0x628 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x628 1. "IMNTR_EN,-" "0,1" bitfld.long 0x628 0. "WAIT_SET,-" "0,1" line.long 0x62C "IMNTRCR395,INTC-Monitor Control Register 395" hexmask.long.word 0x62C 16.--31. 1. "KEYCODE,-" bitfld.long 0x62C 7. "NUM1_EN,-" "0,1" bitfld.long 0x62C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x62C 4. "CNT_RESET,-" "0,1" bitfld.long 0x62C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x62C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x62C 0. "WAIT_SET,-" "0,1" line.long 0x630 "IMNTRCR396,INTC-Monitor Control Register 396" hexmask.long.word 0x630 16.--31. 1. "KEYCODE,-" bitfld.long 0x630 7. "NUM1_EN,-" "0,1" bitfld.long 0x630 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x630 4. "CNT_RESET,-" "0,1" bitfld.long 0x630 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x630 1. "IMNTR_EN,-" "0,1" bitfld.long 0x630 0. "WAIT_SET,-" "0,1" line.long 0x634 "IMNTRCR397,INTC-Monitor Control Register 397" hexmask.long.word 0x634 16.--31. 1. "KEYCODE,-" bitfld.long 0x634 7. "NUM1_EN,-" "0,1" bitfld.long 0x634 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x634 4. "CNT_RESET,-" "0,1" bitfld.long 0x634 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x634 1. "IMNTR_EN,-" "0,1" bitfld.long 0x634 0. "WAIT_SET,-" "0,1" line.long 0x638 "IMNTRCR398,INTC-Monitor Control Register 398" hexmask.long.word 0x638 16.--31. 1. "KEYCODE,-" bitfld.long 0x638 7. "NUM1_EN,-" "0,1" bitfld.long 0x638 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x638 4. "CNT_RESET,-" "0,1" bitfld.long 0x638 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x638 1. "IMNTR_EN,-" "0,1" bitfld.long 0x638 0. "WAIT_SET,-" "0,1" line.long 0x63C "IMNTRCR399,INTC-Monitor Control Register 399" hexmask.long.word 0x63C 16.--31. 1. "KEYCODE,-" bitfld.long 0x63C 7. "NUM1_EN,-" "0,1" bitfld.long 0x63C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x63C 4. "CNT_RESET,-" "0,1" bitfld.long 0x63C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x63C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x63C 0. "WAIT_SET,-" "0,1" line.long 0x640 "IMNTRCR400,INTC-Monitor Control Register 400" hexmask.long.word 0x640 16.--31. 1. "KEYCODE,-" bitfld.long 0x640 7. "NUM1_EN,-" "0,1" bitfld.long 0x640 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x640 4. "CNT_RESET,-" "0,1" bitfld.long 0x640 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x640 1. "IMNTR_EN,-" "0,1" bitfld.long 0x640 0. "WAIT_SET,-" "0,1" line.long 0x644 "IMNTRCR401,INTC-Monitor Control Register 401" hexmask.long.word 0x644 16.--31. 1. "KEYCODE,-" bitfld.long 0x644 7. "NUM1_EN,-" "0,1" bitfld.long 0x644 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x644 4. "CNT_RESET,-" "0,1" bitfld.long 0x644 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x644 1. "IMNTR_EN,-" "0,1" bitfld.long 0x644 0. "WAIT_SET,-" "0,1" line.long 0x648 "IMNTRCR402,INTC-Monitor Control Register 402" hexmask.long.word 0x648 16.--31. 1. "KEYCODE,-" bitfld.long 0x648 7. "NUM1_EN,-" "0,1" bitfld.long 0x648 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x648 4. "CNT_RESET,-" "0,1" bitfld.long 0x648 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x648 1. "IMNTR_EN,-" "0,1" bitfld.long 0x648 0. "WAIT_SET,-" "0,1" line.long 0x64C "IMNTRCR403,INTC-Monitor Control Register 403" hexmask.long.word 0x64C 16.--31. 1. "KEYCODE,-" bitfld.long 0x64C 7. "NUM1_EN,-" "0,1" bitfld.long 0x64C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x64C 4. "CNT_RESET,-" "0,1" bitfld.long 0x64C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x64C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x64C 0. "WAIT_SET,-" "0,1" line.long 0x650 "IMNTRCR404,INTC-Monitor Control Register 404" hexmask.long.word 0x650 16.--31. 1. "KEYCODE,-" bitfld.long 0x650 7. "NUM1_EN,-" "0,1" bitfld.long 0x650 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x650 4. "CNT_RESET,-" "0,1" bitfld.long 0x650 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x650 1. "IMNTR_EN,-" "0,1" bitfld.long 0x650 0. "WAIT_SET,-" "0,1" line.long 0x654 "IMNTRCR405,INTC-Monitor Control Register 405" hexmask.long.word 0x654 16.--31. 1. "KEYCODE,-" bitfld.long 0x654 7. "NUM1_EN,-" "0,1" bitfld.long 0x654 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x654 4. "CNT_RESET,-" "0,1" bitfld.long 0x654 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x654 1. "IMNTR_EN,-" "0,1" bitfld.long 0x654 0. "WAIT_SET,-" "0,1" line.long 0x658 "IMNTRCR406,INTC-Monitor Control Register 406" hexmask.long.word 0x658 16.--31. 1. "KEYCODE,-" bitfld.long 0x658 7. "NUM1_EN,-" "0,1" bitfld.long 0x658 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x658 4. "CNT_RESET,-" "0,1" bitfld.long 0x658 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x658 1. "IMNTR_EN,-" "0,1" bitfld.long 0x658 0. "WAIT_SET,-" "0,1" line.long 0x65C "IMNTRCR407,INTC-Monitor Control Register 407" hexmask.long.word 0x65C 16.--31. 1. "KEYCODE,-" bitfld.long 0x65C 7. "NUM1_EN,-" "0,1" bitfld.long 0x65C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x65C 4. "CNT_RESET,-" "0,1" bitfld.long 0x65C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x65C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x65C 0. "WAIT_SET,-" "0,1" line.long 0x660 "IMNTRCR408,INTC-Monitor Control Register 408" hexmask.long.word 0x660 16.--31. 1. "KEYCODE,-" bitfld.long 0x660 7. "NUM1_EN,-" "0,1" bitfld.long 0x660 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x660 4. "CNT_RESET,-" "0,1" bitfld.long 0x660 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x660 1. "IMNTR_EN,-" "0,1" bitfld.long 0x660 0. "WAIT_SET,-" "0,1" line.long 0x664 "IMNTRCR409,INTC-Monitor Control Register 409" hexmask.long.word 0x664 16.--31. 1. "KEYCODE,-" bitfld.long 0x664 7. "NUM1_EN,-" "0,1" bitfld.long 0x664 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x664 4. "CNT_RESET,-" "0,1" bitfld.long 0x664 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x664 1. "IMNTR_EN,-" "0,1" bitfld.long 0x664 0. "WAIT_SET,-" "0,1" line.long 0x668 "IMNTRCR410,INTC-Monitor Control Register 410" hexmask.long.word 0x668 16.--31. 1. "KEYCODE,-" bitfld.long 0x668 7. "NUM1_EN,-" "0,1" bitfld.long 0x668 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x668 4. "CNT_RESET,-" "0,1" bitfld.long 0x668 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x668 1. "IMNTR_EN,-" "0,1" bitfld.long 0x668 0. "WAIT_SET,-" "0,1" line.long 0x66C "IMNTRCR411,INTC-Monitor Control Register 411" hexmask.long.word 0x66C 16.--31. 1. "KEYCODE,-" bitfld.long 0x66C 7. "NUM1_EN,-" "0,1" bitfld.long 0x66C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x66C 4. "CNT_RESET,-" "0,1" bitfld.long 0x66C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x66C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x66C 0. "WAIT_SET,-" "0,1" line.long 0x670 "IMNTRCR412,INTC-Monitor Control Register 412" hexmask.long.word 0x670 16.--31. 1. "KEYCODE,-" bitfld.long 0x670 7. "NUM1_EN,-" "0,1" bitfld.long 0x670 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x670 4. "CNT_RESET,-" "0,1" bitfld.long 0x670 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x670 1. "IMNTR_EN,-" "0,1" bitfld.long 0x670 0. "WAIT_SET,-" "0,1" line.long 0x674 "IMNTRCR413,INTC-Monitor Control Register 413" hexmask.long.word 0x674 16.--31. 1. "KEYCODE,-" bitfld.long 0x674 7. "NUM1_EN,-" "0,1" bitfld.long 0x674 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x674 4. "CNT_RESET,-" "0,1" bitfld.long 0x674 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x674 1. "IMNTR_EN,-" "0,1" bitfld.long 0x674 0. "WAIT_SET,-" "0,1" line.long 0x678 "IMNTRCR414,INTC-Monitor Control Register 414" hexmask.long.word 0x678 16.--31. 1. "KEYCODE,-" bitfld.long 0x678 7. "NUM1_EN,-" "0,1" bitfld.long 0x678 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x678 4. "CNT_RESET,-" "0,1" bitfld.long 0x678 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x678 1. "IMNTR_EN,-" "0,1" bitfld.long 0x678 0. "WAIT_SET,-" "0,1" line.long 0x67C "IMNTRCR415,INTC-Monitor Control Register 415" hexmask.long.word 0x67C 16.--31. 1. "KEYCODE,-" bitfld.long 0x67C 7. "NUM1_EN,-" "0,1" bitfld.long 0x67C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x67C 4. "CNT_RESET,-" "0,1" bitfld.long 0x67C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x67C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x67C 0. "WAIT_SET,-" "0,1" line.long 0x680 "IMNTRCR416,INTC-Monitor Control Register 416" hexmask.long.word 0x680 16.--31. 1. "KEYCODE,-" bitfld.long 0x680 7. "NUM1_EN,-" "0,1" bitfld.long 0x680 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x680 4. "CNT_RESET,-" "0,1" bitfld.long 0x680 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x680 1. "IMNTR_EN,-" "0,1" bitfld.long 0x680 0. "WAIT_SET,-" "0,1" line.long 0x684 "IMNTRCR417,INTC-Monitor Control Register 417" hexmask.long.word 0x684 16.--31. 1. "KEYCODE,-" bitfld.long 0x684 7. "NUM1_EN,-" "0,1" bitfld.long 0x684 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x684 4. "CNT_RESET,-" "0,1" bitfld.long 0x684 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x684 1. "IMNTR_EN,-" "0,1" bitfld.long 0x684 0. "WAIT_SET,-" "0,1" line.long 0x688 "IMNTRCR418,INTC-Monitor Control Register 418" hexmask.long.word 0x688 16.--31. 1. "KEYCODE,-" bitfld.long 0x688 7. "NUM1_EN,-" "0,1" bitfld.long 0x688 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x688 4. "CNT_RESET,-" "0,1" bitfld.long 0x688 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x688 1. "IMNTR_EN,-" "0,1" bitfld.long 0x688 0. "WAIT_SET,-" "0,1" line.long 0x68C "IMNTRCR419,INTC-Monitor Control Register 419" hexmask.long.word 0x68C 16.--31. 1. "KEYCODE,-" bitfld.long 0x68C 7. "NUM1_EN,-" "0,1" bitfld.long 0x68C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x68C 4. "CNT_RESET,-" "0,1" bitfld.long 0x68C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x68C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x68C 0. "WAIT_SET,-" "0,1" line.long 0x690 "IMNTRCR420,INTC-Monitor Control Register 420" hexmask.long.word 0x690 16.--31. 1. "KEYCODE,-" bitfld.long 0x690 7. "NUM1_EN,-" "0,1" bitfld.long 0x690 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x690 4. "CNT_RESET,-" "0,1" bitfld.long 0x690 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x690 1. "IMNTR_EN,-" "0,1" bitfld.long 0x690 0. "WAIT_SET,-" "0,1" line.long 0x694 "IMNTRCR421,INTC-Monitor Control Register 421" hexmask.long.word 0x694 16.--31. 1. "KEYCODE,-" bitfld.long 0x694 7. "NUM1_EN,-" "0,1" bitfld.long 0x694 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x694 4. "CNT_RESET,-" "0,1" bitfld.long 0x694 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x694 1. "IMNTR_EN,-" "0,1" bitfld.long 0x694 0. "WAIT_SET,-" "0,1" line.long 0x698 "IMNTRCR422,INTC-Monitor Control Register 422" hexmask.long.word 0x698 16.--31. 1. "KEYCODE,-" bitfld.long 0x698 7. "NUM1_EN,-" "0,1" bitfld.long 0x698 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x698 4. "CNT_RESET,-" "0,1" bitfld.long 0x698 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x698 1. "IMNTR_EN,-" "0,1" bitfld.long 0x698 0. "WAIT_SET,-" "0,1" line.long 0x69C "IMNTRCR423,INTC-Monitor Control Register 423" hexmask.long.word 0x69C 16.--31. 1. "KEYCODE,-" bitfld.long 0x69C 7. "NUM1_EN,-" "0,1" bitfld.long 0x69C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x69C 4. "CNT_RESET,-" "0,1" bitfld.long 0x69C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x69C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x69C 0. "WAIT_SET,-" "0,1" line.long 0x6A0 "IMNTRCR424,INTC-Monitor Control Register 424" hexmask.long.word 0x6A0 16.--31. 1. "KEYCODE,-" bitfld.long 0x6A0 7. "NUM1_EN,-" "0,1" bitfld.long 0x6A0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6A0 4. "CNT_RESET,-" "0,1" bitfld.long 0x6A0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6A0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6A0 0. "WAIT_SET,-" "0,1" line.long 0x6A4 "IMNTRCR425,INTC-Monitor Control Register 425" hexmask.long.word 0x6A4 16.--31. 1. "KEYCODE,-" bitfld.long 0x6A4 7. "NUM1_EN,-" "0,1" bitfld.long 0x6A4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6A4 4. "CNT_RESET,-" "0,1" bitfld.long 0x6A4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6A4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6A4 0. "WAIT_SET,-" "0,1" line.long 0x6A8 "IMNTRCR426,INTC-Monitor Control Register 426" hexmask.long.word 0x6A8 16.--31. 1. "KEYCODE,-" bitfld.long 0x6A8 7. "NUM1_EN,-" "0,1" bitfld.long 0x6A8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6A8 4. "CNT_RESET,-" "0,1" bitfld.long 0x6A8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6A8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6A8 0. "WAIT_SET,-" "0,1" line.long 0x6AC "IMNTRCR427,INTC-Monitor Control Register 427" hexmask.long.word 0x6AC 16.--31. 1. "KEYCODE,-" bitfld.long 0x6AC 7. "NUM1_EN,-" "0,1" bitfld.long 0x6AC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6AC 4. "CNT_RESET,-" "0,1" bitfld.long 0x6AC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6AC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6AC 0. "WAIT_SET,-" "0,1" line.long 0x6B0 "IMNTRCR428,INTC-Monitor Control Register 428" hexmask.long.word 0x6B0 16.--31. 1. "KEYCODE,-" bitfld.long 0x6B0 7. "NUM1_EN,-" "0,1" bitfld.long 0x6B0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6B0 4. "CNT_RESET,-" "0,1" bitfld.long 0x6B0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6B0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6B0 0. "WAIT_SET,-" "0,1" line.long 0x6B4 "IMNTRCR429,INTC-Monitor Control Register 429" hexmask.long.word 0x6B4 16.--31. 1. "KEYCODE,-" bitfld.long 0x6B4 7. "NUM1_EN,-" "0,1" bitfld.long 0x6B4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6B4 4. "CNT_RESET,-" "0,1" bitfld.long 0x6B4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6B4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6B4 0. "WAIT_SET,-" "0,1" line.long 0x6B8 "IMNTRCR430,INTC-Monitor Control Register 430" hexmask.long.word 0x6B8 16.--31. 1. "KEYCODE,-" bitfld.long 0x6B8 7. "NUM1_EN,-" "0,1" bitfld.long 0x6B8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6B8 4. "CNT_RESET,-" "0,1" bitfld.long 0x6B8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6B8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6B8 0. "WAIT_SET,-" "0,1" line.long 0x6BC "IMNTRCR431,INTC-Monitor Control Register 431" hexmask.long.word 0x6BC 16.--31. 1. "KEYCODE,-" bitfld.long 0x6BC 7. "NUM1_EN,-" "0,1" bitfld.long 0x6BC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6BC 4. "CNT_RESET,-" "0,1" bitfld.long 0x6BC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6BC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6BC 0. "WAIT_SET,-" "0,1" line.long 0x6C0 "IMNTRCR432,INTC-Monitor Control Register 432" hexmask.long.word 0x6C0 16.--31. 1. "KEYCODE,-" bitfld.long 0x6C0 7. "NUM1_EN,-" "0,1" bitfld.long 0x6C0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6C0 4. "CNT_RESET,-" "0,1" bitfld.long 0x6C0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6C0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6C0 0. "WAIT_SET,-" "0,1" line.long 0x6C4 "IMNTRCR433,INTC-Monitor Control Register 433" hexmask.long.word 0x6C4 16.--31. 1. "KEYCODE,-" bitfld.long 0x6C4 7. "NUM1_EN,-" "0,1" bitfld.long 0x6C4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6C4 4. "CNT_RESET,-" "0,1" bitfld.long 0x6C4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6C4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6C4 0. "WAIT_SET,-" "0,1" line.long 0x6C8 "IMNTRCR434,INTC-Monitor Control Register 434" hexmask.long.word 0x6C8 16.--31. 1. "KEYCODE,-" bitfld.long 0x6C8 7. "NUM1_EN,-" "0,1" bitfld.long 0x6C8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6C8 4. "CNT_RESET,-" "0,1" bitfld.long 0x6C8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6C8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6C8 0. "WAIT_SET,-" "0,1" line.long 0x6CC "IMNTRCR435,INTC-Monitor Control Register 435" hexmask.long.word 0x6CC 16.--31. 1. "KEYCODE,-" bitfld.long 0x6CC 7. "NUM1_EN,-" "0,1" bitfld.long 0x6CC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6CC 4. "CNT_RESET,-" "0,1" bitfld.long 0x6CC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6CC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6CC 0. "WAIT_SET,-" "0,1" line.long 0x6D0 "IMNTRCR436,INTC-Monitor Control Register 436" hexmask.long.word 0x6D0 16.--31. 1. "KEYCODE,-" bitfld.long 0x6D0 7. "NUM1_EN,-" "0,1" bitfld.long 0x6D0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6D0 4. "CNT_RESET,-" "0,1" bitfld.long 0x6D0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6D0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6D0 0. "WAIT_SET,-" "0,1" line.long 0x6D4 "IMNTRCR437,INTC-Monitor Control Register 437" hexmask.long.word 0x6D4 16.--31. 1. "KEYCODE,-" bitfld.long 0x6D4 7. "NUM1_EN,-" "0,1" bitfld.long 0x6D4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6D4 4. "CNT_RESET,-" "0,1" bitfld.long 0x6D4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6D4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6D4 0. "WAIT_SET,-" "0,1" line.long 0x6D8 "IMNTRCR438,INTC-Monitor Control Register 438" hexmask.long.word 0x6D8 16.--31. 1. "KEYCODE,-" bitfld.long 0x6D8 7. "NUM1_EN,-" "0,1" bitfld.long 0x6D8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6D8 4. "CNT_RESET,-" "0,1" bitfld.long 0x6D8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6D8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6D8 0. "WAIT_SET,-" "0,1" line.long 0x6DC "IMNTRCR439,INTC-Monitor Control Register 439" hexmask.long.word 0x6DC 16.--31. 1. "KEYCODE,-" bitfld.long 0x6DC 7. "NUM1_EN,-" "0,1" bitfld.long 0x6DC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6DC 4. "CNT_RESET,-" "0,1" bitfld.long 0x6DC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6DC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6DC 0. "WAIT_SET,-" "0,1" line.long 0x6E0 "IMNTRCR440,INTC-Monitor Control Register 440" hexmask.long.word 0x6E0 16.--31. 1. "KEYCODE,-" bitfld.long 0x6E0 7. "NUM1_EN,-" "0,1" bitfld.long 0x6E0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6E0 4. "CNT_RESET,-" "0,1" bitfld.long 0x6E0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6E0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6E0 0. "WAIT_SET,-" "0,1" line.long 0x6E4 "IMNTRCR441,INTC-Monitor Control Register 441" hexmask.long.word 0x6E4 16.--31. 1. "KEYCODE,-" bitfld.long 0x6E4 7. "NUM1_EN,-" "0,1" bitfld.long 0x6E4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6E4 4. "CNT_RESET,-" "0,1" bitfld.long 0x6E4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6E4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6E4 0. "WAIT_SET,-" "0,1" line.long 0x6E8 "IMNTRCR442,INTC-Monitor Control Register 442" hexmask.long.word 0x6E8 16.--31. 1. "KEYCODE,-" bitfld.long 0x6E8 7. "NUM1_EN,-" "0,1" bitfld.long 0x6E8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6E8 4. "CNT_RESET,-" "0,1" bitfld.long 0x6E8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6E8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6E8 0. "WAIT_SET,-" "0,1" line.long 0x6EC "IMNTRCR443,INTC-Monitor Control Register 443" hexmask.long.word 0x6EC 16.--31. 1. "KEYCODE,-" bitfld.long 0x6EC 7. "NUM1_EN,-" "0,1" bitfld.long 0x6EC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6EC 4. "CNT_RESET,-" "0,1" bitfld.long 0x6EC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6EC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6EC 0. "WAIT_SET,-" "0,1" line.long 0x6F0 "IMNTRCR444,INTC-Monitor Control Register 444" hexmask.long.word 0x6F0 16.--31. 1. "KEYCODE,-" bitfld.long 0x6F0 7. "NUM1_EN,-" "0,1" bitfld.long 0x6F0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6F0 4. "CNT_RESET,-" "0,1" bitfld.long 0x6F0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6F0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6F0 0. "WAIT_SET,-" "0,1" line.long 0x6F4 "IMNTRCR445,INTC-Monitor Control Register 445" hexmask.long.word 0x6F4 16.--31. 1. "KEYCODE,-" bitfld.long 0x6F4 7. "NUM1_EN,-" "0,1" bitfld.long 0x6F4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6F4 4. "CNT_RESET,-" "0,1" bitfld.long 0x6F4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6F4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6F4 0. "WAIT_SET,-" "0,1" line.long 0x6F8 "IMNTRCR446,INTC-Monitor Control Register 446" hexmask.long.word 0x6F8 16.--31. 1. "KEYCODE,-" bitfld.long 0x6F8 7. "NUM1_EN,-" "0,1" bitfld.long 0x6F8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6F8 4. "CNT_RESET,-" "0,1" bitfld.long 0x6F8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6F8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6F8 0. "WAIT_SET,-" "0,1" line.long 0x6FC "IMNTRCR447,INTC-Monitor Control Register 447" hexmask.long.word 0x6FC 16.--31. 1. "KEYCODE,-" bitfld.long 0x6FC 7. "NUM1_EN,-" "0,1" bitfld.long 0x6FC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x6FC 4. "CNT_RESET,-" "0,1" bitfld.long 0x6FC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x6FC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x6FC 0. "WAIT_SET,-" "0,1" line.long 0x700 "IMNTRCR448,INTC-Monitor Control Register 448" hexmask.long.word 0x700 16.--31. 1. "KEYCODE,-" bitfld.long 0x700 7. "NUM1_EN,-" "0,1" bitfld.long 0x700 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x700 4. "CNT_RESET,-" "0,1" bitfld.long 0x700 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x700 1. "IMNTR_EN,-" "0,1" bitfld.long 0x700 0. "WAIT_SET,-" "0,1" line.long 0x704 "IMNTRCR449,INTC-Monitor Control Register 449" hexmask.long.word 0x704 16.--31. 1. "KEYCODE,-" bitfld.long 0x704 7. "NUM1_EN,-" "0,1" bitfld.long 0x704 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x704 4. "CNT_RESET,-" "0,1" bitfld.long 0x704 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x704 1. "IMNTR_EN,-" "0,1" bitfld.long 0x704 0. "WAIT_SET,-" "0,1" line.long 0x708 "IMNTRCR450,INTC-Monitor Control Register 450" hexmask.long.word 0x708 16.--31. 1. "KEYCODE,-" bitfld.long 0x708 7. "NUM1_EN,-" "0,1" bitfld.long 0x708 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x708 4. "CNT_RESET,-" "0,1" bitfld.long 0x708 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x708 1. "IMNTR_EN,-" "0,1" bitfld.long 0x708 0. "WAIT_SET,-" "0,1" line.long 0x70C "IMNTRCR451,INTC-Monitor Control Register 451" hexmask.long.word 0x70C 16.--31. 1. "KEYCODE,-" bitfld.long 0x70C 7. "NUM1_EN,-" "0,1" bitfld.long 0x70C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x70C 4. "CNT_RESET,-" "0,1" bitfld.long 0x70C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x70C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x70C 0. "WAIT_SET,-" "0,1" line.long 0x710 "IMNTRCR452,INTC-Monitor Control Register 452" hexmask.long.word 0x710 16.--31. 1. "KEYCODE,-" bitfld.long 0x710 7. "NUM1_EN,-" "0,1" bitfld.long 0x710 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x710 4. "CNT_RESET,-" "0,1" bitfld.long 0x710 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x710 1. "IMNTR_EN,-" "0,1" bitfld.long 0x710 0. "WAIT_SET,-" "0,1" line.long 0x714 "IMNTRCR453,INTC-Monitor Control Register 453" hexmask.long.word 0x714 16.--31. 1. "KEYCODE,-" bitfld.long 0x714 7. "NUM1_EN,-" "0,1" bitfld.long 0x714 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x714 4. "CNT_RESET,-" "0,1" bitfld.long 0x714 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x714 1. "IMNTR_EN,-" "0,1" bitfld.long 0x714 0. "WAIT_SET,-" "0,1" line.long 0x718 "IMNTRCR454,INTC-Monitor Control Register 454" hexmask.long.word 0x718 16.--31. 1. "KEYCODE,-" bitfld.long 0x718 7. "NUM1_EN,-" "0,1" bitfld.long 0x718 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x718 4. "CNT_RESET,-" "0,1" bitfld.long 0x718 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x718 1. "IMNTR_EN,-" "0,1" bitfld.long 0x718 0. "WAIT_SET,-" "0,1" line.long 0x71C "IMNTRCR455,INTC-Monitor Control Register 455" hexmask.long.word 0x71C 16.--31. 1. "KEYCODE,-" bitfld.long 0x71C 7. "NUM1_EN,-" "0,1" bitfld.long 0x71C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x71C 4. "CNT_RESET,-" "0,1" bitfld.long 0x71C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x71C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x71C 0. "WAIT_SET,-" "0,1" line.long 0x720 "IMNTRCR456,INTC-Monitor Control Register 456" hexmask.long.word 0x720 16.--31. 1. "KEYCODE,-" bitfld.long 0x720 7. "NUM1_EN,-" "0,1" bitfld.long 0x720 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x720 4. "CNT_RESET,-" "0,1" bitfld.long 0x720 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x720 1. "IMNTR_EN,-" "0,1" bitfld.long 0x720 0. "WAIT_SET,-" "0,1" line.long 0x724 "IMNTRCR457,INTC-Monitor Control Register 457" hexmask.long.word 0x724 16.--31. 1. "KEYCODE,-" bitfld.long 0x724 7. "NUM1_EN,-" "0,1" bitfld.long 0x724 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x724 4. "CNT_RESET,-" "0,1" bitfld.long 0x724 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x724 1. "IMNTR_EN,-" "0,1" bitfld.long 0x724 0. "WAIT_SET,-" "0,1" line.long 0x728 "IMNTRCR458,INTC-Monitor Control Register 458" hexmask.long.word 0x728 16.--31. 1. "KEYCODE,-" bitfld.long 0x728 7. "NUM1_EN,-" "0,1" bitfld.long 0x728 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x728 4. "CNT_RESET,-" "0,1" bitfld.long 0x728 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x728 1. "IMNTR_EN,-" "0,1" bitfld.long 0x728 0. "WAIT_SET,-" "0,1" line.long 0x72C "IMNTRCR459,INTC-Monitor Control Register 459" hexmask.long.word 0x72C 16.--31. 1. "KEYCODE,-" bitfld.long 0x72C 7. "NUM1_EN,-" "0,1" bitfld.long 0x72C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x72C 4. "CNT_RESET,-" "0,1" bitfld.long 0x72C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x72C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x72C 0. "WAIT_SET,-" "0,1" line.long 0x730 "IMNTRCR460,INTC-Monitor Control Register 460" hexmask.long.word 0x730 16.--31. 1. "KEYCODE,-" bitfld.long 0x730 7. "NUM1_EN,-" "0,1" bitfld.long 0x730 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x730 4. "CNT_RESET,-" "0,1" bitfld.long 0x730 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x730 1. "IMNTR_EN,-" "0,1" bitfld.long 0x730 0. "WAIT_SET,-" "0,1" line.long 0x734 "IMNTRCR461,INTC-Monitor Control Register 461" hexmask.long.word 0x734 16.--31. 1. "KEYCODE,-" bitfld.long 0x734 7. "NUM1_EN,-" "0,1" bitfld.long 0x734 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x734 4. "CNT_RESET,-" "0,1" bitfld.long 0x734 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x734 1. "IMNTR_EN,-" "0,1" bitfld.long 0x734 0. "WAIT_SET,-" "0,1" line.long 0x738 "IMNTRCR462,INTC-Monitor Control Register 462" hexmask.long.word 0x738 16.--31. 1. "KEYCODE,-" bitfld.long 0x738 7. "NUM1_EN,-" "0,1" bitfld.long 0x738 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x738 4. "CNT_RESET,-" "0,1" bitfld.long 0x738 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x738 1. "IMNTR_EN,-" "0,1" bitfld.long 0x738 0. "WAIT_SET,-" "0,1" line.long 0x73C "IMNTRCR463,INTC-Monitor Control Register 463" hexmask.long.word 0x73C 16.--31. 1. "KEYCODE,-" bitfld.long 0x73C 7. "NUM1_EN,-" "0,1" bitfld.long 0x73C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x73C 4. "CNT_RESET,-" "0,1" bitfld.long 0x73C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x73C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x73C 0. "WAIT_SET,-" "0,1" line.long 0x740 "IMNTRCR464,INTC-Monitor Control Register 464" hexmask.long.word 0x740 16.--31. 1. "KEYCODE,-" bitfld.long 0x740 7. "NUM1_EN,-" "0,1" bitfld.long 0x740 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x740 4. "CNT_RESET,-" "0,1" bitfld.long 0x740 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x740 1. "IMNTR_EN,-" "0,1" bitfld.long 0x740 0. "WAIT_SET,-" "0,1" line.long 0x744 "IMNTRCR465,INTC-Monitor Control Register 465" hexmask.long.word 0x744 16.--31. 1. "KEYCODE,-" bitfld.long 0x744 7. "NUM1_EN,-" "0,1" bitfld.long 0x744 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x744 4. "CNT_RESET,-" "0,1" bitfld.long 0x744 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x744 1. "IMNTR_EN,-" "0,1" bitfld.long 0x744 0. "WAIT_SET,-" "0,1" line.long 0x748 "IMNTRCR466,INTC-Monitor Control Register 466" hexmask.long.word 0x748 16.--31. 1. "KEYCODE,-" bitfld.long 0x748 7. "NUM1_EN,-" "0,1" bitfld.long 0x748 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x748 4. "CNT_RESET,-" "0,1" bitfld.long 0x748 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x748 1. "IMNTR_EN,-" "0,1" bitfld.long 0x748 0. "WAIT_SET,-" "0,1" line.long 0x74C "IMNTRCR467,INTC-Monitor Control Register 467" hexmask.long.word 0x74C 16.--31. 1. "KEYCODE,-" bitfld.long 0x74C 7. "NUM1_EN,-" "0,1" bitfld.long 0x74C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x74C 4. "CNT_RESET,-" "0,1" bitfld.long 0x74C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x74C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x74C 0. "WAIT_SET,-" "0,1" line.long 0x750 "IMNTRCR468,INTC-Monitor Control Register 468" hexmask.long.word 0x750 16.--31. 1. "KEYCODE,-" bitfld.long 0x750 7. "NUM1_EN,-" "0,1" bitfld.long 0x750 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x750 4. "CNT_RESET,-" "0,1" bitfld.long 0x750 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x750 1. "IMNTR_EN,-" "0,1" bitfld.long 0x750 0. "WAIT_SET,-" "0,1" line.long 0x754 "IMNTRCR469,INTC-Monitor Control Register 469" hexmask.long.word 0x754 16.--31. 1. "KEYCODE,-" bitfld.long 0x754 7. "NUM1_EN,-" "0,1" bitfld.long 0x754 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x754 4. "CNT_RESET,-" "0,1" bitfld.long 0x754 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x754 1. "IMNTR_EN,-" "0,1" bitfld.long 0x754 0. "WAIT_SET,-" "0,1" line.long 0x758 "IMNTRCR470,INTC-Monitor Control Register 470" hexmask.long.word 0x758 16.--31. 1. "KEYCODE,-" bitfld.long 0x758 7. "NUM1_EN,-" "0,1" bitfld.long 0x758 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x758 4. "CNT_RESET,-" "0,1" bitfld.long 0x758 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x758 1. "IMNTR_EN,-" "0,1" bitfld.long 0x758 0. "WAIT_SET,-" "0,1" line.long 0x75C "IMNTRCR471,INTC-Monitor Control Register 471" hexmask.long.word 0x75C 16.--31. 1. "KEYCODE,-" bitfld.long 0x75C 7. "NUM1_EN,-" "0,1" bitfld.long 0x75C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x75C 4. "CNT_RESET,-" "0,1" bitfld.long 0x75C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x75C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x75C 0. "WAIT_SET,-" "0,1" line.long 0x760 "IMNTRCR472,INTC-Monitor Control Register 472" hexmask.long.word 0x760 16.--31. 1. "KEYCODE,-" bitfld.long 0x760 7. "NUM1_EN,-" "0,1" bitfld.long 0x760 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x760 4. "CNT_RESET,-" "0,1" bitfld.long 0x760 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x760 1. "IMNTR_EN,-" "0,1" bitfld.long 0x760 0. "WAIT_SET,-" "0,1" line.long 0x764 "IMNTRCR473,INTC-Monitor Control Register 473" hexmask.long.word 0x764 16.--31. 1. "KEYCODE,-" bitfld.long 0x764 7. "NUM1_EN,-" "0,1" bitfld.long 0x764 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x764 4. "CNT_RESET,-" "0,1" bitfld.long 0x764 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x764 1. "IMNTR_EN,-" "0,1" bitfld.long 0x764 0. "WAIT_SET,-" "0,1" line.long 0x768 "IMNTRCR474,INTC-Monitor Control Register 474" hexmask.long.word 0x768 16.--31. 1. "KEYCODE,-" bitfld.long 0x768 7. "NUM1_EN,-" "0,1" bitfld.long 0x768 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x768 4. "CNT_RESET,-" "0,1" bitfld.long 0x768 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x768 1. "IMNTR_EN,-" "0,1" bitfld.long 0x768 0. "WAIT_SET,-" "0,1" line.long 0x76C "IMNTRCR475,INTC-Monitor Control Register 475" hexmask.long.word 0x76C 16.--31. 1. "KEYCODE,-" bitfld.long 0x76C 7. "NUM1_EN,-" "0,1" bitfld.long 0x76C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x76C 4. "CNT_RESET,-" "0,1" bitfld.long 0x76C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x76C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x76C 0. "WAIT_SET,-" "0,1" line.long 0x770 "IMNTRCR476,INTC-Monitor Control Register 476" hexmask.long.word 0x770 16.--31. 1. "KEYCODE,-" bitfld.long 0x770 7. "NUM1_EN,-" "0,1" bitfld.long 0x770 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x770 4. "CNT_RESET,-" "0,1" bitfld.long 0x770 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x770 1. "IMNTR_EN,-" "0,1" bitfld.long 0x770 0. "WAIT_SET,-" "0,1" line.long 0x774 "IMNTRCR477,INTC-Monitor Control Register 477" hexmask.long.word 0x774 16.--31. 1. "KEYCODE,-" bitfld.long 0x774 7. "NUM1_EN,-" "0,1" bitfld.long 0x774 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x774 4. "CNT_RESET,-" "0,1" bitfld.long 0x774 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x774 1. "IMNTR_EN,-" "0,1" bitfld.long 0x774 0. "WAIT_SET,-" "0,1" line.long 0x778 "IMNTRCR478,INTC-Monitor Control Register 478" hexmask.long.word 0x778 16.--31. 1. "KEYCODE,-" bitfld.long 0x778 7. "NUM1_EN,-" "0,1" bitfld.long 0x778 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x778 4. "CNT_RESET,-" "0,1" bitfld.long 0x778 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x778 1. "IMNTR_EN,-" "0,1" bitfld.long 0x778 0. "WAIT_SET,-" "0,1" line.long 0x77C "IMNTRCR479,INTC-Monitor Control Register 479" hexmask.long.word 0x77C 16.--31. 1. "KEYCODE,-" bitfld.long 0x77C 7. "NUM1_EN,-" "0,1" bitfld.long 0x77C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x77C 4. "CNT_RESET,-" "0,1" bitfld.long 0x77C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x77C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x77C 0. "WAIT_SET,-" "0,1" line.long 0x780 "IMNTRCR480,INTC-Monitor Control Register 480" hexmask.long.word 0x780 16.--31. 1. "KEYCODE,-" bitfld.long 0x780 7. "NUM1_EN,-" "0,1" bitfld.long 0x780 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x780 4. "CNT_RESET,-" "0,1" bitfld.long 0x780 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x780 1. "IMNTR_EN,-" "0,1" bitfld.long 0x780 0. "WAIT_SET,-" "0,1" line.long 0x784 "IMNTRCR481,INTC-Monitor Control Register 481" hexmask.long.word 0x784 16.--31. 1. "KEYCODE,-" bitfld.long 0x784 7. "NUM1_EN,-" "0,1" bitfld.long 0x784 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x784 4. "CNT_RESET,-" "0,1" bitfld.long 0x784 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x784 1. "IMNTR_EN,-" "0,1" bitfld.long 0x784 0. "WAIT_SET,-" "0,1" line.long 0x788 "IMNTRCR482,INTC-Monitor Control Register 482" hexmask.long.word 0x788 16.--31. 1. "KEYCODE,-" bitfld.long 0x788 7. "NUM1_EN,-" "0,1" bitfld.long 0x788 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x788 4. "CNT_RESET,-" "0,1" bitfld.long 0x788 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x788 1. "IMNTR_EN,-" "0,1" bitfld.long 0x788 0. "WAIT_SET,-" "0,1" line.long 0x78C "IMNTRCR483,INTC-Monitor Control Register 483" hexmask.long.word 0x78C 16.--31. 1. "KEYCODE,-" bitfld.long 0x78C 7. "NUM1_EN,-" "0,1" bitfld.long 0x78C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x78C 4. "CNT_RESET,-" "0,1" bitfld.long 0x78C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x78C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x78C 0. "WAIT_SET,-" "0,1" line.long 0x790 "IMNTRCR484,INTC-Monitor Control Register 484" hexmask.long.word 0x790 16.--31. 1. "KEYCODE,-" bitfld.long 0x790 7. "NUM1_EN,-" "0,1" bitfld.long 0x790 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x790 4. "CNT_RESET,-" "0,1" bitfld.long 0x790 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x790 1. "IMNTR_EN,-" "0,1" bitfld.long 0x790 0. "WAIT_SET,-" "0,1" line.long 0x794 "IMNTRCR485,INTC-Monitor Control Register 485" hexmask.long.word 0x794 16.--31. 1. "KEYCODE,-" bitfld.long 0x794 7. "NUM1_EN,-" "0,1" bitfld.long 0x794 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x794 4. "CNT_RESET,-" "0,1" bitfld.long 0x794 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x794 1. "IMNTR_EN,-" "0,1" bitfld.long 0x794 0. "WAIT_SET,-" "0,1" line.long 0x798 "IMNTRCR486,INTC-Monitor Control Register 486" hexmask.long.word 0x798 16.--31. 1. "KEYCODE,-" bitfld.long 0x798 7. "NUM1_EN,-" "0,1" bitfld.long 0x798 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x798 4. "CNT_RESET,-" "0,1" bitfld.long 0x798 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x798 1. "IMNTR_EN,-" "0,1" bitfld.long 0x798 0. "WAIT_SET,-" "0,1" line.long 0x79C "IMNTRCR487,INTC-Monitor Control Register 487" hexmask.long.word 0x79C 16.--31. 1. "KEYCODE,-" bitfld.long 0x79C 7. "NUM1_EN,-" "0,1" bitfld.long 0x79C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x79C 4. "CNT_RESET,-" "0,1" bitfld.long 0x79C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x79C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x79C 0. "WAIT_SET,-" "0,1" line.long 0x7A0 "IMNTRCR488,INTC-Monitor Control Register 488" hexmask.long.word 0x7A0 16.--31. 1. "KEYCODE,-" bitfld.long 0x7A0 7. "NUM1_EN,-" "0,1" bitfld.long 0x7A0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7A0 4. "CNT_RESET,-" "0,1" bitfld.long 0x7A0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7A0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7A0 0. "WAIT_SET,-" "0,1" line.long 0x7A4 "IMNTRCR489,INTC-Monitor Control Register 489" hexmask.long.word 0x7A4 16.--31. 1. "KEYCODE,-" bitfld.long 0x7A4 7. "NUM1_EN,-" "0,1" bitfld.long 0x7A4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7A4 4. "CNT_RESET,-" "0,1" bitfld.long 0x7A4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7A4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7A4 0. "WAIT_SET,-" "0,1" line.long 0x7A8 "IMNTRCR490,INTC-Monitor Control Register 490" hexmask.long.word 0x7A8 16.--31. 1. "KEYCODE,-" bitfld.long 0x7A8 7. "NUM1_EN,-" "0,1" bitfld.long 0x7A8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7A8 4. "CNT_RESET,-" "0,1" bitfld.long 0x7A8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7A8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7A8 0. "WAIT_SET,-" "0,1" line.long 0x7AC "IMNTRCR491,INTC-Monitor Control Register 491" hexmask.long.word 0x7AC 16.--31. 1. "KEYCODE,-" bitfld.long 0x7AC 7. "NUM1_EN,-" "0,1" bitfld.long 0x7AC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7AC 4. "CNT_RESET,-" "0,1" bitfld.long 0x7AC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7AC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7AC 0. "WAIT_SET,-" "0,1" line.long 0x7B0 "IMNTRCR492,INTC-Monitor Control Register 492" hexmask.long.word 0x7B0 16.--31. 1. "KEYCODE,-" bitfld.long 0x7B0 7. "NUM1_EN,-" "0,1" bitfld.long 0x7B0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7B0 4. "CNT_RESET,-" "0,1" bitfld.long 0x7B0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7B0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7B0 0. "WAIT_SET,-" "0,1" line.long 0x7B4 "IMNTRCR493,INTC-Monitor Control Register 493" hexmask.long.word 0x7B4 16.--31. 1. "KEYCODE,-" bitfld.long 0x7B4 7. "NUM1_EN,-" "0,1" bitfld.long 0x7B4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7B4 4. "CNT_RESET,-" "0,1" bitfld.long 0x7B4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7B4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7B4 0. "WAIT_SET,-" "0,1" line.long 0x7B8 "IMNTRCR494,INTC-Monitor Control Register 494" hexmask.long.word 0x7B8 16.--31. 1. "KEYCODE,-" bitfld.long 0x7B8 7. "NUM1_EN,-" "0,1" bitfld.long 0x7B8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7B8 4. "CNT_RESET,-" "0,1" bitfld.long 0x7B8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7B8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7B8 0. "WAIT_SET,-" "0,1" line.long 0x7BC "IMNTRCR495,INTC-Monitor Control Register 495" hexmask.long.word 0x7BC 16.--31. 1. "KEYCODE,-" bitfld.long 0x7BC 7. "NUM1_EN,-" "0,1" bitfld.long 0x7BC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7BC 4. "CNT_RESET,-" "0,1" bitfld.long 0x7BC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7BC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7BC 0. "WAIT_SET,-" "0,1" line.long 0x7C0 "IMNTRCR496,INTC-Monitor Control Register 496" hexmask.long.word 0x7C0 16.--31. 1. "KEYCODE,-" bitfld.long 0x7C0 7. "NUM1_EN,-" "0,1" bitfld.long 0x7C0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7C0 4. "CNT_RESET,-" "0,1" bitfld.long 0x7C0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7C0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7C0 0. "WAIT_SET,-" "0,1" line.long 0x7C4 "IMNTRCR497,INTC-Monitor Control Register 497" hexmask.long.word 0x7C4 16.--31. 1. "KEYCODE,-" bitfld.long 0x7C4 7. "NUM1_EN,-" "0,1" bitfld.long 0x7C4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7C4 4. "CNT_RESET,-" "0,1" bitfld.long 0x7C4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7C4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7C4 0. "WAIT_SET,-" "0,1" line.long 0x7C8 "IMNTRCR498,INTC-Monitor Control Register 498" hexmask.long.word 0x7C8 16.--31. 1. "KEYCODE,-" bitfld.long 0x7C8 7. "NUM1_EN,-" "0,1" bitfld.long 0x7C8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7C8 4. "CNT_RESET,-" "0,1" bitfld.long 0x7C8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7C8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7C8 0. "WAIT_SET,-" "0,1" line.long 0x7CC "IMNTRCR499,INTC-Monitor Control Register 499" hexmask.long.word 0x7CC 16.--31. 1. "KEYCODE,-" bitfld.long 0x7CC 7. "NUM1_EN,-" "0,1" bitfld.long 0x7CC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7CC 4. "CNT_RESET,-" "0,1" bitfld.long 0x7CC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7CC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7CC 0. "WAIT_SET,-" "0,1" line.long 0x7D0 "IMNTRCR500,INTC-Monitor Control Register 500" hexmask.long.word 0x7D0 16.--31. 1. "KEYCODE,-" bitfld.long 0x7D0 7. "NUM1_EN,-" "0,1" bitfld.long 0x7D0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7D0 4. "CNT_RESET,-" "0,1" bitfld.long 0x7D0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7D0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7D0 0. "WAIT_SET,-" "0,1" line.long 0x7D4 "IMNTRCR501,INTC-Monitor Control Register 501" hexmask.long.word 0x7D4 16.--31. 1. "KEYCODE,-" bitfld.long 0x7D4 7. "NUM1_EN,-" "0,1" bitfld.long 0x7D4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7D4 4. "CNT_RESET,-" "0,1" bitfld.long 0x7D4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7D4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7D4 0. "WAIT_SET,-" "0,1" line.long 0x7D8 "IMNTRCR502,INTC-Monitor Control Register 502" hexmask.long.word 0x7D8 16.--31. 1. "KEYCODE,-" bitfld.long 0x7D8 7. "NUM1_EN,-" "0,1" bitfld.long 0x7D8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7D8 4. "CNT_RESET,-" "0,1" bitfld.long 0x7D8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7D8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7D8 0. "WAIT_SET,-" "0,1" line.long 0x7DC "IMNTRCR503,INTC-Monitor Control Register 503" hexmask.long.word 0x7DC 16.--31. 1. "KEYCODE,-" bitfld.long 0x7DC 7. "NUM1_EN,-" "0,1" bitfld.long 0x7DC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7DC 4. "CNT_RESET,-" "0,1" bitfld.long 0x7DC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7DC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7DC 0. "WAIT_SET,-" "0,1" line.long 0x7E0 "IMNTRCR504,INTC-Monitor Control Register 504" hexmask.long.word 0x7E0 16.--31. 1. "KEYCODE,-" bitfld.long 0x7E0 7. "NUM1_EN,-" "0,1" bitfld.long 0x7E0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7E0 4. "CNT_RESET,-" "0,1" bitfld.long 0x7E0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7E0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7E0 0. "WAIT_SET,-" "0,1" line.long 0x7E4 "IMNTRCR505,INTC-Monitor Control Register 505" hexmask.long.word 0x7E4 16.--31. 1. "KEYCODE,-" bitfld.long 0x7E4 7. "NUM1_EN,-" "0,1" bitfld.long 0x7E4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7E4 4. "CNT_RESET,-" "0,1" bitfld.long 0x7E4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7E4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7E4 0. "WAIT_SET,-" "0,1" line.long 0x7E8 "IMNTRCR506,INTC-Monitor Control Register 506" hexmask.long.word 0x7E8 16.--31. 1. "KEYCODE,-" bitfld.long 0x7E8 7. "NUM1_EN,-" "0,1" bitfld.long 0x7E8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7E8 4. "CNT_RESET,-" "0,1" bitfld.long 0x7E8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7E8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7E8 0. "WAIT_SET,-" "0,1" line.long 0x7EC "IMNTRCR507,INTC-Monitor Control Register 507" hexmask.long.word 0x7EC 16.--31. 1. "KEYCODE,-" bitfld.long 0x7EC 7. "NUM1_EN,-" "0,1" bitfld.long 0x7EC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7EC 4. "CNT_RESET,-" "0,1" bitfld.long 0x7EC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7EC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7EC 0. "WAIT_SET,-" "0,1" line.long 0x7F0 "IMNTRCR508,INTC-Monitor Control Register 508" hexmask.long.word 0x7F0 16.--31. 1. "KEYCODE,-" bitfld.long 0x7F0 7. "NUM1_EN,-" "0,1" bitfld.long 0x7F0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7F0 4. "CNT_RESET,-" "0,1" bitfld.long 0x7F0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7F0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7F0 0. "WAIT_SET,-" "0,1" line.long 0x7F4 "IMNTRCR509,INTC-Monitor Control Register 509" hexmask.long.word 0x7F4 16.--31. 1. "KEYCODE,-" bitfld.long 0x7F4 7. "NUM1_EN,-" "0,1" bitfld.long 0x7F4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7F4 4. "CNT_RESET,-" "0,1" bitfld.long 0x7F4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7F4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7F4 0. "WAIT_SET,-" "0,1" line.long 0x7F8 "IMNTRCR510,INTC-Monitor Control Register 510" hexmask.long.word 0x7F8 16.--31. 1. "KEYCODE,-" bitfld.long 0x7F8 7. "NUM1_EN,-" "0,1" bitfld.long 0x7F8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7F8 4. "CNT_RESET,-" "0,1" bitfld.long 0x7F8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7F8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7F8 0. "WAIT_SET,-" "0,1" line.long 0x7FC "IMNTRCR511,INTC-Monitor Control Register 511" hexmask.long.word 0x7FC 16.--31. 1. "KEYCODE,-" bitfld.long 0x7FC 7. "NUM1_EN,-" "0,1" bitfld.long 0x7FC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x7FC 4. "CNT_RESET,-" "0,1" bitfld.long 0x7FC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x7FC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x7FC 0. "WAIT_SET,-" "0,1" line.long 0x800 "IMNTRCR512,INTC-Monitor Control Register 512" hexmask.long.word 0x800 16.--31. 1. "KEYCODE,-" bitfld.long 0x800 7. "NUM1_EN,-" "0,1" bitfld.long 0x800 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x800 4. "CNT_RESET,-" "0,1" bitfld.long 0x800 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x800 1. "IMNTR_EN,-" "0,1" bitfld.long 0x800 0. "WAIT_SET,-" "0,1" line.long 0x804 "IMNTRCR513,INTC-Monitor Control Register 513" hexmask.long.word 0x804 16.--31. 1. "KEYCODE,-" bitfld.long 0x804 7. "NUM1_EN,-" "0,1" bitfld.long 0x804 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x804 4. "CNT_RESET,-" "0,1" bitfld.long 0x804 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x804 1. "IMNTR_EN,-" "0,1" bitfld.long 0x804 0. "WAIT_SET,-" "0,1" line.long 0x808 "IMNTRCR514,INTC-Monitor Control Register 514" hexmask.long.word 0x808 16.--31. 1. "KEYCODE,-" bitfld.long 0x808 7. "NUM1_EN,-" "0,1" bitfld.long 0x808 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x808 4. "CNT_RESET,-" "0,1" bitfld.long 0x808 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x808 1. "IMNTR_EN,-" "0,1" bitfld.long 0x808 0. "WAIT_SET,-" "0,1" line.long 0x80C "IMNTRCR515,INTC-Monitor Control Register 515" hexmask.long.word 0x80C 16.--31. 1. "KEYCODE,-" bitfld.long 0x80C 7. "NUM1_EN,-" "0,1" bitfld.long 0x80C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x80C 4. "CNT_RESET,-" "0,1" bitfld.long 0x80C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x80C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x80C 0. "WAIT_SET,-" "0,1" line.long 0x810 "IMNTRCR516,INTC-Monitor Control Register 516" hexmask.long.word 0x810 16.--31. 1. "KEYCODE,-" bitfld.long 0x810 7. "NUM1_EN,-" "0,1" bitfld.long 0x810 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x810 4. "CNT_RESET,-" "0,1" bitfld.long 0x810 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x810 1. "IMNTR_EN,-" "0,1" bitfld.long 0x810 0. "WAIT_SET,-" "0,1" line.long 0x814 "IMNTRCR517,INTC-Monitor Control Register 517" hexmask.long.word 0x814 16.--31. 1. "KEYCODE,-" bitfld.long 0x814 7. "NUM1_EN,-" "0,1" bitfld.long 0x814 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x814 4. "CNT_RESET,-" "0,1" bitfld.long 0x814 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x814 1. "IMNTR_EN,-" "0,1" bitfld.long 0x814 0. "WAIT_SET,-" "0,1" line.long 0x818 "IMNTRCR518,INTC-Monitor Control Register 518" hexmask.long.word 0x818 16.--31. 1. "KEYCODE,-" bitfld.long 0x818 7. "NUM1_EN,-" "0,1" bitfld.long 0x818 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x818 4. "CNT_RESET,-" "0,1" bitfld.long 0x818 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x818 1. "IMNTR_EN,-" "0,1" bitfld.long 0x818 0. "WAIT_SET,-" "0,1" line.long 0x81C "IMNTRCR519,INTC-Monitor Control Register 519" hexmask.long.word 0x81C 16.--31. 1. "KEYCODE,-" bitfld.long 0x81C 7. "NUM1_EN,-" "0,1" bitfld.long 0x81C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x81C 4. "CNT_RESET,-" "0,1" bitfld.long 0x81C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x81C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x81C 0. "WAIT_SET,-" "0,1" line.long 0x820 "IMNTRCR520,INTC-Monitor Control Register 520" hexmask.long.word 0x820 16.--31. 1. "KEYCODE,-" bitfld.long 0x820 7. "NUM1_EN,-" "0,1" bitfld.long 0x820 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x820 4. "CNT_RESET,-" "0,1" bitfld.long 0x820 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x820 1. "IMNTR_EN,-" "0,1" bitfld.long 0x820 0. "WAIT_SET,-" "0,1" line.long 0x824 "IMNTRCR521,INTC-Monitor Control Register 521" hexmask.long.word 0x824 16.--31. 1. "KEYCODE,-" bitfld.long 0x824 7. "NUM1_EN,-" "0,1" bitfld.long 0x824 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x824 4. "CNT_RESET,-" "0,1" bitfld.long 0x824 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x824 1. "IMNTR_EN,-" "0,1" bitfld.long 0x824 0. "WAIT_SET,-" "0,1" line.long 0x828 "IMNTRCR522,INTC-Monitor Control Register 522" hexmask.long.word 0x828 16.--31. 1. "KEYCODE,-" bitfld.long 0x828 7. "NUM1_EN,-" "0,1" bitfld.long 0x828 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x828 4. "CNT_RESET,-" "0,1" bitfld.long 0x828 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x828 1. "IMNTR_EN,-" "0,1" bitfld.long 0x828 0. "WAIT_SET,-" "0,1" line.long 0x82C "IMNTRCR523,INTC-Monitor Control Register 523" hexmask.long.word 0x82C 16.--31. 1. "KEYCODE,-" bitfld.long 0x82C 7. "NUM1_EN,-" "0,1" bitfld.long 0x82C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x82C 4. "CNT_RESET,-" "0,1" bitfld.long 0x82C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x82C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x82C 0. "WAIT_SET,-" "0,1" line.long 0x830 "IMNTRCR524,INTC-Monitor Control Register 524" hexmask.long.word 0x830 16.--31. 1. "KEYCODE,-" bitfld.long 0x830 7. "NUM1_EN,-" "0,1" bitfld.long 0x830 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x830 4. "CNT_RESET,-" "0,1" bitfld.long 0x830 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x830 1. "IMNTR_EN,-" "0,1" bitfld.long 0x830 0. "WAIT_SET,-" "0,1" line.long 0x834 "IMNTRCR525,INTC-Monitor Control Register 525" hexmask.long.word 0x834 16.--31. 1. "KEYCODE,-" bitfld.long 0x834 7. "NUM1_EN,-" "0,1" bitfld.long 0x834 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x834 4. "CNT_RESET,-" "0,1" bitfld.long 0x834 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x834 1. "IMNTR_EN,-" "0,1" bitfld.long 0x834 0. "WAIT_SET,-" "0,1" line.long 0x838 "IMNTRCR526,INTC-Monitor Control Register 526" hexmask.long.word 0x838 16.--31. 1. "KEYCODE,-" bitfld.long 0x838 7. "NUM1_EN,-" "0,1" bitfld.long 0x838 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x838 4. "CNT_RESET,-" "0,1" bitfld.long 0x838 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x838 1. "IMNTR_EN,-" "0,1" bitfld.long 0x838 0. "WAIT_SET,-" "0,1" line.long 0x83C "IMNTRCR527,INTC-Monitor Control Register 527" hexmask.long.word 0x83C 16.--31. 1. "KEYCODE,-" bitfld.long 0x83C 7. "NUM1_EN,-" "0,1" bitfld.long 0x83C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x83C 4. "CNT_RESET,-" "0,1" bitfld.long 0x83C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x83C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x83C 0. "WAIT_SET,-" "0,1" line.long 0x840 "IMNTRCR528,INTC-Monitor Control Register 528" hexmask.long.word 0x840 16.--31. 1. "KEYCODE,-" bitfld.long 0x840 7. "NUM1_EN,-" "0,1" bitfld.long 0x840 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x840 4. "CNT_RESET,-" "0,1" bitfld.long 0x840 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x840 1. "IMNTR_EN,-" "0,1" bitfld.long 0x840 0. "WAIT_SET,-" "0,1" line.long 0x844 "IMNTRCR529,INTC-Monitor Control Register 529" hexmask.long.word 0x844 16.--31. 1. "KEYCODE,-" bitfld.long 0x844 7. "NUM1_EN,-" "0,1" bitfld.long 0x844 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x844 4. "CNT_RESET,-" "0,1" bitfld.long 0x844 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x844 1. "IMNTR_EN,-" "0,1" bitfld.long 0x844 0. "WAIT_SET,-" "0,1" line.long 0x848 "IMNTRCR530,INTC-Monitor Control Register 530" hexmask.long.word 0x848 16.--31. 1. "KEYCODE,-" bitfld.long 0x848 7. "NUM1_EN,-" "0,1" bitfld.long 0x848 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x848 4. "CNT_RESET,-" "0,1" bitfld.long 0x848 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x848 1. "IMNTR_EN,-" "0,1" bitfld.long 0x848 0. "WAIT_SET,-" "0,1" line.long 0x84C "IMNTRCR531,INTC-Monitor Control Register 531" hexmask.long.word 0x84C 16.--31. 1. "KEYCODE,-" bitfld.long 0x84C 7. "NUM1_EN,-" "0,1" bitfld.long 0x84C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x84C 4. "CNT_RESET,-" "0,1" bitfld.long 0x84C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x84C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x84C 0. "WAIT_SET,-" "0,1" line.long 0x850 "IMNTRCR532,INTC-Monitor Control Register 532" hexmask.long.word 0x850 16.--31. 1. "KEYCODE,-" bitfld.long 0x850 7. "NUM1_EN,-" "0,1" bitfld.long 0x850 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x850 4. "CNT_RESET,-" "0,1" bitfld.long 0x850 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x850 1. "IMNTR_EN,-" "0,1" bitfld.long 0x850 0. "WAIT_SET,-" "0,1" line.long 0x854 "IMNTRCR533,INTC-Monitor Control Register 533" hexmask.long.word 0x854 16.--31. 1. "KEYCODE,-" bitfld.long 0x854 7. "NUM1_EN,-" "0,1" bitfld.long 0x854 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x854 4. "CNT_RESET,-" "0,1" bitfld.long 0x854 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x854 1. "IMNTR_EN,-" "0,1" bitfld.long 0x854 0. "WAIT_SET,-" "0,1" line.long 0x858 "IMNTRCR534,INTC-Monitor Control Register 534" hexmask.long.word 0x858 16.--31. 1. "KEYCODE,-" bitfld.long 0x858 7. "NUM1_EN,-" "0,1" bitfld.long 0x858 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x858 4. "CNT_RESET,-" "0,1" bitfld.long 0x858 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x858 1. "IMNTR_EN,-" "0,1" bitfld.long 0x858 0. "WAIT_SET,-" "0,1" line.long 0x85C "IMNTRCR535,INTC-Monitor Control Register 535" hexmask.long.word 0x85C 16.--31. 1. "KEYCODE,-" bitfld.long 0x85C 7. "NUM1_EN,-" "0,1" bitfld.long 0x85C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x85C 4. "CNT_RESET,-" "0,1" bitfld.long 0x85C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x85C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x85C 0. "WAIT_SET,-" "0,1" line.long 0x860 "IMNTRCR536,INTC-Monitor Control Register 536" hexmask.long.word 0x860 16.--31. 1. "KEYCODE,-" bitfld.long 0x860 7. "NUM1_EN,-" "0,1" bitfld.long 0x860 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x860 4. "CNT_RESET,-" "0,1" bitfld.long 0x860 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x860 1. "IMNTR_EN,-" "0,1" bitfld.long 0x860 0. "WAIT_SET,-" "0,1" line.long 0x864 "IMNTRCR537,INTC-Monitor Control Register 537" hexmask.long.word 0x864 16.--31. 1. "KEYCODE,-" bitfld.long 0x864 7. "NUM1_EN,-" "0,1" bitfld.long 0x864 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x864 4. "CNT_RESET,-" "0,1" bitfld.long 0x864 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x864 1. "IMNTR_EN,-" "0,1" bitfld.long 0x864 0. "WAIT_SET,-" "0,1" line.long 0x868 "IMNTRCR538,INTC-Monitor Control Register 538" hexmask.long.word 0x868 16.--31. 1. "KEYCODE,-" bitfld.long 0x868 7. "NUM1_EN,-" "0,1" bitfld.long 0x868 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x868 4. "CNT_RESET,-" "0,1" bitfld.long 0x868 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x868 1. "IMNTR_EN,-" "0,1" bitfld.long 0x868 0. "WAIT_SET,-" "0,1" line.long 0x86C "IMNTRCR539,INTC-Monitor Control Register 539" hexmask.long.word 0x86C 16.--31. 1. "KEYCODE,-" bitfld.long 0x86C 7. "NUM1_EN,-" "0,1" bitfld.long 0x86C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x86C 4. "CNT_RESET,-" "0,1" bitfld.long 0x86C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x86C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x86C 0. "WAIT_SET,-" "0,1" line.long 0x870 "IMNTRCR540,INTC-Monitor Control Register 540" hexmask.long.word 0x870 16.--31. 1. "KEYCODE,-" bitfld.long 0x870 7. "NUM1_EN,-" "0,1" bitfld.long 0x870 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x870 4. "CNT_RESET,-" "0,1" bitfld.long 0x870 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x870 1. "IMNTR_EN,-" "0,1" bitfld.long 0x870 0. "WAIT_SET,-" "0,1" line.long 0x874 "IMNTRCR541,INTC-Monitor Control Register 541" hexmask.long.word 0x874 16.--31. 1. "KEYCODE,-" bitfld.long 0x874 7. "NUM1_EN,-" "0,1" bitfld.long 0x874 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x874 4. "CNT_RESET,-" "0,1" bitfld.long 0x874 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x874 1. "IMNTR_EN,-" "0,1" bitfld.long 0x874 0. "WAIT_SET,-" "0,1" line.long 0x878 "IMNTRCR542,INTC-Monitor Control Register 542" hexmask.long.word 0x878 16.--31. 1. "KEYCODE,-" bitfld.long 0x878 7. "NUM1_EN,-" "0,1" bitfld.long 0x878 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x878 4. "CNT_RESET,-" "0,1" bitfld.long 0x878 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x878 1. "IMNTR_EN,-" "0,1" bitfld.long 0x878 0. "WAIT_SET,-" "0,1" line.long 0x87C "IMNTRCR543,INTC-Monitor Control Register 543" hexmask.long.word 0x87C 16.--31. 1. "KEYCODE,-" bitfld.long 0x87C 7. "NUM1_EN,-" "0,1" bitfld.long 0x87C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x87C 4. "CNT_RESET,-" "0,1" bitfld.long 0x87C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x87C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x87C 0. "WAIT_SET,-" "0,1" line.long 0x880 "IMNTRCR544,INTC-Monitor Control Register 544" hexmask.long.word 0x880 16.--31. 1. "KEYCODE,-" bitfld.long 0x880 7. "NUM1_EN,-" "0,1" bitfld.long 0x880 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x880 4. "CNT_RESET,-" "0,1" bitfld.long 0x880 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x880 1. "IMNTR_EN,-" "0,1" bitfld.long 0x880 0. "WAIT_SET,-" "0,1" line.long 0x884 "IMNTRCR545,INTC-Monitor Control Register 545" hexmask.long.word 0x884 16.--31. 1. "KEYCODE,-" bitfld.long 0x884 7. "NUM1_EN,-" "0,1" bitfld.long 0x884 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x884 4. "CNT_RESET,-" "0,1" bitfld.long 0x884 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x884 1. "IMNTR_EN,-" "0,1" bitfld.long 0x884 0. "WAIT_SET,-" "0,1" line.long 0x888 "IMNTRCR546,INTC-Monitor Control Register 546" hexmask.long.word 0x888 16.--31. 1. "KEYCODE,-" bitfld.long 0x888 7. "NUM1_EN,-" "0,1" bitfld.long 0x888 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x888 4. "CNT_RESET,-" "0,1" bitfld.long 0x888 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x888 1. "IMNTR_EN,-" "0,1" bitfld.long 0x888 0. "WAIT_SET,-" "0,1" line.long 0x88C "IMNTRCR547,INTC-Monitor Control Register 547" hexmask.long.word 0x88C 16.--31. 1. "KEYCODE,-" bitfld.long 0x88C 7. "NUM1_EN,-" "0,1" bitfld.long 0x88C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x88C 4. "CNT_RESET,-" "0,1" bitfld.long 0x88C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x88C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x88C 0. "WAIT_SET,-" "0,1" line.long 0x890 "IMNTRCR548,INTC-Monitor Control Register 548" hexmask.long.word 0x890 16.--31. 1. "KEYCODE,-" bitfld.long 0x890 7. "NUM1_EN,-" "0,1" bitfld.long 0x890 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x890 4. "CNT_RESET,-" "0,1" bitfld.long 0x890 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x890 1. "IMNTR_EN,-" "0,1" bitfld.long 0x890 0. "WAIT_SET,-" "0,1" line.long 0x894 "IMNTRCR549,INTC-Monitor Control Register 549" hexmask.long.word 0x894 16.--31. 1. "KEYCODE,-" bitfld.long 0x894 7. "NUM1_EN,-" "0,1" bitfld.long 0x894 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x894 4. "CNT_RESET,-" "0,1" bitfld.long 0x894 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x894 1. "IMNTR_EN,-" "0,1" bitfld.long 0x894 0. "WAIT_SET,-" "0,1" line.long 0x898 "IMNTRCR550,INTC-Monitor Control Register 550" hexmask.long.word 0x898 16.--31. 1. "KEYCODE,-" bitfld.long 0x898 7. "NUM1_EN,-" "0,1" bitfld.long 0x898 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x898 4. "CNT_RESET,-" "0,1" bitfld.long 0x898 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x898 1. "IMNTR_EN,-" "0,1" bitfld.long 0x898 0. "WAIT_SET,-" "0,1" line.long 0x89C "IMNTRCR551,INTC-Monitor Control Register 551" hexmask.long.word 0x89C 16.--31. 1. "KEYCODE,-" bitfld.long 0x89C 7. "NUM1_EN,-" "0,1" bitfld.long 0x89C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x89C 4. "CNT_RESET,-" "0,1" bitfld.long 0x89C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x89C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x89C 0. "WAIT_SET,-" "0,1" line.long 0x8A0 "IMNTRCR552,INTC-Monitor Control Register 552" hexmask.long.word 0x8A0 16.--31. 1. "KEYCODE,-" bitfld.long 0x8A0 7. "NUM1_EN,-" "0,1" bitfld.long 0x8A0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8A0 4. "CNT_RESET,-" "0,1" bitfld.long 0x8A0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8A0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8A0 0. "WAIT_SET,-" "0,1" line.long 0x8A4 "IMNTRCR553,INTC-Monitor Control Register 553" hexmask.long.word 0x8A4 16.--31. 1. "KEYCODE,-" bitfld.long 0x8A4 7. "NUM1_EN,-" "0,1" bitfld.long 0x8A4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8A4 4. "CNT_RESET,-" "0,1" bitfld.long 0x8A4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8A4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8A4 0. "WAIT_SET,-" "0,1" line.long 0x8A8 "IMNTRCR554,INTC-Monitor Control Register 554" hexmask.long.word 0x8A8 16.--31. 1. "KEYCODE,-" bitfld.long 0x8A8 7. "NUM1_EN,-" "0,1" bitfld.long 0x8A8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8A8 4. "CNT_RESET,-" "0,1" bitfld.long 0x8A8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8A8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8A8 0. "WAIT_SET,-" "0,1" line.long 0x8AC "IMNTRCR555,INTC-Monitor Control Register 555" hexmask.long.word 0x8AC 16.--31. 1. "KEYCODE,-" bitfld.long 0x8AC 7. "NUM1_EN,-" "0,1" bitfld.long 0x8AC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8AC 4. "CNT_RESET,-" "0,1" bitfld.long 0x8AC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8AC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8AC 0. "WAIT_SET,-" "0,1" line.long 0x8B0 "IMNTRCR556,INTC-Monitor Control Register 556" hexmask.long.word 0x8B0 16.--31. 1. "KEYCODE,-" bitfld.long 0x8B0 7. "NUM1_EN,-" "0,1" bitfld.long 0x8B0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8B0 4. "CNT_RESET,-" "0,1" bitfld.long 0x8B0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8B0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8B0 0. "WAIT_SET,-" "0,1" line.long 0x8B4 "IMNTRCR557,INTC-Monitor Control Register 557" hexmask.long.word 0x8B4 16.--31. 1. "KEYCODE,-" bitfld.long 0x8B4 7. "NUM1_EN,-" "0,1" bitfld.long 0x8B4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8B4 4. "CNT_RESET,-" "0,1" bitfld.long 0x8B4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8B4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8B4 0. "WAIT_SET,-" "0,1" line.long 0x8B8 "IMNTRCR558,INTC-Monitor Control Register 558" hexmask.long.word 0x8B8 16.--31. 1. "KEYCODE,-" bitfld.long 0x8B8 7. "NUM1_EN,-" "0,1" bitfld.long 0x8B8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8B8 4. "CNT_RESET,-" "0,1" bitfld.long 0x8B8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8B8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8B8 0. "WAIT_SET,-" "0,1" line.long 0x8BC "IMNTRCR559,INTC-Monitor Control Register 559" hexmask.long.word 0x8BC 16.--31. 1. "KEYCODE,-" bitfld.long 0x8BC 7. "NUM1_EN,-" "0,1" bitfld.long 0x8BC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8BC 4. "CNT_RESET,-" "0,1" bitfld.long 0x8BC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8BC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8BC 0. "WAIT_SET,-" "0,1" line.long 0x8C0 "IMNTRCR560,INTC-Monitor Control Register 560" hexmask.long.word 0x8C0 16.--31. 1. "KEYCODE,-" bitfld.long 0x8C0 7. "NUM1_EN,-" "0,1" bitfld.long 0x8C0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8C0 4. "CNT_RESET,-" "0,1" bitfld.long 0x8C0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8C0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8C0 0. "WAIT_SET,-" "0,1" line.long 0x8C4 "IMNTRCR561,INTC-Monitor Control Register 561" hexmask.long.word 0x8C4 16.--31. 1. "KEYCODE,-" bitfld.long 0x8C4 7. "NUM1_EN,-" "0,1" bitfld.long 0x8C4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8C4 4. "CNT_RESET,-" "0,1" bitfld.long 0x8C4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8C4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8C4 0. "WAIT_SET,-" "0,1" line.long 0x8C8 "IMNTRCR562,INTC-Monitor Control Register 562" hexmask.long.word 0x8C8 16.--31. 1. "KEYCODE,-" bitfld.long 0x8C8 7. "NUM1_EN,-" "0,1" bitfld.long 0x8C8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8C8 4. "CNT_RESET,-" "0,1" bitfld.long 0x8C8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8C8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8C8 0. "WAIT_SET,-" "0,1" line.long 0x8CC "IMNTRCR563,INTC-Monitor Control Register 563" hexmask.long.word 0x8CC 16.--31. 1. "KEYCODE,-" bitfld.long 0x8CC 7. "NUM1_EN,-" "0,1" bitfld.long 0x8CC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8CC 4. "CNT_RESET,-" "0,1" bitfld.long 0x8CC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8CC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8CC 0. "WAIT_SET,-" "0,1" line.long 0x8D0 "IMNTRCR564,INTC-Monitor Control Register 564" hexmask.long.word 0x8D0 16.--31. 1. "KEYCODE,-" bitfld.long 0x8D0 7. "NUM1_EN,-" "0,1" bitfld.long 0x8D0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8D0 4. "CNT_RESET,-" "0,1" bitfld.long 0x8D0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8D0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8D0 0. "WAIT_SET,-" "0,1" line.long 0x8D4 "IMNTRCR565,INTC-Monitor Control Register 565" hexmask.long.word 0x8D4 16.--31. 1. "KEYCODE,-" bitfld.long 0x8D4 7. "NUM1_EN,-" "0,1" bitfld.long 0x8D4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8D4 4. "CNT_RESET,-" "0,1" bitfld.long 0x8D4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8D4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8D4 0. "WAIT_SET,-" "0,1" line.long 0x8D8 "IMNTRCR566,INTC-Monitor Control Register 566" hexmask.long.word 0x8D8 16.--31. 1. "KEYCODE,-" bitfld.long 0x8D8 7. "NUM1_EN,-" "0,1" bitfld.long 0x8D8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8D8 4. "CNT_RESET,-" "0,1" bitfld.long 0x8D8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8D8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8D8 0. "WAIT_SET,-" "0,1" line.long 0x8DC "IMNTRCR567,INTC-Monitor Control Register 567" hexmask.long.word 0x8DC 16.--31. 1. "KEYCODE,-" bitfld.long 0x8DC 7. "NUM1_EN,-" "0,1" bitfld.long 0x8DC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8DC 4. "CNT_RESET,-" "0,1" bitfld.long 0x8DC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8DC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8DC 0. "WAIT_SET,-" "0,1" line.long 0x8E0 "IMNTRCR568,INTC-Monitor Control Register 568" hexmask.long.word 0x8E0 16.--31. 1. "KEYCODE,-" bitfld.long 0x8E0 7. "NUM1_EN,-" "0,1" bitfld.long 0x8E0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8E0 4. "CNT_RESET,-" "0,1" bitfld.long 0x8E0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8E0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8E0 0. "WAIT_SET,-" "0,1" line.long 0x8E4 "IMNTRCR569,INTC-Monitor Control Register 569" hexmask.long.word 0x8E4 16.--31. 1. "KEYCODE,-" bitfld.long 0x8E4 7. "NUM1_EN,-" "0,1" bitfld.long 0x8E4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8E4 4. "CNT_RESET,-" "0,1" bitfld.long 0x8E4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8E4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8E4 0. "WAIT_SET,-" "0,1" line.long 0x8E8 "IMNTRCR570,INTC-Monitor Control Register 570" hexmask.long.word 0x8E8 16.--31. 1. "KEYCODE,-" bitfld.long 0x8E8 7. "NUM1_EN,-" "0,1" bitfld.long 0x8E8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8E8 4. "CNT_RESET,-" "0,1" bitfld.long 0x8E8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8E8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8E8 0. "WAIT_SET,-" "0,1" line.long 0x8EC "IMNTRCR571,INTC-Monitor Control Register 571" hexmask.long.word 0x8EC 16.--31. 1. "KEYCODE,-" bitfld.long 0x8EC 7. "NUM1_EN,-" "0,1" bitfld.long 0x8EC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8EC 4. "CNT_RESET,-" "0,1" bitfld.long 0x8EC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8EC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8EC 0. "WAIT_SET,-" "0,1" line.long 0x8F0 "IMNTRCR572,INTC-Monitor Control Register 572" hexmask.long.word 0x8F0 16.--31. 1. "KEYCODE,-" bitfld.long 0x8F0 7. "NUM1_EN,-" "0,1" bitfld.long 0x8F0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8F0 4. "CNT_RESET,-" "0,1" bitfld.long 0x8F0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8F0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8F0 0. "WAIT_SET,-" "0,1" line.long 0x8F4 "IMNTRCR573,INTC-Monitor Control Register 573" hexmask.long.word 0x8F4 16.--31. 1. "KEYCODE,-" bitfld.long 0x8F4 7. "NUM1_EN,-" "0,1" bitfld.long 0x8F4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8F4 4. "CNT_RESET,-" "0,1" bitfld.long 0x8F4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8F4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8F4 0. "WAIT_SET,-" "0,1" line.long 0x8F8 "IMNTRCR574,INTC-Monitor Control Register 574" hexmask.long.word 0x8F8 16.--31. 1. "KEYCODE,-" bitfld.long 0x8F8 7. "NUM1_EN,-" "0,1" bitfld.long 0x8F8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8F8 4. "CNT_RESET,-" "0,1" bitfld.long 0x8F8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8F8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8F8 0. "WAIT_SET,-" "0,1" line.long 0x8FC "IMNTRCR575,INTC-Monitor Control Register 575" hexmask.long.word 0x8FC 16.--31. 1. "KEYCODE,-" bitfld.long 0x8FC 7. "NUM1_EN,-" "0,1" bitfld.long 0x8FC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x8FC 4. "CNT_RESET,-" "0,1" bitfld.long 0x8FC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x8FC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x8FC 0. "WAIT_SET,-" "0,1" line.long 0x900 "IMNTRCR576,INTC-Monitor Control Register 576" hexmask.long.word 0x900 16.--31. 1. "KEYCODE,-" bitfld.long 0x900 7. "NUM1_EN,-" "0,1" bitfld.long 0x900 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x900 4. "CNT_RESET,-" "0,1" bitfld.long 0x900 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x900 1. "IMNTR_EN,-" "0,1" bitfld.long 0x900 0. "WAIT_SET,-" "0,1" line.long 0x904 "IMNTRCR577,INTC-Monitor Control Register 577" hexmask.long.word 0x904 16.--31. 1. "KEYCODE,-" bitfld.long 0x904 7. "NUM1_EN,-" "0,1" bitfld.long 0x904 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x904 4. "CNT_RESET,-" "0,1" bitfld.long 0x904 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x904 1. "IMNTR_EN,-" "0,1" bitfld.long 0x904 0. "WAIT_SET,-" "0,1" line.long 0x908 "IMNTRCR578,INTC-Monitor Control Register 578" hexmask.long.word 0x908 16.--31. 1. "KEYCODE,-" bitfld.long 0x908 7. "NUM1_EN,-" "0,1" bitfld.long 0x908 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x908 4. "CNT_RESET,-" "0,1" bitfld.long 0x908 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x908 1. "IMNTR_EN,-" "0,1" bitfld.long 0x908 0. "WAIT_SET,-" "0,1" line.long 0x90C "IMNTRCR579,INTC-Monitor Control Register 579" hexmask.long.word 0x90C 16.--31. 1. "KEYCODE,-" bitfld.long 0x90C 7. "NUM1_EN,-" "0,1" bitfld.long 0x90C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x90C 4. "CNT_RESET,-" "0,1" bitfld.long 0x90C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x90C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x90C 0. "WAIT_SET,-" "0,1" line.long 0x910 "IMNTRCR580,INTC-Monitor Control Register 580" hexmask.long.word 0x910 16.--31. 1. "KEYCODE,-" bitfld.long 0x910 7. "NUM1_EN,-" "0,1" bitfld.long 0x910 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x910 4. "CNT_RESET,-" "0,1" bitfld.long 0x910 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x910 1. "IMNTR_EN,-" "0,1" bitfld.long 0x910 0. "WAIT_SET,-" "0,1" line.long 0x914 "IMNTRCR581,INTC-Monitor Control Register 581" hexmask.long.word 0x914 16.--31. 1. "KEYCODE,-" bitfld.long 0x914 7. "NUM1_EN,-" "0,1" bitfld.long 0x914 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x914 4. "CNT_RESET,-" "0,1" bitfld.long 0x914 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x914 1. "IMNTR_EN,-" "0,1" bitfld.long 0x914 0. "WAIT_SET,-" "0,1" line.long 0x918 "IMNTRCR582,INTC-Monitor Control Register 582" hexmask.long.word 0x918 16.--31. 1. "KEYCODE,-" bitfld.long 0x918 7. "NUM1_EN,-" "0,1" bitfld.long 0x918 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x918 4. "CNT_RESET,-" "0,1" bitfld.long 0x918 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x918 1. "IMNTR_EN,-" "0,1" bitfld.long 0x918 0. "WAIT_SET,-" "0,1" line.long 0x91C "IMNTRCR583,INTC-Monitor Control Register 583" hexmask.long.word 0x91C 16.--31. 1. "KEYCODE,-" bitfld.long 0x91C 7. "NUM1_EN,-" "0,1" bitfld.long 0x91C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x91C 4. "CNT_RESET,-" "0,1" bitfld.long 0x91C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x91C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x91C 0. "WAIT_SET,-" "0,1" line.long 0x920 "IMNTRCR584,INTC-Monitor Control Register 584" hexmask.long.word 0x920 16.--31. 1. "KEYCODE,-" bitfld.long 0x920 7. "NUM1_EN,-" "0,1" bitfld.long 0x920 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x920 4. "CNT_RESET,-" "0,1" bitfld.long 0x920 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x920 1. "IMNTR_EN,-" "0,1" bitfld.long 0x920 0. "WAIT_SET,-" "0,1" line.long 0x924 "IMNTRCR585,INTC-Monitor Control Register 585" hexmask.long.word 0x924 16.--31. 1. "KEYCODE,-" bitfld.long 0x924 7. "NUM1_EN,-" "0,1" bitfld.long 0x924 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x924 4. "CNT_RESET,-" "0,1" bitfld.long 0x924 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x924 1. "IMNTR_EN,-" "0,1" bitfld.long 0x924 0. "WAIT_SET,-" "0,1" line.long 0x928 "IMNTRCR586,INTC-Monitor Control Register 586" hexmask.long.word 0x928 16.--31. 1. "KEYCODE,-" bitfld.long 0x928 7. "NUM1_EN,-" "0,1" bitfld.long 0x928 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x928 4. "CNT_RESET,-" "0,1" bitfld.long 0x928 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x928 1. "IMNTR_EN,-" "0,1" bitfld.long 0x928 0. "WAIT_SET,-" "0,1" line.long 0x92C "IMNTRCR587,INTC-Monitor Control Register 587" hexmask.long.word 0x92C 16.--31. 1. "KEYCODE,-" bitfld.long 0x92C 7. "NUM1_EN,-" "0,1" bitfld.long 0x92C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x92C 4. "CNT_RESET,-" "0,1" bitfld.long 0x92C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x92C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x92C 0. "WAIT_SET,-" "0,1" line.long 0x930 "IMNTRCR588,INTC-Monitor Control Register 588" hexmask.long.word 0x930 16.--31. 1. "KEYCODE,-" bitfld.long 0x930 7. "NUM1_EN,-" "0,1" bitfld.long 0x930 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x930 4. "CNT_RESET,-" "0,1" bitfld.long 0x930 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x930 1. "IMNTR_EN,-" "0,1" bitfld.long 0x930 0. "WAIT_SET,-" "0,1" line.long 0x934 "IMNTRCR589,INTC-Monitor Control Register 589" hexmask.long.word 0x934 16.--31. 1. "KEYCODE,-" bitfld.long 0x934 7. "NUM1_EN,-" "0,1" bitfld.long 0x934 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x934 4. "CNT_RESET,-" "0,1" bitfld.long 0x934 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x934 1. "IMNTR_EN,-" "0,1" bitfld.long 0x934 0. "WAIT_SET,-" "0,1" line.long 0x938 "IMNTRCR590,INTC-Monitor Control Register 590" hexmask.long.word 0x938 16.--31. 1. "KEYCODE,-" bitfld.long 0x938 7. "NUM1_EN,-" "0,1" bitfld.long 0x938 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x938 4. "CNT_RESET,-" "0,1" bitfld.long 0x938 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x938 1. "IMNTR_EN,-" "0,1" bitfld.long 0x938 0. "WAIT_SET,-" "0,1" line.long 0x93C "IMNTRCR591,INTC-Monitor Control Register 591" hexmask.long.word 0x93C 16.--31. 1. "KEYCODE,-" bitfld.long 0x93C 7. "NUM1_EN,-" "0,1" bitfld.long 0x93C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x93C 4. "CNT_RESET,-" "0,1" bitfld.long 0x93C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x93C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x93C 0. "WAIT_SET,-" "0,1" line.long 0x940 "IMNTRCR592,INTC-Monitor Control Register 592" hexmask.long.word 0x940 16.--31. 1. "KEYCODE,-" bitfld.long 0x940 7. "NUM1_EN,-" "0,1" bitfld.long 0x940 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x940 4. "CNT_RESET,-" "0,1" bitfld.long 0x940 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x940 1. "IMNTR_EN,-" "0,1" bitfld.long 0x940 0. "WAIT_SET,-" "0,1" line.long 0x944 "IMNTRCR593,INTC-Monitor Control Register 593" hexmask.long.word 0x944 16.--31. 1. "KEYCODE,-" bitfld.long 0x944 7. "NUM1_EN,-" "0,1" bitfld.long 0x944 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x944 4. "CNT_RESET,-" "0,1" bitfld.long 0x944 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x944 1. "IMNTR_EN,-" "0,1" bitfld.long 0x944 0. "WAIT_SET,-" "0,1" line.long 0x948 "IMNTRCR594,INTC-Monitor Control Register 594" hexmask.long.word 0x948 16.--31. 1. "KEYCODE,-" bitfld.long 0x948 7. "NUM1_EN,-" "0,1" bitfld.long 0x948 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x948 4. "CNT_RESET,-" "0,1" bitfld.long 0x948 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x948 1. "IMNTR_EN,-" "0,1" bitfld.long 0x948 0. "WAIT_SET,-" "0,1" line.long 0x94C "IMNTRCR595,INTC-Monitor Control Register 595" hexmask.long.word 0x94C 16.--31. 1. "KEYCODE,-" bitfld.long 0x94C 7. "NUM1_EN,-" "0,1" bitfld.long 0x94C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x94C 4. "CNT_RESET,-" "0,1" bitfld.long 0x94C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x94C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x94C 0. "WAIT_SET,-" "0,1" line.long 0x950 "IMNTRCR596,INTC-Monitor Control Register 596" hexmask.long.word 0x950 16.--31. 1. "KEYCODE,-" bitfld.long 0x950 7. "NUM1_EN,-" "0,1" bitfld.long 0x950 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x950 4. "CNT_RESET,-" "0,1" bitfld.long 0x950 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x950 1. "IMNTR_EN,-" "0,1" bitfld.long 0x950 0. "WAIT_SET,-" "0,1" line.long 0x954 "IMNTRCR597,INTC-Monitor Control Register 597" hexmask.long.word 0x954 16.--31. 1. "KEYCODE,-" bitfld.long 0x954 7. "NUM1_EN,-" "0,1" bitfld.long 0x954 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x954 4. "CNT_RESET,-" "0,1" bitfld.long 0x954 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x954 1. "IMNTR_EN,-" "0,1" bitfld.long 0x954 0. "WAIT_SET,-" "0,1" line.long 0x958 "IMNTRCR598,INTC-Monitor Control Register 598" hexmask.long.word 0x958 16.--31. 1. "KEYCODE,-" bitfld.long 0x958 7. "NUM1_EN,-" "0,1" bitfld.long 0x958 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x958 4. "CNT_RESET,-" "0,1" bitfld.long 0x958 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x958 1. "IMNTR_EN,-" "0,1" bitfld.long 0x958 0. "WAIT_SET,-" "0,1" line.long 0x95C "IMNTRCR599,INTC-Monitor Control Register 599" hexmask.long.word 0x95C 16.--31. 1. "KEYCODE,-" bitfld.long 0x95C 7. "NUM1_EN,-" "0,1" bitfld.long 0x95C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x95C 4. "CNT_RESET,-" "0,1" bitfld.long 0x95C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x95C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x95C 0. "WAIT_SET,-" "0,1" line.long 0x960 "IMNTRCR600,INTC-Monitor Control Register 600" hexmask.long.word 0x960 16.--31. 1. "KEYCODE,-" bitfld.long 0x960 7. "NUM1_EN,-" "0,1" bitfld.long 0x960 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x960 4. "CNT_RESET,-" "0,1" bitfld.long 0x960 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x960 1. "IMNTR_EN,-" "0,1" bitfld.long 0x960 0. "WAIT_SET,-" "0,1" line.long 0x964 "IMNTRCR601,INTC-Monitor Control Register 601" hexmask.long.word 0x964 16.--31. 1. "KEYCODE,-" bitfld.long 0x964 7. "NUM1_EN,-" "0,1" bitfld.long 0x964 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x964 4. "CNT_RESET,-" "0,1" bitfld.long 0x964 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x964 1. "IMNTR_EN,-" "0,1" bitfld.long 0x964 0. "WAIT_SET,-" "0,1" line.long 0x968 "IMNTRCR602,INTC-Monitor Control Register 602" hexmask.long.word 0x968 16.--31. 1. "KEYCODE,-" bitfld.long 0x968 7. "NUM1_EN,-" "0,1" bitfld.long 0x968 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x968 4. "CNT_RESET,-" "0,1" bitfld.long 0x968 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x968 1. "IMNTR_EN,-" "0,1" bitfld.long 0x968 0. "WAIT_SET,-" "0,1" line.long 0x96C "IMNTRCR603,INTC-Monitor Control Register 603" hexmask.long.word 0x96C 16.--31. 1. "KEYCODE,-" bitfld.long 0x96C 7. "NUM1_EN,-" "0,1" bitfld.long 0x96C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x96C 4. "CNT_RESET,-" "0,1" bitfld.long 0x96C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x96C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x96C 0. "WAIT_SET,-" "0,1" line.long 0x970 "IMNTRCR604,INTC-Monitor Control Register 604" hexmask.long.word 0x970 16.--31. 1. "KEYCODE,-" bitfld.long 0x970 7. "NUM1_EN,-" "0,1" bitfld.long 0x970 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x970 4. "CNT_RESET,-" "0,1" bitfld.long 0x970 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x970 1. "IMNTR_EN,-" "0,1" bitfld.long 0x970 0. "WAIT_SET,-" "0,1" line.long 0x974 "IMNTRCR605,INTC-Monitor Control Register 605" hexmask.long.word 0x974 16.--31. 1. "KEYCODE,-" bitfld.long 0x974 7. "NUM1_EN,-" "0,1" bitfld.long 0x974 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x974 4. "CNT_RESET,-" "0,1" bitfld.long 0x974 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x974 1. "IMNTR_EN,-" "0,1" bitfld.long 0x974 0. "WAIT_SET,-" "0,1" line.long 0x978 "IMNTRCR606,INTC-Monitor Control Register 606" hexmask.long.word 0x978 16.--31. 1. "KEYCODE,-" bitfld.long 0x978 7. "NUM1_EN,-" "0,1" bitfld.long 0x978 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x978 4. "CNT_RESET,-" "0,1" bitfld.long 0x978 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x978 1. "IMNTR_EN,-" "0,1" bitfld.long 0x978 0. "WAIT_SET,-" "0,1" line.long 0x97C "IMNTRCR607,INTC-Monitor Control Register 607" hexmask.long.word 0x97C 16.--31. 1. "KEYCODE,-" bitfld.long 0x97C 7. "NUM1_EN,-" "0,1" bitfld.long 0x97C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x97C 4. "CNT_RESET,-" "0,1" bitfld.long 0x97C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x97C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x97C 0. "WAIT_SET,-" "0,1" line.long 0x980 "IMNTRCR608,INTC-Monitor Control Register 608" hexmask.long.word 0x980 16.--31. 1. "KEYCODE,-" bitfld.long 0x980 7. "NUM1_EN,-" "0,1" bitfld.long 0x980 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x980 4. "CNT_RESET,-" "0,1" bitfld.long 0x980 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x980 1. "IMNTR_EN,-" "0,1" bitfld.long 0x980 0. "WAIT_SET,-" "0,1" line.long 0x984 "IMNTRCR609,INTC-Monitor Control Register 609" hexmask.long.word 0x984 16.--31. 1. "KEYCODE,-" bitfld.long 0x984 7. "NUM1_EN,-" "0,1" bitfld.long 0x984 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x984 4. "CNT_RESET,-" "0,1" bitfld.long 0x984 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x984 1. "IMNTR_EN,-" "0,1" bitfld.long 0x984 0. "WAIT_SET,-" "0,1" line.long 0x988 "IMNTRCR610,INTC-Monitor Control Register 610" hexmask.long.word 0x988 16.--31. 1. "KEYCODE,-" bitfld.long 0x988 7. "NUM1_EN,-" "0,1" bitfld.long 0x988 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x988 4. "CNT_RESET,-" "0,1" bitfld.long 0x988 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x988 1. "IMNTR_EN,-" "0,1" bitfld.long 0x988 0. "WAIT_SET,-" "0,1" line.long 0x98C "IMNTRCR611,INTC-Monitor Control Register 611" hexmask.long.word 0x98C 16.--31. 1. "KEYCODE,-" bitfld.long 0x98C 7. "NUM1_EN,-" "0,1" bitfld.long 0x98C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x98C 4. "CNT_RESET,-" "0,1" bitfld.long 0x98C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x98C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x98C 0. "WAIT_SET,-" "0,1" line.long 0x990 "IMNTRCR612,INTC-Monitor Control Register 612" hexmask.long.word 0x990 16.--31. 1. "KEYCODE,-" bitfld.long 0x990 7. "NUM1_EN,-" "0,1" bitfld.long 0x990 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x990 4. "CNT_RESET,-" "0,1" bitfld.long 0x990 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x990 1. "IMNTR_EN,-" "0,1" bitfld.long 0x990 0. "WAIT_SET,-" "0,1" line.long 0x994 "IMNTRCR613,INTC-Monitor Control Register 613" hexmask.long.word 0x994 16.--31. 1. "KEYCODE,-" bitfld.long 0x994 7. "NUM1_EN,-" "0,1" bitfld.long 0x994 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x994 4. "CNT_RESET,-" "0,1" bitfld.long 0x994 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x994 1. "IMNTR_EN,-" "0,1" bitfld.long 0x994 0. "WAIT_SET,-" "0,1" line.long 0x998 "IMNTRCR614,INTC-Monitor Control Register 614" hexmask.long.word 0x998 16.--31. 1. "KEYCODE,-" bitfld.long 0x998 7. "NUM1_EN,-" "0,1" bitfld.long 0x998 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x998 4. "CNT_RESET,-" "0,1" bitfld.long 0x998 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x998 1. "IMNTR_EN,-" "0,1" bitfld.long 0x998 0. "WAIT_SET,-" "0,1" line.long 0x99C "IMNTRCR615,INTC-Monitor Control Register 615" hexmask.long.word 0x99C 16.--31. 1. "KEYCODE,-" bitfld.long 0x99C 7. "NUM1_EN,-" "0,1" bitfld.long 0x99C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x99C 4. "CNT_RESET,-" "0,1" bitfld.long 0x99C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x99C 1. "IMNTR_EN,-" "0,1" bitfld.long 0x99C 0. "WAIT_SET,-" "0,1" line.long 0x9A0 "IMNTRCR616,INTC-Monitor Control Register 616" hexmask.long.word 0x9A0 16.--31. 1. "KEYCODE,-" bitfld.long 0x9A0 7. "NUM1_EN,-" "0,1" bitfld.long 0x9A0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9A0 4. "CNT_RESET,-" "0,1" bitfld.long 0x9A0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9A0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9A0 0. "WAIT_SET,-" "0,1" line.long 0x9A4 "IMNTRCR617,INTC-Monitor Control Register 617" hexmask.long.word 0x9A4 16.--31. 1. "KEYCODE,-" bitfld.long 0x9A4 7. "NUM1_EN,-" "0,1" bitfld.long 0x9A4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9A4 4. "CNT_RESET,-" "0,1" bitfld.long 0x9A4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9A4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9A4 0. "WAIT_SET,-" "0,1" line.long 0x9A8 "IMNTRCR618,INTC-Monitor Control Register 618" hexmask.long.word 0x9A8 16.--31. 1. "KEYCODE,-" bitfld.long 0x9A8 7. "NUM1_EN,-" "0,1" bitfld.long 0x9A8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9A8 4. "CNT_RESET,-" "0,1" bitfld.long 0x9A8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9A8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9A8 0. "WAIT_SET,-" "0,1" line.long 0x9AC "IMNTRCR619,INTC-Monitor Control Register 619" hexmask.long.word 0x9AC 16.--31. 1. "KEYCODE,-" bitfld.long 0x9AC 7. "NUM1_EN,-" "0,1" bitfld.long 0x9AC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9AC 4. "CNT_RESET,-" "0,1" bitfld.long 0x9AC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9AC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9AC 0. "WAIT_SET,-" "0,1" line.long 0x9B0 "IMNTRCR620,INTC-Monitor Control Register 620" hexmask.long.word 0x9B0 16.--31. 1. "KEYCODE,-" bitfld.long 0x9B0 7. "NUM1_EN,-" "0,1" bitfld.long 0x9B0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9B0 4. "CNT_RESET,-" "0,1" bitfld.long 0x9B0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9B0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9B0 0. "WAIT_SET,-" "0,1" line.long 0x9B4 "IMNTRCR621,INTC-Monitor Control Register 621" hexmask.long.word 0x9B4 16.--31. 1. "KEYCODE,-" bitfld.long 0x9B4 7. "NUM1_EN,-" "0,1" bitfld.long 0x9B4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9B4 4. "CNT_RESET,-" "0,1" bitfld.long 0x9B4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9B4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9B4 0. "WAIT_SET,-" "0,1" line.long 0x9B8 "IMNTRCR622,INTC-Monitor Control Register 622" hexmask.long.word 0x9B8 16.--31. 1. "KEYCODE,-" bitfld.long 0x9B8 7. "NUM1_EN,-" "0,1" bitfld.long 0x9B8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9B8 4. "CNT_RESET,-" "0,1" bitfld.long 0x9B8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9B8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9B8 0. "WAIT_SET,-" "0,1" line.long 0x9BC "IMNTRCR623,INTC-Monitor Control Register 623" hexmask.long.word 0x9BC 16.--31. 1. "KEYCODE,-" bitfld.long 0x9BC 7. "NUM1_EN,-" "0,1" bitfld.long 0x9BC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9BC 4. "CNT_RESET,-" "0,1" bitfld.long 0x9BC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9BC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9BC 0. "WAIT_SET,-" "0,1" line.long 0x9C0 "IMNTRCR624,INTC-Monitor Control Register 624" hexmask.long.word 0x9C0 16.--31. 1. "KEYCODE,-" bitfld.long 0x9C0 7. "NUM1_EN,-" "0,1" bitfld.long 0x9C0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9C0 4. "CNT_RESET,-" "0,1" bitfld.long 0x9C0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9C0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9C0 0. "WAIT_SET,-" "0,1" line.long 0x9C4 "IMNTRCR625,INTC-Monitor Control Register 625" hexmask.long.word 0x9C4 16.--31. 1. "KEYCODE,-" bitfld.long 0x9C4 7. "NUM1_EN,-" "0,1" bitfld.long 0x9C4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9C4 4. "CNT_RESET,-" "0,1" bitfld.long 0x9C4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9C4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9C4 0. "WAIT_SET,-" "0,1" line.long 0x9C8 "IMNTRCR626,INTC-Monitor Control Register 626" hexmask.long.word 0x9C8 16.--31. 1. "KEYCODE,-" bitfld.long 0x9C8 7. "NUM1_EN,-" "0,1" bitfld.long 0x9C8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9C8 4. "CNT_RESET,-" "0,1" bitfld.long 0x9C8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9C8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9C8 0. "WAIT_SET,-" "0,1" line.long 0x9CC "IMNTRCR627,INTC-Monitor Control Register 627" hexmask.long.word 0x9CC 16.--31. 1. "KEYCODE,-" bitfld.long 0x9CC 7. "NUM1_EN,-" "0,1" bitfld.long 0x9CC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9CC 4. "CNT_RESET,-" "0,1" bitfld.long 0x9CC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9CC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9CC 0. "WAIT_SET,-" "0,1" line.long 0x9D0 "IMNTRCR628,INTC-Monitor Control Register 628" hexmask.long.word 0x9D0 16.--31. 1. "KEYCODE,-" bitfld.long 0x9D0 7. "NUM1_EN,-" "0,1" bitfld.long 0x9D0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9D0 4. "CNT_RESET,-" "0,1" bitfld.long 0x9D0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9D0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9D0 0. "WAIT_SET,-" "0,1" line.long 0x9D4 "IMNTRCR629,INTC-Monitor Control Register 629" hexmask.long.word 0x9D4 16.--31. 1. "KEYCODE,-" bitfld.long 0x9D4 7. "NUM1_EN,-" "0,1" bitfld.long 0x9D4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9D4 4. "CNT_RESET,-" "0,1" bitfld.long 0x9D4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9D4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9D4 0. "WAIT_SET,-" "0,1" line.long 0x9D8 "IMNTRCR630,INTC-Monitor Control Register 630" hexmask.long.word 0x9D8 16.--31. 1. "KEYCODE,-" bitfld.long 0x9D8 7. "NUM1_EN,-" "0,1" bitfld.long 0x9D8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9D8 4. "CNT_RESET,-" "0,1" bitfld.long 0x9D8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9D8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9D8 0. "WAIT_SET,-" "0,1" line.long 0x9DC "IMNTRCR631,INTC-Monitor Control Register 631" hexmask.long.word 0x9DC 16.--31. 1. "KEYCODE,-" bitfld.long 0x9DC 7. "NUM1_EN,-" "0,1" bitfld.long 0x9DC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9DC 4. "CNT_RESET,-" "0,1" bitfld.long 0x9DC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9DC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9DC 0. "WAIT_SET,-" "0,1" line.long 0x9E0 "IMNTRCR632,INTC-Monitor Control Register 632" hexmask.long.word 0x9E0 16.--31. 1. "KEYCODE,-" bitfld.long 0x9E0 7. "NUM1_EN,-" "0,1" bitfld.long 0x9E0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9E0 4. "CNT_RESET,-" "0,1" bitfld.long 0x9E0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9E0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9E0 0. "WAIT_SET,-" "0,1" line.long 0x9E4 "IMNTRCR633,INTC-Monitor Control Register 633" hexmask.long.word 0x9E4 16.--31. 1. "KEYCODE,-" bitfld.long 0x9E4 7. "NUM1_EN,-" "0,1" bitfld.long 0x9E4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9E4 4. "CNT_RESET,-" "0,1" bitfld.long 0x9E4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9E4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9E4 0. "WAIT_SET,-" "0,1" line.long 0x9E8 "IMNTRCR634,INTC-Monitor Control Register 634" hexmask.long.word 0x9E8 16.--31. 1. "KEYCODE,-" bitfld.long 0x9E8 7. "NUM1_EN,-" "0,1" bitfld.long 0x9E8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9E8 4. "CNT_RESET,-" "0,1" bitfld.long 0x9E8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9E8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9E8 0. "WAIT_SET,-" "0,1" line.long 0x9EC "IMNTRCR635,INTC-Monitor Control Register 635" hexmask.long.word 0x9EC 16.--31. 1. "KEYCODE,-" bitfld.long 0x9EC 7. "NUM1_EN,-" "0,1" bitfld.long 0x9EC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9EC 4. "CNT_RESET,-" "0,1" bitfld.long 0x9EC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9EC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9EC 0. "WAIT_SET,-" "0,1" line.long 0x9F0 "IMNTRCR636,INTC-Monitor Control Register 636" hexmask.long.word 0x9F0 16.--31. 1. "KEYCODE,-" bitfld.long 0x9F0 7. "NUM1_EN,-" "0,1" bitfld.long 0x9F0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9F0 4. "CNT_RESET,-" "0,1" bitfld.long 0x9F0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9F0 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9F0 0. "WAIT_SET,-" "0,1" line.long 0x9F4 "IMNTRCR637,INTC-Monitor Control Register 637" hexmask.long.word 0x9F4 16.--31. 1. "KEYCODE,-" bitfld.long 0x9F4 7. "NUM1_EN,-" "0,1" bitfld.long 0x9F4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9F4 4. "CNT_RESET,-" "0,1" bitfld.long 0x9F4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9F4 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9F4 0. "WAIT_SET,-" "0,1" line.long 0x9F8 "IMNTRCR638,INTC-Monitor Control Register 638" hexmask.long.word 0x9F8 16.--31. 1. "KEYCODE,-" bitfld.long 0x9F8 7. "NUM1_EN,-" "0,1" bitfld.long 0x9F8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9F8 4. "CNT_RESET,-" "0,1" bitfld.long 0x9F8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9F8 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9F8 0. "WAIT_SET,-" "0,1" line.long 0x9FC "IMNTRCR639,INTC-Monitor Control Register 639" hexmask.long.word 0x9FC 16.--31. 1. "KEYCODE,-" bitfld.long 0x9FC 7. "NUM1_EN,-" "0,1" bitfld.long 0x9FC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0x9FC 4. "CNT_RESET,-" "0,1" bitfld.long 0x9FC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0x9FC 1. "IMNTR_EN,-" "0,1" bitfld.long 0x9FC 0. "WAIT_SET,-" "0,1" line.long 0xA00 "IMNTRCR640,INTC-Monitor Control Register 640" hexmask.long.word 0xA00 16.--31. 1. "KEYCODE,-" bitfld.long 0xA00 7. "NUM1_EN,-" "0,1" bitfld.long 0xA00 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA00 4. "CNT_RESET,-" "0,1" bitfld.long 0xA00 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA00 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA00 0. "WAIT_SET,-" "0,1" line.long 0xA04 "IMNTRCR641,INTC-Monitor Control Register 641" hexmask.long.word 0xA04 16.--31. 1. "KEYCODE,-" bitfld.long 0xA04 7. "NUM1_EN,-" "0,1" bitfld.long 0xA04 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA04 4. "CNT_RESET,-" "0,1" bitfld.long 0xA04 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA04 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA04 0. "WAIT_SET,-" "0,1" line.long 0xA08 "IMNTRCR642,INTC-Monitor Control Register 642" hexmask.long.word 0xA08 16.--31. 1. "KEYCODE,-" bitfld.long 0xA08 7. "NUM1_EN,-" "0,1" bitfld.long 0xA08 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA08 4. "CNT_RESET,-" "0,1" bitfld.long 0xA08 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA08 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA08 0. "WAIT_SET,-" "0,1" line.long 0xA0C "IMNTRCR643,INTC-Monitor Control Register 643" hexmask.long.word 0xA0C 16.--31. 1. "KEYCODE,-" bitfld.long 0xA0C 7. "NUM1_EN,-" "0,1" bitfld.long 0xA0C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA0C 4. "CNT_RESET,-" "0,1" bitfld.long 0xA0C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA0C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA0C 0. "WAIT_SET,-" "0,1" line.long 0xA10 "IMNTRCR644,INTC-Monitor Control Register 644" hexmask.long.word 0xA10 16.--31. 1. "KEYCODE,-" bitfld.long 0xA10 7. "NUM1_EN,-" "0,1" bitfld.long 0xA10 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA10 4. "CNT_RESET,-" "0,1" bitfld.long 0xA10 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA10 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA10 0. "WAIT_SET,-" "0,1" line.long 0xA14 "IMNTRCR645,INTC-Monitor Control Register 645" hexmask.long.word 0xA14 16.--31. 1. "KEYCODE,-" bitfld.long 0xA14 7. "NUM1_EN,-" "0,1" bitfld.long 0xA14 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA14 4. "CNT_RESET,-" "0,1" bitfld.long 0xA14 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA14 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA14 0. "WAIT_SET,-" "0,1" line.long 0xA18 "IMNTRCR646,INTC-Monitor Control Register 646" hexmask.long.word 0xA18 16.--31. 1. "KEYCODE,-" bitfld.long 0xA18 7. "NUM1_EN,-" "0,1" bitfld.long 0xA18 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA18 4. "CNT_RESET,-" "0,1" bitfld.long 0xA18 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA18 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA18 0. "WAIT_SET,-" "0,1" line.long 0xA1C "IMNTRCR647,INTC-Monitor Control Register 647" hexmask.long.word 0xA1C 16.--31. 1. "KEYCODE,-" bitfld.long 0xA1C 7. "NUM1_EN,-" "0,1" bitfld.long 0xA1C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA1C 4. "CNT_RESET,-" "0,1" bitfld.long 0xA1C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA1C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA1C 0. "WAIT_SET,-" "0,1" line.long 0xA20 "IMNTRCR648,INTC-Monitor Control Register 648" hexmask.long.word 0xA20 16.--31. 1. "KEYCODE,-" bitfld.long 0xA20 7. "NUM1_EN,-" "0,1" bitfld.long 0xA20 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA20 4. "CNT_RESET,-" "0,1" bitfld.long 0xA20 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA20 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA20 0. "WAIT_SET,-" "0,1" line.long 0xA24 "IMNTRCR649,INTC-Monitor Control Register 649" hexmask.long.word 0xA24 16.--31. 1. "KEYCODE,-" bitfld.long 0xA24 7. "NUM1_EN,-" "0,1" bitfld.long 0xA24 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA24 4. "CNT_RESET,-" "0,1" bitfld.long 0xA24 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA24 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA24 0. "WAIT_SET,-" "0,1" line.long 0xA28 "IMNTRCR650,INTC-Monitor Control Register 650" hexmask.long.word 0xA28 16.--31. 1. "KEYCODE,-" bitfld.long 0xA28 7. "NUM1_EN,-" "0,1" bitfld.long 0xA28 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA28 4. "CNT_RESET,-" "0,1" bitfld.long 0xA28 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA28 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA28 0. "WAIT_SET,-" "0,1" line.long 0xA2C "IMNTRCR651,INTC-Monitor Control Register 651" hexmask.long.word 0xA2C 16.--31. 1. "KEYCODE,-" bitfld.long 0xA2C 7. "NUM1_EN,-" "0,1" bitfld.long 0xA2C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA2C 4. "CNT_RESET,-" "0,1" bitfld.long 0xA2C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA2C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA2C 0. "WAIT_SET,-" "0,1" line.long 0xA30 "IMNTRCR652,INTC-Monitor Control Register 652" hexmask.long.word 0xA30 16.--31. 1. "KEYCODE,-" bitfld.long 0xA30 7. "NUM1_EN,-" "0,1" bitfld.long 0xA30 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA30 4. "CNT_RESET,-" "0,1" bitfld.long 0xA30 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA30 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA30 0. "WAIT_SET,-" "0,1" line.long 0xA34 "IMNTRCR653,INTC-Monitor Control Register 653" hexmask.long.word 0xA34 16.--31. 1. "KEYCODE,-" bitfld.long 0xA34 7. "NUM1_EN,-" "0,1" bitfld.long 0xA34 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA34 4. "CNT_RESET,-" "0,1" bitfld.long 0xA34 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA34 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA34 0. "WAIT_SET,-" "0,1" line.long 0xA38 "IMNTRCR654,INTC-Monitor Control Register 654" hexmask.long.word 0xA38 16.--31. 1. "KEYCODE,-" bitfld.long 0xA38 7. "NUM1_EN,-" "0,1" bitfld.long 0xA38 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA38 4. "CNT_RESET,-" "0,1" bitfld.long 0xA38 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA38 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA38 0. "WAIT_SET,-" "0,1" line.long 0xA3C "IMNTRCR655,INTC-Monitor Control Register 655" hexmask.long.word 0xA3C 16.--31. 1. "KEYCODE,-" bitfld.long 0xA3C 7. "NUM1_EN,-" "0,1" bitfld.long 0xA3C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA3C 4. "CNT_RESET,-" "0,1" bitfld.long 0xA3C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA3C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA3C 0. "WAIT_SET,-" "0,1" line.long 0xA40 "IMNTRCR656,INTC-Monitor Control Register 656" hexmask.long.word 0xA40 16.--31. 1. "KEYCODE,-" bitfld.long 0xA40 7. "NUM1_EN,-" "0,1" bitfld.long 0xA40 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA40 4. "CNT_RESET,-" "0,1" bitfld.long 0xA40 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA40 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA40 0. "WAIT_SET,-" "0,1" line.long 0xA44 "IMNTRCR657,INTC-Monitor Control Register 657" hexmask.long.word 0xA44 16.--31. 1. "KEYCODE,-" bitfld.long 0xA44 7. "NUM1_EN,-" "0,1" bitfld.long 0xA44 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA44 4. "CNT_RESET,-" "0,1" bitfld.long 0xA44 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA44 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA44 0. "WAIT_SET,-" "0,1" line.long 0xA48 "IMNTRCR658,INTC-Monitor Control Register 658" hexmask.long.word 0xA48 16.--31. 1. "KEYCODE,-" bitfld.long 0xA48 7. "NUM1_EN,-" "0,1" bitfld.long 0xA48 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA48 4. "CNT_RESET,-" "0,1" bitfld.long 0xA48 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA48 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA48 0. "WAIT_SET,-" "0,1" line.long 0xA4C "IMNTRCR659,INTC-Monitor Control Register 659" hexmask.long.word 0xA4C 16.--31. 1. "KEYCODE,-" bitfld.long 0xA4C 7. "NUM1_EN,-" "0,1" bitfld.long 0xA4C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA4C 4. "CNT_RESET,-" "0,1" bitfld.long 0xA4C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA4C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA4C 0. "WAIT_SET,-" "0,1" line.long 0xA50 "IMNTRCR660,INTC-Monitor Control Register 660" hexmask.long.word 0xA50 16.--31. 1. "KEYCODE,-" bitfld.long 0xA50 7. "NUM1_EN,-" "0,1" bitfld.long 0xA50 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA50 4. "CNT_RESET,-" "0,1" bitfld.long 0xA50 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA50 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA50 0. "WAIT_SET,-" "0,1" line.long 0xA54 "IMNTRCR661,INTC-Monitor Control Register 661" hexmask.long.word 0xA54 16.--31. 1. "KEYCODE,-" bitfld.long 0xA54 7. "NUM1_EN,-" "0,1" bitfld.long 0xA54 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA54 4. "CNT_RESET,-" "0,1" bitfld.long 0xA54 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA54 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA54 0. "WAIT_SET,-" "0,1" line.long 0xA58 "IMNTRCR662,INTC-Monitor Control Register 662" hexmask.long.word 0xA58 16.--31. 1. "KEYCODE,-" bitfld.long 0xA58 7. "NUM1_EN,-" "0,1" bitfld.long 0xA58 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA58 4. "CNT_RESET,-" "0,1" bitfld.long 0xA58 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA58 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA58 0. "WAIT_SET,-" "0,1" line.long 0xA5C "IMNTRCR663,INTC-Monitor Control Register 663" hexmask.long.word 0xA5C 16.--31. 1. "KEYCODE,-" bitfld.long 0xA5C 7. "NUM1_EN,-" "0,1" bitfld.long 0xA5C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA5C 4. "CNT_RESET,-" "0,1" bitfld.long 0xA5C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA5C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA5C 0. "WAIT_SET,-" "0,1" line.long 0xA60 "IMNTRCR664,INTC-Monitor Control Register 664" hexmask.long.word 0xA60 16.--31. 1. "KEYCODE,-" bitfld.long 0xA60 7. "NUM1_EN,-" "0,1" bitfld.long 0xA60 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA60 4. "CNT_RESET,-" "0,1" bitfld.long 0xA60 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA60 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA60 0. "WAIT_SET,-" "0,1" line.long 0xA64 "IMNTRCR665,INTC-Monitor Control Register 665" hexmask.long.word 0xA64 16.--31. 1. "KEYCODE,-" bitfld.long 0xA64 7. "NUM1_EN,-" "0,1" bitfld.long 0xA64 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA64 4. "CNT_RESET,-" "0,1" bitfld.long 0xA64 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA64 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA64 0. "WAIT_SET,-" "0,1" line.long 0xA68 "IMNTRCR666,INTC-Monitor Control Register 666" hexmask.long.word 0xA68 16.--31. 1. "KEYCODE,-" bitfld.long 0xA68 7. "NUM1_EN,-" "0,1" bitfld.long 0xA68 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA68 4. "CNT_RESET,-" "0,1" bitfld.long 0xA68 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA68 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA68 0. "WAIT_SET,-" "0,1" line.long 0xA6C "IMNTRCR667,INTC-Monitor Control Register 667" hexmask.long.word 0xA6C 16.--31. 1. "KEYCODE,-" bitfld.long 0xA6C 7. "NUM1_EN,-" "0,1" bitfld.long 0xA6C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA6C 4. "CNT_RESET,-" "0,1" bitfld.long 0xA6C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA6C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA6C 0. "WAIT_SET,-" "0,1" line.long 0xA70 "IMNTRCR668,INTC-Monitor Control Register 668" hexmask.long.word 0xA70 16.--31. 1. "KEYCODE,-" bitfld.long 0xA70 7. "NUM1_EN,-" "0,1" bitfld.long 0xA70 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA70 4. "CNT_RESET,-" "0,1" bitfld.long 0xA70 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA70 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA70 0. "WAIT_SET,-" "0,1" line.long 0xA74 "IMNTRCR669,INTC-Monitor Control Register 669" hexmask.long.word 0xA74 16.--31. 1. "KEYCODE,-" bitfld.long 0xA74 7. "NUM1_EN,-" "0,1" bitfld.long 0xA74 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA74 4. "CNT_RESET,-" "0,1" bitfld.long 0xA74 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA74 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA74 0. "WAIT_SET,-" "0,1" line.long 0xA78 "IMNTRCR670,INTC-Monitor Control Register 670" hexmask.long.word 0xA78 16.--31. 1. "KEYCODE,-" bitfld.long 0xA78 7. "NUM1_EN,-" "0,1" bitfld.long 0xA78 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA78 4. "CNT_RESET,-" "0,1" bitfld.long 0xA78 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA78 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA78 0. "WAIT_SET,-" "0,1" line.long 0xA7C "IMNTRCR671,INTC-Monitor Control Register 671" hexmask.long.word 0xA7C 16.--31. 1. "KEYCODE,-" bitfld.long 0xA7C 7. "NUM1_EN,-" "0,1" bitfld.long 0xA7C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA7C 4. "CNT_RESET,-" "0,1" bitfld.long 0xA7C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA7C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA7C 0. "WAIT_SET,-" "0,1" line.long 0xA80 "IMNTRCR672,INTC-Monitor Control Register 672" hexmask.long.word 0xA80 16.--31. 1. "KEYCODE,-" bitfld.long 0xA80 7. "NUM1_EN,-" "0,1" bitfld.long 0xA80 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA80 4. "CNT_RESET,-" "0,1" bitfld.long 0xA80 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA80 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA80 0. "WAIT_SET,-" "0,1" line.long 0xA84 "IMNTRCR673,INTC-Monitor Control Register 673" hexmask.long.word 0xA84 16.--31. 1. "KEYCODE,-" bitfld.long 0xA84 7. "NUM1_EN,-" "0,1" bitfld.long 0xA84 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA84 4. "CNT_RESET,-" "0,1" bitfld.long 0xA84 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA84 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA84 0. "WAIT_SET,-" "0,1" line.long 0xA88 "IMNTRCR674,INTC-Monitor Control Register 674" hexmask.long.word 0xA88 16.--31. 1. "KEYCODE,-" bitfld.long 0xA88 7. "NUM1_EN,-" "0,1" bitfld.long 0xA88 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA88 4. "CNT_RESET,-" "0,1" bitfld.long 0xA88 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA88 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA88 0. "WAIT_SET,-" "0,1" line.long 0xA8C "IMNTRCR675,INTC-Monitor Control Register 675" hexmask.long.word 0xA8C 16.--31. 1. "KEYCODE,-" bitfld.long 0xA8C 7. "NUM1_EN,-" "0,1" bitfld.long 0xA8C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA8C 4. "CNT_RESET,-" "0,1" bitfld.long 0xA8C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA8C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA8C 0. "WAIT_SET,-" "0,1" line.long 0xA90 "IMNTRCR676,INTC-Monitor Control Register 676" hexmask.long.word 0xA90 16.--31. 1. "KEYCODE,-" bitfld.long 0xA90 7. "NUM1_EN,-" "0,1" bitfld.long 0xA90 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA90 4. "CNT_RESET,-" "0,1" bitfld.long 0xA90 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA90 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA90 0. "WAIT_SET,-" "0,1" line.long 0xA94 "IMNTRCR677,INTC-Monitor Control Register 677" hexmask.long.word 0xA94 16.--31. 1. "KEYCODE,-" bitfld.long 0xA94 7. "NUM1_EN,-" "0,1" bitfld.long 0xA94 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA94 4. "CNT_RESET,-" "0,1" bitfld.long 0xA94 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA94 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA94 0. "WAIT_SET,-" "0,1" line.long 0xA98 "IMNTRCR678,INTC-Monitor Control Register 678" hexmask.long.word 0xA98 16.--31. 1. "KEYCODE,-" bitfld.long 0xA98 7. "NUM1_EN,-" "0,1" bitfld.long 0xA98 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA98 4. "CNT_RESET,-" "0,1" bitfld.long 0xA98 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA98 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA98 0. "WAIT_SET,-" "0,1" line.long 0xA9C "IMNTRCR679,INTC-Monitor Control Register 679" hexmask.long.word 0xA9C 16.--31. 1. "KEYCODE,-" bitfld.long 0xA9C 7. "NUM1_EN,-" "0,1" bitfld.long 0xA9C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xA9C 4. "CNT_RESET,-" "0,1" bitfld.long 0xA9C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xA9C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xA9C 0. "WAIT_SET,-" "0,1" line.long 0xAA0 "IMNTRCR680,INTC-Monitor Control Register 680" hexmask.long.word 0xAA0 16.--31. 1. "KEYCODE,-" bitfld.long 0xAA0 7. "NUM1_EN,-" "0,1" bitfld.long 0xAA0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAA0 4. "CNT_RESET,-" "0,1" bitfld.long 0xAA0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAA0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAA0 0. "WAIT_SET,-" "0,1" line.long 0xAA4 "IMNTRCR681,INTC-Monitor Control Register 681" hexmask.long.word 0xAA4 16.--31. 1. "KEYCODE,-" bitfld.long 0xAA4 7. "NUM1_EN,-" "0,1" bitfld.long 0xAA4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAA4 4. "CNT_RESET,-" "0,1" bitfld.long 0xAA4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAA4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAA4 0. "WAIT_SET,-" "0,1" line.long 0xAA8 "IMNTRCR682,INTC-Monitor Control Register 682" hexmask.long.word 0xAA8 16.--31. 1. "KEYCODE,-" bitfld.long 0xAA8 7. "NUM1_EN,-" "0,1" bitfld.long 0xAA8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAA8 4. "CNT_RESET,-" "0,1" bitfld.long 0xAA8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAA8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAA8 0. "WAIT_SET,-" "0,1" line.long 0xAAC "IMNTRCR683,INTC-Monitor Control Register 683" hexmask.long.word 0xAAC 16.--31. 1. "KEYCODE,-" bitfld.long 0xAAC 7. "NUM1_EN,-" "0,1" bitfld.long 0xAAC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAAC 4. "CNT_RESET,-" "0,1" bitfld.long 0xAAC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAAC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAAC 0. "WAIT_SET,-" "0,1" line.long 0xAB0 "IMNTRCR684,INTC-Monitor Control Register 684" hexmask.long.word 0xAB0 16.--31. 1. "KEYCODE,-" bitfld.long 0xAB0 7. "NUM1_EN,-" "0,1" bitfld.long 0xAB0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAB0 4. "CNT_RESET,-" "0,1" bitfld.long 0xAB0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAB0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAB0 0. "WAIT_SET,-" "0,1" line.long 0xAB4 "IMNTRCR685,INTC-Monitor Control Register 685" hexmask.long.word 0xAB4 16.--31. 1. "KEYCODE,-" bitfld.long 0xAB4 7. "NUM1_EN,-" "0,1" bitfld.long 0xAB4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAB4 4. "CNT_RESET,-" "0,1" bitfld.long 0xAB4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAB4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAB4 0. "WAIT_SET,-" "0,1" line.long 0xAB8 "IMNTRCR686,INTC-Monitor Control Register 686" hexmask.long.word 0xAB8 16.--31. 1. "KEYCODE,-" bitfld.long 0xAB8 7. "NUM1_EN,-" "0,1" bitfld.long 0xAB8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAB8 4. "CNT_RESET,-" "0,1" bitfld.long 0xAB8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAB8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAB8 0. "WAIT_SET,-" "0,1" line.long 0xABC "IMNTRCR687,INTC-Monitor Control Register 687" hexmask.long.word 0xABC 16.--31. 1. "KEYCODE,-" bitfld.long 0xABC 7. "NUM1_EN,-" "0,1" bitfld.long 0xABC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xABC 4. "CNT_RESET,-" "0,1" bitfld.long 0xABC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xABC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xABC 0. "WAIT_SET,-" "0,1" line.long 0xAC0 "IMNTRCR688,INTC-Monitor Control Register 688" hexmask.long.word 0xAC0 16.--31. 1. "KEYCODE,-" bitfld.long 0xAC0 7. "NUM1_EN,-" "0,1" bitfld.long 0xAC0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAC0 4. "CNT_RESET,-" "0,1" bitfld.long 0xAC0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAC0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAC0 0. "WAIT_SET,-" "0,1" line.long 0xAC4 "IMNTRCR689,INTC-Monitor Control Register 689" hexmask.long.word 0xAC4 16.--31. 1. "KEYCODE,-" bitfld.long 0xAC4 7. "NUM1_EN,-" "0,1" bitfld.long 0xAC4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAC4 4. "CNT_RESET,-" "0,1" bitfld.long 0xAC4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAC4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAC4 0. "WAIT_SET,-" "0,1" line.long 0xAC8 "IMNTRCR690,INTC-Monitor Control Register 690" hexmask.long.word 0xAC8 16.--31. 1. "KEYCODE,-" bitfld.long 0xAC8 7. "NUM1_EN,-" "0,1" bitfld.long 0xAC8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAC8 4. "CNT_RESET,-" "0,1" bitfld.long 0xAC8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAC8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAC8 0. "WAIT_SET,-" "0,1" line.long 0xACC "IMNTRCR691,INTC-Monitor Control Register 691" hexmask.long.word 0xACC 16.--31. 1. "KEYCODE,-" bitfld.long 0xACC 7. "NUM1_EN,-" "0,1" bitfld.long 0xACC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xACC 4. "CNT_RESET,-" "0,1" bitfld.long 0xACC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xACC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xACC 0. "WAIT_SET,-" "0,1" line.long 0xAD0 "IMNTRCR692,INTC-Monitor Control Register 692" hexmask.long.word 0xAD0 16.--31. 1. "KEYCODE,-" bitfld.long 0xAD0 7. "NUM1_EN,-" "0,1" bitfld.long 0xAD0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAD0 4. "CNT_RESET,-" "0,1" bitfld.long 0xAD0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAD0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAD0 0. "WAIT_SET,-" "0,1" line.long 0xAD4 "IMNTRCR693,INTC-Monitor Control Register 693" hexmask.long.word 0xAD4 16.--31. 1. "KEYCODE,-" bitfld.long 0xAD4 7. "NUM1_EN,-" "0,1" bitfld.long 0xAD4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAD4 4. "CNT_RESET,-" "0,1" bitfld.long 0xAD4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAD4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAD4 0. "WAIT_SET,-" "0,1" line.long 0xAD8 "IMNTRCR694,INTC-Monitor Control Register 694" hexmask.long.word 0xAD8 16.--31. 1. "KEYCODE,-" bitfld.long 0xAD8 7. "NUM1_EN,-" "0,1" bitfld.long 0xAD8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAD8 4. "CNT_RESET,-" "0,1" bitfld.long 0xAD8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAD8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAD8 0. "WAIT_SET,-" "0,1" line.long 0xADC "IMNTRCR695,INTC-Monitor Control Register 695" hexmask.long.word 0xADC 16.--31. 1. "KEYCODE,-" bitfld.long 0xADC 7. "NUM1_EN,-" "0,1" bitfld.long 0xADC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xADC 4. "CNT_RESET,-" "0,1" bitfld.long 0xADC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xADC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xADC 0. "WAIT_SET,-" "0,1" line.long 0xAE0 "IMNTRCR696,INTC-Monitor Control Register 696" hexmask.long.word 0xAE0 16.--31. 1. "KEYCODE,-" bitfld.long 0xAE0 7. "NUM1_EN,-" "0,1" bitfld.long 0xAE0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAE0 4. "CNT_RESET,-" "0,1" bitfld.long 0xAE0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAE0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAE0 0. "WAIT_SET,-" "0,1" line.long 0xAE4 "IMNTRCR697,INTC-Monitor Control Register 697" hexmask.long.word 0xAE4 16.--31. 1. "KEYCODE,-" bitfld.long 0xAE4 7. "NUM1_EN,-" "0,1" bitfld.long 0xAE4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAE4 4. "CNT_RESET,-" "0,1" bitfld.long 0xAE4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAE4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAE4 0. "WAIT_SET,-" "0,1" line.long 0xAE8 "IMNTRCR698,INTC-Monitor Control Register 698" hexmask.long.word 0xAE8 16.--31. 1. "KEYCODE,-" bitfld.long 0xAE8 7. "NUM1_EN,-" "0,1" bitfld.long 0xAE8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAE8 4. "CNT_RESET,-" "0,1" bitfld.long 0xAE8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAE8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAE8 0. "WAIT_SET,-" "0,1" line.long 0xAEC "IMNTRCR699,INTC-Monitor Control Register 699" hexmask.long.word 0xAEC 16.--31. 1. "KEYCODE,-" bitfld.long 0xAEC 7. "NUM1_EN,-" "0,1" bitfld.long 0xAEC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAEC 4. "CNT_RESET,-" "0,1" bitfld.long 0xAEC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAEC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAEC 0. "WAIT_SET,-" "0,1" line.long 0xAF0 "IMNTRCR700,INTC-Monitor Control Register 700" hexmask.long.word 0xAF0 16.--31. 1. "KEYCODE,-" bitfld.long 0xAF0 7. "NUM1_EN,-" "0,1" bitfld.long 0xAF0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAF0 4. "CNT_RESET,-" "0,1" bitfld.long 0xAF0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAF0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAF0 0. "WAIT_SET,-" "0,1" line.long 0xAF4 "IMNTRCR701,INTC-Monitor Control Register 701" hexmask.long.word 0xAF4 16.--31. 1. "KEYCODE,-" bitfld.long 0xAF4 7. "NUM1_EN,-" "0,1" bitfld.long 0xAF4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAF4 4. "CNT_RESET,-" "0,1" bitfld.long 0xAF4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAF4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAF4 0. "WAIT_SET,-" "0,1" line.long 0xAF8 "IMNTRCR702,INTC-Monitor Control Register 702" hexmask.long.word 0xAF8 16.--31. 1. "KEYCODE,-" bitfld.long 0xAF8 7. "NUM1_EN,-" "0,1" bitfld.long 0xAF8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAF8 4. "CNT_RESET,-" "0,1" bitfld.long 0xAF8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAF8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAF8 0. "WAIT_SET,-" "0,1" line.long 0xAFC "IMNTRCR703,INTC-Monitor Control Register 703" hexmask.long.word 0xAFC 16.--31. 1. "KEYCODE,-" bitfld.long 0xAFC 7. "NUM1_EN,-" "0,1" bitfld.long 0xAFC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xAFC 4. "CNT_RESET,-" "0,1" bitfld.long 0xAFC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xAFC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xAFC 0. "WAIT_SET,-" "0,1" line.long 0xB00 "IMNTRCR704,INTC-Monitor Control Register 704" hexmask.long.word 0xB00 16.--31. 1. "KEYCODE,-" bitfld.long 0xB00 7. "NUM1_EN,-" "0,1" bitfld.long 0xB00 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB00 4. "CNT_RESET,-" "0,1" bitfld.long 0xB00 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB00 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB00 0. "WAIT_SET,-" "0,1" line.long 0xB04 "IMNTRCR705,INTC-Monitor Control Register 705" hexmask.long.word 0xB04 16.--31. 1. "KEYCODE,-" bitfld.long 0xB04 7. "NUM1_EN,-" "0,1" bitfld.long 0xB04 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB04 4. "CNT_RESET,-" "0,1" bitfld.long 0xB04 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB04 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB04 0. "WAIT_SET,-" "0,1" line.long 0xB08 "IMNTRCR706,INTC-Monitor Control Register 706" hexmask.long.word 0xB08 16.--31. 1. "KEYCODE,-" bitfld.long 0xB08 7. "NUM1_EN,-" "0,1" bitfld.long 0xB08 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB08 4. "CNT_RESET,-" "0,1" bitfld.long 0xB08 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB08 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB08 0. "WAIT_SET,-" "0,1" line.long 0xB0C "IMNTRCR707,INTC-Monitor Control Register 707" hexmask.long.word 0xB0C 16.--31. 1. "KEYCODE,-" bitfld.long 0xB0C 7. "NUM1_EN,-" "0,1" bitfld.long 0xB0C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB0C 4. "CNT_RESET,-" "0,1" bitfld.long 0xB0C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB0C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB0C 0. "WAIT_SET,-" "0,1" line.long 0xB10 "IMNTRCR708,INTC-Monitor Control Register 708" hexmask.long.word 0xB10 16.--31. 1. "KEYCODE,-" bitfld.long 0xB10 7. "NUM1_EN,-" "0,1" bitfld.long 0xB10 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB10 4. "CNT_RESET,-" "0,1" bitfld.long 0xB10 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB10 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB10 0. "WAIT_SET,-" "0,1" line.long 0xB14 "IMNTRCR709,INTC-Monitor Control Register 709" hexmask.long.word 0xB14 16.--31. 1. "KEYCODE,-" bitfld.long 0xB14 7. "NUM1_EN,-" "0,1" bitfld.long 0xB14 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB14 4. "CNT_RESET,-" "0,1" bitfld.long 0xB14 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB14 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB14 0. "WAIT_SET,-" "0,1" line.long 0xB18 "IMNTRCR710,INTC-Monitor Control Register 710" hexmask.long.word 0xB18 16.--31. 1. "KEYCODE,-" bitfld.long 0xB18 7. "NUM1_EN,-" "0,1" bitfld.long 0xB18 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB18 4. "CNT_RESET,-" "0,1" bitfld.long 0xB18 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB18 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB18 0. "WAIT_SET,-" "0,1" line.long 0xB1C "IMNTRCR711,INTC-Monitor Control Register 711" hexmask.long.word 0xB1C 16.--31. 1. "KEYCODE,-" bitfld.long 0xB1C 7. "NUM1_EN,-" "0,1" bitfld.long 0xB1C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB1C 4. "CNT_RESET,-" "0,1" bitfld.long 0xB1C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB1C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB1C 0. "WAIT_SET,-" "0,1" line.long 0xB20 "IMNTRCR712,INTC-Monitor Control Register 712" hexmask.long.word 0xB20 16.--31. 1. "KEYCODE,-" bitfld.long 0xB20 7. "NUM1_EN,-" "0,1" bitfld.long 0xB20 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB20 4. "CNT_RESET,-" "0,1" bitfld.long 0xB20 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB20 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB20 0. "WAIT_SET,-" "0,1" line.long 0xB24 "IMNTRCR713,INTC-Monitor Control Register 713" hexmask.long.word 0xB24 16.--31. 1. "KEYCODE,-" bitfld.long 0xB24 7. "NUM1_EN,-" "0,1" bitfld.long 0xB24 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB24 4. "CNT_RESET,-" "0,1" bitfld.long 0xB24 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB24 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB24 0. "WAIT_SET,-" "0,1" line.long 0xB28 "IMNTRCR714,INTC-Monitor Control Register 714" hexmask.long.word 0xB28 16.--31. 1. "KEYCODE,-" bitfld.long 0xB28 7. "NUM1_EN,-" "0,1" bitfld.long 0xB28 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB28 4. "CNT_RESET,-" "0,1" bitfld.long 0xB28 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB28 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB28 0. "WAIT_SET,-" "0,1" line.long 0xB2C "IMNTRCR715,INTC-Monitor Control Register 715" hexmask.long.word 0xB2C 16.--31. 1. "KEYCODE,-" bitfld.long 0xB2C 7. "NUM1_EN,-" "0,1" bitfld.long 0xB2C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB2C 4. "CNT_RESET,-" "0,1" bitfld.long 0xB2C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB2C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB2C 0. "WAIT_SET,-" "0,1" line.long 0xB30 "IMNTRCR716,INTC-Monitor Control Register 716" hexmask.long.word 0xB30 16.--31. 1. "KEYCODE,-" bitfld.long 0xB30 7. "NUM1_EN,-" "0,1" bitfld.long 0xB30 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB30 4. "CNT_RESET,-" "0,1" bitfld.long 0xB30 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB30 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB30 0. "WAIT_SET,-" "0,1" line.long 0xB34 "IMNTRCR717,INTC-Monitor Control Register 717" hexmask.long.word 0xB34 16.--31. 1. "KEYCODE,-" bitfld.long 0xB34 7. "NUM1_EN,-" "0,1" bitfld.long 0xB34 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB34 4. "CNT_RESET,-" "0,1" bitfld.long 0xB34 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB34 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB34 0. "WAIT_SET,-" "0,1" line.long 0xB38 "IMNTRCR718,INTC-Monitor Control Register 718" hexmask.long.word 0xB38 16.--31. 1. "KEYCODE,-" bitfld.long 0xB38 7. "NUM1_EN,-" "0,1" bitfld.long 0xB38 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB38 4. "CNT_RESET,-" "0,1" bitfld.long 0xB38 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB38 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB38 0. "WAIT_SET,-" "0,1" line.long 0xB3C "IMNTRCR719,INTC-Monitor Control Register 719" hexmask.long.word 0xB3C 16.--31. 1. "KEYCODE,-" bitfld.long 0xB3C 7. "NUM1_EN,-" "0,1" bitfld.long 0xB3C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB3C 4. "CNT_RESET,-" "0,1" bitfld.long 0xB3C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB3C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB3C 0. "WAIT_SET,-" "0,1" line.long 0xB40 "IMNTRCR720,INTC-Monitor Control Register 720" hexmask.long.word 0xB40 16.--31. 1. "KEYCODE,-" bitfld.long 0xB40 7. "NUM1_EN,-" "0,1" bitfld.long 0xB40 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB40 4. "CNT_RESET,-" "0,1" bitfld.long 0xB40 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB40 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB40 0. "WAIT_SET,-" "0,1" line.long 0xB44 "IMNTRCR721,INTC-Monitor Control Register 721" hexmask.long.word 0xB44 16.--31. 1. "KEYCODE,-" bitfld.long 0xB44 7. "NUM1_EN,-" "0,1" bitfld.long 0xB44 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB44 4. "CNT_RESET,-" "0,1" bitfld.long 0xB44 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB44 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB44 0. "WAIT_SET,-" "0,1" line.long 0xB48 "IMNTRCR722,INTC-Monitor Control Register 722" hexmask.long.word 0xB48 16.--31. 1. "KEYCODE,-" bitfld.long 0xB48 7. "NUM1_EN,-" "0,1" bitfld.long 0xB48 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB48 4. "CNT_RESET,-" "0,1" bitfld.long 0xB48 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB48 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB48 0. "WAIT_SET,-" "0,1" line.long 0xB4C "IMNTRCR723,INTC-Monitor Control Register 723" hexmask.long.word 0xB4C 16.--31. 1. "KEYCODE,-" bitfld.long 0xB4C 7. "NUM1_EN,-" "0,1" bitfld.long 0xB4C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB4C 4. "CNT_RESET,-" "0,1" bitfld.long 0xB4C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB4C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB4C 0. "WAIT_SET,-" "0,1" line.long 0xB50 "IMNTRCR724,INTC-Monitor Control Register 724" hexmask.long.word 0xB50 16.--31. 1. "KEYCODE,-" bitfld.long 0xB50 7. "NUM1_EN,-" "0,1" bitfld.long 0xB50 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB50 4. "CNT_RESET,-" "0,1" bitfld.long 0xB50 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB50 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB50 0. "WAIT_SET,-" "0,1" line.long 0xB54 "IMNTRCR725,INTC-Monitor Control Register 725" hexmask.long.word 0xB54 16.--31. 1. "KEYCODE,-" bitfld.long 0xB54 7. "NUM1_EN,-" "0,1" bitfld.long 0xB54 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB54 4. "CNT_RESET,-" "0,1" bitfld.long 0xB54 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB54 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB54 0. "WAIT_SET,-" "0,1" line.long 0xB58 "IMNTRCR726,INTC-Monitor Control Register 726" hexmask.long.word 0xB58 16.--31. 1. "KEYCODE,-" bitfld.long 0xB58 7. "NUM1_EN,-" "0,1" bitfld.long 0xB58 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB58 4. "CNT_RESET,-" "0,1" bitfld.long 0xB58 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB58 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB58 0. "WAIT_SET,-" "0,1" line.long 0xB5C "IMNTRCR727,INTC-Monitor Control Register 727" hexmask.long.word 0xB5C 16.--31. 1. "KEYCODE,-" bitfld.long 0xB5C 7. "NUM1_EN,-" "0,1" bitfld.long 0xB5C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB5C 4. "CNT_RESET,-" "0,1" bitfld.long 0xB5C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB5C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB5C 0. "WAIT_SET,-" "0,1" line.long 0xB60 "IMNTRCR728,INTC-Monitor Control Register 728" hexmask.long.word 0xB60 16.--31. 1. "KEYCODE,-" bitfld.long 0xB60 7. "NUM1_EN,-" "0,1" bitfld.long 0xB60 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB60 4. "CNT_RESET,-" "0,1" bitfld.long 0xB60 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB60 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB60 0. "WAIT_SET,-" "0,1" line.long 0xB64 "IMNTRCR729,INTC-Monitor Control Register 729" hexmask.long.word 0xB64 16.--31. 1. "KEYCODE,-" bitfld.long 0xB64 7. "NUM1_EN,-" "0,1" bitfld.long 0xB64 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB64 4. "CNT_RESET,-" "0,1" bitfld.long 0xB64 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB64 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB64 0. "WAIT_SET,-" "0,1" line.long 0xB68 "IMNTRCR730,INTC-Monitor Control Register 730" hexmask.long.word 0xB68 16.--31. 1. "KEYCODE,-" bitfld.long 0xB68 7. "NUM1_EN,-" "0,1" bitfld.long 0xB68 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB68 4. "CNT_RESET,-" "0,1" bitfld.long 0xB68 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB68 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB68 0. "WAIT_SET,-" "0,1" line.long 0xB6C "IMNTRCR731,INTC-Monitor Control Register 731" hexmask.long.word 0xB6C 16.--31. 1. "KEYCODE,-" bitfld.long 0xB6C 7. "NUM1_EN,-" "0,1" bitfld.long 0xB6C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB6C 4. "CNT_RESET,-" "0,1" bitfld.long 0xB6C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB6C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB6C 0. "WAIT_SET,-" "0,1" line.long 0xB70 "IMNTRCR732,INTC-Monitor Control Register 732" hexmask.long.word 0xB70 16.--31. 1. "KEYCODE,-" bitfld.long 0xB70 7. "NUM1_EN,-" "0,1" bitfld.long 0xB70 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB70 4. "CNT_RESET,-" "0,1" bitfld.long 0xB70 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB70 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB70 0. "WAIT_SET,-" "0,1" line.long 0xB74 "IMNTRCR733,INTC-Monitor Control Register 733" hexmask.long.word 0xB74 16.--31. 1. "KEYCODE,-" bitfld.long 0xB74 7. "NUM1_EN,-" "0,1" bitfld.long 0xB74 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB74 4. "CNT_RESET,-" "0,1" bitfld.long 0xB74 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB74 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB74 0. "WAIT_SET,-" "0,1" line.long 0xB78 "IMNTRCR734,INTC-Monitor Control Register 734" hexmask.long.word 0xB78 16.--31. 1. "KEYCODE,-" bitfld.long 0xB78 7. "NUM1_EN,-" "0,1" bitfld.long 0xB78 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB78 4. "CNT_RESET,-" "0,1" bitfld.long 0xB78 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB78 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB78 0. "WAIT_SET,-" "0,1" line.long 0xB7C "IMNTRCR735,INTC-Monitor Control Register 735" hexmask.long.word 0xB7C 16.--31. 1. "KEYCODE,-" bitfld.long 0xB7C 7. "NUM1_EN,-" "0,1" bitfld.long 0xB7C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB7C 4. "CNT_RESET,-" "0,1" bitfld.long 0xB7C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB7C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB7C 0. "WAIT_SET,-" "0,1" line.long 0xB80 "IMNTRCR736,INTC-Monitor Control Register 736" hexmask.long.word 0xB80 16.--31. 1. "KEYCODE,-" bitfld.long 0xB80 7. "NUM1_EN,-" "0,1" bitfld.long 0xB80 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB80 4. "CNT_RESET,-" "0,1" bitfld.long 0xB80 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB80 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB80 0. "WAIT_SET,-" "0,1" line.long 0xB84 "IMNTRCR737,INTC-Monitor Control Register 737" hexmask.long.word 0xB84 16.--31. 1. "KEYCODE,-" bitfld.long 0xB84 7. "NUM1_EN,-" "0,1" bitfld.long 0xB84 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB84 4. "CNT_RESET,-" "0,1" bitfld.long 0xB84 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB84 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB84 0. "WAIT_SET,-" "0,1" line.long 0xB88 "IMNTRCR738,INTC-Monitor Control Register 738" hexmask.long.word 0xB88 16.--31. 1. "KEYCODE,-" bitfld.long 0xB88 7. "NUM1_EN,-" "0,1" bitfld.long 0xB88 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB88 4. "CNT_RESET,-" "0,1" bitfld.long 0xB88 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB88 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB88 0. "WAIT_SET,-" "0,1" line.long 0xB8C "IMNTRCR739,INTC-Monitor Control Register 739" hexmask.long.word 0xB8C 16.--31. 1. "KEYCODE,-" bitfld.long 0xB8C 7. "NUM1_EN,-" "0,1" bitfld.long 0xB8C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB8C 4. "CNT_RESET,-" "0,1" bitfld.long 0xB8C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB8C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB8C 0. "WAIT_SET,-" "0,1" line.long 0xB90 "IMNTRCR740,INTC-Monitor Control Register 740" hexmask.long.word 0xB90 16.--31. 1. "KEYCODE,-" bitfld.long 0xB90 7. "NUM1_EN,-" "0,1" bitfld.long 0xB90 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB90 4. "CNT_RESET,-" "0,1" bitfld.long 0xB90 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB90 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB90 0. "WAIT_SET,-" "0,1" line.long 0xB94 "IMNTRCR741,INTC-Monitor Control Register 741" hexmask.long.word 0xB94 16.--31. 1. "KEYCODE,-" bitfld.long 0xB94 7. "NUM1_EN,-" "0,1" bitfld.long 0xB94 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB94 4. "CNT_RESET,-" "0,1" bitfld.long 0xB94 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB94 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB94 0. "WAIT_SET,-" "0,1" line.long 0xB98 "IMNTRCR742,INTC-Monitor Control Register 742" hexmask.long.word 0xB98 16.--31. 1. "KEYCODE,-" bitfld.long 0xB98 7. "NUM1_EN,-" "0,1" bitfld.long 0xB98 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB98 4. "CNT_RESET,-" "0,1" bitfld.long 0xB98 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB98 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB98 0. "WAIT_SET,-" "0,1" line.long 0xB9C "IMNTRCR743,INTC-Monitor Control Register 743" hexmask.long.word 0xB9C 16.--31. 1. "KEYCODE,-" bitfld.long 0xB9C 7. "NUM1_EN,-" "0,1" bitfld.long 0xB9C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xB9C 4. "CNT_RESET,-" "0,1" bitfld.long 0xB9C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xB9C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xB9C 0. "WAIT_SET,-" "0,1" line.long 0xBA0 "IMNTRCR744,INTC-Monitor Control Register 744" hexmask.long.word 0xBA0 16.--31. 1. "KEYCODE,-" bitfld.long 0xBA0 7. "NUM1_EN,-" "0,1" bitfld.long 0xBA0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBA0 4. "CNT_RESET,-" "0,1" bitfld.long 0xBA0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBA0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBA0 0. "WAIT_SET,-" "0,1" line.long 0xBA4 "IMNTRCR745,INTC-Monitor Control Register 745" hexmask.long.word 0xBA4 16.--31. 1. "KEYCODE,-" bitfld.long 0xBA4 7. "NUM1_EN,-" "0,1" bitfld.long 0xBA4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBA4 4. "CNT_RESET,-" "0,1" bitfld.long 0xBA4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBA4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBA4 0. "WAIT_SET,-" "0,1" line.long 0xBA8 "IMNTRCR746,INTC-Monitor Control Register 746" hexmask.long.word 0xBA8 16.--31. 1. "KEYCODE,-" bitfld.long 0xBA8 7. "NUM1_EN,-" "0,1" bitfld.long 0xBA8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBA8 4. "CNT_RESET,-" "0,1" bitfld.long 0xBA8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBA8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBA8 0. "WAIT_SET,-" "0,1" line.long 0xBAC "IMNTRCR747,INTC-Monitor Control Register 747" hexmask.long.word 0xBAC 16.--31. 1. "KEYCODE,-" bitfld.long 0xBAC 7. "NUM1_EN,-" "0,1" bitfld.long 0xBAC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBAC 4. "CNT_RESET,-" "0,1" bitfld.long 0xBAC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBAC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBAC 0. "WAIT_SET,-" "0,1" line.long 0xBB0 "IMNTRCR748,INTC-Monitor Control Register 748" hexmask.long.word 0xBB0 16.--31. 1. "KEYCODE,-" bitfld.long 0xBB0 7. "NUM1_EN,-" "0,1" bitfld.long 0xBB0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBB0 4. "CNT_RESET,-" "0,1" bitfld.long 0xBB0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBB0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBB0 0. "WAIT_SET,-" "0,1" line.long 0xBB4 "IMNTRCR749,INTC-Monitor Control Register 749" hexmask.long.word 0xBB4 16.--31. 1. "KEYCODE,-" bitfld.long 0xBB4 7. "NUM1_EN,-" "0,1" bitfld.long 0xBB4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBB4 4. "CNT_RESET,-" "0,1" bitfld.long 0xBB4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBB4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBB4 0. "WAIT_SET,-" "0,1" line.long 0xBB8 "IMNTRCR750,INTC-Monitor Control Register 750" hexmask.long.word 0xBB8 16.--31. 1. "KEYCODE,-" bitfld.long 0xBB8 7. "NUM1_EN,-" "0,1" bitfld.long 0xBB8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBB8 4. "CNT_RESET,-" "0,1" bitfld.long 0xBB8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBB8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBB8 0. "WAIT_SET,-" "0,1" line.long 0xBBC "IMNTRCR751,INTC-Monitor Control Register 751" hexmask.long.word 0xBBC 16.--31. 1. "KEYCODE,-" bitfld.long 0xBBC 7. "NUM1_EN,-" "0,1" bitfld.long 0xBBC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBBC 4. "CNT_RESET,-" "0,1" bitfld.long 0xBBC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBBC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBBC 0. "WAIT_SET,-" "0,1" line.long 0xBC0 "IMNTRCR752,INTC-Monitor Control Register 752" hexmask.long.word 0xBC0 16.--31. 1. "KEYCODE,-" bitfld.long 0xBC0 7. "NUM1_EN,-" "0,1" bitfld.long 0xBC0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBC0 4. "CNT_RESET,-" "0,1" bitfld.long 0xBC0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBC0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBC0 0. "WAIT_SET,-" "0,1" line.long 0xBC4 "IMNTRCR753,INTC-Monitor Control Register 753" hexmask.long.word 0xBC4 16.--31. 1. "KEYCODE,-" bitfld.long 0xBC4 7. "NUM1_EN,-" "0,1" bitfld.long 0xBC4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBC4 4. "CNT_RESET,-" "0,1" bitfld.long 0xBC4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBC4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBC4 0. "WAIT_SET,-" "0,1" line.long 0xBC8 "IMNTRCR754,INTC-Monitor Control Register 754" hexmask.long.word 0xBC8 16.--31. 1. "KEYCODE,-" bitfld.long 0xBC8 7. "NUM1_EN,-" "0,1" bitfld.long 0xBC8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBC8 4. "CNT_RESET,-" "0,1" bitfld.long 0xBC8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBC8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBC8 0. "WAIT_SET,-" "0,1" line.long 0xBCC "IMNTRCR755,INTC-Monitor Control Register 755" hexmask.long.word 0xBCC 16.--31. 1. "KEYCODE,-" bitfld.long 0xBCC 7. "NUM1_EN,-" "0,1" bitfld.long 0xBCC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBCC 4. "CNT_RESET,-" "0,1" bitfld.long 0xBCC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBCC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBCC 0. "WAIT_SET,-" "0,1" line.long 0xBD0 "IMNTRCR756,INTC-Monitor Control Register 756" hexmask.long.word 0xBD0 16.--31. 1. "KEYCODE,-" bitfld.long 0xBD0 7. "NUM1_EN,-" "0,1" bitfld.long 0xBD0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBD0 4. "CNT_RESET,-" "0,1" bitfld.long 0xBD0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBD0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBD0 0. "WAIT_SET,-" "0,1" line.long 0xBD4 "IMNTRCR757,INTC-Monitor Control Register 757" hexmask.long.word 0xBD4 16.--31. 1. "KEYCODE,-" bitfld.long 0xBD4 7. "NUM1_EN,-" "0,1" bitfld.long 0xBD4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBD4 4. "CNT_RESET,-" "0,1" bitfld.long 0xBD4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBD4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBD4 0. "WAIT_SET,-" "0,1" line.long 0xBD8 "IMNTRCR758,INTC-Monitor Control Register 758" hexmask.long.word 0xBD8 16.--31. 1. "KEYCODE,-" bitfld.long 0xBD8 7. "NUM1_EN,-" "0,1" bitfld.long 0xBD8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBD8 4. "CNT_RESET,-" "0,1" bitfld.long 0xBD8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBD8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBD8 0. "WAIT_SET,-" "0,1" line.long 0xBDC "IMNTRCR759,INTC-Monitor Control Register 759" hexmask.long.word 0xBDC 16.--31. 1. "KEYCODE,-" bitfld.long 0xBDC 7. "NUM1_EN,-" "0,1" bitfld.long 0xBDC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBDC 4. "CNT_RESET,-" "0,1" bitfld.long 0xBDC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBDC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBDC 0. "WAIT_SET,-" "0,1" line.long 0xBE0 "IMNTRCR760,INTC-Monitor Control Register 760" hexmask.long.word 0xBE0 16.--31. 1. "KEYCODE,-" bitfld.long 0xBE0 7. "NUM1_EN,-" "0,1" bitfld.long 0xBE0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBE0 4. "CNT_RESET,-" "0,1" bitfld.long 0xBE0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBE0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBE0 0. "WAIT_SET,-" "0,1" line.long 0xBE4 "IMNTRCR761,INTC-Monitor Control Register 761" hexmask.long.word 0xBE4 16.--31. 1. "KEYCODE,-" bitfld.long 0xBE4 7. "NUM1_EN,-" "0,1" bitfld.long 0xBE4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBE4 4. "CNT_RESET,-" "0,1" bitfld.long 0xBE4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBE4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBE4 0. "WAIT_SET,-" "0,1" line.long 0xBE8 "IMNTRCR762,INTC-Monitor Control Register 762" hexmask.long.word 0xBE8 16.--31. 1. "KEYCODE,-" bitfld.long 0xBE8 7. "NUM1_EN,-" "0,1" bitfld.long 0xBE8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBE8 4. "CNT_RESET,-" "0,1" bitfld.long 0xBE8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBE8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBE8 0. "WAIT_SET,-" "0,1" line.long 0xBEC "IMNTRCR763,INTC-Monitor Control Register 763" hexmask.long.word 0xBEC 16.--31. 1. "KEYCODE,-" bitfld.long 0xBEC 7. "NUM1_EN,-" "0,1" bitfld.long 0xBEC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBEC 4. "CNT_RESET,-" "0,1" bitfld.long 0xBEC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBEC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBEC 0. "WAIT_SET,-" "0,1" line.long 0xBF0 "IMNTRCR764,INTC-Monitor Control Register 764" hexmask.long.word 0xBF0 16.--31. 1. "KEYCODE,-" bitfld.long 0xBF0 7. "NUM1_EN,-" "0,1" bitfld.long 0xBF0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBF0 4. "CNT_RESET,-" "0,1" bitfld.long 0xBF0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBF0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBF0 0. "WAIT_SET,-" "0,1" line.long 0xBF4 "IMNTRCR765,INTC-Monitor Control Register 765" hexmask.long.word 0xBF4 16.--31. 1. "KEYCODE,-" bitfld.long 0xBF4 7. "NUM1_EN,-" "0,1" bitfld.long 0xBF4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBF4 4. "CNT_RESET,-" "0,1" bitfld.long 0xBF4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBF4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBF4 0. "WAIT_SET,-" "0,1" line.long 0xBF8 "IMNTRCR766,INTC-Monitor Control Register 766" hexmask.long.word 0xBF8 16.--31. 1. "KEYCODE,-" bitfld.long 0xBF8 7. "NUM1_EN,-" "0,1" bitfld.long 0xBF8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBF8 4. "CNT_RESET,-" "0,1" bitfld.long 0xBF8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBF8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBF8 0. "WAIT_SET,-" "0,1" line.long 0xBFC "IMNTRCR767,INTC-Monitor Control Register 767" hexmask.long.word 0xBFC 16.--31. 1. "KEYCODE,-" bitfld.long 0xBFC 7. "NUM1_EN,-" "0,1" bitfld.long 0xBFC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xBFC 4. "CNT_RESET,-" "0,1" bitfld.long 0xBFC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xBFC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xBFC 0. "WAIT_SET,-" "0,1" line.long 0xC00 "IMNTRCR768,INTC-Monitor Control Register 768" hexmask.long.word 0xC00 16.--31. 1. "KEYCODE,-" bitfld.long 0xC00 7. "NUM1_EN,-" "0,1" bitfld.long 0xC00 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC00 4. "CNT_RESET,-" "0,1" bitfld.long 0xC00 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC00 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC00 0. "WAIT_SET,-" "0,1" line.long 0xC04 "IMNTRCR769,INTC-Monitor Control Register 769" hexmask.long.word 0xC04 16.--31. 1. "KEYCODE,-" bitfld.long 0xC04 7. "NUM1_EN,-" "0,1" bitfld.long 0xC04 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC04 4. "CNT_RESET,-" "0,1" bitfld.long 0xC04 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC04 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC04 0. "WAIT_SET,-" "0,1" line.long 0xC08 "IMNTRCR770,INTC-Monitor Control Register 770" hexmask.long.word 0xC08 16.--31. 1. "KEYCODE,-" bitfld.long 0xC08 7. "NUM1_EN,-" "0,1" bitfld.long 0xC08 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC08 4. "CNT_RESET,-" "0,1" bitfld.long 0xC08 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC08 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC08 0. "WAIT_SET,-" "0,1" line.long 0xC0C "IMNTRCR771,INTC-Monitor Control Register 771" hexmask.long.word 0xC0C 16.--31. 1. "KEYCODE,-" bitfld.long 0xC0C 7. "NUM1_EN,-" "0,1" bitfld.long 0xC0C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC0C 4. "CNT_RESET,-" "0,1" bitfld.long 0xC0C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC0C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC0C 0. "WAIT_SET,-" "0,1" line.long 0xC10 "IMNTRCR772,INTC-Monitor Control Register 772" hexmask.long.word 0xC10 16.--31. 1. "KEYCODE,-" bitfld.long 0xC10 7. "NUM1_EN,-" "0,1" bitfld.long 0xC10 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC10 4. "CNT_RESET,-" "0,1" bitfld.long 0xC10 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC10 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC10 0. "WAIT_SET,-" "0,1" line.long 0xC14 "IMNTRCR773,INTC-Monitor Control Register 773" hexmask.long.word 0xC14 16.--31. 1. "KEYCODE,-" bitfld.long 0xC14 7. "NUM1_EN,-" "0,1" bitfld.long 0xC14 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC14 4. "CNT_RESET,-" "0,1" bitfld.long 0xC14 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC14 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC14 0. "WAIT_SET,-" "0,1" line.long 0xC18 "IMNTRCR774,INTC-Monitor Control Register 774" hexmask.long.word 0xC18 16.--31. 1. "KEYCODE,-" bitfld.long 0xC18 7. "NUM1_EN,-" "0,1" bitfld.long 0xC18 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC18 4. "CNT_RESET,-" "0,1" bitfld.long 0xC18 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC18 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC18 0. "WAIT_SET,-" "0,1" line.long 0xC1C "IMNTRCR775,INTC-Monitor Control Register 775" hexmask.long.word 0xC1C 16.--31. 1. "KEYCODE,-" bitfld.long 0xC1C 7. "NUM1_EN,-" "0,1" bitfld.long 0xC1C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC1C 4. "CNT_RESET,-" "0,1" bitfld.long 0xC1C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC1C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC1C 0. "WAIT_SET,-" "0,1" line.long 0xC20 "IMNTRCR776,INTC-Monitor Control Register 776" hexmask.long.word 0xC20 16.--31. 1. "KEYCODE,-" bitfld.long 0xC20 7. "NUM1_EN,-" "0,1" bitfld.long 0xC20 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC20 4. "CNT_RESET,-" "0,1" bitfld.long 0xC20 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC20 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC20 0. "WAIT_SET,-" "0,1" line.long 0xC24 "IMNTRCR777,INTC-Monitor Control Register 777" hexmask.long.word 0xC24 16.--31. 1. "KEYCODE,-" bitfld.long 0xC24 7. "NUM1_EN,-" "0,1" bitfld.long 0xC24 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC24 4. "CNT_RESET,-" "0,1" bitfld.long 0xC24 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC24 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC24 0. "WAIT_SET,-" "0,1" line.long 0xC28 "IMNTRCR778,INTC-Monitor Control Register 778" hexmask.long.word 0xC28 16.--31. 1. "KEYCODE,-" bitfld.long 0xC28 7. "NUM1_EN,-" "0,1" bitfld.long 0xC28 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC28 4. "CNT_RESET,-" "0,1" bitfld.long 0xC28 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC28 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC28 0. "WAIT_SET,-" "0,1" line.long 0xC2C "IMNTRCR779,INTC-Monitor Control Register 779" hexmask.long.word 0xC2C 16.--31. 1. "KEYCODE,-" bitfld.long 0xC2C 7. "NUM1_EN,-" "0,1" bitfld.long 0xC2C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC2C 4. "CNT_RESET,-" "0,1" bitfld.long 0xC2C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC2C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC2C 0. "WAIT_SET,-" "0,1" line.long 0xC30 "IMNTRCR780,INTC-Monitor Control Register 780" hexmask.long.word 0xC30 16.--31. 1. "KEYCODE,-" bitfld.long 0xC30 7. "NUM1_EN,-" "0,1" bitfld.long 0xC30 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC30 4. "CNT_RESET,-" "0,1" bitfld.long 0xC30 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC30 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC30 0. "WAIT_SET,-" "0,1" line.long 0xC34 "IMNTRCR781,INTC-Monitor Control Register 781" hexmask.long.word 0xC34 16.--31. 1. "KEYCODE,-" bitfld.long 0xC34 7. "NUM1_EN,-" "0,1" bitfld.long 0xC34 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC34 4. "CNT_RESET,-" "0,1" bitfld.long 0xC34 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC34 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC34 0. "WAIT_SET,-" "0,1" line.long 0xC38 "IMNTRCR782,INTC-Monitor Control Register 782" hexmask.long.word 0xC38 16.--31. 1. "KEYCODE,-" bitfld.long 0xC38 7. "NUM1_EN,-" "0,1" bitfld.long 0xC38 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC38 4. "CNT_RESET,-" "0,1" bitfld.long 0xC38 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC38 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC38 0. "WAIT_SET,-" "0,1" line.long 0xC3C "IMNTRCR783,INTC-Monitor Control Register 783" hexmask.long.word 0xC3C 16.--31. 1. "KEYCODE,-" bitfld.long 0xC3C 7. "NUM1_EN,-" "0,1" bitfld.long 0xC3C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC3C 4. "CNT_RESET,-" "0,1" bitfld.long 0xC3C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC3C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC3C 0. "WAIT_SET,-" "0,1" line.long 0xC40 "IMNTRCR784,INTC-Monitor Control Register 784" hexmask.long.word 0xC40 16.--31. 1. "KEYCODE,-" bitfld.long 0xC40 7. "NUM1_EN,-" "0,1" bitfld.long 0xC40 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC40 4. "CNT_RESET,-" "0,1" bitfld.long 0xC40 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC40 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC40 0. "WAIT_SET,-" "0,1" line.long 0xC44 "IMNTRCR785,INTC-Monitor Control Register 785" hexmask.long.word 0xC44 16.--31. 1. "KEYCODE,-" bitfld.long 0xC44 7. "NUM1_EN,-" "0,1" bitfld.long 0xC44 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC44 4. "CNT_RESET,-" "0,1" bitfld.long 0xC44 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC44 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC44 0. "WAIT_SET,-" "0,1" line.long 0xC48 "IMNTRCR786,INTC-Monitor Control Register 786" hexmask.long.word 0xC48 16.--31. 1. "KEYCODE,-" bitfld.long 0xC48 7. "NUM1_EN,-" "0,1" bitfld.long 0xC48 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC48 4. "CNT_RESET,-" "0,1" bitfld.long 0xC48 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC48 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC48 0. "WAIT_SET,-" "0,1" line.long 0xC4C "IMNTRCR787,INTC-Monitor Control Register 787" hexmask.long.word 0xC4C 16.--31. 1. "KEYCODE,-" bitfld.long 0xC4C 7. "NUM1_EN,-" "0,1" bitfld.long 0xC4C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC4C 4. "CNT_RESET,-" "0,1" bitfld.long 0xC4C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC4C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC4C 0. "WAIT_SET,-" "0,1" line.long 0xC50 "IMNTRCR788,INTC-Monitor Control Register 788" hexmask.long.word 0xC50 16.--31. 1. "KEYCODE,-" bitfld.long 0xC50 7. "NUM1_EN,-" "0,1" bitfld.long 0xC50 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC50 4. "CNT_RESET,-" "0,1" bitfld.long 0xC50 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC50 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC50 0. "WAIT_SET,-" "0,1" line.long 0xC54 "IMNTRCR789,INTC-Monitor Control Register 789" hexmask.long.word 0xC54 16.--31. 1. "KEYCODE,-" bitfld.long 0xC54 7. "NUM1_EN,-" "0,1" bitfld.long 0xC54 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC54 4. "CNT_RESET,-" "0,1" bitfld.long 0xC54 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC54 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC54 0. "WAIT_SET,-" "0,1" line.long 0xC58 "IMNTRCR790,INTC-Monitor Control Register 790" hexmask.long.word 0xC58 16.--31. 1. "KEYCODE,-" bitfld.long 0xC58 7. "NUM1_EN,-" "0,1" bitfld.long 0xC58 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC58 4. "CNT_RESET,-" "0,1" bitfld.long 0xC58 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC58 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC58 0. "WAIT_SET,-" "0,1" line.long 0xC5C "IMNTRCR791,INTC-Monitor Control Register 791" hexmask.long.word 0xC5C 16.--31. 1. "KEYCODE,-" bitfld.long 0xC5C 7. "NUM1_EN,-" "0,1" bitfld.long 0xC5C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC5C 4. "CNT_RESET,-" "0,1" bitfld.long 0xC5C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC5C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC5C 0. "WAIT_SET,-" "0,1" line.long 0xC60 "IMNTRCR792,INTC-Monitor Control Register 792" hexmask.long.word 0xC60 16.--31. 1. "KEYCODE,-" bitfld.long 0xC60 7. "NUM1_EN,-" "0,1" bitfld.long 0xC60 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC60 4. "CNT_RESET,-" "0,1" bitfld.long 0xC60 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC60 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC60 0. "WAIT_SET,-" "0,1" line.long 0xC64 "IMNTRCR793,INTC-Monitor Control Register 793" hexmask.long.word 0xC64 16.--31. 1. "KEYCODE,-" bitfld.long 0xC64 7. "NUM1_EN,-" "0,1" bitfld.long 0xC64 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC64 4. "CNT_RESET,-" "0,1" bitfld.long 0xC64 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC64 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC64 0. "WAIT_SET,-" "0,1" line.long 0xC68 "IMNTRCR794,INTC-Monitor Control Register 794" hexmask.long.word 0xC68 16.--31. 1. "KEYCODE,-" bitfld.long 0xC68 7. "NUM1_EN,-" "0,1" bitfld.long 0xC68 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC68 4. "CNT_RESET,-" "0,1" bitfld.long 0xC68 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC68 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC68 0. "WAIT_SET,-" "0,1" line.long 0xC6C "IMNTRCR795,INTC-Monitor Control Register 795" hexmask.long.word 0xC6C 16.--31. 1. "KEYCODE,-" bitfld.long 0xC6C 7. "NUM1_EN,-" "0,1" bitfld.long 0xC6C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC6C 4. "CNT_RESET,-" "0,1" bitfld.long 0xC6C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC6C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC6C 0. "WAIT_SET,-" "0,1" line.long 0xC70 "IMNTRCR796,INTC-Monitor Control Register 796" hexmask.long.word 0xC70 16.--31. 1. "KEYCODE,-" bitfld.long 0xC70 7. "NUM1_EN,-" "0,1" bitfld.long 0xC70 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC70 4. "CNT_RESET,-" "0,1" bitfld.long 0xC70 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC70 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC70 0. "WAIT_SET,-" "0,1" line.long 0xC74 "IMNTRCR797,INTC-Monitor Control Register 797" hexmask.long.word 0xC74 16.--31. 1. "KEYCODE,-" bitfld.long 0xC74 7. "NUM1_EN,-" "0,1" bitfld.long 0xC74 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC74 4. "CNT_RESET,-" "0,1" bitfld.long 0xC74 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC74 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC74 0. "WAIT_SET,-" "0,1" line.long 0xC78 "IMNTRCR798,INTC-Monitor Control Register 798" hexmask.long.word 0xC78 16.--31. 1. "KEYCODE,-" bitfld.long 0xC78 7. "NUM1_EN,-" "0,1" bitfld.long 0xC78 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC78 4. "CNT_RESET,-" "0,1" bitfld.long 0xC78 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC78 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC78 0. "WAIT_SET,-" "0,1" line.long 0xC7C "IMNTRCR799,INTC-Monitor Control Register 799" hexmask.long.word 0xC7C 16.--31. 1. "KEYCODE,-" bitfld.long 0xC7C 7. "NUM1_EN,-" "0,1" bitfld.long 0xC7C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC7C 4. "CNT_RESET,-" "0,1" bitfld.long 0xC7C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC7C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC7C 0. "WAIT_SET,-" "0,1" line.long 0xC80 "IMNTRCR800,INTC-Monitor Control Register 800" hexmask.long.word 0xC80 16.--31. 1. "KEYCODE,-" bitfld.long 0xC80 7. "NUM1_EN,-" "0,1" bitfld.long 0xC80 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC80 4. "CNT_RESET,-" "0,1" bitfld.long 0xC80 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC80 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC80 0. "WAIT_SET,-" "0,1" line.long 0xC84 "IMNTRCR801,INTC-Monitor Control Register 801" hexmask.long.word 0xC84 16.--31. 1. "KEYCODE,-" bitfld.long 0xC84 7. "NUM1_EN,-" "0,1" bitfld.long 0xC84 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC84 4. "CNT_RESET,-" "0,1" bitfld.long 0xC84 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC84 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC84 0. "WAIT_SET,-" "0,1" line.long 0xC88 "IMNTRCR802,INTC-Monitor Control Register 802" hexmask.long.word 0xC88 16.--31. 1. "KEYCODE,-" bitfld.long 0xC88 7. "NUM1_EN,-" "0,1" bitfld.long 0xC88 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC88 4. "CNT_RESET,-" "0,1" bitfld.long 0xC88 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC88 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC88 0. "WAIT_SET,-" "0,1" line.long 0xC8C "IMNTRCR803,INTC-Monitor Control Register 803" hexmask.long.word 0xC8C 16.--31. 1. "KEYCODE,-" bitfld.long 0xC8C 7. "NUM1_EN,-" "0,1" bitfld.long 0xC8C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC8C 4. "CNT_RESET,-" "0,1" bitfld.long 0xC8C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC8C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC8C 0. "WAIT_SET,-" "0,1" line.long 0xC90 "IMNTRCR804,INTC-Monitor Control Register 804" hexmask.long.word 0xC90 16.--31. 1. "KEYCODE,-" bitfld.long 0xC90 7. "NUM1_EN,-" "0,1" bitfld.long 0xC90 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC90 4. "CNT_RESET,-" "0,1" bitfld.long 0xC90 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC90 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC90 0. "WAIT_SET,-" "0,1" line.long 0xC94 "IMNTRCR805,INTC-Monitor Control Register 805" hexmask.long.word 0xC94 16.--31. 1. "KEYCODE,-" bitfld.long 0xC94 7. "NUM1_EN,-" "0,1" bitfld.long 0xC94 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC94 4. "CNT_RESET,-" "0,1" bitfld.long 0xC94 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC94 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC94 0. "WAIT_SET,-" "0,1" line.long 0xC98 "IMNTRCR806,INTC-Monitor Control Register 806" hexmask.long.word 0xC98 16.--31. 1. "KEYCODE,-" bitfld.long 0xC98 7. "NUM1_EN,-" "0,1" bitfld.long 0xC98 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC98 4. "CNT_RESET,-" "0,1" bitfld.long 0xC98 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC98 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC98 0. "WAIT_SET,-" "0,1" line.long 0xC9C "IMNTRCR807,INTC-Monitor Control Register 807" hexmask.long.word 0xC9C 16.--31. 1. "KEYCODE,-" bitfld.long 0xC9C 7. "NUM1_EN,-" "0,1" bitfld.long 0xC9C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xC9C 4. "CNT_RESET,-" "0,1" bitfld.long 0xC9C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xC9C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xC9C 0. "WAIT_SET,-" "0,1" line.long 0xCA0 "IMNTRCR808,INTC-Monitor Control Register 808" hexmask.long.word 0xCA0 16.--31. 1. "KEYCODE,-" bitfld.long 0xCA0 7. "NUM1_EN,-" "0,1" bitfld.long 0xCA0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCA0 4. "CNT_RESET,-" "0,1" bitfld.long 0xCA0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCA0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCA0 0. "WAIT_SET,-" "0,1" line.long 0xCA4 "IMNTRCR809,INTC-Monitor Control Register 809" hexmask.long.word 0xCA4 16.--31. 1. "KEYCODE,-" bitfld.long 0xCA4 7. "NUM1_EN,-" "0,1" bitfld.long 0xCA4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCA4 4. "CNT_RESET,-" "0,1" bitfld.long 0xCA4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCA4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCA4 0. "WAIT_SET,-" "0,1" line.long 0xCA8 "IMNTRCR810,INTC-Monitor Control Register 810" hexmask.long.word 0xCA8 16.--31. 1. "KEYCODE,-" bitfld.long 0xCA8 7. "NUM1_EN,-" "0,1" bitfld.long 0xCA8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCA8 4. "CNT_RESET,-" "0,1" bitfld.long 0xCA8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCA8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCA8 0. "WAIT_SET,-" "0,1" line.long 0xCAC "IMNTRCR811,INTC-Monitor Control Register 811" hexmask.long.word 0xCAC 16.--31. 1. "KEYCODE,-" bitfld.long 0xCAC 7. "NUM1_EN,-" "0,1" bitfld.long 0xCAC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCAC 4. "CNT_RESET,-" "0,1" bitfld.long 0xCAC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCAC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCAC 0. "WAIT_SET,-" "0,1" line.long 0xCB0 "IMNTRCR812,INTC-Monitor Control Register 812" hexmask.long.word 0xCB0 16.--31. 1. "KEYCODE,-" bitfld.long 0xCB0 7. "NUM1_EN,-" "0,1" bitfld.long 0xCB0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCB0 4. "CNT_RESET,-" "0,1" bitfld.long 0xCB0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCB0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCB0 0. "WAIT_SET,-" "0,1" line.long 0xCB4 "IMNTRCR813,INTC-Monitor Control Register 813" hexmask.long.word 0xCB4 16.--31. 1. "KEYCODE,-" bitfld.long 0xCB4 7. "NUM1_EN,-" "0,1" bitfld.long 0xCB4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCB4 4. "CNT_RESET,-" "0,1" bitfld.long 0xCB4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCB4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCB4 0. "WAIT_SET,-" "0,1" line.long 0xCB8 "IMNTRCR814,INTC-Monitor Control Register 814" hexmask.long.word 0xCB8 16.--31. 1. "KEYCODE,-" bitfld.long 0xCB8 7. "NUM1_EN,-" "0,1" bitfld.long 0xCB8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCB8 4. "CNT_RESET,-" "0,1" bitfld.long 0xCB8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCB8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCB8 0. "WAIT_SET,-" "0,1" line.long 0xCBC "IMNTRCR815,INTC-Monitor Control Register 815" hexmask.long.word 0xCBC 16.--31. 1. "KEYCODE,-" bitfld.long 0xCBC 7. "NUM1_EN,-" "0,1" bitfld.long 0xCBC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCBC 4. "CNT_RESET,-" "0,1" bitfld.long 0xCBC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCBC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCBC 0. "WAIT_SET,-" "0,1" line.long 0xCC0 "IMNTRCR816,INTC-Monitor Control Register 816" hexmask.long.word 0xCC0 16.--31. 1. "KEYCODE,-" bitfld.long 0xCC0 7. "NUM1_EN,-" "0,1" bitfld.long 0xCC0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCC0 4. "CNT_RESET,-" "0,1" bitfld.long 0xCC0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCC0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCC0 0. "WAIT_SET,-" "0,1" line.long 0xCC4 "IMNTRCR817,INTC-Monitor Control Register 817" hexmask.long.word 0xCC4 16.--31. 1. "KEYCODE,-" bitfld.long 0xCC4 7. "NUM1_EN,-" "0,1" bitfld.long 0xCC4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCC4 4. "CNT_RESET,-" "0,1" bitfld.long 0xCC4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCC4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCC4 0. "WAIT_SET,-" "0,1" line.long 0xCC8 "IMNTRCR818,INTC-Monitor Control Register 818" hexmask.long.word 0xCC8 16.--31. 1. "KEYCODE,-" bitfld.long 0xCC8 7. "NUM1_EN,-" "0,1" bitfld.long 0xCC8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCC8 4. "CNT_RESET,-" "0,1" bitfld.long 0xCC8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCC8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCC8 0. "WAIT_SET,-" "0,1" line.long 0xCCC "IMNTRCR819,INTC-Monitor Control Register 819" hexmask.long.word 0xCCC 16.--31. 1. "KEYCODE,-" bitfld.long 0xCCC 7. "NUM1_EN,-" "0,1" bitfld.long 0xCCC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCCC 4. "CNT_RESET,-" "0,1" bitfld.long 0xCCC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCCC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCCC 0. "WAIT_SET,-" "0,1" line.long 0xCD0 "IMNTRCR820,INTC-Monitor Control Register 820" hexmask.long.word 0xCD0 16.--31. 1. "KEYCODE,-" bitfld.long 0xCD0 7. "NUM1_EN,-" "0,1" bitfld.long 0xCD0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCD0 4. "CNT_RESET,-" "0,1" bitfld.long 0xCD0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCD0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCD0 0. "WAIT_SET,-" "0,1" line.long 0xCD4 "IMNTRCR821,INTC-Monitor Control Register 821" hexmask.long.word 0xCD4 16.--31. 1. "KEYCODE,-" bitfld.long 0xCD4 7. "NUM1_EN,-" "0,1" bitfld.long 0xCD4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCD4 4. "CNT_RESET,-" "0,1" bitfld.long 0xCD4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCD4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCD4 0. "WAIT_SET,-" "0,1" line.long 0xCD8 "IMNTRCR822,INTC-Monitor Control Register 822" hexmask.long.word 0xCD8 16.--31. 1. "KEYCODE,-" bitfld.long 0xCD8 7. "NUM1_EN,-" "0,1" bitfld.long 0xCD8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCD8 4. "CNT_RESET,-" "0,1" bitfld.long 0xCD8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCD8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCD8 0. "WAIT_SET,-" "0,1" line.long 0xCDC "IMNTRCR823,INTC-Monitor Control Register 823" hexmask.long.word 0xCDC 16.--31. 1. "KEYCODE,-" bitfld.long 0xCDC 7. "NUM1_EN,-" "0,1" bitfld.long 0xCDC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCDC 4. "CNT_RESET,-" "0,1" bitfld.long 0xCDC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCDC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCDC 0. "WAIT_SET,-" "0,1" line.long 0xCE0 "IMNTRCR824,INTC-Monitor Control Register 824" hexmask.long.word 0xCE0 16.--31. 1. "KEYCODE,-" bitfld.long 0xCE0 7. "NUM1_EN,-" "0,1" bitfld.long 0xCE0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCE0 4. "CNT_RESET,-" "0,1" bitfld.long 0xCE0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCE0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCE0 0. "WAIT_SET,-" "0,1" line.long 0xCE4 "IMNTRCR825,INTC-Monitor Control Register 825" hexmask.long.word 0xCE4 16.--31. 1. "KEYCODE,-" bitfld.long 0xCE4 7. "NUM1_EN,-" "0,1" bitfld.long 0xCE4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCE4 4. "CNT_RESET,-" "0,1" bitfld.long 0xCE4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCE4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCE4 0. "WAIT_SET,-" "0,1" line.long 0xCE8 "IMNTRCR826,INTC-Monitor Control Register 826" hexmask.long.word 0xCE8 16.--31. 1. "KEYCODE,-" bitfld.long 0xCE8 7. "NUM1_EN,-" "0,1" bitfld.long 0xCE8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCE8 4. "CNT_RESET,-" "0,1" bitfld.long 0xCE8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCE8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCE8 0. "WAIT_SET,-" "0,1" line.long 0xCEC "IMNTRCR827,INTC-Monitor Control Register 827" hexmask.long.word 0xCEC 16.--31. 1. "KEYCODE,-" bitfld.long 0xCEC 7. "NUM1_EN,-" "0,1" bitfld.long 0xCEC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCEC 4. "CNT_RESET,-" "0,1" bitfld.long 0xCEC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCEC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCEC 0. "WAIT_SET,-" "0,1" line.long 0xCF0 "IMNTRCR828,INTC-Monitor Control Register 828" hexmask.long.word 0xCF0 16.--31. 1. "KEYCODE,-" bitfld.long 0xCF0 7. "NUM1_EN,-" "0,1" bitfld.long 0xCF0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCF0 4. "CNT_RESET,-" "0,1" bitfld.long 0xCF0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCF0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCF0 0. "WAIT_SET,-" "0,1" line.long 0xCF4 "IMNTRCR829,INTC-Monitor Control Register 829" hexmask.long.word 0xCF4 16.--31. 1. "KEYCODE,-" bitfld.long 0xCF4 7. "NUM1_EN,-" "0,1" bitfld.long 0xCF4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCF4 4. "CNT_RESET,-" "0,1" bitfld.long 0xCF4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCF4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCF4 0. "WAIT_SET,-" "0,1" line.long 0xCF8 "IMNTRCR830,INTC-Monitor Control Register 830" hexmask.long.word 0xCF8 16.--31. 1. "KEYCODE,-" bitfld.long 0xCF8 7. "NUM1_EN,-" "0,1" bitfld.long 0xCF8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCF8 4. "CNT_RESET,-" "0,1" bitfld.long 0xCF8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCF8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCF8 0. "WAIT_SET,-" "0,1" line.long 0xCFC "IMNTRCR831,INTC-Monitor Control Register 831" hexmask.long.word 0xCFC 16.--31. 1. "KEYCODE,-" bitfld.long 0xCFC 7. "NUM1_EN,-" "0,1" bitfld.long 0xCFC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xCFC 4. "CNT_RESET,-" "0,1" bitfld.long 0xCFC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xCFC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xCFC 0. "WAIT_SET,-" "0,1" line.long 0xD00 "IMNTRCR832,INTC-Monitor Control Register 832" hexmask.long.word 0xD00 16.--31. 1. "KEYCODE,-" bitfld.long 0xD00 7. "NUM1_EN,-" "0,1" bitfld.long 0xD00 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD00 4. "CNT_RESET,-" "0,1" bitfld.long 0xD00 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD00 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD00 0. "WAIT_SET,-" "0,1" line.long 0xD04 "IMNTRCR833,INTC-Monitor Control Register 833" hexmask.long.word 0xD04 16.--31. 1. "KEYCODE,-" bitfld.long 0xD04 7. "NUM1_EN,-" "0,1" bitfld.long 0xD04 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD04 4. "CNT_RESET,-" "0,1" bitfld.long 0xD04 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD04 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD04 0. "WAIT_SET,-" "0,1" line.long 0xD08 "IMNTRCR834,INTC-Monitor Control Register 834" hexmask.long.word 0xD08 16.--31. 1. "KEYCODE,-" bitfld.long 0xD08 7. "NUM1_EN,-" "0,1" bitfld.long 0xD08 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD08 4. "CNT_RESET,-" "0,1" bitfld.long 0xD08 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD08 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD08 0. "WAIT_SET,-" "0,1" line.long 0xD0C "IMNTRCR835,INTC-Monitor Control Register 835" hexmask.long.word 0xD0C 16.--31. 1. "KEYCODE,-" bitfld.long 0xD0C 7. "NUM1_EN,-" "0,1" bitfld.long 0xD0C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD0C 4. "CNT_RESET,-" "0,1" bitfld.long 0xD0C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD0C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD0C 0. "WAIT_SET,-" "0,1" line.long 0xD10 "IMNTRCR836,INTC-Monitor Control Register 836" hexmask.long.word 0xD10 16.--31. 1. "KEYCODE,-" bitfld.long 0xD10 7. "NUM1_EN,-" "0,1" bitfld.long 0xD10 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD10 4. "CNT_RESET,-" "0,1" bitfld.long 0xD10 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD10 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD10 0. "WAIT_SET,-" "0,1" line.long 0xD14 "IMNTRCR837,INTC-Monitor Control Register 837" hexmask.long.word 0xD14 16.--31. 1. "KEYCODE,-" bitfld.long 0xD14 7. "NUM1_EN,-" "0,1" bitfld.long 0xD14 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD14 4. "CNT_RESET,-" "0,1" bitfld.long 0xD14 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD14 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD14 0. "WAIT_SET,-" "0,1" line.long 0xD18 "IMNTRCR838,INTC-Monitor Control Register 838" hexmask.long.word 0xD18 16.--31. 1. "KEYCODE,-" bitfld.long 0xD18 7. "NUM1_EN,-" "0,1" bitfld.long 0xD18 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD18 4. "CNT_RESET,-" "0,1" bitfld.long 0xD18 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD18 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD18 0. "WAIT_SET,-" "0,1" line.long 0xD1C "IMNTRCR839,INTC-Monitor Control Register 839" hexmask.long.word 0xD1C 16.--31. 1. "KEYCODE,-" bitfld.long 0xD1C 7. "NUM1_EN,-" "0,1" bitfld.long 0xD1C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD1C 4. "CNT_RESET,-" "0,1" bitfld.long 0xD1C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD1C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD1C 0. "WAIT_SET,-" "0,1" line.long 0xD20 "IMNTRCR840,INTC-Monitor Control Register 840" hexmask.long.word 0xD20 16.--31. 1. "KEYCODE,-" bitfld.long 0xD20 7. "NUM1_EN,-" "0,1" bitfld.long 0xD20 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD20 4. "CNT_RESET,-" "0,1" bitfld.long 0xD20 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD20 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD20 0. "WAIT_SET,-" "0,1" line.long 0xD24 "IMNTRCR841,INTC-Monitor Control Register 841" hexmask.long.word 0xD24 16.--31. 1. "KEYCODE,-" bitfld.long 0xD24 7. "NUM1_EN,-" "0,1" bitfld.long 0xD24 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD24 4. "CNT_RESET,-" "0,1" bitfld.long 0xD24 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD24 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD24 0. "WAIT_SET,-" "0,1" line.long 0xD28 "IMNTRCR842,INTC-Monitor Control Register 842" hexmask.long.word 0xD28 16.--31. 1. "KEYCODE,-" bitfld.long 0xD28 7. "NUM1_EN,-" "0,1" bitfld.long 0xD28 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD28 4. "CNT_RESET,-" "0,1" bitfld.long 0xD28 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD28 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD28 0. "WAIT_SET,-" "0,1" line.long 0xD2C "IMNTRCR843,INTC-Monitor Control Register 843" hexmask.long.word 0xD2C 16.--31. 1. "KEYCODE,-" bitfld.long 0xD2C 7. "NUM1_EN,-" "0,1" bitfld.long 0xD2C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD2C 4. "CNT_RESET,-" "0,1" bitfld.long 0xD2C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD2C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD2C 0. "WAIT_SET,-" "0,1" line.long 0xD30 "IMNTRCR844,INTC-Monitor Control Register 844" hexmask.long.word 0xD30 16.--31. 1. "KEYCODE,-" bitfld.long 0xD30 7. "NUM1_EN,-" "0,1" bitfld.long 0xD30 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD30 4. "CNT_RESET,-" "0,1" bitfld.long 0xD30 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD30 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD30 0. "WAIT_SET,-" "0,1" line.long 0xD34 "IMNTRCR845,INTC-Monitor Control Register 845" hexmask.long.word 0xD34 16.--31. 1. "KEYCODE,-" bitfld.long 0xD34 7. "NUM1_EN,-" "0,1" bitfld.long 0xD34 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD34 4. "CNT_RESET,-" "0,1" bitfld.long 0xD34 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD34 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD34 0. "WAIT_SET,-" "0,1" line.long 0xD38 "IMNTRCR846,INTC-Monitor Control Register 846" hexmask.long.word 0xD38 16.--31. 1. "KEYCODE,-" bitfld.long 0xD38 7. "NUM1_EN,-" "0,1" bitfld.long 0xD38 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD38 4. "CNT_RESET,-" "0,1" bitfld.long 0xD38 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD38 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD38 0. "WAIT_SET,-" "0,1" line.long 0xD3C "IMNTRCR847,INTC-Monitor Control Register 847" hexmask.long.word 0xD3C 16.--31. 1. "KEYCODE,-" bitfld.long 0xD3C 7. "NUM1_EN,-" "0,1" bitfld.long 0xD3C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD3C 4. "CNT_RESET,-" "0,1" bitfld.long 0xD3C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD3C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD3C 0. "WAIT_SET,-" "0,1" line.long 0xD40 "IMNTRCR848,INTC-Monitor Control Register 848" hexmask.long.word 0xD40 16.--31. 1. "KEYCODE,-" bitfld.long 0xD40 7. "NUM1_EN,-" "0,1" bitfld.long 0xD40 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD40 4. "CNT_RESET,-" "0,1" bitfld.long 0xD40 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD40 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD40 0. "WAIT_SET,-" "0,1" line.long 0xD44 "IMNTRCR849,INTC-Monitor Control Register 849" hexmask.long.word 0xD44 16.--31. 1. "KEYCODE,-" bitfld.long 0xD44 7. "NUM1_EN,-" "0,1" bitfld.long 0xD44 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD44 4. "CNT_RESET,-" "0,1" bitfld.long 0xD44 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD44 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD44 0. "WAIT_SET,-" "0,1" line.long 0xD48 "IMNTRCR850,INTC-Monitor Control Register 850" hexmask.long.word 0xD48 16.--31. 1. "KEYCODE,-" bitfld.long 0xD48 7. "NUM1_EN,-" "0,1" bitfld.long 0xD48 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD48 4. "CNT_RESET,-" "0,1" bitfld.long 0xD48 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD48 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD48 0. "WAIT_SET,-" "0,1" line.long 0xD4C "IMNTRCR851,INTC-Monitor Control Register 851" hexmask.long.word 0xD4C 16.--31. 1. "KEYCODE,-" bitfld.long 0xD4C 7. "NUM1_EN,-" "0,1" bitfld.long 0xD4C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD4C 4. "CNT_RESET,-" "0,1" bitfld.long 0xD4C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD4C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD4C 0. "WAIT_SET,-" "0,1" line.long 0xD50 "IMNTRCR852,INTC-Monitor Control Register 852" hexmask.long.word 0xD50 16.--31. 1. "KEYCODE,-" bitfld.long 0xD50 7. "NUM1_EN,-" "0,1" bitfld.long 0xD50 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD50 4. "CNT_RESET,-" "0,1" bitfld.long 0xD50 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD50 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD50 0. "WAIT_SET,-" "0,1" line.long 0xD54 "IMNTRCR853,INTC-Monitor Control Register 853" hexmask.long.word 0xD54 16.--31. 1. "KEYCODE,-" bitfld.long 0xD54 7. "NUM1_EN,-" "0,1" bitfld.long 0xD54 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD54 4. "CNT_RESET,-" "0,1" bitfld.long 0xD54 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD54 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD54 0. "WAIT_SET,-" "0,1" line.long 0xD58 "IMNTRCR854,INTC-Monitor Control Register 854" hexmask.long.word 0xD58 16.--31. 1. "KEYCODE,-" bitfld.long 0xD58 7. "NUM1_EN,-" "0,1" bitfld.long 0xD58 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD58 4. "CNT_RESET,-" "0,1" bitfld.long 0xD58 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD58 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD58 0. "WAIT_SET,-" "0,1" line.long 0xD5C "IMNTRCR855,INTC-Monitor Control Register 855" hexmask.long.word 0xD5C 16.--31. 1. "KEYCODE,-" bitfld.long 0xD5C 7. "NUM1_EN,-" "0,1" bitfld.long 0xD5C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD5C 4. "CNT_RESET,-" "0,1" bitfld.long 0xD5C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD5C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD5C 0. "WAIT_SET,-" "0,1" line.long 0xD60 "IMNTRCR856,INTC-Monitor Control Register 856" hexmask.long.word 0xD60 16.--31. 1. "KEYCODE,-" bitfld.long 0xD60 7. "NUM1_EN,-" "0,1" bitfld.long 0xD60 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD60 4. "CNT_RESET,-" "0,1" bitfld.long 0xD60 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD60 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD60 0. "WAIT_SET,-" "0,1" line.long 0xD64 "IMNTRCR857,INTC-Monitor Control Register 857" hexmask.long.word 0xD64 16.--31. 1. "KEYCODE,-" bitfld.long 0xD64 7. "NUM1_EN,-" "0,1" bitfld.long 0xD64 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD64 4. "CNT_RESET,-" "0,1" bitfld.long 0xD64 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD64 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD64 0. "WAIT_SET,-" "0,1" line.long 0xD68 "IMNTRCR858,INTC-Monitor Control Register 858" hexmask.long.word 0xD68 16.--31. 1. "KEYCODE,-" bitfld.long 0xD68 7. "NUM1_EN,-" "0,1" bitfld.long 0xD68 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD68 4. "CNT_RESET,-" "0,1" bitfld.long 0xD68 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD68 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD68 0. "WAIT_SET,-" "0,1" line.long 0xD6C "IMNTRCR859,INTC-Monitor Control Register 859" hexmask.long.word 0xD6C 16.--31. 1. "KEYCODE,-" bitfld.long 0xD6C 7. "NUM1_EN,-" "0,1" bitfld.long 0xD6C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD6C 4. "CNT_RESET,-" "0,1" bitfld.long 0xD6C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD6C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD6C 0. "WAIT_SET,-" "0,1" line.long 0xD70 "IMNTRCR860,INTC-Monitor Control Register 860" hexmask.long.word 0xD70 16.--31. 1. "KEYCODE,-" bitfld.long 0xD70 7. "NUM1_EN,-" "0,1" bitfld.long 0xD70 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD70 4. "CNT_RESET,-" "0,1" bitfld.long 0xD70 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD70 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD70 0. "WAIT_SET,-" "0,1" line.long 0xD74 "IMNTRCR861,INTC-Monitor Control Register 861" hexmask.long.word 0xD74 16.--31. 1. "KEYCODE,-" bitfld.long 0xD74 7. "NUM1_EN,-" "0,1" bitfld.long 0xD74 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD74 4. "CNT_RESET,-" "0,1" bitfld.long 0xD74 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD74 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD74 0. "WAIT_SET,-" "0,1" line.long 0xD78 "IMNTRCR862,INTC-Monitor Control Register 862" hexmask.long.word 0xD78 16.--31. 1. "KEYCODE,-" bitfld.long 0xD78 7. "NUM1_EN,-" "0,1" bitfld.long 0xD78 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD78 4. "CNT_RESET,-" "0,1" bitfld.long 0xD78 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD78 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD78 0. "WAIT_SET,-" "0,1" line.long 0xD7C "IMNTRCR863,INTC-Monitor Control Register 863" hexmask.long.word 0xD7C 16.--31. 1. "KEYCODE,-" bitfld.long 0xD7C 7. "NUM1_EN,-" "0,1" bitfld.long 0xD7C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD7C 4. "CNT_RESET,-" "0,1" bitfld.long 0xD7C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD7C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD7C 0. "WAIT_SET,-" "0,1" line.long 0xD80 "IMNTRCR864,INTC-Monitor Control Register 864" hexmask.long.word 0xD80 16.--31. 1. "KEYCODE,-" bitfld.long 0xD80 7. "NUM1_EN,-" "0,1" bitfld.long 0xD80 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD80 4. "CNT_RESET,-" "0,1" bitfld.long 0xD80 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD80 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD80 0. "WAIT_SET,-" "0,1" line.long 0xD84 "IMNTRCR865,INTC-Monitor Control Register 865" hexmask.long.word 0xD84 16.--31. 1. "KEYCODE,-" bitfld.long 0xD84 7. "NUM1_EN,-" "0,1" bitfld.long 0xD84 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD84 4. "CNT_RESET,-" "0,1" bitfld.long 0xD84 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD84 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD84 0. "WAIT_SET,-" "0,1" line.long 0xD88 "IMNTRCR866,INTC-Monitor Control Register 866" hexmask.long.word 0xD88 16.--31. 1. "KEYCODE,-" bitfld.long 0xD88 7. "NUM1_EN,-" "0,1" bitfld.long 0xD88 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD88 4. "CNT_RESET,-" "0,1" bitfld.long 0xD88 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD88 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD88 0. "WAIT_SET,-" "0,1" line.long 0xD8C "IMNTRCR867,INTC-Monitor Control Register 867" hexmask.long.word 0xD8C 16.--31. 1. "KEYCODE,-" bitfld.long 0xD8C 7. "NUM1_EN,-" "0,1" bitfld.long 0xD8C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD8C 4. "CNT_RESET,-" "0,1" bitfld.long 0xD8C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD8C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD8C 0. "WAIT_SET,-" "0,1" line.long 0xD90 "IMNTRCR868,INTC-Monitor Control Register 868" hexmask.long.word 0xD90 16.--31. 1. "KEYCODE,-" bitfld.long 0xD90 7. "NUM1_EN,-" "0,1" bitfld.long 0xD90 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD90 4. "CNT_RESET,-" "0,1" bitfld.long 0xD90 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD90 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD90 0. "WAIT_SET,-" "0,1" line.long 0xD94 "IMNTRCR869,INTC-Monitor Control Register 869" hexmask.long.word 0xD94 16.--31. 1. "KEYCODE,-" bitfld.long 0xD94 7. "NUM1_EN,-" "0,1" bitfld.long 0xD94 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD94 4. "CNT_RESET,-" "0,1" bitfld.long 0xD94 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD94 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD94 0. "WAIT_SET,-" "0,1" line.long 0xD98 "IMNTRCR870,INTC-Monitor Control Register 870" hexmask.long.word 0xD98 16.--31. 1. "KEYCODE,-" bitfld.long 0xD98 7. "NUM1_EN,-" "0,1" bitfld.long 0xD98 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD98 4. "CNT_RESET,-" "0,1" bitfld.long 0xD98 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD98 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD98 0. "WAIT_SET,-" "0,1" line.long 0xD9C "IMNTRCR871,INTC-Monitor Control Register 871" hexmask.long.word 0xD9C 16.--31. 1. "KEYCODE,-" bitfld.long 0xD9C 7. "NUM1_EN,-" "0,1" bitfld.long 0xD9C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xD9C 4. "CNT_RESET,-" "0,1" bitfld.long 0xD9C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xD9C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xD9C 0. "WAIT_SET,-" "0,1" line.long 0xDA0 "IMNTRCR872,INTC-Monitor Control Register 872" hexmask.long.word 0xDA0 16.--31. 1. "KEYCODE,-" bitfld.long 0xDA0 7. "NUM1_EN,-" "0,1" bitfld.long 0xDA0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDA0 4. "CNT_RESET,-" "0,1" bitfld.long 0xDA0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDA0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDA0 0. "WAIT_SET,-" "0,1" line.long 0xDA4 "IMNTRCR873,INTC-Monitor Control Register 873" hexmask.long.word 0xDA4 16.--31. 1. "KEYCODE,-" bitfld.long 0xDA4 7. "NUM1_EN,-" "0,1" bitfld.long 0xDA4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDA4 4. "CNT_RESET,-" "0,1" bitfld.long 0xDA4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDA4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDA4 0. "WAIT_SET,-" "0,1" line.long 0xDA8 "IMNTRCR874,INTC-Monitor Control Register 874" hexmask.long.word 0xDA8 16.--31. 1. "KEYCODE,-" bitfld.long 0xDA8 7. "NUM1_EN,-" "0,1" bitfld.long 0xDA8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDA8 4. "CNT_RESET,-" "0,1" bitfld.long 0xDA8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDA8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDA8 0. "WAIT_SET,-" "0,1" line.long 0xDAC "IMNTRCR875,INTC-Monitor Control Register 875" hexmask.long.word 0xDAC 16.--31. 1. "KEYCODE,-" bitfld.long 0xDAC 7. "NUM1_EN,-" "0,1" bitfld.long 0xDAC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDAC 4. "CNT_RESET,-" "0,1" bitfld.long 0xDAC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDAC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDAC 0. "WAIT_SET,-" "0,1" line.long 0xDB0 "IMNTRCR876,INTC-Monitor Control Register 876" hexmask.long.word 0xDB0 16.--31. 1. "KEYCODE,-" bitfld.long 0xDB0 7. "NUM1_EN,-" "0,1" bitfld.long 0xDB0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDB0 4. "CNT_RESET,-" "0,1" bitfld.long 0xDB0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDB0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDB0 0. "WAIT_SET,-" "0,1" line.long 0xDB4 "IMNTRCR877,INTC-Monitor Control Register 877" hexmask.long.word 0xDB4 16.--31. 1. "KEYCODE,-" bitfld.long 0xDB4 7. "NUM1_EN,-" "0,1" bitfld.long 0xDB4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDB4 4. "CNT_RESET,-" "0,1" bitfld.long 0xDB4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDB4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDB4 0. "WAIT_SET,-" "0,1" line.long 0xDB8 "IMNTRCR878,INTC-Monitor Control Register 878" hexmask.long.word 0xDB8 16.--31. 1. "KEYCODE,-" bitfld.long 0xDB8 7. "NUM1_EN,-" "0,1" bitfld.long 0xDB8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDB8 4. "CNT_RESET,-" "0,1" bitfld.long 0xDB8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDB8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDB8 0. "WAIT_SET,-" "0,1" line.long 0xDBC "IMNTRCR879,INTC-Monitor Control Register 879" hexmask.long.word 0xDBC 16.--31. 1. "KEYCODE,-" bitfld.long 0xDBC 7. "NUM1_EN,-" "0,1" bitfld.long 0xDBC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDBC 4. "CNT_RESET,-" "0,1" bitfld.long 0xDBC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDBC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDBC 0. "WAIT_SET,-" "0,1" line.long 0xDC0 "IMNTRCR880,INTC-Monitor Control Register 880" hexmask.long.word 0xDC0 16.--31. 1. "KEYCODE,-" bitfld.long 0xDC0 7. "NUM1_EN,-" "0,1" bitfld.long 0xDC0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDC0 4. "CNT_RESET,-" "0,1" bitfld.long 0xDC0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDC0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDC0 0. "WAIT_SET,-" "0,1" line.long 0xDC4 "IMNTRCR881,INTC-Monitor Control Register 881" hexmask.long.word 0xDC4 16.--31. 1. "KEYCODE,-" bitfld.long 0xDC4 7. "NUM1_EN,-" "0,1" bitfld.long 0xDC4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDC4 4. "CNT_RESET,-" "0,1" bitfld.long 0xDC4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDC4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDC4 0. "WAIT_SET,-" "0,1" line.long 0xDC8 "IMNTRCR882,INTC-Monitor Control Register 882" hexmask.long.word 0xDC8 16.--31. 1. "KEYCODE,-" bitfld.long 0xDC8 7. "NUM1_EN,-" "0,1" bitfld.long 0xDC8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDC8 4. "CNT_RESET,-" "0,1" bitfld.long 0xDC8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDC8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDC8 0. "WAIT_SET,-" "0,1" line.long 0xDCC "IMNTRCR883,INTC-Monitor Control Register 883" hexmask.long.word 0xDCC 16.--31. 1. "KEYCODE,-" bitfld.long 0xDCC 7. "NUM1_EN,-" "0,1" bitfld.long 0xDCC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDCC 4. "CNT_RESET,-" "0,1" bitfld.long 0xDCC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDCC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDCC 0. "WAIT_SET,-" "0,1" line.long 0xDD0 "IMNTRCR884,INTC-Monitor Control Register 884" hexmask.long.word 0xDD0 16.--31. 1. "KEYCODE,-" bitfld.long 0xDD0 7. "NUM1_EN,-" "0,1" bitfld.long 0xDD0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDD0 4. "CNT_RESET,-" "0,1" bitfld.long 0xDD0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDD0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDD0 0. "WAIT_SET,-" "0,1" line.long 0xDD4 "IMNTRCR885,INTC-Monitor Control Register 885" hexmask.long.word 0xDD4 16.--31. 1. "KEYCODE,-" bitfld.long 0xDD4 7. "NUM1_EN,-" "0,1" bitfld.long 0xDD4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDD4 4. "CNT_RESET,-" "0,1" bitfld.long 0xDD4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDD4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDD4 0. "WAIT_SET,-" "0,1" line.long 0xDD8 "IMNTRCR886,INTC-Monitor Control Register 886" hexmask.long.word 0xDD8 16.--31. 1. "KEYCODE,-" bitfld.long 0xDD8 7. "NUM1_EN,-" "0,1" bitfld.long 0xDD8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDD8 4. "CNT_RESET,-" "0,1" bitfld.long 0xDD8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDD8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDD8 0. "WAIT_SET,-" "0,1" line.long 0xDDC "IMNTRCR887,INTC-Monitor Control Register 887" hexmask.long.word 0xDDC 16.--31. 1. "KEYCODE,-" bitfld.long 0xDDC 7. "NUM1_EN,-" "0,1" bitfld.long 0xDDC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDDC 4. "CNT_RESET,-" "0,1" bitfld.long 0xDDC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDDC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDDC 0. "WAIT_SET,-" "0,1" line.long 0xDE0 "IMNTRCR888,INTC-Monitor Control Register 888" hexmask.long.word 0xDE0 16.--31. 1. "KEYCODE,-" bitfld.long 0xDE0 7. "NUM1_EN,-" "0,1" bitfld.long 0xDE0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDE0 4. "CNT_RESET,-" "0,1" bitfld.long 0xDE0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDE0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDE0 0. "WAIT_SET,-" "0,1" line.long 0xDE4 "IMNTRCR889,INTC-Monitor Control Register 889" hexmask.long.word 0xDE4 16.--31. 1. "KEYCODE,-" bitfld.long 0xDE4 7. "NUM1_EN,-" "0,1" bitfld.long 0xDE4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDE4 4. "CNT_RESET,-" "0,1" bitfld.long 0xDE4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDE4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDE4 0. "WAIT_SET,-" "0,1" line.long 0xDE8 "IMNTRCR890,INTC-Monitor Control Register 890" hexmask.long.word 0xDE8 16.--31. 1. "KEYCODE,-" bitfld.long 0xDE8 7. "NUM1_EN,-" "0,1" bitfld.long 0xDE8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDE8 4. "CNT_RESET,-" "0,1" bitfld.long 0xDE8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDE8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDE8 0. "WAIT_SET,-" "0,1" line.long 0xDEC "IMNTRCR891,INTC-Monitor Control Register 891" hexmask.long.word 0xDEC 16.--31. 1. "KEYCODE,-" bitfld.long 0xDEC 7. "NUM1_EN,-" "0,1" bitfld.long 0xDEC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDEC 4. "CNT_RESET,-" "0,1" bitfld.long 0xDEC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDEC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDEC 0. "WAIT_SET,-" "0,1" line.long 0xDF0 "IMNTRCR892,INTC-Monitor Control Register 892" hexmask.long.word 0xDF0 16.--31. 1. "KEYCODE,-" bitfld.long 0xDF0 7. "NUM1_EN,-" "0,1" bitfld.long 0xDF0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDF0 4. "CNT_RESET,-" "0,1" bitfld.long 0xDF0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDF0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDF0 0. "WAIT_SET,-" "0,1" line.long 0xDF4 "IMNTRCR893,INTC-Monitor Control Register 893" hexmask.long.word 0xDF4 16.--31. 1. "KEYCODE,-" bitfld.long 0xDF4 7. "NUM1_EN,-" "0,1" bitfld.long 0xDF4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDF4 4. "CNT_RESET,-" "0,1" bitfld.long 0xDF4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDF4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDF4 0. "WAIT_SET,-" "0,1" line.long 0xDF8 "IMNTRCR894,INTC-Monitor Control Register 894" hexmask.long.word 0xDF8 16.--31. 1. "KEYCODE,-" bitfld.long 0xDF8 7. "NUM1_EN,-" "0,1" bitfld.long 0xDF8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDF8 4. "CNT_RESET,-" "0,1" bitfld.long 0xDF8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDF8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDF8 0. "WAIT_SET,-" "0,1" line.long 0xDFC "IMNTRCR895,INTC-Monitor Control Register 895" hexmask.long.word 0xDFC 16.--31. 1. "KEYCODE,-" bitfld.long 0xDFC 7. "NUM1_EN,-" "0,1" bitfld.long 0xDFC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xDFC 4. "CNT_RESET,-" "0,1" bitfld.long 0xDFC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xDFC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xDFC 0. "WAIT_SET,-" "0,1" line.long 0xE00 "IMNTRCR896,INTC-Monitor Control Register 896" hexmask.long.word 0xE00 16.--31. 1. "KEYCODE,-" bitfld.long 0xE00 7. "NUM1_EN,-" "0,1" bitfld.long 0xE00 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE00 4. "CNT_RESET,-" "0,1" bitfld.long 0xE00 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE00 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE00 0. "WAIT_SET,-" "0,1" line.long 0xE04 "IMNTRCR897,INTC-Monitor Control Register 897" hexmask.long.word 0xE04 16.--31. 1. "KEYCODE,-" bitfld.long 0xE04 7. "NUM1_EN,-" "0,1" bitfld.long 0xE04 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE04 4. "CNT_RESET,-" "0,1" bitfld.long 0xE04 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE04 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE04 0. "WAIT_SET,-" "0,1" line.long 0xE08 "IMNTRCR898,INTC-Monitor Control Register 898" hexmask.long.word 0xE08 16.--31. 1. "KEYCODE,-" bitfld.long 0xE08 7. "NUM1_EN,-" "0,1" bitfld.long 0xE08 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE08 4. "CNT_RESET,-" "0,1" bitfld.long 0xE08 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE08 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE08 0. "WAIT_SET,-" "0,1" line.long 0xE0C "IMNTRCR899,INTC-Monitor Control Register 899" hexmask.long.word 0xE0C 16.--31. 1. "KEYCODE,-" bitfld.long 0xE0C 7. "NUM1_EN,-" "0,1" bitfld.long 0xE0C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE0C 4. "CNT_RESET,-" "0,1" bitfld.long 0xE0C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE0C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE0C 0. "WAIT_SET,-" "0,1" line.long 0xE10 "IMNTRCR900,INTC-Monitor Control Register 900" hexmask.long.word 0xE10 16.--31. 1. "KEYCODE,-" bitfld.long 0xE10 7. "NUM1_EN,-" "0,1" bitfld.long 0xE10 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE10 4. "CNT_RESET,-" "0,1" bitfld.long 0xE10 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE10 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE10 0. "WAIT_SET,-" "0,1" line.long 0xE14 "IMNTRCR901,INTC-Monitor Control Register 901" hexmask.long.word 0xE14 16.--31. 1. "KEYCODE,-" bitfld.long 0xE14 7. "NUM1_EN,-" "0,1" bitfld.long 0xE14 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE14 4. "CNT_RESET,-" "0,1" bitfld.long 0xE14 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE14 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE14 0. "WAIT_SET,-" "0,1" line.long 0xE18 "IMNTRCR902,INTC-Monitor Control Register 902" hexmask.long.word 0xE18 16.--31. 1. "KEYCODE,-" bitfld.long 0xE18 7. "NUM1_EN,-" "0,1" bitfld.long 0xE18 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE18 4. "CNT_RESET,-" "0,1" bitfld.long 0xE18 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE18 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE18 0. "WAIT_SET,-" "0,1" line.long 0xE1C "IMNTRCR903,INTC-Monitor Control Register 903" hexmask.long.word 0xE1C 16.--31. 1. "KEYCODE,-" bitfld.long 0xE1C 7. "NUM1_EN,-" "0,1" bitfld.long 0xE1C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE1C 4. "CNT_RESET,-" "0,1" bitfld.long 0xE1C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE1C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE1C 0. "WAIT_SET,-" "0,1" line.long 0xE20 "IMNTRCR904,INTC-Monitor Control Register 904" hexmask.long.word 0xE20 16.--31. 1. "KEYCODE,-" bitfld.long 0xE20 7. "NUM1_EN,-" "0,1" bitfld.long 0xE20 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE20 4. "CNT_RESET,-" "0,1" bitfld.long 0xE20 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE20 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE20 0. "WAIT_SET,-" "0,1" line.long 0xE24 "IMNTRCR905,INTC-Monitor Control Register 905" hexmask.long.word 0xE24 16.--31. 1. "KEYCODE,-" bitfld.long 0xE24 7. "NUM1_EN,-" "0,1" bitfld.long 0xE24 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE24 4. "CNT_RESET,-" "0,1" bitfld.long 0xE24 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE24 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE24 0. "WAIT_SET,-" "0,1" line.long 0xE28 "IMNTRCR906,INTC-Monitor Control Register 906" hexmask.long.word 0xE28 16.--31. 1. "KEYCODE,-" bitfld.long 0xE28 7. "NUM1_EN,-" "0,1" bitfld.long 0xE28 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE28 4. "CNT_RESET,-" "0,1" bitfld.long 0xE28 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE28 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE28 0. "WAIT_SET,-" "0,1" line.long 0xE2C "IMNTRCR907,INTC-Monitor Control Register 907" hexmask.long.word 0xE2C 16.--31. 1. "KEYCODE,-" bitfld.long 0xE2C 7. "NUM1_EN,-" "0,1" bitfld.long 0xE2C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE2C 4. "CNT_RESET,-" "0,1" bitfld.long 0xE2C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE2C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE2C 0. "WAIT_SET,-" "0,1" line.long 0xE30 "IMNTRCR908,INTC-Monitor Control Register 908" hexmask.long.word 0xE30 16.--31. 1. "KEYCODE,-" bitfld.long 0xE30 7. "NUM1_EN,-" "0,1" bitfld.long 0xE30 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE30 4. "CNT_RESET,-" "0,1" bitfld.long 0xE30 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE30 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE30 0. "WAIT_SET,-" "0,1" line.long 0xE34 "IMNTRCR909,INTC-Monitor Control Register 909" hexmask.long.word 0xE34 16.--31. 1. "KEYCODE,-" bitfld.long 0xE34 7. "NUM1_EN,-" "0,1" bitfld.long 0xE34 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE34 4. "CNT_RESET,-" "0,1" bitfld.long 0xE34 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE34 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE34 0. "WAIT_SET,-" "0,1" line.long 0xE38 "IMNTRCR910,INTC-Monitor Control Register 910" hexmask.long.word 0xE38 16.--31. 1. "KEYCODE,-" bitfld.long 0xE38 7. "NUM1_EN,-" "0,1" bitfld.long 0xE38 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE38 4. "CNT_RESET,-" "0,1" bitfld.long 0xE38 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE38 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE38 0. "WAIT_SET,-" "0,1" line.long 0xE3C "IMNTRCR911,INTC-Monitor Control Register 911" hexmask.long.word 0xE3C 16.--31. 1. "KEYCODE,-" bitfld.long 0xE3C 7. "NUM1_EN,-" "0,1" bitfld.long 0xE3C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE3C 4. "CNT_RESET,-" "0,1" bitfld.long 0xE3C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE3C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE3C 0. "WAIT_SET,-" "0,1" line.long 0xE40 "IMNTRCR912,INTC-Monitor Control Register 912" hexmask.long.word 0xE40 16.--31. 1. "KEYCODE,-" bitfld.long 0xE40 7. "NUM1_EN,-" "0,1" bitfld.long 0xE40 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE40 4. "CNT_RESET,-" "0,1" bitfld.long 0xE40 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE40 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE40 0. "WAIT_SET,-" "0,1" line.long 0xE44 "IMNTRCR913,INTC-Monitor Control Register 913" hexmask.long.word 0xE44 16.--31. 1. "KEYCODE,-" bitfld.long 0xE44 7. "NUM1_EN,-" "0,1" bitfld.long 0xE44 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE44 4. "CNT_RESET,-" "0,1" bitfld.long 0xE44 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE44 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE44 0. "WAIT_SET,-" "0,1" line.long 0xE48 "IMNTRCR914,INTC-Monitor Control Register 914" hexmask.long.word 0xE48 16.--31. 1. "KEYCODE,-" bitfld.long 0xE48 7. "NUM1_EN,-" "0,1" bitfld.long 0xE48 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE48 4. "CNT_RESET,-" "0,1" bitfld.long 0xE48 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE48 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE48 0. "WAIT_SET,-" "0,1" line.long 0xE4C "IMNTRCR915,INTC-Monitor Control Register 915" hexmask.long.word 0xE4C 16.--31. 1. "KEYCODE,-" bitfld.long 0xE4C 7. "NUM1_EN,-" "0,1" bitfld.long 0xE4C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE4C 4. "CNT_RESET,-" "0,1" bitfld.long 0xE4C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE4C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE4C 0. "WAIT_SET,-" "0,1" line.long 0xE50 "IMNTRCR916,INTC-Monitor Control Register 916" hexmask.long.word 0xE50 16.--31. 1. "KEYCODE,-" bitfld.long 0xE50 7. "NUM1_EN,-" "0,1" bitfld.long 0xE50 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE50 4. "CNT_RESET,-" "0,1" bitfld.long 0xE50 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE50 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE50 0. "WAIT_SET,-" "0,1" line.long 0xE54 "IMNTRCR917,INTC-Monitor Control Register 917" hexmask.long.word 0xE54 16.--31. 1. "KEYCODE,-" bitfld.long 0xE54 7. "NUM1_EN,-" "0,1" bitfld.long 0xE54 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE54 4. "CNT_RESET,-" "0,1" bitfld.long 0xE54 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE54 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE54 0. "WAIT_SET,-" "0,1" line.long 0xE58 "IMNTRCR918,INTC-Monitor Control Register 918" hexmask.long.word 0xE58 16.--31. 1. "KEYCODE,-" bitfld.long 0xE58 7. "NUM1_EN,-" "0,1" bitfld.long 0xE58 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE58 4. "CNT_RESET,-" "0,1" bitfld.long 0xE58 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE58 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE58 0. "WAIT_SET,-" "0,1" line.long 0xE5C "IMNTRCR919,INTC-Monitor Control Register 919" hexmask.long.word 0xE5C 16.--31. 1. "KEYCODE,-" bitfld.long 0xE5C 7. "NUM1_EN,-" "0,1" bitfld.long 0xE5C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE5C 4. "CNT_RESET,-" "0,1" bitfld.long 0xE5C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE5C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE5C 0. "WAIT_SET,-" "0,1" line.long 0xE60 "IMNTRCR920,INTC-Monitor Control Register 920" hexmask.long.word 0xE60 16.--31. 1. "KEYCODE,-" bitfld.long 0xE60 7. "NUM1_EN,-" "0,1" bitfld.long 0xE60 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE60 4. "CNT_RESET,-" "0,1" bitfld.long 0xE60 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE60 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE60 0. "WAIT_SET,-" "0,1" line.long 0xE64 "IMNTRCR921,INTC-Monitor Control Register 921" hexmask.long.word 0xE64 16.--31. 1. "KEYCODE,-" bitfld.long 0xE64 7. "NUM1_EN,-" "0,1" bitfld.long 0xE64 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE64 4. "CNT_RESET,-" "0,1" bitfld.long 0xE64 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE64 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE64 0. "WAIT_SET,-" "0,1" line.long 0xE68 "IMNTRCR922,INTC-Monitor Control Register 922" hexmask.long.word 0xE68 16.--31. 1. "KEYCODE,-" bitfld.long 0xE68 7. "NUM1_EN,-" "0,1" bitfld.long 0xE68 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE68 4. "CNT_RESET,-" "0,1" bitfld.long 0xE68 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE68 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE68 0. "WAIT_SET,-" "0,1" line.long 0xE6C "IMNTRCR923,INTC-Monitor Control Register 923" hexmask.long.word 0xE6C 16.--31. 1. "KEYCODE,-" bitfld.long 0xE6C 7. "NUM1_EN,-" "0,1" bitfld.long 0xE6C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE6C 4. "CNT_RESET,-" "0,1" bitfld.long 0xE6C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE6C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE6C 0. "WAIT_SET,-" "0,1" line.long 0xE70 "IMNTRCR924,INTC-Monitor Control Register 924" hexmask.long.word 0xE70 16.--31. 1. "KEYCODE,-" bitfld.long 0xE70 7. "NUM1_EN,-" "0,1" bitfld.long 0xE70 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE70 4. "CNT_RESET,-" "0,1" bitfld.long 0xE70 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE70 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE70 0. "WAIT_SET,-" "0,1" line.long 0xE74 "IMNTRCR925,INTC-Monitor Control Register 925" hexmask.long.word 0xE74 16.--31. 1. "KEYCODE,-" bitfld.long 0xE74 7. "NUM1_EN,-" "0,1" bitfld.long 0xE74 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE74 4. "CNT_RESET,-" "0,1" bitfld.long 0xE74 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE74 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE74 0. "WAIT_SET,-" "0,1" line.long 0xE78 "IMNTRCR926,INTC-Monitor Control Register 926" hexmask.long.word 0xE78 16.--31. 1. "KEYCODE,-" bitfld.long 0xE78 7. "NUM1_EN,-" "0,1" bitfld.long 0xE78 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE78 4. "CNT_RESET,-" "0,1" bitfld.long 0xE78 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE78 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE78 0. "WAIT_SET,-" "0,1" line.long 0xE7C "IMNTRCR927,INTC-Monitor Control Register 927" hexmask.long.word 0xE7C 16.--31. 1. "KEYCODE,-" bitfld.long 0xE7C 7. "NUM1_EN,-" "0,1" bitfld.long 0xE7C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE7C 4. "CNT_RESET,-" "0,1" bitfld.long 0xE7C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE7C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE7C 0. "WAIT_SET,-" "0,1" line.long 0xE80 "IMNTRCR928,INTC-Monitor Control Register 928" hexmask.long.word 0xE80 16.--31. 1. "KEYCODE,-" bitfld.long 0xE80 7. "NUM1_EN,-" "0,1" bitfld.long 0xE80 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE80 4. "CNT_RESET,-" "0,1" bitfld.long 0xE80 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE80 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE80 0. "WAIT_SET,-" "0,1" line.long 0xE84 "IMNTRCR929,INTC-Monitor Control Register 929" hexmask.long.word 0xE84 16.--31. 1. "KEYCODE,-" bitfld.long 0xE84 7. "NUM1_EN,-" "0,1" bitfld.long 0xE84 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE84 4. "CNT_RESET,-" "0,1" bitfld.long 0xE84 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE84 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE84 0. "WAIT_SET,-" "0,1" line.long 0xE88 "IMNTRCR930,INTC-Monitor Control Register 930" hexmask.long.word 0xE88 16.--31. 1. "KEYCODE,-" bitfld.long 0xE88 7. "NUM1_EN,-" "0,1" bitfld.long 0xE88 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE88 4. "CNT_RESET,-" "0,1" bitfld.long 0xE88 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE88 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE88 0. "WAIT_SET,-" "0,1" line.long 0xE8C "IMNTRCR931,INTC-Monitor Control Register 931" hexmask.long.word 0xE8C 16.--31. 1. "KEYCODE,-" bitfld.long 0xE8C 7. "NUM1_EN,-" "0,1" bitfld.long 0xE8C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE8C 4. "CNT_RESET,-" "0,1" bitfld.long 0xE8C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE8C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE8C 0. "WAIT_SET,-" "0,1" line.long 0xE90 "IMNTRCR932,INTC-Monitor Control Register 932" hexmask.long.word 0xE90 16.--31. 1. "KEYCODE,-" bitfld.long 0xE90 7. "NUM1_EN,-" "0,1" bitfld.long 0xE90 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE90 4. "CNT_RESET,-" "0,1" bitfld.long 0xE90 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE90 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE90 0. "WAIT_SET,-" "0,1" line.long 0xE94 "IMNTRCR933,INTC-Monitor Control Register 933" hexmask.long.word 0xE94 16.--31. 1. "KEYCODE,-" bitfld.long 0xE94 7. "NUM1_EN,-" "0,1" bitfld.long 0xE94 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE94 4. "CNT_RESET,-" "0,1" bitfld.long 0xE94 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE94 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE94 0. "WAIT_SET,-" "0,1" line.long 0xE98 "IMNTRCR934,INTC-Monitor Control Register 934" hexmask.long.word 0xE98 16.--31. 1. "KEYCODE,-" bitfld.long 0xE98 7. "NUM1_EN,-" "0,1" bitfld.long 0xE98 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE98 4. "CNT_RESET,-" "0,1" bitfld.long 0xE98 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE98 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE98 0. "WAIT_SET,-" "0,1" line.long 0xE9C "IMNTRCR935,INTC-Monitor Control Register 935" hexmask.long.word 0xE9C 16.--31. 1. "KEYCODE,-" bitfld.long 0xE9C 7. "NUM1_EN,-" "0,1" bitfld.long 0xE9C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xE9C 4. "CNT_RESET,-" "0,1" bitfld.long 0xE9C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xE9C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xE9C 0. "WAIT_SET,-" "0,1" line.long 0xEA0 "IMNTRCR936,INTC-Monitor Control Register 936" hexmask.long.word 0xEA0 16.--31. 1. "KEYCODE,-" bitfld.long 0xEA0 7. "NUM1_EN,-" "0,1" bitfld.long 0xEA0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEA0 4. "CNT_RESET,-" "0,1" bitfld.long 0xEA0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEA0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEA0 0. "WAIT_SET,-" "0,1" line.long 0xEA4 "IMNTRCR937,INTC-Monitor Control Register 937" hexmask.long.word 0xEA4 16.--31. 1. "KEYCODE,-" bitfld.long 0xEA4 7. "NUM1_EN,-" "0,1" bitfld.long 0xEA4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEA4 4. "CNT_RESET,-" "0,1" bitfld.long 0xEA4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEA4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEA4 0. "WAIT_SET,-" "0,1" line.long 0xEA8 "IMNTRCR938,INTC-Monitor Control Register 938" hexmask.long.word 0xEA8 16.--31. 1. "KEYCODE,-" bitfld.long 0xEA8 7. "NUM1_EN,-" "0,1" bitfld.long 0xEA8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEA8 4. "CNT_RESET,-" "0,1" bitfld.long 0xEA8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEA8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEA8 0. "WAIT_SET,-" "0,1" line.long 0xEAC "IMNTRCR939,INTC-Monitor Control Register 939" hexmask.long.word 0xEAC 16.--31. 1. "KEYCODE,-" bitfld.long 0xEAC 7. "NUM1_EN,-" "0,1" bitfld.long 0xEAC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEAC 4. "CNT_RESET,-" "0,1" bitfld.long 0xEAC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEAC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEAC 0. "WAIT_SET,-" "0,1" line.long 0xEB0 "IMNTRCR940,INTC-Monitor Control Register 940" hexmask.long.word 0xEB0 16.--31. 1. "KEYCODE,-" bitfld.long 0xEB0 7. "NUM1_EN,-" "0,1" bitfld.long 0xEB0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEB0 4. "CNT_RESET,-" "0,1" bitfld.long 0xEB0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEB0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEB0 0. "WAIT_SET,-" "0,1" line.long 0xEB4 "IMNTRCR941,INTC-Monitor Control Register 941" hexmask.long.word 0xEB4 16.--31. 1. "KEYCODE,-" bitfld.long 0xEB4 7. "NUM1_EN,-" "0,1" bitfld.long 0xEB4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEB4 4. "CNT_RESET,-" "0,1" bitfld.long 0xEB4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEB4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEB4 0. "WAIT_SET,-" "0,1" line.long 0xEB8 "IMNTRCR942,INTC-Monitor Control Register 942" hexmask.long.word 0xEB8 16.--31. 1. "KEYCODE,-" bitfld.long 0xEB8 7. "NUM1_EN,-" "0,1" bitfld.long 0xEB8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEB8 4. "CNT_RESET,-" "0,1" bitfld.long 0xEB8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEB8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEB8 0. "WAIT_SET,-" "0,1" line.long 0xEBC "IMNTRCR943,INTC-Monitor Control Register 943" hexmask.long.word 0xEBC 16.--31. 1. "KEYCODE,-" bitfld.long 0xEBC 7. "NUM1_EN,-" "0,1" bitfld.long 0xEBC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEBC 4. "CNT_RESET,-" "0,1" bitfld.long 0xEBC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEBC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEBC 0. "WAIT_SET,-" "0,1" line.long 0xEC0 "IMNTRCR944,INTC-Monitor Control Register 944" hexmask.long.word 0xEC0 16.--31. 1. "KEYCODE,-" bitfld.long 0xEC0 7. "NUM1_EN,-" "0,1" bitfld.long 0xEC0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEC0 4. "CNT_RESET,-" "0,1" bitfld.long 0xEC0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEC0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEC0 0. "WAIT_SET,-" "0,1" line.long 0xEC4 "IMNTRCR945,INTC-Monitor Control Register 945" hexmask.long.word 0xEC4 16.--31. 1. "KEYCODE,-" bitfld.long 0xEC4 7. "NUM1_EN,-" "0,1" bitfld.long 0xEC4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEC4 4. "CNT_RESET,-" "0,1" bitfld.long 0xEC4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEC4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEC4 0. "WAIT_SET,-" "0,1" line.long 0xEC8 "IMNTRCR946,INTC-Monitor Control Register 946" hexmask.long.word 0xEC8 16.--31. 1. "KEYCODE,-" bitfld.long 0xEC8 7. "NUM1_EN,-" "0,1" bitfld.long 0xEC8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEC8 4. "CNT_RESET,-" "0,1" bitfld.long 0xEC8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEC8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEC8 0. "WAIT_SET,-" "0,1" line.long 0xECC "IMNTRCR947,INTC-Monitor Control Register 947" hexmask.long.word 0xECC 16.--31. 1. "KEYCODE,-" bitfld.long 0xECC 7. "NUM1_EN,-" "0,1" bitfld.long 0xECC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xECC 4. "CNT_RESET,-" "0,1" bitfld.long 0xECC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xECC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xECC 0. "WAIT_SET,-" "0,1" line.long 0xED0 "IMNTRCR948,INTC-Monitor Control Register 948" hexmask.long.word 0xED0 16.--31. 1. "KEYCODE,-" bitfld.long 0xED0 7. "NUM1_EN,-" "0,1" bitfld.long 0xED0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xED0 4. "CNT_RESET,-" "0,1" bitfld.long 0xED0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xED0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xED0 0. "WAIT_SET,-" "0,1" line.long 0xED4 "IMNTRCR949,INTC-Monitor Control Register 949" hexmask.long.word 0xED4 16.--31. 1. "KEYCODE,-" bitfld.long 0xED4 7. "NUM1_EN,-" "0,1" bitfld.long 0xED4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xED4 4. "CNT_RESET,-" "0,1" bitfld.long 0xED4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xED4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xED4 0. "WAIT_SET,-" "0,1" line.long 0xED8 "IMNTRCR950,INTC-Monitor Control Register 950" hexmask.long.word 0xED8 16.--31. 1. "KEYCODE,-" bitfld.long 0xED8 7. "NUM1_EN,-" "0,1" bitfld.long 0xED8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xED8 4. "CNT_RESET,-" "0,1" bitfld.long 0xED8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xED8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xED8 0. "WAIT_SET,-" "0,1" line.long 0xEDC "IMNTRCR951,INTC-Monitor Control Register 951" hexmask.long.word 0xEDC 16.--31. 1. "KEYCODE,-" bitfld.long 0xEDC 7. "NUM1_EN,-" "0,1" bitfld.long 0xEDC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEDC 4. "CNT_RESET,-" "0,1" bitfld.long 0xEDC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEDC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEDC 0. "WAIT_SET,-" "0,1" line.long 0xEE0 "IMNTRCR952,INTC-Monitor Control Register 952" hexmask.long.word 0xEE0 16.--31. 1. "KEYCODE,-" bitfld.long 0xEE0 7. "NUM1_EN,-" "0,1" bitfld.long 0xEE0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEE0 4. "CNT_RESET,-" "0,1" bitfld.long 0xEE0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEE0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEE0 0. "WAIT_SET,-" "0,1" line.long 0xEE4 "IMNTRCR953,INTC-Monitor Control Register 953" hexmask.long.word 0xEE4 16.--31. 1. "KEYCODE,-" bitfld.long 0xEE4 7. "NUM1_EN,-" "0,1" bitfld.long 0xEE4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEE4 4. "CNT_RESET,-" "0,1" bitfld.long 0xEE4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEE4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEE4 0. "WAIT_SET,-" "0,1" line.long 0xEE8 "IMNTRCR954,INTC-Monitor Control Register 954" hexmask.long.word 0xEE8 16.--31. 1. "KEYCODE,-" bitfld.long 0xEE8 7. "NUM1_EN,-" "0,1" bitfld.long 0xEE8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEE8 4. "CNT_RESET,-" "0,1" bitfld.long 0xEE8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEE8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEE8 0. "WAIT_SET,-" "0,1" line.long 0xEEC "IMNTRCR955,INTC-Monitor Control Register 955" hexmask.long.word 0xEEC 16.--31. 1. "KEYCODE,-" bitfld.long 0xEEC 7. "NUM1_EN,-" "0,1" bitfld.long 0xEEC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEEC 4. "CNT_RESET,-" "0,1" bitfld.long 0xEEC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEEC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEEC 0. "WAIT_SET,-" "0,1" line.long 0xEF0 "IMNTRCR956,INTC-Monitor Control Register 956" hexmask.long.word 0xEF0 16.--31. 1. "KEYCODE,-" bitfld.long 0xEF0 7. "NUM1_EN,-" "0,1" bitfld.long 0xEF0 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEF0 4. "CNT_RESET,-" "0,1" bitfld.long 0xEF0 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEF0 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEF0 0. "WAIT_SET,-" "0,1" line.long 0xEF4 "IMNTRCR957,INTC-Monitor Control Register 957" hexmask.long.word 0xEF4 16.--31. 1. "KEYCODE,-" bitfld.long 0xEF4 7. "NUM1_EN,-" "0,1" bitfld.long 0xEF4 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEF4 4. "CNT_RESET,-" "0,1" bitfld.long 0xEF4 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEF4 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEF4 0. "WAIT_SET,-" "0,1" line.long 0xEF8 "IMNTRCR958,INTC-Monitor Control Register 958" hexmask.long.word 0xEF8 16.--31. 1. "KEYCODE,-" bitfld.long 0xEF8 7. "NUM1_EN,-" "0,1" bitfld.long 0xEF8 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEF8 4. "CNT_RESET,-" "0,1" bitfld.long 0xEF8 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEF8 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEF8 0. "WAIT_SET,-" "0,1" line.long 0xEFC "IMNTRCR959,INTC-Monitor Control Register 959" hexmask.long.word 0xEFC 16.--31. 1. "KEYCODE,-" bitfld.long 0xEFC 7. "NUM1_EN,-" "0,1" bitfld.long 0xEFC 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xEFC 4. "CNT_RESET,-" "0,1" bitfld.long 0xEFC 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xEFC 1. "IMNTR_EN,-" "0,1" bitfld.long 0xEFC 0. "WAIT_SET,-" "0,1" line.long 0xF00 "IMNTRCR960,INTC-Monitor Control Register 960" hexmask.long.word 0xF00 16.--31. 1. "KEYCODE,-" bitfld.long 0xF00 7. "NUM1_EN,-" "0,1" bitfld.long 0xF00 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF00 4. "CNT_RESET,-" "0,1" bitfld.long 0xF00 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF00 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF00 0. "WAIT_SET,-" "0,1" line.long 0xF04 "IMNTRCR961,INTC-Monitor Control Register 961" hexmask.long.word 0xF04 16.--31. 1. "KEYCODE,-" bitfld.long 0xF04 7. "NUM1_EN,-" "0,1" bitfld.long 0xF04 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF04 4. "CNT_RESET,-" "0,1" bitfld.long 0xF04 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF04 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF04 0. "WAIT_SET,-" "0,1" line.long 0xF08 "IMNTRCR962,INTC-Monitor Control Register 962" hexmask.long.word 0xF08 16.--31. 1. "KEYCODE,-" bitfld.long 0xF08 7. "NUM1_EN,-" "0,1" bitfld.long 0xF08 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF08 4. "CNT_RESET,-" "0,1" bitfld.long 0xF08 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF08 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF08 0. "WAIT_SET,-" "0,1" line.long 0xF0C "IMNTRCR963,INTC-Monitor Control Register 963" hexmask.long.word 0xF0C 16.--31. 1. "KEYCODE,-" bitfld.long 0xF0C 7. "NUM1_EN,-" "0,1" bitfld.long 0xF0C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF0C 4. "CNT_RESET,-" "0,1" bitfld.long 0xF0C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF0C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF0C 0. "WAIT_SET,-" "0,1" line.long 0xF10 "IMNTRCR964,INTC-Monitor Control Register 964" hexmask.long.word 0xF10 16.--31. 1. "KEYCODE,-" bitfld.long 0xF10 7. "NUM1_EN,-" "0,1" bitfld.long 0xF10 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF10 4. "CNT_RESET,-" "0,1" bitfld.long 0xF10 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF10 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF10 0. "WAIT_SET,-" "0,1" line.long 0xF14 "IMNTRCR965,INTC-Monitor Control Register 965" hexmask.long.word 0xF14 16.--31. 1. "KEYCODE,-" bitfld.long 0xF14 7. "NUM1_EN,-" "0,1" bitfld.long 0xF14 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF14 4. "CNT_RESET,-" "0,1" bitfld.long 0xF14 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF14 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF14 0. "WAIT_SET,-" "0,1" line.long 0xF18 "IMNTRCR966,INTC-Monitor Control Register 966" hexmask.long.word 0xF18 16.--31. 1. "KEYCODE,-" bitfld.long 0xF18 7. "NUM1_EN,-" "0,1" bitfld.long 0xF18 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF18 4. "CNT_RESET,-" "0,1" bitfld.long 0xF18 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF18 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF18 0. "WAIT_SET,-" "0,1" line.long 0xF1C "IMNTRCR967,INTC-Monitor Control Register 967" hexmask.long.word 0xF1C 16.--31. 1. "KEYCODE,-" bitfld.long 0xF1C 7. "NUM1_EN,-" "0,1" bitfld.long 0xF1C 5.--6. "CNT_NUM1,-" "0,1,2,3" bitfld.long 0xF1C 4. "CNT_RESET,-" "0,1" bitfld.long 0xF1C 2.--3. "CNT_NUM0,-" "0,1,2,3" bitfld.long 0xF1C 1. "IMNTR_EN,-" "0,1" bitfld.long 0xF1C 0. "WAIT_SET,-" "0,1" group.long 0x3000++0x1E3 line.long 0x0 "IMNTRSR0,INTC-Monitor Status Register 0" hexmask.long.word 0x0 16.--31. 1. "KEYCODE,-" bitfld.long 0x0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x0 0. "WAIT_ERR[x],-" "0,1" line.long 0x4 "IMNTRSR1,INTC-Monitor Status Register 1" hexmask.long.word 0x4 16.--31. 1. "KEYCODE,-" bitfld.long 0x4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x4 0. "WAIT_ERR[x],-" "0,1" line.long 0x8 "IMNTRSR2,INTC-Monitor Status Register 2" hexmask.long.word 0x8 16.--31. 1. "KEYCODE,-" bitfld.long 0x8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x8 0. "WAIT_ERR[x],-" "0,1" line.long 0xC "IMNTRSR3,INTC-Monitor Status Register 3" hexmask.long.word 0xC 16.--31. 1. "KEYCODE,-" bitfld.long 0xC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xC 0. "WAIT_ERR[x],-" "0,1" line.long 0x10 "IMNTRSR4,INTC-Monitor Status Register 4" hexmask.long.word 0x10 16.--31. 1. "KEYCODE,-" bitfld.long 0x10 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x10 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x10 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x10 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x10 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x10 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x10 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x10 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x10 0. "WAIT_ERR[x],-" "0,1" line.long 0x14 "IMNTRSR5,INTC-Monitor Status Register 5" hexmask.long.word 0x14 16.--31. 1. "KEYCODE,-" bitfld.long 0x14 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x14 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x14 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x14 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x14 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x14 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x14 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x14 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x14 0. "WAIT_ERR[x],-" "0,1" line.long 0x18 "IMNTRSR6,INTC-Monitor Status Register 6" hexmask.long.word 0x18 16.--31. 1. "KEYCODE,-" bitfld.long 0x18 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x18 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x18 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x18 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x18 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x18 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x18 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x18 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x18 0. "WAIT_ERR[x],-" "0,1" line.long 0x1C "IMNTRSR7,INTC-Monitor Status Register 7" hexmask.long.word 0x1C 16.--31. 1. "KEYCODE,-" bitfld.long 0x1C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1C 0. "WAIT_ERR[x],-" "0,1" line.long 0x20 "IMNTRSR8,INTC-Monitor Status Register 8" hexmask.long.word 0x20 16.--31. 1. "KEYCODE,-" bitfld.long 0x20 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x20 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x20 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x20 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x20 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x20 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x20 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x20 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x20 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x20 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x20 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x20 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x20 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x20 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x20 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x20 0. "WAIT_ERR[x],-" "0,1" line.long 0x24 "IMNTRSR9,INTC-Monitor Status Register 9" hexmask.long.word 0x24 16.--31. 1. "KEYCODE,-" bitfld.long 0x24 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x24 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x24 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x24 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x24 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x24 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x24 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x24 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x24 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x24 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x24 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x24 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x24 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x24 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x24 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x24 0. "WAIT_ERR[x],-" "0,1" line.long 0x28 "IMNTRSR10,INTC-Monitor Status Register 10" hexmask.long.word 0x28 16.--31. 1. "KEYCODE,-" bitfld.long 0x28 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x28 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x28 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x28 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x28 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x28 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x28 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x28 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x28 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x28 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x28 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x28 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x28 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x28 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x28 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x28 0. "WAIT_ERR[x],-" "0,1" line.long 0x2C "IMNTRSR11,INTC-Monitor Status Register 11" hexmask.long.word 0x2C 16.--31. 1. "KEYCODE,-" bitfld.long 0x2C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x2C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x2C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x2C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x2C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x2C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x2C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x2C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x2C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x2C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x2C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x2C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x2C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x2C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x2C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x2C 0. "WAIT_ERR[x],-" "0,1" line.long 0x30 "IMNTRSR12,INTC-Monitor Status Register 12" hexmask.long.word 0x30 16.--31. 1. "KEYCODE,-" bitfld.long 0x30 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x30 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x30 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x30 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x30 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x30 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x30 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x30 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x30 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x30 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x30 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x30 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x30 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x30 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x30 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x30 0. "WAIT_ERR[x],-" "0,1" line.long 0x34 "IMNTRSR13,INTC-Monitor Status Register 13" hexmask.long.word 0x34 16.--31. 1. "KEYCODE,-" bitfld.long 0x34 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x34 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x34 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x34 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x34 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x34 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x34 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x34 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x34 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x34 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x34 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x34 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x34 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x34 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x34 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x34 0. "WAIT_ERR[x],-" "0,1" line.long 0x38 "IMNTRSR14,INTC-Monitor Status Register 14" hexmask.long.word 0x38 16.--31. 1. "KEYCODE,-" bitfld.long 0x38 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x38 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x38 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x38 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x38 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x38 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x38 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x38 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x38 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x38 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x38 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x38 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x38 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x38 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x38 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x38 0. "WAIT_ERR[x],-" "0,1" line.long 0x3C "IMNTRSR15,INTC-Monitor Status Register 15" hexmask.long.word 0x3C 16.--31. 1. "KEYCODE,-" bitfld.long 0x3C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x3C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x3C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x3C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x3C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x3C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x3C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x3C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x3C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x3C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x3C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x3C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x3C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x3C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x3C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x3C 0. "WAIT_ERR[x],-" "0,1" line.long 0x40 "IMNTRSR16,INTC-Monitor Status Register 16" hexmask.long.word 0x40 16.--31. 1. "KEYCODE,-" bitfld.long 0x40 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x40 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x40 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x40 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x40 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x40 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x40 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x40 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x40 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x40 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x40 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x40 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x40 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x40 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x40 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x40 0. "WAIT_ERR[x],-" "0,1" line.long 0x44 "IMNTRSR17,INTC-Monitor Status Register 17" hexmask.long.word 0x44 16.--31. 1. "KEYCODE,-" bitfld.long 0x44 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x44 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x44 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x44 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x44 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x44 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x44 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x44 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x44 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x44 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x44 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x44 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x44 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x44 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x44 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x44 0. "WAIT_ERR[x],-" "0,1" line.long 0x48 "IMNTRSR18,INTC-Monitor Status Register 18" hexmask.long.word 0x48 16.--31. 1. "KEYCODE,-" bitfld.long 0x48 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x48 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x48 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x48 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x48 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x48 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x48 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x48 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x48 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x48 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x48 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x48 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x48 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x48 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x48 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x48 0. "WAIT_ERR[x],-" "0,1" line.long 0x4C "IMNTRSR19,INTC-Monitor Status Register 19" hexmask.long.word 0x4C 16.--31. 1. "KEYCODE,-" bitfld.long 0x4C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x4C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x4C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x4C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x4C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x4C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x4C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x4C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x4C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x4C 0. "WAIT_ERR[x],-" "0,1" line.long 0x50 "IMNTRSR20,INTC-Monitor Status Register 20" hexmask.long.word 0x50 16.--31. 1. "KEYCODE,-" bitfld.long 0x50 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x50 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x50 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x50 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x50 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x50 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x50 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x50 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x50 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x50 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x50 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x50 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x50 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x50 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x50 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x50 0. "WAIT_ERR[x],-" "0,1" line.long 0x54 "IMNTRSR21,INTC-Monitor Status Register 21" hexmask.long.word 0x54 16.--31. 1. "KEYCODE,-" bitfld.long 0x54 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x54 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x54 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x54 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x54 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x54 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x54 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x54 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x54 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x54 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x54 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x54 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x54 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x54 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x54 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x54 0. "WAIT_ERR[x],-" "0,1" line.long 0x58 "IMNTRSR22,INTC-Monitor Status Register 22" hexmask.long.word 0x58 16.--31. 1. "KEYCODE,-" bitfld.long 0x58 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x58 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x58 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x58 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x58 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x58 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x58 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x58 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x58 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x58 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x58 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x58 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x58 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x58 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x58 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x58 0. "WAIT_ERR[x],-" "0,1" line.long 0x5C "IMNTRSR23,INTC-Monitor Status Register 23" hexmask.long.word 0x5C 16.--31. 1. "KEYCODE,-" bitfld.long 0x5C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x5C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x5C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x5C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x5C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x5C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x5C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x5C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x5C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x5C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x5C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x5C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x5C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x5C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x5C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x5C 0. "WAIT_ERR[x],-" "0,1" line.long 0x60 "IMNTRSR24,INTC-Monitor Status Register 24" hexmask.long.word 0x60 16.--31. 1. "KEYCODE,-" bitfld.long 0x60 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x60 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x60 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x60 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x60 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x60 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x60 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x60 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x60 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x60 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x60 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x60 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x60 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x60 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x60 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x60 0. "WAIT_ERR[x],-" "0,1" line.long 0x64 "IMNTRSR25,INTC-Monitor Status Register 25" hexmask.long.word 0x64 16.--31. 1. "KEYCODE,-" bitfld.long 0x64 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x64 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x64 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x64 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x64 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x64 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x64 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x64 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x64 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x64 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x64 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x64 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x64 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x64 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x64 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x64 0. "WAIT_ERR[x],-" "0,1" line.long 0x68 "IMNTRSR26,INTC-Monitor Status Register 26" hexmask.long.word 0x68 16.--31. 1. "KEYCODE,-" bitfld.long 0x68 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x68 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x68 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x68 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x68 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x68 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x68 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x68 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x68 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x68 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x68 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x68 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x68 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x68 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x68 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x68 0. "WAIT_ERR[x],-" "0,1" line.long 0x6C "IMNTRSR27,INTC-Monitor Status Register 27" hexmask.long.word 0x6C 16.--31. 1. "KEYCODE,-" bitfld.long 0x6C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x6C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x6C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x6C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x6C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x6C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x6C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x6C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x6C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x6C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x6C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x6C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x6C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x6C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x6C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x6C 0. "WAIT_ERR[x],-" "0,1" line.long 0x70 "IMNTRSR28,INTC-Monitor Status Register 28" hexmask.long.word 0x70 16.--31. 1. "KEYCODE,-" bitfld.long 0x70 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x70 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x70 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x70 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x70 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x70 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x70 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x70 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x70 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x70 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x70 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x70 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x70 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x70 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x70 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x70 0. "WAIT_ERR[x],-" "0,1" line.long 0x74 "IMNTRSR29,INTC-Monitor Status Register 29" hexmask.long.word 0x74 16.--31. 1. "KEYCODE,-" bitfld.long 0x74 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x74 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x74 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x74 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x74 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x74 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x74 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x74 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x74 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x74 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x74 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x74 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x74 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x74 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x74 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x74 0. "WAIT_ERR[x],-" "0,1" line.long 0x78 "IMNTRSR30,INTC-Monitor Status Register 30" hexmask.long.word 0x78 16.--31. 1. "KEYCODE,-" bitfld.long 0x78 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x78 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x78 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x78 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x78 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x78 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x78 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x78 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x78 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x78 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x78 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x78 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x78 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x78 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x78 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x78 0. "WAIT_ERR[x],-" "0,1" line.long 0x7C "IMNTRSR31,INTC-Monitor Status Register 31" hexmask.long.word 0x7C 16.--31. 1. "KEYCODE,-" bitfld.long 0x7C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x7C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x7C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x7C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x7C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x7C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x7C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x7C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x7C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x7C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x7C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x7C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x7C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x7C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x7C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x7C 0. "WAIT_ERR[x],-" "0,1" line.long 0x80 "IMNTRSR32,INTC-Monitor Status Register 32" hexmask.long.word 0x80 16.--31. 1. "KEYCODE,-" bitfld.long 0x80 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x80 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x80 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x80 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x80 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x80 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x80 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x80 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x80 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x80 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x80 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x80 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x80 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x80 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x80 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x80 0. "WAIT_ERR[x],-" "0,1" line.long 0x84 "IMNTRSR33,INTC-Monitor Status Register 33" hexmask.long.word 0x84 16.--31. 1. "KEYCODE,-" bitfld.long 0x84 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x84 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x84 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x84 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x84 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x84 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x84 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x84 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x84 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x84 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x84 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x84 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x84 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x84 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x84 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x84 0. "WAIT_ERR[x],-" "0,1" line.long 0x88 "IMNTRSR34,INTC-Monitor Status Register 34" hexmask.long.word 0x88 16.--31. 1. "KEYCODE,-" bitfld.long 0x88 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x88 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x88 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x88 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x88 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x88 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x88 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x88 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x88 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x88 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x88 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x88 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x88 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x88 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x88 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x88 0. "WAIT_ERR[x],-" "0,1" line.long 0x8C "IMNTRSR35,INTC-Monitor Status Register 35" hexmask.long.word 0x8C 16.--31. 1. "KEYCODE,-" bitfld.long 0x8C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x8C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x8C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x8C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x8C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x8C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x8C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x8C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x8C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x8C 0. "WAIT_ERR[x],-" "0,1" line.long 0x90 "IMNTRSR36,INTC-Monitor Status Register 36" hexmask.long.word 0x90 16.--31. 1. "KEYCODE,-" bitfld.long 0x90 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x90 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x90 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x90 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x90 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x90 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x90 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x90 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x90 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x90 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x90 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x90 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x90 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x90 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x90 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x90 0. "WAIT_ERR[x],-" "0,1" line.long 0x94 "IMNTRSR37,INTC-Monitor Status Register 37" hexmask.long.word 0x94 16.--31. 1. "KEYCODE,-" bitfld.long 0x94 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x94 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x94 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x94 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x94 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x94 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x94 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x94 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x94 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x94 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x94 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x94 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x94 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x94 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x94 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x94 0. "WAIT_ERR[x],-" "0,1" line.long 0x98 "IMNTRSR38,INTC-Monitor Status Register 38" hexmask.long.word 0x98 16.--31. 1. "KEYCODE,-" bitfld.long 0x98 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x98 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x98 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x98 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x98 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x98 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x98 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x98 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x98 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x98 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x98 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x98 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x98 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x98 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x98 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x98 0. "WAIT_ERR[x],-" "0,1" line.long 0x9C "IMNTRSR39,INTC-Monitor Status Register 39" hexmask.long.word 0x9C 16.--31. 1. "KEYCODE,-" bitfld.long 0x9C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x9C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x9C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x9C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x9C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x9C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x9C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x9C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x9C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x9C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x9C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x9C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x9C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x9C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x9C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x9C 0. "WAIT_ERR[x],-" "0,1" line.long 0xA0 "IMNTRSR40,INTC-Monitor Status Register 40" hexmask.long.word 0xA0 16.--31. 1. "KEYCODE,-" bitfld.long 0xA0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xA0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xA0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xA0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xA0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xA0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xA0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xA0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xA0 0. "WAIT_ERR[x],-" "0,1" line.long 0xA4 "IMNTRSR41,INTC-Monitor Status Register 41" hexmask.long.word 0xA4 16.--31. 1. "KEYCODE,-" bitfld.long 0xA4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xA4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xA4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xA4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xA4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xA4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xA4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xA4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xA4 0. "WAIT_ERR[x],-" "0,1" line.long 0xA8 "IMNTRSR42,INTC-Monitor Status Register 42" hexmask.long.word 0xA8 16.--31. 1. "KEYCODE,-" bitfld.long 0xA8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xA8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xA8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xA8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xA8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xA8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xA8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xA8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xA8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xA8 0. "WAIT_ERR[x],-" "0,1" line.long 0xAC "IMNTRSR43,INTC-Monitor Status Register 43" hexmask.long.word 0xAC 16.--31. 1. "KEYCODE,-" bitfld.long 0xAC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xAC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xAC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xAC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xAC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xAC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xAC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xAC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xAC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xAC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xAC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xAC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xAC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xAC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xAC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xAC 0. "WAIT_ERR[x],-" "0,1" line.long 0xB0 "IMNTRSR44,INTC-Monitor Status Register 44" hexmask.long.word 0xB0 16.--31. 1. "KEYCODE,-" bitfld.long 0xB0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xB0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xB0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xB0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xB0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xB0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xB0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xB0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xB0 0. "WAIT_ERR[x],-" "0,1" line.long 0xB4 "IMNTRSR45,INTC-Monitor Status Register 45" hexmask.long.word 0xB4 16.--31. 1. "KEYCODE,-" bitfld.long 0xB4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xB4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xB4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xB4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xB4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xB4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xB4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xB4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xB4 0. "WAIT_ERR[x],-" "0,1" line.long 0xB8 "IMNTRSR46,INTC-Monitor Status Register 46" hexmask.long.word 0xB8 16.--31. 1. "KEYCODE,-" bitfld.long 0xB8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xB8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xB8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xB8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xB8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xB8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xB8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xB8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xB8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xB8 0. "WAIT_ERR[x],-" "0,1" line.long 0xBC "IMNTRSR47,INTC-Monitor Status Register 47" hexmask.long.word 0xBC 16.--31. 1. "KEYCODE,-" bitfld.long 0xBC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xBC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xBC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xBC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xBC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xBC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xBC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xBC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xBC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xBC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xBC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xBC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xBC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xBC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xBC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xBC 0. "WAIT_ERR[x],-" "0,1" line.long 0xC0 "IMNTRSR48,INTC-Monitor Status Register 48" hexmask.long.word 0xC0 16.--31. 1. "KEYCODE,-" bitfld.long 0xC0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xC0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xC0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xC0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xC0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xC0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xC0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xC0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xC0 0. "WAIT_ERR[x],-" "0,1" line.long 0xC4 "IMNTRSR49,INTC-Monitor Status Register 49" hexmask.long.word 0xC4 16.--31. 1. "KEYCODE,-" bitfld.long 0xC4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xC4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xC4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xC4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xC4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xC4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xC4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xC4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xC4 0. "WAIT_ERR[x],-" "0,1" line.long 0xC8 "IMNTRSR50,INTC-Monitor Status Register 50" hexmask.long.word 0xC8 16.--31. 1. "KEYCODE,-" bitfld.long 0xC8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xC8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xC8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xC8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xC8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xC8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xC8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xC8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xC8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xC8 0. "WAIT_ERR[x],-" "0,1" line.long 0xCC "IMNTRSR51,INTC-Monitor Status Register 51" hexmask.long.word 0xCC 16.--31. 1. "KEYCODE,-" bitfld.long 0xCC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xCC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xCC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xCC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xCC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xCC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xCC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xCC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xCC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xCC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xCC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xCC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xCC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xCC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xCC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xCC 0. "WAIT_ERR[x],-" "0,1" line.long 0xD0 "IMNTRSR52,INTC-Monitor Status Register 52" hexmask.long.word 0xD0 16.--31. 1. "KEYCODE,-" bitfld.long 0xD0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xD0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xD0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xD0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xD0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xD0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xD0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xD0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xD0 0. "WAIT_ERR[x],-" "0,1" line.long 0xD4 "IMNTRSR53,INTC-Monitor Status Register 53" hexmask.long.word 0xD4 16.--31. 1. "KEYCODE,-" bitfld.long 0xD4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xD4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xD4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xD4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xD4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xD4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xD4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xD4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xD4 0. "WAIT_ERR[x],-" "0,1" line.long 0xD8 "IMNTRSR54,INTC-Monitor Status Register 54" hexmask.long.word 0xD8 16.--31. 1. "KEYCODE,-" bitfld.long 0xD8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xD8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xD8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xD8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xD8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xD8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xD8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xD8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xD8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xD8 0. "WAIT_ERR[x],-" "0,1" line.long 0xDC "IMNTRSR55,INTC-Monitor Status Register 55" hexmask.long.word 0xDC 16.--31. 1. "KEYCODE,-" bitfld.long 0xDC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xDC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xDC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xDC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xDC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xDC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xDC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xDC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xDC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xDC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xDC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xDC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xDC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xDC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xDC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xDC 0. "WAIT_ERR[x],-" "0,1" line.long 0xE0 "IMNTRSR56,INTC-Monitor Status Register 56" hexmask.long.word 0xE0 16.--31. 1. "KEYCODE,-" bitfld.long 0xE0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xE0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xE0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xE0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xE0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xE0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xE0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xE0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xE0 0. "WAIT_ERR[x],-" "0,1" line.long 0xE4 "IMNTRSR57,INTC-Monitor Status Register 57" hexmask.long.word 0xE4 16.--31. 1. "KEYCODE,-" bitfld.long 0xE4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xE4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xE4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xE4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xE4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xE4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xE4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xE4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xE4 0. "WAIT_ERR[x],-" "0,1" line.long 0xE8 "IMNTRSR58,INTC-Monitor Status Register 58" hexmask.long.word 0xE8 16.--31. 1. "KEYCODE,-" bitfld.long 0xE8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xE8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xE8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xE8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xE8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xE8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xE8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xE8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xE8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xE8 0. "WAIT_ERR[x],-" "0,1" line.long 0xEC "IMNTRSR59,INTC-Monitor Status Register 59" hexmask.long.word 0xEC 16.--31. 1. "KEYCODE,-" bitfld.long 0xEC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xEC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xEC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xEC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xEC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xEC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xEC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xEC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xEC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xEC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xEC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xEC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xEC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xEC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xEC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xEC 0. "WAIT_ERR[x],-" "0,1" line.long 0xF0 "IMNTRSR60,INTC-Monitor Status Register 60" hexmask.long.word 0xF0 16.--31. 1. "KEYCODE,-" bitfld.long 0xF0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xF0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xF0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xF0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xF0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xF0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xF0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xF0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xF0 0. "WAIT_ERR[x],-" "0,1" line.long 0xF4 "IMNTRSR61,INTC-Monitor Status Register 61" hexmask.long.word 0xF4 16.--31. 1. "KEYCODE,-" bitfld.long 0xF4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xF4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xF4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xF4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xF4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xF4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xF4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xF4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xF4 0. "WAIT_ERR[x],-" "0,1" line.long 0xF8 "IMNTRSR62,INTC-Monitor Status Register 62" hexmask.long.word 0xF8 16.--31. 1. "KEYCODE,-" bitfld.long 0xF8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xF8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xF8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xF8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xF8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xF8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xF8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xF8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xF8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xF8 0. "WAIT_ERR[x],-" "0,1" line.long 0xFC "IMNTRSR63,INTC-Monitor Status Register 63" hexmask.long.word 0xFC 16.--31. 1. "KEYCODE,-" bitfld.long 0xFC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0xFC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0xFC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0xFC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0xFC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0xFC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0xFC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xFC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0xFC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0xFC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0xFC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0xFC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0xFC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0xFC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0xFC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0xFC 0. "WAIT_ERR[x],-" "0,1" line.long 0x100 "IMNTRSR64,INTC-Monitor Status Register 64" hexmask.long.word 0x100 16.--31. 1. "KEYCODE,-" bitfld.long 0x100 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x100 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x100 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x100 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x100 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x100 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x100 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x100 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x100 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x100 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x100 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x100 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x100 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x100 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x100 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x100 0. "WAIT_ERR[x],-" "0,1" line.long 0x104 "IMNTRSR65,INTC-Monitor Status Register 65" hexmask.long.word 0x104 16.--31. 1. "KEYCODE,-" bitfld.long 0x104 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x104 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x104 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x104 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x104 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x104 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x104 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x104 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x104 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x104 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x104 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x104 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x104 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x104 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x104 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x104 0. "WAIT_ERR[x],-" "0,1" line.long 0x108 "IMNTRSR66,INTC-Monitor Status Register 66" hexmask.long.word 0x108 16.--31. 1. "KEYCODE,-" bitfld.long 0x108 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x108 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x108 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x108 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x108 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x108 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x108 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x108 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x108 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x108 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x108 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x108 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x108 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x108 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x108 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x108 0. "WAIT_ERR[x],-" "0,1" line.long 0x10C "IMNTRSR67,INTC-Monitor Status Register 67" hexmask.long.word 0x10C 16.--31. 1. "KEYCODE,-" bitfld.long 0x10C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x10C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x10C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x10C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x10C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x10C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x10C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x10C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x10C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x10C 0. "WAIT_ERR[x],-" "0,1" line.long 0x110 "IMNTRSR68,INTC-Monitor Status Register 68" hexmask.long.word 0x110 16.--31. 1. "KEYCODE,-" bitfld.long 0x110 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x110 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x110 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x110 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x110 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x110 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x110 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x110 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x110 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x110 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x110 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x110 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x110 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x110 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x110 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x110 0. "WAIT_ERR[x],-" "0,1" line.long 0x114 "IMNTRSR69,INTC-Monitor Status Register 69" hexmask.long.word 0x114 16.--31. 1. "KEYCODE,-" bitfld.long 0x114 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x114 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x114 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x114 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x114 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x114 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x114 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x114 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x114 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x114 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x114 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x114 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x114 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x114 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x114 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x114 0. "WAIT_ERR[x],-" "0,1" line.long 0x118 "IMNTRSR70,INTC-Monitor Status Register 70" hexmask.long.word 0x118 16.--31. 1. "KEYCODE,-" bitfld.long 0x118 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x118 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x118 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x118 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x118 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x118 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x118 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x118 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x118 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x118 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x118 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x118 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x118 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x118 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x118 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x118 0. "WAIT_ERR[x],-" "0,1" line.long 0x11C "IMNTRSR71,INTC-Monitor Status Register 71" hexmask.long.word 0x11C 16.--31. 1. "KEYCODE,-" bitfld.long 0x11C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x11C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x11C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x11C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x11C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x11C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x11C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x11C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x11C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x11C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x11C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x11C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x11C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x11C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x11C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x11C 0. "WAIT_ERR[x],-" "0,1" line.long 0x120 "IMNTRSR72,INTC-Monitor Status Register 72" hexmask.long.word 0x120 16.--31. 1. "KEYCODE,-" bitfld.long 0x120 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x120 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x120 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x120 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x120 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x120 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x120 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x120 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x120 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x120 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x120 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x120 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x120 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x120 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x120 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x120 0. "WAIT_ERR[x],-" "0,1" line.long 0x124 "IMNTRSR73,INTC-Monitor Status Register 73" hexmask.long.word 0x124 16.--31. 1. "KEYCODE,-" bitfld.long 0x124 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x124 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x124 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x124 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x124 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x124 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x124 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x124 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x124 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x124 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x124 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x124 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x124 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x124 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x124 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x124 0. "WAIT_ERR[x],-" "0,1" line.long 0x128 "IMNTRSR74,INTC-Monitor Status Register 74" hexmask.long.word 0x128 16.--31. 1. "KEYCODE,-" bitfld.long 0x128 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x128 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x128 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x128 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x128 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x128 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x128 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x128 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x128 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x128 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x128 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x128 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x128 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x128 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x128 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x128 0. "WAIT_ERR[x],-" "0,1" line.long 0x12C "IMNTRSR75,INTC-Monitor Status Register 75" hexmask.long.word 0x12C 16.--31. 1. "KEYCODE,-" bitfld.long 0x12C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x12C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x12C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x12C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x12C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x12C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x12C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x12C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x12C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x12C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x12C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x12C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x12C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x12C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x12C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x12C 0. "WAIT_ERR[x],-" "0,1" line.long 0x130 "IMNTRSR76,INTC-Monitor Status Register 76" hexmask.long.word 0x130 16.--31. 1. "KEYCODE,-" bitfld.long 0x130 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x130 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x130 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x130 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x130 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x130 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x130 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x130 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x130 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x130 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x130 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x130 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x130 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x130 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x130 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x130 0. "WAIT_ERR[x],-" "0,1" line.long 0x134 "IMNTRSR77,INTC-Monitor Status Register 77" hexmask.long.word 0x134 16.--31. 1. "KEYCODE,-" bitfld.long 0x134 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x134 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x134 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x134 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x134 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x134 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x134 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x134 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x134 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x134 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x134 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x134 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x134 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x134 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x134 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x134 0. "WAIT_ERR[x],-" "0,1" line.long 0x138 "IMNTRSR78,INTC-Monitor Status Register 78" hexmask.long.word 0x138 16.--31. 1. "KEYCODE,-" bitfld.long 0x138 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x138 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x138 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x138 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x138 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x138 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x138 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x138 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x138 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x138 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x138 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x138 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x138 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x138 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x138 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x138 0. "WAIT_ERR[x],-" "0,1" line.long 0x13C "IMNTRSR79,INTC-Monitor Status Register 79" hexmask.long.word 0x13C 16.--31. 1. "KEYCODE,-" bitfld.long 0x13C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x13C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x13C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x13C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x13C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x13C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x13C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x13C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x13C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x13C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x13C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x13C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x13C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x13C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x13C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x13C 0. "WAIT_ERR[x],-" "0,1" line.long 0x140 "IMNTRSR80,INTC-Monitor Status Register 80" hexmask.long.word 0x140 16.--31. 1. "KEYCODE,-" bitfld.long 0x140 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x140 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x140 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x140 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x140 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x140 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x140 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x140 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x140 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x140 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x140 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x140 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x140 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x140 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x140 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x140 0. "WAIT_ERR[x],-" "0,1" line.long 0x144 "IMNTRSR81,INTC-Monitor Status Register 81" hexmask.long.word 0x144 16.--31. 1. "KEYCODE,-" bitfld.long 0x144 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x144 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x144 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x144 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x144 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x144 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x144 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x144 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x144 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x144 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x144 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x144 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x144 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x144 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x144 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x144 0. "WAIT_ERR[x],-" "0,1" line.long 0x148 "IMNTRSR82,INTC-Monitor Status Register 82" hexmask.long.word 0x148 16.--31. 1. "KEYCODE,-" bitfld.long 0x148 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x148 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x148 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x148 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x148 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x148 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x148 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x148 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x148 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x148 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x148 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x148 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x148 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x148 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x148 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x148 0. "WAIT_ERR[x],-" "0,1" line.long 0x14C "IMNTRSR83,INTC-Monitor Status Register 83" hexmask.long.word 0x14C 16.--31. 1. "KEYCODE,-" bitfld.long 0x14C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x14C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x14C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x14C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x14C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x14C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x14C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x14C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x14C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x14C 0. "WAIT_ERR[x],-" "0,1" line.long 0x150 "IMNTRSR84,INTC-Monitor Status Register 84" hexmask.long.word 0x150 16.--31. 1. "KEYCODE,-" bitfld.long 0x150 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x150 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x150 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x150 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x150 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x150 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x150 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x150 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x150 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x150 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x150 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x150 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x150 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x150 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x150 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x150 0. "WAIT_ERR[x],-" "0,1" line.long 0x154 "IMNTRSR85,INTC-Monitor Status Register 85" hexmask.long.word 0x154 16.--31. 1. "KEYCODE,-" bitfld.long 0x154 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x154 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x154 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x154 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x154 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x154 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x154 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x154 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x154 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x154 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x154 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x154 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x154 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x154 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x154 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x154 0. "WAIT_ERR[x],-" "0,1" line.long 0x158 "IMNTRSR86,INTC-Monitor Status Register 86" hexmask.long.word 0x158 16.--31. 1. "KEYCODE,-" bitfld.long 0x158 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x158 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x158 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x158 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x158 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x158 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x158 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x158 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x158 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x158 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x158 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x158 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x158 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x158 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x158 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x158 0. "WAIT_ERR[x],-" "0,1" line.long 0x15C "IMNTRSR87,INTC-Monitor Status Register 87" hexmask.long.word 0x15C 16.--31. 1. "KEYCODE,-" bitfld.long 0x15C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x15C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x15C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x15C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x15C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x15C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x15C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x15C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x15C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x15C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x15C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x15C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x15C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x15C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x15C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x15C 0. "WAIT_ERR[x],-" "0,1" line.long 0x160 "IMNTRSR88,INTC-Monitor Status Register 88" hexmask.long.word 0x160 16.--31. 1. "KEYCODE,-" bitfld.long 0x160 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x160 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x160 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x160 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x160 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x160 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x160 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x160 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x160 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x160 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x160 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x160 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x160 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x160 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x160 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x160 0. "WAIT_ERR[x],-" "0,1" line.long 0x164 "IMNTRSR89,INTC-Monitor Status Register 89" hexmask.long.word 0x164 16.--31. 1. "KEYCODE,-" bitfld.long 0x164 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x164 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x164 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x164 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x164 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x164 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x164 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x164 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x164 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x164 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x164 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x164 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x164 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x164 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x164 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x164 0. "WAIT_ERR[x],-" "0,1" line.long 0x168 "IMNTRSR90,INTC-Monitor Status Register 90" hexmask.long.word 0x168 16.--31. 1. "KEYCODE,-" bitfld.long 0x168 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x168 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x168 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x168 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x168 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x168 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x168 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x168 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x168 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x168 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x168 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x168 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x168 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x168 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x168 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x168 0. "WAIT_ERR[x],-" "0,1" line.long 0x16C "IMNTRSR91,INTC-Monitor Status Register 91" hexmask.long.word 0x16C 16.--31. 1. "KEYCODE,-" bitfld.long 0x16C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x16C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x16C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x16C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x16C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x16C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x16C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x16C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x16C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x16C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x16C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x16C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x16C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x16C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x16C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x16C 0. "WAIT_ERR[x],-" "0,1" line.long 0x170 "IMNTRSR92,INTC-Monitor Status Register 92" hexmask.long.word 0x170 16.--31. 1. "KEYCODE,-" bitfld.long 0x170 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x170 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x170 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x170 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x170 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x170 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x170 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x170 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x170 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x170 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x170 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x170 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x170 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x170 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x170 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x170 0. "WAIT_ERR[x],-" "0,1" line.long 0x174 "IMNTRSR93,INTC-Monitor Status Register 93" hexmask.long.word 0x174 16.--31. 1. "KEYCODE,-" bitfld.long 0x174 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x174 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x174 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x174 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x174 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x174 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x174 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x174 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x174 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x174 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x174 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x174 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x174 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x174 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x174 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x174 0. "WAIT_ERR[x],-" "0,1" line.long 0x178 "IMNTRSR94,INTC-Monitor Status Register 94" hexmask.long.word 0x178 16.--31. 1. "KEYCODE,-" bitfld.long 0x178 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x178 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x178 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x178 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x178 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x178 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x178 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x178 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x178 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x178 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x178 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x178 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x178 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x178 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x178 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x178 0. "WAIT_ERR[x],-" "0,1" line.long 0x17C "IMNTRSR95,INTC-Monitor Status Register 95" hexmask.long.word 0x17C 16.--31. 1. "KEYCODE,-" bitfld.long 0x17C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x17C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x17C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x17C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x17C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x17C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x17C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x17C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x17C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x17C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x17C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x17C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x17C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x17C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x17C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x17C 0. "WAIT_ERR[x],-" "0,1" line.long 0x180 "IMNTRSR96,INTC-Monitor Status Register 96" hexmask.long.word 0x180 16.--31. 1. "KEYCODE,-" bitfld.long 0x180 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x180 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x180 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x180 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x180 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x180 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x180 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x180 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x180 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x180 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x180 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x180 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x180 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x180 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x180 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x180 0. "WAIT_ERR[x],-" "0,1" line.long 0x184 "IMNTRSR97,INTC-Monitor Status Register 97" hexmask.long.word 0x184 16.--31. 1. "KEYCODE,-" bitfld.long 0x184 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x184 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x184 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x184 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x184 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x184 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x184 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x184 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x184 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x184 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x184 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x184 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x184 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x184 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x184 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x184 0. "WAIT_ERR[x],-" "0,1" line.long 0x188 "IMNTRSR98,INTC-Monitor Status Register 98" hexmask.long.word 0x188 16.--31. 1. "KEYCODE,-" bitfld.long 0x188 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x188 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x188 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x188 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x188 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x188 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x188 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x188 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x188 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x188 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x188 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x188 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x188 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x188 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x188 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x188 0. "WAIT_ERR[x],-" "0,1" line.long 0x18C "IMNTRSR99,INTC-Monitor Status Register 99" hexmask.long.word 0x18C 16.--31. 1. "KEYCODE,-" bitfld.long 0x18C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x18C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x18C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x18C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x18C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x18C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x18C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x18C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x18C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x18C 0. "WAIT_ERR[x],-" "0,1" line.long 0x190 "IMNTRSR100,INTC-Monitor Status Register 100" hexmask.long.word 0x190 16.--31. 1. "KEYCODE,-" bitfld.long 0x190 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x190 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x190 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x190 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x190 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x190 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x190 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x190 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x190 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x190 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x190 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x190 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x190 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x190 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x190 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x190 0. "WAIT_ERR[x],-" "0,1" line.long 0x194 "IMNTRSR101,INTC-Monitor Status Register 101" hexmask.long.word 0x194 16.--31. 1. "KEYCODE,-" bitfld.long 0x194 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x194 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x194 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x194 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x194 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x194 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x194 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x194 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x194 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x194 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x194 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x194 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x194 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x194 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x194 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x194 0. "WAIT_ERR[x],-" "0,1" line.long 0x198 "IMNTRSR102,INTC-Monitor Status Register 102" hexmask.long.word 0x198 16.--31. 1. "KEYCODE,-" bitfld.long 0x198 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x198 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x198 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x198 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x198 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x198 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x198 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x198 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x198 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x198 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x198 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x198 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x198 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x198 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x198 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x198 0. "WAIT_ERR[x],-" "0,1" line.long 0x19C "IMNTRSR103,INTC-Monitor Status Register 103" hexmask.long.word 0x19C 16.--31. 1. "KEYCODE,-" bitfld.long 0x19C 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x19C 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x19C 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x19C 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x19C 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x19C 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x19C 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x19C 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x19C 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x19C 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x19C 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x19C 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x19C 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x19C 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x19C 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x19C 0. "WAIT_ERR[x],-" "0,1" line.long 0x1A0 "IMNTRSR104,INTC-Monitor Status Register 104" hexmask.long.word 0x1A0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1A0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1A0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1A0 0. "WAIT_ERR[x],-" "0,1" line.long 0x1A4 "IMNTRSR105,INTC-Monitor Status Register 105" hexmask.long.word 0x1A4 16.--31. 1. "KEYCODE,-" bitfld.long 0x1A4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1A4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1A4 0. "WAIT_ERR[x],-" "0,1" line.long 0x1A8 "IMNTRSR106,INTC-Monitor Status Register 106" hexmask.long.word 0x1A8 16.--31. 1. "KEYCODE,-" bitfld.long 0x1A8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1A8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1A8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1A8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1A8 0. "WAIT_ERR[x],-" "0,1" line.long 0x1AC "IMNTRSR107,INTC-Monitor Status Register 107" hexmask.long.word 0x1AC 16.--31. 1. "KEYCODE,-" bitfld.long 0x1AC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1AC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1AC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1AC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1AC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1AC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1AC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1AC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1AC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1AC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1AC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1AC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1AC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1AC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1AC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1AC 0. "WAIT_ERR[x],-" "0,1" line.long 0x1B0 "IMNTRSR108,INTC-Monitor Status Register 108" hexmask.long.word 0x1B0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1B0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1B0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1B0 0. "WAIT_ERR[x],-" "0,1" line.long 0x1B4 "IMNTRSR109,INTC-Monitor Status Register 109" hexmask.long.word 0x1B4 16.--31. 1. "KEYCODE,-" bitfld.long 0x1B4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1B4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1B4 0. "WAIT_ERR[x],-" "0,1" line.long 0x1B8 "IMNTRSR110,INTC-Monitor Status Register 110" hexmask.long.word 0x1B8 16.--31. 1. "KEYCODE,-" bitfld.long 0x1B8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1B8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1B8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1B8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1B8 0. "WAIT_ERR[x],-" "0,1" line.long 0x1BC "IMNTRSR111,INTC-Monitor Status Register 111" hexmask.long.word 0x1BC 16.--31. 1. "KEYCODE,-" bitfld.long 0x1BC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1BC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1BC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1BC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1BC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1BC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1BC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1BC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1BC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1BC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1BC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1BC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1BC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1BC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1BC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1BC 0. "WAIT_ERR[x],-" "0,1" line.long 0x1C0 "IMNTRSR112,INTC-Monitor Status Register 112" hexmask.long.word 0x1C0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1C0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1C0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1C0 0. "WAIT_ERR[x],-" "0,1" line.long 0x1C4 "IMNTRSR113,INTC-Monitor Status Register 113" hexmask.long.word 0x1C4 16.--31. 1. "KEYCODE,-" bitfld.long 0x1C4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1C4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1C4 0. "WAIT_ERR[x],-" "0,1" line.long 0x1C8 "IMNTRSR114,INTC-Monitor Status Register 114" hexmask.long.word 0x1C8 16.--31. 1. "KEYCODE,-" bitfld.long 0x1C8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1C8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1C8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1C8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1C8 0. "WAIT_ERR[x],-" "0,1" line.long 0x1CC "IMNTRSR115,INTC-Monitor Status Register 115" hexmask.long.word 0x1CC 16.--31. 1. "KEYCODE,-" bitfld.long 0x1CC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1CC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1CC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1CC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1CC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1CC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1CC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1CC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1CC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1CC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1CC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1CC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1CC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1CC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1CC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1CC 0. "WAIT_ERR[x],-" "0,1" line.long 0x1D0 "IMNTRSR116,INTC-Monitor Status Register 116" hexmask.long.word 0x1D0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1D0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1D0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1D0 0. "WAIT_ERR[x],-" "0,1" line.long 0x1D4 "IMNTRSR117,INTC-Monitor Status Register 117" hexmask.long.word 0x1D4 16.--31. 1. "KEYCODE,-" bitfld.long 0x1D4 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D4 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D4 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D4 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D4 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D4 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D4 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1D4 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D4 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D4 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D4 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D4 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D4 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D4 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D4 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1D4 0. "WAIT_ERR[x],-" "0,1" line.long 0x1D8 "IMNTRSR118,INTC-Monitor Status Register 118" hexmask.long.word 0x1D8 16.--31. 1. "KEYCODE,-" bitfld.long 0x1D8 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D8 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D8 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D8 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D8 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D8 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D8 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1D8 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D8 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D8 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D8 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D8 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D8 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1D8 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1D8 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1D8 0. "WAIT_ERR[x],-" "0,1" line.long 0x1DC "IMNTRSR119,INTC-Monitor Status Register 119" hexmask.long.word 0x1DC 16.--31. 1. "KEYCODE,-" bitfld.long 0x1DC 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1DC 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1DC 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1DC 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1DC 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1DC 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1DC 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1DC 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1DC 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1DC 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1DC 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1DC 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1DC 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1DC 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1DC 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1DC 0. "WAIT_ERR[x],-" "0,1" line.long 0x1E0 "IMNTRSR120,INTC-Monitor Status Register 120" hexmask.long.word 0x1E0 16.--31. 1. "KEYCODE,-" bitfld.long 0x1E0 15. "CNT_ERR[x],-" "0,1" bitfld.long 0x1E0 14. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1E0 13. "CNT_ERR[x],-" "0,1" bitfld.long 0x1E0 12. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1E0 11. "CNT_ERR[x],-" "0,1" bitfld.long 0x1E0 10. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1E0 9. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1E0 8. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1E0 7. "CNT_ERR[x],-" "0,1" bitfld.long 0x1E0 6. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1E0 5. "CNT_ERR[x],-" "0,1" bitfld.long 0x1E0 4. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1E0 3. "CNT_ERR[x],-" "0,1" bitfld.long 0x1E0 2. "WAIT_ERR[x],-" "0,1" bitfld.long 0x1E0 1. "CNT_ERR[x],-" "0,1" newline bitfld.long 0x1E0 0. "WAIT_ERR[x],-" "0,1" rgroup.long 0x6000++0xF3 line.long 0x0 "IMNTRRTR0,INTC-Monitor Runtime Test Register 0" bitfld.long 0x0 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x0 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x0 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x0 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x0 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x0 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x0 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x0 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x0 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x0 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x0 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x0 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x0 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x0 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x0 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x0 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x4 "IMNTRRTR1,INTC-Monitor Runtime Test Register 1" bitfld.long 0x4 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x4 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x4 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x4 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x4 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x4 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x4 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x4 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x4 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x4 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x4 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x4 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x4 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x4 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x4 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x4 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x8 "IMNTRRTR2,INTC-Monitor Runtime Test Register 2" bitfld.long 0x8 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x8 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x8 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x8 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x8 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x8 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x8 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x8 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x8 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x8 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x8 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x8 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x8 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x8 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x8 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x8 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xC "IMNTRRTR3,INTC-Monitor Runtime Test Register 3" bitfld.long 0xC 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xC 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xC 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xC 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xC 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xC 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xC 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xC 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xC 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xC 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xC 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xC 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xC 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xC 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xC 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xC 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x10 "IMNTRRTR4,INTC-Monitor Runtime Test Register 4" bitfld.long 0x10 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x10 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x10 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x10 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x10 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x10 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x10 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x10 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x10 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x10 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x10 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x10 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x10 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x10 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x10 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x10 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x14 "IMNTRRTR5,INTC-Monitor Runtime Test Register 5" bitfld.long 0x14 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x14 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x14 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x14 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x14 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x14 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x14 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x14 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x14 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x14 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x14 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x14 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x14 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x14 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x14 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x14 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x18 "IMNTRRTR6,INTC-Monitor Runtime Test Register 6" bitfld.long 0x18 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x18 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x18 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x18 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x18 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x18 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x18 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x18 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x18 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x18 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x18 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x18 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x18 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x18 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x18 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x18 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x1C "IMNTRRTR7,INTC-Monitor Runtime Test Register 7" bitfld.long 0x1C 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x1C 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x1C 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x1C 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x1C 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x1C 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x1C 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x1C 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x1C 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x1C 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x1C 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x1C 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x1C 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x1C 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x1C 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x1C 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x20 "IMNTRRTR8,INTC-Monitor Runtime Test Register 8" bitfld.long 0x20 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x20 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x20 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x20 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x20 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x20 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x20 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x20 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x20 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x20 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x20 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x20 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x20 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x20 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x20 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x20 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x24 "IMNTRRTR9,INTC-Monitor Runtime Test Register 9" bitfld.long 0x24 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x24 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x24 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x24 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x24 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x24 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x24 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x24 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x24 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x24 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x24 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x24 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x24 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x24 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x24 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x24 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x28 "IMNTRRTR10,INTC-Monitor Runtime Test Register 10" bitfld.long 0x28 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x28 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x28 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x28 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x28 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x28 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x28 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x28 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x28 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x28 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x28 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x28 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x28 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x28 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x28 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x28 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x2C "IMNTRRTR11,INTC-Monitor Runtime Test Register 11" bitfld.long 0x2C 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x2C 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x2C 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x2C 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x2C 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x2C 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x2C 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x2C 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x2C 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x2C 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x2C 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x2C 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x2C 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x2C 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x2C 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x2C 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x30 "IMNTRRTR12,INTC-Monitor Runtime Test Register 12" bitfld.long 0x30 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x30 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x30 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x30 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x30 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x30 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x30 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x30 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x30 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x30 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x30 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x30 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x30 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x30 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x30 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x30 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x34 "IMNTRRTR13,INTC-Monitor Runtime Test Register 13" bitfld.long 0x34 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x34 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x34 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x34 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x34 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x34 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x34 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x34 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x34 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x34 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x34 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x34 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x34 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x34 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x34 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x34 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x38 "IMNTRRTR14,INTC-Monitor Runtime Test Register 14" bitfld.long 0x38 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x38 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x38 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x38 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x38 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x38 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x38 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x38 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x38 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x38 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x38 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x38 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x38 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x38 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x38 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x38 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x3C "IMNTRRTR15,INTC-Monitor Runtime Test Register 15" bitfld.long 0x3C 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x3C 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x3C 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x3C 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x3C 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x3C 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x3C 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x3C 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x3C 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x3C 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x3C 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x3C 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x3C 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x3C 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x3C 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x3C 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x40 "IMNTRRTR16,INTC-Monitor Runtime Test Register 16" bitfld.long 0x40 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x40 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x40 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x40 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x40 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x40 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x40 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x40 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x40 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x40 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x40 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x40 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x40 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x40 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x40 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x40 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x44 "IMNTRRTR17,INTC-Monitor Runtime Test Register 17" bitfld.long 0x44 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x44 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x44 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x44 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x44 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x44 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x44 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x44 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x44 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x44 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x44 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x44 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x44 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x44 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x44 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x44 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x48 "IMNTRRTR18,INTC-Monitor Runtime Test Register 18" bitfld.long 0x48 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x48 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x48 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x48 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x48 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x48 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x48 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x48 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x48 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x48 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x48 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x48 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x48 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x48 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x48 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x48 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x4C "IMNTRRTR19,INTC-Monitor Runtime Test Register 19" bitfld.long 0x4C 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x4C 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x4C 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x4C 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x4C 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x4C 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x4C 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x4C 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x4C 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x4C 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x4C 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x4C 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x4C 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x4C 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x4C 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x4C 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x50 "IMNTRRTR20,INTC-Monitor Runtime Test Register 20" bitfld.long 0x50 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x50 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x50 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x50 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x50 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x50 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x50 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x50 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x50 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x50 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x50 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x50 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x50 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x50 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x50 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x50 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x54 "IMNTRRTR21,INTC-Monitor Runtime Test Register 21" bitfld.long 0x54 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x54 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x54 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x54 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x54 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x54 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x54 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x54 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x54 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x54 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x54 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x54 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x54 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x54 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x54 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x54 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x58 "IMNTRRTR22,INTC-Monitor Runtime Test Register 22" bitfld.long 0x58 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x58 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x58 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x58 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x58 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x58 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x58 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x58 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x58 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x58 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x58 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x58 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x58 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x58 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x58 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x58 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x5C "IMNTRRTR23,INTC-Monitor Runtime Test Register 23" bitfld.long 0x5C 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x5C 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x5C 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x5C 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x5C 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x5C 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x5C 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x5C 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x5C 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x5C 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x5C 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x5C 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x5C 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x5C 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x5C 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x5C 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x60 "IMNTRRTR24,INTC-Monitor Runtime Test Register 24" bitfld.long 0x60 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x60 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x60 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x60 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x60 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x60 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x60 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x60 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x60 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x60 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x60 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x60 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x60 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x60 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x60 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x60 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x64 "IMNTRRTR25,INTC-Monitor Runtime Test Register 25" bitfld.long 0x64 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x64 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x64 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x64 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x64 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x64 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x64 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x64 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x64 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x64 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x64 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x64 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x64 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x64 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x64 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x64 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x68 "IMNTRRTR26,INTC-Monitor Runtime Test Register 26" bitfld.long 0x68 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x68 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x68 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x68 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x68 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x68 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x68 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x68 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x68 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x68 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x68 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x68 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x68 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x68 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x68 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x68 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x6C "IMNTRRTR27,INTC-Monitor Runtime Test Register 27" bitfld.long 0x6C 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x6C 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x6C 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x6C 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x6C 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x6C 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x6C 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x6C 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x6C 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x6C 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x6C 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x6C 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x6C 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x6C 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x6C 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x6C 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x70 "IMNTRRTR28,INTC-Monitor Runtime Test Register 28" bitfld.long 0x70 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x70 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x70 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x70 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x70 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x70 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x70 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x70 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x70 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x70 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x70 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x70 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x70 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x70 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x70 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x70 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x74 "IMNTRRTR29,INTC-Monitor Runtime Test Register 29" bitfld.long 0x74 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x74 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x74 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x74 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x74 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x74 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x74 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x74 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x74 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x74 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x74 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x74 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x74 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x74 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x74 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x74 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x78 "IMNTRRTR30,INTC-Monitor Runtime Test Register 30" bitfld.long 0x78 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x78 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x78 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x78 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x78 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x78 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x78 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x78 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x78 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x78 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x78 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x78 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x78 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x78 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x78 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x78 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x7C "IMNTRRTR31,INTC-Monitor Runtime Test Register 31" bitfld.long 0x7C 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x7C 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x7C 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x7C 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x7C 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x7C 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x7C 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x7C 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x7C 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x7C 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x7C 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x7C 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x7C 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x7C 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x7C 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x7C 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x80 "IMNTRRTR32,INTC-Monitor Runtime Test Register 32" bitfld.long 0x80 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x80 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x80 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x80 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x80 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x80 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x80 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x80 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x80 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x80 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x80 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x80 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x80 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x80 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x80 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x80 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x84 "IMNTRRTR33,INTC-Monitor Runtime Test Register 33" bitfld.long 0x84 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x84 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x84 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x84 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x84 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x84 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x84 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x84 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x84 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x84 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x84 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x84 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x84 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x84 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x84 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x84 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x88 "IMNTRRTR34,INTC-Monitor Runtime Test Register 34" bitfld.long 0x88 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x88 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x88 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x88 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x88 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x88 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x88 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x88 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x88 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x88 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x88 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x88 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x88 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x88 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x88 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x88 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x8C "IMNTRRTR35,INTC-Monitor Runtime Test Register 35" bitfld.long 0x8C 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x8C 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x8C 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x8C 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x8C 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x8C 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x8C 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x8C 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x8C 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x8C 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x8C 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x8C 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x8C 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x8C 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x8C 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x8C 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x90 "IMNTRRTR36,INTC-Monitor Runtime Test Register 36" bitfld.long 0x90 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x90 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x90 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x90 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x90 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x90 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x90 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x90 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x90 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x90 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x90 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x90 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x90 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x90 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x90 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x90 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x94 "IMNTRRTR37,INTC-Monitor Runtime Test Register 37" bitfld.long 0x94 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x94 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x94 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x94 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x94 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x94 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x94 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x94 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x94 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x94 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x94 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x94 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x94 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x94 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x94 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x94 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x98 "IMNTRRTR38,INTC-Monitor Runtime Test Register 38" bitfld.long 0x98 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x98 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x98 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x98 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x98 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x98 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x98 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x98 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x98 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x98 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x98 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x98 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x98 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x98 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x98 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x98 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0x9C "IMNTRRTR39,INTC-Monitor Runtime Test Register 39" bitfld.long 0x9C 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0x9C 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0x9C 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0x9C 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0x9C 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0x9C 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0x9C 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0x9C 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0x9C 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0x9C 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0x9C 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0x9C 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0x9C 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0x9C 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0x9C 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0x9C 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xA0 "IMNTRRTR40,INTC-Monitor Runtime Test Register 40" bitfld.long 0xA0 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xA0 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xA0 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xA0 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xA0 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xA0 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xA0 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xA0 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xA0 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xA0 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xA0 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xA0 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xA0 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xA0 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xA0 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xA0 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xA4 "IMNTRRTR41,INTC-Monitor Runtime Test Register 41" bitfld.long 0xA4 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xA4 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xA4 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xA4 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xA4 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xA4 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xA4 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xA4 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xA4 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xA4 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xA4 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xA4 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xA4 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xA4 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xA4 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xA4 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xA8 "IMNTRRTR42,INTC-Monitor Runtime Test Register 42" bitfld.long 0xA8 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xA8 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xA8 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xA8 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xA8 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xA8 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xA8 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xA8 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xA8 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xA8 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xA8 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xA8 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xA8 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xA8 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xA8 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xA8 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xAC "IMNTRRTR43,INTC-Monitor Runtime Test Register 43" bitfld.long 0xAC 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xAC 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xAC 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xAC 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xAC 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xAC 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xAC 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xAC 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xAC 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xAC 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xAC 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xAC 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xAC 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xAC 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xAC 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xAC 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xB0 "IMNTRRTR44,INTC-Monitor Runtime Test Register 44" bitfld.long 0xB0 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xB0 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xB0 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xB0 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xB0 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xB0 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xB0 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xB0 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xB0 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xB0 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xB0 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xB0 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xB0 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xB0 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xB0 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xB0 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xB4 "IMNTRRTR45,INTC-Monitor Runtime Test Register 45" bitfld.long 0xB4 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xB4 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xB4 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xB4 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xB4 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xB4 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xB4 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xB4 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xB4 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xB4 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xB4 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xB4 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xB4 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xB4 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xB4 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xB4 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xB8 "IMNTRRTR46,INTC-Monitor Runtime Test Register 46" bitfld.long 0xB8 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xB8 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xB8 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xB8 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xB8 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xB8 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xB8 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xB8 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xB8 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xB8 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xB8 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xB8 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xB8 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xB8 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xB8 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xB8 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xBC "IMNTRRTR47,INTC-Monitor Runtime Test Register 47" bitfld.long 0xBC 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xBC 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xBC 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xBC 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xBC 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xBC 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xBC 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xBC 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xBC 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xBC 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xBC 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xBC 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xBC 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xBC 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xBC 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xBC 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xC0 "IMNTRRTR48,INTC-Monitor Runtime Test Register 48" bitfld.long 0xC0 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xC0 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xC0 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xC0 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xC0 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xC0 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xC0 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xC0 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xC0 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xC0 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xC0 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xC0 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xC0 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xC0 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xC0 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xC0 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xC4 "IMNTRRTR49,INTC-Monitor Runtime Test Register 49" bitfld.long 0xC4 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xC4 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xC4 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xC4 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xC4 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xC4 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xC4 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xC4 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xC4 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xC4 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xC4 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xC4 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xC4 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xC4 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xC4 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xC4 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xC8 "IMNTRRTR50,INTC-Monitor Runtime Test Register 50" bitfld.long 0xC8 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xC8 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xC8 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xC8 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xC8 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xC8 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xC8 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xC8 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xC8 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xC8 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xC8 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xC8 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xC8 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xC8 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xC8 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xC8 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xCC "IMNTRRTR51,INTC-Monitor Runtime Test Register 51" bitfld.long 0xCC 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xCC 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xCC 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xCC 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xCC 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xCC 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xCC 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xCC 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xCC 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xCC 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xCC 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xCC 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xCC 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xCC 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xCC 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xCC 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xD0 "IMNTRRTR52,INTC-Monitor Runtime Test Register 52" bitfld.long 0xD0 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xD0 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xD0 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xD0 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xD0 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xD0 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xD0 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xD0 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xD0 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xD0 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xD0 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xD0 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xD0 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xD0 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xD0 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xD0 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xD4 "IMNTRRTR53,INTC-Monitor Runtime Test Register 53" bitfld.long 0xD4 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xD4 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xD4 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xD4 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xD4 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xD4 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xD4 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xD4 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xD4 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xD4 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xD4 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xD4 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xD4 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xD4 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xD4 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xD4 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xD8 "IMNTRRTR54,INTC-Monitor Runtime Test Register 54" bitfld.long 0xD8 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xD8 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xD8 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xD8 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xD8 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xD8 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xD8 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xD8 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xD8 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xD8 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xD8 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xD8 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xD8 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xD8 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xD8 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xD8 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xDC "IMNTRRTR55,INTC-Monitor Runtime Test Register 55" bitfld.long 0xDC 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xDC 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xDC 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xDC 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xDC 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xDC 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xDC 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xDC 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xDC 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xDC 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xDC 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xDC 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xDC 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xDC 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xDC 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xDC 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xE0 "IMNTRRTR56,INTC-Monitor Runtime Test Register 56" bitfld.long 0xE0 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xE0 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xE0 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xE0 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xE0 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xE0 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xE0 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xE0 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xE0 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xE0 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xE0 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xE0 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xE0 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xE0 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xE0 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xE0 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xE4 "IMNTRRTR57,INTC-Monitor Runtime Test Register 57" bitfld.long 0xE4 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xE4 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xE4 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xE4 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xE4 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xE4 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xE4 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xE4 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xE4 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xE4 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xE4 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xE4 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xE4 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xE4 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xE4 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xE4 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xE8 "IMNTRRTR58,INTC-Monitor Runtime Test Register 58" bitfld.long 0xE8 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xE8 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xE8 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xE8 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xE8 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xE8 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xE8 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xE8 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xE8 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xE8 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xE8 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xE8 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xE8 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xE8 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xE8 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xE8 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xEC "IMNTRRTR59,INTC-Monitor Runtime Test Register 59" bitfld.long 0xEC 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xEC 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xEC 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xEC 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xEC 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xEC 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xEC 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xEC 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xEC 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xEC 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xEC 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xEC 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xEC 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xEC 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xEC 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xEC 0.--1. "IMNTRCR0,-" "0,1,2,3" line.long 0xF0 "IMNTRRTR60,INTC-Monitor Runtime Test Register 60" bitfld.long 0xF0 30.--31. "IMNTRCR15,-" "0,1,2,3" bitfld.long 0xF0 28.--29. "IMNTRCR14,-" "0,1,2,3" bitfld.long 0xF0 26.--27. "IMNTRCR13,-" "0,1,2,3" bitfld.long 0xF0 24.--25. "IMNTRCR12,-" "0,1,2,3" bitfld.long 0xF0 22.--23. "IMNTRCR11,-" "0,1,2,3" bitfld.long 0xF0 20.--21. "IMNTRCR10,-" "0,1,2,3" bitfld.long 0xF0 18.--19. "IMNTRCR9,-" "0,1,2,3" bitfld.long 0xF0 16.--17. "IMNTRCR8,-" "0,1,2,3" newline bitfld.long 0xF0 14.--15. "IMNTRCR7,-" "0,1,2,3" bitfld.long 0xF0 12.--13. "IMNTRCR6,-" "0,1,2,3" bitfld.long 0xF0 10.--11. "IMNTRCR5,-" "0,1,2,3" bitfld.long 0xF0 8.--9. "IMNTRCR4,-" "0,1,2,3" bitfld.long 0xF0 6.--7. "IMNTRCR3,-" "0,1,2,3" bitfld.long 0xF0 4.--5. "IMNTRCR2,-" "0,1,2,3" bitfld.long 0xF0 2.--3. "IMNTRCR1,-" "0,1,2,3" bitfld.long 0xF0 0.--1. "IMNTRCR0,-" "0,1,2,3" tree.end tree "INTC-EX" base ad:0xE61C0000 rgroup.long 0x0++0x3 line.long 0x0 "INTREQ_STS0,This register shows interrupt request status." hexmask.long.byte 0x0 0.--5. 1. "INTREQ,Interrupt Status" group.long 0x4++0x3 line.long 0x0 "INTEN_STS0,This register shows interrupt enable status and clear interrupt enable." hexmask.long.byte 0x0 0.--5. 1. "INTEN,Interrupt Enable" rgroup.long 0x8++0x3 line.long 0x0 "INTEN_SET0,This register set interrupt enable." hexmask.long.byte 0x0 0.--5. 1. "INTENS,Interrupt Enable Set" group.long 0x100++0x3 line.long 0x0 "DETECT_STATUS,This register shows IRQn event detection status and provides the function to clear edge-triggered event. The status bit is cleared by writing 1 to the corresponding bit in edge-triggered mode. Writing 0 to this register bits does not affect.." hexmask.long.byte 0x0 0.--5. 1. "IRQnDET,IRQn Event Detection Status" rgroup.long 0x104++0x1F line.long 0x0 "MONITOR,This register provide external signal monitor." hexmask.long.byte 0x0 0.--5. 1. "IRQnMON,IRQn External Signal Level Monitor" line.long 0x4 "HLVL_STS,This register provides interrupt detail detect status." hexmask.long.byte 0x4 0.--5. 1. "IRQnHSTS,IRQn High Level Interrupt Status" line.long 0x8 "LLVL_STS,This register provides interrupt detail detect status." hexmask.long.byte 0x8 0.--5. 1. "IRQnLSTS,IRQn Low Level Interrupt Status" line.long 0xC "S_R_EDGE_STS,This register provides interrupt detail detect status." hexmask.long.byte 0xC 0.--5. 1. "IRQnSRSTS,IRQn Synchronous Rise Edge Interrupt Status" line.long 0x10 "S_F_EDGE_STS,This register provides interrupt detail detect status." hexmask.long.byte 0x10 0.--5. 1. "IRQnSFSTS,IRQn Synchronous Fall Edge Interrupt Status" line.long 0x14 "A_R_EDGE_STS,This register provides interrupt detail detect status." hexmask.long.byte 0x14 0.--5. 1. "IRQnARSTS,IRQn Asynchronous Rise Edge Interrupt Status" line.long 0x18 "A_F_EDGE_STS,This register provides interrupt detail detect status." hexmask.long.byte 0x18 0.--5. 1. "IRQnAFSTS,IRQn Asynchronous Fall Edge Interrupt Status" line.long 0x1C "CHTEN_STS,This register shows chattering reduction enable status." hexmask.long.byte 0x1C 0.--5. 1. "CHTEN,Chattering Reduction Enable Status" group.long 0x180++0x17 line.long 0x0 "CONFIG_0,This register provides detection mode and chattering reduction setting." bitfld.long 0x0 31. "CHTEN,Chattering Reduction Enable" "0: Chattering reduction disabled,1: Chattering reduction enabled" bitfld.long 0x0 22.--23. "STS1,IRQn Scan Timing" "0: 1 ms,1: 2 ms,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "STS2,IRQn Chattering Reduction Period" hexmask.long.byte 0x0 0.--5. 1. "SS,Sense Selection" line.long 0x4 "CONFIG_1,This register provides detection mode and chattering reduction setting." bitfld.long 0x4 31. "CHTEN,Chattering Reduction Enable" "0: Chattering reduction disabled,1: Chattering reduction enabled" bitfld.long 0x4 22.--23. "STS1,IRQn Scan Timing" "0: 1 ms,1: 2 ms,?,?" newline hexmask.long.byte 0x4 16.--21. 1. "STS2,IRQn Chattering Reduction Period" hexmask.long.byte 0x4 0.--5. 1. "SS,Sense Selection" line.long 0x8 "CONFIG_2,This register provides detection mode and chattering reduction setting." bitfld.long 0x8 31. "CHTEN,Chattering Reduction Enable" "0: Chattering reduction disabled,1: Chattering reduction enabled" bitfld.long 0x8 22.--23. "STS1,IRQn Scan Timing" "0: 1 ms,1: 2 ms,?,?" newline hexmask.long.byte 0x8 16.--21. 1. "STS2,IRQn Chattering Reduction Period" hexmask.long.byte 0x8 0.--5. 1. "SS,Sense Selection" line.long 0xC "CONFIG_3,This register provides detection mode and chattering reduction setting." bitfld.long 0xC 31. "CHTEN,Chattering Reduction Enable" "0: Chattering reduction disabled,1: Chattering reduction enabled" bitfld.long 0xC 22.--23. "STS1,IRQn Scan Timing" "0: 1 ms,1: 2 ms,?,?" newline hexmask.long.byte 0xC 16.--21. 1. "STS2,IRQn Chattering Reduction Period" hexmask.long.byte 0xC 0.--5. 1. "SS,Sense Selection" line.long 0x10 "CONFIG_4,This register provides detection mode and chattering reduction setting." bitfld.long 0x10 31. "CHTEN,Chattering Reduction Enable" "0: Chattering reduction disabled,1: Chattering reduction enabled" bitfld.long 0x10 22.--23. "STS1,IRQn Scan Timing" "0: 1 ms,1: 2 ms,?,?" newline hexmask.long.byte 0x10 16.--21. 1. "STS2,IRQn Chattering Reduction Period" hexmask.long.byte 0x10 0.--5. 1. "SS,Sense Selection" line.long 0x14 "CONFIG_5,This register provides detection mode and chattering reduction setting." bitfld.long 0x14 31. "CHTEN,Chattering Reduction Enable" "0: Chattering reduction disabled,1: Chattering reduction enabled" bitfld.long 0x14 22.--23. "STS1,IRQn Scan Timing" "0: 1 ms,1: 2 ms,?,?" newline hexmask.long.byte 0x14 16.--21. 1. "STS2,IRQn Chattering Reduction Period" hexmask.long.byte 0x14 0.--5. 1. "SS,Sense Selection" rgroup.long 0x0++0x3 line.long 0x0 "NMIREQ_STS0,This register shows external NMI request status." bitfld.long 0x0 7. "C7STS,NMI Status for CPU7 interface (INTC-AP/INTC-RT)" "0: not during NMI service,1: during NMI service" bitfld.long 0x0 6. "C6STS,NMI Status for CPU6 interface (INTC-AP/INTC-RT)" "0: not during NMI service,1: during NMI service" newline bitfld.long 0x0 5. "C5STS,NMI Status for CPU5 interface (INTC-AP/INTC-RT)" "0: not during NMI service,1: during NMI service" bitfld.long 0x0 4. "C4STS,NMI Status for CPU4 interface (INTC-AP/INTC-RT)" "0: not during NMI service,1: during NMI service" newline bitfld.long 0x0 3. "C3STS,NMI Status for CPU3 interface (INTC-AP/INTC-RT)" "0: not during NMI service,1: during NMI service" bitfld.long 0x0 2. "C2STS,NMI Status for CPU2 interface (INTC-AP/INTC-RT)" "0: not during NMI service,1: during NMI service" newline bitfld.long 0x0 1. "C1STS,NMI Status for CPU1 interface (INTC-AP/INTC-RT)" "0: not during NMI service,1: during NMI service" bitfld.long 0x0 0. "C0STS,NMI Status for CPU0 interface (INTC-AP/INTC-RT)" "0: not during NMI service,1: during NMI service" group.long 0x4++0x3 line.long 0x0 "NMIEN_STS0,This register shows NMI interrupt enable status and clears NMI interrupt enable." bitfld.long 0x0 7. "C7IEN,Interrupt Enable for CPU7 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: NMI interrupt enable clear" bitfld.long 0x0 6. "C6IEN,Interrupt Enable for CPU6 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: NMI interrupt enable clear" newline bitfld.long 0x0 5. "C5IEN,Interrupt Enable for CPU5 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: NMI interrupt enable clear" bitfld.long 0x0 4. "C4IEN,Interrupt Enable for CPU4 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: NMI interrupt enable clear" newline bitfld.long 0x0 3. "C3IEN,Interrupt Enable for CPU3 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: NMI interrupt enable clear" bitfld.long 0x0 2. "C2IEN,Interrupt Enable for CPU2 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: NMI interrupt enable clear" newline bitfld.long 0x0 1. "C1IEN,Interrupt Enable for CPU1 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: NMI interrupt enable clear" bitfld.long 0x0 0. "C0IEN,Interrupt Enable for CPU0 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: NMI interrupt enable clear" wgroup.long 0x8++0x3 line.long 0x0 "NMIEN_SET0,This register enables the NMI interrupt to each CPU" bitfld.long 0x0 7. "C7SET,Interrupt Enable Set for CPU7 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: Interrupt enable set" bitfld.long 0x0 6. "C6SET,Interrupt Enable Set for CPU6 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: Interrupt enable set" newline bitfld.long 0x0 5. "C5SET,Interrupt Enable Set for CPU5 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: Interrupt enable set" bitfld.long 0x0 4. "C4SET,Interrupt Enable Set for CPU4 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: Interrupt enable set" newline bitfld.long 0x0 3. "C3SET,Interrupt Enable Set for CPU3 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: Interrupt enable set" bitfld.long 0x0 2. "C2SET,Interrupt Enable Set for CPU2 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: Interrupt enable set" newline bitfld.long 0x0 1. "C1SET,Interrupt Enable Set for CPU1 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: Interrupt enable set" bitfld.long 0x0 0. "C0SET,Interrupt Enable Set for CPU0 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: Interrupt enable set" group.long 0x100++0x3 line.long 0x0 "DETECT_STATUS_NMI,This register shows NMIn event detection status and provides the function to clear edge-triggered event. The status bit is cleared by writing 1 to the corresponding bit in edge-triggered mode. Writing 0 to this register bits does not.." bitfld.long 0x0 7. "NMI7DET,NMI7 Event Detection Status for CPU7 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: No functional effect" bitfld.long 0x0 6. "NMI6DET,NMI7 Event Detection Status for CPU6 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: No functional effect" newline bitfld.long 0x0 5. "NMI5DET,NMI7 Event Detection Status for CPU5 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: No functional effect" bitfld.long 0x0 4. "NMI4DET,NMI7 Event Detection Status for CPU4 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: No functional effect" newline bitfld.long 0x0 3. "NMI3DET,NMI7 Event Detection Status for CPU3 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: No functional effect" bitfld.long 0x0 2. "NMI2DET,NMI7 Event Detection Status for CPU2 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: No functional effect" newline bitfld.long 0x0 1. "NMI1DET,NMI7 Event Detection Status for CPU1 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: No functional effect" bitfld.long 0x0 0. "NMI0DET,NMI7 Event Detection Status for CPU0 interface (INTC-AP/INTC-RT)" "0: No functional effect,1: No functional effect" rgroup.long 0x104++0x1F line.long 0x0 "MONITOR_NMI,This register provides external signal monitor." bitfld.long 0x0 7. "NMI7MON,NMI7 External Signal Level Monitor for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI7 is low level,1: NMI7 is high level" bitfld.long 0x0 6. "NMI6MON,NMI7 External Signal Level Monitor for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI6 is low level,1: NMI6 is high level" newline bitfld.long 0x0 5. "NMI5MON,NMI7 External Signal Level Monitor for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI5 is low level,1: NMI5 is high level" bitfld.long 0x0 4. "NMI4MON,NMI7 External Signal Level Monitor for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI4 is low level,1: NMI4 is high level" newline bitfld.long 0x0 3. "NMI3MON,NMI7 External Signal Level Monitor for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI3 is low level,1: NMI3 is high level" bitfld.long 0x0 2. "NMI2MON,NMI7 External Signal Level Monitor for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI2 is low level,1: NMI2 is high level" newline bitfld.long 0x0 1. "NMI1MON,NMI7 External Signal Level Monitor for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI1 is low level,1: NMI1 is high level" bitfld.long 0x0 0. "NMI0MON,NMI7 External Signal Level Monitor for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI0 is low level,1: NMI0 is high level" line.long 0x4 "HLVL_STS_NMI,This register provides interrupt detail detect status." bitfld.long 0x4 7. "NMI7HSTS,NMI7 High Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI7 high level interrupt request not occurred,1: NMI7 high level interrupt request occurred" bitfld.long 0x4 6. "NMI6HSTS,NMI6 High Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI6 high level interrupt request not occurred,1: NMI6 high level interrupt request occurred" newline bitfld.long 0x4 5. "NMI5HSTS,NMI5 High Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI5 high level interrupt request not occurred,1: NMI5 high level interrupt request occurred" bitfld.long 0x4 4. "NMI4HSTS,NMI4 High Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI4 high level interrupt request not occurred,1: NMI4 high level interrupt request occurred" newline bitfld.long 0x4 3. "NMI3HSTS,NMI3 High Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI3 high level interrupt request not occurred,1: NMI3 high level interrupt request occurred" bitfld.long 0x4 2. "NMI2HSTS,NMI2 High Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI2 high level interrupt request not occurred,1: NMI2 high level interrupt request occurred" newline bitfld.long 0x4 1. "NMI1HSTS,NMI1 High Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI1 high level interrupt request not occurred,1: NMI1 high level interrupt request occurred" bitfld.long 0x4 0. "NMI0HSTS,NMI0 High Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI0 high level interrupt request not occurred,1: NMI0 high level interrupt request occurred" line.long 0x8 "LLVL_STS_NMI,This register provides interrupt detail detect status." bitfld.long 0x8 7. "NMI7LSTS,NMI7 Low Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI7 low level interrupt request not occurred,1: NMI7 low level interrupt request occurred" bitfld.long 0x8 6. "NMI6LSTS,NMI6 Low Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI6 low level interrupt request not occurred,1: NMI6 low level interrupt request occurred" newline bitfld.long 0x8 5. "NMI5LSTS,NMI5 Low Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI5 low level interrupt request not occurred,1: NMI5 low level interrupt request occurred" bitfld.long 0x8 4. "NMI4LSTS,NMI4 Low Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI4 low level interrupt request not occurred,1: NMI4 low level interrupt request occurred" newline bitfld.long 0x8 3. "NMI3LSTS,NMI3 Low Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI3 low level interrupt request not occurred,1: NMI3 low level interrupt request occurred" bitfld.long 0x8 2. "NMI2LSTS,NMI2 Low Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI2 low level interrupt request not occurred,1: NMI2 low level interrupt request occurred" newline bitfld.long 0x8 1. "NMI1LSTS,NMI1 Low Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI1 low level interrupt request not occurred,1: NMI1 low level interrupt request occurred" bitfld.long 0x8 0. "NMI0LSTS,NMI0 Low Level Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI0 low level interrupt request not occurred,1: NMI0 low level interrupt request occurred" line.long 0xC "S_R_EDGE_STS_NMI,This register provides interrupt detail detect status." bitfld.long 0xC 7. "NMI7SRSTS,NMI7 Synchronous Rise Edge Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI7 rise edge interrupt request not occurred,1: NMI7 rise edge interrupt request occurred" bitfld.long 0xC 6. "NMI6SRSTS,NMI6 Synchronous Rise Edge Interrupt Status for CPU6 interface (INTC-AP/INTC-RT)" "0: NMI6 rise edge interrupt request not occurred,1: NMI6 rise edge interrupt request occurred" newline bitfld.long 0xC 5. "NMI5SRSTS,NMI5 Synchronous Rise Edge Interrupt Status for CPU5 interface (INTC-AP/INTC-RT)" "0: NMI5 rise edge interrupt request not occurred,1: NMI5 rise edge interrupt request occurred" bitfld.long 0xC 4. "NMI4SRSTS,NMI4 Synchronous Rise Edge Interrupt Status for CPU4 interface (INTC-AP/INTC-RT)" "0: NMI4 rise edge interrupt request not occurred,1: NMI4 rise edge interrupt request occurred" newline bitfld.long 0xC 3. "NMI3SRSTS,NMI3 Synchronous Rise Edge Interrupt Status for CPU3 interface (INTC-AP/INTC-RT)" "0: NMI3 rise edge interrupt request not occurred,1: NMI3 rise edge interrupt request occurred" bitfld.long 0xC 2. "NMI2SRSTS,NMI2 Synchronous Rise Edge Interrupt Status for CPU2 interface (INTC-AP/INTC-RT)" "0: NMI2 rise edge interrupt request not occurred,1: NMI2 rise edge interrupt request occurred" newline bitfld.long 0xC 1. "NMI1SRSTS,NMI1 Synchronous Rise Edge Interrupt Status for CPU1 interface (INTC-AP/INTC-RT)" "0: NMI1 rise edge interrupt request not occurred,1: NMI1 rise edge interrupt request occurred" bitfld.long 0xC 0. "NMI0SRSTS,NMI7 Synchronous Rise Edge Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI7 rise edge interrupt request not occurred,1: NMI7 rise edge interrupt request occurred" line.long 0x10 "S_F_EDGE_STS_NMI,This register provides interrupt detail detect status." bitfld.long 0x10 7. "NMI7SFSTS,NMI7 Synchronous Fall Edge Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI7 fall edge interrupt request not occurred,1: NMI7 fall edge interrupt request occurred" bitfld.long 0x10 6. "NMI6SFSTS,NMI6 Synchronous Fall Edge Interrupt Status for CPU6 interface (INTC-AP/INTC-RT)" "0: NMI6 fall edge interrupt request not occurred,1: NMI6 fall edge interrupt request occurred" newline bitfld.long 0x10 5. "NMI5SFSTS,NMI5 Synchronous Fall Edge Interrupt Status for CPU5 interface (INTC-AP/INTC-RT)" "0: NMI5 fall edge interrupt request not occurred,1: NMI5 fall edge interrupt request occurred" bitfld.long 0x10 4. "NMI4SFSTS,NMI4 Synchronous Fall Edge Interrupt Status for CPU4 interface (INTC-AP/INTC-RT)" "0: NMI4 fall edge interrupt request not occurred,1: NMI4 fall edge interrupt request occurred" newline bitfld.long 0x10 3. "NMI3SFSTS,NMI3 Synchronous Fall Edge Interrupt Status for CPU3 interface (INTC-AP/INTC-RT)" "0: NMI3 fall edge interrupt request not occurred,1: NMI3 fall edge interrupt request occurred" bitfld.long 0x10 2. "NMI2SFSTS,NMI2 Synchronous Fall Edge Interrupt Status for CPU2 interface (INTC-AP/INTC-RT)" "0: NMI2 fall edge interrupt request not occurred,1: NMI2 fall edge interrupt request occurred" newline bitfld.long 0x10 1. "NMI1SFSTS,NMI1 Synchronous Fall Edge Interrupt Status for CPU1 interface (INTC-AP/INTC-RT)" "0: NMI1 fall edge interrupt request not occurred,1: NMI1 fall edge interrupt request occurred" bitfld.long 0x10 0. "NMI0SFSTS,NMI0 Synchronous Fall Edge Interrupt Status for CPU0 interface (INTC-AP/INTC-RT)" "0: NMI0 fall edge interrupt request not occurred,1: NMI0 fall edge interrupt request occurred" line.long 0x14 "A_R_EDGE_STS_NMI,This register provides interrupt detail detect status." bitfld.long 0x14 7. "NMI7ARSTS,NMI7 Asynchronous Rise Edge Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI7 rise edge interrupt request not occurred,1: NMI7 rise edge interrupt request occurred" bitfld.long 0x14 6. "NMI6ARSTS,NMI6 Asynchronous Rise Edge Interrupt Status for CPU6 interface (INTC-AP/INTC-RT)" "0: NMI6 rise edge interrupt request not occurred,1: NMI6 rise edge interrupt request occurred" newline bitfld.long 0x14 5. "NMI5ARSTS,NMI5 Asynchronous Rise Edge Interrupt Status for CPU5 interface (INTC-AP/INTC-RT)" "0: NMI5 rise edge interrupt request not occurred,1: NMI5 rise edge interrupt request occurred" bitfld.long 0x14 4. "NMI4ARSTS,NMI4 Asynchronous Rise Edge Interrupt Status for CPU4 interface (INTC-AP/INTC-RT)" "0: NMI4 rise edge interrupt request not occurred,1: NMI4 rise edge interrupt request occurred" newline bitfld.long 0x14 3. "NMI3ARSTS,NMI3 Asynchronous Rise Edge Interrupt Status for CPU3 interface (INTC-AP/INTC-RT)" "0: NMI3 rise edge interrupt request not occurred,1: NMI3 rise edge interrupt request occurred" bitfld.long 0x14 2. "NMI2ARSTS,NMI2 Asynchronous Rise Edge Interrupt Status for CPU2 interface (INTC-AP/INTC-RT)" "0: NMI2 rise edge interrupt request not occurred,1: NMI2 rise edge interrupt request occurred" newline bitfld.long 0x14 1. "NMI1ARSTS,NMI1 Asynchronous Rise Edge Interrupt Status for CPU1 interface (INTC-AP/INTC-RT)" "0: NMI1 rise edge interrupt request not occurred,1: NMI1 rise edge interrupt request occurred" bitfld.long 0x14 0. "NMI0ARSTS,NMI0 Asynchronous Rise Edge Interrupt Status for CPU0 interface (INTC-AP/INTC-RT)" "0: NMI0 rise edge interrupt request not occurred,1: NMI0 rise edge interrupt request occurred" line.long 0x18 "A_F_EDGE_STS_NMI,This register provides interrupt detail detect status." bitfld.long 0x18 7. "NMI7AFSTS,NMI7 Asynchronous Fall Edge Interrupt Status for CPU7 interface (INTC-AP/INTC-RT)" "0: NMI7 fall edge interrupt request not occurred,1: NMI7 fall edge interrupt request occurred" bitfld.long 0x18 6. "NMI6AFSTS,NMI6 Asynchronous Fall Edge Interrupt Status for CPU6 interface (INTC-AP/INTC-RT)" "0: NMI6 fall edge interrupt request not occurred,1: NMI6 fall edge interrupt request occurred" newline bitfld.long 0x18 5. "NMI5AFSTS,NMI5 Asynchronous Fall Edge Interrupt Status for CPU5 interface (INTC-AP/INTC-RT)" "0: NMI5 fall edge interrupt request not occurred,1: NMI5 fall edge interrupt request occurred" bitfld.long 0x18 4. "NMI4AFSTS,NMI4 Asynchronous Fall Edge Interrupt Status for CPU4 interface (INTC-AP/INTC-RT)" "0: NMI4 fall edge interrupt request not occurred,1: NMI4 fall edge interrupt request occurred" newline bitfld.long 0x18 3. "NMI3AFSTS,NMI3 Asynchronous Fall Edge Interrupt Status for CPU3 interface (INTC-AP/INTC-RT)" "0: NMI3 fall edge interrupt request not occurred,1: NMI3 fall edge interrupt request occurred" bitfld.long 0x18 2. "NMI2AFSTS,NMI2 Asynchronous Fall Edge Interrupt Status for CPU2 interface (INTC-AP/INTC-RT)" "0: NMI2 fall edge interrupt request not occurred,1: NMI2 fall edge interrupt request occurred" newline bitfld.long 0x18 1. "NMI1AFSTS,NMI1 Asynchronous Fall Edge Interrupt Status for CPU1 interface (INTC-AP/INTC-RT)" "0: NMI1 fall edge interrupt request not occurred,1: NMI1 fall edge interrupt request occurred" bitfld.long 0x18 0. "NMI0AFSTS,NMI0 Asynchronous Fall Edge Interrupt Status for CPU0 interface (INTC-AP/INTC-RT)" "0: NMI0 fall edge interrupt request not occurred,1: NMI0 fall edge interrupt request occurred" line.long 0x1C "CHTEN_STS_NMI,This register shows chattering reduction enable status." bitfld.long 0x1C 0. "CHTEN,Chattering Reduction Enable Status" "0: Chattering reduction disabled,1: Chattering reduction enabled" group.long 0x140++0x3 line.long 0x0 "DEB_SET_NMI,This register provides chattering reduction setting." bitfld.long 0x0 31. "CHTEN,Chattering Reduction Enable" "0: Chattering reduction disabled,1: Chattering reduction enabled" bitfld.long 0x0 22.--23. "STS1,NMI Scan Timing" "0: 1 ms,1: 2 ms,?,?" newline hexmask.long.byte 0x0 16.--21. 1. "STS2,NMI Chattering Reduction Period" group.long 0x180++0x1F line.long 0x0 "CONFIG0_NMI,This register provides chattering reduction setting." hexmask.long.byte 0x0 0.--5. 1. "SS,Sense Selection" line.long 0x4 "CONFIG1_NMI,This register provides chattering reduction setting." hexmask.long.byte 0x4 0.--5. 1. "SS,Sense Selection" line.long 0x8 "CONFIG2_NMI,This register provides chattering reduction setting." hexmask.long.byte 0x8 0.--5. 1. "SS,Sense Selection" line.long 0xC "CONFIG3_NMI,This register provides chattering reduction setting." hexmask.long.byte 0xC 0.--5. 1. "SS,Sense Selection" line.long 0x10 "CONFIG4_NMI,This register provides chattering reduction setting." hexmask.long.byte 0x10 0.--5. 1. "SS,Sense Selection" line.long 0x14 "CONFIG5_NMI,This register provides chattering reduction setting." hexmask.long.byte 0x14 0.--5. 1. "SS,Sense Selection" line.long 0x18 "CONFIG6_NMI,This register provides chattering reduction setting." hexmask.long.byte 0x18 0.--5. 1. "SS,Sense Selection" line.long 0x1C "CONFIG7_NMI,This register provides chattering reduction setting." hexmask.long.byte 0x1C 0.--5. 1. "SS,Sense Selection" group.long 0x0++0xF line.long 0x0 "NMI_LCK,This register provides NMI mask locking feature. When set the same value as NMI_LCKCODE. then NMI cannot be masked by software (always accept NMI interrupt)." hexmask.long 0x0 0.--31. 1. "MSKLCK,Lock code setting" line.long 0x4 "NMI_LCKCODE,This register sets the value for lock code of NMI mask." hexmask.long 0x4 0.--31. 1. "LCKCODE,NMI mask lock code setting" line.long 0x8 "NMI_DBG,This register enables the debug feature for NMI mask lock." bitfld.long 0x8 0. "DBGEN,Enable debug for NMI mask lock feature" "0,1" line.long 0xC "NMI_DBGCODE,This register sets value for debug code of NMI mask lock. When set the following value. then unlock this mask feature." hexmask.long 0xC 0.--31. 1. "DBGCODE,NMI mask lock debug code setting" tree.end tree "IPC" base ad:0x0 tree "IPC_DATALINK" base ad:0xFFCD0000 group.long 0x0++0xB line.long 0x0 "HSIPCL1TXHEADER,This register sets the values of the payload and channel type fields in transmission of an L1 frame." bitfld.long 0x0 5.--7. "Payload,These bits set the value of the payload field of the L1 header in transmission of an L1 frame." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 1.--4. 1. "Channel_Type,These bits set the value of the channel type field of the L1 header in transmission of an L1 frame." line.long 0x4 "HSIPCL1TXPAYLOAD,This register sets the value of the payload in transmission of an L1 frame." hexmask.long 0x4 0.--31. 1. "L1_Tx_Payload_Value,These bits set the value of the payload in transmission of an L1 frame." line.long 0x8 "HSIPCL1TXENABLE,This register enables transmission of an L1 frame." bitfld.long 0x8 0. "L1_Tx_Enable,L1 Frame Transmission Enable" "0,1" rgroup.long 0x10++0x7 line.long 0x0 "HSIPCL1RXPAYLOAD,This register indicates the value of the payload when an L1 frame is received from the other party." hexmask.long 0x0 0.--31. 1. "L1_Rx_Payload_Value,These bits indicate the value of the payload of the last L1 frame to have been received." line.long 0x4 "HSIPCL1RXINTST,This register indicates the state that led to an interrupt when an L1 interface control frame was received from the other party." bitfld.long 0x4 16. "mi0_status,Status flag when an interrupt was due to reception of a ping answer frame" "0,1" newline bitfld.long 0x4 11. "si11_status,Status flag when an interrupt was due to reception of a frame which turns payload loopback on." "0,1" newline bitfld.long 0x4 10. "si10_status,Status flag when an interrupt was due to reception of a frame which turns test mode off." "0,1" newline bitfld.long 0x4 9. "si9_status,Status flag when an interrupt was due to reception of a frame which turns test mode on." "0,1" newline bitfld.long 0x4 8. "si8_status,Status flag when an interrupt was due to reception of a frame which disables the slave interface transmitter." "0,1" newline bitfld.long 0x4 7. "si7_status,Status flag when an interrupt was due to reception of a frame which enables the slave interface transmitter." "0,1" newline bitfld.long 0x4 6. "si6_status,Status flag when an interrupt was due to reception of a frame which selects fast mode for transfer from the slave interface to the master interface." "0,1" newline bitfld.long 0x4 5. "si5_status,Status flag when an interrupt was due to reception of a frame which selects slow mode for transfer from the slave interface to the master interface." "0,1" newline bitfld.long 0x4 4. "si4_status,Status flag when an interrupt was due to reception of a frame which selects fast mode for transfer from the master interface to the slave interface." "0,1" newline bitfld.long 0x4 3. "si3_status,Status flag when an interrupt was due to reception of a frame which selects slow mode for transfer from the master interface to the slave interface." "0,1" newline bitfld.long 0x4 2. "si2_status,Status flag when an interrupt was due to reception of a frame which stops the clock multiplier of the slave interface." "0,1" newline bitfld.long 0x4 1. "si1_status,Status flag when an interrupt was due to reception of a frame which starts the clock multiplier of the slave interface." "0,1" newline bitfld.long 0x4 0. "si0_status,Status flag when an interrupt was due to reception of a ping frame" "0,1" group.long 0x18++0x3 line.long 0x0 "HSIPCL1RXINTENB,This register enables or disables interrupts due to the various reception sources when L1 interface control frames are received from the other party." bitfld.long 0x0 16. "mi0_enb,Setting this bit to 1 enables interrupts due to the reception of ping answer frames." "0,1" newline bitfld.long 0x0 11. "si11_enb,Setting this bit to 1 enables interrupts due to the reception of frames which turn payload loopback on." "0,1" newline bitfld.long 0x0 10. "si10_enb,Setting this bit to 1 enables interrupts due to the reception of frames which turn test mode off." "0,1" newline bitfld.long 0x0 9. "si9_enb,Setting this bit to 1 enables interrupts due to the reception of frames which turn test mode on." "0,1" newline bitfld.long 0x0 8. "si8_enb,Setting this bit to 1 enables interrupts due to the reception of frames which disable the slave interface transmitter." "0,1" newline bitfld.long 0x0 7. "si7_enb,Setting this bit to 1 enables interrupts due to the reception of frames which enable the slave interface transmitter." "0,1" newline bitfld.long 0x0 6. "si6_enb,Setting this bit to 1 enables interrupts due to the reception of frames which select fast mode for transfer from the slave interface to the master interface." "0,1" newline bitfld.long 0x0 5. "si5_enb,Setting this bit to 1 enables interrupts due to the reception of frames which select slow mode for transfer from the slave interface to the master interface." "0,1" newline bitfld.long 0x0 4. "si4_enb,Setting this bit to 1 enables interrupts due to the reception of frames which select fast mode for transfer from the master interface to the slave interface." "0,1" newline bitfld.long 0x0 3. "si3_enb,Setting this bit to 1 enables interrupts due to the reception of frames which select slow mode for transfer from the master interface to the slave interface." "0,1" newline bitfld.long 0x0 2. "si2_enb,Setting this bit to 1 enables interrupts due to the reception of frames which stop the clock multiplier of the slave interface." "0,1" newline bitfld.long 0x0 1. "si1_enb,Setting this bit to 1 enables interrupts due to the reception of frames which start the clock multiplier of the slave interface." "0,1" newline bitfld.long 0x0 0. "si0_enb,Setting this bit to 1 enables interrupts due to the reception of ping frames" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "HSIPCL1RXINTCLR,This register clears the states of reception-related interrupt source flags set in response to the reception of L1 interface control frames from the other party. Writing 1 to an effective bit leads to clearing of the corresponding status.." bitfld.long 0x0 16. "mi0_clear,Setting this bit to 1 clears the status flag for the reception of a ping answer frame" "0,1" newline bitfld.long 0x0 11. "si11_clear,Setting this bit to 1 clears the status flag for the reception of a frame which turns payload loopback on." "0,1" newline bitfld.long 0x0 10. "si10_clear,Setting this bit to 1 clears the status flag for the reception of a frame which turns test mode off." "0,1" newline bitfld.long 0x0 9. "si9_clear,Setting this bit to 1 clears the status flag for the reception of a frame which turns test mode on." "0,1" newline bitfld.long 0x0 8. "si8_clear,Setting this bit to 1 clears the status flag for the reception of a frame which disables the slave interface transmitter." "0,1" newline bitfld.long 0x0 7. "si7_clear,Setting this bit to 1 clears the status flag for the reception of a frame which enables the slave interface transmitter." "0,1" newline bitfld.long 0x0 6. "si6_clear,Setting this bit to 1 clears the status flag for the reception of a frame which selects fast mode for transfer from the slave interface to the master interface." "0,1" newline bitfld.long 0x0 5. "si5_clear,Setting this bit to 1 clears the status flag for the reception of a frame which selects slow mode for transfer from the slave interface to the master interface." "0,1" newline bitfld.long 0x0 4. "si4_clear,Setting this bit to 1 clears the status flag for the reception of a frame which selects fast mode for transfer from the master interface to the slave interface." "0,1" newline bitfld.long 0x0 3. "si3_clear,Setting this bit to 1 clears the status flag for the reception of a frame which selects slow mode for transfer from the master interface to the slave interface." "0,1" newline bitfld.long 0x0 2. "si2_clear,Setting this bit to 1 clears the status flag for the reception of a frame which stops the clock multiplier of the slave interface." "0,1" newline bitfld.long 0x0 1. "si1_clear,Setting this bit to 1 clears the status flag for the reception of a frame which starts the clock multiplier of the slave interface." "0,1" newline bitfld.long 0x0 0. "si0_clear,Setting this bit to 1 clears the status flag for the reception of a ping frame." "0,1" rgroup.long 0x20++0x3 line.long 0x0 "HSIPCL1TRXEINTST,This register indicates the states of interrupt sources due to errors found in the L1 headers of frames for transmission and received frames." bitfld.long 0x0 27. "re11_status,Status flag for an interrupt due to an error in the form of non-matching between the payload size specified in a received frame and the actual size" "0,1" newline bitfld.long 0x0 26. "re10_status,Status flag for an interrupt due to channel type code error 9 being found in the L1 header of a received frame" "0,1" newline bitfld.long 0x0 25. "re9_status,Status flag for an interrupt due to channel type code error 8 being found in the L1 header of a received frame" "0,1" newline bitfld.long 0x0 24. "re8_status,Status flag for an interrupt due to channel type code error 7 being found in the L1 header of a received frame" "0,1" newline bitfld.long 0x0 23. "re7_status,Status flag for an interrupt due to channel type code error 6 being found in the L1 header of a received frame" "0,1" newline bitfld.long 0x0 22. "re6_status,Status flag for an interrupt due to channel type code error 5 being found in the L1 header of a received frame" "0,1" newline bitfld.long 0x0 21. "re5_status,Status flag for an interrupt due to channel type code error 4 being found in the L1 header of a received frame" "0,1" newline bitfld.long 0x0 20. "re4_status,Status flag for an interrupt due to channel type code error 3 being found in the L1 header of a received frame" "0,1" newline bitfld.long 0x0 19. "re3_status,Status flag for an interrupt due to channel type code error 2 being found in the L1 header of a received frame" "0,1" newline bitfld.long 0x0 18. "re2_status,Status flag for an interrupt due to channel type code error 1 being found in the L1 header of a received frame" "0,1" newline bitfld.long 0x0 17. "re1_status,Status flag for an interrupt due to channel type code error 0 being found in the L1 header of a received frame" "0,1" newline bitfld.long 0x0 11. "te11_status,Status flag for an interrupt due to an error in the form of non-matching between the payload size specified in the transmitted frame and the actual size" "0,1" newline bitfld.long 0x0 10. "te10_status,Status flag for an interrupt due to channel type code error 9 being found in the L1 header of a frame for transmission" "0,1" newline bitfld.long 0x0 9. "te9_status,Status flag for an interrupt due to channel type code error 8 being found in the L1 header of a frame for transmission" "0,1" newline bitfld.long 0x0 8. "te8_status,Status flag for an interrupt due to channel type code error 7 being found in the L1 header of a frame for transmission" "0,1" newline bitfld.long 0x0 7. "te7_status,Status flag for an interrupt due to channel type code error 6 being found in the L1 header of a frame for transmission" "0,1" newline bitfld.long 0x0 6. "te6_status,Status flag for an interrupt due to channel type code error 5 being found in the L1 header of a frame for transmission" "0,1" newline bitfld.long 0x0 5. "te5_status,Status flag for an interrupt due to channel type code error 4 being found in the L1 header of a frame for transmission" "0,1" newline bitfld.long 0x0 4. "te4_status,Status flag for an interrupt due to channel type code error 3 being found in the L1 header of a frame for transmission" "0,1" newline bitfld.long 0x0 3. "te3_status,Status flag for an interrupt due to channel type code error 2 being found in the L1 header of a frame for transmission" "0,1" newline bitfld.long 0x0 2. "te2_status,Status flag for an interrupt due to channel type code error 1 being found in the L1 header of a frame for transmission" "0,1" newline bitfld.long 0x0 1. "te1_status,Status flag for an interrupt due to channel type code error 0 being found in the L1 header of a frame for transmission" "0,1" group.long 0x24++0x3 line.long 0x0 "HSIPCL1TRXEINTENB,This register enables or disables interrupts due to errors found in the L1 headers of frames for transmission and received frames." bitfld.long 0x0 27. "re11_enb,Setting this bit to 1 enables interrupts due to errors in the form of non-matching between the payload sizes specified in received frames and the actual sizes." "0,1" newline bitfld.long 0x0 26. "re10_enb,Setting this bit to 1 enables interrupts due to channel type code error 9 found in the L1 headers of received frames." "0,1" newline bitfld.long 0x0 25. "re9_enb,Setting this bit to 1 enables interrupts due to channel type code error 8 found in the L1 headers of received frames." "0,1" newline bitfld.long 0x0 24. "re8_enb,Setting this bit to 1 enables interrupts due to channel type code error 7 found in the L1 headers of received frames." "0,1" newline bitfld.long 0x0 23. "re7_enb,Setting this bit to 1 enables interrupts due to channel type code error 6 found in the L1 headers of received frames." "0,1" newline bitfld.long 0x0 22. "re6_enb,Setting this bit to 1 enables interrupts due to channel type code error 5 found in the L1 headers of received frames." "0,1" newline bitfld.long 0x0 21. "re5_enb,Setting this bit to 1 enables interrupts due to channel type code error 4 found in the L1 headers of received frames." "0,1" newline bitfld.long 0x0 20. "re4_enb,Setting this bit to 1 enables interrupts due to channel type code error 3 found in the L1 headers of received frames." "0,1" newline bitfld.long 0x0 19. "re3_enb,Setting this bit to 1 enables interrupts due to channel type code error 2 found in the L1 headers of received frames." "0,1" newline bitfld.long 0x0 18. "re2_enb,Setting this bit to 1 enables interrupts due to channel type code error 1 found in the L1 headers of received frames." "0,1" newline bitfld.long 0x0 17. "re1_enb,Setting this bit to 1 enables interrupts due to channel type code error 0 found in the L1 headers of received frames." "0,1" newline bitfld.long 0x0 11. "te11_enb,Setting this bit to 1 enables interrupts due to errors in the form of non-matching between the payload sizes specified in the transmitted frames and the actual sizes." "0,1" newline bitfld.long 0x0 10. "te10_enb,Setting this bit to 1 enables interrupts due to channel type code error 9 found in the L1 headers of frames for transmission." "0,1" newline bitfld.long 0x0 9. "te9_enb,Setting this bit to 1 enables interrupts due to channel type code error 8 found in the L1 headers of frames for transmission." "0,1" newline bitfld.long 0x0 8. "te8_enb,Setting this bit to 1 enables interrupts due to channel type code error 7 found in the L1 headers of frames for transmission." "0,1" newline bitfld.long 0x0 7. "te7_enb,Setting this bit to 1 enables interrupts due to channel type code error 6 found in the L1 headers of frames for transmission." "0,1" newline bitfld.long 0x0 6. "te6_enb,Setting this bit to 1 enables interrupts due to channel type code error 5 found in the L1 headers of frames for transmission." "0,1" newline bitfld.long 0x0 5. "te5_enb,Setting this bit to 1 enables interrupts due to channel type code error 4 found in the L1 headers of frames for transmission." "0,1" newline bitfld.long 0x0 4. "te4_enb,Setting this bit to 1 enables interrupts due to channel type code error 3 found in the L1 headers of frames for transmission." "0,1" newline bitfld.long 0x0 3. "te3_enb,Setting this bit to 1 enables interrupts due to channel type code error 2 found in the L1 headers of frames for transmission." "0,1" newline bitfld.long 0x0 2. "te2_enb,Setting this bit to 1 enables interrupts due to channel type code error 1 found in the L1 headers of frames for transmission." "0,1" newline bitfld.long 0x0 1. "te1_enb,Setting this bit to 1 enables interrupts due to channel type code error 0 found in the L1 headers of frames for transmission." "0,1" wgroup.long 0x28++0x3 line.long 0x0 "HSIPCL1TRXEINTCLR,This register clears the states of interrupt source flags set in response to errors found in the L1 headers of frames for transmission and received frames." bitfld.long 0x0 27. "re11_clear,Setting this bit to 1 clears the status flag for an error in the form of non-matching between the payload size specified in a received frame and the actual size." "0,1" newline bitfld.long 0x0 26. "re10_clear,Setting this bit to 1 clears the status flag for channel type code error 9 being found in the L1 header of a received frame." "0,1" newline bitfld.long 0x0 25. "re9_clear,Setting this bit to 1 clears the status flag for channel type code error 8 being found in the L1 header of a received frame." "0,1" newline bitfld.long 0x0 24. "re8_clear,Setting this bit to 1 clears the status flag for channel type code error 7 being found in the L1 header of a received frame." "0,1" newline bitfld.long 0x0 23. "re7_clear,Setting this bit to 1 clears the status flag for channel type code error 6 being found in the L1 header of a received frame." "0,1" newline bitfld.long 0x0 22. "re6_clear,Setting this bit to 1 clears the status flag for channel type code error 5 being found in the L1 header of a received frame." "0,1" newline bitfld.long 0x0 21. "re5_clear,Setting this bit to 1 clears the status flag for channel type code error 4 being found in the L1 header of a received frame." "0,1" newline bitfld.long 0x0 20. "re4_clear,Setting this bit to 1 clears the status flag for channel type code error 3 being found in the L1 header of a received frame." "0,1" newline bitfld.long 0x0 19. "re3_clear,Setting this bit to 1 clears the status flag for channel type code error 2 being found in the L1 header of a received frame." "0,1" newline bitfld.long 0x0 18. "re2_clear,Setting this bit to 1 clears the status flag for channel type code error 1 being found in the L1 header of a received frame." "0,1" newline bitfld.long 0x0 17. "re1_clear,Setting this bit to 1 clears the status flag for channel type code error 0 being found in the L1 header of a received frame." "0,1" newline bitfld.long 0x0 11. "te11_clear,Setting this bit to 1 clears the status flag for an error in the form of non-matching between the payload size specified in the transmitted frame and the actual size." "0,1" newline bitfld.long 0x0 10. "te10_clear,Setting this bit to 1 clears the status flag for channel type code error 9 being found in the L1 header of a frame for transmission." "0,1" newline bitfld.long 0x0 9. "te9_clear,Setting this bit to 1 clears the status flag for channel type code error 8 being found in the L1 header of a frame for transmission." "0,1" newline bitfld.long 0x0 8. "te8_clear,Setting this bit to 1 clears the status flag for channel type code error 7 being found in the L1 header of a frame for transmission." "0,1" newline bitfld.long 0x0 7. "te7_clear,Setting this bit to 1 clears the status flag for channel type code error 6 being found in the L1 header of a frame for transmission." "0,1" newline bitfld.long 0x0 6. "te6_clear,Setting this bit to 1 clears the status flag for channel type code error 5 being found in the L1 header of a frame for transmission." "0,1" newline bitfld.long 0x0 5. "te5_clear,Setting this bit to 1 clears the status flag for channel type code error 4 being found in the L1 header of a frame for transmission." "0,1" newline bitfld.long 0x0 4. "te4_clear,Setting this bit to 1 clears the status flag for channel type code error 3 being found in the L1 header of a frame for transmission." "0,1" newline bitfld.long 0x0 3. "te3_clear,Setting this bit to 1 clears the status flag for channel type code error 2 being found in the L1 header of a frame for transmission." "0,1" newline bitfld.long 0x0 2. "te2_clear,Setting this bit to 1 clears the status flag for channel type code error 1 being found in the L1 header of a frame for transmission." "0,1" newline bitfld.long 0x0 1. "te1_clear,Setting this bit to 1 clears the status flag for channel type code error 0 being found in the L1 header of a frame for transmission." "0,1" group.long 0x2C++0xB line.long 0x0 "HSIPCL1TRXFLOW,This register is used to control the flow control bit (CTS bit) in frames for transmission and to enable or disable the flow control bit (CTS bit) in received frames." bitfld.long 0x0 8. "rxe,This bit enables or disables flow control by the CTS bit in received frames." "0: The CTS bit is disabled,1: The CTS bit is enabled" newline bitfld.long 0x0 4. "txc,This bit specifies the value to be set in the CTS bit when the txe bit (bit 0 of this register) is set to 1 (enabling this bit)." "0,1" newline bitfld.long 0x0 0. "txe,This bit sets the CTS bit in frames for transmission to 1 or selects setting of the CTS bit to the value of the txc bit." "0: The CTS bit is set to 1,1: The CTS bit reflects the value of the txc bit" line.long 0x4 "HSIPCL1RXICLC,This register enables or disables the reception of interface control frames." bitfld.long 0x4 0. "rxie,This bit enables or disables the reception of interface control frames." "0: Disabled,1: Enabled" line.long 0x8 "HSIPCL1TRXENABLE,This register enables or disables the transmission and reception of frames other than enable slave interface frames." bitfld.long 0x8 0. "trxe,This bit enables or disables the transmission and reception of frames other than enable slave interface frames." "0: Disabled,1: Enabled" rgroup.long 0x38++0x7 line.long 0x0 "HSIPCL1TXFRMST,This register indicates the state of the last frame to have been transmitted." bitfld.long 0x0 5.--7. "ltxpl,These bits indicate the payload value of the last frame to have been transmitted." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 1.--4. 1. "ltxch,These bits indicate the channel type value of the last frame to have been transmitted." newline bitfld.long 0x0 0. "ltxc,This bit indicates the value of the CTS bit in the last frame to have been transmitted." "0,1" line.long 0x4 "HSIPCL1RXFRMST,This register indicates the state of the last frame to have been received." bitfld.long 0x4 5.--7. "lrxpl,These bits indicate the payload value of the last frame to have been received." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 1.--4. 1. "lrxch,These bits indicate the channel type value of the last frame to have been received." newline bitfld.long 0x4 0. "lrxc,This bit indicates the value of the CTS bit in the last frame to have been received." "0,1" group.long 0x40++0x3 line.long 0x0 "HSIPCL1TESTMD,L1 Test Mode Register" group.long 0x70++0x3 line.long 0x0 "HSIPCSPSET,This register sets the transfer rate." bitfld.long 0x0 8.--9. "TX_SPSET,Transmit Rate Setting" "0: Low speed,?,?,?" newline bitfld.long 0x0 0.--1. "RX_SPSET,Reception Rate Setting" "0: Low speed,?,?,?" rgroup.long 0x74++0x3 line.long 0x0 "HSIPCSPMON,This register monitors the setting for the transfer rate." bitfld.long 0x0 8.--9. "tx_lvmonst,Transmission Rate Setting Monitor" "0: Low speed,?,?,?" newline bitfld.long 0x0 0.--1. "rx_lvmonst,Reception Rate Setting Monitor" "0: Low speed,?,?,?" group.long 0x78++0x7 line.long 0x0 "HSIPCTXINTVL,This register sets the interval between frames being transmitted." hexmask.long.byte 0x0 0.--4. 1. "TXINTVL,These bits set the interval between frames being transmitted." line.long 0x4 "HSIPCPDSIZE,Payload Size Register" wgroup.long 0x80++0x7 line.long 0x0 "HSIPCTONTM,This register is used to control the “turn on test mode” function specifiable by L1 control frames." bitfld.long 0x0 16. "TX_TONTM,In slave mode writing 1 here starts the transmission of a toggled pattern." "0,1" newline bitfld.long 0x0 0. "RX_TONTM,In master mode writing 1 here starts checking for the reception of a toggled pattern." "0,1" line.long 0x4 "HSIPCTOFFTM,This register is used to control the “turn off test mode” function specifiable by L1 control frames." bitfld.long 0x4 16. "TX_TOFFTM,In slave mode writing 1 here stops the transmission of a toggled pattern." "0,1" newline bitfld.long 0x4 0. "RX_TOFFTM,In master mode writing 1 here stops checking for the reception of a toggled pattern." "0,1" group.long 0x88++0xB line.long 0x0 "HSIPCTOTMST,This register indicates the state of the “turn on test mode” function specifiable by L1 control frames." rbitfld.long 0x0 16. "TX_TMBUSY,This bit indicates the state of transmission of a toggled pattern in slave mode." "0: A toggled pattern is not being transmitted,1: A toggled pattern is being transmitted" newline bitfld.long 0x0 9. "RX_TGLST,This bit indicates the detection of a toggled pattern." "0: A toggled pattern has not been detected,1: A toggled pattern has been detected" newline bitfld.long 0x0 8. "TM_RESULT,This bit indicates the result of checking for reception of a toggled pattern." "0: OK,1: NG" newline rbitfld.long 0x0 0. "RX_TMBUSY,This bit indicates the state of checking for the reception of a toggled pattern in master mode." "0: Checking for the reception of a toggled pattern..,1: Checking for the reception of a toggled pattern.." line.long 0x4 "HSIPCTGLOKCNT,This register indicates the number of times the result of checking for a toggled pattern was “OK” during operation in test mode after “turn on test mode” was specified by an L1 control frame in master mode." hexmask.long 0x4 0.--31. 1. "TGLOKCNT,These bits indicate the number of times that the detected toggled pattern was correct in checking for the reception of a toggled pattern in master mode." line.long 0x8 "HSIPCTGLNGCNT,This register indicates the number of times the result of checking for a toggled pattern was “NG” during operation in test mode after “turn on test mode” was specified by an L1 control frame in master mode." hexmask.long 0x8 0.--31. 1. "TGLNGCNT,These bits indicate the number of times that the detected toggled pattern was not as expected in checking for the reception of a toggled pattern in master mode." group.long 0x98++0xF line.long 0x0 "HSIPCCLKFON,This register forcibly enables clock drivers." bitfld.long 0x0 12. "RXLVDSCLK0_FON,Forcibly turns the driver for the RXLVDSCLK0 clock on." "0: The driver is only turned on when the RXLVDSCLK0..,1: The driver is always turned on" newline bitfld.long 0x0 8. "RXDCLK0_FON,Forcibly turns the driver for the RXDCLK0 clock on." "0: The driver is only turned on when the RXDCLK0..,1: The driver is always turned on" newline bitfld.long 0x0 4. "TXLVDSCLK0_FON,Forcibly turns the driver for the TXLVDSCLK0 clock on." "0: The driver is only turned on when the TXLVDSCLK0..,1: The driver is always turned on" newline bitfld.long 0x0 0. "TXDCLK0_FON,Forcibly turns the driver for the TXDCLK0 clock on." "0: The driver is only turned on when the TXDCLK0..,1: The driver is always turned on" line.long 0x4 "HSIPCACKCANSEL,ACK Cancellation Register" line.long 0x8 "RESERVE,Reserved Register" line.long 0xC "HSIPCSYNCSEL,SYNC Word Select Register" group.long 0xB0++0x13 line.long 0x0 "HSIPCDRF_IGR0,Internal General Register 0" line.long 0x4 "HSIPCDRF_IGR1,Internal General Register 1" line.long 0x8 "HSIPCDRF_IGR2,Internal General Register 2" line.long 0xC "HSIPCDRF_IGR3,Internal General Register 3" line.long 0x10 "HSIPCDRF_RES,Reset Register" group.long 0xC8++0x3 line.long 0x0 "HSIPCTSTLVDSC,Test LVDS Control Register" rgroup.long 0xCC++0x3 line.long 0x0 "HSIPCTSTLVDSM,Test LVDS Monitoring Register" group.long 0xD0++0x7 line.long 0x0 "HSIPCCLKGENMD0,This register specifies whether the CLKGEN is to serve in a master or slave role. and selects the frequency of the output clock in master mode." bitfld.long 0x0 1. "OUT_CLK_SEL,Selection of the frequency of the DIGRF_CLK_OUT signal" "0: 10 MHz,1: 20 MHz" newline bitfld.long 0x0 0. "MST_SEL,This bit selects either the master or slave role in HSSL communications." "0: Slave role,1: Master role" line.long 0x4 "HSIPCCLKGENMD1,This register sets parameters for the PLL in the CLKGEN." hexmask.long.word 0x4 16.--28. 1. "PLL_SET,SET signal is input to the PLL." newline bitfld.long 0x4 13. "STP_FBCLKOUT,STP_FBCLKOUT signal is input to the PLL." "0,1" newline bitfld.long 0x4 12. "STP_CLKOUT,STP_CLKOUTE signal is input to the PLL." "0,1" newline bitfld.long 0x4 8.--10. "PLL_M,Input signal on the M pin of the PLL" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 1.--7. 1. "PLL_N,Input signal on the N pin of the PLL" newline bitfld.long 0x4 0. "OUTLOOP,Input signal on the OUTLOOP pin of the PLL" "0,1" group.long 0xE8++0x7 line.long 0x0 "HSIPCCLKGENRST,This register is used to place the PLL. MDLL. and SDLY0 to SDLY2 in the CLKGEN in the standby or reset state." bitfld.long 0x0 4. "PLL_STBY,This bit is used to place the PLL on standby." "?,1: The PLL is placed on standby" line.long 0x4 "HSIPCPADCTL,This register is used to control the pads." bitfld.long 0x4 9. "CLKEN_IN_EN,This bit selects whether the DIGRF_CLKEN_IN input signal is effective or not." "0: The DIGRF_CLKEN_IN input signal is not effective,1: The DIGRF_CLKEN_IN input signal is effective" newline bitfld.long 0x4 8. "digrf_clken_out,This bit sets the output level of the DIGRF_CLKEN_OUT signal." "0: The low level is output,1: The high level is output" newline bitfld.long 0x4 5. "LVDS_RX_ERT,This bit controls the termination resistor enable of LVDS reception." "0: Disable,1: Enable" newline bitfld.long 0x4 4. "LVDS_TX_VODSEL,This bit controls the driver output amplitude switching for LVDS transmission." "0: normal amplitude,1: amplitude increase" newline bitfld.long 0x4 2. "LVDS_RX_EN,This bit enables reception on LVDS pins." "0: Reception is disabled,1: Reception is enabled" newline bitfld.long 0x4 1. "LVDS_BEN,This bit enables biasing on LVDS pins." "0: Biasing is disabled,1: Biasing is enabled" newline bitfld.long 0x4 0. "LVDS_TX_OEN,This bit enables transmission on LVDS pins." "0: Transmission is disabled,1: Transmission is enabled" rgroup.long 0xF0++0x3 line.long 0x0 "HSIPCHMMON,This register indicates values of the output signals of the MDLL. and of SDLY0 to SDLY2. It also indicates the value of the DIGRF_CLKEN_IN signal from the corresponding pad." bitfld.long 0x0 5. "digrf_clken_in,This bit monitors the DIGRF_CLKEN_IN input signal." "0,1" group.long 0xF4++0x3 line.long 0x0 "HSIPCCDR8_PARA,This register makes settings for the 8-phase clock selection circuit (CDR) of High speed mode reception circuit." bitfld.long 0x0 25. "CNT_MODE1,Used to select 8 phase clock for high speed reception." "0,1" newline bitfld.long 0x0 24. "CNT_MODE0,Used to select 8 phase clock for high speed reception." "0,1" newline bitfld.long 0x0 17. "CDR_STATIC,Used to select 8 phase clock for high speed reception." "0,1" newline bitfld.long 0x0 14.--16. "MPHASESEL,Used to select 8 phase clock for high speed reception." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--13. 1. "CDR_AVRG_SI,This field is not disclosed. The value of this regisrer must not be changed from the initial value." newline bitfld.long 0x0 7. "CDR_REG_3,This field is not disclosed. The value of this regisrer must not be changed from the initial value." "0,1" newline bitfld.long 0x0 6. "CDR_REG_2,This field is not disclosed. The value of this regisrer must not be changed from the initial value." "0,1" newline bitfld.long 0x0 5. "CDR_REG_1,This field is not disclosed. The value of this regisrer must not be changed from the initial value." "0,1" newline bitfld.long 0x0 4. "CDR_REG_0,This field is not disclosed. The value of this regisrer must not be changed from the initial value." "0,1" newline bitfld.long 0x0 1.--3. "RX_PREP_LEN,This field is not disclosed. The value of this regisrer must not be changed from the initial value." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "DAT_MASK_EN,This field is not disclosed. The value of this regisrer must not be changed from the initial value." "0,1" rgroup.long 0xF8++0x3 line.long 0x0 "HSIPCCDR8_MON,CDR Monitoring Register" group.long 0xFC++0x3 line.long 0x0 "HSIPCTSTREG,Test Register" tree.end tree "IPC_HSSL" base ad:0xE6A20000 group.long 0x0++0x3 line.long 0x0 "HSIPCnMMD,Module Mode Register" bitfld.long 0x0 0. "CHCT,This bit specifies the type of the channel number code table to be used for this IP." "0: 000b,1: 001b" group.long 0x8++0x3 line.long 0x0 "HSIPCnMCT,Module Control Register" bitfld.long 0x0 13. "WDWE,This bit specifies whether to enable the write operation for memory window D." "0,1" bitfld.long 0x0 12. "WDRE,This bit specifies whether to enable the read operation for memory window D." "0,1" bitfld.long 0x0 9. "WCWE,This bit specifies whether to enable the write operation for memory window C." "0,1" bitfld.long 0x0 8. "WCRE,This bit specifies whether to enable the read operation for memory window C." "0,1" bitfld.long 0x0 5. "WBWE,This bit specifies whether to enable the write operation for memory window B." "0,1" bitfld.long 0x0 4. "WBRE,This bit specifies whether to enable the read operation for memory window B." "0,1" bitfld.long 0x0 1. "WAWE,This bit specifies whether to enable the write operation for memory window A." "0,1" bitfld.long 0x0 0. "WARE,This bit specifies whether to enable the read operation for memory window A." "0,1" rgroup.long 0x18++0x3 line.long 0x0 "HSIPCnMIST,Module Interrupt Status Register" bitfld.long 0x0 31. "DBGS,When set to 1 this bit indicates that there is a debug interrupt factor." "0,1" bitfld.long 0x0 27. "MESS,When set to 1 this bit indicates that there is an error interrupt factor independent of channel." "0,1" bitfld.long 0x0 25. "SRES,When set to 1 this bit indicates that there is an error interrupt factor concerning stream reception." "0,1" bitfld.long 0x0 24. "STES,When set to 1 this bit indicates that there is an error interrupt factor concerning stream transmission." "0,1" bitfld.long 0x0 23. "CERS3,When set to 1 this bit indicates that there is an error interrupt factor concerning channel 3." "0,1" bitfld.long 0x0 22. "CERS2,When set to 1 this bit indicates that there is an error interrupt factor concerning channel 2." "0,1" bitfld.long 0x0 21. "CERS1,When set to 1 this bit indicates that there is an error interrupt factor concerning channel 1." "0,1" bitfld.long 0x0 20. "CERS0,When set to 1 this bit indicates that there is an error interrupt factor concerning channel 0." "0,1" bitfld.long 0x0 18. "SRCS1,When set to 1 this bit indicates that there is a factor of completing stream interrupt reception (of not less than the specified size)." "0,1" bitfld.long 0x0 17. "SRCS0,When set to 1 this bit indicates that there is a factor of completing stream interrupt reception (of not less than the data size of one frame)." "0,1" bitfld.long 0x0 16. "STCS,When set to 1 this bit indicates that there is a factor of completing stream interrupt transmission." "0,1" newline bitfld.long 0x0 14. "TERS3,When set to 1 this bit indicates that there is a factor of receiving an Event Command as a channel 3 interrupt." "0,1" bitfld.long 0x0 13. "AKRS3,When set to 1 this bit indicates that there is a factor of receiving an ACK Command as a channel 3 interrupt." "0,1" bitfld.long 0x0 12. "RARS3,When set to 1 this bit indicates that there is a factor of receiving a Read Answer Command as a channel 3 interrupt." "0,1" bitfld.long 0x0 10. "TERS2,When set to 1 this bit indicates that there is a factor of receiving an Event Command as a channel 2 interrupt." "0,1" bitfld.long 0x0 9. "AKRS2,When set to 1 this bit indicates that there is a factor of receiving an ACK Command as a channel 2 interrupt." "0,1" bitfld.long 0x0 8. "RARS2,When set to 1 this bit indicates that there is a factor of receiving a Read Answer Command as a channel 2 interrupt." "0,1" bitfld.long 0x0 6. "TERS1,When set to 1 this bit indicates that there is a factor of receiving an Event Command as a channel 1 interrupt." "0,1" bitfld.long 0x0 5. "AKRS1,When set to 1 this bit indicates that there is a factor of receiving an ACK Command as a channel 1 interrupt." "0,1" bitfld.long 0x0 4. "RARS1,When set to 1 this bit indicates that there is a factor of receiving a Read Answer Command as a channel 1 interrupt." "0,1" bitfld.long 0x0 2. "TERS0,When set to 1 this bit indicates that there is a factor of receiving an Event Command as a channel 0 interrupt." "0,1" bitfld.long 0x0 1. "AKRS0,When set to 1 this bit indicates that there is a factor of receiving an ACK Command as a channel 0 interrupt." "0,1" newline bitfld.long 0x0 0. "RARS0,When set to 1 this bit indicates that there is a factor of receiving a Read Answer Command as a channel 0 interrupt." "0,1" group.long 0x20++0x3 line.long 0x0 "HSIPCnMRT,Module Reply Timeout Time Register" hexmask.long.byte 0x0 12.--15. 1. "RSCL,These bits specify the reference clock for the reply timer." hexmask.long.word 0x0 0.--9. 1. "RCNT,These bits specify the limit count for the reply timer." group.long 0x40++0x3 line.long 0x0 "HSIPCnMWAA,Module Memory Window A Start Address Register" hexmask.long 0x0 2.--31. 1. "MW_X_A,These bits specify the start address of the window that is allowed to be accessed when this IP generates a AXI read or write request as bus master." group.long 0x48++0x3 line.long 0x0 "HSIPCnMWAS,Module Memory Window A Size Register" hexmask.long 0x0 2.--31. 1. "MW_X_S,These bits specify the size of the window that is allowed to be accessed when this IP generates a AXI read or write request as bus master. Write 1 to all the bits lower than those corresponding to the valid size value and write 0 to all the bits.." group.long 0x50++0x3 line.long 0x0 "HSIPCnMWBA,Module Memory Window B Start Address Register" hexmask.long 0x0 2.--31. 1. "MW_X_A,These bits specify the start address of the window that is allowed to be accessed when this IP generates a AXI read or write request as bus master." group.long 0x58++0x3 line.long 0x0 "HSIPCnMWBS,Module Memory Window B Size Register" hexmask.long 0x0 2.--31. 1. "MW_X_S,These bits specify the size of the window that is allowed to be accessed when this IP generates a AXI read or write request as bus master. Write 1 to all the bits lower than those corresponding to the valid size value and write 0 to all the bits.." group.long 0x60++0x3 line.long 0x0 "HSIPCnMWCA,Module Memory Window C Start Address Register" hexmask.long 0x0 2.--31. 1. "MW_X_A,These bits specify the start address of the window that is allowed to be accessed when this IP generates a AXI read or write request as bus master." group.long 0x68++0x3 line.long 0x0 "HSIPCnMWCS,Module Memory Window C Size Register" hexmask.long 0x0 2.--31. 1. "MW_X_S,These bits specify the size of the window that is allowed to be accessed when this IP generates a AXI read or write request as bus master. Write 1 to all the bits lower than those corresponding to the valid size value and write 0 to all the bits.." group.long 0x70++0x3 line.long 0x0 "HSIPCnMWDA,Module Memory Window D Start Address Register" hexmask.long 0x0 2.--31. 1. "MW_X_A,These bits specify the start address of the window that is allowed to be accessed when this IP generates a AXI read or write request as bus master." group.long 0x78++0x3 line.long 0x0 "HSIPCnMWDS,Module Memory Window D Size Register" hexmask.long 0x0 2.--31. 1. "MW_X_S,These bits specify the size of the window that is allowed to be accessed when this IP generates a AXI read or write request as bus master. Write 1 to all the bits lower than those corresponding to the valid size value and write 0 to all the bits.." group.long 0xE0++0x3 line.long 0x0 "HSIPCnMEST,Module Error Status Register" group.long 0xE8++0x3 line.long 0x0 "HSIPCnMESC,Module Error Status Clear Register" group.long 0xF0++0x3 line.long 0x0 "HSIPCnMEIE,Module Error Interrupt Enable Register" group.long 0x200++0x3 line.long 0x0 "HSIPCnSTMD,Stream Tx Mode Register" bitfld.long 0x0 20. "STNK,This bit specifies the operation that is necessary when this IP operating as an initiator node receives a NACK Command from a link partner in response to a Stream Command the initiator node transmitted." "0,1" bitfld.long 0x0 16. "STPS,This bit specifies the data payload size of the frame when this IP operating as an initiator node transmits a Stream Command." "0,1" rbitfld.long 0x0 12.--14. "STTH,These bits specify the size of the data buffer space required to request the AXI for reading when this IP operating as an initiator node transmits a Stream Command." "0,1,2,3,4,5,6,7" rbitfld.long 0x0 8.--10. "STBL,These bits specify the maximum number of bursts to request the AXI for reading when this IP operating as an initiator node transmits a Stream Command." "0,1,2,3,4,5,6,7" rbitfld.long 0x0 4.--6. "STOS,These bits specify the maximum number of outstanding requests to request the AXI for reading when this IP operating as an initiator node transmits a Stream Command." "0,1,2,3,4,5,6,7" group.long 0x208++0x3 line.long 0x0 "HSIPCnSTCT,Stream Tx Control Register" bitfld.long 0x0 0. "STDE,This bit specifies whether to enable the DMAC. Write 1 to this bit to start the DMAC when this IP operating as an initiator node transmits a Stream Command." "0,1" rgroup.long 0x210++0x3 line.long 0x0 "HSIPCnSTST,Stream Tx Status Register" bitfld.long 0x0 20. "STE3,This bit is set to 1 when a transfer error occurs in the AXI bus and the DMAC stops abnormally (because of the error) after this IP operating as an initiator has started the DMAC for Stream Command transmission." "0,1" bitfld.long 0x0 5. "STE2,This bit is set to 1 when a reply Command (ACK NACK or Read Answer) causing a transaction ID error is detected and the DMAC stops abnormally (because of the error) after this IP operating as an initiator has started the DMAC for Stream Command.." "0,1" bitfld.long 0x0 4. "STE1,This bit is set to 1 when the DMAC stops abnormally because it does not receive any response within the time set in the HSIPCnMRT bits after this IP operating as an initiator has started the DMAC for Stream Command transmission." "0,1" bitfld.long 0x0 2. "STE0,This bit is set to 1 when an NACK Command is received and the DMAC stops abnormally after this IP operating as an initiator has started the DMAC for Stream Command transmission." "0,1" bitfld.long 0x0 0. "STC,This bit is set to 1 when the transfer of all data ends normally after this IP operating as an initiator has started the DMAC for Stream Command transmission." "0,1" group.long 0x218++0x3 line.long 0x0 "HSIPCnSTSC,Stream Tx Status Clear Register" bitfld.long 0x0 20. "STEC3,Writing 1 to this bit clears the HSIPCnSTST.STE3 bit." "0,1" bitfld.long 0x0 5. "STEC2,Writing 1 to this bit clears the HSIPCnSTST.STE2 bit." "0,1" bitfld.long 0x0 4. "STEC1,Writing 1 to this bit clears the HSIPCnSTST.STE1 bit." "0,1" bitfld.long 0x0 2. "STEC0,Writing 1 to this bit clears the HSIPCnSTST.STE0 bit." "0,1" bitfld.long 0x0 0. "STCC,Writing 1 to this bit clears the HSIPCnSTST.STC bit." "0,1" group.long 0x220++0x3 line.long 0x0 "HSIPCnSTIE,Stream Tx Interrupt Enable Register" bitfld.long 0x0 20. "STEE3,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnSTST.STE3 bit." "0,1" bitfld.long 0x0 5. "STEE2,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnSTST.STE2 bit." "0,1" bitfld.long 0x0 4. "STEE1,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnSTST.STE1 bit." "0,1" bitfld.long 0x0 2. "STEE0,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnSTST.STE0 bit." "0,1" bitfld.long 0x0 0. "STCE,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnSTST.STC bit." "0,1" group.long 0x228++0x3 line.long 0x0 "HSIPCnSTSA,Stream Tx Source Address Register" hexmask.long 0x0 4.--31. 1. "STSA,These bits specify the start address of the area storing the data to be transferred when this IP operating as an initiator node starts the DMAC for Stream Command transmission." group.long 0x230++0x3 line.long 0x0 "HSIPCnSTBC,Stream Tx Byte Count Register" hexmask.long.tbyte 0x0 4.--24. 1. "STBC,These bits specify the total number of bytes of the data to be transferred when this IP operating as an initiator node starts the DMAC for Stream Command transmission." group.long 0x280++0x3 line.long 0x0 "HSIPCnSRMD,Stream Rx Mode Register" bitfld.long 0x0 20. "SRMC,This bit specifies the operation to be done if an error occurs when this IP operating as a target node receives a Stream Command." "0,1" bitfld.long 0x0 16. "SRPS,This bit specifies the frame data payload size that is expected when this IP operating as a target node receives a Stream Command." "0,1" rbitfld.long 0x0 4. "SROS,This bit specifies the maximum number of outstanding requests to request the AXI for writing when this IP operating as a target node receives a Stream Command." "0,1" group.long 0x288++0x3 line.long 0x0 "HSIPCnSRCT,Stream Rx Control Register" bitfld.long 0x0 0. "SRDE,This bit specifies whether to enable the DMAC. Write 1 to this bit to start the DMAC when this IP operating as a target node receives a Stream Command." "0,1" bitfld.long 0x0 0. "SRDE,This bit specifies whether to enable the DMAC. Write 1 to this bit to start the DMAC when this IP operating as a target node receives a Stream Command." "0,1" rgroup.long 0x290++0x3 line.long 0x0 "HSIPCnSRST,Stream Rx Status Register" bitfld.long 0x0 31. "SRA,This bit is set to 1 if HSIPCnSRCT.SRDE is cleared automatically because this IP operating as a target node detects error about receiving Stream Command." "0,1" bitfld.long 0x0 21. "SRE1,This bit is set to 1 if Stream Command data is discarded because the data storage area is full when this IP operating as a target node receives a Stream Command." "0,1" bitfld.long 0x0 20. "SRE0,This bit is set to 1 if an error occurs when this IP operating as a target node transfers received Stream Command data to the AXI bus." "0,1" bitfld.long 0x0 15. "SRTA,This bit indicates the processing status of the received Stream Command when this IP is operating as a target node." "0,1" bitfld.long 0x0 1. "SRC1,This bit is set to 1 when the size of unprocessed data (in the received Stream Command when this IP is operating as a target node) is not less than the value set in HSIPCnSRBC." "0,1" bitfld.long 0x0 0. "SRC0,This bit is set to 1 when the size of unprocessed data (in the received Stream Command when this IP is operating as a target node) is not 0." "0,1" group.long 0x298++0x3 line.long 0x0 "HSIPCnSRSC,Stream Rx Status Clear Register" bitfld.long 0x0 31. "SRAC,Writing 1 to this bit clears the HSIPCnSRST.SRA bit." "0,1" bitfld.long 0x0 21. "SREC1,Writing 1 to this bit clears the HSIPCnSRST.SRE1 bit." "0,1" bitfld.long 0x0 20. "SREC0,Writing 1 to this bit clears the HSIPCnSRST.SRE0 bit." "0,1" group.long 0x2A0++0x3 line.long 0x0 "HSIPCnSRIE,Stream Rx Interrupt Enable Register" bitfld.long 0x0 31. "SRAE,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnSRST.SRA bit." "0,1" bitfld.long 0x0 21. "SREE1,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnSRST.SRE1 bit." "0,1" bitfld.long 0x0 20. "SREE0,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnSRST.SRE0 bit." "0,1" bitfld.long 0x0 1. "SRCE1,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnSRST.SRC1 bit." "0,1" bitfld.long 0x0 0. "SRCE0,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnSRST.SRC0 bit." "0,1" group.long 0x2A8++0x3 line.long 0x0 "HSIPCnSRDA,Stream Rx Destination Area Start Address Register" hexmask.long 0x0 4.--31. 1. "SRDA,These bits specify the start address of the area to store data when this IP operating as a target node receives a Stream Command." group.long 0x2B0++0x3 line.long 0x0 "HSIPCnSRDS,Stream Rx Destination Area Size Register" hexmask.long.tbyte 0x0 4.--24. 1. "SRDS,These bits specify the valid size of the area to store data when this IP operating as a target node receives a Stream Command. Write 1 to all the bits lower than those corresponding to the valid size value and write 0 to all the bits higher than.." group.long 0x2B8++0x3 line.long 0x0 "HSIPCnSRBC,Stream Rx Byte Count Register" hexmask.long.tbyte 0x0 4.--24. 1. "SRBC,These bits specify the number of bytes that triggers a notification when this IP operating as a target node receives a Stream Command. When the size of unprocessed data reaches or exceeds the value specified in these bits the HSIPCnSRST.SRC1 bit.." rgroup.long 0x2C0++0x3 line.long 0x0 "HSIPCnSRWP,Stream Rx Write Pointer Register" hexmask.long.tbyte 0x0 4.--24. 1. "SRWP,These bits indicate the value of the write pointer (offset value from start address) to the area to store received data when this IP operating as a target node receives a Stream Command. The number of valid bits of the pointer corresponds to the.." bitfld.long 0x0 0. "SRWT,This bit is a toggle bit for the SRWP bits." "0,1" group.long 0x2C8++0x3 line.long 0x0 "HSIPCnSRRP,Stream Rx Read Pointer Register" hexmask.long.tbyte 0x0 4.--24. 1. "SRRP,These bits indicate the value of the read pointer (offset value from start address) to the area to store received data when this IP operating as a target node receives a Stream Command. The number of valid bits of the pointer corresponds to the.." bitfld.long 0x0 0. "SRRT,This bit is a toggle bit for the SRRP bits." "0,1" group.long 0x400++0x3 line.long 0x0 "HSIPCnCMD0,Channel 0 Mode Register" bitfld.long 0x0 16. "TNME_N,This bit specifies whether to enable the target node function." "0,1" bitfld.long 0x0 0. "INME_N,This bit specifies whether to enable the initiator node function." "0,1" group.long 0x408++0x3 line.long 0x0 "HSIPCnCCT0,Channel 0 Control Register" bitfld.long 0x0 7. "CTYW_N,“1” must be written to this bit at the same time as writing data to the CTY(N) bits when this IP operating as an initiator node transmits a request Command other than a Stream Command." "0,1" hexmask.long.byte 0x0 0.--4. 1. "CTY_N,A Command type must be set in these bits when this IP operating as an initiator node transmits a request Command other than a Stream Command. When this IP transmits a Command 1 must be written to the CTYW(N) bit at the same time as writing data.." rgroup.long 0x410++0x3 line.long 0x0 "HSIPCnCST0,Channel 0 Status Register" bitfld.long 0x0 31. "CRE_N,This bit is set to 1 when a Command causing a CRC error is detected in the channel corresponding to the bit number." "0,1" bitfld.long 0x0 20. "BRE_N,This bit is set to 1 when an error has occurred during data transfer in the AXI bus by a Read or Write Command received by this IP operating as a target node." "0,1" bitfld.long 0x0 16. "TER_N,This bit is set to 1 when this IP operating as a target mode receives an Event Command." "0,1" bitfld.long 0x0 15. "RDY_N,This bit indicates whether this IP operating as an initiator node can transmit request Commands other than Stream Commands." "0,1" bitfld.long 0x0 7. "AOE_N,This bit is set to 1 when an error that cannot be classified as the one indicated by the AKE or IDE bit is detected after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 5. "IDE_N,This bit is set to 1 when a reply Command (ACK NACK or Read Answer) causing a transaction ID error is detected after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 4. "TOE_N,This bit is set to 1 when this IP cannot receive a response within the time set in HSIPCnMRT after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 2. "AKE_N,This bit is set to 1 when this IP receives an NACK Command after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 1. "AKR_N,This bit is set to 1 when this IP receives an ACK Command after this IP operating as an initiator node has transmitted a Write or Event Command." "0,1" bitfld.long 0x0 0. "RAR_N,This bit is set to 1 when this IP receives a Read Answer Command after this IP operating as an initiator node has transmitted a Read or ID Command." "0,1" group.long 0x418++0x3 line.long 0x0 "HSIPCnCSC0,Channel 0 Status Clear Register" bitfld.long 0x0 31. "CREC_N,Writing 1 to this bit clears the HSIPCnCST(N).CRE(N) bit." "0,1" bitfld.long 0x0 20. "BREC_N,Writing 1 to this bit clears the HSIPCnCST(N).BRE(N) bit." "0,1" bitfld.long 0x0 16. "TERC_N,Writing 1 to this bit clears the HSIPCnCST(N).TER(N) bit." "0,1" bitfld.long 0x0 7. "AOEC_N,Writing 1 to this bit clears the HSIPCnCST(N).AOE(N) bit." "0,1" bitfld.long 0x0 5. "IDEC_N,Writing 1 to this bit clears the HSIPCnCST(N).IDE(N) bit." "0,1" bitfld.long 0x0 4. "TOEC_N,Writing 1 to this bit clears the HSIPCnCST(N).TOE(N) bit." "0,1" bitfld.long 0x0 2. "AKEC_N,Writing 1 to this bit clears the HSIPCnCST(N).AKE(N) bit." "0,1" bitfld.long 0x0 1. "AKRC_N,Writing 1 to this bit clears the HSIPCnCST(N).AKR(N) bit." "0,1" bitfld.long 0x0 0. "RARC_N,Writing 1 to this bit clears the HSIPCnCST(N).RAR(N) bit." "0,1" group.long 0x420++0x3 line.long 0x0 "HSIPCnCIE0,Channel 0 Interrupt Enable Register" bitfld.long 0x0 31. "CREE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).CRE(N) bit." "0,1" bitfld.long 0x0 20. "BREE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).BRE(N) bit." "0,1" bitfld.long 0x0 16. "TERE_N,This bit specifies whether to enable the interrupt that is triggered by the This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).TER(N) bit." "0,1" bitfld.long 0x0 7. "AOEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AOE(N) bit." "0,1" bitfld.long 0x0 5. "IDEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).IDE(N) bit." "0,1" bitfld.long 0x0 4. "TOEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).TOE(N) bit." "0,1" bitfld.long 0x0 2. "AKEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AKE(N) bit." "0,1" bitfld.long 0x0 1. "AKRE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AKR(N) bit." "0,1" bitfld.long 0x0 0. "RARE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).RAR(N) bit." "0,1" group.long 0x428++0x3 line.long 0x0 "HSIPCnCAR0,Channel 0 Read Write Address Register" hexmask.long 0x0 0.--31. 1. "CAR_N,These bits specify the address of the area that is the target of a Read or Write Command when this IP operating as an initiator node transmits the Read or Write Command." group.long 0x430++0x3 line.long 0x0 "HSIPCnCWD0,Channel 0 Write Data Register" hexmask.long 0x0 0.--31. 1. "CWD_N,These bits are used to set the data to be transmitted when this IP operating as an initiator node transmits a Write Command." rgroup.long 0x438++0x3 line.long 0x0 "HSIPCnCRD0,Channel 0 Read Data Register" hexmask.long 0x0 0.--31. 1. "CRD_N,These bits contain the data that is received from a target node after this IP operating as an initiator node has transmitted a Read or ID Command to the target node." group.long 0x460++0x3 line.long 0x0 "HSIPCnCEST0,Channel 0 Error Status Register" group.long 0x468++0x3 line.long 0x0 "HSIPCnCESC0,Channel 0 Error Status Clear Register" group.long 0x470++0x3 line.long 0x0 "HSIPCnCEIE0,Channel 0 Error Interrupt Enable Register" group.long 0x480++0x3 line.long 0x0 "HSIPCnCMD1,Channel 1 Mode Register" bitfld.long 0x0 16. "TNME_N,This bit specifies whether to enable the target node function." "0,1" bitfld.long 0x0 0. "INME_N,This bit specifies whether to enable the initiator node function." "0,1" group.long 0x488++0x3 line.long 0x0 "HSIPCnCCT1,Channel 1 Control Register" bitfld.long 0x0 7. "CTYW_N,“1” must be written to this bit at the same time as writing data to the CTY(N) bits when this IP operating as an initiator node transmits a request Command other than a Stream Command." "0,1" hexmask.long.byte 0x0 0.--4. 1. "CTY_N,A Command type must be set in these bits when this IP operating as an initiator node transmits a request Command other than a Stream Command. When this IP transmits a Command 1 must be written to the CTYW(N) bit at the same time as writing data.." rgroup.long 0x490++0x3 line.long 0x0 "HSIPCnCST1,Channel 1 Status Register" bitfld.long 0x0 31. "CRE_N,This bit is set to 1 when a Command causing a CRC error is detected in the channel corresponding to the bit number." "0,1" bitfld.long 0x0 20. "BRE_N,This bit is set to 1 when an error has occurred during data transfer in the AXI bus by a Read or Write Command received by this IP operating as a target node." "0,1" bitfld.long 0x0 16. "TER_N,This bit is set to 1 when this IP operating as a target mode receives an Event Command." "0,1" bitfld.long 0x0 15. "RDY_N,This bit indicates whether this IP operating as an initiator node can transmit request Commands other than Stream Commands." "0,1" bitfld.long 0x0 7. "AOE_N,This bit is set to 1 when an error that cannot be classified as the one indicated by the AKE or IDE bit is detected after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 5. "IDE_N,This bit is set to 1 when a reply Command (ACK NACK or Read Answer) causing a transaction ID error is detected after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 4. "TOE_N,This bit is set to 1 when this IP cannot receive a response within the time set in HSIPCnMRT after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 2. "AKE_N,This bit is set to 1 when this IP receives an NACK Command after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 1. "AKR_N,This bit is set to 1 when this IP receives an ACK Command after this IP operating as an initiator node has transmitted a Write or Event Command." "0,1" bitfld.long 0x0 0. "RAR_N,This bit is set to 1 when this IP receives a Read Answer Command after this IP operating as an initiator node has transmitted a Read or ID Command." "0,1" group.long 0x498++0x3 line.long 0x0 "HSIPCnCSC1,Channel 1 Status Clear Register" bitfld.long 0x0 31. "CREC_N,Writing 1 to this bit clears the HSIPCnCST(N).CRE(N) bit." "0,1" bitfld.long 0x0 20. "BREC_N,Writing 1 to this bit clears the HSIPCnCST(N).BRE(N) bit." "0,1" bitfld.long 0x0 16. "TERC_N,Writing 1 to this bit clears the HSIPCnCST(N).TER(N) bit." "0,1" bitfld.long 0x0 7. "AOEC_N,Writing 1 to this bit clears the HSIPCnCST(N).AOE(N) bit." "0,1" bitfld.long 0x0 5. "IDEC_N,Writing 1 to this bit clears the HSIPCnCST(N).IDE(N) bit." "0,1" bitfld.long 0x0 4. "TOEC_N,Writing 1 to this bit clears the HSIPCnCST(N).TOE(N) bit." "0,1" bitfld.long 0x0 2. "AKEC_N,Writing 1 to this bit clears the HSIPCnCST(N).AKE(N) bit." "0,1" bitfld.long 0x0 1. "AKRC_N,Writing 1 to this bit clears the HSIPCnCST(N).AKR(N) bit." "0,1" bitfld.long 0x0 0. "RARC_N,Writing 1 to this bit clears the HSIPCnCST(N).RAR(N) bit." "0,1" group.long 0x4A0++0x3 line.long 0x0 "HSIPCnCIE1,Channel 1 Interrupt Enable Register" bitfld.long 0x0 31. "CREE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).CRE(N) bit." "0,1" bitfld.long 0x0 20. "BREE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).BRE(N) bit." "0,1" bitfld.long 0x0 16. "TERE_N,This bit specifies whether to enable the interrupt that is triggered by the This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).TER(N) bit." "0,1" bitfld.long 0x0 7. "AOEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AOE(N) bit." "0,1" bitfld.long 0x0 5. "IDEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).IDE(N) bit." "0,1" bitfld.long 0x0 4. "TOEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).TOE(N) bit." "0,1" bitfld.long 0x0 2. "AKEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AKE(N) bit." "0,1" bitfld.long 0x0 1. "AKRE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AKR(N) bit." "0,1" bitfld.long 0x0 0. "RARE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).RAR(N) bit." "0,1" group.long 0x4A8++0x3 line.long 0x0 "HSIPCnCAR1,Channel 1 Read Write Address Register" hexmask.long 0x0 0.--31. 1. "CAR_N,These bits specify the address of the area that is the target of a Read or Write Command when this IP operating as an initiator node transmits the Read or Write Command." group.long 0x4B0++0x3 line.long 0x0 "HSIPCnCWD1,Channel 1 Write Data Register" hexmask.long 0x0 0.--31. 1. "CWD_N,These bits are used to set the data to be transmitted when this IP operating as an initiator node transmits a Write Command." rgroup.long 0x4B8++0x3 line.long 0x0 "HSIPCnCRD1,Channel 1 Read Data Register" hexmask.long 0x0 0.--31. 1. "CRD_N,These bits contain the data that is received from a target node after this IP operating as an initiator node has transmitted a Read or ID Command to the target node." group.long 0x4E0++0x3 line.long 0x0 "HSIPCnCEST1,Channel 1 Error Status Register" group.long 0x4E8++0x3 line.long 0x0 "HSIPCnCESC1,Channel 1 Error Status Clear Register" group.long 0x4F0++0x3 line.long 0x0 "HSIPCnCEIE1,Channel 1 Error Interrupt Enable Register" group.long 0x500++0x3 line.long 0x0 "HSIPCnCMD2,Channel 2 Mode Register" bitfld.long 0x0 16. "TNME_N,This bit specifies whether to enable the target node function." "0,1" bitfld.long 0x0 0. "INME_N,This bit specifies whether to enable the initiator node function." "0,1" group.long 0x508++0x3 line.long 0x0 "HSIPCnCCT2,Channel 2 Control Register" bitfld.long 0x0 7. "CTYW_N,“1” must be written to this bit at the same time as writing data to the CTY(N) bits when this IP operating as an initiator node transmits a request Command other than a Stream Command." "0,1" hexmask.long.byte 0x0 0.--4. 1. "CTY_N,A Command type must be set in these bits when this IP operating as an initiator node transmits a request Command other than a Stream Command. When this IP transmits a Command 1 must be written to the CTYW(N) bit at the same time as writing data.." rgroup.long 0x510++0x3 line.long 0x0 "HSIPCnCST2,Channel 2 Status Register" bitfld.long 0x0 31. "CRE_N,This bit is set to 1 when a Command causing a CRC error is detected in the channel corresponding to the bit number." "0,1" bitfld.long 0x0 20. "BRE_N,This bit is set to 1 when an error has occurred during data transfer in the AXI bus by a Read or Write Command received by this IP operating as a target node." "0,1" bitfld.long 0x0 16. "TER_N,This bit is set to 1 when this IP operating as a target mode receives an Event Command." "0,1" bitfld.long 0x0 15. "RDY_N,This bit indicates whether this IP operating as an initiator node can transmit request Commands other than Stream Commands." "0,1" bitfld.long 0x0 7. "AOE_N,This bit is set to 1 when an error that cannot be classified as the one indicated by the AKE or IDE bit is detected after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 5. "IDE_N,This bit is set to 1 when a reply Command (ACK NACK or Read Answer) causing a transaction ID error is detected after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 4. "TOE_N,This bit is set to 1 when this IP cannot receive a response within the time set in HSIPCnMRT after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 2. "AKE_N,This bit is set to 1 when this IP receives an NACK Command after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 1. "AKR_N,This bit is set to 1 when this IP receives an ACK Command after this IP operating as an initiator node has transmitted a Write or Event Command." "0,1" bitfld.long 0x0 0. "RAR_N,This bit is set to 1 when this IP receives a Read Answer Command after this IP operating as an initiator node has transmitted a Read or ID Command." "0,1" group.long 0x518++0x3 line.long 0x0 "HSIPCnCSC2,Channel 2 Status Clear Register" bitfld.long 0x0 31. "CREC_N,Writing 1 to this bit clears the HSIPCnCST(N).CRE(N) bit." "0,1" bitfld.long 0x0 20. "BREC_N,Writing 1 to this bit clears the HSIPCnCST(N).BRE(N) bit." "0,1" bitfld.long 0x0 16. "TERC_N,Writing 1 to this bit clears the HSIPCnCST(N).TER(N) bit." "0,1" bitfld.long 0x0 7. "AOEC_N,Writing 1 to this bit clears the HSIPCnCST(N).AOE(N) bit." "0,1" bitfld.long 0x0 5. "IDEC_N,Writing 1 to this bit clears the HSIPCnCST(N).IDE(N) bit." "0,1" bitfld.long 0x0 4. "TOEC_N,Writing 1 to this bit clears the HSIPCnCST(N).TOE(N) bit." "0,1" bitfld.long 0x0 2. "AKEC_N,Writing 1 to this bit clears the HSIPCnCST(N).AKE(N) bit." "0,1" bitfld.long 0x0 1. "AKRC_N,Writing 1 to this bit clears the HSIPCnCST(N).AKR(N) bit." "0,1" bitfld.long 0x0 0. "RARC_N,Writing 1 to this bit clears the HSIPCnCST(N).RAR(N) bit." "0,1" group.long 0x520++0x3 line.long 0x0 "HSIPCnCIE2,Channel 2 Interrupt Enable Register" bitfld.long 0x0 31. "CREE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).CRE(N) bit." "0,1" bitfld.long 0x0 20. "BREE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).BRE(N) bit." "0,1" bitfld.long 0x0 16. "TERE_N,This bit specifies whether to enable the interrupt that is triggered by the This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).TER(N) bit." "0,1" bitfld.long 0x0 7. "AOEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AOE(N) bit." "0,1" bitfld.long 0x0 5. "IDEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).IDE(N) bit." "0,1" bitfld.long 0x0 4. "TOEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).TOE(N) bit." "0,1" bitfld.long 0x0 2. "AKEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AKE(N) bit." "0,1" bitfld.long 0x0 1. "AKRE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AKR(N) bit." "0,1" bitfld.long 0x0 0. "RARE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).RAR(N) bit." "0,1" group.long 0x528++0x3 line.long 0x0 "HSIPCnCAR2,Channel 2 Read Write Address Register" hexmask.long 0x0 0.--31. 1. "CAR_N,These bits specify the address of the area that is the target of a Read or Write Command when this IP operating as an initiator node transmits the Read or Write Command." group.long 0x530++0x3 line.long 0x0 "HSIPCnCWD2,Channel 2 Write Data Register" hexmask.long 0x0 0.--31. 1. "CWD_N,These bits are used to set the data to be transmitted when this IP operating as an initiator node transmits a Write Command." rgroup.long 0x538++0x3 line.long 0x0 "HSIPCnCRD2,Channel 2 Read Data Register" hexmask.long 0x0 0.--31. 1. "CRD_N,These bits contain the data that is received from a target node after this IP operating as an initiator node has transmitted a Read or ID Command to the target node." group.long 0x560++0x3 line.long 0x0 "HSIPCnCEST2,Channel 2 Error Status Register" group.long 0x568++0x3 line.long 0x0 "HSIPCnCESC2,Channel 2 Error Status Clear Register" group.long 0x570++0x3 line.long 0x0 "HSIPCnCEIE2,Channel 2 Error Interrupt Enable Register" group.long 0x580++0x3 line.long 0x0 "HSIPCnCMD3,Channel 3 Mode Register" bitfld.long 0x0 16. "TNME_N,This bit specifies whether to enable the target node function." "0,1" bitfld.long 0x0 0. "INME_N,This bit specifies whether to enable the initiator node function." "0,1" group.long 0x588++0x3 line.long 0x0 "HSIPCnCCT3,Channel 3 Control Register" bitfld.long 0x0 7. "CTYW_N,“1” must be written to this bit at the same time as writing data to the CTY(N) bits when this IP operating as an initiator node transmits a request Command other than a Stream Command." "0,1" hexmask.long.byte 0x0 0.--4. 1. "CTY_N,A Command type must be set in these bits when this IP operating as an initiator node transmits a request Command other than a Stream Command. When this IP transmits a Command 1 must be written to the CTYW(N) bit at the same time as writing data.." rgroup.long 0x590++0x3 line.long 0x0 "HSIPCnCST3,Channel 3 Status Register" bitfld.long 0x0 31. "CRE_N,This bit is set to 1 when a Command causing a CRC error is detected in the channel corresponding to the bit number." "0,1" bitfld.long 0x0 20. "BRE_N,This bit is set to 1 when an error has occurred during data transfer in the AXI bus by a Read or Write Command received by this IP operating as a target node." "0,1" bitfld.long 0x0 16. "TER_N,This bit is set to 1 when this IP operating as a target mode receives an Event Command." "0,1" bitfld.long 0x0 15. "RDY_N,This bit indicates whether this IP operating as an initiator node can transmit request Commands other than Stream Commands." "0,1" bitfld.long 0x0 7. "AOE_N,This bit is set to 1 when an error that cannot be classified as the one indicated by the AKE or IDE bit is detected after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 5. "IDE_N,This bit is set to 1 when a reply Command (ACK NACK or Read Answer) causing a transaction ID error is detected after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 4. "TOE_N,This bit is set to 1 when this IP cannot receive a response within the time set in HSIPCnMRT after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 2. "AKE_N,This bit is set to 1 when this IP receives an NACK Command after this IP operating as an initiator node has transmitted a Read Write Event or ID Command." "0,1" bitfld.long 0x0 1. "AKR_N,This bit is set to 1 when this IP receives an ACK Command after this IP operating as an initiator node has transmitted a Write or Event Command." "0,1" bitfld.long 0x0 0. "RAR_N,This bit is set to 1 when this IP receives a Read Answer Command after this IP operating as an initiator node has transmitted a Read or ID Command." "0,1" group.long 0x598++0x3 line.long 0x0 "HSIPCnCSC3,Channel 3 Status Clear Register" bitfld.long 0x0 31. "CREC_N,Writing 1 to this bit clears the HSIPCnCST(N).CRE(N) bit." "0,1" bitfld.long 0x0 20. "BREC_N,Writing 1 to this bit clears the HSIPCnCST(N).BRE(N) bit." "0,1" bitfld.long 0x0 16. "TERC_N,Writing 1 to this bit clears the HSIPCnCST(N).TER(N) bit." "0,1" bitfld.long 0x0 7. "AOEC_N,Writing 1 to this bit clears the HSIPCnCST(N).AOE(N) bit." "0,1" bitfld.long 0x0 5. "IDEC_N,Writing 1 to this bit clears the HSIPCnCST(N).IDE(N) bit." "0,1" bitfld.long 0x0 4. "TOEC_N,Writing 1 to this bit clears the HSIPCnCST(N).TOE(N) bit." "0,1" bitfld.long 0x0 2. "AKEC_N,Writing 1 to this bit clears the HSIPCnCST(N).AKE(N) bit." "0,1" bitfld.long 0x0 1. "AKRC_N,Writing 1 to this bit clears the HSIPCnCST(N).AKR(N) bit." "0,1" bitfld.long 0x0 0. "RARC_N,Writing 1 to this bit clears the HSIPCnCST(N).RAR(N) bit." "0,1" group.long 0x5A0++0x3 line.long 0x0 "HSIPCnCIE3,Channel 3 Interrupt Enable Register" bitfld.long 0x0 31. "CREE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).CRE(N) bit." "0,1" bitfld.long 0x0 20. "BREE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).BRE(N) bit." "0,1" bitfld.long 0x0 16. "TERE_N,This bit specifies whether to enable the interrupt that is triggered by the This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).TER(N) bit." "0,1" bitfld.long 0x0 7. "AOEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AOE(N) bit." "0,1" bitfld.long 0x0 5. "IDEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).IDE(N) bit." "0,1" bitfld.long 0x0 4. "TOEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).TOE(N) bit." "0,1" bitfld.long 0x0 2. "AKEE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AKE(N) bit." "0,1" bitfld.long 0x0 1. "AKRE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).AKR(N) bit." "0,1" bitfld.long 0x0 0. "RARE_N,This bit specifies whether to enable the interrupt that is triggered by the HSIPCnCST(N).RAR(N) bit." "0,1" group.long 0x5A8++0x3 line.long 0x0 "HSIPCnCAR3,Channel 3 Read Write Address Register" hexmask.long 0x0 0.--31. 1. "CAR_N,These bits specify the address of the area that is the target of a Read or Write Command when this IP operating as an initiator node transmits the Read or Write Command." group.long 0x5B0++0x3 line.long 0x0 "HSIPCnCWD3,Channel 3 Write Data Register" hexmask.long 0x0 0.--31. 1. "CWD_N,These bits are used to set the data to be transmitted when this IP operating as an initiator node transmits a Write Command." rgroup.long 0x5B8++0x3 line.long 0x0 "HSIPCnCRD3,Channel 3 Read Data Register" hexmask.long 0x0 0.--31. 1. "CRD_N,These bits contain the data that is received from a target node after this IP operating as an initiator node has transmitted a Read or ID Command to the target node." group.long 0x5E0++0x3 line.long 0x0 "HSIPCnCEST3,Channel 3 Error Status Register" group.long 0x5E8++0x3 line.long 0x0 "HSIPCnCESC3,Channel 3 Error Status Clear Register" group.long 0x5F0++0x3 line.long 0x0 "HSIPCnCEIE3,Channel 3 Error Interrupt Enable Register" tree.end tree.end tree "KCRC" base ad:0x0 tree "KCRC_0" base ad:0xE7020000 group.long 0x0++0x3 line.long 0x0 "KCRCmDIN,KCRC Data Input Register" hexmask.long 0x0 0.--31. 1. "DIN,Input Data for CRC calculation." group.long 0x80++0x3 line.long 0x0 "KCRCmDOUT,KCRC Data Output Register" hexmask.long 0x0 0.--31. 1. "DOUT,Output Data for CRC calculation." group.long 0x90++0x3 line.long 0x0 "KCRCmCTL,This register provided CRC calculate setting." hexmask.long.byte 0x0 16.--20. 1. "PSIZE,Polynomial size" bitfld.long 0x0 8. "CMD0,Calculate Mode 0" "0: Mode N,1: Mode R" bitfld.long 0x0 5. "CMD1,Calculate Mode 1" "0: Mode N,1: Mode R" bitfld.long 0x0 4. "CMD2,Calculate Mode 2" "0: Mode M,1: Mode L" bitfld.long 0x0 0.--2. "DW,Input Data size select" "0: 32 bit fix mode,1: 16 bit fix mode,?,?,?,?,?,?" group.long 0xA0++0x3 line.long 0x0 "KCRCmPOLY,KCRC Polynomial Register" hexmask.long 0x0 0.--31. 1. "POLY,Polynomial for CRC calculation." group.long 0xB0++0x3 line.long 0x0 "KCRCmXOR,KCRC XOR Mask Register" hexmask.long 0x0 0.--31. 1. "XOR,XOR mask for Data output." tree.end tree "KCRC_1" base ad:0xE7030000 group.long 0x0++0x3 line.long 0x0 "KCRCmDIN,KCRC Data Input Register" hexmask.long 0x0 0.--31. 1. "DIN,Input Data for CRC calculation." group.long 0x80++0x3 line.long 0x0 "KCRCmDOUT,KCRC Data Output Register" hexmask.long 0x0 0.--31. 1. "DOUT,Output Data for CRC calculation." group.long 0x90++0x3 line.long 0x0 "KCRCmCTL,This register provided CRC calculate setting." hexmask.long.byte 0x0 16.--20. 1. "PSIZE,Polynomial size" bitfld.long 0x0 8. "CMD0,Calculate Mode 0" "0: Mode N,1: Mode R" bitfld.long 0x0 5. "CMD1,Calculate Mode 1" "0: Mode N,1: Mode R" bitfld.long 0x0 4. "CMD2,Calculate Mode 2" "0: Mode M,1: Mode L" bitfld.long 0x0 0.--2. "DW,Input Data size select" "0: 32 bit fix mode,1: 16 bit fix mode,?,?,?,?,?,?" group.long 0xA0++0x3 line.long 0x0 "KCRCmPOLY,KCRC Polynomial Register" hexmask.long 0x0 0.--31. 1. "POLY,Polynomial for CRC calculation." group.long 0xB0++0x3 line.long 0x0 "KCRCmXOR,KCRC XOR Mask Register" hexmask.long 0x0 0.--31. 1. "XOR,XOR mask for Data output." tree.end tree "KCRC_2" base ad:0xE7040000 group.long 0x0++0x3 line.long 0x0 "KCRCmDIN,KCRC Data Input Register" hexmask.long 0x0 0.--31. 1. "DIN,Input Data for CRC calculation." group.long 0x80++0x3 line.long 0x0 "KCRCmDOUT,KCRC Data Output Register" hexmask.long 0x0 0.--31. 1. "DOUT,Output Data for CRC calculation." group.long 0x90++0x3 line.long 0x0 "KCRCmCTL,This register provided CRC calculate setting." hexmask.long.byte 0x0 16.--20. 1. "PSIZE,Polynomial size" bitfld.long 0x0 8. "CMD0,Calculate Mode 0" "0: Mode N,1: Mode R" bitfld.long 0x0 5. "CMD1,Calculate Mode 1" "0: Mode N,1: Mode R" bitfld.long 0x0 4. "CMD2,Calculate Mode 2" "0: Mode M,1: Mode L" bitfld.long 0x0 0.--2. "DW,Input Data size select" "0: 32 bit fix mode,1: 16 bit fix mode,?,?,?,?,?,?" group.long 0xA0++0x3 line.long 0x0 "KCRCmPOLY,KCRC Polynomial Register" hexmask.long 0x0 0.--31. 1. "POLY,Polynomial for CRC calculation." group.long 0xB0++0x3 line.long 0x0 "KCRCmXOR,KCRC XOR Mask Register" hexmask.long 0x0 0.--31. 1. "XOR,XOR mask for Data output." tree.end tree "KCRC_3" base ad:0xE7050000 group.long 0x0++0x3 line.long 0x0 "KCRCmDIN,KCRC Data Input Register" hexmask.long 0x0 0.--31. 1. "DIN,Input Data for CRC calculation." group.long 0x80++0x3 line.long 0x0 "KCRCmDOUT,KCRC Data Output Register" hexmask.long 0x0 0.--31. 1. "DOUT,Output Data for CRC calculation." group.long 0x90++0x3 line.long 0x0 "KCRCmCTL,This register provided CRC calculate setting." hexmask.long.byte 0x0 16.--20. 1. "PSIZE,Polynomial size" bitfld.long 0x0 8. "CMD0,Calculate Mode 0" "0: Mode N,1: Mode R" bitfld.long 0x0 5. "CMD1,Calculate Mode 1" "0: Mode N,1: Mode R" bitfld.long 0x0 4. "CMD2,Calculate Mode 2" "0: Mode M,1: Mode L" bitfld.long 0x0 0.--2. "DW,Input Data size select" "0: 32 bit fix mode,1: 16 bit fix mode,?,?,?,?,?,?" group.long 0xA0++0x3 line.long 0x0 "KCRCmPOLY,KCRC Polynomial Register" hexmask.long 0x0 0.--31. 1. "POLY,Polynomial for CRC calculation." group.long 0xB0++0x3 line.long 0x0 "KCRCmXOR,KCRC XOR Mask Register" hexmask.long 0x0 0.--31. 1. "XOR,XOR mask for Data output." tree.end tree.end tree "LIFEC" base ad:0xE6110000 group.long 0x238++0x3 line.long 0x0 "DBSCRM,DBSCRM controls SDRAM write/read data scramble/de-scramble function." hexmask.long 0x0 0.--31. 1. "DATA,All 0 : Disable scramble/descramble function." tree.end tree "MFIS" base ad:0xE6260000 group.long 0xC0++0x1F line.long 0x0 "MFISLCKR0,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to any read access and it retains this value until the.." bitfld.long 0x0 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x4 "MFISLCKR1,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to any read access and it retains this value until the.." bitfld.long 0x4 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x8 "MFISLCKR2,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to any read access and it retains this value until the.." bitfld.long 0x8 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xC "MFISLCKR3,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to any read access and it retains this value until the.." bitfld.long 0xC 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x10 "MFISLCKR4,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to any read access and it retains this value until the.." bitfld.long 0x10 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x14 "MFISLCKR5,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to any read access and it retains this value until the.." bitfld.long 0x14 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x18 "MFISLCKR6,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to any read access and it retains this value until the.." bitfld.long 0x18 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x1C "MFISLCKR7,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to any read access and it retains this value until the.." bitfld.long 0x1C 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" group.long 0x160++0xF line.long 0x0 "MFICKMCSR,Clock Monitor Control/Status Register" rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - MFICKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline rbitfld.long 0x0 18. "RSTMMON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" rbitfld.long 0x0 17. "RSTMSMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "MFICKMECR,Clock Monitor Error Clear Register" bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "MFICKMLCH,Clock Monitor Limit Count H Register" hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "MFICKMLCL,Clock Monitor Limit Count L Register" hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The lower limit to judge as expected oscillation." rgroup.long 0x170++0xF line.long 0x0 "MFICKMCNT,Clock Monitor Count Register" hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "MFICKMCNTE,Clock Monitor Count on Error Register" bitfld.long 0x4 31. "VLD,Valid bit." "0: UPDCNTE & MONCNTE are showing invalid value,1: UPDCNTE & MONCNTE are showing valid value" hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE,MFICKMCNT.UPDCNT value when the first error occurred." newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE,The counter value of clock monitor when the first error occurred." line.long 0x8 "MFICKMMDR,Clock Monitor Mode Register" hexmask.long.word 0x8 0.--15. 1. "MODE" line.long 0xC "MFICKMSR,Clock Monitor Status Register" bitfld.long 0xC 0. "CKM_STS,STS bit[15] of Clock Monitor" "0,1" group.long 0x1400++0x3 line.long 0x0 "MFISARIICR0,MFISARIICR is a read/write register to generate the interrupt from ARM Application Core domain to ARM Realtime Core domain by software." hexmask.long.word 0x0 1.--15. 1. "IIC,Interrupt Source (from ARM Application core to ARM Realtime Core)" bitfld.long 0x0 0. "IIR,Internal Interrupt Request" "0,1" group.long 0x2408++0x3 line.long 0x0 "MFISARIICR1,MFISARIICR is a read/write register to generate the interrupt from ARM Application Core domain to ARM Realtime Core domain by software." hexmask.long.word 0x0 1.--15. 1. "IIC,Interrupt Source (from ARM Application core to ARM Realtime Core)" bitfld.long 0x0 0. "IIR,Internal Interrupt Request" "0,1" group.long 0x3410++0x3 line.long 0x0 "MFISARIICR2,MFISARIICR is a read/write register to generate the interrupt from ARM Application Core domain to ARM Realtime Core domain by software." hexmask.long.word 0x0 1.--15. 1. "IIC,Interrupt Source (from ARM Application core to ARM Realtime Core)" bitfld.long 0x0 0. "IIR,Internal Interrupt Request" "0,1" group.long 0x4418++0x3 line.long 0x0 "MFISARIICR3,MFISARIICR is a read/write register to generate the interrupt from ARM Application Core domain to ARM Realtime Core domain by software." hexmask.long.word 0x0 1.--15. 1. "IIC,Interrupt Source (from ARM Application core to ARM Realtime Core)" bitfld.long 0x0 0. "IIR,Internal Interrupt Request" "0,1" group.long 0x5420++0x3 line.long 0x0 "MFISARIICR4,MFISARIICR is a read/write register to generate the interrupt from ARM Application Core domain to ARM Realtime Core domain by software." hexmask.long.word 0x0 1.--15. 1. "IIC,Interrupt Source (from ARM Application core to ARM Realtime Core)" bitfld.long 0x0 0. "IIR,Internal Interrupt Request" "0,1" group.long 0x6428++0x3 line.long 0x0 "MFISARIICR5,MFISARIICR is a read/write register to generate the interrupt from ARM Application Core domain to ARM Realtime Core domain by software." hexmask.long.word 0x0 1.--15. 1. "IIC,Interrupt Source (from ARM Application core to ARM Realtime Core)" bitfld.long 0x0 0. "IIR,Internal Interrupt Request" "0,1" group.long 0x7430++0x3 line.long 0x0 "MFISARIICR6,MFISARIICR is a read/write register to generate the interrupt from ARM Application Core domain to ARM Realtime Core domain by software." hexmask.long.word 0x0 1.--15. 1. "IIC,Interrupt Source (from ARM Application core to ARM Realtime Core)" bitfld.long 0x0 0. "IIR,Internal Interrupt Request" "0,1" group.long 0x8438++0x3 line.long 0x0 "MFISARIICR7,MFISARIICR is a read/write register to generate the interrupt from ARM Application Core domain to ARM Realtime Core domain by software." hexmask.long.word 0x0 1.--15. 1. "IIC,Interrupt Source (from ARM Application core to ARM Realtime Core)" bitfld.long 0x0 0. "IIR,Internal Interrupt Request" "0,1" group.long 0x9404++0x3 line.long 0x0 "MFISAREICR0,MFISAREICR is a read/write register to generate the interrupt from ARM Realtime Core to ARM Application Core by software." hexmask.long.word 0x0 1.--15. 1. "EIC,Interrupt Source (from ARM Realtime Core to ARM Application Core)" bitfld.long 0x0 0. "EIR,Internal Interrupt Request" "0,1" group.long 0x940C++0x3 line.long 0x0 "MFISAREICR1,MFISAREICR is a read/write register to generate the interrupt from ARM Realtime Core to ARM Application Core by software." hexmask.long.word 0x0 1.--15. 1. "EIC,Interrupt Source (from ARM Realtime Core to ARM Application Core)" bitfld.long 0x0 0. "EIR,Internal Interrupt Request" "0,1" group.long 0x9414++0x3 line.long 0x0 "MFISAREICR2,MFISAREICR is a read/write register to generate the interrupt from ARM Realtime Core to ARM Application Core by software." hexmask.long.word 0x0 1.--15. 1. "EIC,Interrupt Source (from ARM Realtime Core to ARM Application Core)" bitfld.long 0x0 0. "EIR,Internal Interrupt Request" "0,1" group.long 0x941C++0x3 line.long 0x0 "MFISAREICR3,MFISAREICR is a read/write register to generate the interrupt from ARM Realtime Core to ARM Application Core by software." hexmask.long.word 0x0 1.--15. 1. "EIC,Interrupt Source (from ARM Realtime Core to ARM Application Core)" bitfld.long 0x0 0. "EIR,Internal Interrupt Request" "0,1" group.long 0x9424++0x3 line.long 0x0 "MFISAREICR4,MFISAREICR is a read/write register to generate the interrupt from ARM Realtime Core to ARM Application Core by software." hexmask.long.word 0x0 1.--15. 1. "EIC,Interrupt Source (from ARM Realtime Core to ARM Application Core)" bitfld.long 0x0 0. "EIR,Internal Interrupt Request" "0,1" group.long 0x942C++0x3 line.long 0x0 "MFISAREICR5,MFISAREICR is a read/write register to generate the interrupt from ARM Realtime Core to ARM Application Core by software." hexmask.long.word 0x0 1.--15. 1. "EIC,Interrupt Source (from ARM Realtime Core to ARM Application Core)" bitfld.long 0x0 0. "EIR,Internal Interrupt Request" "0,1" group.long 0x9434++0x3 line.long 0x0 "MFISAREICR6,MFISAREICR is a read/write register to generate the interrupt from ARM Realtime Core to ARM Application Core by software." hexmask.long.word 0x0 1.--15. 1. "EIC,Interrupt Source (from ARM Realtime Core to ARM Application Core)" bitfld.long 0x0 0. "EIR,Internal Interrupt Request" "0,1" group.long 0x943C++0x3 line.long 0x0 "MFISAREICR7,MFISAREICR is a read/write register to generate the interrupt from ARM Realtime Core to ARM Application Core by software." hexmask.long.word 0x0 1.--15. 1. "EIC,Interrupt Source (from ARM Realtime Core to ARM Application Core)" bitfld.long 0x0 0. "EIR,Internal Interrupt Request" "0,1" group.long 0x1440++0x3 line.long 0x0 "MFISARIMBR0,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x0 0.--31. 1. "IMSG,The message buffer for CPU communication or temporary buffer used for general purpose." group.long 0x2444++0x3 line.long 0x0 "MFISARIMBR1,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x0 0.--31. 1. "IMSG,The message buffer for CPU communication or temporary buffer used for general purpose." group.long 0x3448++0x3 line.long 0x0 "MFISARIMBR2,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x0 0.--31. 1. "IMSG,The message buffer for CPU communication or temporary buffer used for general purpose." group.long 0x444C++0x3 line.long 0x0 "MFISARIMBR3,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x0 0.--31. 1. "IMSG,The message buffer for CPU communication or temporary buffer used for general purpose." group.long 0x5450++0x3 line.long 0x0 "MFISARIMBR4,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x0 0.--31. 1. "IMSG,The message buffer for CPU communication or temporary buffer used for general purpose." group.long 0x6454++0x3 line.long 0x0 "MFISARIMBR5,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x0 0.--31. 1. "IMSG,The message buffer for CPU communication or temporary buffer used for general purpose." group.long 0x7458++0x3 line.long 0x0 "MFISARIMBR6,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x0 0.--31. 1. "IMSG,The message buffer for CPU communication or temporary buffer used for general purpose." group.long 0x845C++0x3 line.long 0x0 "MFISARIMBR7,MFISARIMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x0 0.--31. 1. "IMSG,The message buffer for CPU communication or temporary buffer used for general purpose." group.long 0x9460++0x1F line.long 0x0 "MFISAREMBR0,MFISAREMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x0 0.--31. 1. "EMSG,The message buffer for CPU communication or temporary buffer used for general purpose." line.long 0x4 "MFISAREMBR1,MFISAREMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x4 0.--31. 1. "EMSG,The message buffer for CPU communication or temporary buffer used for general purpose." line.long 0x8 "MFISAREMBR2,MFISAREMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x8 0.--31. 1. "EMSG,The message buffer for CPU communication or temporary buffer used for general purpose." line.long 0xC "MFISAREMBR3,MFISAREMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0xC 0.--31. 1. "EMSG,The message buffer for CPU communication or temporary buffer used for general purpose." line.long 0x10 "MFISAREMBR4,MFISAREMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x10 0.--31. 1. "EMSG,The message buffer for CPU communication or temporary buffer used for general purpose." line.long 0x14 "MFISAREMBR5,MFISAREMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x14 0.--31. 1. "EMSG,The message buffer for CPU communication or temporary buffer used for general purpose." line.long 0x18 "MFISAREMBR6,MFISAREMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x18 0.--31. 1. "EMSG,The message buffer for CPU communication or temporary buffer used for general purpose." line.long 0x1C "MFISAREMBR7,MFISAREMBR is a read/write register to inform the interrupt messages to the corresponding CPU. This register can also be used as the general purpose register." hexmask.long 0x1C 0.--31. 1. "EMSG,The message buffer for CPU communication or temporary buffer used for general purpose." rgroup.long 0x600++0x3 line.long 0x0 "MFISOFTMDR,This register indicate the value of input port SOFTMD[3:0]." hexmask.long.byte 0x0 0.--3. 1. "SOFTMD,Show “SOFTMD[3:0]” from FUSE module. Any CPU and USER can read." group.long 0x604++0x3 line.long 0x0 "MFISBTSTSR,This register indicates the boot status and is used for software. No influence on the hardware operation." hexmask.long 0x0 0.--31. 1. "Status,Update and monitor secure status" group.long 0x724++0xDF line.long 0x0 "MFISLCKR8,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains this.." bitfld.long 0x0 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x4 "MFISLCKR9,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains this.." bitfld.long 0x4 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x8 "MFISLCKR10,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x8 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xC "MFISLCKR11,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xC 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x10 "MFISLCKR12,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x10 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x14 "MFISLCKR13,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x14 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x18 "MFISLCKR14,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x18 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x1C "MFISLCKR15,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x1C 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x20 "MFISLCKR16,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x20 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x24 "MFISLCKR17,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x24 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x28 "MFISLCKR18,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x28 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x2C "MFISLCKR19,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x2C 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x30 "MFISLCKR20,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x30 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x34 "MFISLCKR21,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x34 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x38 "MFISLCKR22,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x38 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x3C "MFISLCKR23,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x3C 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x40 "MFISLCKR24,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x40 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x44 "MFISLCKR25,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x44 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x48 "MFISLCKR26,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x48 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x4C "MFISLCKR27,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x4C 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x50 "MFISLCKR28,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x50 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x54 "MFISLCKR29,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x54 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x58 "MFISLCKR30,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x58 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x5C "MFISLCKR31,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x5C 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x60 "MFISLCKR32,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x60 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x64 "MFISLCKR33,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x64 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x68 "MFISLCKR34,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x68 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x6C "MFISLCKR35,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x6C 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x70 "MFISLCKR36,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x70 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x74 "MFISLCKR37,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x74 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x78 "MFISLCKR38,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x78 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x7C "MFISLCKR39,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x7C 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x80 "MFISLCKR40,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x80 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x84 "MFISLCKR41,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x84 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x88 "MFISLCKR42,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x88 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x8C "MFISLCKR43,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x8C 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x90 "MFISLCKR44,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x90 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x94 "MFISLCKR45,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x94 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x98 "MFISLCKR46,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x98 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0x9C "MFISLCKR47,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0x9C 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xA0 "MFISLCKR48,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xA0 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xA4 "MFISLCKR49,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xA4 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xA8 "MFISLCKR50,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xA8 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xAC "MFISLCKR51,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xAC 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xB0 "MFISLCKR52,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xB0 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xB4 "MFISLCKR53,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xB4 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xB8 "MFISLCKR54,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xB8 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xBC "MFISLCKR55,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xBC 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xC0 "MFISLCKR56,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xC0 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xC4 "MFISLCKR57,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xC4 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xC8 "MFISLCKR58,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xC8 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xCC "MFISLCKR59,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xCC 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xD0 "MFISLCKR60,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xD0 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xD4 "MFISLCKR61,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xD4 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xD8 "MFISLCKR62,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xD8 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" line.long 0xDC "MFISLCKR63,MFISLCKR is the dedicated register to realize the “mutex” function by use of LDR/STR instruction. If the value of the LCK bit is 0. this bit is automatically set to “1” in response to reading of the register by a CPU and it retains.." bitfld.long 0xDC 0. "LCK,Mutex Control" "0: Releases the shared resources,1: Forbidden" group.long 0x900++0x7 line.long 0x0 "MFISWPCNTR,This register is used to control write protection for all registers in ECM" hexmask.long.word 0x0 16.--31. 1. "CodeValue,Code Value(H'ACCE)" bitfld.long 0x0 0. "WPD,Write Protection Disable" "0,1" line.long 0x4 "MFISWACNTR,This register is used when write access for the target register is executed. Unless the target register address is written in this register. the contents of the target register cannot not be updated." hexmask.long.word 0x4 16.--31. 1. "CodeValue,Code Value(H'ACCE)" hexmask.long.word 0x4 0.--15. 1. "RegisterAddress,Target register address" group.long 0x2C0++0x7 line.long 0x0 "MFIEDCSIDADDR,Error SID Register for PADDR" eventfld.long 0x0 31. "CLR,Clear SRC_ID which captured at EDC address check" "0: No effect,1: Clear SRC_ID" hexmask.long.tbyte 0x0 8.--30. 1. "Reserved,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "SRC_ID,SRC_ID after EDC error detection" line.long 0x4 "MFIEDCSIDWDATA,Error SID Register for PWDATA" eventfld.long 0x4 31. "CLR,Clear SRC_ID which captured at EDC address check" "0: No effect,1: Clear SRC_ID" hexmask.long.tbyte 0x4 8.--30. 1. "Reserved,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "SRC_ID,SRC_ID after EDC error detection" group.long 0x944++0x3 line.long 0x0 "MFIERRINJ,DCLS Comparator Error Injection" hexmask.long 0x0 2.--31. 1. "Reserved,Reserved" bitfld.long 0x0 1. "POS_INJ,Post-fault injection" "0: Normal Operation,1: Error asserted" newline bitfld.long 0x0 0. "PRE_INJ,Pre-fault injection" "0: Normal Operation,1: Error asserted" group.long 0x8B8++0x3 line.long 0x0 "MFISCMPERRSTSR,DCLS Compare Error Status" hexmask.long.word 0x0 16.--31. 1. "Reserved,Reserved" hexmask.long.word 0x0 4.--15. 1. "CMPERRSTS,Error detection status" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved,Reserved" group.long 0x5F0++0x7 line.long 0x0 "MFISECCTLR,This register is used for the security protection of the MFIS registers." bitfld.long 0x0 0. "SECEN,1: Security No Protection" "0: Security Protection,1: Security No Protection" line.long 0x4 "MFISECSTSR,This register indicates the occurrence of the security error." bitfld.long 0x4 0. "SECTS,1: Security Error Occur" "0: No Error,1: Security Error Occur" rgroup.long 0x5FC++0x3 line.long 0x0 "MFISECSADR,This register holds the request address which security error detected." hexmask.long 0x0 0.--31. 1. "SADR,SADR : Address of accessed Register when “Security Error occurred” (Bit MFISECSTSR[0] = 1’b1)" tree.end tree "MSIOF" base ad:0x0 tree "MSIOF_0" base ad:0xE6E90000 group.long 0x0++0xB line.long 0x0 "SITMDR1,SITMDR1 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0: Slave mode,1: Master mode" bitfld.long 0x0 30. "PCON,Transfer Signal Connection" "0: Setting prohibited,1: MSIOF_SCK and MSIOF_SYNC are used as common.." newline bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" bitfld.long 0x0 26.--27. "SYNCCH,Synchronization Signal Channel Select" "0: The frame synchronization signal output at..,1: The frame synchronization signal output at..,?,?" newline bitfld.long 0x0 25. "SYNCAC,MSIOF_SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,Frame Synchronization Signal Timing Delay" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" newline bitfld.long 0x0 2.--3. "FLD,Frame Synchronization Signal Interval" "0: 0-clock-cycle delay,1: 1-clock-cycle delay,?,?" bitfld.long 0x0 0. "TXSTP,Transmission Stop" "0: Setting prohibited,1: Stop a frame from starting to transmit until.." line.long 0x4 "SITMDR2,SITMDR2 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Data Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SITMDR3,SITMDR3 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.long 0x10++0xB line.long 0x0 "SIRMDR1,SIRMDR1 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0,1" bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" newline bitfld.long 0x0 25. "SYNCAC,SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,MSIOF_SYNC Timing Delay" "0,1,2,3,4,5,6,7" line.long 0x4 "SIRMDR2,SIRMDR2 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Word Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SIRMDR3,SIRMDR3 is a 32-bit readable/writable register that specifies the MSIOF receive mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.word 0x20++0x1 line.word 0x0 "SITSCR,SITSCR is a 16-bit readable/writable register that specifies the conditions for generating transmit serial clock in master mode. SITSCR can be specified when the TRMD bit in SITMDR1 is set to B'1." bitfld.word 0x0 14.--15. "MSSEL,Master Clock Source Select" "0: Selects module clock as the source of master clock,?,?,?" bitfld.word 0x0 13. "MSIMM,Master Clock Direct Select" "0: Selects the clock output from the baud rate..,1: Setting prohibited" newline hexmask.word.byte 0x0 8.--12. 1. "BRPS,Prescaler Setting" bitfld.word 0x0 0.--2. "BRDV,Baud Rate Generator's Division Ratio" "0: Prescaler output × 1/2,1: Prescaler output × 1/4,?,?,?,?,?,?" group.long 0x28++0x3 line.long 0x0 "SICTR,SICTR is a 32-bit readable/writable register that specifies the MSIOF operating state." bitfld.long 0x0 30.--31. "TSCKIZ,Transmit Clock Input/output Polarity Select in SPI Mode When Transmission is Disabled" "0: Inputs MSIOF_SCK when transmission is disabled,1: Setting prohibited,?,?" bitfld.long 0x0 28.--29. "RSCKIZ,Receive Clock Polarity Select in SPI Mode" "0,1,2,3" newline bitfld.long 0x0 27. "TEDG,Transmit Timing" "0: Outputs transmit data at the rising edge of the..,1: Outputs transmit data at the falling edge of the.." bitfld.long 0x0 26. "REDG,Receive Timing" "0: Samples receive data at the falling edge of the..,1: Samples receive data at the rising edge of the.." newline bitfld.long 0x0 22.--23. "TXDIZ,Pin Output When Transmission is Disabled" "0: Outputs 0,1: Outputs 1,?,?" bitfld.long 0x0 15. "TSCKE,Transmit Serial Clock Output Enable" "0: Does not output MSIOF_SCK,1: Outputs MSIOF_SCK" newline bitfld.long 0x0 14. "TFSE,Transmit Frame Synchronization Signal Output Enable" "0: Does not output MSIOF_SYNC,1: Outputs MSIOF_SYNC" bitfld.long 0x0 13. "RSCKE,Receive Serial Clock Output Enable" "0,1" newline bitfld.long 0x0 12. "RFSE,Receive Frame Synchronization Signal Output Enable" "0,1" bitfld.long 0x0 9. "TXE,Transmit Enable" "0: Does not output MSIOF_TXD,1: Outputs MSIOF_TXD" newline bitfld.long 0x0 8. "RXE,Receive Enable" "0: Data is not received through MSIOF_RXD,1: Data can be received through MSIOF_RXD" bitfld.long 0x0 1. "TXRST,Transmit Reset" "0: Transmit operation reset is completed,1: Transmit operation is being reset" newline bitfld.long 0x0 0. "RXRST,Receive Reset" "0: Receive operation reset is completed,1: Receive operation is being reset" group.long 0x30++0x3 line.long 0x0 "SIFCTR,SIFCTR is a 32-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer." bitfld.long 0x0 29.--31. "TFWM,Transmit FIFO Watermark" "0: Issues a transfer request when 64 stages of the..,1: Issues a transfer request when 32 or more stages..,?,?,?,?,?,?" hexmask.long.byte 0x0 20.--26. 1. "TFUA,Transmit FIFO Usable Area" newline bitfld.long 0x0 13.--15. "RFWM,Receive FIFO Watermark" "0: Issues a transfer request when 1 stage or more..,1: Issues a transfer request when 4 or more stages..,?,?,?,?,?,?" hexmask.long.word 0x0 4.--12. 1. "RFUA,Receive FIFO Usable Area" group.long 0x40++0x7 line.long 0x0 "SISTR,Each bit in SISTR becomes an MSIOF interrupt source when the corresponding bit in SIIER is set to 1." bitfld.long 0x0 29. "TFEMP,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty" rbitfld.long 0x0 28. "TDREQ,Transmit Data Transfer Request" "0: The size of empty space in the transmit FIFO has..,1: The size of empty space in the transmit FIFO has.." newline bitfld.long 0x0 23. "TEOF,Frame Transmission End" "0: One-frame transmission end is not detected,1: One-frame transmission end is detected" bitfld.long 0x0 21. "TFSERR,Transmit Frame Synchronization Error" "0: No transmit frame synchronization error has..,1: A transmit frame synchronization error has.." newline bitfld.long 0x0 20. "TFOVF,Transmit FIFO Overflow" "0: No transmit FIFO overflow has occurred,1: A transmit FIFO overflow has occurred" bitfld.long 0x0 19. "TFUDF,Transmit FIFO Underflow" "0: No transmit FIFO underflow has occurred,1: A transmit FIFO underflow has occurred" newline bitfld.long 0x0 13. "RFFUL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" rbitfld.long 0x0 12. "RDREQ,Receive Data Transfer Request" "0: The size of valid data space in the receive FIFO..,1: The size of valid data space in the receive FIFO.." newline bitfld.long 0x0 7. "REOF,Frame Reception End" "0: One-frame reception end is not detected,1: One-frame reception end is detected" bitfld.long 0x0 5. "RFSERR,Receive Frame Synchronization Error" "0: No receive frame synchronization error has..,1: A receive frame synchronization error has occurred" newline bitfld.long 0x0 4. "RFUDF,Receive FIFO Underflow" "0: No receive FIFO underflow has occurred,1: A receive FIFO underflow has occurred" bitfld.long 0x0 3. "RFOVF,Receive FIFO Overflow" "0: No receive FIFO overflow has occurred,1: A receive FIFO overflow has occurred" line.long 0x4 "SIIER,SIIER is a 32-bit readable/writable register that enables the issuance of MSIOF interrupts. When each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1. the MSIOF issues an interrupt." bitfld.long 0x4 31. "TDMAE,Transmit Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" bitfld.long 0x4 29. "TFEMPE,Transmit FIFO Empty Enable" "0: Disables interrupts due to transmit FIFO empty,1: Enables interrupts due to transmit FIFO empty" newline bitfld.long 0x4 28. "TDREQE,Transmit Data Transfer Request Enable" "0: Disables interrupts due to transmit data..,1: Enables interrupts due to transmit data transfer.." bitfld.long 0x4 23. "TEOFE,Frame Transmission End Enable" "0: Disables a frame transmission end interrupt,1: Enables a frame transmission end interrupt" newline bitfld.long 0x4 21. "TFSERRE,Transmit Frame Synchronization Error Enable" "0: Disables interrupts due to transmit frame..,1: Enables interrupts due to transmit frame.." bitfld.long 0x4 20. "TFOVFE,Transmit FIFO Overflow Enable" "0: Disables interrupts due to transmit FIFO overflow,1: Enables interrupts due to transmit FIFO overflow" newline bitfld.long 0x4 19. "TFUDFE,Transmit FIFO Underflow Enable" "0: Disables interrupts due to transmit FIFO underflow,1: Enables interrupts due to transmit FIFO underflow" bitfld.long 0x4 15. "RDMAE,Receive Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" newline bitfld.long 0x4 13. "RFFULE,Receive FIFO Full Enable" "0: Disables interrupts due to receive FIFO full,1: Enables interrupts due to receive FIFO full" bitfld.long 0x4 12. "RDREQE,Receive Data Transfer Request Enable" "0: Disables interrupts due to receive data transfer..,1: Enables interrupts due to receive data transfer.." newline bitfld.long 0x4 7. "REOFE,Frame Reception End Enable" "0: Disables a frame reception end interrupt,1: Enables a frame reception end interrupt" bitfld.long 0x4 5. "RFSERRE,Receive Frame Synchronization Error Enable" "0: Disables interrupts due to receive frame..,1: Enables interrupts due to receive frame.." newline bitfld.long 0x4 4. "RFUDFE,Receive FIFO Underflow Enable" "0: Disables interrupts due to receive FIFO underflow,1: Enables interrupts due to receive FIFO underflow" bitfld.long 0x4 3. "RFOVFE,Receive FIFO Overflow Enable" "0: Disables interrupts due to receive FIFO overflow,1: Enables interrupts due to receive FIFO overflow" wgroup.long 0x50++0x3 line.long 0x0 "SITFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD." hexmask.long.word 0x0 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD." rgroup.long 0x60++0x3 line.long 0x0 "SIRFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD." hexmask.long.word 0x0 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD." tree.end tree "MSIOF_1" base ad:0xE6EA0000 group.long 0x0++0xB line.long 0x0 "SITMDR1,SITMDR1 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0: Slave mode,1: Master mode" bitfld.long 0x0 30. "PCON,Transfer Signal Connection" "0: Setting prohibited,1: MSIOF_SCK and MSIOF_SYNC are used as common.." newline bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" bitfld.long 0x0 26.--27. "SYNCCH,Synchronization Signal Channel Select" "0: The frame synchronization signal output at..,1: The frame synchronization signal output at..,?,?" newline bitfld.long 0x0 25. "SYNCAC,MSIOF_SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,Frame Synchronization Signal Timing Delay" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" newline bitfld.long 0x0 2.--3. "FLD,Frame Synchronization Signal Interval" "0: 0-clock-cycle delay,1: 1-clock-cycle delay,?,?" bitfld.long 0x0 0. "TXSTP,Transmission Stop" "0: Setting prohibited,1: Stop a frame from starting to transmit until.." line.long 0x4 "SITMDR2,SITMDR2 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Data Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SITMDR3,SITMDR3 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.long 0x10++0xB line.long 0x0 "SIRMDR1,SIRMDR1 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0,1" bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" newline bitfld.long 0x0 25. "SYNCAC,SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,MSIOF_SYNC Timing Delay" "0,1,2,3,4,5,6,7" line.long 0x4 "SIRMDR2,SIRMDR2 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Word Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SIRMDR3,SIRMDR3 is a 32-bit readable/writable register that specifies the MSIOF receive mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.word 0x20++0x1 line.word 0x0 "SITSCR,SITSCR is a 16-bit readable/writable register that specifies the conditions for generating transmit serial clock in master mode. SITSCR can be specified when the TRMD bit in SITMDR1 is set to B'1." bitfld.word 0x0 14.--15. "MSSEL,Master Clock Source Select" "0: Selects module clock as the source of master clock,?,?,?" bitfld.word 0x0 13. "MSIMM,Master Clock Direct Select" "0: Selects the clock output from the baud rate..,1: Setting prohibited" newline hexmask.word.byte 0x0 8.--12. 1. "BRPS,Prescaler Setting" bitfld.word 0x0 0.--2. "BRDV,Baud Rate Generator's Division Ratio" "0: Prescaler output × 1/2,1: Prescaler output × 1/4,?,?,?,?,?,?" group.long 0x28++0x3 line.long 0x0 "SICTR,SICTR is a 32-bit readable/writable register that specifies the MSIOF operating state." bitfld.long 0x0 30.--31. "TSCKIZ,Transmit Clock Input/output Polarity Select in SPI Mode When Transmission is Disabled" "0: Inputs MSIOF_SCK when transmission is disabled,1: Setting prohibited,?,?" bitfld.long 0x0 28.--29. "RSCKIZ,Receive Clock Polarity Select in SPI Mode" "0,1,2,3" newline bitfld.long 0x0 27. "TEDG,Transmit Timing" "0: Outputs transmit data at the rising edge of the..,1: Outputs transmit data at the falling edge of the.." bitfld.long 0x0 26. "REDG,Receive Timing" "0: Samples receive data at the falling edge of the..,1: Samples receive data at the rising edge of the.." newline bitfld.long 0x0 22.--23. "TXDIZ,Pin Output When Transmission is Disabled" "0: Outputs 0,1: Outputs 1,?,?" bitfld.long 0x0 15. "TSCKE,Transmit Serial Clock Output Enable" "0: Does not output MSIOF_SCK,1: Outputs MSIOF_SCK" newline bitfld.long 0x0 14. "TFSE,Transmit Frame Synchronization Signal Output Enable" "0: Does not output MSIOF_SYNC,1: Outputs MSIOF_SYNC" bitfld.long 0x0 13. "RSCKE,Receive Serial Clock Output Enable" "0,1" newline bitfld.long 0x0 12. "RFSE,Receive Frame Synchronization Signal Output Enable" "0,1" bitfld.long 0x0 9. "TXE,Transmit Enable" "0: Does not output MSIOF_TXD,1: Outputs MSIOF_TXD" newline bitfld.long 0x0 8. "RXE,Receive Enable" "0: Data is not received through MSIOF_RXD,1: Data can be received through MSIOF_RXD" bitfld.long 0x0 1. "TXRST,Transmit Reset" "0: Transmit operation reset is completed,1: Transmit operation is being reset" newline bitfld.long 0x0 0. "RXRST,Receive Reset" "0: Receive operation reset is completed,1: Receive operation is being reset" group.long 0x30++0x3 line.long 0x0 "SIFCTR,SIFCTR is a 32-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer." bitfld.long 0x0 29.--31. "TFWM,Transmit FIFO Watermark" "0: Issues a transfer request when 64 stages of the..,1: Issues a transfer request when 32 or more stages..,?,?,?,?,?,?" hexmask.long.byte 0x0 20.--26. 1. "TFUA,Transmit FIFO Usable Area" newline bitfld.long 0x0 13.--15. "RFWM,Receive FIFO Watermark" "0: Issues a transfer request when 1 stage or more..,1: Issues a transfer request when 4 or more stages..,?,?,?,?,?,?" hexmask.long.word 0x0 4.--12. 1. "RFUA,Receive FIFO Usable Area" group.long 0x40++0x7 line.long 0x0 "SISTR,Each bit in SISTR becomes an MSIOF interrupt source when the corresponding bit in SIIER is set to 1." bitfld.long 0x0 29. "TFEMP,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty" rbitfld.long 0x0 28. "TDREQ,Transmit Data Transfer Request" "0: The size of empty space in the transmit FIFO has..,1: The size of empty space in the transmit FIFO has.." newline bitfld.long 0x0 23. "TEOF,Frame Transmission End" "0: One-frame transmission end is not detected,1: One-frame transmission end is detected" bitfld.long 0x0 21. "TFSERR,Transmit Frame Synchronization Error" "0: No transmit frame synchronization error has..,1: A transmit frame synchronization error has.." newline bitfld.long 0x0 20. "TFOVF,Transmit FIFO Overflow" "0: No transmit FIFO overflow has occurred,1: A transmit FIFO overflow has occurred" bitfld.long 0x0 19. "TFUDF,Transmit FIFO Underflow" "0: No transmit FIFO underflow has occurred,1: A transmit FIFO underflow has occurred" newline bitfld.long 0x0 13. "RFFUL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" rbitfld.long 0x0 12. "RDREQ,Receive Data Transfer Request" "0: The size of valid data space in the receive FIFO..,1: The size of valid data space in the receive FIFO.." newline bitfld.long 0x0 7. "REOF,Frame Reception End" "0: One-frame reception end is not detected,1: One-frame reception end is detected" bitfld.long 0x0 5. "RFSERR,Receive Frame Synchronization Error" "0: No receive frame synchronization error has..,1: A receive frame synchronization error has occurred" newline bitfld.long 0x0 4. "RFUDF,Receive FIFO Underflow" "0: No receive FIFO underflow has occurred,1: A receive FIFO underflow has occurred" bitfld.long 0x0 3. "RFOVF,Receive FIFO Overflow" "0: No receive FIFO overflow has occurred,1: A receive FIFO overflow has occurred" line.long 0x4 "SIIER,SIIER is a 32-bit readable/writable register that enables the issuance of MSIOF interrupts. When each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1. the MSIOF issues an interrupt." bitfld.long 0x4 31. "TDMAE,Transmit Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" bitfld.long 0x4 29. "TFEMPE,Transmit FIFO Empty Enable" "0: Disables interrupts due to transmit FIFO empty,1: Enables interrupts due to transmit FIFO empty" newline bitfld.long 0x4 28. "TDREQE,Transmit Data Transfer Request Enable" "0: Disables interrupts due to transmit data..,1: Enables interrupts due to transmit data transfer.." bitfld.long 0x4 23. "TEOFE,Frame Transmission End Enable" "0: Disables a frame transmission end interrupt,1: Enables a frame transmission end interrupt" newline bitfld.long 0x4 21. "TFSERRE,Transmit Frame Synchronization Error Enable" "0: Disables interrupts due to transmit frame..,1: Enables interrupts due to transmit frame.." bitfld.long 0x4 20. "TFOVFE,Transmit FIFO Overflow Enable" "0: Disables interrupts due to transmit FIFO overflow,1: Enables interrupts due to transmit FIFO overflow" newline bitfld.long 0x4 19. "TFUDFE,Transmit FIFO Underflow Enable" "0: Disables interrupts due to transmit FIFO underflow,1: Enables interrupts due to transmit FIFO underflow" bitfld.long 0x4 15. "RDMAE,Receive Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" newline bitfld.long 0x4 13. "RFFULE,Receive FIFO Full Enable" "0: Disables interrupts due to receive FIFO full,1: Enables interrupts due to receive FIFO full" bitfld.long 0x4 12. "RDREQE,Receive Data Transfer Request Enable" "0: Disables interrupts due to receive data transfer..,1: Enables interrupts due to receive data transfer.." newline bitfld.long 0x4 7. "REOFE,Frame Reception End Enable" "0: Disables a frame reception end interrupt,1: Enables a frame reception end interrupt" bitfld.long 0x4 5. "RFSERRE,Receive Frame Synchronization Error Enable" "0: Disables interrupts due to receive frame..,1: Enables interrupts due to receive frame.." newline bitfld.long 0x4 4. "RFUDFE,Receive FIFO Underflow Enable" "0: Disables interrupts due to receive FIFO underflow,1: Enables interrupts due to receive FIFO underflow" bitfld.long 0x4 3. "RFOVFE,Receive FIFO Overflow Enable" "0: Disables interrupts due to receive FIFO overflow,1: Enables interrupts due to receive FIFO overflow" wgroup.long 0x50++0x3 line.long 0x0 "SITFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD." hexmask.long.word 0x0 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD." rgroup.long 0x60++0x3 line.long 0x0 "SIRFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD." hexmask.long.word 0x0 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD." tree.end tree "MSIOF_2" base ad:0xE6C00000 group.long 0x0++0xB line.long 0x0 "SITMDR1,SITMDR1 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0: Slave mode,1: Master mode" bitfld.long 0x0 30. "PCON,Transfer Signal Connection" "0: Setting prohibited,1: MSIOF_SCK and MSIOF_SYNC are used as common.." newline bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" bitfld.long 0x0 26.--27. "SYNCCH,Synchronization Signal Channel Select" "0: The frame synchronization signal output at..,1: The frame synchronization signal output at..,?,?" newline bitfld.long 0x0 25. "SYNCAC,MSIOF_SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,Frame Synchronization Signal Timing Delay" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" newline bitfld.long 0x0 2.--3. "FLD,Frame Synchronization Signal Interval" "0: 0-clock-cycle delay,1: 1-clock-cycle delay,?,?" bitfld.long 0x0 0. "TXSTP,Transmission Stop" "0: Setting prohibited,1: Stop a frame from starting to transmit until.." line.long 0x4 "SITMDR2,SITMDR2 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Data Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SITMDR3,SITMDR3 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.long 0x10++0xB line.long 0x0 "SIRMDR1,SIRMDR1 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0,1" bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" newline bitfld.long 0x0 25. "SYNCAC,SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,MSIOF_SYNC Timing Delay" "0,1,2,3,4,5,6,7" line.long 0x4 "SIRMDR2,SIRMDR2 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Word Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SIRMDR3,SIRMDR3 is a 32-bit readable/writable register that specifies the MSIOF receive mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.word 0x20++0x1 line.word 0x0 "SITSCR,SITSCR is a 16-bit readable/writable register that specifies the conditions for generating transmit serial clock in master mode. SITSCR can be specified when the TRMD bit in SITMDR1 is set to B'1." bitfld.word 0x0 14.--15. "MSSEL,Master Clock Source Select" "0: Selects module clock as the source of master clock,?,?,?" bitfld.word 0x0 13. "MSIMM,Master Clock Direct Select" "0: Selects the clock output from the baud rate..,1: Setting prohibited" newline hexmask.word.byte 0x0 8.--12. 1. "BRPS,Prescaler Setting" bitfld.word 0x0 0.--2. "BRDV,Baud Rate Generator's Division Ratio" "0: Prescaler output × 1/2,1: Prescaler output × 1/4,?,?,?,?,?,?" group.long 0x28++0x3 line.long 0x0 "SICTR,SICTR is a 32-bit readable/writable register that specifies the MSIOF operating state." bitfld.long 0x0 30.--31. "TSCKIZ,Transmit Clock Input/output Polarity Select in SPI Mode When Transmission is Disabled" "0: Inputs MSIOF_SCK when transmission is disabled,1: Setting prohibited,?,?" bitfld.long 0x0 28.--29. "RSCKIZ,Receive Clock Polarity Select in SPI Mode" "0,1,2,3" newline bitfld.long 0x0 27. "TEDG,Transmit Timing" "0: Outputs transmit data at the rising edge of the..,1: Outputs transmit data at the falling edge of the.." bitfld.long 0x0 26. "REDG,Receive Timing" "0: Samples receive data at the falling edge of the..,1: Samples receive data at the rising edge of the.." newline bitfld.long 0x0 22.--23. "TXDIZ,Pin Output When Transmission is Disabled" "0: Outputs 0,1: Outputs 1,?,?" bitfld.long 0x0 15. "TSCKE,Transmit Serial Clock Output Enable" "0: Does not output MSIOF_SCK,1: Outputs MSIOF_SCK" newline bitfld.long 0x0 14. "TFSE,Transmit Frame Synchronization Signal Output Enable" "0: Does not output MSIOF_SYNC,1: Outputs MSIOF_SYNC" bitfld.long 0x0 13. "RSCKE,Receive Serial Clock Output Enable" "0,1" newline bitfld.long 0x0 12. "RFSE,Receive Frame Synchronization Signal Output Enable" "0,1" bitfld.long 0x0 9. "TXE,Transmit Enable" "0: Does not output MSIOF_TXD,1: Outputs MSIOF_TXD" newline bitfld.long 0x0 8. "RXE,Receive Enable" "0: Data is not received through MSIOF_RXD,1: Data can be received through MSIOF_RXD" bitfld.long 0x0 1. "TXRST,Transmit Reset" "0: Transmit operation reset is completed,1: Transmit operation is being reset" newline bitfld.long 0x0 0. "RXRST,Receive Reset" "0: Receive operation reset is completed,1: Receive operation is being reset" group.long 0x30++0x3 line.long 0x0 "SIFCTR,SIFCTR is a 32-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer." bitfld.long 0x0 29.--31. "TFWM,Transmit FIFO Watermark" "0: Issues a transfer request when 64 stages of the..,1: Issues a transfer request when 32 or more stages..,?,?,?,?,?,?" hexmask.long.byte 0x0 20.--26. 1. "TFUA,Transmit FIFO Usable Area" newline bitfld.long 0x0 13.--15. "RFWM,Receive FIFO Watermark" "0: Issues a transfer request when 1 stage or more..,1: Issues a transfer request when 4 or more stages..,?,?,?,?,?,?" hexmask.long.word 0x0 4.--12. 1. "RFUA,Receive FIFO Usable Area" group.long 0x40++0x7 line.long 0x0 "SISTR,Each bit in SISTR becomes an MSIOF interrupt source when the corresponding bit in SIIER is set to 1." bitfld.long 0x0 29. "TFEMP,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty" rbitfld.long 0x0 28. "TDREQ,Transmit Data Transfer Request" "0: The size of empty space in the transmit FIFO has..,1: The size of empty space in the transmit FIFO has.." newline bitfld.long 0x0 23. "TEOF,Frame Transmission End" "0: One-frame transmission end is not detected,1: One-frame transmission end is detected" bitfld.long 0x0 21. "TFSERR,Transmit Frame Synchronization Error" "0: No transmit frame synchronization error has..,1: A transmit frame synchronization error has.." newline bitfld.long 0x0 20. "TFOVF,Transmit FIFO Overflow" "0: No transmit FIFO overflow has occurred,1: A transmit FIFO overflow has occurred" bitfld.long 0x0 19. "TFUDF,Transmit FIFO Underflow" "0: No transmit FIFO underflow has occurred,1: A transmit FIFO underflow has occurred" newline bitfld.long 0x0 13. "RFFUL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" rbitfld.long 0x0 12. "RDREQ,Receive Data Transfer Request" "0: The size of valid data space in the receive FIFO..,1: The size of valid data space in the receive FIFO.." newline bitfld.long 0x0 7. "REOF,Frame Reception End" "0: One-frame reception end is not detected,1: One-frame reception end is detected" bitfld.long 0x0 5. "RFSERR,Receive Frame Synchronization Error" "0: No receive frame synchronization error has..,1: A receive frame synchronization error has occurred" newline bitfld.long 0x0 4. "RFUDF,Receive FIFO Underflow" "0: No receive FIFO underflow has occurred,1: A receive FIFO underflow has occurred" bitfld.long 0x0 3. "RFOVF,Receive FIFO Overflow" "0: No receive FIFO overflow has occurred,1: A receive FIFO overflow has occurred" line.long 0x4 "SIIER,SIIER is a 32-bit readable/writable register that enables the issuance of MSIOF interrupts. When each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1. the MSIOF issues an interrupt." bitfld.long 0x4 31. "TDMAE,Transmit Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" bitfld.long 0x4 29. "TFEMPE,Transmit FIFO Empty Enable" "0: Disables interrupts due to transmit FIFO empty,1: Enables interrupts due to transmit FIFO empty" newline bitfld.long 0x4 28. "TDREQE,Transmit Data Transfer Request Enable" "0: Disables interrupts due to transmit data..,1: Enables interrupts due to transmit data transfer.." bitfld.long 0x4 23. "TEOFE,Frame Transmission End Enable" "0: Disables a frame transmission end interrupt,1: Enables a frame transmission end interrupt" newline bitfld.long 0x4 21. "TFSERRE,Transmit Frame Synchronization Error Enable" "0: Disables interrupts due to transmit frame..,1: Enables interrupts due to transmit frame.." bitfld.long 0x4 20. "TFOVFE,Transmit FIFO Overflow Enable" "0: Disables interrupts due to transmit FIFO overflow,1: Enables interrupts due to transmit FIFO overflow" newline bitfld.long 0x4 19. "TFUDFE,Transmit FIFO Underflow Enable" "0: Disables interrupts due to transmit FIFO underflow,1: Enables interrupts due to transmit FIFO underflow" bitfld.long 0x4 15. "RDMAE,Receive Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" newline bitfld.long 0x4 13. "RFFULE,Receive FIFO Full Enable" "0: Disables interrupts due to receive FIFO full,1: Enables interrupts due to receive FIFO full" bitfld.long 0x4 12. "RDREQE,Receive Data Transfer Request Enable" "0: Disables interrupts due to receive data transfer..,1: Enables interrupts due to receive data transfer.." newline bitfld.long 0x4 7. "REOFE,Frame Reception End Enable" "0: Disables a frame reception end interrupt,1: Enables a frame reception end interrupt" bitfld.long 0x4 5. "RFSERRE,Receive Frame Synchronization Error Enable" "0: Disables interrupts due to receive frame..,1: Enables interrupts due to receive frame.." newline bitfld.long 0x4 4. "RFUDFE,Receive FIFO Underflow Enable" "0: Disables interrupts due to receive FIFO underflow,1: Enables interrupts due to receive FIFO underflow" bitfld.long 0x4 3. "RFOVFE,Receive FIFO Overflow Enable" "0: Disables interrupts due to receive FIFO overflow,1: Enables interrupts due to receive FIFO overflow" wgroup.long 0x50++0x3 line.long 0x0 "SITFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD." hexmask.long.word 0x0 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD." rgroup.long 0x60++0x3 line.long 0x0 "SIRFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD." hexmask.long.word 0x0 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD." tree.end tree "MSIOF_3" base ad:0xE6C10000 group.long 0x0++0xB line.long 0x0 "SITMDR1,SITMDR1 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0: Slave mode,1: Master mode" bitfld.long 0x0 30. "PCON,Transfer Signal Connection" "0: Setting prohibited,1: MSIOF_SCK and MSIOF_SYNC are used as common.." newline bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" bitfld.long 0x0 26.--27. "SYNCCH,Synchronization Signal Channel Select" "0: The frame synchronization signal output at..,1: The frame synchronization signal output at..,?,?" newline bitfld.long 0x0 25. "SYNCAC,MSIOF_SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,Frame Synchronization Signal Timing Delay" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" newline bitfld.long 0x0 2.--3. "FLD,Frame Synchronization Signal Interval" "0: 0-clock-cycle delay,1: 1-clock-cycle delay,?,?" bitfld.long 0x0 0. "TXSTP,Transmission Stop" "0: Setting prohibited,1: Stop a frame from starting to transmit until.." line.long 0x4 "SITMDR2,SITMDR2 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Data Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SITMDR3,SITMDR3 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.long 0x10++0xB line.long 0x0 "SIRMDR1,SIRMDR1 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0,1" bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" newline bitfld.long 0x0 25. "SYNCAC,SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,MSIOF_SYNC Timing Delay" "0,1,2,3,4,5,6,7" line.long 0x4 "SIRMDR2,SIRMDR2 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Word Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SIRMDR3,SIRMDR3 is a 32-bit readable/writable register that specifies the MSIOF receive mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.word 0x20++0x1 line.word 0x0 "SITSCR,SITSCR is a 16-bit readable/writable register that specifies the conditions for generating transmit serial clock in master mode. SITSCR can be specified when the TRMD bit in SITMDR1 is set to B'1." bitfld.word 0x0 14.--15. "MSSEL,Master Clock Source Select" "0: Selects module clock as the source of master clock,?,?,?" bitfld.word 0x0 13. "MSIMM,Master Clock Direct Select" "0: Selects the clock output from the baud rate..,1: Setting prohibited" newline hexmask.word.byte 0x0 8.--12. 1. "BRPS,Prescaler Setting" bitfld.word 0x0 0.--2. "BRDV,Baud Rate Generator's Division Ratio" "0: Prescaler output × 1/2,1: Prescaler output × 1/4,?,?,?,?,?,?" group.long 0x28++0x3 line.long 0x0 "SICTR,SICTR is a 32-bit readable/writable register that specifies the MSIOF operating state." bitfld.long 0x0 30.--31. "TSCKIZ,Transmit Clock Input/output Polarity Select in SPI Mode When Transmission is Disabled" "0: Inputs MSIOF_SCK when transmission is disabled,1: Setting prohibited,?,?" bitfld.long 0x0 28.--29. "RSCKIZ,Receive Clock Polarity Select in SPI Mode" "0,1,2,3" newline bitfld.long 0x0 27. "TEDG,Transmit Timing" "0: Outputs transmit data at the rising edge of the..,1: Outputs transmit data at the falling edge of the.." bitfld.long 0x0 26. "REDG,Receive Timing" "0: Samples receive data at the falling edge of the..,1: Samples receive data at the rising edge of the.." newline bitfld.long 0x0 22.--23. "TXDIZ,Pin Output When Transmission is Disabled" "0: Outputs 0,1: Outputs 1,?,?" bitfld.long 0x0 15. "TSCKE,Transmit Serial Clock Output Enable" "0: Does not output MSIOF_SCK,1: Outputs MSIOF_SCK" newline bitfld.long 0x0 14. "TFSE,Transmit Frame Synchronization Signal Output Enable" "0: Does not output MSIOF_SYNC,1: Outputs MSIOF_SYNC" bitfld.long 0x0 13. "RSCKE,Receive Serial Clock Output Enable" "0,1" newline bitfld.long 0x0 12. "RFSE,Receive Frame Synchronization Signal Output Enable" "0,1" bitfld.long 0x0 9. "TXE,Transmit Enable" "0: Does not output MSIOF_TXD,1: Outputs MSIOF_TXD" newline bitfld.long 0x0 8. "RXE,Receive Enable" "0: Data is not received through MSIOF_RXD,1: Data can be received through MSIOF_RXD" bitfld.long 0x0 1. "TXRST,Transmit Reset" "0: Transmit operation reset is completed,1: Transmit operation is being reset" newline bitfld.long 0x0 0. "RXRST,Receive Reset" "0: Receive operation reset is completed,1: Receive operation is being reset" group.long 0x30++0x3 line.long 0x0 "SIFCTR,SIFCTR is a 32-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer." bitfld.long 0x0 29.--31. "TFWM,Transmit FIFO Watermark" "0: Issues a transfer request when 64 stages of the..,1: Issues a transfer request when 32 or more stages..,?,?,?,?,?,?" hexmask.long.byte 0x0 20.--26. 1. "TFUA,Transmit FIFO Usable Area" newline bitfld.long 0x0 13.--15. "RFWM,Receive FIFO Watermark" "0: Issues a transfer request when 1 stage or more..,1: Issues a transfer request when 4 or more stages..,?,?,?,?,?,?" hexmask.long.word 0x0 4.--12. 1. "RFUA,Receive FIFO Usable Area" group.long 0x40++0x7 line.long 0x0 "SISTR,Each bit in SISTR becomes an MSIOF interrupt source when the corresponding bit in SIIER is set to 1." bitfld.long 0x0 29. "TFEMP,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty" rbitfld.long 0x0 28. "TDREQ,Transmit Data Transfer Request" "0: The size of empty space in the transmit FIFO has..,1: The size of empty space in the transmit FIFO has.." newline bitfld.long 0x0 23. "TEOF,Frame Transmission End" "0: One-frame transmission end is not detected,1: One-frame transmission end is detected" bitfld.long 0x0 21. "TFSERR,Transmit Frame Synchronization Error" "0: No transmit frame synchronization error has..,1: A transmit frame synchronization error has.." newline bitfld.long 0x0 20. "TFOVF,Transmit FIFO Overflow" "0: No transmit FIFO overflow has occurred,1: A transmit FIFO overflow has occurred" bitfld.long 0x0 19. "TFUDF,Transmit FIFO Underflow" "0: No transmit FIFO underflow has occurred,1: A transmit FIFO underflow has occurred" newline bitfld.long 0x0 13. "RFFUL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" rbitfld.long 0x0 12. "RDREQ,Receive Data Transfer Request" "0: The size of valid data space in the receive FIFO..,1: The size of valid data space in the receive FIFO.." newline bitfld.long 0x0 7. "REOF,Frame Reception End" "0: One-frame reception end is not detected,1: One-frame reception end is detected" bitfld.long 0x0 5. "RFSERR,Receive Frame Synchronization Error" "0: No receive frame synchronization error has..,1: A receive frame synchronization error has occurred" newline bitfld.long 0x0 4. "RFUDF,Receive FIFO Underflow" "0: No receive FIFO underflow has occurred,1: A receive FIFO underflow has occurred" bitfld.long 0x0 3. "RFOVF,Receive FIFO Overflow" "0: No receive FIFO overflow has occurred,1: A receive FIFO overflow has occurred" line.long 0x4 "SIIER,SIIER is a 32-bit readable/writable register that enables the issuance of MSIOF interrupts. When each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1. the MSIOF issues an interrupt." bitfld.long 0x4 31. "TDMAE,Transmit Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" bitfld.long 0x4 29. "TFEMPE,Transmit FIFO Empty Enable" "0: Disables interrupts due to transmit FIFO empty,1: Enables interrupts due to transmit FIFO empty" newline bitfld.long 0x4 28. "TDREQE,Transmit Data Transfer Request Enable" "0: Disables interrupts due to transmit data..,1: Enables interrupts due to transmit data transfer.." bitfld.long 0x4 23. "TEOFE,Frame Transmission End Enable" "0: Disables a frame transmission end interrupt,1: Enables a frame transmission end interrupt" newline bitfld.long 0x4 21. "TFSERRE,Transmit Frame Synchronization Error Enable" "0: Disables interrupts due to transmit frame..,1: Enables interrupts due to transmit frame.." bitfld.long 0x4 20. "TFOVFE,Transmit FIFO Overflow Enable" "0: Disables interrupts due to transmit FIFO overflow,1: Enables interrupts due to transmit FIFO overflow" newline bitfld.long 0x4 19. "TFUDFE,Transmit FIFO Underflow Enable" "0: Disables interrupts due to transmit FIFO underflow,1: Enables interrupts due to transmit FIFO underflow" bitfld.long 0x4 15. "RDMAE,Receive Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" newline bitfld.long 0x4 13. "RFFULE,Receive FIFO Full Enable" "0: Disables interrupts due to receive FIFO full,1: Enables interrupts due to receive FIFO full" bitfld.long 0x4 12. "RDREQE,Receive Data Transfer Request Enable" "0: Disables interrupts due to receive data transfer..,1: Enables interrupts due to receive data transfer.." newline bitfld.long 0x4 7. "REOFE,Frame Reception End Enable" "0: Disables a frame reception end interrupt,1: Enables a frame reception end interrupt" bitfld.long 0x4 5. "RFSERRE,Receive Frame Synchronization Error Enable" "0: Disables interrupts due to receive frame..,1: Enables interrupts due to receive frame.." newline bitfld.long 0x4 4. "RFUDFE,Receive FIFO Underflow Enable" "0: Disables interrupts due to receive FIFO underflow,1: Enables interrupts due to receive FIFO underflow" bitfld.long 0x4 3. "RFOVFE,Receive FIFO Overflow Enable" "0: Disables interrupts due to receive FIFO overflow,1: Enables interrupts due to receive FIFO overflow" wgroup.long 0x50++0x3 line.long 0x0 "SITFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD." hexmask.long.word 0x0 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD." rgroup.long 0x60++0x3 line.long 0x0 "SIRFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD." hexmask.long.word 0x0 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD." tree.end tree "MSIOF_4" base ad:0xE6C20000 group.long 0x0++0xB line.long 0x0 "SITMDR1,SITMDR1 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0: Slave mode,1: Master mode" bitfld.long 0x0 30. "PCON,Transfer Signal Connection" "0: Setting prohibited,1: MSIOF_SCK and MSIOF_SYNC are used as common.." newline bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" bitfld.long 0x0 26.--27. "SYNCCH,Synchronization Signal Channel Select" "0: The frame synchronization signal output at..,1: The frame synchronization signal output at..,?,?" newline bitfld.long 0x0 25. "SYNCAC,MSIOF_SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,Frame Synchronization Signal Timing Delay" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" newline bitfld.long 0x0 2.--3. "FLD,Frame Synchronization Signal Interval" "0: 0-clock-cycle delay,1: 1-clock-cycle delay,?,?" bitfld.long 0x0 0. "TXSTP,Transmission Stop" "0: Setting prohibited,1: Stop a frame from starting to transmit until.." line.long 0x4 "SITMDR2,SITMDR2 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Data Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SITMDR3,SITMDR3 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.long 0x10++0xB line.long 0x0 "SIRMDR1,SIRMDR1 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0,1" bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" newline bitfld.long 0x0 25. "SYNCAC,SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,MSIOF_SYNC Timing Delay" "0,1,2,3,4,5,6,7" line.long 0x4 "SIRMDR2,SIRMDR2 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Word Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SIRMDR3,SIRMDR3 is a 32-bit readable/writable register that specifies the MSIOF receive mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.word 0x20++0x1 line.word 0x0 "SITSCR,SITSCR is a 16-bit readable/writable register that specifies the conditions for generating transmit serial clock in master mode. SITSCR can be specified when the TRMD bit in SITMDR1 is set to B'1." bitfld.word 0x0 14.--15. "MSSEL,Master Clock Source Select" "0: Selects module clock as the source of master clock,?,?,?" bitfld.word 0x0 13. "MSIMM,Master Clock Direct Select" "0: Selects the clock output from the baud rate..,1: Setting prohibited" newline hexmask.word.byte 0x0 8.--12. 1. "BRPS,Prescaler Setting" bitfld.word 0x0 0.--2. "BRDV,Baud Rate Generator's Division Ratio" "0: Prescaler output × 1/2,1: Prescaler output × 1/4,?,?,?,?,?,?" group.long 0x28++0x3 line.long 0x0 "SICTR,SICTR is a 32-bit readable/writable register that specifies the MSIOF operating state." bitfld.long 0x0 30.--31. "TSCKIZ,Transmit Clock Input/output Polarity Select in SPI Mode When Transmission is Disabled" "0: Inputs MSIOF_SCK when transmission is disabled,1: Setting prohibited,?,?" bitfld.long 0x0 28.--29. "RSCKIZ,Receive Clock Polarity Select in SPI Mode" "0,1,2,3" newline bitfld.long 0x0 27. "TEDG,Transmit Timing" "0: Outputs transmit data at the rising edge of the..,1: Outputs transmit data at the falling edge of the.." bitfld.long 0x0 26. "REDG,Receive Timing" "0: Samples receive data at the falling edge of the..,1: Samples receive data at the rising edge of the.." newline bitfld.long 0x0 22.--23. "TXDIZ,Pin Output When Transmission is Disabled" "0: Outputs 0,1: Outputs 1,?,?" bitfld.long 0x0 15. "TSCKE,Transmit Serial Clock Output Enable" "0: Does not output MSIOF_SCK,1: Outputs MSIOF_SCK" newline bitfld.long 0x0 14. "TFSE,Transmit Frame Synchronization Signal Output Enable" "0: Does not output MSIOF_SYNC,1: Outputs MSIOF_SYNC" bitfld.long 0x0 13. "RSCKE,Receive Serial Clock Output Enable" "0,1" newline bitfld.long 0x0 12. "RFSE,Receive Frame Synchronization Signal Output Enable" "0,1" bitfld.long 0x0 9. "TXE,Transmit Enable" "0: Does not output MSIOF_TXD,1: Outputs MSIOF_TXD" newline bitfld.long 0x0 8. "RXE,Receive Enable" "0: Data is not received through MSIOF_RXD,1: Data can be received through MSIOF_RXD" bitfld.long 0x0 1. "TXRST,Transmit Reset" "0: Transmit operation reset is completed,1: Transmit operation is being reset" newline bitfld.long 0x0 0. "RXRST,Receive Reset" "0: Receive operation reset is completed,1: Receive operation is being reset" group.long 0x30++0x3 line.long 0x0 "SIFCTR,SIFCTR is a 32-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer." bitfld.long 0x0 29.--31. "TFWM,Transmit FIFO Watermark" "0: Issues a transfer request when 64 stages of the..,1: Issues a transfer request when 32 or more stages..,?,?,?,?,?,?" hexmask.long.byte 0x0 20.--26. 1. "TFUA,Transmit FIFO Usable Area" newline bitfld.long 0x0 13.--15. "RFWM,Receive FIFO Watermark" "0: Issues a transfer request when 1 stage or more..,1: Issues a transfer request when 4 or more stages..,?,?,?,?,?,?" hexmask.long.word 0x0 4.--12. 1. "RFUA,Receive FIFO Usable Area" group.long 0x40++0x7 line.long 0x0 "SISTR,Each bit in SISTR becomes an MSIOF interrupt source when the corresponding bit in SIIER is set to 1." bitfld.long 0x0 29. "TFEMP,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty" rbitfld.long 0x0 28. "TDREQ,Transmit Data Transfer Request" "0: The size of empty space in the transmit FIFO has..,1: The size of empty space in the transmit FIFO has.." newline bitfld.long 0x0 23. "TEOF,Frame Transmission End" "0: One-frame transmission end is not detected,1: One-frame transmission end is detected" bitfld.long 0x0 21. "TFSERR,Transmit Frame Synchronization Error" "0: No transmit frame synchronization error has..,1: A transmit frame synchronization error has.." newline bitfld.long 0x0 20. "TFOVF,Transmit FIFO Overflow" "0: No transmit FIFO overflow has occurred,1: A transmit FIFO overflow has occurred" bitfld.long 0x0 19. "TFUDF,Transmit FIFO Underflow" "0: No transmit FIFO underflow has occurred,1: A transmit FIFO underflow has occurred" newline bitfld.long 0x0 13. "RFFUL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" rbitfld.long 0x0 12. "RDREQ,Receive Data Transfer Request" "0: The size of valid data space in the receive FIFO..,1: The size of valid data space in the receive FIFO.." newline bitfld.long 0x0 7. "REOF,Frame Reception End" "0: One-frame reception end is not detected,1: One-frame reception end is detected" bitfld.long 0x0 5. "RFSERR,Receive Frame Synchronization Error" "0: No receive frame synchronization error has..,1: A receive frame synchronization error has occurred" newline bitfld.long 0x0 4. "RFUDF,Receive FIFO Underflow" "0: No receive FIFO underflow has occurred,1: A receive FIFO underflow has occurred" bitfld.long 0x0 3. "RFOVF,Receive FIFO Overflow" "0: No receive FIFO overflow has occurred,1: A receive FIFO overflow has occurred" line.long 0x4 "SIIER,SIIER is a 32-bit readable/writable register that enables the issuance of MSIOF interrupts. When each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1. the MSIOF issues an interrupt." bitfld.long 0x4 31. "TDMAE,Transmit Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" bitfld.long 0x4 29. "TFEMPE,Transmit FIFO Empty Enable" "0: Disables interrupts due to transmit FIFO empty,1: Enables interrupts due to transmit FIFO empty" newline bitfld.long 0x4 28. "TDREQE,Transmit Data Transfer Request Enable" "0: Disables interrupts due to transmit data..,1: Enables interrupts due to transmit data transfer.." bitfld.long 0x4 23. "TEOFE,Frame Transmission End Enable" "0: Disables a frame transmission end interrupt,1: Enables a frame transmission end interrupt" newline bitfld.long 0x4 21. "TFSERRE,Transmit Frame Synchronization Error Enable" "0: Disables interrupts due to transmit frame..,1: Enables interrupts due to transmit frame.." bitfld.long 0x4 20. "TFOVFE,Transmit FIFO Overflow Enable" "0: Disables interrupts due to transmit FIFO overflow,1: Enables interrupts due to transmit FIFO overflow" newline bitfld.long 0x4 19. "TFUDFE,Transmit FIFO Underflow Enable" "0: Disables interrupts due to transmit FIFO underflow,1: Enables interrupts due to transmit FIFO underflow" bitfld.long 0x4 15. "RDMAE,Receive Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" newline bitfld.long 0x4 13. "RFFULE,Receive FIFO Full Enable" "0: Disables interrupts due to receive FIFO full,1: Enables interrupts due to receive FIFO full" bitfld.long 0x4 12. "RDREQE,Receive Data Transfer Request Enable" "0: Disables interrupts due to receive data transfer..,1: Enables interrupts due to receive data transfer.." newline bitfld.long 0x4 7. "REOFE,Frame Reception End Enable" "0: Disables a frame reception end interrupt,1: Enables a frame reception end interrupt" bitfld.long 0x4 5. "RFSERRE,Receive Frame Synchronization Error Enable" "0: Disables interrupts due to receive frame..,1: Enables interrupts due to receive frame.." newline bitfld.long 0x4 4. "RFUDFE,Receive FIFO Underflow Enable" "0: Disables interrupts due to receive FIFO underflow,1: Enables interrupts due to receive FIFO underflow" bitfld.long 0x4 3. "RFOVFE,Receive FIFO Overflow Enable" "0: Disables interrupts due to receive FIFO overflow,1: Enables interrupts due to receive FIFO overflow" wgroup.long 0x50++0x3 line.long 0x0 "SITFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD." hexmask.long.word 0x0 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD." rgroup.long 0x60++0x3 line.long 0x0 "SIRFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD." hexmask.long.word 0x0 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD." tree.end tree "MSIOF_5" base ad:0xE6C28000 group.long 0x0++0xB line.long 0x0 "SITMDR1,SITMDR1 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0: Slave mode,1: Master mode" bitfld.long 0x0 30. "PCON,Transfer Signal Connection" "0: Setting prohibited,1: MSIOF_SCK and MSIOF_SYNC are used as common.." newline bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" bitfld.long 0x0 26.--27. "SYNCCH,Synchronization Signal Channel Select" "0: The frame synchronization signal output at..,1: The frame synchronization signal output at..,?,?" newline bitfld.long 0x0 25. "SYNCAC,MSIOF_SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,Frame Synchronization Signal Timing Delay" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" newline bitfld.long 0x0 2.--3. "FLD,Frame Synchronization Signal Interval" "0: 0-clock-cycle delay,1: 1-clock-cycle delay,?,?" bitfld.long 0x0 0. "TXSTP,Transmission Stop" "0: Setting prohibited,1: Stop a frame from starting to transmit until.." line.long 0x4 "SITMDR2,SITMDR2 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Data Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SITMDR3,SITMDR3 is a 32-bit readable/writable register that specifies the MSIOF transmit mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.long 0x10++0xB line.long 0x0 "SIRMDR1,SIRMDR1 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x0 31. "TRMD,Transfer Mode" "0,1" bitfld.long 0x0 28.--29. "SYNCMD,SYNC Mode" "0: Frame start synchronization pulse,1: Reserved,?,?" newline bitfld.long 0x0 25. "SYNCAC,SYNC Polarity" "0: Active-high signal in synchronization pulse or..,1: Active-low signal in synchronization pulse or.." bitfld.long 0x0 24. "BITLSB,MSB/LSB First" "0: MSB first,1: LSB first" newline bitfld.long 0x0 20.--22. "DTDL,Data Pin Bit Delay for MSIOF_SYNC Pin" "0: No bit delay,1: 1-clock-cycle delay,?,?,?,?,?,?" bitfld.long 0x0 16.--18. "SYNCDL,MSIOF_SYNC Timing Delay" "0,1,2,3,4,5,6,7" line.long 0x4 "SIRMDR2,SIRMDR2 is a 32-bit readable/writable register that specifies the MSIOF receive mode." bitfld.long 0x4 30. "GRP,Group Count" "0: Group count 1,1: Group count 2" hexmask.long.byte 0x4 24.--28. 1. "BITLEN1,Word Size (8 to 32 bits)" newline hexmask.long.byte 0x4 16.--21. 1. "WDLEN1,Word Count (1 to 64 words)" line.long 0x8 "SIRMDR3,SIRMDR3 is a 32-bit readable/writable register that specifies the MSIOF receive mode." hexmask.long.byte 0x8 24.--28. 1. "BITLEN2,Word Size (8 to 32 bits)" hexmask.long.byte 0x8 16.--21. 1. "WDLEN2,Word Count (1 to 64 words)" group.word 0x20++0x1 line.word 0x0 "SITSCR,SITSCR is a 16-bit readable/writable register that specifies the conditions for generating transmit serial clock in master mode. SITSCR can be specified when the TRMD bit in SITMDR1 is set to B'1." bitfld.word 0x0 14.--15. "MSSEL,Master Clock Source Select" "0: Selects module clock as the source of master clock,?,?,?" bitfld.word 0x0 13. "MSIMM,Master Clock Direct Select" "0: Selects the clock output from the baud rate..,1: Setting prohibited" newline hexmask.word.byte 0x0 8.--12. 1. "BRPS,Prescaler Setting" bitfld.word 0x0 0.--2. "BRDV,Baud Rate Generator's Division Ratio" "0: Prescaler output × 1/2,1: Prescaler output × 1/4,?,?,?,?,?,?" group.long 0x28++0x3 line.long 0x0 "SICTR,SICTR is a 32-bit readable/writable register that specifies the MSIOF operating state." bitfld.long 0x0 30.--31. "TSCKIZ,Transmit Clock Input/output Polarity Select in SPI Mode When Transmission is Disabled" "0: Inputs MSIOF_SCK when transmission is disabled,1: Setting prohibited,?,?" bitfld.long 0x0 28.--29. "RSCKIZ,Receive Clock Polarity Select in SPI Mode" "0,1,2,3" newline bitfld.long 0x0 27. "TEDG,Transmit Timing" "0: Outputs transmit data at the rising edge of the..,1: Outputs transmit data at the falling edge of the.." bitfld.long 0x0 26. "REDG,Receive Timing" "0: Samples receive data at the falling edge of the..,1: Samples receive data at the rising edge of the.." newline bitfld.long 0x0 22.--23. "TXDIZ,Pin Output When Transmission is Disabled" "0: Outputs 0,1: Outputs 1,?,?" bitfld.long 0x0 15. "TSCKE,Transmit Serial Clock Output Enable" "0: Does not output MSIOF_SCK,1: Outputs MSIOF_SCK" newline bitfld.long 0x0 14. "TFSE,Transmit Frame Synchronization Signal Output Enable" "0: Does not output MSIOF_SYNC,1: Outputs MSIOF_SYNC" bitfld.long 0x0 13. "RSCKE,Receive Serial Clock Output Enable" "0,1" newline bitfld.long 0x0 12. "RFSE,Receive Frame Synchronization Signal Output Enable" "0,1" bitfld.long 0x0 9. "TXE,Transmit Enable" "0: Does not output MSIOF_TXD,1: Outputs MSIOF_TXD" newline bitfld.long 0x0 8. "RXE,Receive Enable" "0: Data is not received through MSIOF_RXD,1: Data can be received through MSIOF_RXD" bitfld.long 0x0 1. "TXRST,Transmit Reset" "0: Transmit operation reset is completed,1: Transmit operation is being reset" newline bitfld.long 0x0 0. "RXRST,Receive Reset" "0: Receive operation reset is completed,1: Receive operation is being reset" group.long 0x30++0x3 line.long 0x0 "SIFCTR,SIFCTR is a 32-bit readable/writable register that indicates the area available for the transmit/receive FIFO transfer." bitfld.long 0x0 29.--31. "TFWM,Transmit FIFO Watermark" "0: Issues a transfer request when 64 stages of the..,1: Issues a transfer request when 32 or more stages..,?,?,?,?,?,?" hexmask.long.byte 0x0 20.--26. 1. "TFUA,Transmit FIFO Usable Area" newline bitfld.long 0x0 13.--15. "RFWM,Receive FIFO Watermark" "0: Issues a transfer request when 1 stage or more..,1: Issues a transfer request when 4 or more stages..,?,?,?,?,?,?" hexmask.long.word 0x0 4.--12. 1. "RFUA,Receive FIFO Usable Area" group.long 0x40++0x7 line.long 0x0 "SISTR,Each bit in SISTR becomes an MSIOF interrupt source when the corresponding bit in SIIER is set to 1." bitfld.long 0x0 29. "TFEMP,Transmit FIFO Empty" "0: Transmit FIFO is not empty,1: Transmit FIFO is empty" rbitfld.long 0x0 28. "TDREQ,Transmit Data Transfer Request" "0: The size of empty space in the transmit FIFO has..,1: The size of empty space in the transmit FIFO has.." newline bitfld.long 0x0 23. "TEOF,Frame Transmission End" "0: One-frame transmission end is not detected,1: One-frame transmission end is detected" bitfld.long 0x0 21. "TFSERR,Transmit Frame Synchronization Error" "0: No transmit frame synchronization error has..,1: A transmit frame synchronization error has.." newline bitfld.long 0x0 20. "TFOVF,Transmit FIFO Overflow" "0: No transmit FIFO overflow has occurred,1: A transmit FIFO overflow has occurred" bitfld.long 0x0 19. "TFUDF,Transmit FIFO Underflow" "0: No transmit FIFO underflow has occurred,1: A transmit FIFO underflow has occurred" newline bitfld.long 0x0 13. "RFFUL,Receive FIFO Full" "0: Receive FIFO is not full,1: Receive FIFO is full" rbitfld.long 0x0 12. "RDREQ,Receive Data Transfer Request" "0: The size of valid data space in the receive FIFO..,1: The size of valid data space in the receive FIFO.." newline bitfld.long 0x0 7. "REOF,Frame Reception End" "0: One-frame reception end is not detected,1: One-frame reception end is detected" bitfld.long 0x0 5. "RFSERR,Receive Frame Synchronization Error" "0: No receive frame synchronization error has..,1: A receive frame synchronization error has occurred" newline bitfld.long 0x0 4. "RFUDF,Receive FIFO Underflow" "0: No receive FIFO underflow has occurred,1: A receive FIFO underflow has occurred" bitfld.long 0x0 3. "RFOVF,Receive FIFO Overflow" "0: No receive FIFO overflow has occurred,1: A receive FIFO overflow has occurred" line.long 0x4 "SIIER,SIIER is a 32-bit readable/writable register that enables the issuance of MSIOF interrupts. When each bit in this register is set to 1 and the corresponding bit in SISTR is set to 1. the MSIOF issues an interrupt." bitfld.long 0x4 31. "TDMAE,Transmit Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" bitfld.long 0x4 29. "TFEMPE,Transmit FIFO Empty Enable" "0: Disables interrupts due to transmit FIFO empty,1: Enables interrupts due to transmit FIFO empty" newline bitfld.long 0x4 28. "TDREQE,Transmit Data Transfer Request Enable" "0: Disables interrupts due to transmit data..,1: Enables interrupts due to transmit data transfer.." bitfld.long 0x4 23. "TEOFE,Frame Transmission End Enable" "0: Disables a frame transmission end interrupt,1: Enables a frame transmission end interrupt" newline bitfld.long 0x4 21. "TFSERRE,Transmit Frame Synchronization Error Enable" "0: Disables interrupts due to transmit frame..,1: Enables interrupts due to transmit frame.." bitfld.long 0x4 20. "TFOVFE,Transmit FIFO Overflow Enable" "0: Disables interrupts due to transmit FIFO overflow,1: Enables interrupts due to transmit FIFO overflow" newline bitfld.long 0x4 19. "TFUDFE,Transmit FIFO Underflow Enable" "0: Disables interrupts due to transmit FIFO underflow,1: Enables interrupts due to transmit FIFO underflow" bitfld.long 0x4 15. "RDMAE,Receive Data DMA Transfer Request Enable" "0: Sends an interrupt request to the CPU,1: Sends a DMA transfer request to the DMAC" newline bitfld.long 0x4 13. "RFFULE,Receive FIFO Full Enable" "0: Disables interrupts due to receive FIFO full,1: Enables interrupts due to receive FIFO full" bitfld.long 0x4 12. "RDREQE,Receive Data Transfer Request Enable" "0: Disables interrupts due to receive data transfer..,1: Enables interrupts due to receive data transfer.." newline bitfld.long 0x4 7. "REOFE,Frame Reception End Enable" "0: Disables a frame reception end interrupt,1: Enables a frame reception end interrupt" bitfld.long 0x4 5. "RFSERRE,Receive Frame Synchronization Error Enable" "0: Disables interrupts due to receive frame..,1: Enables interrupts due to receive frame.." newline bitfld.long 0x4 4. "RFUDFE,Receive FIFO Underflow Enable" "0: Disables interrupts due to receive FIFO underflow,1: Enables interrupts due to receive FIFO underflow" bitfld.long 0x4 3. "RFOVFE,Receive FIFO Overflow Enable" "0: Disables interrupts due to receive FIFO overflow,1: Enables interrupts due to receive FIFO overflow" wgroup.long 0x50++0x3 line.long 0x0 "SITFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SITFD1,These bits specify the upper 16 bits of the FIFO data to be output through MSIOF_TXD." hexmask.long.word 0x0 0.--15. 1. "SITFD2,These bits specify the lower 16 bits of the FIFO data to be output through MSIOF_TXD." rgroup.long 0x60++0x3 line.long 0x0 "SIRFDR,[R-Car H3. R-Car M3-W. R-Car V3M. R-Car D3. R-Car M3-N and R-Car E3]" hexmask.long.word 0x0 16.--31. 1. "SIRFD1,Store the upper 16 bits of the FIFO data received through MSIOF_RXD." hexmask.long.word 0x0 0.--15. 1. "SIRFD2,Store the lower 16 bits of the FIFO data received through MSIOF_RXD." tree.end tree.end tree "MSTPCR" base ad:0xE6150000 group.long 0x0++0x3B line.long 0x0 "MSTPCR0,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x0 31. "ocv3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 30. "ocv2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 29. "ocv1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 28. "ocv0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 27. "imppsc0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 26. "impdma0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 25. "imp1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 24. "imp0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 23. "spmc0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 22. "impcnn0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 21. "radsp1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 20. "radsp0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 19. "isp3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 18. "isp2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 17. "isp1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 16. "isp0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 14. "cle3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 13. "cle2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 12. "cle1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 11. "cle0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 10. "umfl1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 9. "umfl0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 2. "disp1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x0 1. "disp0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x0 0. "rgx,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x4 "MSTPCR1,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x4 22. "adg,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x4 21. "spmi1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x4 20. "spmi0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x4 19. "ipmmuir,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x4 18. "impslv,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x4 17. "impldmam,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x4 16. "impdta,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x4 9. "spmc1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x4 8. "impcnn1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x4 7. "ocv5,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x4 6. "imppsc1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x4 5. "impdma1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x4 4. "imp3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x4 3. "imp2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x4 2. "spmc2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x4 1. "impcnn2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x4 0. "ocv4,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x8 "MSTPCR2,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x8 16. "avb5,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x8 15. "avb4,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x8 14. "avb3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x8 13. "avb2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x8 12. "avb1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x8 11. "avb0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0xC "MSTPCR3,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0xC 31. "csi4lnk0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0xC 29. "cr0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0xC 28. "canfd,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0xC 14. "ocv7,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0xC 13. "ocv6,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x10 "MSTPCR4,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x10 15. "dsitxlink0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x10 14. "doc2ch,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x10 13. "ipmmuvi1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x10 12. "ipmmuvi0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x10 11. "dis0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x10 6. "dbs1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x10 5. "dbs0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x10 4. "dbprend,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x10 3. "dbplend,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x10 2. "csi4lnk3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x10 1. "csi4lnk2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x10 0. "csi4lnk1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x14 "MSTPCR5,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x14 31. "intap,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 30. "ims1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x14 29. "ims0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 28. "imr3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x14 27. "imr2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 26. "imr1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x14 25. "imr0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 24. "i2c6,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x14 23. "i2c5,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 22. "i2c4,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x14 21. "i2c3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 20. "i2c2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x14 19. "i2c1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 18. "i2c0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x14 17. "hscif3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 16. "hscif2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x14 15. "hscif1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 14. "hscif0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x14 13. "fray,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 9. "fcpvd1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x14 8. "fcpvd0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x14 7. "fcpcs,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x18 "MSTPCR6,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x18 31. "rtdm1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 30. "rtdm0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 29. "rpc,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 28. "pwm0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 26.--27. "pci23,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the..,?,?" bitfld.long 0x18 24.--25. "pci01,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the..,?,?" newline bitfld.long 0x18 23. "msi5,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 22. "msi4,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 21. "msi3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 20. "msi2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 19. "msi1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 18. "msi0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 17. "mfi,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 16. "iv1es,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline hexmask.long.byte 0x18 12.--15. 1. "ispcs,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." bitfld.long 0x18 11. "irqc,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 10. "ipmmuvip1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 9. "ipmmuvip0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 8. "inttp,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 7. "ipmmuvc,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 6. "ipmmurt1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 5. "ipmmurt0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 4. "ipmmupv0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 3. "ipmmumm,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 2. "ipmmuds1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x18 1. "ipmmuds0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x18 0. "ipc,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x1C "MSTPCR7,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x1C 31. "vin01,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 30. "vin00,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 29. "vcp4l,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 20. "tsiplt,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 19. "tsip,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 18. "tpu0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 17. "tmu4,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 16. "tmu3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 15. "tmu2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 14. "tmu1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 13. "tmu0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 12. "bkbuf,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 11. "sysram0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3.." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 10. "sydm2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 9. "sydm1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 8. "stat,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 7. "secrom,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 6. "sdhi0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 5. "scif4,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 4. "scif3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 3. "scif1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 2. "scif0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x1C 1. "rtdm3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x1C 0. "rtdm2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x20 "MSTPCR8,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x20 31. "vspd1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 30. "vspd0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 29. "vin37,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 28. "vin36,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 27. "vin35,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 26. "vin34,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 25. "vin33,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 24. "vin32,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 23. "vin31,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 22. "vin30,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 21. "vin27,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 20. "vin26,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 19. "vin25,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 18. "vin24,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 17. "vin23,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 16. "vin22,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 15. "vin21,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 14. "vin20,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 13. "vin17,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 12. "vin16,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 11. "vin15,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 10. "vin14,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 9. "vin13,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 8. "vin12,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 7. "vin11,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 6. "vin10,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 5. "vin07,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 4. "vin06,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 3. "vin05,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 2. "vin04,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x20 1. "vin03,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x20 0. "vin02,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x24 "MSTPCR9,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x24 20. "ucmt,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x24 19. "tsc,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x24 18. "pfc3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x24 17. "pfc2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x24 16. "pfc1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x24 15. "pfc0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x24 14. "ecmtop,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x24 13. "cmt3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x24 12. "cmt2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x24 11. "cmt1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x24 10. "cmt0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x24 8.--9. "aps0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the..,?,?" newline bitfld.long 0x24 7. "wdt,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x24 6. "wcrc3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x24 5. "wcrc2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x24 4. "wcrc1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x24 3. "wcrc0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x28 "MSTPCR10,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x28 31. "vspx3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x28 30. "vspx2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x28 29. "vspx1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x28 28. "vspx0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x28 27. "radsp1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x28 25. "radsp0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x2C "MSTPCR11,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x2C 17. "fbc,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x2C 3. "fcpvx3,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x2C 2. "fcpvx2,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." bitfld.long 0x2C 1. "fcpvx1,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." newline bitfld.long 0x2C 0. "fcpvx0,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x30 "MSTPCR12,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x30 30. "fso,MSTPCRn is 32-bit readable/writable registers which control supply of the clock signal to the modules assigned to the corresponding bits. Only by setting MSTPCRn module stop signals can be controlled which is different from previous Gen3 series." "0: Enables supply of the clock signal to the..,1: Stops supply of the clock signal to the.." line.long 0x34 "MSTPCR13,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." line.long 0x38 "MSTPCR14,Module Stop Control Register (MSTPCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." tree.end tree "MSTPSR" base ad:0xE6150000 rgroup.long 0x0++0x3 line.long 0x0 "MSTPSR0,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x0 31. "ocv3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 30. "ocv2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 29. "ocv1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 28. "ocv0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 27. "imppsc0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 26. "impdma0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 25. "imp1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 24. "imp0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 23. "spmc0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 22. "impcnn0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 21. "radsp1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 20. "radsp0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 19. "isp3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 18. "isp2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 17. "isp1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 16. "isp0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 14. "cle3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 13. "cle2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 12. "cle1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 11. "cle0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 10. "umfl1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 9. "umfl0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 2. "disp1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 1. "disp0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 0. "rgx,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." group.long 0x4++0x3 line.long 0x0 "MSTPSR1,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x0 22. "adg,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 21. "spmi1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 20. "spmi0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 19. "ipmmuir,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 18. "impslv,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 17. "impldmam,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 16. "impdta,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 9. "spmc1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 8. "impcnn1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 7. "ocv5,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 6. "imppsc1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 5. "impdma1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 4. "imp3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 3. "imp2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 2. "spmc2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 1. "impcnn2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 0. "ocv4,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." rgroup.long 0x8++0x2B line.long 0x0 "MSTPSR2,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x0 16. "avb5,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 15. "avb4,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 14. "avb3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 13. "avb2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x0 12. "avb1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x0 11. "avb0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." line.long 0x4 "MSTPSR3,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x4 31. "csi4lnk0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x4 29. "cr0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x4 28. "canfd,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x4 14. "ocv7,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x4 13. "ocv6,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." line.long 0x8 "MSTPSR4,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x8 15. "dsitxlink0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x8 14. "doc2ch,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x8 13. "ipmmuvi1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x8 12. "ipmmuvi0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x8 11. "dis0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x8 6. "dbs1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x8 5. "dbs0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x8 4. "dbprend,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x8 3. "dbplend,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x8 2. "csi4lnk3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x8 1. "csi4lnk2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x8 0. "csi4lnk1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." line.long 0xC "MSTPSR5,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0xC 31. "intap,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 30. "ims1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0xC 29. "ims0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 28. "imr3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0xC 27. "imr2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 26. "imr1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0xC 25. "imr0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 24. "i2c6,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0xC 23. "i2c5,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 22. "i2c4,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0xC 21. "i2c3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 20. "i2c2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0xC 19. "i2c1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 18. "i2c0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0xC 17. "hscif3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 16. "hscif2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0xC 15. "hscif1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 14. "hscif0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0xC 13. "fray,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 9. "fcpvd1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0xC 8. "fcpvd0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0xC 7. "fcpcs,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." line.long 0x10 "MSTPSR6,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x10 31. "rtdm1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 30. "rtdm0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 29. "rpc,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 28. "pwm0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 26.--27. "pci23,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding..,?,?" bitfld.long 0x10 24.--25. "pci01,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding..,?,?" newline bitfld.long 0x10 23. "msi5,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 22. "msi4,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 21. "msi3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 20. "msi2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 19. "msi1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 18. "msi0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 17. "mfi,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 16. "iv1es,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline hexmask.long.byte 0x10 12.--15. 1. "ispcs,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." bitfld.long 0x10 11. "irqc,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 10. "ipmmuvip1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 9. "ipmmuvip0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 8. "inttp,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 7. "ipmmuvc,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 6. "ipmmurt1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 5. "ipmmurt0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 4. "ipmmupv0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 3. "ipmmumm,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 2. "ipmmuds1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x10 1. "ipmmuds0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x10 0. "ipc,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." line.long 0x14 "MSTPSR7,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x14 31. "vin01,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 30. "vin00,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 29. "vcp4l,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 20. "tsiplt,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 19. "tsip,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 18. "tpu0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 17. "tmu4,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 16. "tmu3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 15. "tmu2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 14. "tmu1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 13. "tmu0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 12. "bkbuf,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 11. "sysram0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 10. "sydm2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 9. "sydm1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 8. "stat,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 7. "secrom,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 6. "sdhi0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 5. "scif4,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 4. "scif3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 3. "scif1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 2. "scif0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x14 1. "rtdm3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x14 0. "rtdm2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." line.long 0x18 "MSTPSR8,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x18 31. "vspd1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 30. "vspd0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 29. "vin37,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 28. "vin36,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 27. "vin35,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 26. "vin34,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 25. "vin33,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 24. "vin32,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 23. "vin31,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 22. "vin30,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 21. "vin27,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 20. "vin26,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 19. "vin25,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 18. "vin24,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 17. "vin23,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 16. "vin22,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 15. "vin21,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 14. "vin20,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 13. "vin17,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 12. "vin16,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 11. "vin15,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 10. "vin14,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 9. "vin13,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 8. "vin12,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 7. "vin11,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 6. "vin10,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 5. "vin07,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 4. "vin06,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 3. "vin05,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 2. "vin04,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x18 1. "vin03,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x18 0. "vin02,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." line.long 0x1C "MSTPSR9,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x1C 20. "ucmt,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x1C 19. "tsc,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x1C 18. "pfc3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x1C 17. "pfc2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x1C 16. "pfc1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x1C 15. "pfc0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x1C 14. "ecmtop,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x1C 13. "cmt3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x1C 12. "cmt2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x1C 11. "cmt1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x1C 10. "cmt0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x1C 8.--9. "aps0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding..,?,?" newline bitfld.long 0x1C 7. "wdt,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x1C 6. "wcrc3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x1C 5. "wcrc2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x1C 4. "wcrc1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x1C 3. "wcrc0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." line.long 0x20 "MSTPSR10,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x20 31. "vspx3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x20 30. "vspx2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x20 29. "vspx1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x20 28. "vspx0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x20 27. "radsp1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x20 25. "radsp0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." line.long 0x24 "MSTPSR11,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x24 17. "fbc,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x24 3. "fcpvx3,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x24 2. "fcpvx2,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." bitfld.long 0x24 1. "fcpvx1,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." newline bitfld.long 0x24 0. "fcpvx0,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." line.long 0x28 "MSTPSR12,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x28 30. "fso,MSTPSRn is a 32-bit readable register that indicates whether the on-chip modules are in the module standby state. Setting a bit in this register to 1 stops supply of the clock signal to the corresponding module and the setting a bit to 0 enables.." "0: Supply of the clock signal to the corresponding..,1: Supply of the clock signal to the corresponding.." group.long 0x34++0x7 line.long 0x0 "MSTPSR13,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." line.long 0x4 "MSTPSR14,Module Stop Status Register (MSTPSRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." tree.end tree "PFC" base ad:0x0 tree "PFC_0" base ad:0xE6050000 group.long 0x0++0x3 line.long 0x0 "PMMR_B0P1T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x200++0x3 line.long 0x0 "PMMR_B0P1T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x400++0x3 line.long 0x0 "PMMR_B0P1T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x800++0x3 line.long 0x0 "PMMR_B0P2T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xA00++0x3 line.long 0x0 "PMMR_B0P2T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xC00++0x3 line.long 0x0 "PMMR_B0P2T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2000++0x3 line.long 0x0 "PMMR_B1P1T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2200++0x3 line.long 0x0 "PMMR_B1P1T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2400++0x3 line.long 0x0 "PMMR_B1P1T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2800++0x3 line.long 0x0 "PMMR_B1P2T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2A00++0x3 line.long 0x0 "PMMR_B1P2T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2C00++0x3 line.long 0x0 "PMMR_B1P2T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4000++0x3 line.long 0x0 "PMMR_B2P1T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4200++0x3 line.long 0x0 "PMMR_B2P1T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4400++0x3 line.long 0x0 "PMMR_B2P1T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4800++0x3 line.long 0x0 "PMMR_B2P2T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4A00++0x3 line.long 0x0 "PMMR_B2P2T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4C00++0x3 line.long 0x0 "PMMR_B2P2T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6000++0x3 line.long 0x0 "PMMR_B3P1T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6200++0x3 line.long 0x0 "PMMR_B3P1T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6400++0x3 line.long 0x0 "PMMR_B3P1T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6800++0x3 line.long 0x0 "PMMR_B3P2T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6A00++0x3 line.long 0x0 "PMMR_B3P2T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6C00++0x3 line.long 0x0 "PMMR_B3P2T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x40++0x3 line.long 0x0 "GPSR_B0P1T0,GPIO/Peripheral Function Select Register B0P1T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x240++0x3 line.long 0x0 "GPSR_B0P1T1,GPIO/Peripheral Function Select Register B0P1T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x440++0x3 line.long 0x0 "GPSR_B0P1T2,GPIO/Peripheral Function Select Register B0P1T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2040++0x3 line.long 0x0 "GPSR_B1P1T0,GPIO/Peripheral Function Select Register B1P1T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2240++0x3 line.long 0x0 "GPSR_B1P1T1,GPIO/Peripheral Function Select Register B1P1T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2440++0x3 line.long 0x0 "GPSR_B1P1T2,GPIO/Peripheral Function Select Register B1P1T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4040++0x3 line.long 0x0 "GPSR_B2P1T0,GPIO/Peripheral Function Select Register B2P1T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4240++0x3 line.long 0x0 "GPSR_B2P1T1,GPIO/Peripheral Function Select Register B2P1T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4440++0x3 line.long 0x0 "GPSR_B2P1T2,GPIO/Peripheral Function Select Register B2P1T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6040++0x3 line.long 0x0 "GPSR_B3P1T0,GPIO/Peripheral Function Select Register B3P1T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6240++0x3 line.long 0x0 "GPSR_B3P1T1,GPIO/Peripheral Function Select Register B3P1T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6440++0x3 line.long 0x0 "GPSR_B3P1T2,GPIO/Peripheral Function Select Register B3P1T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x60++0x3 line.long 0x0 "IP0SR_B0P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x260++0x3 line.long 0x0 "IP0SR_B0P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x460++0x3 line.long 0x0 "IP0SR_B0P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2060++0x3 line.long 0x0 "IP0SR_B1P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2260++0x3 line.long 0x0 "IP0SR_B1P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2460++0x3 line.long 0x0 "IP0SR_B1P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4060++0x3 line.long 0x0 "IP0SR_B2P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4260++0x3 line.long 0x0 "IP0SR_B2P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4460++0x3 line.long 0x0 "IP0SR_B2P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6060++0x3 line.long 0x0 "IP0SR_B3P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6260++0x3 line.long 0x0 "IP0SR_B3P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6460++0x3 line.long 0x0 "IP0SR_B3P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x64++0x3 line.long 0x0 "IP1SR_B0P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x264++0x3 line.long 0x0 "IP1SR_B0P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x464++0x3 line.long 0x0 "IP1SR_B0P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2064++0x3 line.long 0x0 "IP1SR_B1P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2264++0x3 line.long 0x0 "IP1SR_B1P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2464++0x3 line.long 0x0 "IP1SR_B1P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4064++0x3 line.long 0x0 "IP1SR_B2P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4264++0x3 line.long 0x0 "IP1SR_B2P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4464++0x3 line.long 0x0 "IP1SR_B2P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6064++0x3 line.long 0x0 "IP1SR_B3P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6264++0x3 line.long 0x0 "IP1SR_B3P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6464++0x3 line.long 0x0 "IP1SR_B3P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x68++0x3 line.long 0x0 "IP2SR_B0P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x268++0x3 line.long 0x0 "IP2SR_B0P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x468++0x3 line.long 0x0 "IP2SR_B0P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2068++0x3 line.long 0x0 "IP2SR_B1P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2268++0x3 line.long 0x0 "IP2SR_B1P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2468++0x3 line.long 0x0 "IP2SR_B1P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4068++0x3 line.long 0x0 "IP2SR_B2P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4268++0x3 line.long 0x0 "IP2SR_B2P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4468++0x3 line.long 0x0 "IP2SR_B2P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6068++0x3 line.long 0x0 "IP2SR_B3P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6268++0x3 line.long 0x0 "IP2SR_B3P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6468++0x3 line.long 0x0 "IP2SR_B3P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x80++0x3 line.long 0x0 "DRV0CTRL_B0P1T0,DRV Control Register0 B0P1T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x280++0x3 line.long 0x0 "DRV0CTRL_B0P1T1,DRV Control Register0 B0P1T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x480++0x3 line.long 0x0 "DRV0CTRL_B0P1T2,DRV Control Register0 B0P1T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2080++0x3 line.long 0x0 "DRV0CTRL_B1P1T0,DRV Control Register0 B1P1T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2280++0x3 line.long 0x0 "DRV0CTRL_B1P1T1,DRV Control Register0 B1P1T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2480++0x3 line.long 0x0 "DRV0CTRL_B1P1T2,DRV Control Register0 B1P1T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4080++0x3 line.long 0x0 "DRV0CTRL_B2P1T0,DRV Control Register0 B2P1T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4280++0x3 line.long 0x0 "DRV0CTRL_B2P1T1,DRV Control Register0 B2P1T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4480++0x3 line.long 0x0 "DRV0CTRL_B2P1T2,DRV Control Register0 B2P1T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6080++0x3 line.long 0x0 "DRV0CTRL_B3P1T0,DRV Control Register0 B3P1T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6280++0x3 line.long 0x0 "DRV0CTRL_B3P1T1,DRV Control Register0 B3P1T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6480++0x3 line.long 0x0 "DRV0CTRL_B3P1T2,DRV Control Register0 B3P1T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0xA0++0x3 line.long 0x0 "POC_B0P1T0,POC Control Register B0P1T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x2A0++0x3 line.long 0x0 "POC_B0P1T1,POC Control Register B0P1T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x4A0++0x3 line.long 0x0 "POC_B0P1T2,POC Control Register B0P1T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x20A0++0x3 line.long 0x0 "POC_B1P1T0,POC Control Register B1P1T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x22A0++0x3 line.long 0x0 "POC_B1P1T1,POC Control Register B1P1T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x24A0++0x3 line.long 0x0 "POC_B1P1T2,POC Control Register B1P1T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x40A0++0x3 line.long 0x0 "POC_B2P1T0,POC Control Register B2P1T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x42A0++0x3 line.long 0x0 "POC_B2P1T1,POC Control Register B2P1T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x44A0++0x3 line.long 0x0 "POC_B2P1T2,POC Control Register B2P1T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x60A0++0x3 line.long 0x0 "POC_B3P1T0,POC Control Register B3P1T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x62A0++0x3 line.long 0x0 "POC_B3P1T1,POC Control Register B3P1T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x64A0++0x3 line.long 0x0 "POC_B3P1T2,POC Control Register B3P1T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0xC0++0x3 line.long 0x0 "PUEN_B0P1T0,LSI Pin Pull-enable Register B0P1T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x2C0++0x3 line.long 0x0 "PUEN_B0P1T1,LSI Pin Pull-enable Register B0P1T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x4C0++0x3 line.long 0x0 "PUEN_B0P1T2,LSI Pin Pull-enable Register B0P1T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x20C0++0x3 line.long 0x0 "PUEN_B1P1T0,LSI Pin Pull-enable Register B1P1T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x22C0++0x3 line.long 0x0 "PUEN_B1P1T1,LSI Pin Pull-enable Register B1P1T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x24C0++0x3 line.long 0x0 "PUEN_B1P1T2,LSI Pin Pull-enable Register B1P1T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x40C0++0x3 line.long 0x0 "PUEN_B2P1T0,LSI Pin Pull-enable Register B2P1T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x42C0++0x3 line.long 0x0 "PUEN_B2P1T1,LSI Pin Pull-enable Register B2P1T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x44C0++0x3 line.long 0x0 "PUEN_B2P1T2,LSI Pin Pull-enable Register B2P1T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x60C0++0x3 line.long 0x0 "PUEN_B3P1T0,LSI Pin Pull-enable Register B3P1T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x62C0++0x3 line.long 0x0 "PUEN_B3P1T1,LSI Pin Pull-enable Register B3P1T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x64C0++0x3 line.long 0x0 "PUEN_B3P1T2,LSI Pin Pull-enable Register B3P1T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0xE0++0x3 line.long 0x0 "PUD_B0P1T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x2E0++0x3 line.long 0x0 "PUD_B0P1T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x4E0++0x3 line.long 0x0 "PUD_B0P1T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x20E0++0x3 line.long 0x0 "PUD_B1P1T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x22E0++0x3 line.long 0x0 "PUD_B1P1T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x24E0++0x3 line.long 0x0 "PUD_B1P1T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x40E0++0x3 line.long 0x0 "PUD_B2P1T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x42E0++0x3 line.long 0x0 "PUD_B2P1T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x44E0++0x3 line.long 0x0 "PUD_B2P1T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x60E0++0x3 line.long 0x0 "PUD_B3P1T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x62E0++0x3 line.long 0x0 "PUD_B3P1T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x64E0++0x3 line.long 0x0 "PUD_B3P1T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x0++0x3 line.long 0x0 "PMMR_B0P1T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x200++0x3 line.long 0x0 "PMMR_B0P1T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x400++0x3 line.long 0x0 "PMMR_B0P1T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x800++0x3 line.long 0x0 "PMMR_B0P2T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xA00++0x3 line.long 0x0 "PMMR_B0P2T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xC00++0x3 line.long 0x0 "PMMR_B0P2T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2000++0x3 line.long 0x0 "PMMR_B1P1T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2200++0x3 line.long 0x0 "PMMR_B1P1T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2400++0x3 line.long 0x0 "PMMR_B1P1T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2800++0x3 line.long 0x0 "PMMR_B1P2T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2A00++0x3 line.long 0x0 "PMMR_B1P2T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2C00++0x3 line.long 0x0 "PMMR_B1P2T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4000++0x3 line.long 0x0 "PMMR_B2P1T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4200++0x3 line.long 0x0 "PMMR_B2P1T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4400++0x3 line.long 0x0 "PMMR_B2P1T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4800++0x3 line.long 0x0 "PMMR_B2P2T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4A00++0x3 line.long 0x0 "PMMR_B2P2T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4C00++0x3 line.long 0x0 "PMMR_B2P2T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6000++0x3 line.long 0x0 "PMMR_B3P1T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6200++0x3 line.long 0x0 "PMMR_B3P1T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6400++0x3 line.long 0x0 "PMMR_B3P1T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6800++0x3 line.long 0x0 "PMMR_B3P2T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6A00++0x3 line.long 0x0 "PMMR_B3P2T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6C00++0x3 line.long 0x0 "PMMR_B3P2T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4++0x3 line.long 0x0 "PMMER_B0P1T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x204++0x3 line.long 0x0 "PMMER_B0P1T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x404++0x3 line.long 0x0 "PMMER_B0P1T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x804++0x3 line.long 0x0 "PMMER_B0P2T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0xA04++0x3 line.long 0x0 "PMMER_B0P2T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0xC04++0x3 line.long 0x0 "PMMER_B0P2T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2004++0x3 line.long 0x0 "PMMER_B1P1T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2204++0x3 line.long 0x0 "PMMER_B1P1T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2404++0x3 line.long 0x0 "PMMER_B1P1T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2804++0x3 line.long 0x0 "PMMER_B1P2T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2A04++0x3 line.long 0x0 "PMMER_B1P2T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2C04++0x3 line.long 0x0 "PMMER_B1P2T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4004++0x3 line.long 0x0 "PMMER_B2P1T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4204++0x3 line.long 0x0 "PMMER_B2P1T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4404++0x3 line.long 0x0 "PMMER_B2P1T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4804++0x3 line.long 0x0 "PMMER_B2P2T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4A04++0x3 line.long 0x0 "PMMER_B2P2T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4C04++0x3 line.long 0x0 "PMMER_B2P2T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6004++0x3 line.long 0x0 "PMMER_B3P1T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6204++0x3 line.long 0x0 "PMMER_B3P1T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6404++0x3 line.long 0x0 "PMMER_B3P1T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6804++0x3 line.long 0x0 "PMMER_B3P2T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6A04++0x3 line.long 0x0 "PMMER_B3P2T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6C04++0x3 line.long 0x0 "PMMER_B3P2T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x20++0x3 line.long 0x0 "DMPR0_B0P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x220++0x3 line.long 0x0 "DMPR0_B0P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x420++0x3 line.long 0x0 "DMPR0_B0P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x820++0x3 line.long 0x0 "DMPR0_B0P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA20++0x3 line.long 0x0 "DMPR0_B0P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC20++0x3 line.long 0x0 "DMPR0_B0P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2020++0x3 line.long 0x0 "DMPR0_B1P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2220++0x3 line.long 0x0 "DMPR0_B1P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2420++0x3 line.long 0x0 "DMPR0_B1P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2820++0x3 line.long 0x0 "DMPR0_B1P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A20++0x3 line.long 0x0 "DMPR0_B1P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C20++0x3 line.long 0x0 "DMPR0_B1P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4020++0x3 line.long 0x0 "DMPR0_B2P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4220++0x3 line.long 0x0 "DMPR0_B2P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4420++0x3 line.long 0x0 "DMPR0_B2P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4820++0x3 line.long 0x0 "DMPR0_B2P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A20++0x3 line.long 0x0 "DMPR0_B2P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C20++0x3 line.long 0x0 "DMPR0_B2P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6020++0x3 line.long 0x0 "DMPR0_B3P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6220++0x3 line.long 0x0 "DMPR0_B3P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6420++0x3 line.long 0x0 "DMPR0_B3P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6820++0x3 line.long 0x0 "DMPR0_B3P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A20++0x3 line.long 0x0 "DMPR0_B3P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C20++0x3 line.long 0x0 "DMPR0_B3P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x24++0x3 line.long 0x0 "DMPR1_B0P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x224++0x3 line.long 0x0 "DMPR1_B0P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x424++0x3 line.long 0x0 "DMPR1_B0P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x824++0x3 line.long 0x0 "DMPR1_B0P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA24++0x3 line.long 0x0 "DMPR1_B0P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC24++0x3 line.long 0x0 "DMPR1_B0P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2024++0x3 line.long 0x0 "DMPR1_B1P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2224++0x3 line.long 0x0 "DMPR1_B1P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2424++0x3 line.long 0x0 "DMPR1_B1P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2824++0x3 line.long 0x0 "DMPR1_B1P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A24++0x3 line.long 0x0 "DMPR1_B1P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C24++0x3 line.long 0x0 "DMPR1_B1P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4024++0x3 line.long 0x0 "DMPR1_B2P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4224++0x3 line.long 0x0 "DMPR1_B2P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4424++0x3 line.long 0x0 "DMPR1_B2P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4824++0x3 line.long 0x0 "DMPR1_B2P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A24++0x3 line.long 0x0 "DMPR1_B2P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C24++0x3 line.long 0x0 "DMPR1_B2P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6024++0x3 line.long 0x0 "DMPR1_B3P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6224++0x3 line.long 0x0 "DMPR1_B3P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6424++0x3 line.long 0x0 "DMPR1_B3P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6824++0x3 line.long 0x0 "DMPR1_B3P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A24++0x3 line.long 0x0 "DMPR1_B3P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C24++0x3 line.long 0x0 "DMPR1_B3P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x28++0x3 line.long 0x0 "DMPR2_B0P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x228++0x3 line.long 0x0 "DMPR2_B0P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x428++0x3 line.long 0x0 "DMPR2_B0P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x828++0x3 line.long 0x0 "DMPR2_B0P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA28++0x3 line.long 0x0 "DMPR2_B0P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC28++0x3 line.long 0x0 "DMPR2_B0P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2028++0x3 line.long 0x0 "DMPR2_B1P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2228++0x3 line.long 0x0 "DMPR2_B1P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2428++0x3 line.long 0x0 "DMPR2_B1P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2828++0x3 line.long 0x0 "DMPR2_B1P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A28++0x3 line.long 0x0 "DMPR2_B1P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C28++0x3 line.long 0x0 "DMPR2_B1P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4028++0x3 line.long 0x0 "DMPR2_B2P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4228++0x3 line.long 0x0 "DMPR2_B2P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4428++0x3 line.long 0x0 "DMPR2_B2P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4828++0x3 line.long 0x0 "DMPR2_B2P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A28++0x3 line.long 0x0 "DMPR2_B2P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C28++0x3 line.long 0x0 "DMPR2_B2P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6028++0x3 line.long 0x0 "DMPR2_B3P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6228++0x3 line.long 0x0 "DMPR2_B3P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6428++0x3 line.long 0x0 "DMPR2_B3P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6828++0x3 line.long 0x0 "DMPR2_B3P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A28++0x3 line.long 0x0 "DMPR2_B3P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C28++0x3 line.long 0x0 "DMPR2_B3P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C++0x3 line.long 0x0 "DMPR3_B0P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x22C++0x3 line.long 0x0 "DMPR3_B0P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x42C++0x3 line.long 0x0 "DMPR3_B0P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x82C++0x3 line.long 0x0 "DMPR3_B0P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA2C++0x3 line.long 0x0 "DMPR3_B0P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC2C++0x3 line.long 0x0 "DMPR3_B0P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x202C++0x3 line.long 0x0 "DMPR3_B1P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x222C++0x3 line.long 0x0 "DMPR3_B1P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x242C++0x3 line.long 0x0 "DMPR3_B1P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x282C++0x3 line.long 0x0 "DMPR3_B1P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A2C++0x3 line.long 0x0 "DMPR3_B1P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C2C++0x3 line.long 0x0 "DMPR3_B1P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x402C++0x3 line.long 0x0 "DMPR3_B2P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x422C++0x3 line.long 0x0 "DMPR3_B2P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x442C++0x3 line.long 0x0 "DMPR3_B2P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x482C++0x3 line.long 0x0 "DMPR3_B2P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A2C++0x3 line.long 0x0 "DMPR3_B2P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C2C++0x3 line.long 0x0 "DMPR3_B2P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x602C++0x3 line.long 0x0 "DMPR3_B3P1T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x622C++0x3 line.long 0x0 "DMPR3_B3P1T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x642C++0x3 line.long 0x0 "DMPR3_B3P1T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x682C++0x3 line.long 0x0 "DMPR3_B3P2T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A2C++0x3 line.long 0x0 "DMPR3_B3P2T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C2C++0x3 line.long 0x0 "DMPR3_B3P2T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C++0x3 line.long 0x0 "IP3SR_B0P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x26C++0x3 line.long 0x0 "IP3SR_B0P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x46C++0x3 line.long 0x0 "IP3SR_B0P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x86C++0x3 line.long 0x0 "IP3SR_B0P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xA6C++0x3 line.long 0x0 "IP3SR_B0P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xC6C++0x3 line.long 0x0 "IP3SR_B0P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x206C++0x3 line.long 0x0 "IP3SR_B1P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x226C++0x3 line.long 0x0 "IP3SR_B1P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x246C++0x3 line.long 0x0 "IP3SR_B1P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x286C++0x3 line.long 0x0 "IP3SR_B1P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2A6C++0x3 line.long 0x0 "IP3SR_B1P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2C6C++0x3 line.long 0x0 "IP3SR_B1P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x406C++0x3 line.long 0x0 "IP3SR_B2P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x426C++0x3 line.long 0x0 "IP3SR_B2P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x446C++0x3 line.long 0x0 "IP3SR_B2P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x486C++0x3 line.long 0x0 "IP3SR_B2P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4A6C++0x3 line.long 0x0 "IP3SR_B2P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4C6C++0x3 line.long 0x0 "IP3SR_B2P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x606C++0x3 line.long 0x0 "IP3SR_B3P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x626C++0x3 line.long 0x0 "IP3SR_B3P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x646C++0x3 line.long 0x0 "IP3SR_B3P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x686C++0x3 line.long 0x0 "IP3SR_B3P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6A6C++0x3 line.long 0x0 "IP3SR_B3P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6C6C++0x3 line.long 0x0 "IP3SR_B3P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x84++0x3 line.long 0x0 "DRV1CTRL_B0P1T0,DRV Control Register1 B0P1T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x284++0x3 line.long 0x0 "DRV1CTRL_B0P1T1,DRV Control Register1 B0P1T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x484++0x3 line.long 0x0 "DRV1CTRL_B0P1T2,DRV Control Register1 B0P1T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x884++0x3 line.long 0x0 "DRV1CTRL_B0P2T0,DRV Control Register1 B0P2T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0xA84++0x3 line.long 0x0 "DRV1CTRL_B0P2T1,DRV Control Register1 B0P2T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0xC84++0x3 line.long 0x0 "DRV1CTRL_B0P2T2,DRV Control Register1 B0P2T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2084++0x3 line.long 0x0 "DRV1CTRL_B1P1T0,DRV Control Register1 B1P1T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2284++0x3 line.long 0x0 "DRV1CTRL_B1P1T1,DRV Control Register1 B1P1T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2484++0x3 line.long 0x0 "DRV1CTRL_B1P1T2,DRV Control Register1 B1P1T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2884++0x3 line.long 0x0 "DRV1CTRL_B1P2T0,DRV Control Register1 B1P2T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2A84++0x3 line.long 0x0 "DRV1CTRL_B1P2T1,DRV Control Register1 B1P2T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2C84++0x3 line.long 0x0 "DRV1CTRL_B1P2T2,DRV Control Register1 B1P2T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4084++0x3 line.long 0x0 "DRV1CTRL_B2P1T0,DRV Control Register1 B2P1T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4284++0x3 line.long 0x0 "DRV1CTRL_B2P1T1,DRV Control Register1 B2P1T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4484++0x3 line.long 0x0 "DRV1CTRL_B2P1T2,DRV Control Register1 B2P1T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4884++0x3 line.long 0x0 "DRV1CTRL_B2P2T0,DRV Control Register1 B2P2T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4A84++0x3 line.long 0x0 "DRV1CTRL_B2P2T1,DRV Control Register1 B2P2T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4C84++0x3 line.long 0x0 "DRV1CTRL_B2P2T2,DRV Control Register1 B2P2T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6084++0x3 line.long 0x0 "DRV1CTRL_B3P1T0,DRV Control Register1 B3P1T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6284++0x3 line.long 0x0 "DRV1CTRL_B3P1T1,DRV Control Register1 B3P1T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6484++0x3 line.long 0x0 "DRV1CTRL_B3P1T2,DRV Control Register1 B3P1T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6884++0x3 line.long 0x0 "DRV1CTRL_B3P2T0,DRV Control Register1 B3P2T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6A84++0x3 line.long 0x0 "DRV1CTRL_B3P2T1,DRV Control Register1 B3P2T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6C84++0x3 line.long 0x0 "DRV1CTRL_B3P2T2,DRV Control Register1 B3P2T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x100++0x3 line.long 0x0 "MODSEL_B0P1T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x300++0x3 line.long 0x0 "MODSEL_B0P1T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x500++0x3 line.long 0x0 "MODSEL_B0P1T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x900++0x3 line.long 0x0 "MODSEL_B0P2T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0xB00++0x3 line.long 0x0 "MODSEL_B0P2T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0xD00++0x3 line.long 0x0 "MODSEL_B0P2T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2100++0x3 line.long 0x0 "MODSEL_B1P1T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2300++0x3 line.long 0x0 "MODSEL_B1P1T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2500++0x3 line.long 0x0 "MODSEL_B1P1T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2900++0x3 line.long 0x0 "MODSEL_B1P2T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2B00++0x3 line.long 0x0 "MODSEL_B1P2T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2D00++0x3 line.long 0x0 "MODSEL_B1P2T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4100++0x3 line.long 0x0 "MODSEL_B2P1T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4300++0x3 line.long 0x0 "MODSEL_B2P1T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4500++0x3 line.long 0x0 "MODSEL_B2P1T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4900++0x3 line.long 0x0 "MODSEL_B2P2T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4B00++0x3 line.long 0x0 "MODSEL_B2P2T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4D00++0x3 line.long 0x0 "MODSEL_B2P2T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6100++0x3 line.long 0x0 "MODSEL_B3P1T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6300++0x3 line.long 0x0 "MODSEL_B3P1T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6500++0x3 line.long 0x0 "MODSEL_B3P1T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6900++0x3 line.long 0x0 "MODSEL_B3P2T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6B00++0x3 line.long 0x0 "MODSEL_B3P2T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6D00++0x3 line.long 0x0 "MODSEL_B3P2T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x120++0x3 line.long 0x0 "TD0SEL_B0P1T0,TDSEL Control Register0 B0P1T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x320++0x3 line.long 0x0 "TD0SEL_B0P1T1,TDSEL Control Register0 B0P1T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x520++0x3 line.long 0x0 "TD0SEL_B0P1T2,TDSEL Control Register0 B0P1T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x920++0x3 line.long 0x0 "TD0SEL_B0P2T0,TDSEL Control Register0 B0P2T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0xB20++0x3 line.long 0x0 "TD0SEL_B0P2T1,TDSEL Control Register0 B0P2T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0xD20++0x3 line.long 0x0 "TD0SEL_B0P2T2,TDSEL Control Register0 B0P2T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2120++0x3 line.long 0x0 "TD0SEL_B1P1T0,TDSEL Control Register0 B1P1T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2320++0x3 line.long 0x0 "TD0SEL_B1P1T1,TDSEL Control Register0 B1P1T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2520++0x3 line.long 0x0 "TD0SEL_B1P1T2,TDSEL Control Register0 B1P1T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2920++0x3 line.long 0x0 "TD0SEL_B1P2T0,TDSEL Control Register0 B1P2T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2B20++0x3 line.long 0x0 "TD0SEL_B1P2T1,TDSEL Control Register0 B1P2T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2D20++0x3 line.long 0x0 "TD0SEL_B1P2T2,TDSEL Control Register0 B1P2T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4120++0x3 line.long 0x0 "TD0SEL_B2P1T0,TDSEL Control Register0 B2P1T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4320++0x3 line.long 0x0 "TD0SEL_B2P1T1,TDSEL Control Register0 B2P1T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4520++0x3 line.long 0x0 "TD0SEL_B2P1T2,TDSEL Control Register0 B2P1T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4920++0x3 line.long 0x0 "TD0SEL_B2P2T0,TDSEL Control Register0 B2P2T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4B20++0x3 line.long 0x0 "TD0SEL_B2P2T1,TDSEL Control Register0 B2P2T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4D20++0x3 line.long 0x0 "TD0SEL_B2P2T2,TDSEL Control Register0 B2P2T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6120++0x3 line.long 0x0 "TD0SEL_B3P1T0,TDSEL Control Register0 B3P1T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6320++0x3 line.long 0x0 "TD0SEL_B3P1T1,TDSEL Control Register0 B3P1T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6520++0x3 line.long 0x0 "TD0SEL_B3P1T2,TDSEL Control Register0 B3P1T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6920++0x3 line.long 0x0 "TD0SEL_B3P2T0,TDSEL Control Register0 B3P2T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6B20++0x3 line.long 0x0 "TD0SEL_B3P2T1,TDSEL Control Register0 B3P2T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6D20++0x3 line.long 0x0 "TD0SEL_B3P2T2,TDSEL Control Register0 B3P2T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x124++0x3 line.long 0x0 "TD1SEL_B0P1T0,TDSEL Control Register1 B0P1T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x324++0x3 line.long 0x0 "TD1SEL_B0P1T1,TDSEL Control Register1 B0P1T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x524++0x3 line.long 0x0 "TD1SEL_B0P1T2,TDSEL Control Register1 B0P1T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x924++0x3 line.long 0x0 "TD1SEL_B0P2T0,TDSEL Control Register1 B0P2T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0xB24++0x3 line.long 0x0 "TD1SEL_B0P2T1,TDSEL Control Register1 B0P2T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0xD24++0x3 line.long 0x0 "TD1SEL_B0P2T2,TDSEL Control Register1 B0P2T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2124++0x3 line.long 0x0 "TD1SEL_B1P1T0,TDSEL Control Register1 B1P1T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2324++0x3 line.long 0x0 "TD1SEL_B1P1T1,TDSEL Control Register1 B1P1T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2524++0x3 line.long 0x0 "TD1SEL_B1P1T2,TDSEL Control Register1 B1P1T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2924++0x3 line.long 0x0 "TD1SEL_B1P2T0,TDSEL Control Register1 B1P2T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2B24++0x3 line.long 0x0 "TD1SEL_B1P2T1,TDSEL Control Register1 B1P2T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2D24++0x3 line.long 0x0 "TD1SEL_B1P2T2,TDSEL Control Register1 B1P2T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4124++0x3 line.long 0x0 "TD1SEL_B2P1T0,TDSEL Control Register1 B2P1T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4324++0x3 line.long 0x0 "TD1SEL_B2P1T1,TDSEL Control Register1 B2P1T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4524++0x3 line.long 0x0 "TD1SEL_B2P1T2,TDSEL Control Register1 B2P1T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4924++0x3 line.long 0x0 "TD1SEL_B2P2T0,TDSEL Control Register1 B2P2T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4B24++0x3 line.long 0x0 "TD1SEL_B2P2T1,TDSEL Control Register1 B2P2T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4D24++0x3 line.long 0x0 "TD1SEL_B2P2T2,TDSEL Control Register1 B2P2T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6124++0x3 line.long 0x0 "TD1SEL_B3P1T0,TDSEL Control Register1 B3P1T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6324++0x3 line.long 0x0 "TD1SEL_B3P1T1,TDSEL Control Register1 B3P1T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6524++0x3 line.long 0x0 "TD1SEL_B3P1T2,TDSEL Control Register1 B3P1T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6924++0x3 line.long 0x0 "TD1SEL_B3P2T0,TDSEL Control Register1 B3P2T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6B24++0x3 line.long 0x0 "TD1SEL_B3P2T1,TDSEL Control Register1 B3P2T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6D24++0x3 line.long 0x0 "TD1SEL_B3P2T2,TDSEL Control Register1 B3P2T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x140++0x3 line.long 0x0 "BIPSR0_B0P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x340++0x3 line.long 0x0 "BIPSR0_B0P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x540++0x3 line.long 0x0 "BIPSR0_B0P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x940++0x3 line.long 0x0 "BIPSR0_B0P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB40++0x3 line.long 0x0 "BIPSR0_B0P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD40++0x3 line.long 0x0 "BIPSR0_B0P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2140++0x3 line.long 0x0 "BIPSR0_B1P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2340++0x3 line.long 0x0 "BIPSR0_B1P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2540++0x3 line.long 0x0 "BIPSR0_B1P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2940++0x3 line.long 0x0 "BIPSR0_B1P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B40++0x3 line.long 0x0 "BIPSR0_B1P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D40++0x3 line.long 0x0 "BIPSR0_B1P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4140++0x3 line.long 0x0 "BIPSR0_B2P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4340++0x3 line.long 0x0 "BIPSR0_B2P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4540++0x3 line.long 0x0 "BIPSR0_B2P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4940++0x3 line.long 0x0 "BIPSR0_B2P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B40++0x3 line.long 0x0 "BIPSR0_B2P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D40++0x3 line.long 0x0 "BIPSR0_B2P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6140++0x3 line.long 0x0 "BIPSR0_B3P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6340++0x3 line.long 0x0 "BIPSR0_B3P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6540++0x3 line.long 0x0 "BIPSR0_B3P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6940++0x3 line.long 0x0 "BIPSR0_B3P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B40++0x3 line.long 0x0 "BIPSR0_B3P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D40++0x3 line.long 0x0 "BIPSR0_B3P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x144++0x3 line.long 0x0 "BIPSR1_B0P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x344++0x3 line.long 0x0 "BIPSR1_B0P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x544++0x3 line.long 0x0 "BIPSR1_B0P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x944++0x3 line.long 0x0 "BIPSR1_B0P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB44++0x3 line.long 0x0 "BIPSR1_B0P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD44++0x3 line.long 0x0 "BIPSR1_B0P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2144++0x3 line.long 0x0 "BIPSR1_B1P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2344++0x3 line.long 0x0 "BIPSR1_B1P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2544++0x3 line.long 0x0 "BIPSR1_B1P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2944++0x3 line.long 0x0 "BIPSR1_B1P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B44++0x3 line.long 0x0 "BIPSR1_B1P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D44++0x3 line.long 0x0 "BIPSR1_B1P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4144++0x3 line.long 0x0 "BIPSR1_B2P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4344++0x3 line.long 0x0 "BIPSR1_B2P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4544++0x3 line.long 0x0 "BIPSR1_B2P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4944++0x3 line.long 0x0 "BIPSR1_B2P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B44++0x3 line.long 0x0 "BIPSR1_B2P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D44++0x3 line.long 0x0 "BIPSR1_B2P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6144++0x3 line.long 0x0 "BIPSR1_B3P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6344++0x3 line.long 0x0 "BIPSR1_B3P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6544++0x3 line.long 0x0 "BIPSR1_B3P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6944++0x3 line.long 0x0 "BIPSR1_B3P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B44++0x3 line.long 0x0 "BIPSR1_B3P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D44++0x3 line.long 0x0 "BIPSR1_B3P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x148++0x3 line.long 0x0 "BIPSR2_B0P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x348++0x3 line.long 0x0 "BIPSR2_B0P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x548++0x3 line.long 0x0 "BIPSR2_B0P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x948++0x3 line.long 0x0 "BIPSR2_B0P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB48++0x3 line.long 0x0 "BIPSR2_B0P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD48++0x3 line.long 0x0 "BIPSR2_B0P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2148++0x3 line.long 0x0 "BIPSR2_B1P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2348++0x3 line.long 0x0 "BIPSR2_B1P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2548++0x3 line.long 0x0 "BIPSR2_B1P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2948++0x3 line.long 0x0 "BIPSR2_B1P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B48++0x3 line.long 0x0 "BIPSR2_B1P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D48++0x3 line.long 0x0 "BIPSR2_B1P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4148++0x3 line.long 0x0 "BIPSR2_B2P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4348++0x3 line.long 0x0 "BIPSR2_B2P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4548++0x3 line.long 0x0 "BIPSR2_B2P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4948++0x3 line.long 0x0 "BIPSR2_B2P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B48++0x3 line.long 0x0 "BIPSR2_B2P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D48++0x3 line.long 0x0 "BIPSR2_B2P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6148++0x3 line.long 0x0 "BIPSR2_B3P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6348++0x3 line.long 0x0 "BIPSR2_B3P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6548++0x3 line.long 0x0 "BIPSR2_B3P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6948++0x3 line.long 0x0 "BIPSR2_B3P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B48++0x3 line.long 0x0 "BIPSR2_B3P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D48++0x3 line.long 0x0 "BIPSR2_B3P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x14C++0x3 line.long 0x0 "BIPSR3_B0P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x34C++0x3 line.long 0x0 "BIPSR3_B0P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x54C++0x3 line.long 0x0 "BIPSR3_B0P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x94C++0x3 line.long 0x0 "BIPSR3_B0P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB4C++0x3 line.long 0x0 "BIPSR3_B0P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD4C++0x3 line.long 0x0 "BIPSR3_B0P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x214C++0x3 line.long 0x0 "BIPSR3_B1P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x234C++0x3 line.long 0x0 "BIPSR3_B1P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x254C++0x3 line.long 0x0 "BIPSR3_B1P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x294C++0x3 line.long 0x0 "BIPSR3_B1P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B4C++0x3 line.long 0x0 "BIPSR3_B1P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D4C++0x3 line.long 0x0 "BIPSR3_B1P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x414C++0x3 line.long 0x0 "BIPSR3_B2P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x434C++0x3 line.long 0x0 "BIPSR3_B2P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x454C++0x3 line.long 0x0 "BIPSR3_B2P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x494C++0x3 line.long 0x0 "BIPSR3_B2P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B4C++0x3 line.long 0x0 "BIPSR3_B2P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D4C++0x3 line.long 0x0 "BIPSR3_B2P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x614C++0x3 line.long 0x0 "BIPSR3_B3P1T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x634C++0x3 line.long 0x0 "BIPSR3_B3P1T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x654C++0x3 line.long 0x0 "BIPSR3_B3P1T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x694C++0x3 line.long 0x0 "BIPSR3_B3P2T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B4C++0x3 line.long 0x0 "BIPSR3_B3P2T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D4C++0x3 line.long 0x0 "BIPSR3_B3P2T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x160++0x3 line.long 0x0 "PSER_B0P1T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x360++0x3 line.long 0x0 "PSER_B0P1T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x560++0x3 line.long 0x0 "PSER_B0P1T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x960++0x3 line.long 0x0 "PSER_B0P2T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0xB60++0x3 line.long 0x0 "PSER_B0P2T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0xD60++0x3 line.long 0x0 "PSER_B0P2T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2160++0x3 line.long 0x0 "PSER_B1P1T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2360++0x3 line.long 0x0 "PSER_B1P1T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2560++0x3 line.long 0x0 "PSER_B1P1T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2960++0x3 line.long 0x0 "PSER_B1P2T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2B60++0x3 line.long 0x0 "PSER_B1P2T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2D60++0x3 line.long 0x0 "PSER_B1P2T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4160++0x3 line.long 0x0 "PSER_B2P1T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4360++0x3 line.long 0x0 "PSER_B2P1T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4560++0x3 line.long 0x0 "PSER_B2P1T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4960++0x3 line.long 0x0 "PSER_B2P2T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4B60++0x3 line.long 0x0 "PSER_B2P2T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4D60++0x3 line.long 0x0 "PSER_B2P2T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6160++0x3 line.long 0x0 "PSER_B3P1T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6360++0x3 line.long 0x0 "PSER_B3P1T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6560++0x3 line.long 0x0 "PSER_B3P1T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6960++0x3 line.long 0x0 "PSER_B3P2T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6B60++0x3 line.long 0x0 "PSER_B3P2T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6D60++0x3 line.long 0x0 "PSER_B3P2T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x164++0x3 line.long 0x0 "PS0SR_B0P1T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x364++0x3 line.long 0x0 "PS0SR_B0P1T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x564++0x3 line.long 0x0 "PS0SR_B0P1T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x964++0x3 line.long 0x0 "PS0SR_B0P2T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0xB64++0x3 line.long 0x0 "PS0SR_B0P2T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0xD64++0x3 line.long 0x0 "PS0SR_B0P2T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2164++0x3 line.long 0x0 "PS0SR_B1P1T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2364++0x3 line.long 0x0 "PS0SR_B1P1T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2564++0x3 line.long 0x0 "PS0SR_B1P1T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2964++0x3 line.long 0x0 "PS0SR_B1P2T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2B64++0x3 line.long 0x0 "PS0SR_B1P2T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2D64++0x3 line.long 0x0 "PS0SR_B1P2T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4164++0x3 line.long 0x0 "PS0SR_B2P1T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4364++0x3 line.long 0x0 "PS0SR_B2P1T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4564++0x3 line.long 0x0 "PS0SR_B2P1T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4964++0x3 line.long 0x0 "PS0SR_B2P2T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4B64++0x3 line.long 0x0 "PS0SR_B2P2T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4D64++0x3 line.long 0x0 "PS0SR_B2P2T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6164++0x3 line.long 0x0 "PS0SR_B3P1T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6364++0x3 line.long 0x0 "PS0SR_B3P1T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6564++0x3 line.long 0x0 "PS0SR_B3P1T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6964++0x3 line.long 0x0 "PS0SR_B3P2T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6B64++0x3 line.long 0x0 "PS0SR_B3P2T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6D64++0x3 line.long 0x0 "PS0SR_B3P2T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x168++0x3 line.long 0x0 "PS1SR_B0P1T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x368++0x3 line.long 0x0 "PS1SR_B0P1T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x568++0x3 line.long 0x0 "PS1SR_B0P1T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x968++0x3 line.long 0x0 "PS1SR_B0P2T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0xB68++0x3 line.long 0x0 "PS1SR_B0P2T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0xD68++0x3 line.long 0x0 "PS1SR_B0P2T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2168++0x3 line.long 0x0 "PS1SR_B1P1T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2368++0x3 line.long 0x0 "PS1SR_B1P1T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2568++0x3 line.long 0x0 "PS1SR_B1P1T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2968++0x3 line.long 0x0 "PS1SR_B1P2T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2B68++0x3 line.long 0x0 "PS1SR_B1P2T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2D68++0x3 line.long 0x0 "PS1SR_B1P2T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4168++0x3 line.long 0x0 "PS1SR_B2P1T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4368++0x3 line.long 0x0 "PS1SR_B2P1T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4568++0x3 line.long 0x0 "PS1SR_B2P1T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4968++0x3 line.long 0x0 "PS1SR_B2P2T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4B68++0x3 line.long 0x0 "PS1SR_B2P2T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4D68++0x3 line.long 0x0 "PS1SR_B2P2T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6168++0x3 line.long 0x0 "PS1SR_B3P1T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6368++0x3 line.long 0x0 "PS1SR_B3P1T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6568++0x3 line.long 0x0 "PS1SR_B3P1T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6968++0x3 line.long 0x0 "PS1SR_B3P2T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6B68++0x3 line.long 0x0 "PS1SR_B3P2T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6D68++0x3 line.long 0x0 "PS1SR_B3P2T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x180++0x3 line.long 0x0 "IOINTSEL_B0P1T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x380++0x3 line.long 0x0 "IOINTSEL_B0P1T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x580++0x3 line.long 0x0 "IOINTSEL_B0P1T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x980++0x3 line.long 0x0 "IOINTSEL_B0P2T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0xB80++0x3 line.long 0x0 "IOINTSEL_B0P2T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0xD80++0x3 line.long 0x0 "IOINTSEL_B0P2T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2180++0x3 line.long 0x0 "IOINTSEL_B1P1T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2380++0x3 line.long 0x0 "IOINTSEL_B1P1T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2580++0x3 line.long 0x0 "IOINTSEL_B1P1T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2980++0x3 line.long 0x0 "IOINTSEL_B1P2T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2B80++0x3 line.long 0x0 "IOINTSEL_B1P2T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2D80++0x3 line.long 0x0 "IOINTSEL_B1P2T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4180++0x3 line.long 0x0 "IOINTSEL_B2P1T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4380++0x3 line.long 0x0 "IOINTSEL_B2P1T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4580++0x3 line.long 0x0 "IOINTSEL_B2P1T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4980++0x3 line.long 0x0 "IOINTSEL_B2P2T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4B80++0x3 line.long 0x0 "IOINTSEL_B2P2T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4D80++0x3 line.long 0x0 "IOINTSEL_B2P2T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6180++0x3 line.long 0x0 "IOINTSEL_B3P1T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6380++0x3 line.long 0x0 "IOINTSEL_B3P1T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6580++0x3 line.long 0x0 "IOINTSEL_B3P1T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6980++0x3 line.long 0x0 "IOINTSEL_B3P2T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6B80++0x3 line.long 0x0 "IOINTSEL_B3P2T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6D80++0x3 line.long 0x0 "IOINTSEL_B3P2T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x184++0x3 line.long 0x0 "INOUTSEL_B0P1T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x384++0x3 line.long 0x0 "INOUTSEL_B0P1T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x584++0x3 line.long 0x0 "INOUTSEL_B0P1T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x984++0x3 line.long 0x0 "INOUTSEL_B0P2T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0xB84++0x3 line.long 0x0 "INOUTSEL_B0P2T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0xD84++0x3 line.long 0x0 "INOUTSEL_B0P2T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2184++0x3 line.long 0x0 "INOUTSEL_B1P1T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2384++0x3 line.long 0x0 "INOUTSEL_B1P1T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2584++0x3 line.long 0x0 "INOUTSEL_B1P1T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2984++0x3 line.long 0x0 "INOUTSEL_B1P2T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2B84++0x3 line.long 0x0 "INOUTSEL_B1P2T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2D84++0x3 line.long 0x0 "INOUTSEL_B1P2T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4184++0x3 line.long 0x0 "INOUTSEL_B2P1T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4384++0x3 line.long 0x0 "INOUTSEL_B2P1T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4584++0x3 line.long 0x0 "INOUTSEL_B2P1T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4984++0x3 line.long 0x0 "INOUTSEL_B2P2T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4B84++0x3 line.long 0x0 "INOUTSEL_B2P2T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4D84++0x3 line.long 0x0 "INOUTSEL_B2P2T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6184++0x3 line.long 0x0 "INOUTSEL_B3P1T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6384++0x3 line.long 0x0 "INOUTSEL_B3P1T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6584++0x3 line.long 0x0 "INOUTSEL_B3P1T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6984++0x3 line.long 0x0 "INOUTSEL_B3P2T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6B84++0x3 line.long 0x0 "INOUTSEL_B3P2T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6D84++0x3 line.long 0x0 "INOUTSEL_B3P2T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x188++0x3 line.long 0x0 "OUTDT_B0P1T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x388++0x3 line.long 0x0 "OUTDT_B0P1T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x588++0x3 line.long 0x0 "OUTDT_B0P1T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x988++0x3 line.long 0x0 "OUTDT_B0P2T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0xB88++0x3 line.long 0x0 "OUTDT_B0P2T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0xD88++0x3 line.long 0x0 "OUTDT_B0P2T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2188++0x3 line.long 0x0 "OUTDT_B1P1T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2388++0x3 line.long 0x0 "OUTDT_B1P1T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2588++0x3 line.long 0x0 "OUTDT_B1P1T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2988++0x3 line.long 0x0 "OUTDT_B1P2T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2B88++0x3 line.long 0x0 "OUTDT_B1P2T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2D88++0x3 line.long 0x0 "OUTDT_B1P2T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4188++0x3 line.long 0x0 "OUTDT_B2P1T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4388++0x3 line.long 0x0 "OUTDT_B2P1T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4588++0x3 line.long 0x0 "OUTDT_B2P1T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4988++0x3 line.long 0x0 "OUTDT_B2P2T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4B88++0x3 line.long 0x0 "OUTDT_B2P2T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4D88++0x3 line.long 0x0 "OUTDT_B2P2T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6188++0x3 line.long 0x0 "OUTDT_B3P1T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6388++0x3 line.long 0x0 "OUTDT_B3P1T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6588++0x3 line.long 0x0 "OUTDT_B3P1T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6988++0x3 line.long 0x0 "OUTDT_B3P2T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6B88++0x3 line.long 0x0 "OUTDT_B3P2T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6D88++0x3 line.long 0x0 "OUTDT_B3P2T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." rgroup.long 0x18C++0x3 line.long 0x0 "INDT_B0P1T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x38C++0x3 line.long 0x0 "INDT_B0P1T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x58C++0x3 line.long 0x0 "INDT_B0P1T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x98C++0x3 line.long 0x0 "INDT_B0P2T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0xB8C++0x3 line.long 0x0 "INDT_B0P2T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0xD8C++0x3 line.long 0x0 "INDT_B0P2T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x218C++0x3 line.long 0x0 "INDT_B1P1T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x238C++0x3 line.long 0x0 "INDT_B1P1T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x258C++0x3 line.long 0x0 "INDT_B1P1T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x298C++0x3 line.long 0x0 "INDT_B1P2T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x2B8C++0x3 line.long 0x0 "INDT_B1P2T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x2D8C++0x3 line.long 0x0 "INDT_B1P2T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x418C++0x3 line.long 0x0 "INDT_B2P1T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x438C++0x3 line.long 0x0 "INDT_B2P1T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x458C++0x3 line.long 0x0 "INDT_B2P1T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x498C++0x3 line.long 0x0 "INDT_B2P2T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x4B8C++0x3 line.long 0x0 "INDT_B2P2T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x4D8C++0x3 line.long 0x0 "INDT_B2P2T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x618C++0x3 line.long 0x0 "INDT_B3P1T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x638C++0x3 line.long 0x0 "INDT_B3P1T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x658C++0x3 line.long 0x0 "INDT_B3P1T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x698C++0x3 line.long 0x0 "INDT_B3P2T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x6B8C++0x3 line.long 0x0 "INDT_B3P2T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x6D8C++0x3 line.long 0x0 "INDT_B3P2T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x190++0x3 line.long 0x0 "INTDT_B0P1T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x390++0x3 line.long 0x0 "INTDT_B0P1T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x590++0x3 line.long 0x0 "INTDT_B0P1T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x990++0x3 line.long 0x0 "INTDT_B0P2T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0xB90++0x3 line.long 0x0 "INTDT_B0P2T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0xD90++0x3 line.long 0x0 "INTDT_B0P2T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2190++0x3 line.long 0x0 "INTDT_B1P1T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2390++0x3 line.long 0x0 "INTDT_B1P1T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2590++0x3 line.long 0x0 "INTDT_B1P1T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2990++0x3 line.long 0x0 "INTDT_B1P2T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2B90++0x3 line.long 0x0 "INTDT_B1P2T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2D90++0x3 line.long 0x0 "INTDT_B1P2T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4190++0x3 line.long 0x0 "INTDT_B2P1T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4390++0x3 line.long 0x0 "INTDT_B2P1T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4590++0x3 line.long 0x0 "INTDT_B2P1T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4990++0x3 line.long 0x0 "INTDT_B2P2T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4B90++0x3 line.long 0x0 "INTDT_B2P2T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4D90++0x3 line.long 0x0 "INTDT_B2P2T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6190++0x3 line.long 0x0 "INTDT_B3P1T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6390++0x3 line.long 0x0 "INTDT_B3P1T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6590++0x3 line.long 0x0 "INTDT_B3P1T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6990++0x3 line.long 0x0 "INTDT_B3P2T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6B90++0x3 line.long 0x0 "INTDT_B3P2T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6D90++0x3 line.long 0x0 "INTDT_B3P2T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." group.long 0x194++0x3 line.long 0x0 "INTCLR_B0P1T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x394++0x3 line.long 0x0 "INTCLR_B0P1T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x594++0x3 line.long 0x0 "INTCLR_B0P1T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x994++0x3 line.long 0x0 "INTCLR_B0P2T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0xB94++0x3 line.long 0x0 "INTCLR_B0P2T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0xD94++0x3 line.long 0x0 "INTCLR_B0P2T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2194++0x3 line.long 0x0 "INTCLR_B1P1T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2394++0x3 line.long 0x0 "INTCLR_B1P1T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2594++0x3 line.long 0x0 "INTCLR_B1P1T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2994++0x3 line.long 0x0 "INTCLR_B1P2T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2B94++0x3 line.long 0x0 "INTCLR_B1P2T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2D94++0x3 line.long 0x0 "INTCLR_B1P2T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4194++0x3 line.long 0x0 "INTCLR_B2P1T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4394++0x3 line.long 0x0 "INTCLR_B2P1T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4594++0x3 line.long 0x0 "INTCLR_B2P1T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4994++0x3 line.long 0x0 "INTCLR_B2P2T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4B94++0x3 line.long 0x0 "INTCLR_B2P2T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4D94++0x3 line.long 0x0 "INTCLR_B2P2T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6194++0x3 line.long 0x0 "INTCLR_B3P1T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6394++0x3 line.long 0x0 "INTCLR_B3P1T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6594++0x3 line.long 0x0 "INTCLR_B3P1T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6994++0x3 line.long 0x0 "INTCLR_B3P2T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6B94++0x3 line.long 0x0 "INTCLR_B3P2T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6D94++0x3 line.long 0x0 "INTCLR_B3P2T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x198++0x3 line.long 0x0 "INTMSK_B0P1T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x398++0x3 line.long 0x0 "INTMSK_B0P1T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x598++0x3 line.long 0x0 "INTMSK_B0P1T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x998++0x3 line.long 0x0 "INTMSK_B0P2T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0xB98++0x3 line.long 0x0 "INTMSK_B0P2T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0xD98++0x3 line.long 0x0 "INTMSK_B0P2T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2198++0x3 line.long 0x0 "INTMSK_B1P1T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2398++0x3 line.long 0x0 "INTMSK_B1P1T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2598++0x3 line.long 0x0 "INTMSK_B1P1T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2998++0x3 line.long 0x0 "INTMSK_B1P2T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2B98++0x3 line.long 0x0 "INTMSK_B1P2T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2D98++0x3 line.long 0x0 "INTMSK_B1P2T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4198++0x3 line.long 0x0 "INTMSK_B2P1T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4398++0x3 line.long 0x0 "INTMSK_B2P1T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4598++0x3 line.long 0x0 "INTMSK_B2P1T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4998++0x3 line.long 0x0 "INTMSK_B2P2T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4B98++0x3 line.long 0x0 "INTMSK_B2P2T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4D98++0x3 line.long 0x0 "INTMSK_B2P2T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6198++0x3 line.long 0x0 "INTMSK_B3P1T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6398++0x3 line.long 0x0 "INTMSK_B3P1T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6598++0x3 line.long 0x0 "INTMSK_B3P1T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6998++0x3 line.long 0x0 "INTMSK_B3P2T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6B98++0x3 line.long 0x0 "INTMSK_B3P2T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6D98++0x3 line.long 0x0 "INTMSK_B3P2T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x19C++0x3 line.long 0x0 "MSKCLR_B0P1T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x39C++0x3 line.long 0x0 "MSKCLR_B0P1T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x59C++0x3 line.long 0x0 "MSKCLR_B0P1T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x99C++0x3 line.long 0x0 "MSKCLR_B0P2T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0xB9C++0x3 line.long 0x0 "MSKCLR_B0P2T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0xD9C++0x3 line.long 0x0 "MSKCLR_B0P2T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x219C++0x3 line.long 0x0 "MSKCLR_B1P1T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x239C++0x3 line.long 0x0 "MSKCLR_B1P1T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x259C++0x3 line.long 0x0 "MSKCLR_B1P1T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x299C++0x3 line.long 0x0 "MSKCLR_B1P2T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x2B9C++0x3 line.long 0x0 "MSKCLR_B1P2T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x2D9C++0x3 line.long 0x0 "MSKCLR_B1P2T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x419C++0x3 line.long 0x0 "MSKCLR_B2P1T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x439C++0x3 line.long 0x0 "MSKCLR_B2P1T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x459C++0x3 line.long 0x0 "MSKCLR_B2P1T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x499C++0x3 line.long 0x0 "MSKCLR_B2P2T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x4B9C++0x3 line.long 0x0 "MSKCLR_B2P2T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x4D9C++0x3 line.long 0x0 "MSKCLR_B2P2T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x619C++0x3 line.long 0x0 "MSKCLR_B3P1T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x639C++0x3 line.long 0x0 "MSKCLR_B3P1T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x659C++0x3 line.long 0x0 "MSKCLR_B3P1T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x699C++0x3 line.long 0x0 "MSKCLR_B3P2T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x6B9C++0x3 line.long 0x0 "MSKCLR_B3P2T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x6D9C++0x3 line.long 0x0 "MSKCLR_B3P2T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x1A0++0x3 line.long 0x0 "POSNEG_B0P1T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x3A0++0x3 line.long 0x0 "POSNEG_B0P1T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x5A0++0x3 line.long 0x0 "POSNEG_B0P1T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x9A0++0x3 line.long 0x0 "POSNEG_B0P2T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0xBA0++0x3 line.long 0x0 "POSNEG_B0P2T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0xDA0++0x3 line.long 0x0 "POSNEG_B0P2T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x21A0++0x3 line.long 0x0 "POSNEG_B1P1T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x23A0++0x3 line.long 0x0 "POSNEG_B1P1T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x25A0++0x3 line.long 0x0 "POSNEG_B1P1T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x29A0++0x3 line.long 0x0 "POSNEG_B1P2T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x2BA0++0x3 line.long 0x0 "POSNEG_B1P2T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x2DA0++0x3 line.long 0x0 "POSNEG_B1P2T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x41A0++0x3 line.long 0x0 "POSNEG_B2P1T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x43A0++0x3 line.long 0x0 "POSNEG_B2P1T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x45A0++0x3 line.long 0x0 "POSNEG_B2P1T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x49A0++0x3 line.long 0x0 "POSNEG_B2P2T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x4BA0++0x3 line.long 0x0 "POSNEG_B2P2T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x4DA0++0x3 line.long 0x0 "POSNEG_B2P2T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x61A0++0x3 line.long 0x0 "POSNEG_B3P1T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x63A0++0x3 line.long 0x0 "POSNEG_B3P1T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x65A0++0x3 line.long 0x0 "POSNEG_B3P1T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x69A0++0x3 line.long 0x0 "POSNEG_B3P2T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x6BA0++0x3 line.long 0x0 "POSNEG_B3P2T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x6DA0++0x3 line.long 0x0 "POSNEG_B3P2T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x1A4++0x3 line.long 0x0 "EDGLEVEL_B0P1T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x3A4++0x3 line.long 0x0 "EDGLEVEL_B0P1T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x5A4++0x3 line.long 0x0 "EDGLEVEL_B0P1T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x9A4++0x3 line.long 0x0 "EDGLEVEL_B0P2T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0xBA4++0x3 line.long 0x0 "EDGLEVEL_B0P2T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0xDA4++0x3 line.long 0x0 "EDGLEVEL_B0P2T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x21A4++0x3 line.long 0x0 "EDGLEVEL_B1P1T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x23A4++0x3 line.long 0x0 "EDGLEVEL_B1P1T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x25A4++0x3 line.long 0x0 "EDGLEVEL_B1P1T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x29A4++0x3 line.long 0x0 "EDGLEVEL_B1P2T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x2BA4++0x3 line.long 0x0 "EDGLEVEL_B1P2T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x2DA4++0x3 line.long 0x0 "EDGLEVEL_B1P2T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x41A4++0x3 line.long 0x0 "EDGLEVEL_B2P1T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x43A4++0x3 line.long 0x0 "EDGLEVEL_B2P1T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x45A4++0x3 line.long 0x0 "EDGLEVEL_B2P1T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x49A4++0x3 line.long 0x0 "EDGLEVEL_B2P2T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x4BA4++0x3 line.long 0x0 "EDGLEVEL_B2P2T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x4DA4++0x3 line.long 0x0 "EDGLEVEL_B2P2T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x61A4++0x3 line.long 0x0 "EDGLEVEL_B3P1T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x63A4++0x3 line.long 0x0 "EDGLEVEL_B3P1T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x65A4++0x3 line.long 0x0 "EDGLEVEL_B3P1T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x69A4++0x3 line.long 0x0 "EDGLEVEL_B3P2T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x6BA4++0x3 line.long 0x0 "EDGLEVEL_B3P2T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x6DA4++0x3 line.long 0x0 "EDGLEVEL_B3P2T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x1A8++0x3 line.long 0x0 "FILONOFF_B0P1T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x3A8++0x3 line.long 0x0 "FILONOFF_B0P1T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x5A8++0x3 line.long 0x0 "FILONOFF_B0P1T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x9A8++0x3 line.long 0x0 "FILONOFF_B0P2T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0xBA8++0x3 line.long 0x0 "FILONOFF_B0P2T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0xDA8++0x3 line.long 0x0 "FILONOFF_B0P2T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x21A8++0x3 line.long 0x0 "FILONOFF_B1P1T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x23A8++0x3 line.long 0x0 "FILONOFF_B1P1T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x25A8++0x3 line.long 0x0 "FILONOFF_B1P1T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x29A8++0x3 line.long 0x0 "FILONOFF_B1P2T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x2BA8++0x3 line.long 0x0 "FILONOFF_B1P2T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x2DA8++0x3 line.long 0x0 "FILONOFF_B1P2T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x41A8++0x3 line.long 0x0 "FILONOFF_B2P1T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x43A8++0x3 line.long 0x0 "FILONOFF_B2P1T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x45A8++0x3 line.long 0x0 "FILONOFF_B2P1T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x49A8++0x3 line.long 0x0 "FILONOFF_B2P2T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x4BA8++0x3 line.long 0x0 "FILONOFF_B2P2T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x4DA8++0x3 line.long 0x0 "FILONOFF_B2P2T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x61A8++0x3 line.long 0x0 "FILONOFF_B3P1T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x63A8++0x3 line.long 0x0 "FILONOFF_B3P1T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x65A8++0x3 line.long 0x0 "FILONOFF_B3P1T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x69A8++0x3 line.long 0x0 "FILONOFF_B3P2T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x6BA8++0x3 line.long 0x0 "FILONOFF_B3P2T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x6DA8++0x3 line.long 0x0 "FILONOFF_B3P2T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x1AC++0x3 line.long 0x0 "FILCLKSEL_B0P1T0,Chattering Prevention Clock Select Register B0P1T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x3AC++0x3 line.long 0x0 "FILCLKSEL_B0P1T1,Chattering Prevention Clock Select Register B0P1T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x5AC++0x3 line.long 0x0 "FILCLKSEL_B0P1T2,Chattering Prevention Clock Select Register B0P1T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x9AC++0x3 line.long 0x0 "FILCLKSEL_B0P2T0,Chattering Prevention Clock Select Register B0P2T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0xBAC++0x3 line.long 0x0 "FILCLKSEL_B0P2T1,Chattering Prevention Clock Select Register B0P2T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0xDAC++0x3 line.long 0x0 "FILCLKSEL_B0P2T2,Chattering Prevention Clock Select Register B0P2T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x21AC++0x3 line.long 0x0 "FILCLKSEL_B1P1T0,Chattering Prevention Clock Select Register B1P1T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x23AC++0x3 line.long 0x0 "FILCLKSEL_B1P1T1,Chattering Prevention Clock Select Register B1P1T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x25AC++0x3 line.long 0x0 "FILCLKSEL_B1P1T2,Chattering Prevention Clock Select Register B1P1T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x29AC++0x3 line.long 0x0 "FILCLKSEL_B1P2T0,Chattering Prevention Clock Select Register B1P2T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x2BAC++0x3 line.long 0x0 "FILCLKSEL_B1P2T1,Chattering Prevention Clock Select Register B1P2T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x2DAC++0x3 line.long 0x0 "FILCLKSEL_B1P2T2,Chattering Prevention Clock Select Register B1P2T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x41AC++0x3 line.long 0x0 "FILCLKSEL_B2P1T0,Chattering Prevention Clock Select Register B2P1T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x43AC++0x3 line.long 0x0 "FILCLKSEL_B2P1T1,Chattering Prevention Clock Select Register B2P1T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x45AC++0x3 line.long 0x0 "FILCLKSEL_B2P1T2,Chattering Prevention Clock Select Register B2P1T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x49AC++0x3 line.long 0x0 "FILCLKSEL_B2P2T0,Chattering Prevention Clock Select Register B2P2T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x4BAC++0x3 line.long 0x0 "FILCLKSEL_B2P2T1,Chattering Prevention Clock Select Register B2P2T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x4DAC++0x3 line.long 0x0 "FILCLKSEL_B2P2T2,Chattering Prevention Clock Select Register B2P2T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x61AC++0x3 line.long 0x0 "FILCLKSEL_B3P1T0,Chattering Prevention Clock Select Register B3P1T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x63AC++0x3 line.long 0x0 "FILCLKSEL_B3P1T1,Chattering Prevention Clock Select Register B3P1T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x65AC++0x3 line.long 0x0 "FILCLKSEL_B3P1T2,Chattering Prevention Clock Select Register B3P1T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x69AC++0x3 line.long 0x0 "FILCLKSEL_B3P2T0,Chattering Prevention Clock Select Register B3P2T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x6BAC++0x3 line.long 0x0 "FILCLKSEL_B3P2T1,Chattering Prevention Clock Select Register B3P2T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x6DAC++0x3 line.long 0x0 "FILCLKSEL_B3P2T2,Chattering Prevention Clock Select Register B3P2T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x1C0++0x3 line.long 0x0 "OUTDTSEL_B0P1T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x3C0++0x3 line.long 0x0 "OUTDTSEL_B0P1T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x5C0++0x3 line.long 0x0 "OUTDTSEL_B0P1T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x9C0++0x3 line.long 0x0 "OUTDTSEL_B0P2T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0xBC0++0x3 line.long 0x0 "OUTDTSEL_B0P2T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0xDC0++0x3 line.long 0x0 "OUTDTSEL_B0P2T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x21C0++0x3 line.long 0x0 "OUTDTSEL_B1P1T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x23C0++0x3 line.long 0x0 "OUTDTSEL_B1P1T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x25C0++0x3 line.long 0x0 "OUTDTSEL_B1P1T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x29C0++0x3 line.long 0x0 "OUTDTSEL_B1P2T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x2BC0++0x3 line.long 0x0 "OUTDTSEL_B1P2T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x2DC0++0x3 line.long 0x0 "OUTDTSEL_B1P2T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x41C0++0x3 line.long 0x0 "OUTDTSEL_B2P1T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x43C0++0x3 line.long 0x0 "OUTDTSEL_B2P1T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x45C0++0x3 line.long 0x0 "OUTDTSEL_B2P1T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x49C0++0x3 line.long 0x0 "OUTDTSEL_B2P2T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x4BC0++0x3 line.long 0x0 "OUTDTSEL_B2P2T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x4DC0++0x3 line.long 0x0 "OUTDTSEL_B2P2T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x61C0++0x3 line.long 0x0 "OUTDTSEL_B3P1T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x63C0++0x3 line.long 0x0 "OUTDTSEL_B3P1T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x65C0++0x3 line.long 0x0 "OUTDTSEL_B3P1T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x69C0++0x3 line.long 0x0 "OUTDTSEL_B3P2T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x6BC0++0x3 line.long 0x0 "OUTDTSEL_B3P2T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x6DC0++0x3 line.long 0x0 "OUTDTSEL_B3P2T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x1C4++0x3 line.long 0x0 "OUTDTH_B0P1T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x3C4++0x3 line.long 0x0 "OUTDTH_B0P1T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x5C4++0x3 line.long 0x0 "OUTDTH_B0P1T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x9C4++0x3 line.long 0x0 "OUTDTH_B0P2T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0xBC4++0x3 line.long 0x0 "OUTDTH_B0P2T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0xDC4++0x3 line.long 0x0 "OUTDTH_B0P2T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x21C4++0x3 line.long 0x0 "OUTDTH_B1P1T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x23C4++0x3 line.long 0x0 "OUTDTH_B1P1T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x25C4++0x3 line.long 0x0 "OUTDTH_B1P1T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x29C4++0x3 line.long 0x0 "OUTDTH_B1P2T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x2BC4++0x3 line.long 0x0 "OUTDTH_B1P2T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x2DC4++0x3 line.long 0x0 "OUTDTH_B1P2T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x41C4++0x3 line.long 0x0 "OUTDTH_B2P1T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x43C4++0x3 line.long 0x0 "OUTDTH_B2P1T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x45C4++0x3 line.long 0x0 "OUTDTH_B2P1T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x49C4++0x3 line.long 0x0 "OUTDTH_B2P2T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x4BC4++0x3 line.long 0x0 "OUTDTH_B2P2T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x4DC4++0x3 line.long 0x0 "OUTDTH_B2P2T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x61C4++0x3 line.long 0x0 "OUTDTH_B3P1T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x63C4++0x3 line.long 0x0 "OUTDTH_B3P1T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x65C4++0x3 line.long 0x0 "OUTDTH_B3P1T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x69C4++0x3 line.long 0x0 "OUTDTH_B3P2T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x6BC4++0x3 line.long 0x0 "OUTDTH_B3P2T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x6DC4++0x3 line.long 0x0 "OUTDTH_B3P2T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x1C8++0x3 line.long 0x0 "OUTDTL_B0P1T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x3C8++0x3 line.long 0x0 "OUTDTL_B0P1T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x5C8++0x3 line.long 0x0 "OUTDTL_B0P1T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x9C8++0x3 line.long 0x0 "OUTDTL_B0P2T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0xBC8++0x3 line.long 0x0 "OUTDTL_B0P2T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0xDC8++0x3 line.long 0x0 "OUTDTL_B0P2T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x21C8++0x3 line.long 0x0 "OUTDTL_B1P1T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x23C8++0x3 line.long 0x0 "OUTDTL_B1P1T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x25C8++0x3 line.long 0x0 "OUTDTL_B1P1T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x29C8++0x3 line.long 0x0 "OUTDTL_B1P2T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x2BC8++0x3 line.long 0x0 "OUTDTL_B1P2T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x2DC8++0x3 line.long 0x0 "OUTDTL_B1P2T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x41C8++0x3 line.long 0x0 "OUTDTL_B2P1T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x43C8++0x3 line.long 0x0 "OUTDTL_B2P1T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x45C8++0x3 line.long 0x0 "OUTDTL_B2P1T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x49C8++0x3 line.long 0x0 "OUTDTL_B2P2T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x4BC8++0x3 line.long 0x0 "OUTDTL_B2P2T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x4DC8++0x3 line.long 0x0 "OUTDTL_B2P2T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x61C8++0x3 line.long 0x0 "OUTDTL_B3P1T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x63C8++0x3 line.long 0x0 "OUTDTL_B3P1T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x65C8++0x3 line.long 0x0 "OUTDTL_B3P1T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x69C8++0x3 line.long 0x0 "OUTDTL_B3P2T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x6BC8++0x3 line.long 0x0 "OUTDTL_B3P2T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x6DC8++0x3 line.long 0x0 "OUTDTL_B3P2T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x1CC++0x3 line.long 0x0 "BOTHEDGE_B0P1T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x3CC++0x3 line.long 0x0 "BOTHEDGE_B0P1T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x5CC++0x3 line.long 0x0 "BOTHEDGE_B0P1T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x9CC++0x3 line.long 0x0 "BOTHEDGE_B0P2T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0xBCC++0x3 line.long 0x0 "BOTHEDGE_B0P2T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0xDCC++0x3 line.long 0x0 "BOTHEDGE_B0P2T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x21CC++0x3 line.long 0x0 "BOTHEDGE_B1P1T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x23CC++0x3 line.long 0x0 "BOTHEDGE_B1P1T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x25CC++0x3 line.long 0x0 "BOTHEDGE_B1P1T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x29CC++0x3 line.long 0x0 "BOTHEDGE_B1P2T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x2BCC++0x3 line.long 0x0 "BOTHEDGE_B1P2T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x2DCC++0x3 line.long 0x0 "BOTHEDGE_B1P2T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x41CC++0x3 line.long 0x0 "BOTHEDGE_B2P1T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x43CC++0x3 line.long 0x0 "BOTHEDGE_B2P1T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x45CC++0x3 line.long 0x0 "BOTHEDGE_B2P1T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x49CC++0x3 line.long 0x0 "BOTHEDGE_B2P2T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x4BCC++0x3 line.long 0x0 "BOTHEDGE_B2P2T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x4DCC++0x3 line.long 0x0 "BOTHEDGE_B2P2T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x61CC++0x3 line.long 0x0 "BOTHEDGE_B3P1T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x63CC++0x3 line.long 0x0 "BOTHEDGE_B3P1T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x65CC++0x3 line.long 0x0 "BOTHEDGE_B3P1T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x69CC++0x3 line.long 0x0 "BOTHEDGE_B3P2T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x6BCC++0x3 line.long 0x0 "BOTHEDGE_B3P2T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x6DCC++0x3 line.long 0x0 "BOTHEDGE_B3P2T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x1D0++0x3 line.long 0x0 "INEN_B0P1T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x3D0++0x3 line.long 0x0 "INEN_B0P1T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x5D0++0x3 line.long 0x0 "INEN_B0P1T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x9D0++0x3 line.long 0x0 "INEN_B0P2T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0xBD0++0x3 line.long 0x0 "INEN_B0P2T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0xDD0++0x3 line.long 0x0 "INEN_B0P2T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x21D0++0x3 line.long 0x0 "INEN_B1P1T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x23D0++0x3 line.long 0x0 "INEN_B1P1T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x25D0++0x3 line.long 0x0 "INEN_B1P1T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x29D0++0x3 line.long 0x0 "INEN_B1P2T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x2BD0++0x3 line.long 0x0 "INEN_B1P2T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x2DD0++0x3 line.long 0x0 "INEN_B1P2T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x41D0++0x3 line.long 0x0 "INEN_B2P1T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x43D0++0x3 line.long 0x0 "INEN_B2P1T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x45D0++0x3 line.long 0x0 "INEN_B2P1T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x49D0++0x3 line.long 0x0 "INEN_B2P2T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x4BD0++0x3 line.long 0x0 "INEN_B2P2T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x4DD0++0x3 line.long 0x0 "INEN_B2P2T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x61D0++0x3 line.long 0x0 "INEN_B3P1T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x63D0++0x3 line.long 0x0 "INEN_B3P1T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x65D0++0x3 line.long 0x0 "INEN_B3P1T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x69D0++0x3 line.long 0x0 "INEN_B3P2T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x6BD0++0x3 line.long 0x0 "INEN_B3P2T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x6DD0++0x3 line.long 0x0 "INEN_B3P2T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x88++0x3 line.long 0x0 "DRV2CTRL_B0P1T0,DRV Control Register2 B0P1T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x288++0x3 line.long 0x0 "DRV2CTRL_B0P1T1,DRV Control Register2 B0P1T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x488++0x3 line.long 0x0 "DRV2CTRL_B0P1T2,DRV Control Register2 B0P1T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x888++0x3 line.long 0x0 "DRV2CTRL_B0P2T0,DRV Control Register2 B0P2T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0xA88++0x3 line.long 0x0 "DRV2CTRL_B0P2T1,DRV Control Register2 B0P2T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0xC88++0x3 line.long 0x0 "DRV2CTRL_B0P2T2,DRV Control Register2 B0P2T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2088++0x3 line.long 0x0 "DRV2CTRL_B1P1T0,DRV Control Register2 B1P1T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2288++0x3 line.long 0x0 "DRV2CTRL_B1P1T1,DRV Control Register2 B1P1T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2488++0x3 line.long 0x0 "DRV2CTRL_B1P1T2,DRV Control Register2 B1P1T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2888++0x3 line.long 0x0 "DRV2CTRL_B1P2T0,DRV Control Register2 B1P2T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2A88++0x3 line.long 0x0 "DRV2CTRL_B1P2T1,DRV Control Register2 B1P2T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2C88++0x3 line.long 0x0 "DRV2CTRL_B1P2T2,DRV Control Register2 B1P2T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4088++0x3 line.long 0x0 "DRV2CTRL_B2P1T0,DRV Control Register2 B2P1T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4288++0x3 line.long 0x0 "DRV2CTRL_B2P1T1,DRV Control Register2 B2P1T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4488++0x3 line.long 0x0 "DRV2CTRL_B2P1T2,DRV Control Register2 B2P1T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4888++0x3 line.long 0x0 "DRV2CTRL_B2P2T0,DRV Control Register2 B2P2T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4A88++0x3 line.long 0x0 "DRV2CTRL_B2P2T1,DRV Control Register2 B2P2T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4C88++0x3 line.long 0x0 "DRV2CTRL_B2P2T2,DRV Control Register2 B2P2T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6088++0x3 line.long 0x0 "DRV2CTRL_B3P1T0,DRV Control Register2 B3P1T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6288++0x3 line.long 0x0 "DRV2CTRL_B3P1T1,DRV Control Register2 B3P1T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6488++0x3 line.long 0x0 "DRV2CTRL_B3P1T2,DRV Control Register2 B3P1T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6888++0x3 line.long 0x0 "DRV2CTRL_B3P2T0,DRV Control Register2 B3P2T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6A88++0x3 line.long 0x0 "DRV2CTRL_B3P2T1,DRV Control Register2 B3P2T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6C88++0x3 line.long 0x0 "DRV2CTRL_B3P2T2,DRV Control Register2 B3P2T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x8C++0x3 line.long 0x0 "DRV3CTRL_B0P1T0,DRV Control Register3 B0P1T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x28C++0x3 line.long 0x0 "DRV3CTRL_B0P1T1,DRV Control Register3 B0P1T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x48C++0x3 line.long 0x0 "DRV3CTRL_B0P1T2,DRV Control Register3 B0P1T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x88C++0x3 line.long 0x0 "DRV3CTRL_B0P2T0,DRV Control Register3 B0P2T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0xA8C++0x3 line.long 0x0 "DRV3CTRL_B0P2T1,DRV Control Register3 B0P2T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0xC8C++0x3 line.long 0x0 "DRV3CTRL_B0P2T2,DRV Control Register3 B0P2T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x208C++0x3 line.long 0x0 "DRV3CTRL_B1P1T0,DRV Control Register3 B1P1T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x228C++0x3 line.long 0x0 "DRV3CTRL_B1P1T1,DRV Control Register3 B1P1T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x248C++0x3 line.long 0x0 "DRV3CTRL_B1P1T2,DRV Control Register3 B1P1T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x288C++0x3 line.long 0x0 "DRV3CTRL_B1P2T0,DRV Control Register3 B1P2T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x2A8C++0x3 line.long 0x0 "DRV3CTRL_B1P2T1,DRV Control Register3 B1P2T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x2C8C++0x3 line.long 0x0 "DRV3CTRL_B1P2T2,DRV Control Register3 B1P2T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x408C++0x3 line.long 0x0 "DRV3CTRL_B2P1T0,DRV Control Register3 B2P1T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x428C++0x3 line.long 0x0 "DRV3CTRL_B2P1T1,DRV Control Register3 B2P1T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x448C++0x3 line.long 0x0 "DRV3CTRL_B2P1T2,DRV Control Register3 B2P1T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x488C++0x3 line.long 0x0 "DRV3CTRL_B2P2T0,DRV Control Register3 B2P2T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x4A8C++0x3 line.long 0x0 "DRV3CTRL_B2P2T1,DRV Control Register3 B2P2T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x4C8C++0x3 line.long 0x0 "DRV3CTRL_B2P2T2,DRV Control Register3 B2P2T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x608C++0x3 line.long 0x0 "DRV3CTRL_B3P1T0,DRV Control Register3 B3P1T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x628C++0x3 line.long 0x0 "DRV3CTRL_B3P1T1,DRV Control Register3 B3P1T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x648C++0x3 line.long 0x0 "DRV3CTRL_B3P1T2,DRV Control Register3 B3P1T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x688C++0x3 line.long 0x0 "DRV3CTRL_B3P2T0,DRV Control Register3 B3P2T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x6A8C++0x3 line.long 0x0 "DRV3CTRL_B3P2T1,DRV Control Register3 B3P2T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x6C8C++0x3 line.long 0x0 "DRV3CTRL_B3P2T2,DRV Control Register3 B3P2T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" tree.end tree "PFC_1" base ad:0xE6050000 group.long 0x0++0x3 line.long 0x0 "PMMR_B0P0T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x200++0x3 line.long 0x0 "PMMR_B0P0T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x400++0x3 line.long 0x0 "PMMR_B0P0T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x800++0x3 line.long 0x0 "PMMR_B0P3T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xA00++0x3 line.long 0x0 "PMMR_B0P3T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xC00++0x3 line.long 0x0 "PMMR_B0P3T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2000++0x3 line.long 0x0 "PMMR_B1P0T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2200++0x3 line.long 0x0 "PMMR_B1P0T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2400++0x3 line.long 0x0 "PMMR_B1P0T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2800++0x3 line.long 0x0 "PMMR_B1P3T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2A00++0x3 line.long 0x0 "PMMR_B1P3T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2C00++0x3 line.long 0x0 "PMMR_B1P3T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4000++0x3 line.long 0x0 "PMMR_B2P0T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4200++0x3 line.long 0x0 "PMMR_B2P0T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4400++0x3 line.long 0x0 "PMMR_B2P0T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4800++0x3 line.long 0x0 "PMMR_B2P3T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4A00++0x3 line.long 0x0 "PMMR_B2P3T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4C00++0x3 line.long 0x0 "PMMR_B2P3T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6000++0x3 line.long 0x0 "PMMR_B3P0T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6200++0x3 line.long 0x0 "PMMR_B3P0T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6400++0x3 line.long 0x0 "PMMR_B3P0T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6800++0x3 line.long 0x0 "PMMR_B3P3T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6A00++0x3 line.long 0x0 "PMMR_B3P3T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6C00++0x3 line.long 0x0 "PMMR_B3P3T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x40++0x3 line.long 0x0 "GPSR_B0P0T0,GPIO/Peripheral Function Select Register B0P0T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x240++0x3 line.long 0x0 "GPSR_B0P0T1,GPIO/Peripheral Function Select Register B0P0T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x440++0x3 line.long 0x0 "GPSR_B0P0T2,GPIO/Peripheral Function Select Register B0P0T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2040++0x3 line.long 0x0 "GPSR_B1P0T0,GPIO/Peripheral Function Select Register B1P0T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2240++0x3 line.long 0x0 "GPSR_B1P0T1,GPIO/Peripheral Function Select Register B1P0T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2440++0x3 line.long 0x0 "GPSR_B1P0T2,GPIO/Peripheral Function Select Register B1P0T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4040++0x3 line.long 0x0 "GPSR_B2P0T0,GPIO/Peripheral Function Select Register B2P0T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4240++0x3 line.long 0x0 "GPSR_B2P0T1,GPIO/Peripheral Function Select Register B2P0T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4440++0x3 line.long 0x0 "GPSR_B2P0T2,GPIO/Peripheral Function Select Register B2P0T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6040++0x3 line.long 0x0 "GPSR_B3P0T0,GPIO/Peripheral Function Select Register B3P0T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6240++0x3 line.long 0x0 "GPSR_B3P0T1,GPIO/Peripheral Function Select Register B3P0T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6440++0x3 line.long 0x0 "GPSR_B3P0T2,GPIO/Peripheral Function Select Register B3P0T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x60++0x3 line.long 0x0 "IP0SR_B0P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x260++0x3 line.long 0x0 "IP0SR_B0P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x460++0x3 line.long 0x0 "IP0SR_B0P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2060++0x3 line.long 0x0 "IP0SR_B1P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2260++0x3 line.long 0x0 "IP0SR_B1P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2460++0x3 line.long 0x0 "IP0SR_B1P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4060++0x3 line.long 0x0 "IP0SR_B2P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4260++0x3 line.long 0x0 "IP0SR_B2P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4460++0x3 line.long 0x0 "IP0SR_B2P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6060++0x3 line.long 0x0 "IP0SR_B3P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6260++0x3 line.long 0x0 "IP0SR_B3P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6460++0x3 line.long 0x0 "IP0SR_B3P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x64++0x3 line.long 0x0 "IP1SR_B0P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x264++0x3 line.long 0x0 "IP1SR_B0P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x464++0x3 line.long 0x0 "IP1SR_B0P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2064++0x3 line.long 0x0 "IP1SR_B1P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2264++0x3 line.long 0x0 "IP1SR_B1P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2464++0x3 line.long 0x0 "IP1SR_B1P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4064++0x3 line.long 0x0 "IP1SR_B2P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4264++0x3 line.long 0x0 "IP1SR_B2P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4464++0x3 line.long 0x0 "IP1SR_B2P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6064++0x3 line.long 0x0 "IP1SR_B3P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6264++0x3 line.long 0x0 "IP1SR_B3P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6464++0x3 line.long 0x0 "IP1SR_B3P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x68++0x3 line.long 0x0 "IP2SR_B0P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x268++0x3 line.long 0x0 "IP2SR_B0P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x468++0x3 line.long 0x0 "IP2SR_B0P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2068++0x3 line.long 0x0 "IP2SR_B1P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2268++0x3 line.long 0x0 "IP2SR_B1P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2468++0x3 line.long 0x0 "IP2SR_B1P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4068++0x3 line.long 0x0 "IP2SR_B2P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4268++0x3 line.long 0x0 "IP2SR_B2P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4468++0x3 line.long 0x0 "IP2SR_B2P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6068++0x3 line.long 0x0 "IP2SR_B3P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6268++0x3 line.long 0x0 "IP2SR_B3P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6468++0x3 line.long 0x0 "IP2SR_B3P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x80++0x3 line.long 0x0 "DRV0CTRL_B0P0T0,DRV Control Register0 B0P0T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x280++0x3 line.long 0x0 "DRV0CTRL_B0P0T1,DRV Control Register0 B0P0T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x480++0x3 line.long 0x0 "DRV0CTRL_B0P0T2,DRV Control Register0 B0P0T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2080++0x3 line.long 0x0 "DRV0CTRL_B1P0T0,DRV Control Register0 B1P0T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2280++0x3 line.long 0x0 "DRV0CTRL_B1P0T1,DRV Control Register0 B1P0T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2480++0x3 line.long 0x0 "DRV0CTRL_B1P0T2,DRV Control Register0 B1P0T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4080++0x3 line.long 0x0 "DRV0CTRL_B2P0T0,DRV Control Register0 B2P0T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4280++0x3 line.long 0x0 "DRV0CTRL_B2P0T1,DRV Control Register0 B2P0T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4480++0x3 line.long 0x0 "DRV0CTRL_B2P0T2,DRV Control Register0 B2P0T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6080++0x3 line.long 0x0 "DRV0CTRL_B3P0T0,DRV Control Register0 B3P0T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6280++0x3 line.long 0x0 "DRV0CTRL_B3P0T1,DRV Control Register0 B3P0T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6480++0x3 line.long 0x0 "DRV0CTRL_B3P0T2,DRV Control Register0 B3P0T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0xA0++0x3 line.long 0x0 "POC_B0P0T0,POC Control Register B0P0T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x2A0++0x3 line.long 0x0 "POC_B0P0T1,POC Control Register B0P0T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x4A0++0x3 line.long 0x0 "POC_B0P0T2,POC Control Register B0P0T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x20A0++0x3 line.long 0x0 "POC_B1P0T0,POC Control Register B1P0T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x22A0++0x3 line.long 0x0 "POC_B1P0T1,POC Control Register B1P0T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x24A0++0x3 line.long 0x0 "POC_B1P0T2,POC Control Register B1P0T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x40A0++0x3 line.long 0x0 "POC_B2P0T0,POC Control Register B2P0T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x42A0++0x3 line.long 0x0 "POC_B2P0T1,POC Control Register B2P0T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x44A0++0x3 line.long 0x0 "POC_B2P0T2,POC Control Register B2P0T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x60A0++0x3 line.long 0x0 "POC_B3P0T0,POC Control Register B3P0T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x62A0++0x3 line.long 0x0 "POC_B3P0T1,POC Control Register B3P0T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x64A0++0x3 line.long 0x0 "POC_B3P0T2,POC Control Register B3P0T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0xC0++0x3 line.long 0x0 "PUEN_B0P0T0,LSI Pin Pull-enable Register B0P0T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x2C0++0x3 line.long 0x0 "PUEN_B0P0T1,LSI Pin Pull-enable Register B0P0T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x4C0++0x3 line.long 0x0 "PUEN_B0P0T2,LSI Pin Pull-enable Register B0P0T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x20C0++0x3 line.long 0x0 "PUEN_B1P0T0,LSI Pin Pull-enable Register B1P0T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x22C0++0x3 line.long 0x0 "PUEN_B1P0T1,LSI Pin Pull-enable Register B1P0T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x24C0++0x3 line.long 0x0 "PUEN_B1P0T2,LSI Pin Pull-enable Register B1P0T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x40C0++0x3 line.long 0x0 "PUEN_B2P0T0,LSI Pin Pull-enable Register B2P0T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x42C0++0x3 line.long 0x0 "PUEN_B2P0T1,LSI Pin Pull-enable Register B2P0T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x44C0++0x3 line.long 0x0 "PUEN_B2P0T2,LSI Pin Pull-enable Register B2P0T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x60C0++0x3 line.long 0x0 "PUEN_B3P0T0,LSI Pin Pull-enable Register B3P0T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x62C0++0x3 line.long 0x0 "PUEN_B3P0T1,LSI Pin Pull-enable Register B3P0T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x64C0++0x3 line.long 0x0 "PUEN_B3P0T2,LSI Pin Pull-enable Register B3P0T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0xE0++0x3 line.long 0x0 "PUD_B0P0T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x2E0++0x3 line.long 0x0 "PUD_B0P0T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x4E0++0x3 line.long 0x0 "PUD_B0P0T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x20E0++0x3 line.long 0x0 "PUD_B1P0T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x22E0++0x3 line.long 0x0 "PUD_B1P0T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x24E0++0x3 line.long 0x0 "PUD_B1P0T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x40E0++0x3 line.long 0x0 "PUD_B2P0T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x42E0++0x3 line.long 0x0 "PUD_B2P0T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x44E0++0x3 line.long 0x0 "PUD_B2P0T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x60E0++0x3 line.long 0x0 "PUD_B3P0T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x62E0++0x3 line.long 0x0 "PUD_B3P0T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x64E0++0x3 line.long 0x0 "PUD_B3P0T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x0++0x3 line.long 0x0 "PMMR_B0P0T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x200++0x3 line.long 0x0 "PMMR_B0P0T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x400++0x3 line.long 0x0 "PMMR_B0P0T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x800++0x3 line.long 0x0 "PMMR_B0P3T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xA00++0x3 line.long 0x0 "PMMR_B0P3T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xC00++0x3 line.long 0x0 "PMMR_B0P3T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2000++0x3 line.long 0x0 "PMMR_B1P0T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2200++0x3 line.long 0x0 "PMMR_B1P0T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2400++0x3 line.long 0x0 "PMMR_B1P0T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2800++0x3 line.long 0x0 "PMMR_B1P3T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2A00++0x3 line.long 0x0 "PMMR_B1P3T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2C00++0x3 line.long 0x0 "PMMR_B1P3T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4000++0x3 line.long 0x0 "PMMR_B2P0T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4200++0x3 line.long 0x0 "PMMR_B2P0T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4400++0x3 line.long 0x0 "PMMR_B2P0T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4800++0x3 line.long 0x0 "PMMR_B2P3T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4A00++0x3 line.long 0x0 "PMMR_B2P3T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4C00++0x3 line.long 0x0 "PMMR_B2P3T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6000++0x3 line.long 0x0 "PMMR_B3P0T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6200++0x3 line.long 0x0 "PMMR_B3P0T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6400++0x3 line.long 0x0 "PMMR_B3P0T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6800++0x3 line.long 0x0 "PMMR_B3P3T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6A00++0x3 line.long 0x0 "PMMR_B3P3T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6C00++0x3 line.long 0x0 "PMMR_B3P3T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4++0x3 line.long 0x0 "PMMER_B0P0T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x204++0x3 line.long 0x0 "PMMER_B0P0T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x404++0x3 line.long 0x0 "PMMER_B0P0T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x804++0x3 line.long 0x0 "PMMER_B0P3T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0xA04++0x3 line.long 0x0 "PMMER_B0P3T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0xC04++0x3 line.long 0x0 "PMMER_B0P3T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2004++0x3 line.long 0x0 "PMMER_B1P0T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2204++0x3 line.long 0x0 "PMMER_B1P0T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2404++0x3 line.long 0x0 "PMMER_B1P0T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2804++0x3 line.long 0x0 "PMMER_B1P3T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2A04++0x3 line.long 0x0 "PMMER_B1P3T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2C04++0x3 line.long 0x0 "PMMER_B1P3T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4004++0x3 line.long 0x0 "PMMER_B2P0T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4204++0x3 line.long 0x0 "PMMER_B2P0T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4404++0x3 line.long 0x0 "PMMER_B2P0T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4804++0x3 line.long 0x0 "PMMER_B2P3T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4A04++0x3 line.long 0x0 "PMMER_B2P3T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4C04++0x3 line.long 0x0 "PMMER_B2P3T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6004++0x3 line.long 0x0 "PMMER_B3P0T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6204++0x3 line.long 0x0 "PMMER_B3P0T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6404++0x3 line.long 0x0 "PMMER_B3P0T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6804++0x3 line.long 0x0 "PMMER_B3P3T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6A04++0x3 line.long 0x0 "PMMER_B3P3T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6C04++0x3 line.long 0x0 "PMMER_B3P3T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x20++0x3 line.long 0x0 "DMPR0_B0P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x220++0x3 line.long 0x0 "DMPR0_B0P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x420++0x3 line.long 0x0 "DMPR0_B0P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x820++0x3 line.long 0x0 "DMPR0_B0P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA20++0x3 line.long 0x0 "DMPR0_B0P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC20++0x3 line.long 0x0 "DMPR0_B0P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2020++0x3 line.long 0x0 "DMPR0_B1P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2220++0x3 line.long 0x0 "DMPR0_B1P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2420++0x3 line.long 0x0 "DMPR0_B1P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2820++0x3 line.long 0x0 "DMPR0_B1P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A20++0x3 line.long 0x0 "DMPR0_B1P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C20++0x3 line.long 0x0 "DMPR0_B1P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4020++0x3 line.long 0x0 "DMPR0_B2P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4220++0x3 line.long 0x0 "DMPR0_B2P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4420++0x3 line.long 0x0 "DMPR0_B2P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4820++0x3 line.long 0x0 "DMPR0_B2P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A20++0x3 line.long 0x0 "DMPR0_B2P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C20++0x3 line.long 0x0 "DMPR0_B2P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6020++0x3 line.long 0x0 "DMPR0_B3P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6220++0x3 line.long 0x0 "DMPR0_B3P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6420++0x3 line.long 0x0 "DMPR0_B3P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6820++0x3 line.long 0x0 "DMPR0_B3P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A20++0x3 line.long 0x0 "DMPR0_B3P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C20++0x3 line.long 0x0 "DMPR0_B3P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x24++0x3 line.long 0x0 "DMPR1_B0P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x224++0x3 line.long 0x0 "DMPR1_B0P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x424++0x3 line.long 0x0 "DMPR1_B0P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x824++0x3 line.long 0x0 "DMPR1_B0P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA24++0x3 line.long 0x0 "DMPR1_B0P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC24++0x3 line.long 0x0 "DMPR1_B0P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2024++0x3 line.long 0x0 "DMPR1_B1P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2224++0x3 line.long 0x0 "DMPR1_B1P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2424++0x3 line.long 0x0 "DMPR1_B1P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2824++0x3 line.long 0x0 "DMPR1_B1P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A24++0x3 line.long 0x0 "DMPR1_B1P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C24++0x3 line.long 0x0 "DMPR1_B1P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4024++0x3 line.long 0x0 "DMPR1_B2P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4224++0x3 line.long 0x0 "DMPR1_B2P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4424++0x3 line.long 0x0 "DMPR1_B2P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4824++0x3 line.long 0x0 "DMPR1_B2P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A24++0x3 line.long 0x0 "DMPR1_B2P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C24++0x3 line.long 0x0 "DMPR1_B2P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6024++0x3 line.long 0x0 "DMPR1_B3P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6224++0x3 line.long 0x0 "DMPR1_B3P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6424++0x3 line.long 0x0 "DMPR1_B3P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6824++0x3 line.long 0x0 "DMPR1_B3P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A24++0x3 line.long 0x0 "DMPR1_B3P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C24++0x3 line.long 0x0 "DMPR1_B3P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x28++0x3 line.long 0x0 "DMPR2_B0P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x228++0x3 line.long 0x0 "DMPR2_B0P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x428++0x3 line.long 0x0 "DMPR2_B0P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x828++0x3 line.long 0x0 "DMPR2_B0P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA28++0x3 line.long 0x0 "DMPR2_B0P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC28++0x3 line.long 0x0 "DMPR2_B0P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2028++0x3 line.long 0x0 "DMPR2_B1P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2228++0x3 line.long 0x0 "DMPR2_B1P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2428++0x3 line.long 0x0 "DMPR2_B1P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2828++0x3 line.long 0x0 "DMPR2_B1P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A28++0x3 line.long 0x0 "DMPR2_B1P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C28++0x3 line.long 0x0 "DMPR2_B1P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4028++0x3 line.long 0x0 "DMPR2_B2P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4228++0x3 line.long 0x0 "DMPR2_B2P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4428++0x3 line.long 0x0 "DMPR2_B2P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4828++0x3 line.long 0x0 "DMPR2_B2P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A28++0x3 line.long 0x0 "DMPR2_B2P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C28++0x3 line.long 0x0 "DMPR2_B2P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6028++0x3 line.long 0x0 "DMPR2_B3P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6228++0x3 line.long 0x0 "DMPR2_B3P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6428++0x3 line.long 0x0 "DMPR2_B3P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6828++0x3 line.long 0x0 "DMPR2_B3P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A28++0x3 line.long 0x0 "DMPR2_B3P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C28++0x3 line.long 0x0 "DMPR2_B3P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C++0x3 line.long 0x0 "DMPR3_B0P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x22C++0x3 line.long 0x0 "DMPR3_B0P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x42C++0x3 line.long 0x0 "DMPR3_B0P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x82C++0x3 line.long 0x0 "DMPR3_B0P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA2C++0x3 line.long 0x0 "DMPR3_B0P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC2C++0x3 line.long 0x0 "DMPR3_B0P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x202C++0x3 line.long 0x0 "DMPR3_B1P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x222C++0x3 line.long 0x0 "DMPR3_B1P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x242C++0x3 line.long 0x0 "DMPR3_B1P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x282C++0x3 line.long 0x0 "DMPR3_B1P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A2C++0x3 line.long 0x0 "DMPR3_B1P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C2C++0x3 line.long 0x0 "DMPR3_B1P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x402C++0x3 line.long 0x0 "DMPR3_B2P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x422C++0x3 line.long 0x0 "DMPR3_B2P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x442C++0x3 line.long 0x0 "DMPR3_B2P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x482C++0x3 line.long 0x0 "DMPR3_B2P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A2C++0x3 line.long 0x0 "DMPR3_B2P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C2C++0x3 line.long 0x0 "DMPR3_B2P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x602C++0x3 line.long 0x0 "DMPR3_B3P0T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x622C++0x3 line.long 0x0 "DMPR3_B3P0T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x642C++0x3 line.long 0x0 "DMPR3_B3P0T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x682C++0x3 line.long 0x0 "DMPR3_B3P3T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A2C++0x3 line.long 0x0 "DMPR3_B3P3T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C2C++0x3 line.long 0x0 "DMPR3_B3P3T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C++0x3 line.long 0x0 "IP3SR_B0P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x26C++0x3 line.long 0x0 "IP3SR_B0P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x46C++0x3 line.long 0x0 "IP3SR_B0P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x86C++0x3 line.long 0x0 "IP3SR_B0P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xA6C++0x3 line.long 0x0 "IP3SR_B0P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xC6C++0x3 line.long 0x0 "IP3SR_B0P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x206C++0x3 line.long 0x0 "IP3SR_B1P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x226C++0x3 line.long 0x0 "IP3SR_B1P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x246C++0x3 line.long 0x0 "IP3SR_B1P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x286C++0x3 line.long 0x0 "IP3SR_B1P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2A6C++0x3 line.long 0x0 "IP3SR_B1P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2C6C++0x3 line.long 0x0 "IP3SR_B1P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x406C++0x3 line.long 0x0 "IP3SR_B2P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x426C++0x3 line.long 0x0 "IP3SR_B2P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x446C++0x3 line.long 0x0 "IP3SR_B2P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x486C++0x3 line.long 0x0 "IP3SR_B2P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4A6C++0x3 line.long 0x0 "IP3SR_B2P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4C6C++0x3 line.long 0x0 "IP3SR_B2P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x606C++0x3 line.long 0x0 "IP3SR_B3P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x626C++0x3 line.long 0x0 "IP3SR_B3P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x646C++0x3 line.long 0x0 "IP3SR_B3P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x686C++0x3 line.long 0x0 "IP3SR_B3P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6A6C++0x3 line.long 0x0 "IP3SR_B3P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6C6C++0x3 line.long 0x0 "IP3SR_B3P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x84++0x3 line.long 0x0 "DRV1CTRL_B0P0T0,DRV Control Register1 B0P0T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x284++0x3 line.long 0x0 "DRV1CTRL_B0P0T1,DRV Control Register1 B0P0T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x484++0x3 line.long 0x0 "DRV1CTRL_B0P0T2,DRV Control Register1 B0P0T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x884++0x3 line.long 0x0 "DRV1CTRL_B0P3T0,DRV Control Register1 B0P3T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0xA84++0x3 line.long 0x0 "DRV1CTRL_B0P3T1,DRV Control Register1 B0P3T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0xC84++0x3 line.long 0x0 "DRV1CTRL_B0P3T2,DRV Control Register1 B0P3T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2084++0x3 line.long 0x0 "DRV1CTRL_B1P0T0,DRV Control Register1 B1P0T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2284++0x3 line.long 0x0 "DRV1CTRL_B1P0T1,DRV Control Register1 B1P0T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2484++0x3 line.long 0x0 "DRV1CTRL_B1P0T2,DRV Control Register1 B1P0T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2884++0x3 line.long 0x0 "DRV1CTRL_B1P3T0,DRV Control Register1 B1P3T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2A84++0x3 line.long 0x0 "DRV1CTRL_B1P3T1,DRV Control Register1 B1P3T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2C84++0x3 line.long 0x0 "DRV1CTRL_B1P3T2,DRV Control Register1 B1P3T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4084++0x3 line.long 0x0 "DRV1CTRL_B2P0T0,DRV Control Register1 B2P0T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4284++0x3 line.long 0x0 "DRV1CTRL_B2P0T1,DRV Control Register1 B2P0T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4484++0x3 line.long 0x0 "DRV1CTRL_B2P0T2,DRV Control Register1 B2P0T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4884++0x3 line.long 0x0 "DRV1CTRL_B2P3T0,DRV Control Register1 B2P3T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4A84++0x3 line.long 0x0 "DRV1CTRL_B2P3T1,DRV Control Register1 B2P3T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4C84++0x3 line.long 0x0 "DRV1CTRL_B2P3T2,DRV Control Register1 B2P3T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6084++0x3 line.long 0x0 "DRV1CTRL_B3P0T0,DRV Control Register1 B3P0T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6284++0x3 line.long 0x0 "DRV1CTRL_B3P0T1,DRV Control Register1 B3P0T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6484++0x3 line.long 0x0 "DRV1CTRL_B3P0T2,DRV Control Register1 B3P0T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6884++0x3 line.long 0x0 "DRV1CTRL_B3P3T0,DRV Control Register1 B3P3T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6A84++0x3 line.long 0x0 "DRV1CTRL_B3P3T1,DRV Control Register1 B3P3T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6C84++0x3 line.long 0x0 "DRV1CTRL_B3P3T2,DRV Control Register1 B3P3T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x100++0x3 line.long 0x0 "MODSEL_B0P0T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x300++0x3 line.long 0x0 "MODSEL_B0P0T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x500++0x3 line.long 0x0 "MODSEL_B0P0T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x900++0x3 line.long 0x0 "MODSEL_B0P3T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0xB00++0x3 line.long 0x0 "MODSEL_B0P3T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0xD00++0x3 line.long 0x0 "MODSEL_B0P3T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2100++0x3 line.long 0x0 "MODSEL_B1P0T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2300++0x3 line.long 0x0 "MODSEL_B1P0T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2500++0x3 line.long 0x0 "MODSEL_B1P0T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2900++0x3 line.long 0x0 "MODSEL_B1P3T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2B00++0x3 line.long 0x0 "MODSEL_B1P3T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2D00++0x3 line.long 0x0 "MODSEL_B1P3T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4100++0x3 line.long 0x0 "MODSEL_B2P0T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4300++0x3 line.long 0x0 "MODSEL_B2P0T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4500++0x3 line.long 0x0 "MODSEL_B2P0T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4900++0x3 line.long 0x0 "MODSEL_B2P3T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4B00++0x3 line.long 0x0 "MODSEL_B2P3T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4D00++0x3 line.long 0x0 "MODSEL_B2P3T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6100++0x3 line.long 0x0 "MODSEL_B3P0T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6300++0x3 line.long 0x0 "MODSEL_B3P0T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6500++0x3 line.long 0x0 "MODSEL_B3P0T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6900++0x3 line.long 0x0 "MODSEL_B3P3T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6B00++0x3 line.long 0x0 "MODSEL_B3P3T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6D00++0x3 line.long 0x0 "MODSEL_B3P3T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x120++0x3 line.long 0x0 "TD0SEL_B0P0T0,TDSEL Control Register0 B0P0T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x320++0x3 line.long 0x0 "TD0SEL_B0P0T1,TDSEL Control Register0 B0P0T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x520++0x3 line.long 0x0 "TD0SEL_B0P0T2,TDSEL Control Register0 B0P0T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x920++0x3 line.long 0x0 "TD0SEL_B0P3T0,TDSEL Control Register0 B0P3T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0xB20++0x3 line.long 0x0 "TD0SEL_B0P3T1,TDSEL Control Register0 B0P3T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0xD20++0x3 line.long 0x0 "TD0SEL_B0P3T2,TDSEL Control Register0 B0P3T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2120++0x3 line.long 0x0 "TD0SEL_B1P0T0,TDSEL Control Register0 B1P0T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2320++0x3 line.long 0x0 "TD0SEL_B1P0T1,TDSEL Control Register0 B1P0T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2520++0x3 line.long 0x0 "TD0SEL_B1P0T2,TDSEL Control Register0 B1P0T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2920++0x3 line.long 0x0 "TD0SEL_B1P3T0,TDSEL Control Register0 B1P3T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2B20++0x3 line.long 0x0 "TD0SEL_B1P3T1,TDSEL Control Register0 B1P3T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2D20++0x3 line.long 0x0 "TD0SEL_B1P3T2,TDSEL Control Register0 B1P3T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4120++0x3 line.long 0x0 "TD0SEL_B2P0T0,TDSEL Control Register0 B2P0T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4320++0x3 line.long 0x0 "TD0SEL_B2P0T1,TDSEL Control Register0 B2P0T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4520++0x3 line.long 0x0 "TD0SEL_B2P0T2,TDSEL Control Register0 B2P0T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4920++0x3 line.long 0x0 "TD0SEL_B2P3T0,TDSEL Control Register0 B2P3T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4B20++0x3 line.long 0x0 "TD0SEL_B2P3T1,TDSEL Control Register0 B2P3T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4D20++0x3 line.long 0x0 "TD0SEL_B2P3T2,TDSEL Control Register0 B2P3T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6120++0x3 line.long 0x0 "TD0SEL_B3P0T0,TDSEL Control Register0 B3P0T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6320++0x3 line.long 0x0 "TD0SEL_B3P0T1,TDSEL Control Register0 B3P0T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6520++0x3 line.long 0x0 "TD0SEL_B3P0T2,TDSEL Control Register0 B3P0T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6920++0x3 line.long 0x0 "TD0SEL_B3P3T0,TDSEL Control Register0 B3P3T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6B20++0x3 line.long 0x0 "TD0SEL_B3P3T1,TDSEL Control Register0 B3P3T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6D20++0x3 line.long 0x0 "TD0SEL_B3P3T2,TDSEL Control Register0 B3P3T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x124++0x3 line.long 0x0 "TD1SEL_B0P0T0,TDSEL Control Register1 B0P0T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x324++0x3 line.long 0x0 "TD1SEL_B0P0T1,TDSEL Control Register1 B0P0T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x524++0x3 line.long 0x0 "TD1SEL_B0P0T2,TDSEL Control Register1 B0P0T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x924++0x3 line.long 0x0 "TD1SEL_B0P3T0,TDSEL Control Register1 B0P3T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0xB24++0x3 line.long 0x0 "TD1SEL_B0P3T1,TDSEL Control Register1 B0P3T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0xD24++0x3 line.long 0x0 "TD1SEL_B0P3T2,TDSEL Control Register1 B0P3T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2124++0x3 line.long 0x0 "TD1SEL_B1P0T0,TDSEL Control Register1 B1P0T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2324++0x3 line.long 0x0 "TD1SEL_B1P0T1,TDSEL Control Register1 B1P0T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2524++0x3 line.long 0x0 "TD1SEL_B1P0T2,TDSEL Control Register1 B1P0T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2924++0x3 line.long 0x0 "TD1SEL_B1P3T0,TDSEL Control Register1 B1P3T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2B24++0x3 line.long 0x0 "TD1SEL_B1P3T1,TDSEL Control Register1 B1P3T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2D24++0x3 line.long 0x0 "TD1SEL_B1P3T2,TDSEL Control Register1 B1P3T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4124++0x3 line.long 0x0 "TD1SEL_B2P0T0,TDSEL Control Register1 B2P0T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4324++0x3 line.long 0x0 "TD1SEL_B2P0T1,TDSEL Control Register1 B2P0T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4524++0x3 line.long 0x0 "TD1SEL_B2P0T2,TDSEL Control Register1 B2P0T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4924++0x3 line.long 0x0 "TD1SEL_B2P3T0,TDSEL Control Register1 B2P3T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4B24++0x3 line.long 0x0 "TD1SEL_B2P3T1,TDSEL Control Register1 B2P3T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4D24++0x3 line.long 0x0 "TD1SEL_B2P3T2,TDSEL Control Register1 B2P3T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6124++0x3 line.long 0x0 "TD1SEL_B3P0T0,TDSEL Control Register1 B3P0T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6324++0x3 line.long 0x0 "TD1SEL_B3P0T1,TDSEL Control Register1 B3P0T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6524++0x3 line.long 0x0 "TD1SEL_B3P0T2,TDSEL Control Register1 B3P0T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6924++0x3 line.long 0x0 "TD1SEL_B3P3T0,TDSEL Control Register1 B3P3T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6B24++0x3 line.long 0x0 "TD1SEL_B3P3T1,TDSEL Control Register1 B3P3T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6D24++0x3 line.long 0x0 "TD1SEL_B3P3T2,TDSEL Control Register1 B3P3T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x140++0x3 line.long 0x0 "BIPSR0_B0P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x340++0x3 line.long 0x0 "BIPSR0_B0P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x540++0x3 line.long 0x0 "BIPSR0_B0P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x940++0x3 line.long 0x0 "BIPSR0_B0P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB40++0x3 line.long 0x0 "BIPSR0_B0P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD40++0x3 line.long 0x0 "BIPSR0_B0P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2140++0x3 line.long 0x0 "BIPSR0_B1P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2340++0x3 line.long 0x0 "BIPSR0_B1P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2540++0x3 line.long 0x0 "BIPSR0_B1P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2940++0x3 line.long 0x0 "BIPSR0_B1P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B40++0x3 line.long 0x0 "BIPSR0_B1P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D40++0x3 line.long 0x0 "BIPSR0_B1P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4140++0x3 line.long 0x0 "BIPSR0_B2P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4340++0x3 line.long 0x0 "BIPSR0_B2P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4540++0x3 line.long 0x0 "BIPSR0_B2P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4940++0x3 line.long 0x0 "BIPSR0_B2P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B40++0x3 line.long 0x0 "BIPSR0_B2P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D40++0x3 line.long 0x0 "BIPSR0_B2P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6140++0x3 line.long 0x0 "BIPSR0_B3P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6340++0x3 line.long 0x0 "BIPSR0_B3P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6540++0x3 line.long 0x0 "BIPSR0_B3P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6940++0x3 line.long 0x0 "BIPSR0_B3P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B40++0x3 line.long 0x0 "BIPSR0_B3P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D40++0x3 line.long 0x0 "BIPSR0_B3P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x144++0x3 line.long 0x0 "BIPSR1_B0P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x344++0x3 line.long 0x0 "BIPSR1_B0P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x544++0x3 line.long 0x0 "BIPSR1_B0P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x944++0x3 line.long 0x0 "BIPSR1_B0P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB44++0x3 line.long 0x0 "BIPSR1_B0P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD44++0x3 line.long 0x0 "BIPSR1_B0P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2144++0x3 line.long 0x0 "BIPSR1_B1P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2344++0x3 line.long 0x0 "BIPSR1_B1P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2544++0x3 line.long 0x0 "BIPSR1_B1P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2944++0x3 line.long 0x0 "BIPSR1_B1P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B44++0x3 line.long 0x0 "BIPSR1_B1P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D44++0x3 line.long 0x0 "BIPSR1_B1P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4144++0x3 line.long 0x0 "BIPSR1_B2P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4344++0x3 line.long 0x0 "BIPSR1_B2P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4544++0x3 line.long 0x0 "BIPSR1_B2P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4944++0x3 line.long 0x0 "BIPSR1_B2P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B44++0x3 line.long 0x0 "BIPSR1_B2P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D44++0x3 line.long 0x0 "BIPSR1_B2P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6144++0x3 line.long 0x0 "BIPSR1_B3P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6344++0x3 line.long 0x0 "BIPSR1_B3P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6544++0x3 line.long 0x0 "BIPSR1_B3P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6944++0x3 line.long 0x0 "BIPSR1_B3P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B44++0x3 line.long 0x0 "BIPSR1_B3P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D44++0x3 line.long 0x0 "BIPSR1_B3P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x148++0x3 line.long 0x0 "BIPSR2_B0P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x348++0x3 line.long 0x0 "BIPSR2_B0P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x548++0x3 line.long 0x0 "BIPSR2_B0P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x948++0x3 line.long 0x0 "BIPSR2_B0P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB48++0x3 line.long 0x0 "BIPSR2_B0P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD48++0x3 line.long 0x0 "BIPSR2_B0P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2148++0x3 line.long 0x0 "BIPSR2_B1P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2348++0x3 line.long 0x0 "BIPSR2_B1P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2548++0x3 line.long 0x0 "BIPSR2_B1P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2948++0x3 line.long 0x0 "BIPSR2_B1P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B48++0x3 line.long 0x0 "BIPSR2_B1P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D48++0x3 line.long 0x0 "BIPSR2_B1P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4148++0x3 line.long 0x0 "BIPSR2_B2P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4348++0x3 line.long 0x0 "BIPSR2_B2P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4548++0x3 line.long 0x0 "BIPSR2_B2P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4948++0x3 line.long 0x0 "BIPSR2_B2P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B48++0x3 line.long 0x0 "BIPSR2_B2P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D48++0x3 line.long 0x0 "BIPSR2_B2P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6148++0x3 line.long 0x0 "BIPSR2_B3P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6348++0x3 line.long 0x0 "BIPSR2_B3P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6548++0x3 line.long 0x0 "BIPSR2_B3P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6948++0x3 line.long 0x0 "BIPSR2_B3P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B48++0x3 line.long 0x0 "BIPSR2_B3P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D48++0x3 line.long 0x0 "BIPSR2_B3P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x14C++0x3 line.long 0x0 "BIPSR3_B0P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x34C++0x3 line.long 0x0 "BIPSR3_B0P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x54C++0x3 line.long 0x0 "BIPSR3_B0P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x94C++0x3 line.long 0x0 "BIPSR3_B0P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB4C++0x3 line.long 0x0 "BIPSR3_B0P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD4C++0x3 line.long 0x0 "BIPSR3_B0P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x214C++0x3 line.long 0x0 "BIPSR3_B1P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x234C++0x3 line.long 0x0 "BIPSR3_B1P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x254C++0x3 line.long 0x0 "BIPSR3_B1P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x294C++0x3 line.long 0x0 "BIPSR3_B1P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B4C++0x3 line.long 0x0 "BIPSR3_B1P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D4C++0x3 line.long 0x0 "BIPSR3_B1P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x414C++0x3 line.long 0x0 "BIPSR3_B2P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x434C++0x3 line.long 0x0 "BIPSR3_B2P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x454C++0x3 line.long 0x0 "BIPSR3_B2P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x494C++0x3 line.long 0x0 "BIPSR3_B2P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B4C++0x3 line.long 0x0 "BIPSR3_B2P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D4C++0x3 line.long 0x0 "BIPSR3_B2P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x614C++0x3 line.long 0x0 "BIPSR3_B3P0T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x634C++0x3 line.long 0x0 "BIPSR3_B3P0T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x654C++0x3 line.long 0x0 "BIPSR3_B3P0T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x694C++0x3 line.long 0x0 "BIPSR3_B3P3T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B4C++0x3 line.long 0x0 "BIPSR3_B3P3T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D4C++0x3 line.long 0x0 "BIPSR3_B3P3T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x160++0x3 line.long 0x0 "PSER_B0P0T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x360++0x3 line.long 0x0 "PSER_B0P0T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x560++0x3 line.long 0x0 "PSER_B0P0T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x960++0x3 line.long 0x0 "PSER_B0P3T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0xB60++0x3 line.long 0x0 "PSER_B0P3T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0xD60++0x3 line.long 0x0 "PSER_B0P3T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2160++0x3 line.long 0x0 "PSER_B1P0T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2360++0x3 line.long 0x0 "PSER_B1P0T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2560++0x3 line.long 0x0 "PSER_B1P0T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2960++0x3 line.long 0x0 "PSER_B1P3T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2B60++0x3 line.long 0x0 "PSER_B1P3T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2D60++0x3 line.long 0x0 "PSER_B1P3T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4160++0x3 line.long 0x0 "PSER_B2P0T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4360++0x3 line.long 0x0 "PSER_B2P0T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4560++0x3 line.long 0x0 "PSER_B2P0T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4960++0x3 line.long 0x0 "PSER_B2P3T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4B60++0x3 line.long 0x0 "PSER_B2P3T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4D60++0x3 line.long 0x0 "PSER_B2P3T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6160++0x3 line.long 0x0 "PSER_B3P0T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6360++0x3 line.long 0x0 "PSER_B3P0T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6560++0x3 line.long 0x0 "PSER_B3P0T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6960++0x3 line.long 0x0 "PSER_B3P3T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6B60++0x3 line.long 0x0 "PSER_B3P3T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6D60++0x3 line.long 0x0 "PSER_B3P3T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x164++0x3 line.long 0x0 "PS0SR_B0P0T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x364++0x3 line.long 0x0 "PS0SR_B0P0T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x564++0x3 line.long 0x0 "PS0SR_B0P0T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x964++0x3 line.long 0x0 "PS0SR_B0P3T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0xB64++0x3 line.long 0x0 "PS0SR_B0P3T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0xD64++0x3 line.long 0x0 "PS0SR_B0P3T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2164++0x3 line.long 0x0 "PS0SR_B1P0T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2364++0x3 line.long 0x0 "PS0SR_B1P0T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2564++0x3 line.long 0x0 "PS0SR_B1P0T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2964++0x3 line.long 0x0 "PS0SR_B1P3T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2B64++0x3 line.long 0x0 "PS0SR_B1P3T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2D64++0x3 line.long 0x0 "PS0SR_B1P3T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4164++0x3 line.long 0x0 "PS0SR_B2P0T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4364++0x3 line.long 0x0 "PS0SR_B2P0T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4564++0x3 line.long 0x0 "PS0SR_B2P0T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4964++0x3 line.long 0x0 "PS0SR_B2P3T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4B64++0x3 line.long 0x0 "PS0SR_B2P3T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4D64++0x3 line.long 0x0 "PS0SR_B2P3T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6164++0x3 line.long 0x0 "PS0SR_B3P0T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6364++0x3 line.long 0x0 "PS0SR_B3P0T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6564++0x3 line.long 0x0 "PS0SR_B3P0T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6964++0x3 line.long 0x0 "PS0SR_B3P3T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6B64++0x3 line.long 0x0 "PS0SR_B3P3T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6D64++0x3 line.long 0x0 "PS0SR_B3P3T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x168++0x3 line.long 0x0 "PS1SR_B0P0T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x368++0x3 line.long 0x0 "PS1SR_B0P0T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x568++0x3 line.long 0x0 "PS1SR_B0P0T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x968++0x3 line.long 0x0 "PS1SR_B0P3T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0xB68++0x3 line.long 0x0 "PS1SR_B0P3T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0xD68++0x3 line.long 0x0 "PS1SR_B0P3T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2168++0x3 line.long 0x0 "PS1SR_B1P0T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2368++0x3 line.long 0x0 "PS1SR_B1P0T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2568++0x3 line.long 0x0 "PS1SR_B1P0T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2968++0x3 line.long 0x0 "PS1SR_B1P3T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2B68++0x3 line.long 0x0 "PS1SR_B1P3T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2D68++0x3 line.long 0x0 "PS1SR_B1P3T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4168++0x3 line.long 0x0 "PS1SR_B2P0T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4368++0x3 line.long 0x0 "PS1SR_B2P0T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4568++0x3 line.long 0x0 "PS1SR_B2P0T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4968++0x3 line.long 0x0 "PS1SR_B2P3T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4B68++0x3 line.long 0x0 "PS1SR_B2P3T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4D68++0x3 line.long 0x0 "PS1SR_B2P3T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6168++0x3 line.long 0x0 "PS1SR_B3P0T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6368++0x3 line.long 0x0 "PS1SR_B3P0T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6568++0x3 line.long 0x0 "PS1SR_B3P0T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6968++0x3 line.long 0x0 "PS1SR_B3P3T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6B68++0x3 line.long 0x0 "PS1SR_B3P3T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6D68++0x3 line.long 0x0 "PS1SR_B3P3T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x180++0x3 line.long 0x0 "IOINTSEL_B0P0T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x380++0x3 line.long 0x0 "IOINTSEL_B0P0T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x580++0x3 line.long 0x0 "IOINTSEL_B0P0T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x980++0x3 line.long 0x0 "IOINTSEL_B0P3T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0xB80++0x3 line.long 0x0 "IOINTSEL_B0P3T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0xD80++0x3 line.long 0x0 "IOINTSEL_B0P3T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2180++0x3 line.long 0x0 "IOINTSEL_B1P0T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2380++0x3 line.long 0x0 "IOINTSEL_B1P0T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2580++0x3 line.long 0x0 "IOINTSEL_B1P0T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2980++0x3 line.long 0x0 "IOINTSEL_B1P3T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2B80++0x3 line.long 0x0 "IOINTSEL_B1P3T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2D80++0x3 line.long 0x0 "IOINTSEL_B1P3T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4180++0x3 line.long 0x0 "IOINTSEL_B2P0T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4380++0x3 line.long 0x0 "IOINTSEL_B2P0T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4580++0x3 line.long 0x0 "IOINTSEL_B2P0T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4980++0x3 line.long 0x0 "IOINTSEL_B2P3T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4B80++0x3 line.long 0x0 "IOINTSEL_B2P3T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4D80++0x3 line.long 0x0 "IOINTSEL_B2P3T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6180++0x3 line.long 0x0 "IOINTSEL_B3P0T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6380++0x3 line.long 0x0 "IOINTSEL_B3P0T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6580++0x3 line.long 0x0 "IOINTSEL_B3P0T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6980++0x3 line.long 0x0 "IOINTSEL_B3P3T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6B80++0x3 line.long 0x0 "IOINTSEL_B3P3T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6D80++0x3 line.long 0x0 "IOINTSEL_B3P3T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x184++0x3 line.long 0x0 "INOUTSEL_B0P0T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x384++0x3 line.long 0x0 "INOUTSEL_B0P0T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x584++0x3 line.long 0x0 "INOUTSEL_B0P0T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x984++0x3 line.long 0x0 "INOUTSEL_B0P3T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0xB84++0x3 line.long 0x0 "INOUTSEL_B0P3T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0xD84++0x3 line.long 0x0 "INOUTSEL_B0P3T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2184++0x3 line.long 0x0 "INOUTSEL_B1P0T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2384++0x3 line.long 0x0 "INOUTSEL_B1P0T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2584++0x3 line.long 0x0 "INOUTSEL_B1P0T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2984++0x3 line.long 0x0 "INOUTSEL_B1P3T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2B84++0x3 line.long 0x0 "INOUTSEL_B1P3T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2D84++0x3 line.long 0x0 "INOUTSEL_B1P3T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4184++0x3 line.long 0x0 "INOUTSEL_B2P0T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4384++0x3 line.long 0x0 "INOUTSEL_B2P0T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4584++0x3 line.long 0x0 "INOUTSEL_B2P0T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4984++0x3 line.long 0x0 "INOUTSEL_B2P3T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4B84++0x3 line.long 0x0 "INOUTSEL_B2P3T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4D84++0x3 line.long 0x0 "INOUTSEL_B2P3T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6184++0x3 line.long 0x0 "INOUTSEL_B3P0T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6384++0x3 line.long 0x0 "INOUTSEL_B3P0T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6584++0x3 line.long 0x0 "INOUTSEL_B3P0T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6984++0x3 line.long 0x0 "INOUTSEL_B3P3T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6B84++0x3 line.long 0x0 "INOUTSEL_B3P3T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6D84++0x3 line.long 0x0 "INOUTSEL_B3P3T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x188++0x3 line.long 0x0 "OUTDT_B0P0T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x388++0x3 line.long 0x0 "OUTDT_B0P0T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x588++0x3 line.long 0x0 "OUTDT_B0P0T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x988++0x3 line.long 0x0 "OUTDT_B0P3T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0xB88++0x3 line.long 0x0 "OUTDT_B0P3T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0xD88++0x3 line.long 0x0 "OUTDT_B0P3T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2188++0x3 line.long 0x0 "OUTDT_B1P0T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2388++0x3 line.long 0x0 "OUTDT_B1P0T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2588++0x3 line.long 0x0 "OUTDT_B1P0T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2988++0x3 line.long 0x0 "OUTDT_B1P3T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2B88++0x3 line.long 0x0 "OUTDT_B1P3T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2D88++0x3 line.long 0x0 "OUTDT_B1P3T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4188++0x3 line.long 0x0 "OUTDT_B2P0T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4388++0x3 line.long 0x0 "OUTDT_B2P0T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4588++0x3 line.long 0x0 "OUTDT_B2P0T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4988++0x3 line.long 0x0 "OUTDT_B2P3T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4B88++0x3 line.long 0x0 "OUTDT_B2P3T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4D88++0x3 line.long 0x0 "OUTDT_B2P3T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6188++0x3 line.long 0x0 "OUTDT_B3P0T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6388++0x3 line.long 0x0 "OUTDT_B3P0T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6588++0x3 line.long 0x0 "OUTDT_B3P0T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6988++0x3 line.long 0x0 "OUTDT_B3P3T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6B88++0x3 line.long 0x0 "OUTDT_B3P3T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6D88++0x3 line.long 0x0 "OUTDT_B3P3T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." rgroup.long 0x18C++0x3 line.long 0x0 "INDT_B0P0T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x38C++0x3 line.long 0x0 "INDT_B0P0T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x58C++0x3 line.long 0x0 "INDT_B0P0T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x98C++0x3 line.long 0x0 "INDT_B0P3T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0xB8C++0x3 line.long 0x0 "INDT_B0P3T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0xD8C++0x3 line.long 0x0 "INDT_B0P3T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x218C++0x3 line.long 0x0 "INDT_B1P0T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x238C++0x3 line.long 0x0 "INDT_B1P0T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x258C++0x3 line.long 0x0 "INDT_B1P0T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x298C++0x3 line.long 0x0 "INDT_B1P3T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x2B8C++0x3 line.long 0x0 "INDT_B1P3T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x2D8C++0x3 line.long 0x0 "INDT_B1P3T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x418C++0x3 line.long 0x0 "INDT_B2P0T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x438C++0x3 line.long 0x0 "INDT_B2P0T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x458C++0x3 line.long 0x0 "INDT_B2P0T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x498C++0x3 line.long 0x0 "INDT_B2P3T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x4B8C++0x3 line.long 0x0 "INDT_B2P3T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x4D8C++0x3 line.long 0x0 "INDT_B2P3T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x618C++0x3 line.long 0x0 "INDT_B3P0T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x638C++0x3 line.long 0x0 "INDT_B3P0T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x658C++0x3 line.long 0x0 "INDT_B3P0T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x698C++0x3 line.long 0x0 "INDT_B3P3T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x6B8C++0x3 line.long 0x0 "INDT_B3P3T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x6D8C++0x3 line.long 0x0 "INDT_B3P3T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x190++0x3 line.long 0x0 "INTDT_B0P0T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x390++0x3 line.long 0x0 "INTDT_B0P0T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x590++0x3 line.long 0x0 "INTDT_B0P0T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x990++0x3 line.long 0x0 "INTDT_B0P3T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0xB90++0x3 line.long 0x0 "INTDT_B0P3T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0xD90++0x3 line.long 0x0 "INTDT_B0P3T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2190++0x3 line.long 0x0 "INTDT_B1P0T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2390++0x3 line.long 0x0 "INTDT_B1P0T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2590++0x3 line.long 0x0 "INTDT_B1P0T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2990++0x3 line.long 0x0 "INTDT_B1P3T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2B90++0x3 line.long 0x0 "INTDT_B1P3T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2D90++0x3 line.long 0x0 "INTDT_B1P3T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4190++0x3 line.long 0x0 "INTDT_B2P0T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4390++0x3 line.long 0x0 "INTDT_B2P0T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4590++0x3 line.long 0x0 "INTDT_B2P0T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4990++0x3 line.long 0x0 "INTDT_B2P3T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4B90++0x3 line.long 0x0 "INTDT_B2P3T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4D90++0x3 line.long 0x0 "INTDT_B2P3T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6190++0x3 line.long 0x0 "INTDT_B3P0T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6390++0x3 line.long 0x0 "INTDT_B3P0T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6590++0x3 line.long 0x0 "INTDT_B3P0T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6990++0x3 line.long 0x0 "INTDT_B3P3T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6B90++0x3 line.long 0x0 "INTDT_B3P3T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6D90++0x3 line.long 0x0 "INTDT_B3P3T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." group.long 0x194++0x3 line.long 0x0 "INTCLR_B0P0T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x394++0x3 line.long 0x0 "INTCLR_B0P0T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x594++0x3 line.long 0x0 "INTCLR_B0P0T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x994++0x3 line.long 0x0 "INTCLR_B0P3T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0xB94++0x3 line.long 0x0 "INTCLR_B0P3T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0xD94++0x3 line.long 0x0 "INTCLR_B0P3T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2194++0x3 line.long 0x0 "INTCLR_B1P0T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2394++0x3 line.long 0x0 "INTCLR_B1P0T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2594++0x3 line.long 0x0 "INTCLR_B1P0T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2994++0x3 line.long 0x0 "INTCLR_B1P3T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2B94++0x3 line.long 0x0 "INTCLR_B1P3T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2D94++0x3 line.long 0x0 "INTCLR_B1P3T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4194++0x3 line.long 0x0 "INTCLR_B2P0T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4394++0x3 line.long 0x0 "INTCLR_B2P0T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4594++0x3 line.long 0x0 "INTCLR_B2P0T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4994++0x3 line.long 0x0 "INTCLR_B2P3T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4B94++0x3 line.long 0x0 "INTCLR_B2P3T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4D94++0x3 line.long 0x0 "INTCLR_B2P3T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6194++0x3 line.long 0x0 "INTCLR_B3P0T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6394++0x3 line.long 0x0 "INTCLR_B3P0T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6594++0x3 line.long 0x0 "INTCLR_B3P0T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6994++0x3 line.long 0x0 "INTCLR_B3P3T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6B94++0x3 line.long 0x0 "INTCLR_B3P3T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6D94++0x3 line.long 0x0 "INTCLR_B3P3T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x198++0x3 line.long 0x0 "INTMSK_B0P0T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x398++0x3 line.long 0x0 "INTMSK_B0P0T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x598++0x3 line.long 0x0 "INTMSK_B0P0T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x998++0x3 line.long 0x0 "INTMSK_B0P3T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0xB98++0x3 line.long 0x0 "INTMSK_B0P3T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0xD98++0x3 line.long 0x0 "INTMSK_B0P3T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2198++0x3 line.long 0x0 "INTMSK_B1P0T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2398++0x3 line.long 0x0 "INTMSK_B1P0T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2598++0x3 line.long 0x0 "INTMSK_B1P0T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2998++0x3 line.long 0x0 "INTMSK_B1P3T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2B98++0x3 line.long 0x0 "INTMSK_B1P3T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2D98++0x3 line.long 0x0 "INTMSK_B1P3T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4198++0x3 line.long 0x0 "INTMSK_B2P0T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4398++0x3 line.long 0x0 "INTMSK_B2P0T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4598++0x3 line.long 0x0 "INTMSK_B2P0T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4998++0x3 line.long 0x0 "INTMSK_B2P3T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4B98++0x3 line.long 0x0 "INTMSK_B2P3T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4D98++0x3 line.long 0x0 "INTMSK_B2P3T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6198++0x3 line.long 0x0 "INTMSK_B3P0T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6398++0x3 line.long 0x0 "INTMSK_B3P0T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6598++0x3 line.long 0x0 "INTMSK_B3P0T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6998++0x3 line.long 0x0 "INTMSK_B3P3T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6B98++0x3 line.long 0x0 "INTMSK_B3P3T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6D98++0x3 line.long 0x0 "INTMSK_B3P3T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x19C++0x3 line.long 0x0 "MSKCLR_B0P0T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x39C++0x3 line.long 0x0 "MSKCLR_B0P0T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x59C++0x3 line.long 0x0 "MSKCLR_B0P0T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x99C++0x3 line.long 0x0 "MSKCLR_B0P3T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0xB9C++0x3 line.long 0x0 "MSKCLR_B0P3T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0xD9C++0x3 line.long 0x0 "MSKCLR_B0P3T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x219C++0x3 line.long 0x0 "MSKCLR_B1P0T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x239C++0x3 line.long 0x0 "MSKCLR_B1P0T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x259C++0x3 line.long 0x0 "MSKCLR_B1P0T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x299C++0x3 line.long 0x0 "MSKCLR_B1P3T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x2B9C++0x3 line.long 0x0 "MSKCLR_B1P3T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x2D9C++0x3 line.long 0x0 "MSKCLR_B1P3T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x419C++0x3 line.long 0x0 "MSKCLR_B2P0T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x439C++0x3 line.long 0x0 "MSKCLR_B2P0T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x459C++0x3 line.long 0x0 "MSKCLR_B2P0T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x499C++0x3 line.long 0x0 "MSKCLR_B2P3T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x4B9C++0x3 line.long 0x0 "MSKCLR_B2P3T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x4D9C++0x3 line.long 0x0 "MSKCLR_B2P3T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x619C++0x3 line.long 0x0 "MSKCLR_B3P0T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x639C++0x3 line.long 0x0 "MSKCLR_B3P0T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x659C++0x3 line.long 0x0 "MSKCLR_B3P0T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x699C++0x3 line.long 0x0 "MSKCLR_B3P3T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x6B9C++0x3 line.long 0x0 "MSKCLR_B3P3T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x6D9C++0x3 line.long 0x0 "MSKCLR_B3P3T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x1A0++0x3 line.long 0x0 "POSNEG_B0P0T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x3A0++0x3 line.long 0x0 "POSNEG_B0P0T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x5A0++0x3 line.long 0x0 "POSNEG_B0P0T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x9A0++0x3 line.long 0x0 "POSNEG_B0P3T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0xBA0++0x3 line.long 0x0 "POSNEG_B0P3T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0xDA0++0x3 line.long 0x0 "POSNEG_B0P3T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x21A0++0x3 line.long 0x0 "POSNEG_B1P0T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x23A0++0x3 line.long 0x0 "POSNEG_B1P0T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x25A0++0x3 line.long 0x0 "POSNEG_B1P0T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x29A0++0x3 line.long 0x0 "POSNEG_B1P3T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x2BA0++0x3 line.long 0x0 "POSNEG_B1P3T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x2DA0++0x3 line.long 0x0 "POSNEG_B1P3T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x41A0++0x3 line.long 0x0 "POSNEG_B2P0T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x43A0++0x3 line.long 0x0 "POSNEG_B2P0T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x45A0++0x3 line.long 0x0 "POSNEG_B2P0T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x49A0++0x3 line.long 0x0 "POSNEG_B2P3T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x4BA0++0x3 line.long 0x0 "POSNEG_B2P3T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x4DA0++0x3 line.long 0x0 "POSNEG_B2P3T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x61A0++0x3 line.long 0x0 "POSNEG_B3P0T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x63A0++0x3 line.long 0x0 "POSNEG_B3P0T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x65A0++0x3 line.long 0x0 "POSNEG_B3P0T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x69A0++0x3 line.long 0x0 "POSNEG_B3P3T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x6BA0++0x3 line.long 0x0 "POSNEG_B3P3T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x6DA0++0x3 line.long 0x0 "POSNEG_B3P3T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x1A4++0x3 line.long 0x0 "EDGLEVEL_B0P0T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x3A4++0x3 line.long 0x0 "EDGLEVEL_B0P0T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x5A4++0x3 line.long 0x0 "EDGLEVEL_B0P0T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x9A4++0x3 line.long 0x0 "EDGLEVEL_B0P3T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0xBA4++0x3 line.long 0x0 "EDGLEVEL_B0P3T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0xDA4++0x3 line.long 0x0 "EDGLEVEL_B0P3T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x21A4++0x3 line.long 0x0 "EDGLEVEL_B1P0T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x23A4++0x3 line.long 0x0 "EDGLEVEL_B1P0T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x25A4++0x3 line.long 0x0 "EDGLEVEL_B1P0T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x29A4++0x3 line.long 0x0 "EDGLEVEL_B1P3T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x2BA4++0x3 line.long 0x0 "EDGLEVEL_B1P3T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x2DA4++0x3 line.long 0x0 "EDGLEVEL_B1P3T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x41A4++0x3 line.long 0x0 "EDGLEVEL_B2P0T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x43A4++0x3 line.long 0x0 "EDGLEVEL_B2P0T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x45A4++0x3 line.long 0x0 "EDGLEVEL_B2P0T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x49A4++0x3 line.long 0x0 "EDGLEVEL_B2P3T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x4BA4++0x3 line.long 0x0 "EDGLEVEL_B2P3T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x4DA4++0x3 line.long 0x0 "EDGLEVEL_B2P3T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x61A4++0x3 line.long 0x0 "EDGLEVEL_B3P0T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x63A4++0x3 line.long 0x0 "EDGLEVEL_B3P0T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x65A4++0x3 line.long 0x0 "EDGLEVEL_B3P0T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x69A4++0x3 line.long 0x0 "EDGLEVEL_B3P3T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x6BA4++0x3 line.long 0x0 "EDGLEVEL_B3P3T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x6DA4++0x3 line.long 0x0 "EDGLEVEL_B3P3T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x1A8++0x3 line.long 0x0 "FILONOFF_B0P0T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x3A8++0x3 line.long 0x0 "FILONOFF_B0P0T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x5A8++0x3 line.long 0x0 "FILONOFF_B0P0T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x9A8++0x3 line.long 0x0 "FILONOFF_B0P3T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0xBA8++0x3 line.long 0x0 "FILONOFF_B0P3T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0xDA8++0x3 line.long 0x0 "FILONOFF_B0P3T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x21A8++0x3 line.long 0x0 "FILONOFF_B1P0T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x23A8++0x3 line.long 0x0 "FILONOFF_B1P0T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x25A8++0x3 line.long 0x0 "FILONOFF_B1P0T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x29A8++0x3 line.long 0x0 "FILONOFF_B1P3T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x2BA8++0x3 line.long 0x0 "FILONOFF_B1P3T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x2DA8++0x3 line.long 0x0 "FILONOFF_B1P3T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x41A8++0x3 line.long 0x0 "FILONOFF_B2P0T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x43A8++0x3 line.long 0x0 "FILONOFF_B2P0T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x45A8++0x3 line.long 0x0 "FILONOFF_B2P0T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x49A8++0x3 line.long 0x0 "FILONOFF_B2P3T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x4BA8++0x3 line.long 0x0 "FILONOFF_B2P3T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x4DA8++0x3 line.long 0x0 "FILONOFF_B2P3T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x61A8++0x3 line.long 0x0 "FILONOFF_B3P0T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x63A8++0x3 line.long 0x0 "FILONOFF_B3P0T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x65A8++0x3 line.long 0x0 "FILONOFF_B3P0T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x69A8++0x3 line.long 0x0 "FILONOFF_B3P3T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x6BA8++0x3 line.long 0x0 "FILONOFF_B3P3T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x6DA8++0x3 line.long 0x0 "FILONOFF_B3P3T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x1AC++0x3 line.long 0x0 "FILCLKSEL_B0P0T0,Chattering Prevention Clock Select Register B0P0T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x3AC++0x3 line.long 0x0 "FILCLKSEL_B0P0T1,Chattering Prevention Clock Select Register B0P0T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x5AC++0x3 line.long 0x0 "FILCLKSEL_B0P0T2,Chattering Prevention Clock Select Register B0P0T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x9AC++0x3 line.long 0x0 "FILCLKSEL_B0P3T0,Chattering Prevention Clock Select Register B0P3T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0xBAC++0x3 line.long 0x0 "FILCLKSEL_B0P3T1,Chattering Prevention Clock Select Register B0P3T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0xDAC++0x3 line.long 0x0 "FILCLKSEL_B0P3T2,Chattering Prevention Clock Select Register B0P3T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x21AC++0x3 line.long 0x0 "FILCLKSEL_B1P0T0,Chattering Prevention Clock Select Register B1P0T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x23AC++0x3 line.long 0x0 "FILCLKSEL_B1P0T1,Chattering Prevention Clock Select Register B1P0T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x25AC++0x3 line.long 0x0 "FILCLKSEL_B1P0T2,Chattering Prevention Clock Select Register B1P0T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x29AC++0x3 line.long 0x0 "FILCLKSEL_B1P3T0,Chattering Prevention Clock Select Register B1P3T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x2BAC++0x3 line.long 0x0 "FILCLKSEL_B1P3T1,Chattering Prevention Clock Select Register B1P3T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x2DAC++0x3 line.long 0x0 "FILCLKSEL_B1P3T2,Chattering Prevention Clock Select Register B1P3T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x41AC++0x3 line.long 0x0 "FILCLKSEL_B2P0T0,Chattering Prevention Clock Select Register B2P0T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x43AC++0x3 line.long 0x0 "FILCLKSEL_B2P0T1,Chattering Prevention Clock Select Register B2P0T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x45AC++0x3 line.long 0x0 "FILCLKSEL_B2P0T2,Chattering Prevention Clock Select Register B2P0T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x49AC++0x3 line.long 0x0 "FILCLKSEL_B2P3T0,Chattering Prevention Clock Select Register B2P3T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x4BAC++0x3 line.long 0x0 "FILCLKSEL_B2P3T1,Chattering Prevention Clock Select Register B2P3T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x4DAC++0x3 line.long 0x0 "FILCLKSEL_B2P3T2,Chattering Prevention Clock Select Register B2P3T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x61AC++0x3 line.long 0x0 "FILCLKSEL_B3P0T0,Chattering Prevention Clock Select Register B3P0T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x63AC++0x3 line.long 0x0 "FILCLKSEL_B3P0T1,Chattering Prevention Clock Select Register B3P0T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x65AC++0x3 line.long 0x0 "FILCLKSEL_B3P0T2,Chattering Prevention Clock Select Register B3P0T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x69AC++0x3 line.long 0x0 "FILCLKSEL_B3P3T0,Chattering Prevention Clock Select Register B3P3T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x6BAC++0x3 line.long 0x0 "FILCLKSEL_B3P3T1,Chattering Prevention Clock Select Register B3P3T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x6DAC++0x3 line.long 0x0 "FILCLKSEL_B3P3T2,Chattering Prevention Clock Select Register B3P3T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x1C0++0x3 line.long 0x0 "OUTDTSEL_B0P0T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x3C0++0x3 line.long 0x0 "OUTDTSEL_B0P0T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x5C0++0x3 line.long 0x0 "OUTDTSEL_B0P0T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x9C0++0x3 line.long 0x0 "OUTDTSEL_B0P3T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0xBC0++0x3 line.long 0x0 "OUTDTSEL_B0P3T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0xDC0++0x3 line.long 0x0 "OUTDTSEL_B0P3T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x21C0++0x3 line.long 0x0 "OUTDTSEL_B1P0T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x23C0++0x3 line.long 0x0 "OUTDTSEL_B1P0T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x25C0++0x3 line.long 0x0 "OUTDTSEL_B1P0T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x29C0++0x3 line.long 0x0 "OUTDTSEL_B1P3T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x2BC0++0x3 line.long 0x0 "OUTDTSEL_B1P3T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x2DC0++0x3 line.long 0x0 "OUTDTSEL_B1P3T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x41C0++0x3 line.long 0x0 "OUTDTSEL_B2P0T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x43C0++0x3 line.long 0x0 "OUTDTSEL_B2P0T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x45C0++0x3 line.long 0x0 "OUTDTSEL_B2P0T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x49C0++0x3 line.long 0x0 "OUTDTSEL_B2P3T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x4BC0++0x3 line.long 0x0 "OUTDTSEL_B2P3T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x4DC0++0x3 line.long 0x0 "OUTDTSEL_B2P3T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x61C0++0x3 line.long 0x0 "OUTDTSEL_B3P0T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x63C0++0x3 line.long 0x0 "OUTDTSEL_B3P0T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x65C0++0x3 line.long 0x0 "OUTDTSEL_B3P0T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x69C0++0x3 line.long 0x0 "OUTDTSEL_B3P3T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x6BC0++0x3 line.long 0x0 "OUTDTSEL_B3P3T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x6DC0++0x3 line.long 0x0 "OUTDTSEL_B3P3T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x1C4++0x3 line.long 0x0 "OUTDTH_B0P0T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x3C4++0x3 line.long 0x0 "OUTDTH_B0P0T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x5C4++0x3 line.long 0x0 "OUTDTH_B0P0T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x9C4++0x3 line.long 0x0 "OUTDTH_B0P3T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0xBC4++0x3 line.long 0x0 "OUTDTH_B0P3T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0xDC4++0x3 line.long 0x0 "OUTDTH_B0P3T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x21C4++0x3 line.long 0x0 "OUTDTH_B1P0T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x23C4++0x3 line.long 0x0 "OUTDTH_B1P0T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x25C4++0x3 line.long 0x0 "OUTDTH_B1P0T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x29C4++0x3 line.long 0x0 "OUTDTH_B1P3T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x2BC4++0x3 line.long 0x0 "OUTDTH_B1P3T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x2DC4++0x3 line.long 0x0 "OUTDTH_B1P3T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x41C4++0x3 line.long 0x0 "OUTDTH_B2P0T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x43C4++0x3 line.long 0x0 "OUTDTH_B2P0T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x45C4++0x3 line.long 0x0 "OUTDTH_B2P0T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x49C4++0x3 line.long 0x0 "OUTDTH_B2P3T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x4BC4++0x3 line.long 0x0 "OUTDTH_B2P3T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x4DC4++0x3 line.long 0x0 "OUTDTH_B2P3T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x61C4++0x3 line.long 0x0 "OUTDTH_B3P0T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x63C4++0x3 line.long 0x0 "OUTDTH_B3P0T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x65C4++0x3 line.long 0x0 "OUTDTH_B3P0T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x69C4++0x3 line.long 0x0 "OUTDTH_B3P3T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x6BC4++0x3 line.long 0x0 "OUTDTH_B3P3T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x6DC4++0x3 line.long 0x0 "OUTDTH_B3P3T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x1C8++0x3 line.long 0x0 "OUTDTL_B0P0T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x3C8++0x3 line.long 0x0 "OUTDTL_B0P0T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x5C8++0x3 line.long 0x0 "OUTDTL_B0P0T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x9C8++0x3 line.long 0x0 "OUTDTL_B0P3T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0xBC8++0x3 line.long 0x0 "OUTDTL_B0P3T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0xDC8++0x3 line.long 0x0 "OUTDTL_B0P3T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x21C8++0x3 line.long 0x0 "OUTDTL_B1P0T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x23C8++0x3 line.long 0x0 "OUTDTL_B1P0T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x25C8++0x3 line.long 0x0 "OUTDTL_B1P0T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x29C8++0x3 line.long 0x0 "OUTDTL_B1P3T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x2BC8++0x3 line.long 0x0 "OUTDTL_B1P3T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x2DC8++0x3 line.long 0x0 "OUTDTL_B1P3T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x41C8++0x3 line.long 0x0 "OUTDTL_B2P0T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x43C8++0x3 line.long 0x0 "OUTDTL_B2P0T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x45C8++0x3 line.long 0x0 "OUTDTL_B2P0T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x49C8++0x3 line.long 0x0 "OUTDTL_B2P3T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x4BC8++0x3 line.long 0x0 "OUTDTL_B2P3T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x4DC8++0x3 line.long 0x0 "OUTDTL_B2P3T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x61C8++0x3 line.long 0x0 "OUTDTL_B3P0T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x63C8++0x3 line.long 0x0 "OUTDTL_B3P0T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x65C8++0x3 line.long 0x0 "OUTDTL_B3P0T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x69C8++0x3 line.long 0x0 "OUTDTL_B3P3T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x6BC8++0x3 line.long 0x0 "OUTDTL_B3P3T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x6DC8++0x3 line.long 0x0 "OUTDTL_B3P3T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x1CC++0x3 line.long 0x0 "BOTHEDGE_B0P0T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x3CC++0x3 line.long 0x0 "BOTHEDGE_B0P0T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x5CC++0x3 line.long 0x0 "BOTHEDGE_B0P0T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x9CC++0x3 line.long 0x0 "BOTHEDGE_B0P3T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0xBCC++0x3 line.long 0x0 "BOTHEDGE_B0P3T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0xDCC++0x3 line.long 0x0 "BOTHEDGE_B0P3T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x21CC++0x3 line.long 0x0 "BOTHEDGE_B1P0T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x23CC++0x3 line.long 0x0 "BOTHEDGE_B1P0T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x25CC++0x3 line.long 0x0 "BOTHEDGE_B1P0T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x29CC++0x3 line.long 0x0 "BOTHEDGE_B1P3T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x2BCC++0x3 line.long 0x0 "BOTHEDGE_B1P3T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x2DCC++0x3 line.long 0x0 "BOTHEDGE_B1P3T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x41CC++0x3 line.long 0x0 "BOTHEDGE_B2P0T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x43CC++0x3 line.long 0x0 "BOTHEDGE_B2P0T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x45CC++0x3 line.long 0x0 "BOTHEDGE_B2P0T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x49CC++0x3 line.long 0x0 "BOTHEDGE_B2P3T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x4BCC++0x3 line.long 0x0 "BOTHEDGE_B2P3T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x4DCC++0x3 line.long 0x0 "BOTHEDGE_B2P3T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x61CC++0x3 line.long 0x0 "BOTHEDGE_B3P0T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x63CC++0x3 line.long 0x0 "BOTHEDGE_B3P0T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x65CC++0x3 line.long 0x0 "BOTHEDGE_B3P0T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x69CC++0x3 line.long 0x0 "BOTHEDGE_B3P3T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x6BCC++0x3 line.long 0x0 "BOTHEDGE_B3P3T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x6DCC++0x3 line.long 0x0 "BOTHEDGE_B3P3T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x1D0++0x3 line.long 0x0 "INEN_B0P0T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x3D0++0x3 line.long 0x0 "INEN_B0P0T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x5D0++0x3 line.long 0x0 "INEN_B0P0T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x9D0++0x3 line.long 0x0 "INEN_B0P3T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0xBD0++0x3 line.long 0x0 "INEN_B0P3T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0xDD0++0x3 line.long 0x0 "INEN_B0P3T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x21D0++0x3 line.long 0x0 "INEN_B1P0T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x23D0++0x3 line.long 0x0 "INEN_B1P0T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x25D0++0x3 line.long 0x0 "INEN_B1P0T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x29D0++0x3 line.long 0x0 "INEN_B1P3T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x2BD0++0x3 line.long 0x0 "INEN_B1P3T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x2DD0++0x3 line.long 0x0 "INEN_B1P3T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x41D0++0x3 line.long 0x0 "INEN_B2P0T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x43D0++0x3 line.long 0x0 "INEN_B2P0T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x45D0++0x3 line.long 0x0 "INEN_B2P0T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x49D0++0x3 line.long 0x0 "INEN_B2P3T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x4BD0++0x3 line.long 0x0 "INEN_B2P3T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x4DD0++0x3 line.long 0x0 "INEN_B2P3T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x61D0++0x3 line.long 0x0 "INEN_B3P0T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x63D0++0x3 line.long 0x0 "INEN_B3P0T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x65D0++0x3 line.long 0x0 "INEN_B3P0T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x69D0++0x3 line.long 0x0 "INEN_B3P3T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x6BD0++0x3 line.long 0x0 "INEN_B3P3T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x6DD0++0x3 line.long 0x0 "INEN_B3P3T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x88++0x3 line.long 0x0 "DRV2CTRL_B0P0T0,DRV Control Register2 B0P0T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x288++0x3 line.long 0x0 "DRV2CTRL_B0P0T1,DRV Control Register2 B0P0T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x488++0x3 line.long 0x0 "DRV2CTRL_B0P0T2,DRV Control Register2 B0P0T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x888++0x3 line.long 0x0 "DRV2CTRL_B0P3T0,DRV Control Register2 B0P3T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0xA88++0x3 line.long 0x0 "DRV2CTRL_B0P3T1,DRV Control Register2 B0P3T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0xC88++0x3 line.long 0x0 "DRV2CTRL_B0P3T2,DRV Control Register2 B0P3T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2088++0x3 line.long 0x0 "DRV2CTRL_B1P0T0,DRV Control Register2 B1P0T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2288++0x3 line.long 0x0 "DRV2CTRL_B1P0T1,DRV Control Register2 B1P0T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2488++0x3 line.long 0x0 "DRV2CTRL_B1P0T2,DRV Control Register2 B1P0T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2888++0x3 line.long 0x0 "DRV2CTRL_B1P3T0,DRV Control Register2 B1P3T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2A88++0x3 line.long 0x0 "DRV2CTRL_B1P3T1,DRV Control Register2 B1P3T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2C88++0x3 line.long 0x0 "DRV2CTRL_B1P3T2,DRV Control Register2 B1P3T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4088++0x3 line.long 0x0 "DRV2CTRL_B2P0T0,DRV Control Register2 B2P0T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4288++0x3 line.long 0x0 "DRV2CTRL_B2P0T1,DRV Control Register2 B2P0T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4488++0x3 line.long 0x0 "DRV2CTRL_B2P0T2,DRV Control Register2 B2P0T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4888++0x3 line.long 0x0 "DRV2CTRL_B2P3T0,DRV Control Register2 B2P3T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4A88++0x3 line.long 0x0 "DRV2CTRL_B2P3T1,DRV Control Register2 B2P3T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4C88++0x3 line.long 0x0 "DRV2CTRL_B2P3T2,DRV Control Register2 B2P3T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6088++0x3 line.long 0x0 "DRV2CTRL_B3P0T0,DRV Control Register2 B3P0T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6288++0x3 line.long 0x0 "DRV2CTRL_B3P0T1,DRV Control Register2 B3P0T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6488++0x3 line.long 0x0 "DRV2CTRL_B3P0T2,DRV Control Register2 B3P0T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6888++0x3 line.long 0x0 "DRV2CTRL_B3P3T0,DRV Control Register2 B3P3T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6A88++0x3 line.long 0x0 "DRV2CTRL_B3P3T1,DRV Control Register2 B3P3T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6C88++0x3 line.long 0x0 "DRV2CTRL_B3P3T2,DRV Control Register2 B3P3T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x8C++0x3 line.long 0x0 "DRV3CTRL_B0P0T0,DRV Control Register3 B0P0T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x28C++0x3 line.long 0x0 "DRV3CTRL_B0P0T1,DRV Control Register3 B0P0T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x48C++0x3 line.long 0x0 "DRV3CTRL_B0P0T2,DRV Control Register3 B0P0T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x88C++0x3 line.long 0x0 "DRV3CTRL_B0P3T0,DRV Control Register3 B0P3T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0xA8C++0x3 line.long 0x0 "DRV3CTRL_B0P3T1,DRV Control Register3 B0P3T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0xC8C++0x3 line.long 0x0 "DRV3CTRL_B0P3T2,DRV Control Register3 B0P3T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x208C++0x3 line.long 0x0 "DRV3CTRL_B1P0T0,DRV Control Register3 B1P0T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x228C++0x3 line.long 0x0 "DRV3CTRL_B1P0T1,DRV Control Register3 B1P0T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x248C++0x3 line.long 0x0 "DRV3CTRL_B1P0T2,DRV Control Register3 B1P0T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x288C++0x3 line.long 0x0 "DRV3CTRL_B1P3T0,DRV Control Register3 B1P3T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x2A8C++0x3 line.long 0x0 "DRV3CTRL_B1P3T1,DRV Control Register3 B1P3T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x2C8C++0x3 line.long 0x0 "DRV3CTRL_B1P3T2,DRV Control Register3 B1P3T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x408C++0x3 line.long 0x0 "DRV3CTRL_B2P0T0,DRV Control Register3 B2P0T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x428C++0x3 line.long 0x0 "DRV3CTRL_B2P0T1,DRV Control Register3 B2P0T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x448C++0x3 line.long 0x0 "DRV3CTRL_B2P0T2,DRV Control Register3 B2P0T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x488C++0x3 line.long 0x0 "DRV3CTRL_B2P3T0,DRV Control Register3 B2P3T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x4A8C++0x3 line.long 0x0 "DRV3CTRL_B2P3T1,DRV Control Register3 B2P3T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x4C8C++0x3 line.long 0x0 "DRV3CTRL_B2P3T2,DRV Control Register3 B2P3T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x608C++0x3 line.long 0x0 "DRV3CTRL_B3P0T0,DRV Control Register3 B3P0T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x628C++0x3 line.long 0x0 "DRV3CTRL_B3P0T1,DRV Control Register3 B3P0T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x648C++0x3 line.long 0x0 "DRV3CTRL_B3P0T2,DRV Control Register3 B3P0T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x688C++0x3 line.long 0x0 "DRV3CTRL_B3P3T0,DRV Control Register3 B3P3T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x6A8C++0x3 line.long 0x0 "DRV3CTRL_B3P3T1,DRV Control Register3 B3P3T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x6C8C++0x3 line.long 0x0 "DRV3CTRL_B3P3T2,DRV Control Register3 B3P3T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" tree.end tree "PFC_2" base ad:0xE6060000 group.long 0x0++0x3 line.long 0x0 "PMMR_B0P4T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x200++0x3 line.long 0x0 "PMMR_B0P4T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x400++0x3 line.long 0x0 "PMMR_B0P4T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x800++0x3 line.long 0x0 "PMMR_B0P5T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xA00++0x3 line.long 0x0 "PMMR_B0P5T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xC00++0x3 line.long 0x0 "PMMR_B0P5T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2000++0x3 line.long 0x0 "PMMR_B1P4T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2200++0x3 line.long 0x0 "PMMR_B1P4T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2400++0x3 line.long 0x0 "PMMR_B1P4T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2800++0x3 line.long 0x0 "PMMR_B1P5T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2A00++0x3 line.long 0x0 "PMMR_B1P5T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2C00++0x3 line.long 0x0 "PMMR_B1P5T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4000++0x3 line.long 0x0 "PMMR_B2P4T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4200++0x3 line.long 0x0 "PMMR_B2P4T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4400++0x3 line.long 0x0 "PMMR_B2P4T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4800++0x3 line.long 0x0 "PMMR_B2P5T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4A00++0x3 line.long 0x0 "PMMR_B2P5T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4C00++0x3 line.long 0x0 "PMMR_B2P5T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6000++0x3 line.long 0x0 "PMMR_B3P4T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6200++0x3 line.long 0x0 "PMMR_B3P4T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6400++0x3 line.long 0x0 "PMMR_B3P4T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6800++0x3 line.long 0x0 "PMMR_B3P5T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6A00++0x3 line.long 0x0 "PMMR_B3P5T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6C00++0x3 line.long 0x0 "PMMR_B3P5T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x40++0x3 line.long 0x0 "GPSR_B0P4T0,GPIO/Peripheral Function Select Register B0P4T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x240++0x3 line.long 0x0 "GPSR_B0P4T1,GPIO/Peripheral Function Select Register B0P4T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x440++0x3 line.long 0x0 "GPSR_B0P4T2,GPIO/Peripheral Function Select Register B0P4T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x40++0x3 line.long 0x0 "GPSR_B0P5T0,GPIO/Peripheral Function Select Register B0P5T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x240++0x3 line.long 0x0 "GPSR_B0P5T1,GPIO/Peripheral Function Select Register B0P5T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x440++0x3 line.long 0x0 "GPSR_B0P5T2,GPIO/Peripheral Function Select Register B0P5T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2040++0x3 line.long 0x0 "GPSR_B1P4T0,GPIO/Peripheral Function Select Register B1P4T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2240++0x3 line.long 0x0 "GPSR_B1P4T1,GPIO/Peripheral Function Select Register B1P4T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2440++0x3 line.long 0x0 "GPSR_B1P4T2,GPIO/Peripheral Function Select Register B1P4T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2040++0x3 line.long 0x0 "GPSR_B1P5T0,GPIO/Peripheral Function Select Register B1P5T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2240++0x3 line.long 0x0 "GPSR_B1P5T1,GPIO/Peripheral Function Select Register B1P5T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2440++0x3 line.long 0x0 "GPSR_B1P5T2,GPIO/Peripheral Function Select Register B1P5T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4040++0x3 line.long 0x0 "GPSR_B2P4T0,GPIO/Peripheral Function Select Register B2P4T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4240++0x3 line.long 0x0 "GPSR_B2P4T1,GPIO/Peripheral Function Select Register B2P4T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4440++0x3 line.long 0x0 "GPSR_B2P4T2,GPIO/Peripheral Function Select Register B2P4T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4040++0x3 line.long 0x0 "GPSR_B2P5T0,GPIO/Peripheral Function Select Register B2P5T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4240++0x3 line.long 0x0 "GPSR_B2P5T1,GPIO/Peripheral Function Select Register B2P5T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4440++0x3 line.long 0x0 "GPSR_B2P5T2,GPIO/Peripheral Function Select Register B2P5T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6040++0x3 line.long 0x0 "GPSR_B3P4T0,GPIO/Peripheral Function Select Register B3P4T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6240++0x3 line.long 0x0 "GPSR_B3P4T1,GPIO/Peripheral Function Select Register B3P4T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6440++0x3 line.long 0x0 "GPSR_B3P4T2,GPIO/Peripheral Function Select Register B3P4T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6040++0x3 line.long 0x0 "GPSR_B3P5T0,GPIO/Peripheral Function Select Register B3P5T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6240++0x3 line.long 0x0 "GPSR_B3P5T1,GPIO/Peripheral Function Select Register B3P5T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6440++0x3 line.long 0x0 "GPSR_B3P5T2,GPIO/Peripheral Function Select Register B3P5T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x60++0x3 line.long 0x0 "IP0SR_B0P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x260++0x3 line.long 0x0 "IP0SR_B0P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x460++0x3 line.long 0x0 "IP0SR_B0P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x60++0x3 line.long 0x0 "IP0SR_B0P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x260++0x3 line.long 0x0 "IP0SR_B0P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x460++0x3 line.long 0x0 "IP0SR_B0P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2060++0x3 line.long 0x0 "IP0SR_B1P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2260++0x3 line.long 0x0 "IP0SR_B1P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2460++0x3 line.long 0x0 "IP0SR_B1P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2060++0x3 line.long 0x0 "IP0SR_B1P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2260++0x3 line.long 0x0 "IP0SR_B1P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2460++0x3 line.long 0x0 "IP0SR_B1P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4060++0x3 line.long 0x0 "IP0SR_B2P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4260++0x3 line.long 0x0 "IP0SR_B2P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4460++0x3 line.long 0x0 "IP0SR_B2P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4060++0x3 line.long 0x0 "IP0SR_B2P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4260++0x3 line.long 0x0 "IP0SR_B2P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4460++0x3 line.long 0x0 "IP0SR_B2P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6060++0x3 line.long 0x0 "IP0SR_B3P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6260++0x3 line.long 0x0 "IP0SR_B3P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6460++0x3 line.long 0x0 "IP0SR_B3P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6060++0x3 line.long 0x0 "IP0SR_B3P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6260++0x3 line.long 0x0 "IP0SR_B3P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6460++0x3 line.long 0x0 "IP0SR_B3P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x64++0x3 line.long 0x0 "IP1SR_B0P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x264++0x3 line.long 0x0 "IP1SR_B0P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x464++0x3 line.long 0x0 "IP1SR_B0P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x64++0x3 line.long 0x0 "IP1SR_B0P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x264++0x3 line.long 0x0 "IP1SR_B0P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x464++0x3 line.long 0x0 "IP1SR_B0P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2064++0x3 line.long 0x0 "IP1SR_B1P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2264++0x3 line.long 0x0 "IP1SR_B1P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2464++0x3 line.long 0x0 "IP1SR_B1P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2064++0x3 line.long 0x0 "IP1SR_B1P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2264++0x3 line.long 0x0 "IP1SR_B1P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2464++0x3 line.long 0x0 "IP1SR_B1P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4064++0x3 line.long 0x0 "IP1SR_B2P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4264++0x3 line.long 0x0 "IP1SR_B2P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4464++0x3 line.long 0x0 "IP1SR_B2P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4064++0x3 line.long 0x0 "IP1SR_B2P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4264++0x3 line.long 0x0 "IP1SR_B2P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4464++0x3 line.long 0x0 "IP1SR_B2P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6064++0x3 line.long 0x0 "IP1SR_B3P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6264++0x3 line.long 0x0 "IP1SR_B3P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6464++0x3 line.long 0x0 "IP1SR_B3P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6064++0x3 line.long 0x0 "IP1SR_B3P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6264++0x3 line.long 0x0 "IP1SR_B3P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6464++0x3 line.long 0x0 "IP1SR_B3P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x68++0x3 line.long 0x0 "IP2SR_B0P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x268++0x3 line.long 0x0 "IP2SR_B0P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x468++0x3 line.long 0x0 "IP2SR_B0P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x68++0x3 line.long 0x0 "IP2SR_B0P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x268++0x3 line.long 0x0 "IP2SR_B0P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x468++0x3 line.long 0x0 "IP2SR_B0P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2068++0x3 line.long 0x0 "IP2SR_B1P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2268++0x3 line.long 0x0 "IP2SR_B1P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2468++0x3 line.long 0x0 "IP2SR_B1P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2068++0x3 line.long 0x0 "IP2SR_B1P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2268++0x3 line.long 0x0 "IP2SR_B1P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2468++0x3 line.long 0x0 "IP2SR_B1P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4068++0x3 line.long 0x0 "IP2SR_B2P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4268++0x3 line.long 0x0 "IP2SR_B2P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4468++0x3 line.long 0x0 "IP2SR_B2P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4068++0x3 line.long 0x0 "IP2SR_B2P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4268++0x3 line.long 0x0 "IP2SR_B2P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4468++0x3 line.long 0x0 "IP2SR_B2P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6068++0x3 line.long 0x0 "IP2SR_B3P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6268++0x3 line.long 0x0 "IP2SR_B3P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6468++0x3 line.long 0x0 "IP2SR_B3P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6068++0x3 line.long 0x0 "IP2SR_B3P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6268++0x3 line.long 0x0 "IP2SR_B3P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6468++0x3 line.long 0x0 "IP2SR_B3P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x80++0x3 line.long 0x0 "DRV0CTRL_B0P4T0,DRV Control Register0 B0P4T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x280++0x3 line.long 0x0 "DRV0CTRL_B0P4T1,DRV Control Register0 B0P4T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x480++0x3 line.long 0x0 "DRV0CTRL_B0P4T2,DRV Control Register0 B0P4T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x80++0x3 line.long 0x0 "DRV0CTRL_B0P5T0,DRV Control Register0 B0P5T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x280++0x3 line.long 0x0 "DRV0CTRL_B0P5T1,DRV Control Register0 B0P5T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x480++0x3 line.long 0x0 "DRV0CTRL_B0P5T2,DRV Control Register0 B0P5T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2080++0x3 line.long 0x0 "DRV0CTRL_B1P4T0,DRV Control Register0 B1P4T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2280++0x3 line.long 0x0 "DRV0CTRL_B1P4T1,DRV Control Register0 B1P4T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2480++0x3 line.long 0x0 "DRV0CTRL_B1P4T2,DRV Control Register0 B1P4T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2080++0x3 line.long 0x0 "DRV0CTRL_B1P5T0,DRV Control Register0 B1P5T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2280++0x3 line.long 0x0 "DRV0CTRL_B1P5T1,DRV Control Register0 B1P5T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2480++0x3 line.long 0x0 "DRV0CTRL_B1P5T2,DRV Control Register0 B1P5T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4080++0x3 line.long 0x0 "DRV0CTRL_B2P4T0,DRV Control Register0 B2P4T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4280++0x3 line.long 0x0 "DRV0CTRL_B2P4T1,DRV Control Register0 B2P4T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4480++0x3 line.long 0x0 "DRV0CTRL_B2P4T2,DRV Control Register0 B2P4T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4080++0x3 line.long 0x0 "DRV0CTRL_B2P5T0,DRV Control Register0 B2P5T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4280++0x3 line.long 0x0 "DRV0CTRL_B2P5T1,DRV Control Register0 B2P5T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4480++0x3 line.long 0x0 "DRV0CTRL_B2P5T2,DRV Control Register0 B2P5T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6080++0x3 line.long 0x0 "DRV0CTRL_B3P4T0,DRV Control Register0 B3P4T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6280++0x3 line.long 0x0 "DRV0CTRL_B3P4T1,DRV Control Register0 B3P4T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6480++0x3 line.long 0x0 "DRV0CTRL_B3P4T2,DRV Control Register0 B3P4T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6080++0x3 line.long 0x0 "DRV0CTRL_B3P5T0,DRV Control Register0 B3P5T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6280++0x3 line.long 0x0 "DRV0CTRL_B3P5T1,DRV Control Register0 B3P5T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6480++0x3 line.long 0x0 "DRV0CTRL_B3P5T2,DRV Control Register0 B3P5T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0xA0++0x3 line.long 0x0 "POC_B0P4T0,POC Control Register B0P4T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x2A0++0x3 line.long 0x0 "POC_B0P4T1,POC Control Register B0P4T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x4A0++0x3 line.long 0x0 "POC_B0P4T2,POC Control Register B0P4T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0xA0++0x3 line.long 0x0 "POC_B0P5T0,POC Control Register B0P5T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x2A0++0x3 line.long 0x0 "POC_B0P5T1,POC Control Register B0P5T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x4A0++0x3 line.long 0x0 "POC_B0P5T2,POC Control Register B0P5T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x20A0++0x3 line.long 0x0 "POC_B1P4T0,POC Control Register B1P4T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x22A0++0x3 line.long 0x0 "POC_B1P4T1,POC Control Register B1P4T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x24A0++0x3 line.long 0x0 "POC_B1P4T2,POC Control Register B1P4T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x20A0++0x3 line.long 0x0 "POC_B1P5T0,POC Control Register B1P5T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x22A0++0x3 line.long 0x0 "POC_B1P5T1,POC Control Register B1P5T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x24A0++0x3 line.long 0x0 "POC_B1P5T2,POC Control Register B1P5T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x40A0++0x3 line.long 0x0 "POC_B2P4T0,POC Control Register B2P4T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x42A0++0x3 line.long 0x0 "POC_B2P4T1,POC Control Register B2P4T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x44A0++0x3 line.long 0x0 "POC_B2P4T2,POC Control Register B2P4T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x40A0++0x3 line.long 0x0 "POC_B2P5T0,POC Control Register B2P5T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x42A0++0x3 line.long 0x0 "POC_B2P5T1,POC Control Register B2P5T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x44A0++0x3 line.long 0x0 "POC_B2P5T2,POC Control Register B2P5T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x60A0++0x3 line.long 0x0 "POC_B3P4T0,POC Control Register B3P4T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x62A0++0x3 line.long 0x0 "POC_B3P4T1,POC Control Register B3P4T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x64A0++0x3 line.long 0x0 "POC_B3P4T2,POC Control Register B3P4T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x60A0++0x3 line.long 0x0 "POC_B3P5T0,POC Control Register B3P5T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x62A0++0x3 line.long 0x0 "POC_B3P5T1,POC Control Register B3P5T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x64A0++0x3 line.long 0x0 "POC_B3P5T2,POC Control Register B3P5T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0xC0++0x3 line.long 0x0 "PUEN_B0P4T0,LSI Pin Pull-enable Register B0P4T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x2C0++0x3 line.long 0x0 "PUEN_B0P4T1,LSI Pin Pull-enable Register B0P4T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x4C0++0x3 line.long 0x0 "PUEN_B0P4T2,LSI Pin Pull-enable Register B0P4T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0xC0++0x3 line.long 0x0 "PUEN_B0P5T0,LSI Pin Pull-enable Register B0P5T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x2C0++0x3 line.long 0x0 "PUEN_B0P5T1,LSI Pin Pull-enable Register B0P5T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x4C0++0x3 line.long 0x0 "PUEN_B0P5T2,LSI Pin Pull-enable Register B0P5T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x20C0++0x3 line.long 0x0 "PUEN_B1P4T0,LSI Pin Pull-enable Register B1P4T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x22C0++0x3 line.long 0x0 "PUEN_B1P4T1,LSI Pin Pull-enable Register B1P4T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x24C0++0x3 line.long 0x0 "PUEN_B1P4T2,LSI Pin Pull-enable Register B1P4T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x20C0++0x3 line.long 0x0 "PUEN_B1P5T0,LSI Pin Pull-enable Register B1P5T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x22C0++0x3 line.long 0x0 "PUEN_B1P5T1,LSI Pin Pull-enable Register B1P5T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x24C0++0x3 line.long 0x0 "PUEN_B1P5T2,LSI Pin Pull-enable Register B1P5T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x40C0++0x3 line.long 0x0 "PUEN_B2P4T0,LSI Pin Pull-enable Register B2P4T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x42C0++0x3 line.long 0x0 "PUEN_B2P4T1,LSI Pin Pull-enable Register B2P4T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x44C0++0x3 line.long 0x0 "PUEN_B2P4T2,LSI Pin Pull-enable Register B2P4T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x40C0++0x3 line.long 0x0 "PUEN_B2P5T0,LSI Pin Pull-enable Register B2P5T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x42C0++0x3 line.long 0x0 "PUEN_B2P5T1,LSI Pin Pull-enable Register B2P5T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x44C0++0x3 line.long 0x0 "PUEN_B2P5T2,LSI Pin Pull-enable Register B2P5T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x60C0++0x3 line.long 0x0 "PUEN_B3P4T0,LSI Pin Pull-enable Register B3P4T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x62C0++0x3 line.long 0x0 "PUEN_B3P4T1,LSI Pin Pull-enable Register B3P4T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x64C0++0x3 line.long 0x0 "PUEN_B3P4T2,LSI Pin Pull-enable Register B3P4T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x60C0++0x3 line.long 0x0 "PUEN_B3P5T0,LSI Pin Pull-enable Register B3P5T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x62C0++0x3 line.long 0x0 "PUEN_B3P5T1,LSI Pin Pull-enable Register B3P5T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x64C0++0x3 line.long 0x0 "PUEN_B3P5T2,LSI Pin Pull-enable Register B3P5T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0xE0++0x3 line.long 0x0 "PUD_B0P4T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x2E0++0x3 line.long 0x0 "PUD_B0P4T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x4E0++0x3 line.long 0x0 "PUD_B0P4T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0xE0++0x3 line.long 0x0 "PUD_B0P5T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x2E0++0x3 line.long 0x0 "PUD_B0P5T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x4E0++0x3 line.long 0x0 "PUD_B0P5T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x20E0++0x3 line.long 0x0 "PUD_B1P4T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x22E0++0x3 line.long 0x0 "PUD_B1P4T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x24E0++0x3 line.long 0x0 "PUD_B1P4T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x20E0++0x3 line.long 0x0 "PUD_B1P5T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x22E0++0x3 line.long 0x0 "PUD_B1P5T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x24E0++0x3 line.long 0x0 "PUD_B1P5T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x40E0++0x3 line.long 0x0 "PUD_B2P4T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x42E0++0x3 line.long 0x0 "PUD_B2P4T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x44E0++0x3 line.long 0x0 "PUD_B2P4T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x40E0++0x3 line.long 0x0 "PUD_B2P5T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x42E0++0x3 line.long 0x0 "PUD_B2P5T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x44E0++0x3 line.long 0x0 "PUD_B2P5T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x60E0++0x3 line.long 0x0 "PUD_B3P4T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x62E0++0x3 line.long 0x0 "PUD_B3P4T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x64E0++0x3 line.long 0x0 "PUD_B3P4T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x60E0++0x3 line.long 0x0 "PUD_B3P5T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x62E0++0x3 line.long 0x0 "PUD_B3P5T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x64E0++0x3 line.long 0x0 "PUD_B3P5T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x0++0x3 line.long 0x0 "PMMR_B0P4T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x200++0x3 line.long 0x0 "PMMR_B0P4T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x400++0x3 line.long 0x0 "PMMR_B0P4T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x800++0x3 line.long 0x0 "PMMR_B0P5T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xA00++0x3 line.long 0x0 "PMMR_B0P5T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xC00++0x3 line.long 0x0 "PMMR_B0P5T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2000++0x3 line.long 0x0 "PMMR_B1P4T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2200++0x3 line.long 0x0 "PMMR_B1P4T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2400++0x3 line.long 0x0 "PMMR_B1P4T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2800++0x3 line.long 0x0 "PMMR_B1P5T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2A00++0x3 line.long 0x0 "PMMR_B1P5T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2C00++0x3 line.long 0x0 "PMMR_B1P5T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4000++0x3 line.long 0x0 "PMMR_B2P4T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4200++0x3 line.long 0x0 "PMMR_B2P4T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4400++0x3 line.long 0x0 "PMMR_B2P4T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4800++0x3 line.long 0x0 "PMMR_B2P5T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4A00++0x3 line.long 0x0 "PMMR_B2P5T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4C00++0x3 line.long 0x0 "PMMR_B2P5T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6000++0x3 line.long 0x0 "PMMR_B3P4T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6200++0x3 line.long 0x0 "PMMR_B3P4T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6400++0x3 line.long 0x0 "PMMR_B3P4T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6800++0x3 line.long 0x0 "PMMR_B3P5T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6A00++0x3 line.long 0x0 "PMMR_B3P5T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6C00++0x3 line.long 0x0 "PMMR_B3P5T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4++0x3 line.long 0x0 "PMMER_B0P4T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x204++0x3 line.long 0x0 "PMMER_B0P4T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x404++0x3 line.long 0x0 "PMMER_B0P4T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x804++0x3 line.long 0x0 "PMMER_B0P5T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0xA04++0x3 line.long 0x0 "PMMER_B0P5T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0xC04++0x3 line.long 0x0 "PMMER_B0P5T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2004++0x3 line.long 0x0 "PMMER_B1P4T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2204++0x3 line.long 0x0 "PMMER_B1P4T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2404++0x3 line.long 0x0 "PMMER_B1P4T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2804++0x3 line.long 0x0 "PMMER_B1P5T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2A04++0x3 line.long 0x0 "PMMER_B1P5T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2C04++0x3 line.long 0x0 "PMMER_B1P5T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4004++0x3 line.long 0x0 "PMMER_B2P4T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4204++0x3 line.long 0x0 "PMMER_B2P4T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4404++0x3 line.long 0x0 "PMMER_B2P4T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4804++0x3 line.long 0x0 "PMMER_B2P5T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4A04++0x3 line.long 0x0 "PMMER_B2P5T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4C04++0x3 line.long 0x0 "PMMER_B2P5T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6004++0x3 line.long 0x0 "PMMER_B3P4T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6204++0x3 line.long 0x0 "PMMER_B3P4T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6404++0x3 line.long 0x0 "PMMER_B3P4T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6804++0x3 line.long 0x0 "PMMER_B3P5T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6A04++0x3 line.long 0x0 "PMMER_B3P5T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6C04++0x3 line.long 0x0 "PMMER_B3P5T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x20++0x3 line.long 0x0 "DMPR0_B0P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x220++0x3 line.long 0x0 "DMPR0_B0P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x420++0x3 line.long 0x0 "DMPR0_B0P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x820++0x3 line.long 0x0 "DMPR0_B0P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA20++0x3 line.long 0x0 "DMPR0_B0P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC20++0x3 line.long 0x0 "DMPR0_B0P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2020++0x3 line.long 0x0 "DMPR0_B1P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2220++0x3 line.long 0x0 "DMPR0_B1P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2420++0x3 line.long 0x0 "DMPR0_B1P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2820++0x3 line.long 0x0 "DMPR0_B1P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A20++0x3 line.long 0x0 "DMPR0_B1P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C20++0x3 line.long 0x0 "DMPR0_B1P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4020++0x3 line.long 0x0 "DMPR0_B2P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4220++0x3 line.long 0x0 "DMPR0_B2P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4420++0x3 line.long 0x0 "DMPR0_B2P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4820++0x3 line.long 0x0 "DMPR0_B2P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A20++0x3 line.long 0x0 "DMPR0_B2P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C20++0x3 line.long 0x0 "DMPR0_B2P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6020++0x3 line.long 0x0 "DMPR0_B3P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6220++0x3 line.long 0x0 "DMPR0_B3P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6420++0x3 line.long 0x0 "DMPR0_B3P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6820++0x3 line.long 0x0 "DMPR0_B3P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A20++0x3 line.long 0x0 "DMPR0_B3P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C20++0x3 line.long 0x0 "DMPR0_B3P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x24++0x3 line.long 0x0 "DMPR1_B0P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x224++0x3 line.long 0x0 "DMPR1_B0P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x424++0x3 line.long 0x0 "DMPR1_B0P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x824++0x3 line.long 0x0 "DMPR1_B0P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA24++0x3 line.long 0x0 "DMPR1_B0P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC24++0x3 line.long 0x0 "DMPR1_B0P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2024++0x3 line.long 0x0 "DMPR1_B1P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2224++0x3 line.long 0x0 "DMPR1_B1P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2424++0x3 line.long 0x0 "DMPR1_B1P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2824++0x3 line.long 0x0 "DMPR1_B1P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A24++0x3 line.long 0x0 "DMPR1_B1P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C24++0x3 line.long 0x0 "DMPR1_B1P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4024++0x3 line.long 0x0 "DMPR1_B2P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4224++0x3 line.long 0x0 "DMPR1_B2P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4424++0x3 line.long 0x0 "DMPR1_B2P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4824++0x3 line.long 0x0 "DMPR1_B2P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A24++0x3 line.long 0x0 "DMPR1_B2P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C24++0x3 line.long 0x0 "DMPR1_B2P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6024++0x3 line.long 0x0 "DMPR1_B3P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6224++0x3 line.long 0x0 "DMPR1_B3P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6424++0x3 line.long 0x0 "DMPR1_B3P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6824++0x3 line.long 0x0 "DMPR1_B3P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A24++0x3 line.long 0x0 "DMPR1_B3P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C24++0x3 line.long 0x0 "DMPR1_B3P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x28++0x3 line.long 0x0 "DMPR2_B0P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x228++0x3 line.long 0x0 "DMPR2_B0P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x428++0x3 line.long 0x0 "DMPR2_B0P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x828++0x3 line.long 0x0 "DMPR2_B0P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA28++0x3 line.long 0x0 "DMPR2_B0P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC28++0x3 line.long 0x0 "DMPR2_B0P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2028++0x3 line.long 0x0 "DMPR2_B1P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2228++0x3 line.long 0x0 "DMPR2_B1P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2428++0x3 line.long 0x0 "DMPR2_B1P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2828++0x3 line.long 0x0 "DMPR2_B1P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A28++0x3 line.long 0x0 "DMPR2_B1P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C28++0x3 line.long 0x0 "DMPR2_B1P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4028++0x3 line.long 0x0 "DMPR2_B2P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4228++0x3 line.long 0x0 "DMPR2_B2P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4428++0x3 line.long 0x0 "DMPR2_B2P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4828++0x3 line.long 0x0 "DMPR2_B2P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A28++0x3 line.long 0x0 "DMPR2_B2P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C28++0x3 line.long 0x0 "DMPR2_B2P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6028++0x3 line.long 0x0 "DMPR2_B3P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6228++0x3 line.long 0x0 "DMPR2_B3P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6428++0x3 line.long 0x0 "DMPR2_B3P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6828++0x3 line.long 0x0 "DMPR2_B3P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A28++0x3 line.long 0x0 "DMPR2_B3P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C28++0x3 line.long 0x0 "DMPR2_B3P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C++0x3 line.long 0x0 "DMPR3_B0P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x22C++0x3 line.long 0x0 "DMPR3_B0P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x42C++0x3 line.long 0x0 "DMPR3_B0P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x82C++0x3 line.long 0x0 "DMPR3_B0P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA2C++0x3 line.long 0x0 "DMPR3_B0P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC2C++0x3 line.long 0x0 "DMPR3_B0P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x202C++0x3 line.long 0x0 "DMPR3_B1P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x222C++0x3 line.long 0x0 "DMPR3_B1P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x242C++0x3 line.long 0x0 "DMPR3_B1P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x282C++0x3 line.long 0x0 "DMPR3_B1P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A2C++0x3 line.long 0x0 "DMPR3_B1P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C2C++0x3 line.long 0x0 "DMPR3_B1P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x402C++0x3 line.long 0x0 "DMPR3_B2P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x422C++0x3 line.long 0x0 "DMPR3_B2P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x442C++0x3 line.long 0x0 "DMPR3_B2P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x482C++0x3 line.long 0x0 "DMPR3_B2P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A2C++0x3 line.long 0x0 "DMPR3_B2P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C2C++0x3 line.long 0x0 "DMPR3_B2P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x602C++0x3 line.long 0x0 "DMPR3_B3P4T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x622C++0x3 line.long 0x0 "DMPR3_B3P4T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x642C++0x3 line.long 0x0 "DMPR3_B3P4T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x682C++0x3 line.long 0x0 "DMPR3_B3P5T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A2C++0x3 line.long 0x0 "DMPR3_B3P5T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C2C++0x3 line.long 0x0 "DMPR3_B3P5T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C++0x3 line.long 0x0 "IP3SR_B0P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x26C++0x3 line.long 0x0 "IP3SR_B0P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x46C++0x3 line.long 0x0 "IP3SR_B0P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x86C++0x3 line.long 0x0 "IP3SR_B0P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xA6C++0x3 line.long 0x0 "IP3SR_B0P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xC6C++0x3 line.long 0x0 "IP3SR_B0P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x206C++0x3 line.long 0x0 "IP3SR_B1P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x226C++0x3 line.long 0x0 "IP3SR_B1P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x246C++0x3 line.long 0x0 "IP3SR_B1P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x286C++0x3 line.long 0x0 "IP3SR_B1P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2A6C++0x3 line.long 0x0 "IP3SR_B1P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2C6C++0x3 line.long 0x0 "IP3SR_B1P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x406C++0x3 line.long 0x0 "IP3SR_B2P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x426C++0x3 line.long 0x0 "IP3SR_B2P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x446C++0x3 line.long 0x0 "IP3SR_B2P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x486C++0x3 line.long 0x0 "IP3SR_B2P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4A6C++0x3 line.long 0x0 "IP3SR_B2P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4C6C++0x3 line.long 0x0 "IP3SR_B2P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x606C++0x3 line.long 0x0 "IP3SR_B3P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x626C++0x3 line.long 0x0 "IP3SR_B3P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x646C++0x3 line.long 0x0 "IP3SR_B3P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x686C++0x3 line.long 0x0 "IP3SR_B3P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6A6C++0x3 line.long 0x0 "IP3SR_B3P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6C6C++0x3 line.long 0x0 "IP3SR_B3P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x84++0x3 line.long 0x0 "DRV1CTRL_B0P4T0,DRV Control Register1 B0P4T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x284++0x3 line.long 0x0 "DRV1CTRL_B0P4T1,DRV Control Register1 B0P4T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x484++0x3 line.long 0x0 "DRV1CTRL_B0P4T2,DRV Control Register1 B0P4T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x884++0x3 line.long 0x0 "DRV1CTRL_B0P5T0,DRV Control Register1 B0P5T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0xA84++0x3 line.long 0x0 "DRV1CTRL_B0P5T1,DRV Control Register1 B0P5T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0xC84++0x3 line.long 0x0 "DRV1CTRL_B0P5T2,DRV Control Register1 B0P5T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2084++0x3 line.long 0x0 "DRV1CTRL_B1P4T0,DRV Control Register1 B1P4T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2284++0x3 line.long 0x0 "DRV1CTRL_B1P4T1,DRV Control Register1 B1P4T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2484++0x3 line.long 0x0 "DRV1CTRL_B1P4T2,DRV Control Register1 B1P4T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2884++0x3 line.long 0x0 "DRV1CTRL_B1P5T0,DRV Control Register1 B1P5T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2A84++0x3 line.long 0x0 "DRV1CTRL_B1P5T1,DRV Control Register1 B1P5T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2C84++0x3 line.long 0x0 "DRV1CTRL_B1P5T2,DRV Control Register1 B1P5T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4084++0x3 line.long 0x0 "DRV1CTRL_B2P4T0,DRV Control Register1 B2P4T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4284++0x3 line.long 0x0 "DRV1CTRL_B2P4T1,DRV Control Register1 B2P4T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4484++0x3 line.long 0x0 "DRV1CTRL_B2P4T2,DRV Control Register1 B2P4T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4884++0x3 line.long 0x0 "DRV1CTRL_B2P5T0,DRV Control Register1 B2P5T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4A84++0x3 line.long 0x0 "DRV1CTRL_B2P5T1,DRV Control Register1 B2P5T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4C84++0x3 line.long 0x0 "DRV1CTRL_B2P5T2,DRV Control Register1 B2P5T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6084++0x3 line.long 0x0 "DRV1CTRL_B3P4T0,DRV Control Register1 B3P4T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6284++0x3 line.long 0x0 "DRV1CTRL_B3P4T1,DRV Control Register1 B3P4T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6484++0x3 line.long 0x0 "DRV1CTRL_B3P4T2,DRV Control Register1 B3P4T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6884++0x3 line.long 0x0 "DRV1CTRL_B3P5T0,DRV Control Register1 B3P5T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6A84++0x3 line.long 0x0 "DRV1CTRL_B3P5T1,DRV Control Register1 B3P5T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6C84++0x3 line.long 0x0 "DRV1CTRL_B3P5T2,DRV Control Register1 B3P5T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x100++0x3 line.long 0x0 "MODSEL_B0P4T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x300++0x3 line.long 0x0 "MODSEL_B0P4T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x500++0x3 line.long 0x0 "MODSEL_B0P4T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x900++0x3 line.long 0x0 "MODSEL_B0P5T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0xB00++0x3 line.long 0x0 "MODSEL_B0P5T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0xD00++0x3 line.long 0x0 "MODSEL_B0P5T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2100++0x3 line.long 0x0 "MODSEL_B1P4T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2300++0x3 line.long 0x0 "MODSEL_B1P4T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2500++0x3 line.long 0x0 "MODSEL_B1P4T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2900++0x3 line.long 0x0 "MODSEL_B1P5T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2B00++0x3 line.long 0x0 "MODSEL_B1P5T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2D00++0x3 line.long 0x0 "MODSEL_B1P5T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4100++0x3 line.long 0x0 "MODSEL_B2P4T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4300++0x3 line.long 0x0 "MODSEL_B2P4T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4500++0x3 line.long 0x0 "MODSEL_B2P4T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4900++0x3 line.long 0x0 "MODSEL_B2P5T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4B00++0x3 line.long 0x0 "MODSEL_B2P5T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4D00++0x3 line.long 0x0 "MODSEL_B2P5T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6100++0x3 line.long 0x0 "MODSEL_B3P4T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6300++0x3 line.long 0x0 "MODSEL_B3P4T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6500++0x3 line.long 0x0 "MODSEL_B3P4T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6900++0x3 line.long 0x0 "MODSEL_B3P5T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6B00++0x3 line.long 0x0 "MODSEL_B3P5T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6D00++0x3 line.long 0x0 "MODSEL_B3P5T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x120++0x3 line.long 0x0 "TD0SEL_B0P4T0,TDSEL Control Register0 B0P4T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x320++0x3 line.long 0x0 "TD0SEL_B0P4T1,TDSEL Control Register0 B0P4T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x520++0x3 line.long 0x0 "TD0SEL_B0P4T2,TDSEL Control Register0 B0P4T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x920++0x3 line.long 0x0 "TD0SEL_B0P5T0,TDSEL Control Register0 B0P5T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0xB20++0x3 line.long 0x0 "TD0SEL_B0P5T1,TDSEL Control Register0 B0P5T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0xD20++0x3 line.long 0x0 "TD0SEL_B0P5T2,TDSEL Control Register0 B0P5T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2120++0x3 line.long 0x0 "TD0SEL_B1P4T0,TDSEL Control Register0 B1P4T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2320++0x3 line.long 0x0 "TD0SEL_B1P4T1,TDSEL Control Register0 B1P4T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2520++0x3 line.long 0x0 "TD0SEL_B1P4T2,TDSEL Control Register0 B1P4T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2920++0x3 line.long 0x0 "TD0SEL_B1P5T0,TDSEL Control Register0 B1P5T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2B20++0x3 line.long 0x0 "TD0SEL_B1P5T1,TDSEL Control Register0 B1P5T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2D20++0x3 line.long 0x0 "TD0SEL_B1P5T2,TDSEL Control Register0 B1P5T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4120++0x3 line.long 0x0 "TD0SEL_B2P4T0,TDSEL Control Register0 B2P4T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4320++0x3 line.long 0x0 "TD0SEL_B2P4T1,TDSEL Control Register0 B2P4T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4520++0x3 line.long 0x0 "TD0SEL_B2P4T2,TDSEL Control Register0 B2P4T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4920++0x3 line.long 0x0 "TD0SEL_B2P5T0,TDSEL Control Register0 B2P5T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4B20++0x3 line.long 0x0 "TD0SEL_B2P5T1,TDSEL Control Register0 B2P5T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4D20++0x3 line.long 0x0 "TD0SEL_B2P5T2,TDSEL Control Register0 B2P5T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6120++0x3 line.long 0x0 "TD0SEL_B3P4T0,TDSEL Control Register0 B3P4T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6320++0x3 line.long 0x0 "TD0SEL_B3P4T1,TDSEL Control Register0 B3P4T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6520++0x3 line.long 0x0 "TD0SEL_B3P4T2,TDSEL Control Register0 B3P4T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6920++0x3 line.long 0x0 "TD0SEL_B3P5T0,TDSEL Control Register0 B3P5T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6B20++0x3 line.long 0x0 "TD0SEL_B3P5T1,TDSEL Control Register0 B3P5T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6D20++0x3 line.long 0x0 "TD0SEL_B3P5T2,TDSEL Control Register0 B3P5T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x124++0x3 line.long 0x0 "TD1SEL_B0P4T0,TDSEL Control Register1 B0P4T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x324++0x3 line.long 0x0 "TD1SEL_B0P4T1,TDSEL Control Register1 B0P4T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x524++0x3 line.long 0x0 "TD1SEL_B0P4T2,TDSEL Control Register1 B0P4T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x924++0x3 line.long 0x0 "TD1SEL_B0P5T0,TDSEL Control Register1 B0P5T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0xB24++0x3 line.long 0x0 "TD1SEL_B0P5T1,TDSEL Control Register1 B0P5T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0xD24++0x3 line.long 0x0 "TD1SEL_B0P5T2,TDSEL Control Register1 B0P5T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2124++0x3 line.long 0x0 "TD1SEL_B1P4T0,TDSEL Control Register1 B1P4T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2324++0x3 line.long 0x0 "TD1SEL_B1P4T1,TDSEL Control Register1 B1P4T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2524++0x3 line.long 0x0 "TD1SEL_B1P4T2,TDSEL Control Register1 B1P4T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2924++0x3 line.long 0x0 "TD1SEL_B1P5T0,TDSEL Control Register1 B1P5T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2B24++0x3 line.long 0x0 "TD1SEL_B1P5T1,TDSEL Control Register1 B1P5T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2D24++0x3 line.long 0x0 "TD1SEL_B1P5T2,TDSEL Control Register1 B1P5T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4124++0x3 line.long 0x0 "TD1SEL_B2P4T0,TDSEL Control Register1 B2P4T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4324++0x3 line.long 0x0 "TD1SEL_B2P4T1,TDSEL Control Register1 B2P4T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4524++0x3 line.long 0x0 "TD1SEL_B2P4T2,TDSEL Control Register1 B2P4T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4924++0x3 line.long 0x0 "TD1SEL_B2P5T0,TDSEL Control Register1 B2P5T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4B24++0x3 line.long 0x0 "TD1SEL_B2P5T1,TDSEL Control Register1 B2P5T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4D24++0x3 line.long 0x0 "TD1SEL_B2P5T2,TDSEL Control Register1 B2P5T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6124++0x3 line.long 0x0 "TD1SEL_B3P4T0,TDSEL Control Register1 B3P4T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6324++0x3 line.long 0x0 "TD1SEL_B3P4T1,TDSEL Control Register1 B3P4T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6524++0x3 line.long 0x0 "TD1SEL_B3P4T2,TDSEL Control Register1 B3P4T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6924++0x3 line.long 0x0 "TD1SEL_B3P5T0,TDSEL Control Register1 B3P5T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6B24++0x3 line.long 0x0 "TD1SEL_B3P5T1,TDSEL Control Register1 B3P5T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6D24++0x3 line.long 0x0 "TD1SEL_B3P5T2,TDSEL Control Register1 B3P5T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x140++0x3 line.long 0x0 "BIPSR0_B0P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x340++0x3 line.long 0x0 "BIPSR0_B0P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x540++0x3 line.long 0x0 "BIPSR0_B0P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x940++0x3 line.long 0x0 "BIPSR0_B0P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB40++0x3 line.long 0x0 "BIPSR0_B0P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD40++0x3 line.long 0x0 "BIPSR0_B0P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2140++0x3 line.long 0x0 "BIPSR0_B1P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2340++0x3 line.long 0x0 "BIPSR0_B1P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2540++0x3 line.long 0x0 "BIPSR0_B1P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2940++0x3 line.long 0x0 "BIPSR0_B1P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B40++0x3 line.long 0x0 "BIPSR0_B1P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D40++0x3 line.long 0x0 "BIPSR0_B1P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4140++0x3 line.long 0x0 "BIPSR0_B2P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4340++0x3 line.long 0x0 "BIPSR0_B2P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4540++0x3 line.long 0x0 "BIPSR0_B2P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4940++0x3 line.long 0x0 "BIPSR0_B2P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B40++0x3 line.long 0x0 "BIPSR0_B2P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D40++0x3 line.long 0x0 "BIPSR0_B2P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6140++0x3 line.long 0x0 "BIPSR0_B3P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6340++0x3 line.long 0x0 "BIPSR0_B3P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6540++0x3 line.long 0x0 "BIPSR0_B3P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6940++0x3 line.long 0x0 "BIPSR0_B3P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B40++0x3 line.long 0x0 "BIPSR0_B3P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D40++0x3 line.long 0x0 "BIPSR0_B3P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x144++0x3 line.long 0x0 "BIPSR1_B0P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x344++0x3 line.long 0x0 "BIPSR1_B0P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x544++0x3 line.long 0x0 "BIPSR1_B0P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x944++0x3 line.long 0x0 "BIPSR1_B0P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB44++0x3 line.long 0x0 "BIPSR1_B0P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD44++0x3 line.long 0x0 "BIPSR1_B0P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2144++0x3 line.long 0x0 "BIPSR1_B1P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2344++0x3 line.long 0x0 "BIPSR1_B1P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2544++0x3 line.long 0x0 "BIPSR1_B1P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2944++0x3 line.long 0x0 "BIPSR1_B1P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B44++0x3 line.long 0x0 "BIPSR1_B1P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D44++0x3 line.long 0x0 "BIPSR1_B1P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4144++0x3 line.long 0x0 "BIPSR1_B2P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4344++0x3 line.long 0x0 "BIPSR1_B2P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4544++0x3 line.long 0x0 "BIPSR1_B2P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4944++0x3 line.long 0x0 "BIPSR1_B2P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B44++0x3 line.long 0x0 "BIPSR1_B2P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D44++0x3 line.long 0x0 "BIPSR1_B2P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6144++0x3 line.long 0x0 "BIPSR1_B3P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6344++0x3 line.long 0x0 "BIPSR1_B3P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6544++0x3 line.long 0x0 "BIPSR1_B3P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6944++0x3 line.long 0x0 "BIPSR1_B3P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B44++0x3 line.long 0x0 "BIPSR1_B3P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D44++0x3 line.long 0x0 "BIPSR1_B3P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x148++0x3 line.long 0x0 "BIPSR2_B0P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x348++0x3 line.long 0x0 "BIPSR2_B0P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x548++0x3 line.long 0x0 "BIPSR2_B0P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x948++0x3 line.long 0x0 "BIPSR2_B0P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB48++0x3 line.long 0x0 "BIPSR2_B0P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD48++0x3 line.long 0x0 "BIPSR2_B0P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2148++0x3 line.long 0x0 "BIPSR2_B1P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2348++0x3 line.long 0x0 "BIPSR2_B1P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2548++0x3 line.long 0x0 "BIPSR2_B1P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2948++0x3 line.long 0x0 "BIPSR2_B1P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B48++0x3 line.long 0x0 "BIPSR2_B1P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D48++0x3 line.long 0x0 "BIPSR2_B1P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4148++0x3 line.long 0x0 "BIPSR2_B2P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4348++0x3 line.long 0x0 "BIPSR2_B2P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4548++0x3 line.long 0x0 "BIPSR2_B2P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4948++0x3 line.long 0x0 "BIPSR2_B2P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B48++0x3 line.long 0x0 "BIPSR2_B2P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D48++0x3 line.long 0x0 "BIPSR2_B2P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6148++0x3 line.long 0x0 "BIPSR2_B3P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6348++0x3 line.long 0x0 "BIPSR2_B3P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6548++0x3 line.long 0x0 "BIPSR2_B3P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6948++0x3 line.long 0x0 "BIPSR2_B3P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B48++0x3 line.long 0x0 "BIPSR2_B3P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D48++0x3 line.long 0x0 "BIPSR2_B3P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x14C++0x3 line.long 0x0 "BIPSR3_B0P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x34C++0x3 line.long 0x0 "BIPSR3_B0P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x54C++0x3 line.long 0x0 "BIPSR3_B0P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x94C++0x3 line.long 0x0 "BIPSR3_B0P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB4C++0x3 line.long 0x0 "BIPSR3_B0P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD4C++0x3 line.long 0x0 "BIPSR3_B0P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x214C++0x3 line.long 0x0 "BIPSR3_B1P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x234C++0x3 line.long 0x0 "BIPSR3_B1P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x254C++0x3 line.long 0x0 "BIPSR3_B1P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x294C++0x3 line.long 0x0 "BIPSR3_B1P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B4C++0x3 line.long 0x0 "BIPSR3_B1P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D4C++0x3 line.long 0x0 "BIPSR3_B1P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x414C++0x3 line.long 0x0 "BIPSR3_B2P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x434C++0x3 line.long 0x0 "BIPSR3_B2P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x454C++0x3 line.long 0x0 "BIPSR3_B2P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x494C++0x3 line.long 0x0 "BIPSR3_B2P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B4C++0x3 line.long 0x0 "BIPSR3_B2P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D4C++0x3 line.long 0x0 "BIPSR3_B2P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x614C++0x3 line.long 0x0 "BIPSR3_B3P4T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x634C++0x3 line.long 0x0 "BIPSR3_B3P4T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x654C++0x3 line.long 0x0 "BIPSR3_B3P4T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x694C++0x3 line.long 0x0 "BIPSR3_B3P5T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B4C++0x3 line.long 0x0 "BIPSR3_B3P5T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D4C++0x3 line.long 0x0 "BIPSR3_B3P5T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x160++0x3 line.long 0x0 "PSER_B0P4T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x360++0x3 line.long 0x0 "PSER_B0P4T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x560++0x3 line.long 0x0 "PSER_B0P4T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x960++0x3 line.long 0x0 "PSER_B0P5T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0xB60++0x3 line.long 0x0 "PSER_B0P5T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0xD60++0x3 line.long 0x0 "PSER_B0P5T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2160++0x3 line.long 0x0 "PSER_B1P4T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2360++0x3 line.long 0x0 "PSER_B1P4T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2560++0x3 line.long 0x0 "PSER_B1P4T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2960++0x3 line.long 0x0 "PSER_B1P5T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2B60++0x3 line.long 0x0 "PSER_B1P5T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2D60++0x3 line.long 0x0 "PSER_B1P5T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4160++0x3 line.long 0x0 "PSER_B2P4T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4360++0x3 line.long 0x0 "PSER_B2P4T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4560++0x3 line.long 0x0 "PSER_B2P4T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4960++0x3 line.long 0x0 "PSER_B2P5T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4B60++0x3 line.long 0x0 "PSER_B2P5T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4D60++0x3 line.long 0x0 "PSER_B2P5T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6160++0x3 line.long 0x0 "PSER_B3P4T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6360++0x3 line.long 0x0 "PSER_B3P4T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6560++0x3 line.long 0x0 "PSER_B3P4T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6960++0x3 line.long 0x0 "PSER_B3P5T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6B60++0x3 line.long 0x0 "PSER_B3P5T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6D60++0x3 line.long 0x0 "PSER_B3P5T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x164++0x3 line.long 0x0 "PS0SR_B0P4T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x364++0x3 line.long 0x0 "PS0SR_B0P4T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x564++0x3 line.long 0x0 "PS0SR_B0P4T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x964++0x3 line.long 0x0 "PS0SR_B0P5T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0xB64++0x3 line.long 0x0 "PS0SR_B0P5T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0xD64++0x3 line.long 0x0 "PS0SR_B0P5T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2164++0x3 line.long 0x0 "PS0SR_B1P4T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2364++0x3 line.long 0x0 "PS0SR_B1P4T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2564++0x3 line.long 0x0 "PS0SR_B1P4T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2964++0x3 line.long 0x0 "PS0SR_B1P5T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2B64++0x3 line.long 0x0 "PS0SR_B1P5T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2D64++0x3 line.long 0x0 "PS0SR_B1P5T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4164++0x3 line.long 0x0 "PS0SR_B2P4T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4364++0x3 line.long 0x0 "PS0SR_B2P4T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4564++0x3 line.long 0x0 "PS0SR_B2P4T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4964++0x3 line.long 0x0 "PS0SR_B2P5T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4B64++0x3 line.long 0x0 "PS0SR_B2P5T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4D64++0x3 line.long 0x0 "PS0SR_B2P5T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6164++0x3 line.long 0x0 "PS0SR_B3P4T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6364++0x3 line.long 0x0 "PS0SR_B3P4T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6564++0x3 line.long 0x0 "PS0SR_B3P4T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6964++0x3 line.long 0x0 "PS0SR_B3P5T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6B64++0x3 line.long 0x0 "PS0SR_B3P5T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6D64++0x3 line.long 0x0 "PS0SR_B3P5T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x168++0x3 line.long 0x0 "PS1SR_B0P4T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x368++0x3 line.long 0x0 "PS1SR_B0P4T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x568++0x3 line.long 0x0 "PS1SR_B0P4T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x968++0x3 line.long 0x0 "PS1SR_B0P5T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0xB68++0x3 line.long 0x0 "PS1SR_B0P5T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0xD68++0x3 line.long 0x0 "PS1SR_B0P5T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2168++0x3 line.long 0x0 "PS1SR_B1P4T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2368++0x3 line.long 0x0 "PS1SR_B1P4T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2568++0x3 line.long 0x0 "PS1SR_B1P4T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2968++0x3 line.long 0x0 "PS1SR_B1P5T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2B68++0x3 line.long 0x0 "PS1SR_B1P5T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2D68++0x3 line.long 0x0 "PS1SR_B1P5T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4168++0x3 line.long 0x0 "PS1SR_B2P4T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4368++0x3 line.long 0x0 "PS1SR_B2P4T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4568++0x3 line.long 0x0 "PS1SR_B2P4T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4968++0x3 line.long 0x0 "PS1SR_B2P5T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4B68++0x3 line.long 0x0 "PS1SR_B2P5T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4D68++0x3 line.long 0x0 "PS1SR_B2P5T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6168++0x3 line.long 0x0 "PS1SR_B3P4T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6368++0x3 line.long 0x0 "PS1SR_B3P4T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6568++0x3 line.long 0x0 "PS1SR_B3P4T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6968++0x3 line.long 0x0 "PS1SR_B3P5T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6B68++0x3 line.long 0x0 "PS1SR_B3P5T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6D68++0x3 line.long 0x0 "PS1SR_B3P5T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x180++0x3 line.long 0x0 "IOINTSEL_B0P4T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x380++0x3 line.long 0x0 "IOINTSEL_B0P4T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x580++0x3 line.long 0x0 "IOINTSEL_B0P4T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x980++0x3 line.long 0x0 "IOINTSEL_B0P5T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0xB80++0x3 line.long 0x0 "IOINTSEL_B0P5T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0xD80++0x3 line.long 0x0 "IOINTSEL_B0P5T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2180++0x3 line.long 0x0 "IOINTSEL_B1P4T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2380++0x3 line.long 0x0 "IOINTSEL_B1P4T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2580++0x3 line.long 0x0 "IOINTSEL_B1P4T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2980++0x3 line.long 0x0 "IOINTSEL_B1P5T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2B80++0x3 line.long 0x0 "IOINTSEL_B1P5T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2D80++0x3 line.long 0x0 "IOINTSEL_B1P5T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4180++0x3 line.long 0x0 "IOINTSEL_B2P4T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4380++0x3 line.long 0x0 "IOINTSEL_B2P4T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4580++0x3 line.long 0x0 "IOINTSEL_B2P4T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4980++0x3 line.long 0x0 "IOINTSEL_B2P5T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4B80++0x3 line.long 0x0 "IOINTSEL_B2P5T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4D80++0x3 line.long 0x0 "IOINTSEL_B2P5T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6180++0x3 line.long 0x0 "IOINTSEL_B3P4T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6380++0x3 line.long 0x0 "IOINTSEL_B3P4T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6580++0x3 line.long 0x0 "IOINTSEL_B3P4T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6980++0x3 line.long 0x0 "IOINTSEL_B3P5T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6B80++0x3 line.long 0x0 "IOINTSEL_B3P5T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6D80++0x3 line.long 0x0 "IOINTSEL_B3P5T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x184++0x3 line.long 0x0 "INOUTSEL_B0P4T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x384++0x3 line.long 0x0 "INOUTSEL_B0P4T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x584++0x3 line.long 0x0 "INOUTSEL_B0P4T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x984++0x3 line.long 0x0 "INOUTSEL_B0P5T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0xB84++0x3 line.long 0x0 "INOUTSEL_B0P5T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0xD84++0x3 line.long 0x0 "INOUTSEL_B0P5T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2184++0x3 line.long 0x0 "INOUTSEL_B1P4T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2384++0x3 line.long 0x0 "INOUTSEL_B1P4T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2584++0x3 line.long 0x0 "INOUTSEL_B1P4T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2984++0x3 line.long 0x0 "INOUTSEL_B1P5T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2B84++0x3 line.long 0x0 "INOUTSEL_B1P5T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2D84++0x3 line.long 0x0 "INOUTSEL_B1P5T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4184++0x3 line.long 0x0 "INOUTSEL_B2P4T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4384++0x3 line.long 0x0 "INOUTSEL_B2P4T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4584++0x3 line.long 0x0 "INOUTSEL_B2P4T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4984++0x3 line.long 0x0 "INOUTSEL_B2P5T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4B84++0x3 line.long 0x0 "INOUTSEL_B2P5T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4D84++0x3 line.long 0x0 "INOUTSEL_B2P5T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6184++0x3 line.long 0x0 "INOUTSEL_B3P4T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6384++0x3 line.long 0x0 "INOUTSEL_B3P4T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6584++0x3 line.long 0x0 "INOUTSEL_B3P4T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6984++0x3 line.long 0x0 "INOUTSEL_B3P5T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6B84++0x3 line.long 0x0 "INOUTSEL_B3P5T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6D84++0x3 line.long 0x0 "INOUTSEL_B3P5T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x188++0x3 line.long 0x0 "OUTDT_B0P4T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x388++0x3 line.long 0x0 "OUTDT_B0P4T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x588++0x3 line.long 0x0 "OUTDT_B0P4T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x988++0x3 line.long 0x0 "OUTDT_B0P5T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0xB88++0x3 line.long 0x0 "OUTDT_B0P5T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0xD88++0x3 line.long 0x0 "OUTDT_B0P5T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2188++0x3 line.long 0x0 "OUTDT_B1P4T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2388++0x3 line.long 0x0 "OUTDT_B1P4T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2588++0x3 line.long 0x0 "OUTDT_B1P4T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2988++0x3 line.long 0x0 "OUTDT_B1P5T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2B88++0x3 line.long 0x0 "OUTDT_B1P5T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2D88++0x3 line.long 0x0 "OUTDT_B1P5T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4188++0x3 line.long 0x0 "OUTDT_B2P4T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4388++0x3 line.long 0x0 "OUTDT_B2P4T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4588++0x3 line.long 0x0 "OUTDT_B2P4T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4988++0x3 line.long 0x0 "OUTDT_B2P5T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4B88++0x3 line.long 0x0 "OUTDT_B2P5T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4D88++0x3 line.long 0x0 "OUTDT_B2P5T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6188++0x3 line.long 0x0 "OUTDT_B3P4T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6388++0x3 line.long 0x0 "OUTDT_B3P4T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6588++0x3 line.long 0x0 "OUTDT_B3P4T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6988++0x3 line.long 0x0 "OUTDT_B3P5T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6B88++0x3 line.long 0x0 "OUTDT_B3P5T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6D88++0x3 line.long 0x0 "OUTDT_B3P5T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." rgroup.long 0x18C++0x3 line.long 0x0 "INDT_B0P4T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x38C++0x3 line.long 0x0 "INDT_B0P4T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x58C++0x3 line.long 0x0 "INDT_B0P4T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x98C++0x3 line.long 0x0 "INDT_B0P5T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0xB8C++0x3 line.long 0x0 "INDT_B0P5T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0xD8C++0x3 line.long 0x0 "INDT_B0P5T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x218C++0x3 line.long 0x0 "INDT_B1P4T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x238C++0x3 line.long 0x0 "INDT_B1P4T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x258C++0x3 line.long 0x0 "INDT_B1P4T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x298C++0x3 line.long 0x0 "INDT_B1P5T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x2B8C++0x3 line.long 0x0 "INDT_B1P5T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x2D8C++0x3 line.long 0x0 "INDT_B1P5T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x418C++0x3 line.long 0x0 "INDT_B2P4T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x438C++0x3 line.long 0x0 "INDT_B2P4T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x458C++0x3 line.long 0x0 "INDT_B2P4T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x498C++0x3 line.long 0x0 "INDT_B2P5T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x4B8C++0x3 line.long 0x0 "INDT_B2P5T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x4D8C++0x3 line.long 0x0 "INDT_B2P5T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x618C++0x3 line.long 0x0 "INDT_B3P4T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x638C++0x3 line.long 0x0 "INDT_B3P4T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x658C++0x3 line.long 0x0 "INDT_B3P4T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x698C++0x3 line.long 0x0 "INDT_B3P5T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x6B8C++0x3 line.long 0x0 "INDT_B3P5T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x6D8C++0x3 line.long 0x0 "INDT_B3P5T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x190++0x3 line.long 0x0 "INTDT_B0P4T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x390++0x3 line.long 0x0 "INTDT_B0P4T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x590++0x3 line.long 0x0 "INTDT_B0P4T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x990++0x3 line.long 0x0 "INTDT_B0P5T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0xB90++0x3 line.long 0x0 "INTDT_B0P5T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0xD90++0x3 line.long 0x0 "INTDT_B0P5T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2190++0x3 line.long 0x0 "INTDT_B1P4T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2390++0x3 line.long 0x0 "INTDT_B1P4T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2590++0x3 line.long 0x0 "INTDT_B1P4T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2990++0x3 line.long 0x0 "INTDT_B1P5T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2B90++0x3 line.long 0x0 "INTDT_B1P5T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2D90++0x3 line.long 0x0 "INTDT_B1P5T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4190++0x3 line.long 0x0 "INTDT_B2P4T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4390++0x3 line.long 0x0 "INTDT_B2P4T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4590++0x3 line.long 0x0 "INTDT_B2P4T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4990++0x3 line.long 0x0 "INTDT_B2P5T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4B90++0x3 line.long 0x0 "INTDT_B2P5T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4D90++0x3 line.long 0x0 "INTDT_B2P5T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6190++0x3 line.long 0x0 "INTDT_B3P4T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6390++0x3 line.long 0x0 "INTDT_B3P4T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6590++0x3 line.long 0x0 "INTDT_B3P4T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6990++0x3 line.long 0x0 "INTDT_B3P5T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6B90++0x3 line.long 0x0 "INTDT_B3P5T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6D90++0x3 line.long 0x0 "INTDT_B3P5T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." group.long 0x194++0x3 line.long 0x0 "INTCLR_B0P4T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x394++0x3 line.long 0x0 "INTCLR_B0P4T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x594++0x3 line.long 0x0 "INTCLR_B0P4T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x994++0x3 line.long 0x0 "INTCLR_B0P5T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0xB94++0x3 line.long 0x0 "INTCLR_B0P5T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0xD94++0x3 line.long 0x0 "INTCLR_B0P5T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2194++0x3 line.long 0x0 "INTCLR_B1P4T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2394++0x3 line.long 0x0 "INTCLR_B1P4T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2594++0x3 line.long 0x0 "INTCLR_B1P4T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2994++0x3 line.long 0x0 "INTCLR_B1P5T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2B94++0x3 line.long 0x0 "INTCLR_B1P5T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2D94++0x3 line.long 0x0 "INTCLR_B1P5T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4194++0x3 line.long 0x0 "INTCLR_B2P4T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4394++0x3 line.long 0x0 "INTCLR_B2P4T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4594++0x3 line.long 0x0 "INTCLR_B2P4T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4994++0x3 line.long 0x0 "INTCLR_B2P5T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4B94++0x3 line.long 0x0 "INTCLR_B2P5T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4D94++0x3 line.long 0x0 "INTCLR_B2P5T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6194++0x3 line.long 0x0 "INTCLR_B3P4T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6394++0x3 line.long 0x0 "INTCLR_B3P4T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6594++0x3 line.long 0x0 "INTCLR_B3P4T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6994++0x3 line.long 0x0 "INTCLR_B3P5T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6B94++0x3 line.long 0x0 "INTCLR_B3P5T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6D94++0x3 line.long 0x0 "INTCLR_B3P5T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x198++0x3 line.long 0x0 "INTMSK_B0P4T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x398++0x3 line.long 0x0 "INTMSK_B0P4T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x598++0x3 line.long 0x0 "INTMSK_B0P4T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x998++0x3 line.long 0x0 "INTMSK_B0P5T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0xB98++0x3 line.long 0x0 "INTMSK_B0P5T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0xD98++0x3 line.long 0x0 "INTMSK_B0P5T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2198++0x3 line.long 0x0 "INTMSK_B1P4T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2398++0x3 line.long 0x0 "INTMSK_B1P4T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2598++0x3 line.long 0x0 "INTMSK_B1P4T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2998++0x3 line.long 0x0 "INTMSK_B1P5T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2B98++0x3 line.long 0x0 "INTMSK_B1P5T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2D98++0x3 line.long 0x0 "INTMSK_B1P5T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4198++0x3 line.long 0x0 "INTMSK_B2P4T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4398++0x3 line.long 0x0 "INTMSK_B2P4T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4598++0x3 line.long 0x0 "INTMSK_B2P4T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4998++0x3 line.long 0x0 "INTMSK_B2P5T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4B98++0x3 line.long 0x0 "INTMSK_B2P5T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4D98++0x3 line.long 0x0 "INTMSK_B2P5T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6198++0x3 line.long 0x0 "INTMSK_B3P4T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6398++0x3 line.long 0x0 "INTMSK_B3P4T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6598++0x3 line.long 0x0 "INTMSK_B3P4T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6998++0x3 line.long 0x0 "INTMSK_B3P5T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6B98++0x3 line.long 0x0 "INTMSK_B3P5T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6D98++0x3 line.long 0x0 "INTMSK_B3P5T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x19C++0x3 line.long 0x0 "MSKCLR_B0P4T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x39C++0x3 line.long 0x0 "MSKCLR_B0P4T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x59C++0x3 line.long 0x0 "MSKCLR_B0P4T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x99C++0x3 line.long 0x0 "MSKCLR_B0P5T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0xB9C++0x3 line.long 0x0 "MSKCLR_B0P5T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0xD9C++0x3 line.long 0x0 "MSKCLR_B0P5T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x219C++0x3 line.long 0x0 "MSKCLR_B1P4T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x239C++0x3 line.long 0x0 "MSKCLR_B1P4T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x259C++0x3 line.long 0x0 "MSKCLR_B1P4T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x299C++0x3 line.long 0x0 "MSKCLR_B1P5T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x2B9C++0x3 line.long 0x0 "MSKCLR_B1P5T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x2D9C++0x3 line.long 0x0 "MSKCLR_B1P5T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x419C++0x3 line.long 0x0 "MSKCLR_B2P4T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x439C++0x3 line.long 0x0 "MSKCLR_B2P4T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x459C++0x3 line.long 0x0 "MSKCLR_B2P4T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x499C++0x3 line.long 0x0 "MSKCLR_B2P5T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x4B9C++0x3 line.long 0x0 "MSKCLR_B2P5T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x4D9C++0x3 line.long 0x0 "MSKCLR_B2P5T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x619C++0x3 line.long 0x0 "MSKCLR_B3P4T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x639C++0x3 line.long 0x0 "MSKCLR_B3P4T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x659C++0x3 line.long 0x0 "MSKCLR_B3P4T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x699C++0x3 line.long 0x0 "MSKCLR_B3P5T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x6B9C++0x3 line.long 0x0 "MSKCLR_B3P5T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x6D9C++0x3 line.long 0x0 "MSKCLR_B3P5T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x1A0++0x3 line.long 0x0 "POSNEG_B0P4T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x3A0++0x3 line.long 0x0 "POSNEG_B0P4T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x5A0++0x3 line.long 0x0 "POSNEG_B0P4T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x9A0++0x3 line.long 0x0 "POSNEG_B0P5T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0xBA0++0x3 line.long 0x0 "POSNEG_B0P5T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0xDA0++0x3 line.long 0x0 "POSNEG_B0P5T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x21A0++0x3 line.long 0x0 "POSNEG_B1P4T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x23A0++0x3 line.long 0x0 "POSNEG_B1P4T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x25A0++0x3 line.long 0x0 "POSNEG_B1P4T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x29A0++0x3 line.long 0x0 "POSNEG_B1P5T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x2BA0++0x3 line.long 0x0 "POSNEG_B1P5T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x2DA0++0x3 line.long 0x0 "POSNEG_B1P5T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x41A0++0x3 line.long 0x0 "POSNEG_B2P4T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x43A0++0x3 line.long 0x0 "POSNEG_B2P4T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x45A0++0x3 line.long 0x0 "POSNEG_B2P4T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x49A0++0x3 line.long 0x0 "POSNEG_B2P5T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x4BA0++0x3 line.long 0x0 "POSNEG_B2P5T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x4DA0++0x3 line.long 0x0 "POSNEG_B2P5T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x61A0++0x3 line.long 0x0 "POSNEG_B3P4T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x63A0++0x3 line.long 0x0 "POSNEG_B3P4T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x65A0++0x3 line.long 0x0 "POSNEG_B3P4T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x69A0++0x3 line.long 0x0 "POSNEG_B3P5T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x6BA0++0x3 line.long 0x0 "POSNEG_B3P5T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x6DA0++0x3 line.long 0x0 "POSNEG_B3P5T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x1A4++0x3 line.long 0x0 "EDGLEVEL_B0P4T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x3A4++0x3 line.long 0x0 "EDGLEVEL_B0P4T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x5A4++0x3 line.long 0x0 "EDGLEVEL_B0P4T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x9A4++0x3 line.long 0x0 "EDGLEVEL_B0P5T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0xBA4++0x3 line.long 0x0 "EDGLEVEL_B0P5T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0xDA4++0x3 line.long 0x0 "EDGLEVEL_B0P5T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x21A4++0x3 line.long 0x0 "EDGLEVEL_B1P4T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x23A4++0x3 line.long 0x0 "EDGLEVEL_B1P4T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x25A4++0x3 line.long 0x0 "EDGLEVEL_B1P4T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x29A4++0x3 line.long 0x0 "EDGLEVEL_B1P5T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x2BA4++0x3 line.long 0x0 "EDGLEVEL_B1P5T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x2DA4++0x3 line.long 0x0 "EDGLEVEL_B1P5T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x41A4++0x3 line.long 0x0 "EDGLEVEL_B2P4T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x43A4++0x3 line.long 0x0 "EDGLEVEL_B2P4T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x45A4++0x3 line.long 0x0 "EDGLEVEL_B2P4T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x49A4++0x3 line.long 0x0 "EDGLEVEL_B2P5T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x4BA4++0x3 line.long 0x0 "EDGLEVEL_B2P5T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x4DA4++0x3 line.long 0x0 "EDGLEVEL_B2P5T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x61A4++0x3 line.long 0x0 "EDGLEVEL_B3P4T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x63A4++0x3 line.long 0x0 "EDGLEVEL_B3P4T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x65A4++0x3 line.long 0x0 "EDGLEVEL_B3P4T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x69A4++0x3 line.long 0x0 "EDGLEVEL_B3P5T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x6BA4++0x3 line.long 0x0 "EDGLEVEL_B3P5T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x6DA4++0x3 line.long 0x0 "EDGLEVEL_B3P5T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x1A8++0x3 line.long 0x0 "FILONOFF_B0P4T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x3A8++0x3 line.long 0x0 "FILONOFF_B0P4T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x5A8++0x3 line.long 0x0 "FILONOFF_B0P4T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x9A8++0x3 line.long 0x0 "FILONOFF_B0P5T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0xBA8++0x3 line.long 0x0 "FILONOFF_B0P5T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0xDA8++0x3 line.long 0x0 "FILONOFF_B0P5T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x21A8++0x3 line.long 0x0 "FILONOFF_B1P4T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x23A8++0x3 line.long 0x0 "FILONOFF_B1P4T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x25A8++0x3 line.long 0x0 "FILONOFF_B1P4T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x29A8++0x3 line.long 0x0 "FILONOFF_B1P5T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x2BA8++0x3 line.long 0x0 "FILONOFF_B1P5T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x2DA8++0x3 line.long 0x0 "FILONOFF_B1P5T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x41A8++0x3 line.long 0x0 "FILONOFF_B2P4T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x43A8++0x3 line.long 0x0 "FILONOFF_B2P4T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x45A8++0x3 line.long 0x0 "FILONOFF_B2P4T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x49A8++0x3 line.long 0x0 "FILONOFF_B2P5T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x4BA8++0x3 line.long 0x0 "FILONOFF_B2P5T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x4DA8++0x3 line.long 0x0 "FILONOFF_B2P5T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x61A8++0x3 line.long 0x0 "FILONOFF_B3P4T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x63A8++0x3 line.long 0x0 "FILONOFF_B3P4T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x65A8++0x3 line.long 0x0 "FILONOFF_B3P4T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x69A8++0x3 line.long 0x0 "FILONOFF_B3P5T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x6BA8++0x3 line.long 0x0 "FILONOFF_B3P5T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x6DA8++0x3 line.long 0x0 "FILONOFF_B3P5T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x1AC++0x3 line.long 0x0 "FILCLKSEL_B0P4T0,Chattering Prevention Clock Select Register B0P4T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x3AC++0x3 line.long 0x0 "FILCLKSEL_B0P4T1,Chattering Prevention Clock Select Register B0P4T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x5AC++0x3 line.long 0x0 "FILCLKSEL_B0P4T2,Chattering Prevention Clock Select Register B0P4T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x9AC++0x3 line.long 0x0 "FILCLKSEL_B0P5T0,Chattering Prevention Clock Select Register B0P5T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0xBAC++0x3 line.long 0x0 "FILCLKSEL_B0P5T1,Chattering Prevention Clock Select Register B0P5T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0xDAC++0x3 line.long 0x0 "FILCLKSEL_B0P5T2,Chattering Prevention Clock Select Register B0P5T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x21AC++0x3 line.long 0x0 "FILCLKSEL_B1P4T0,Chattering Prevention Clock Select Register B1P4T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x23AC++0x3 line.long 0x0 "FILCLKSEL_B1P4T1,Chattering Prevention Clock Select Register B1P4T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x25AC++0x3 line.long 0x0 "FILCLKSEL_B1P4T2,Chattering Prevention Clock Select Register B1P4T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x29AC++0x3 line.long 0x0 "FILCLKSEL_B1P5T0,Chattering Prevention Clock Select Register B1P5T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x2BAC++0x3 line.long 0x0 "FILCLKSEL_B1P5T1,Chattering Prevention Clock Select Register B1P5T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x2DAC++0x3 line.long 0x0 "FILCLKSEL_B1P5T2,Chattering Prevention Clock Select Register B1P5T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x41AC++0x3 line.long 0x0 "FILCLKSEL_B2P4T0,Chattering Prevention Clock Select Register B2P4T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x43AC++0x3 line.long 0x0 "FILCLKSEL_B2P4T1,Chattering Prevention Clock Select Register B2P4T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x45AC++0x3 line.long 0x0 "FILCLKSEL_B2P4T2,Chattering Prevention Clock Select Register B2P4T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x49AC++0x3 line.long 0x0 "FILCLKSEL_B2P5T0,Chattering Prevention Clock Select Register B2P5T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x4BAC++0x3 line.long 0x0 "FILCLKSEL_B2P5T1,Chattering Prevention Clock Select Register B2P5T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x4DAC++0x3 line.long 0x0 "FILCLKSEL_B2P5T2,Chattering Prevention Clock Select Register B2P5T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x61AC++0x3 line.long 0x0 "FILCLKSEL_B3P4T0,Chattering Prevention Clock Select Register B3P4T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x63AC++0x3 line.long 0x0 "FILCLKSEL_B3P4T1,Chattering Prevention Clock Select Register B3P4T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x65AC++0x3 line.long 0x0 "FILCLKSEL_B3P4T2,Chattering Prevention Clock Select Register B3P4T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x69AC++0x3 line.long 0x0 "FILCLKSEL_B3P5T0,Chattering Prevention Clock Select Register B3P5T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x6BAC++0x3 line.long 0x0 "FILCLKSEL_B3P5T1,Chattering Prevention Clock Select Register B3P5T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x6DAC++0x3 line.long 0x0 "FILCLKSEL_B3P5T2,Chattering Prevention Clock Select Register B3P5T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x1C0++0x3 line.long 0x0 "OUTDTSEL_B0P4T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x3C0++0x3 line.long 0x0 "OUTDTSEL_B0P4T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x5C0++0x3 line.long 0x0 "OUTDTSEL_B0P4T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x9C0++0x3 line.long 0x0 "OUTDTSEL_B0P5T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0xBC0++0x3 line.long 0x0 "OUTDTSEL_B0P5T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0xDC0++0x3 line.long 0x0 "OUTDTSEL_B0P5T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x21C0++0x3 line.long 0x0 "OUTDTSEL_B1P4T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x23C0++0x3 line.long 0x0 "OUTDTSEL_B1P4T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x25C0++0x3 line.long 0x0 "OUTDTSEL_B1P4T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x29C0++0x3 line.long 0x0 "OUTDTSEL_B1P5T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x2BC0++0x3 line.long 0x0 "OUTDTSEL_B1P5T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x2DC0++0x3 line.long 0x0 "OUTDTSEL_B1P5T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x41C0++0x3 line.long 0x0 "OUTDTSEL_B2P4T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x43C0++0x3 line.long 0x0 "OUTDTSEL_B2P4T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x45C0++0x3 line.long 0x0 "OUTDTSEL_B2P4T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x49C0++0x3 line.long 0x0 "OUTDTSEL_B2P5T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x4BC0++0x3 line.long 0x0 "OUTDTSEL_B2P5T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x4DC0++0x3 line.long 0x0 "OUTDTSEL_B2P5T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x61C0++0x3 line.long 0x0 "OUTDTSEL_B3P4T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x63C0++0x3 line.long 0x0 "OUTDTSEL_B3P4T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x65C0++0x3 line.long 0x0 "OUTDTSEL_B3P4T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x69C0++0x3 line.long 0x0 "OUTDTSEL_B3P5T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x6BC0++0x3 line.long 0x0 "OUTDTSEL_B3P5T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x6DC0++0x3 line.long 0x0 "OUTDTSEL_B3P5T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x1C4++0x3 line.long 0x0 "OUTDTH_B0P4T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x3C4++0x3 line.long 0x0 "OUTDTH_B0P4T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x5C4++0x3 line.long 0x0 "OUTDTH_B0P4T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x9C4++0x3 line.long 0x0 "OUTDTH_B0P5T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0xBC4++0x3 line.long 0x0 "OUTDTH_B0P5T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0xDC4++0x3 line.long 0x0 "OUTDTH_B0P5T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x21C4++0x3 line.long 0x0 "OUTDTH_B1P4T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x23C4++0x3 line.long 0x0 "OUTDTH_B1P4T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x25C4++0x3 line.long 0x0 "OUTDTH_B1P4T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x29C4++0x3 line.long 0x0 "OUTDTH_B1P5T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x2BC4++0x3 line.long 0x0 "OUTDTH_B1P5T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x2DC4++0x3 line.long 0x0 "OUTDTH_B1P5T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x41C4++0x3 line.long 0x0 "OUTDTH_B2P4T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x43C4++0x3 line.long 0x0 "OUTDTH_B2P4T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x45C4++0x3 line.long 0x0 "OUTDTH_B2P4T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x49C4++0x3 line.long 0x0 "OUTDTH_B2P5T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x4BC4++0x3 line.long 0x0 "OUTDTH_B2P5T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x4DC4++0x3 line.long 0x0 "OUTDTH_B2P5T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x61C4++0x3 line.long 0x0 "OUTDTH_B3P4T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x63C4++0x3 line.long 0x0 "OUTDTH_B3P4T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x65C4++0x3 line.long 0x0 "OUTDTH_B3P4T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x69C4++0x3 line.long 0x0 "OUTDTH_B3P5T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x6BC4++0x3 line.long 0x0 "OUTDTH_B3P5T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x6DC4++0x3 line.long 0x0 "OUTDTH_B3P5T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x1C8++0x3 line.long 0x0 "OUTDTL_B0P4T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x3C8++0x3 line.long 0x0 "OUTDTL_B0P4T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x5C8++0x3 line.long 0x0 "OUTDTL_B0P4T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x9C8++0x3 line.long 0x0 "OUTDTL_B0P5T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0xBC8++0x3 line.long 0x0 "OUTDTL_B0P5T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0xDC8++0x3 line.long 0x0 "OUTDTL_B0P5T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x21C8++0x3 line.long 0x0 "OUTDTL_B1P4T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x23C8++0x3 line.long 0x0 "OUTDTL_B1P4T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x25C8++0x3 line.long 0x0 "OUTDTL_B1P4T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x29C8++0x3 line.long 0x0 "OUTDTL_B1P5T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x2BC8++0x3 line.long 0x0 "OUTDTL_B1P5T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x2DC8++0x3 line.long 0x0 "OUTDTL_B1P5T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x41C8++0x3 line.long 0x0 "OUTDTL_B2P4T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x43C8++0x3 line.long 0x0 "OUTDTL_B2P4T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x45C8++0x3 line.long 0x0 "OUTDTL_B2P4T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x49C8++0x3 line.long 0x0 "OUTDTL_B2P5T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x4BC8++0x3 line.long 0x0 "OUTDTL_B2P5T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x4DC8++0x3 line.long 0x0 "OUTDTL_B2P5T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x61C8++0x3 line.long 0x0 "OUTDTL_B3P4T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x63C8++0x3 line.long 0x0 "OUTDTL_B3P4T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x65C8++0x3 line.long 0x0 "OUTDTL_B3P4T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x69C8++0x3 line.long 0x0 "OUTDTL_B3P5T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x6BC8++0x3 line.long 0x0 "OUTDTL_B3P5T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x6DC8++0x3 line.long 0x0 "OUTDTL_B3P5T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x1CC++0x3 line.long 0x0 "BOTHEDGE_B0P4T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x3CC++0x3 line.long 0x0 "BOTHEDGE_B0P4T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x5CC++0x3 line.long 0x0 "BOTHEDGE_B0P4T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x9CC++0x3 line.long 0x0 "BOTHEDGE_B0P5T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0xBCC++0x3 line.long 0x0 "BOTHEDGE_B0P5T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0xDCC++0x3 line.long 0x0 "BOTHEDGE_B0P5T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x21CC++0x3 line.long 0x0 "BOTHEDGE_B1P4T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x23CC++0x3 line.long 0x0 "BOTHEDGE_B1P4T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x25CC++0x3 line.long 0x0 "BOTHEDGE_B1P4T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x29CC++0x3 line.long 0x0 "BOTHEDGE_B1P5T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x2BCC++0x3 line.long 0x0 "BOTHEDGE_B1P5T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x2DCC++0x3 line.long 0x0 "BOTHEDGE_B1P5T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x41CC++0x3 line.long 0x0 "BOTHEDGE_B2P4T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x43CC++0x3 line.long 0x0 "BOTHEDGE_B2P4T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x45CC++0x3 line.long 0x0 "BOTHEDGE_B2P4T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x49CC++0x3 line.long 0x0 "BOTHEDGE_B2P5T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x4BCC++0x3 line.long 0x0 "BOTHEDGE_B2P5T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x4DCC++0x3 line.long 0x0 "BOTHEDGE_B2P5T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x61CC++0x3 line.long 0x0 "BOTHEDGE_B3P4T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x63CC++0x3 line.long 0x0 "BOTHEDGE_B3P4T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x65CC++0x3 line.long 0x0 "BOTHEDGE_B3P4T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x69CC++0x3 line.long 0x0 "BOTHEDGE_B3P5T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x6BCC++0x3 line.long 0x0 "BOTHEDGE_B3P5T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x6DCC++0x3 line.long 0x0 "BOTHEDGE_B3P5T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x1D0++0x3 line.long 0x0 "INEN_B0P4T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x3D0++0x3 line.long 0x0 "INEN_B0P4T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x5D0++0x3 line.long 0x0 "INEN_B0P4T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x9D0++0x3 line.long 0x0 "INEN_B0P5T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0xBD0++0x3 line.long 0x0 "INEN_B0P5T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0xDD0++0x3 line.long 0x0 "INEN_B0P5T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x21D0++0x3 line.long 0x0 "INEN_B1P4T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x23D0++0x3 line.long 0x0 "INEN_B1P4T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x25D0++0x3 line.long 0x0 "INEN_B1P4T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x29D0++0x3 line.long 0x0 "INEN_B1P5T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x2BD0++0x3 line.long 0x0 "INEN_B1P5T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x2DD0++0x3 line.long 0x0 "INEN_B1P5T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x41D0++0x3 line.long 0x0 "INEN_B2P4T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x43D0++0x3 line.long 0x0 "INEN_B2P4T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x45D0++0x3 line.long 0x0 "INEN_B2P4T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x49D0++0x3 line.long 0x0 "INEN_B2P5T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x4BD0++0x3 line.long 0x0 "INEN_B2P5T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x4DD0++0x3 line.long 0x0 "INEN_B2P5T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x61D0++0x3 line.long 0x0 "INEN_B3P4T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x63D0++0x3 line.long 0x0 "INEN_B3P4T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x65D0++0x3 line.long 0x0 "INEN_B3P4T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x69D0++0x3 line.long 0x0 "INEN_B3P5T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x6BD0++0x3 line.long 0x0 "INEN_B3P5T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x6DD0++0x3 line.long 0x0 "INEN_B3P5T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x88++0x3 line.long 0x0 "DRV2CTRL_B0P4T0,DRV Control Register2 B0P4T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x288++0x3 line.long 0x0 "DRV2CTRL_B0P4T1,DRV Control Register2 B0P4T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x488++0x3 line.long 0x0 "DRV2CTRL_B0P4T2,DRV Control Register2 B0P4T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x888++0x3 line.long 0x0 "DRV2CTRL_B0P5T0,DRV Control Register2 B0P5T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0xA88++0x3 line.long 0x0 "DRV2CTRL_B0P5T1,DRV Control Register2 B0P5T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0xC88++0x3 line.long 0x0 "DRV2CTRL_B0P5T2,DRV Control Register2 B0P5T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2088++0x3 line.long 0x0 "DRV2CTRL_B1P4T0,DRV Control Register2 B1P4T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2288++0x3 line.long 0x0 "DRV2CTRL_B1P4T1,DRV Control Register2 B1P4T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2488++0x3 line.long 0x0 "DRV2CTRL_B1P4T2,DRV Control Register2 B1P4T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2888++0x3 line.long 0x0 "DRV2CTRL_B1P5T0,DRV Control Register2 B1P5T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2A88++0x3 line.long 0x0 "DRV2CTRL_B1P5T1,DRV Control Register2 B1P5T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2C88++0x3 line.long 0x0 "DRV2CTRL_B1P5T2,DRV Control Register2 B1P5T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4088++0x3 line.long 0x0 "DRV2CTRL_B2P4T0,DRV Control Register2 B2P4T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4288++0x3 line.long 0x0 "DRV2CTRL_B2P4T1,DRV Control Register2 B2P4T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4488++0x3 line.long 0x0 "DRV2CTRL_B2P4T2,DRV Control Register2 B2P4T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4888++0x3 line.long 0x0 "DRV2CTRL_B2P5T0,DRV Control Register2 B2P5T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4A88++0x3 line.long 0x0 "DRV2CTRL_B2P5T1,DRV Control Register2 B2P5T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4C88++0x3 line.long 0x0 "DRV2CTRL_B2P5T2,DRV Control Register2 B2P5T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6088++0x3 line.long 0x0 "DRV2CTRL_B3P4T0,DRV Control Register2 B3P4T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6288++0x3 line.long 0x0 "DRV2CTRL_B3P4T1,DRV Control Register2 B3P4T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6488++0x3 line.long 0x0 "DRV2CTRL_B3P4T2,DRV Control Register2 B3P4T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6888++0x3 line.long 0x0 "DRV2CTRL_B3P5T0,DRV Control Register2 B3P5T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6A88++0x3 line.long 0x0 "DRV2CTRL_B3P5T1,DRV Control Register2 B3P5T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6C88++0x3 line.long 0x0 "DRV2CTRL_B3P5T2,DRV Control Register2 B3P5T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x8C++0x3 line.long 0x0 "DRV3CTRL_B0P4T0,DRV Control Register3 B0P4T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x28C++0x3 line.long 0x0 "DRV3CTRL_B0P4T1,DRV Control Register3 B0P4T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x48C++0x3 line.long 0x0 "DRV3CTRL_B0P4T2,DRV Control Register3 B0P4T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x88C++0x3 line.long 0x0 "DRV3CTRL_B0P5T0,DRV Control Register3 B0P5T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0xA8C++0x3 line.long 0x0 "DRV3CTRL_B0P5T1,DRV Control Register3 B0P5T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0xC8C++0x3 line.long 0x0 "DRV3CTRL_B0P5T2,DRV Control Register3 B0P5T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x208C++0x3 line.long 0x0 "DRV3CTRL_B1P4T0,DRV Control Register3 B1P4T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x228C++0x3 line.long 0x0 "DRV3CTRL_B1P4T1,DRV Control Register3 B1P4T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x248C++0x3 line.long 0x0 "DRV3CTRL_B1P4T2,DRV Control Register3 B1P4T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x288C++0x3 line.long 0x0 "DRV3CTRL_B1P5T0,DRV Control Register3 B1P5T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x2A8C++0x3 line.long 0x0 "DRV3CTRL_B1P5T1,DRV Control Register3 B1P5T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x2C8C++0x3 line.long 0x0 "DRV3CTRL_B1P5T2,DRV Control Register3 B1P5T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x408C++0x3 line.long 0x0 "DRV3CTRL_B2P4T0,DRV Control Register3 B2P4T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x428C++0x3 line.long 0x0 "DRV3CTRL_B2P4T1,DRV Control Register3 B2P4T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x448C++0x3 line.long 0x0 "DRV3CTRL_B2P4T2,DRV Control Register3 B2P4T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x488C++0x3 line.long 0x0 "DRV3CTRL_B2P5T0,DRV Control Register3 B2P5T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x4A8C++0x3 line.long 0x0 "DRV3CTRL_B2P5T1,DRV Control Register3 B2P5T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x4C8C++0x3 line.long 0x0 "DRV3CTRL_B2P5T2,DRV Control Register3 B2P5T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x608C++0x3 line.long 0x0 "DRV3CTRL_B3P4T0,DRV Control Register3 B3P4T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x628C++0x3 line.long 0x0 "DRV3CTRL_B3P4T1,DRV Control Register3 B3P4T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x648C++0x3 line.long 0x0 "DRV3CTRL_B3P4T2,DRV Control Register3 B3P4T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x688C++0x3 line.long 0x0 "DRV3CTRL_B3P5T0,DRV Control Register3 B3P5T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x6A8C++0x3 line.long 0x0 "DRV3CTRL_B3P5T1,DRV Control Register3 B3P5T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x6C8C++0x3 line.long 0x0 "DRV3CTRL_B3P5T2,DRV Control Register3 B3P5T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" tree.end tree "PFC_3" base ad:0xE6060000 group.long 0x0++0x3 line.long 0x0 "PMMR_B0P6T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x200++0x3 line.long 0x0 "PMMR_B0P6T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x400++0x3 line.long 0x0 "PMMR_B0P6T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x800++0x3 line.long 0x0 "PMMR_B0P7T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xA00++0x3 line.long 0x0 "PMMR_B0P7T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xC00++0x3 line.long 0x0 "PMMR_B0P7T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1000++0x3 line.long 0x0 "PMMR_B0P8T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1200++0x3 line.long 0x0 "PMMR_B0P8T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1400++0x3 line.long 0x0 "PMMR_B0P8T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1800++0x3 line.long 0x0 "PMMR_B0P9T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1A00++0x3 line.long 0x0 "PMMR_B0P9T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1C00++0x3 line.long 0x0 "PMMR_B0P9T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2000++0x3 line.long 0x0 "PMMR_B1P6T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2200++0x3 line.long 0x0 "PMMR_B1P6T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2400++0x3 line.long 0x0 "PMMR_B1P6T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2800++0x3 line.long 0x0 "PMMR_B1P7T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2A00++0x3 line.long 0x0 "PMMR_B1P7T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2C00++0x3 line.long 0x0 "PMMR_B1P7T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3000++0x3 line.long 0x0 "PMMR_B1P8T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3200++0x3 line.long 0x0 "PMMR_B1P8T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3400++0x3 line.long 0x0 "PMMR_B1P8T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3800++0x3 line.long 0x0 "PMMR_B1P9T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3A00++0x3 line.long 0x0 "PMMR_B1P9T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3C00++0x3 line.long 0x0 "PMMR_B1P9T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4000++0x3 line.long 0x0 "PMMR_B2P6T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4200++0x3 line.long 0x0 "PMMR_B2P6T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4400++0x3 line.long 0x0 "PMMR_B2P6T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4800++0x3 line.long 0x0 "PMMR_B2P7T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4A00++0x3 line.long 0x0 "PMMR_B2P7T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4C00++0x3 line.long 0x0 "PMMR_B2P7T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5000++0x3 line.long 0x0 "PMMR_B2P8T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5200++0x3 line.long 0x0 "PMMR_B2P8T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5400++0x3 line.long 0x0 "PMMR_B2P8T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5800++0x3 line.long 0x0 "PMMR_B2P9T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5A00++0x3 line.long 0x0 "PMMR_B2P9T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5C00++0x3 line.long 0x0 "PMMR_B2P9T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6000++0x3 line.long 0x0 "PMMR_B3P6T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6200++0x3 line.long 0x0 "PMMR_B3P6T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6400++0x3 line.long 0x0 "PMMR_B3P6T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6800++0x3 line.long 0x0 "PMMR_B3P7T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6A00++0x3 line.long 0x0 "PMMR_B3P7T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6C00++0x3 line.long 0x0 "PMMR_B3P7T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7000++0x3 line.long 0x0 "PMMR_B3P8T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7200++0x3 line.long 0x0 "PMMR_B3P8T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7400++0x3 line.long 0x0 "PMMR_B3P8T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7800++0x3 line.long 0x0 "PMMR_B3P9T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7A00++0x3 line.long 0x0 "PMMR_B3P9T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7C00++0x3 line.long 0x0 "PMMR_B3P9T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x40++0x3 line.long 0x0 "GPSR_B0P6T0,GPIO/Peripheral Function Select Register B0P6T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x240++0x3 line.long 0x0 "GPSR_B0P6T1,GPIO/Peripheral Function Select Register B0P6T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x440++0x3 line.long 0x0 "GPSR_B0P6T2,GPIO/Peripheral Function Select Register B0P6T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x40++0x3 line.long 0x0 "GPSR_B0P7T0,GPIO/Peripheral Function Select Register B0P7T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x240++0x3 line.long 0x0 "GPSR_B0P7T1,GPIO/Peripheral Function Select Register B0P7T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x440++0x3 line.long 0x0 "GPSR_B0P7T2,GPIO/Peripheral Function Select Register B0P7T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x40++0x3 line.long 0x0 "GPSR_B0P8T0,GPIO/Peripheral Function Select Register B0P8T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x240++0x3 line.long 0x0 "GPSR_B0P8T1,GPIO/Peripheral Function Select Register B0P8T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x440++0x3 line.long 0x0 "GPSR_B0P8T2,GPIO/Peripheral Function Select Register B0P8T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x40++0x3 line.long 0x0 "GPSR_B0P9T0,GPIO/Peripheral Function Select Register B0P9T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x240++0x3 line.long 0x0 "GPSR_B0P9T1,GPIO/Peripheral Function Select Register B0P9T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x440++0x3 line.long 0x0 "GPSR_B0P9T2,GPIO/Peripheral Function Select Register B0P9T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2040++0x3 line.long 0x0 "GPSR_B1P6T0,GPIO/Peripheral Function Select Register B1P6T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2240++0x3 line.long 0x0 "GPSR_B1P6T1,GPIO/Peripheral Function Select Register B1P6T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2440++0x3 line.long 0x0 "GPSR_B1P6T2,GPIO/Peripheral Function Select Register B1P6T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2040++0x3 line.long 0x0 "GPSR_B1P7T0,GPIO/Peripheral Function Select Register B1P7T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2240++0x3 line.long 0x0 "GPSR_B1P7T1,GPIO/Peripheral Function Select Register B1P7T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2440++0x3 line.long 0x0 "GPSR_B1P7T2,GPIO/Peripheral Function Select Register B1P7T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2040++0x3 line.long 0x0 "GPSR_B1P8T0,GPIO/Peripheral Function Select Register B1P8T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2240++0x3 line.long 0x0 "GPSR_B1P8T1,GPIO/Peripheral Function Select Register B1P8T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2440++0x3 line.long 0x0 "GPSR_B1P8T2,GPIO/Peripheral Function Select Register B1P8T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2040++0x3 line.long 0x0 "GPSR_B1P9T0,GPIO/Peripheral Function Select Register B1P9T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2240++0x3 line.long 0x0 "GPSR_B1P9T1,GPIO/Peripheral Function Select Register B1P9T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x2440++0x3 line.long 0x0 "GPSR_B1P9T2,GPIO/Peripheral Function Select Register B1P9T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4040++0x3 line.long 0x0 "GPSR_B2P6T0,GPIO/Peripheral Function Select Register B2P6T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4240++0x3 line.long 0x0 "GPSR_B2P6T1,GPIO/Peripheral Function Select Register B2P6T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4440++0x3 line.long 0x0 "GPSR_B2P6T2,GPIO/Peripheral Function Select Register B2P6T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4040++0x3 line.long 0x0 "GPSR_B2P7T0,GPIO/Peripheral Function Select Register B2P7T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4240++0x3 line.long 0x0 "GPSR_B2P7T1,GPIO/Peripheral Function Select Register B2P7T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4440++0x3 line.long 0x0 "GPSR_B2P7T2,GPIO/Peripheral Function Select Register B2P7T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4040++0x3 line.long 0x0 "GPSR_B2P8T0,GPIO/Peripheral Function Select Register B2P8T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4240++0x3 line.long 0x0 "GPSR_B2P8T1,GPIO/Peripheral Function Select Register B2P8T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4440++0x3 line.long 0x0 "GPSR_B2P8T2,GPIO/Peripheral Function Select Register B2P8T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4040++0x3 line.long 0x0 "GPSR_B2P9T0,GPIO/Peripheral Function Select Register B2P9T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4240++0x3 line.long 0x0 "GPSR_B2P9T1,GPIO/Peripheral Function Select Register B2P9T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x4440++0x3 line.long 0x0 "GPSR_B2P9T2,GPIO/Peripheral Function Select Register B2P9T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6040++0x3 line.long 0x0 "GPSR_B3P6T0,GPIO/Peripheral Function Select Register B3P6T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6240++0x3 line.long 0x0 "GPSR_B3P6T1,GPIO/Peripheral Function Select Register B3P6T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6440++0x3 line.long 0x0 "GPSR_B3P6T2,GPIO/Peripheral Function Select Register B3P6T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6040++0x3 line.long 0x0 "GPSR_B3P7T0,GPIO/Peripheral Function Select Register B3P7T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6240++0x3 line.long 0x0 "GPSR_B3P7T1,GPIO/Peripheral Function Select Register B3P7T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6440++0x3 line.long 0x0 "GPSR_B3P7T2,GPIO/Peripheral Function Select Register B3P7T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6040++0x3 line.long 0x0 "GPSR_B3P8T0,GPIO/Peripheral Function Select Register B3P8T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6240++0x3 line.long 0x0 "GPSR_B3P8T1,GPIO/Peripheral Function Select Register B3P8T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6440++0x3 line.long 0x0 "GPSR_B3P8T2,GPIO/Peripheral Function Select Register B3P8T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6040++0x3 line.long 0x0 "GPSR_B3P9T0,GPIO/Peripheral Function Select Register B3P9T0" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6240++0x3 line.long 0x0 "GPSR_B3P9T1,GPIO/Peripheral Function Select Register B3P9T1" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x6440++0x3 line.long 0x0 "GPSR_B3P9T2,GPIO/Peripheral Function Select Register B3P9T2" hexmask.long 0x0 0.--31. 1. "GPSR" group.long 0x60++0x3 line.long 0x0 "IP0SR_B0P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x260++0x3 line.long 0x0 "IP0SR_B0P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x460++0x3 line.long 0x0 "IP0SR_B0P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x60++0x3 line.long 0x0 "IP0SR_B0P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x260++0x3 line.long 0x0 "IP0SR_B0P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x460++0x3 line.long 0x0 "IP0SR_B0P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x60++0x3 line.long 0x0 "IP0SR_B0P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x260++0x3 line.long 0x0 "IP0SR_B0P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x460++0x3 line.long 0x0 "IP0SR_B0P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x60++0x3 line.long 0x0 "IP0SR_B0P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x260++0x3 line.long 0x0 "IP0SR_B0P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x460++0x3 line.long 0x0 "IP0SR_B0P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2060++0x3 line.long 0x0 "IP0SR_B1P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2260++0x3 line.long 0x0 "IP0SR_B1P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2460++0x3 line.long 0x0 "IP0SR_B1P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2060++0x3 line.long 0x0 "IP0SR_B1P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2260++0x3 line.long 0x0 "IP0SR_B1P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2460++0x3 line.long 0x0 "IP0SR_B1P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2060++0x3 line.long 0x0 "IP0SR_B1P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2260++0x3 line.long 0x0 "IP0SR_B1P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2460++0x3 line.long 0x0 "IP0SR_B1P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2060++0x3 line.long 0x0 "IP0SR_B1P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2260++0x3 line.long 0x0 "IP0SR_B1P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2460++0x3 line.long 0x0 "IP0SR_B1P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4060++0x3 line.long 0x0 "IP0SR_B2P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4260++0x3 line.long 0x0 "IP0SR_B2P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4460++0x3 line.long 0x0 "IP0SR_B2P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4060++0x3 line.long 0x0 "IP0SR_B2P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4260++0x3 line.long 0x0 "IP0SR_B2P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4460++0x3 line.long 0x0 "IP0SR_B2P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4060++0x3 line.long 0x0 "IP0SR_B2P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4260++0x3 line.long 0x0 "IP0SR_B2P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4460++0x3 line.long 0x0 "IP0SR_B2P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4060++0x3 line.long 0x0 "IP0SR_B2P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4260++0x3 line.long 0x0 "IP0SR_B2P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4460++0x3 line.long 0x0 "IP0SR_B2P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6060++0x3 line.long 0x0 "IP0SR_B3P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6260++0x3 line.long 0x0 "IP0SR_B3P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6460++0x3 line.long 0x0 "IP0SR_B3P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6060++0x3 line.long 0x0 "IP0SR_B3P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6260++0x3 line.long 0x0 "IP0SR_B3P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6460++0x3 line.long 0x0 "IP0SR_B3P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6060++0x3 line.long 0x0 "IP0SR_B3P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6260++0x3 line.long 0x0 "IP0SR_B3P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6460++0x3 line.long 0x0 "IP0SR_B3P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6060++0x3 line.long 0x0 "IP0SR_B3P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6260++0x3 line.long 0x0 "IP0SR_B3P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6460++0x3 line.long 0x0 "IP0SR_B3P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x64++0x3 line.long 0x0 "IP1SR_B0P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x264++0x3 line.long 0x0 "IP1SR_B0P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x464++0x3 line.long 0x0 "IP1SR_B0P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x64++0x3 line.long 0x0 "IP1SR_B0P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x264++0x3 line.long 0x0 "IP1SR_B0P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x464++0x3 line.long 0x0 "IP1SR_B0P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x64++0x3 line.long 0x0 "IP1SR_B0P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x264++0x3 line.long 0x0 "IP1SR_B0P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x464++0x3 line.long 0x0 "IP1SR_B0P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x64++0x3 line.long 0x0 "IP1SR_B0P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x264++0x3 line.long 0x0 "IP1SR_B0P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x464++0x3 line.long 0x0 "IP1SR_B0P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2064++0x3 line.long 0x0 "IP1SR_B1P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2264++0x3 line.long 0x0 "IP1SR_B1P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2464++0x3 line.long 0x0 "IP1SR_B1P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2064++0x3 line.long 0x0 "IP1SR_B1P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2264++0x3 line.long 0x0 "IP1SR_B1P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2464++0x3 line.long 0x0 "IP1SR_B1P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2064++0x3 line.long 0x0 "IP1SR_B1P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2264++0x3 line.long 0x0 "IP1SR_B1P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2464++0x3 line.long 0x0 "IP1SR_B1P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2064++0x3 line.long 0x0 "IP1SR_B1P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2264++0x3 line.long 0x0 "IP1SR_B1P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x2464++0x3 line.long 0x0 "IP1SR_B1P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4064++0x3 line.long 0x0 "IP1SR_B2P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4264++0x3 line.long 0x0 "IP1SR_B2P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4464++0x3 line.long 0x0 "IP1SR_B2P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4064++0x3 line.long 0x0 "IP1SR_B2P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4264++0x3 line.long 0x0 "IP1SR_B2P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4464++0x3 line.long 0x0 "IP1SR_B2P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4064++0x3 line.long 0x0 "IP1SR_B2P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4264++0x3 line.long 0x0 "IP1SR_B2P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4464++0x3 line.long 0x0 "IP1SR_B2P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4064++0x3 line.long 0x0 "IP1SR_B2P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4264++0x3 line.long 0x0 "IP1SR_B2P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x4464++0x3 line.long 0x0 "IP1SR_B2P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6064++0x3 line.long 0x0 "IP1SR_B3P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6264++0x3 line.long 0x0 "IP1SR_B3P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6464++0x3 line.long 0x0 "IP1SR_B3P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6064++0x3 line.long 0x0 "IP1SR_B3P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6264++0x3 line.long 0x0 "IP1SR_B3P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6464++0x3 line.long 0x0 "IP1SR_B3P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6064++0x3 line.long 0x0 "IP1SR_B3P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6264++0x3 line.long 0x0 "IP1SR_B3P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6464++0x3 line.long 0x0 "IP1SR_B3P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6064++0x3 line.long 0x0 "IP1SR_B3P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6264++0x3 line.long 0x0 "IP1SR_B3P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x6464++0x3 line.long 0x0 "IP1SR_B3P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP1SR,The functions of the LSI pins are selected according to the table below." group.long 0x68++0x3 line.long 0x0 "IP2SR_B0P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x268++0x3 line.long 0x0 "IP2SR_B0P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x468++0x3 line.long 0x0 "IP2SR_B0P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x68++0x3 line.long 0x0 "IP2SR_B0P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x268++0x3 line.long 0x0 "IP2SR_B0P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x468++0x3 line.long 0x0 "IP2SR_B0P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x68++0x3 line.long 0x0 "IP2SR_B0P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x268++0x3 line.long 0x0 "IP2SR_B0P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x468++0x3 line.long 0x0 "IP2SR_B0P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x68++0x3 line.long 0x0 "IP2SR_B0P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x268++0x3 line.long 0x0 "IP2SR_B0P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x468++0x3 line.long 0x0 "IP2SR_B0P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2068++0x3 line.long 0x0 "IP2SR_B1P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2268++0x3 line.long 0x0 "IP2SR_B1P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2468++0x3 line.long 0x0 "IP2SR_B1P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2068++0x3 line.long 0x0 "IP2SR_B1P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2268++0x3 line.long 0x0 "IP2SR_B1P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2468++0x3 line.long 0x0 "IP2SR_B1P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2068++0x3 line.long 0x0 "IP2SR_B1P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2268++0x3 line.long 0x0 "IP2SR_B1P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2468++0x3 line.long 0x0 "IP2SR_B1P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2068++0x3 line.long 0x0 "IP2SR_B1P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2268++0x3 line.long 0x0 "IP2SR_B1P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x2468++0x3 line.long 0x0 "IP2SR_B1P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4068++0x3 line.long 0x0 "IP2SR_B2P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4268++0x3 line.long 0x0 "IP2SR_B2P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4468++0x3 line.long 0x0 "IP2SR_B2P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4068++0x3 line.long 0x0 "IP2SR_B2P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4268++0x3 line.long 0x0 "IP2SR_B2P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4468++0x3 line.long 0x0 "IP2SR_B2P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4068++0x3 line.long 0x0 "IP2SR_B2P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4268++0x3 line.long 0x0 "IP2SR_B2P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4468++0x3 line.long 0x0 "IP2SR_B2P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4068++0x3 line.long 0x0 "IP2SR_B2P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4268++0x3 line.long 0x0 "IP2SR_B2P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x4468++0x3 line.long 0x0 "IP2SR_B2P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6068++0x3 line.long 0x0 "IP2SR_B3P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6268++0x3 line.long 0x0 "IP2SR_B3P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6468++0x3 line.long 0x0 "IP2SR_B3P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6068++0x3 line.long 0x0 "IP2SR_B3P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6268++0x3 line.long 0x0 "IP2SR_B3P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6468++0x3 line.long 0x0 "IP2SR_B3P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6068++0x3 line.long 0x0 "IP2SR_B3P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6268++0x3 line.long 0x0 "IP2SR_B3P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6468++0x3 line.long 0x0 "IP2SR_B3P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6068++0x3 line.long 0x0 "IP2SR_B3P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6268++0x3 line.long 0x0 "IP2SR_B3P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x6468++0x3 line.long 0x0 "IP2SR_B3P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP2SR,The functions of the LSI pins are selected according to the table below." group.long 0x80++0x3 line.long 0x0 "DRV0CTRL_B0P6T0,DRV Control Register0 B0P6T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x280++0x3 line.long 0x0 "DRV0CTRL_B0P6T1,DRV Control Register0 B0P6T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x480++0x3 line.long 0x0 "DRV0CTRL_B0P6T2,DRV Control Register0 B0P6T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x80++0x3 line.long 0x0 "DRV0CTRL_B0P7T0,DRV Control Register0 B0P7T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x280++0x3 line.long 0x0 "DRV0CTRL_B0P7T1,DRV Control Register0 B0P7T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x480++0x3 line.long 0x0 "DRV0CTRL_B0P7T2,DRV Control Register0 B0P7T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x80++0x3 line.long 0x0 "DRV0CTRL_B0P8T0,DRV Control Register0 B0P8T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x280++0x3 line.long 0x0 "DRV0CTRL_B0P8T1,DRV Control Register0 B0P8T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x480++0x3 line.long 0x0 "DRV0CTRL_B0P8T2,DRV Control Register0 B0P8T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x80++0x3 line.long 0x0 "DRV0CTRL_B0P9T0,DRV Control Register0 B0P9T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x280++0x3 line.long 0x0 "DRV0CTRL_B0P9T1,DRV Control Register0 B0P9T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x480++0x3 line.long 0x0 "DRV0CTRL_B0P9T2,DRV Control Register0 B0P9T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2080++0x3 line.long 0x0 "DRV0CTRL_B1P6T0,DRV Control Register0 B1P6T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2280++0x3 line.long 0x0 "DRV0CTRL_B1P6T1,DRV Control Register0 B1P6T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2480++0x3 line.long 0x0 "DRV0CTRL_B1P6T2,DRV Control Register0 B1P6T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2080++0x3 line.long 0x0 "DRV0CTRL_B1P7T0,DRV Control Register0 B1P7T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2280++0x3 line.long 0x0 "DRV0CTRL_B1P7T1,DRV Control Register0 B1P7T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2480++0x3 line.long 0x0 "DRV0CTRL_B1P7T2,DRV Control Register0 B1P7T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2080++0x3 line.long 0x0 "DRV0CTRL_B1P8T0,DRV Control Register0 B1P8T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2280++0x3 line.long 0x0 "DRV0CTRL_B1P8T1,DRV Control Register0 B1P8T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2480++0x3 line.long 0x0 "DRV0CTRL_B1P8T2,DRV Control Register0 B1P8T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2080++0x3 line.long 0x0 "DRV0CTRL_B1P9T0,DRV Control Register0 B1P9T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2280++0x3 line.long 0x0 "DRV0CTRL_B1P9T1,DRV Control Register0 B1P9T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x2480++0x3 line.long 0x0 "DRV0CTRL_B1P9T2,DRV Control Register0 B1P9T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4080++0x3 line.long 0x0 "DRV0CTRL_B2P6T0,DRV Control Register0 B2P6T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4280++0x3 line.long 0x0 "DRV0CTRL_B2P6T1,DRV Control Register0 B2P6T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4480++0x3 line.long 0x0 "DRV0CTRL_B2P6T2,DRV Control Register0 B2P6T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4080++0x3 line.long 0x0 "DRV0CTRL_B2P7T0,DRV Control Register0 B2P7T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4280++0x3 line.long 0x0 "DRV0CTRL_B2P7T1,DRV Control Register0 B2P7T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4480++0x3 line.long 0x0 "DRV0CTRL_B2P7T2,DRV Control Register0 B2P7T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4080++0x3 line.long 0x0 "DRV0CTRL_B2P8T0,DRV Control Register0 B2P8T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4280++0x3 line.long 0x0 "DRV0CTRL_B2P8T1,DRV Control Register0 B2P8T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4480++0x3 line.long 0x0 "DRV0CTRL_B2P8T2,DRV Control Register0 B2P8T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4080++0x3 line.long 0x0 "DRV0CTRL_B2P9T0,DRV Control Register0 B2P9T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4280++0x3 line.long 0x0 "DRV0CTRL_B2P9T1,DRV Control Register0 B2P9T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x4480++0x3 line.long 0x0 "DRV0CTRL_B2P9T2,DRV Control Register0 B2P9T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6080++0x3 line.long 0x0 "DRV0CTRL_B3P6T0,DRV Control Register0 B3P6T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6280++0x3 line.long 0x0 "DRV0CTRL_B3P6T1,DRV Control Register0 B3P6T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6480++0x3 line.long 0x0 "DRV0CTRL_B3P6T2,DRV Control Register0 B3P6T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6080++0x3 line.long 0x0 "DRV0CTRL_B3P7T0,DRV Control Register0 B3P7T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6280++0x3 line.long 0x0 "DRV0CTRL_B3P7T1,DRV Control Register0 B3P7T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6480++0x3 line.long 0x0 "DRV0CTRL_B3P7T2,DRV Control Register0 B3P7T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6080++0x3 line.long 0x0 "DRV0CTRL_B3P8T0,DRV Control Register0 B3P8T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6280++0x3 line.long 0x0 "DRV0CTRL_B3P8T1,DRV Control Register0 B3P8T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6480++0x3 line.long 0x0 "DRV0CTRL_B3P8T2,DRV Control Register0 B3P8T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6080++0x3 line.long 0x0 "DRV0CTRL_B3P9T0,DRV Control Register0 B3P9T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6280++0x3 line.long 0x0 "DRV0CTRL_B3P9T1,DRV Control Register0 B3P9T1" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0x6480++0x3 line.long 0x0 "DRV0CTRL_B3P9T2,DRV Control Register0 B3P9T2" hexmask.long 0x0 0.--31. 1. "DRV0CTRL" group.long 0xA0++0x3 line.long 0x0 "POC_B0P6T0,POC Control Register B0P6T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x2A0++0x3 line.long 0x0 "POC_B0P6T1,POC Control Register B0P6T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x4A0++0x3 line.long 0x0 "POC_B0P6T2,POC Control Register B0P6T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0xA0++0x3 line.long 0x0 "POC_B0P7T0,POC Control Register B0P7T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x2A0++0x3 line.long 0x0 "POC_B0P7T1,POC Control Register B0P7T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x4A0++0x3 line.long 0x0 "POC_B0P7T2,POC Control Register B0P7T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0xA0++0x3 line.long 0x0 "POC_B0P8T0,POC Control Register B0P8T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x2A0++0x3 line.long 0x0 "POC_B0P8T1,POC Control Register B0P8T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x4A0++0x3 line.long 0x0 "POC_B0P8T2,POC Control Register B0P8T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0xA0++0x3 line.long 0x0 "POC_B0P9T0,POC Control Register B0P9T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x2A0++0x3 line.long 0x0 "POC_B0P9T1,POC Control Register B0P9T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x4A0++0x3 line.long 0x0 "POC_B0P9T2,POC Control Register B0P9T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x20A0++0x3 line.long 0x0 "POC_B1P6T0,POC Control Register B1P6T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x22A0++0x3 line.long 0x0 "POC_B1P6T1,POC Control Register B1P6T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x24A0++0x3 line.long 0x0 "POC_B1P6T2,POC Control Register B1P6T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x20A0++0x3 line.long 0x0 "POC_B1P7T0,POC Control Register B1P7T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x22A0++0x3 line.long 0x0 "POC_B1P7T1,POC Control Register B1P7T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x24A0++0x3 line.long 0x0 "POC_B1P7T2,POC Control Register B1P7T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x20A0++0x3 line.long 0x0 "POC_B1P8T0,POC Control Register B1P8T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x22A0++0x3 line.long 0x0 "POC_B1P8T1,POC Control Register B1P8T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x24A0++0x3 line.long 0x0 "POC_B1P8T2,POC Control Register B1P8T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x20A0++0x3 line.long 0x0 "POC_B1P9T0,POC Control Register B1P9T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x22A0++0x3 line.long 0x0 "POC_B1P9T1,POC Control Register B1P9T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x24A0++0x3 line.long 0x0 "POC_B1P9T2,POC Control Register B1P9T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x40A0++0x3 line.long 0x0 "POC_B2P6T0,POC Control Register B2P6T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x42A0++0x3 line.long 0x0 "POC_B2P6T1,POC Control Register B2P6T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x44A0++0x3 line.long 0x0 "POC_B2P6T2,POC Control Register B2P6T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x40A0++0x3 line.long 0x0 "POC_B2P7T0,POC Control Register B2P7T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x42A0++0x3 line.long 0x0 "POC_B2P7T1,POC Control Register B2P7T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x44A0++0x3 line.long 0x0 "POC_B2P7T2,POC Control Register B2P7T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x40A0++0x3 line.long 0x0 "POC_B2P8T0,POC Control Register B2P8T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x42A0++0x3 line.long 0x0 "POC_B2P8T1,POC Control Register B2P8T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x44A0++0x3 line.long 0x0 "POC_B2P8T2,POC Control Register B2P8T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x40A0++0x3 line.long 0x0 "POC_B2P9T0,POC Control Register B2P9T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x42A0++0x3 line.long 0x0 "POC_B2P9T1,POC Control Register B2P9T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x44A0++0x3 line.long 0x0 "POC_B2P9T2,POC Control Register B2P9T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x60A0++0x3 line.long 0x0 "POC_B3P6T0,POC Control Register B3P6T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x62A0++0x3 line.long 0x0 "POC_B3P6T1,POC Control Register B3P6T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x64A0++0x3 line.long 0x0 "POC_B3P6T2,POC Control Register B3P6T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x60A0++0x3 line.long 0x0 "POC_B3P7T0,POC Control Register B3P7T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x62A0++0x3 line.long 0x0 "POC_B3P7T1,POC Control Register B3P7T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x64A0++0x3 line.long 0x0 "POC_B3P7T2,POC Control Register B3P7T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x60A0++0x3 line.long 0x0 "POC_B3P8T0,POC Control Register B3P8T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x62A0++0x3 line.long 0x0 "POC_B3P8T1,POC Control Register B3P8T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x64A0++0x3 line.long 0x0 "POC_B3P8T2,POC Control Register B3P8T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x60A0++0x3 line.long 0x0 "POC_B3P9T0,POC Control Register B3P9T0" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x62A0++0x3 line.long 0x0 "POC_B3P9T1,POC Control Register B3P9T1" hexmask.long 0x0 0.--31. 1. "POC" group.long 0x64A0++0x3 line.long 0x0 "POC_B3P9T2,POC Control Register B3P9T2" hexmask.long 0x0 0.--31. 1. "POC" group.long 0xC0++0x3 line.long 0x0 "PUEN_B0P6T0,LSI Pin Pull-enable Register B0P6T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x2C0++0x3 line.long 0x0 "PUEN_B0P6T1,LSI Pin Pull-enable Register B0P6T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x4C0++0x3 line.long 0x0 "PUEN_B0P6T2,LSI Pin Pull-enable Register B0P6T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0xC0++0x3 line.long 0x0 "PUEN_B0P7T0,LSI Pin Pull-enable Register B0P7T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x2C0++0x3 line.long 0x0 "PUEN_B0P7T1,LSI Pin Pull-enable Register B0P7T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x4C0++0x3 line.long 0x0 "PUEN_B0P7T2,LSI Pin Pull-enable Register B0P7T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0xC0++0x3 line.long 0x0 "PUEN_B0P8T0,LSI Pin Pull-enable Register B0P8T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x2C0++0x3 line.long 0x0 "PUEN_B0P8T1,LSI Pin Pull-enable Register B0P8T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x4C0++0x3 line.long 0x0 "PUEN_B0P8T2,LSI Pin Pull-enable Register B0P8T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0xC0++0x3 line.long 0x0 "PUEN_B0P9T0,LSI Pin Pull-enable Register B0P9T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x2C0++0x3 line.long 0x0 "PUEN_B0P9T1,LSI Pin Pull-enable Register B0P9T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x4C0++0x3 line.long 0x0 "PUEN_B0P9T2,LSI Pin Pull-enable Register B0P9T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x20C0++0x3 line.long 0x0 "PUEN_B1P6T0,LSI Pin Pull-enable Register B1P6T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x22C0++0x3 line.long 0x0 "PUEN_B1P6T1,LSI Pin Pull-enable Register B1P6T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x24C0++0x3 line.long 0x0 "PUEN_B1P6T2,LSI Pin Pull-enable Register B1P6T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x20C0++0x3 line.long 0x0 "PUEN_B1P7T0,LSI Pin Pull-enable Register B1P7T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x22C0++0x3 line.long 0x0 "PUEN_B1P7T1,LSI Pin Pull-enable Register B1P7T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x24C0++0x3 line.long 0x0 "PUEN_B1P7T2,LSI Pin Pull-enable Register B1P7T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x20C0++0x3 line.long 0x0 "PUEN_B1P8T0,LSI Pin Pull-enable Register B1P8T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x22C0++0x3 line.long 0x0 "PUEN_B1P8T1,LSI Pin Pull-enable Register B1P8T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x24C0++0x3 line.long 0x0 "PUEN_B1P8T2,LSI Pin Pull-enable Register B1P8T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x20C0++0x3 line.long 0x0 "PUEN_B1P9T0,LSI Pin Pull-enable Register B1P9T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x22C0++0x3 line.long 0x0 "PUEN_B1P9T1,LSI Pin Pull-enable Register B1P9T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x24C0++0x3 line.long 0x0 "PUEN_B1P9T2,LSI Pin Pull-enable Register B1P9T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x40C0++0x3 line.long 0x0 "PUEN_B2P6T0,LSI Pin Pull-enable Register B2P6T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x42C0++0x3 line.long 0x0 "PUEN_B2P6T1,LSI Pin Pull-enable Register B2P6T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x44C0++0x3 line.long 0x0 "PUEN_B2P6T2,LSI Pin Pull-enable Register B2P6T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x40C0++0x3 line.long 0x0 "PUEN_B2P7T0,LSI Pin Pull-enable Register B2P7T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x42C0++0x3 line.long 0x0 "PUEN_B2P7T1,LSI Pin Pull-enable Register B2P7T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x44C0++0x3 line.long 0x0 "PUEN_B2P7T2,LSI Pin Pull-enable Register B2P7T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x40C0++0x3 line.long 0x0 "PUEN_B2P8T0,LSI Pin Pull-enable Register B2P8T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x42C0++0x3 line.long 0x0 "PUEN_B2P8T1,LSI Pin Pull-enable Register B2P8T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x44C0++0x3 line.long 0x0 "PUEN_B2P8T2,LSI Pin Pull-enable Register B2P8T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x40C0++0x3 line.long 0x0 "PUEN_B2P9T0,LSI Pin Pull-enable Register B2P9T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x42C0++0x3 line.long 0x0 "PUEN_B2P9T1,LSI Pin Pull-enable Register B2P9T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x44C0++0x3 line.long 0x0 "PUEN_B2P9T2,LSI Pin Pull-enable Register B2P9T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x60C0++0x3 line.long 0x0 "PUEN_B3P6T0,LSI Pin Pull-enable Register B3P6T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x62C0++0x3 line.long 0x0 "PUEN_B3P6T1,LSI Pin Pull-enable Register B3P6T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x64C0++0x3 line.long 0x0 "PUEN_B3P6T2,LSI Pin Pull-enable Register B3P6T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x60C0++0x3 line.long 0x0 "PUEN_B3P7T0,LSI Pin Pull-enable Register B3P7T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x62C0++0x3 line.long 0x0 "PUEN_B3P7T1,LSI Pin Pull-enable Register B3P7T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x64C0++0x3 line.long 0x0 "PUEN_B3P7T2,LSI Pin Pull-enable Register B3P7T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x60C0++0x3 line.long 0x0 "PUEN_B3P8T0,LSI Pin Pull-enable Register B3P8T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x62C0++0x3 line.long 0x0 "PUEN_B3P8T1,LSI Pin Pull-enable Register B3P8T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x64C0++0x3 line.long 0x0 "PUEN_B3P8T2,LSI Pin Pull-enable Register B3P8T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x60C0++0x3 line.long 0x0 "PUEN_B3P9T0,LSI Pin Pull-enable Register B3P9T0" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x62C0++0x3 line.long 0x0 "PUEN_B3P9T1,LSI Pin Pull-enable Register B3P9T1" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0x64C0++0x3 line.long 0x0 "PUEN_B3P9T2,LSI Pin Pull-enable Register B3P9T2" hexmask.long 0x0 0.--31. 1. "PUEN" group.long 0xE0++0x3 line.long 0x0 "PUD_B0P6T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x2E0++0x3 line.long 0x0 "PUD_B0P6T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x4E0++0x3 line.long 0x0 "PUD_B0P6T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0xE0++0x3 line.long 0x0 "PUD_B0P7T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x2E0++0x3 line.long 0x0 "PUD_B0P7T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x4E0++0x3 line.long 0x0 "PUD_B0P7T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0xE0++0x3 line.long 0x0 "PUD_B0P8T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x2E0++0x3 line.long 0x0 "PUD_B0P8T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x4E0++0x3 line.long 0x0 "PUD_B0P8T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0xE0++0x3 line.long 0x0 "PUD_B0P9T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x2E0++0x3 line.long 0x0 "PUD_B0P9T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x4E0++0x3 line.long 0x0 "PUD_B0P9T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x20E0++0x3 line.long 0x0 "PUD_B1P6T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x22E0++0x3 line.long 0x0 "PUD_B1P6T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x24E0++0x3 line.long 0x0 "PUD_B1P6T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x20E0++0x3 line.long 0x0 "PUD_B1P7T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x22E0++0x3 line.long 0x0 "PUD_B1P7T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x24E0++0x3 line.long 0x0 "PUD_B1P7T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x20E0++0x3 line.long 0x0 "PUD_B1P8T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x22E0++0x3 line.long 0x0 "PUD_B1P8T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x24E0++0x3 line.long 0x0 "PUD_B1P8T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x20E0++0x3 line.long 0x0 "PUD_B1P9T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x22E0++0x3 line.long 0x0 "PUD_B1P9T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x24E0++0x3 line.long 0x0 "PUD_B1P9T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x40E0++0x3 line.long 0x0 "PUD_B2P6T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x42E0++0x3 line.long 0x0 "PUD_B2P6T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x44E0++0x3 line.long 0x0 "PUD_B2P6T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x40E0++0x3 line.long 0x0 "PUD_B2P7T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x42E0++0x3 line.long 0x0 "PUD_B2P7T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x44E0++0x3 line.long 0x0 "PUD_B2P7T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x40E0++0x3 line.long 0x0 "PUD_B2P8T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x42E0++0x3 line.long 0x0 "PUD_B2P8T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x44E0++0x3 line.long 0x0 "PUD_B2P8T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x40E0++0x3 line.long 0x0 "PUD_B2P9T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x42E0++0x3 line.long 0x0 "PUD_B2P9T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x44E0++0x3 line.long 0x0 "PUD_B2P9T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x60E0++0x3 line.long 0x0 "PUD_B3P6T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x62E0++0x3 line.long 0x0 "PUD_B3P6T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x64E0++0x3 line.long 0x0 "PUD_B3P6T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x60E0++0x3 line.long 0x0 "PUD_B3P7T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x62E0++0x3 line.long 0x0 "PUD_B3P7T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x64E0++0x3 line.long 0x0 "PUD_B3P7T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x60E0++0x3 line.long 0x0 "PUD_B3P8T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x62E0++0x3 line.long 0x0 "PUD_B3P8T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x64E0++0x3 line.long 0x0 "PUD_B3P8T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x60E0++0x3 line.long 0x0 "PUD_B3P9T0,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x62E0++0x3 line.long 0x0 "PUD_B3P9T1,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x64E0++0x3 line.long 0x0 "PUD_B3P9T2,Function: PUDn / PUDSYS performs pull-up / pull-down control of the pull resistors." hexmask.long 0x0 0.--31. 1. "PUD,Refer to Table 6.41" group.long 0x0++0x3 line.long 0x0 "PMMR_B0P6T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x200++0x3 line.long 0x0 "PMMR_B0P6T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x400++0x3 line.long 0x0 "PMMR_B0P6T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x800++0x3 line.long 0x0 "PMMR_B0P7T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xA00++0x3 line.long 0x0 "PMMR_B0P7T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0xC00++0x3 line.long 0x0 "PMMR_B0P7T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1000++0x3 line.long 0x0 "PMMR_B0P8T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1200++0x3 line.long 0x0 "PMMR_B0P8T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1400++0x3 line.long 0x0 "PMMR_B0P8T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1800++0x3 line.long 0x0 "PMMR_B0P9T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1A00++0x3 line.long 0x0 "PMMR_B0P9T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x1C00++0x3 line.long 0x0 "PMMR_B0P9T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2000++0x3 line.long 0x0 "PMMR_B1P6T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2200++0x3 line.long 0x0 "PMMR_B1P6T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2400++0x3 line.long 0x0 "PMMR_B1P6T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2800++0x3 line.long 0x0 "PMMR_B1P7T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2A00++0x3 line.long 0x0 "PMMR_B1P7T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x2C00++0x3 line.long 0x0 "PMMR_B1P7T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3000++0x3 line.long 0x0 "PMMR_B1P8T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3200++0x3 line.long 0x0 "PMMR_B1P8T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3400++0x3 line.long 0x0 "PMMR_B1P8T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3800++0x3 line.long 0x0 "PMMR_B1P9T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3A00++0x3 line.long 0x0 "PMMR_B1P9T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x3C00++0x3 line.long 0x0 "PMMR_B1P9T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4000++0x3 line.long 0x0 "PMMR_B2P6T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4200++0x3 line.long 0x0 "PMMR_B2P6T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4400++0x3 line.long 0x0 "PMMR_B2P6T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4800++0x3 line.long 0x0 "PMMR_B2P7T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4A00++0x3 line.long 0x0 "PMMR_B2P7T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4C00++0x3 line.long 0x0 "PMMR_B2P7T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5000++0x3 line.long 0x0 "PMMR_B2P8T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5200++0x3 line.long 0x0 "PMMR_B2P8T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5400++0x3 line.long 0x0 "PMMR_B2P8T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5800++0x3 line.long 0x0 "PMMR_B2P9T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5A00++0x3 line.long 0x0 "PMMR_B2P9T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x5C00++0x3 line.long 0x0 "PMMR_B2P9T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6000++0x3 line.long 0x0 "PMMR_B3P6T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6200++0x3 line.long 0x0 "PMMR_B3P6T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6400++0x3 line.long 0x0 "PMMR_B3P6T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6800++0x3 line.long 0x0 "PMMR_B3P7T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6A00++0x3 line.long 0x0 "PMMR_B3P7T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x6C00++0x3 line.long 0x0 "PMMR_B3P7T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7000++0x3 line.long 0x0 "PMMR_B3P8T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7200++0x3 line.long 0x0 "PMMR_B3P8T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7400++0x3 line.long 0x0 "PMMR_B3P8T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7800++0x3 line.long 0x0 "PMMR_B3P9T0,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7A00++0x3 line.long 0x0 "PMMR_B3P9T1,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x7C00++0x3 line.long 0x0 "PMMR_B3P9T2,Function: PMMRn / PMMRSYS enables / disables writing to the multiplexed pin setting registers." hexmask.long 0x0 0.--31. 1. "PMMR,Multiplexed Pin Setting Mask" group.long 0x4++0x3 line.long 0x0 "PMMER_B0P6T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x204++0x3 line.long 0x0 "PMMER_B0P6T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x404++0x3 line.long 0x0 "PMMER_B0P6T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x804++0x3 line.long 0x0 "PMMER_B0P7T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0xA04++0x3 line.long 0x0 "PMMER_B0P7T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0xC04++0x3 line.long 0x0 "PMMER_B0P7T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x1004++0x3 line.long 0x0 "PMMER_B0P8T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x1204++0x3 line.long 0x0 "PMMER_B0P8T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x1404++0x3 line.long 0x0 "PMMER_B0P8T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x1804++0x3 line.long 0x0 "PMMER_B0P9T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x1A04++0x3 line.long 0x0 "PMMER_B0P9T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x1C04++0x3 line.long 0x0 "PMMER_B0P9T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2004++0x3 line.long 0x0 "PMMER_B1P6T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2204++0x3 line.long 0x0 "PMMER_B1P6T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2404++0x3 line.long 0x0 "PMMER_B1P6T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2804++0x3 line.long 0x0 "PMMER_B1P7T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2A04++0x3 line.long 0x0 "PMMER_B1P7T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x2C04++0x3 line.long 0x0 "PMMER_B1P7T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x3004++0x3 line.long 0x0 "PMMER_B1P8T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x3204++0x3 line.long 0x0 "PMMER_B1P8T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x3404++0x3 line.long 0x0 "PMMER_B1P8T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x3804++0x3 line.long 0x0 "PMMER_B1P9T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x3A04++0x3 line.long 0x0 "PMMER_B1P9T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x3C04++0x3 line.long 0x0 "PMMER_B1P9T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4004++0x3 line.long 0x0 "PMMER_B2P6T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4204++0x3 line.long 0x0 "PMMER_B2P6T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4404++0x3 line.long 0x0 "PMMER_B2P6T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4804++0x3 line.long 0x0 "PMMER_B2P7T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4A04++0x3 line.long 0x0 "PMMER_B2P7T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x4C04++0x3 line.long 0x0 "PMMER_B2P7T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x5004++0x3 line.long 0x0 "PMMER_B2P8T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x5204++0x3 line.long 0x0 "PMMER_B2P8T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x5404++0x3 line.long 0x0 "PMMER_B2P8T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x5804++0x3 line.long 0x0 "PMMER_B2P9T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x5A04++0x3 line.long 0x0 "PMMER_B2P9T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x5C04++0x3 line.long 0x0 "PMMER_B2P9T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6004++0x3 line.long 0x0 "PMMER_B3P6T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6204++0x3 line.long 0x0 "PMMER_B3P6T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6404++0x3 line.long 0x0 "PMMER_B3P6T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6804++0x3 line.long 0x0 "PMMER_B3P7T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6A04++0x3 line.long 0x0 "PMMER_B3P7T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x6C04++0x3 line.long 0x0 "PMMER_B3P7T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x7004++0x3 line.long 0x0 "PMMER_B3P8T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x7204++0x3 line.long 0x0 "PMMER_B3P8T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x7404++0x3 line.long 0x0 "PMMER_B3P8T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x7804++0x3 line.long 0x0 "PMMER_B3P9T0,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x7A04++0x3 line.long 0x0 "PMMER_B3P9T1,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x7C04++0x3 line.long 0x0 "PMMER_B3P9T2,Function: PMMERn / PMMERSYS performs enables / disables control of the PMMR." bitfld.long 0x0 0. "PMMER,Multiplexed Pin Setting Mask Enable" "0: PMMR function is disabled,1: PMMR function is enabled" group.long 0x20++0x3 line.long 0x0 "DMPR0_B0P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x220++0x3 line.long 0x0 "DMPR0_B0P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x420++0x3 line.long 0x0 "DMPR0_B0P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x820++0x3 line.long 0x0 "DMPR0_B0P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA20++0x3 line.long 0x0 "DMPR0_B0P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC20++0x3 line.long 0x0 "DMPR0_B0P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1020++0x3 line.long 0x0 "DMPR0_B0P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1220++0x3 line.long 0x0 "DMPR0_B0P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1420++0x3 line.long 0x0 "DMPR0_B0P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1820++0x3 line.long 0x0 "DMPR0_B0P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1A20++0x3 line.long 0x0 "DMPR0_B0P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1C20++0x3 line.long 0x0 "DMPR0_B0P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2020++0x3 line.long 0x0 "DMPR0_B1P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2220++0x3 line.long 0x0 "DMPR0_B1P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2420++0x3 line.long 0x0 "DMPR0_B1P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2820++0x3 line.long 0x0 "DMPR0_B1P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A20++0x3 line.long 0x0 "DMPR0_B1P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C20++0x3 line.long 0x0 "DMPR0_B1P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3020++0x3 line.long 0x0 "DMPR0_B1P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3220++0x3 line.long 0x0 "DMPR0_B1P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3420++0x3 line.long 0x0 "DMPR0_B1P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3820++0x3 line.long 0x0 "DMPR0_B1P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3A20++0x3 line.long 0x0 "DMPR0_B1P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3C20++0x3 line.long 0x0 "DMPR0_B1P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4020++0x3 line.long 0x0 "DMPR0_B2P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4220++0x3 line.long 0x0 "DMPR0_B2P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4420++0x3 line.long 0x0 "DMPR0_B2P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4820++0x3 line.long 0x0 "DMPR0_B2P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A20++0x3 line.long 0x0 "DMPR0_B2P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C20++0x3 line.long 0x0 "DMPR0_B2P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5020++0x3 line.long 0x0 "DMPR0_B2P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5220++0x3 line.long 0x0 "DMPR0_B2P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5420++0x3 line.long 0x0 "DMPR0_B2P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5820++0x3 line.long 0x0 "DMPR0_B2P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5A20++0x3 line.long 0x0 "DMPR0_B2P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5C20++0x3 line.long 0x0 "DMPR0_B2P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6020++0x3 line.long 0x0 "DMPR0_B3P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6220++0x3 line.long 0x0 "DMPR0_B3P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6420++0x3 line.long 0x0 "DMPR0_B3P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6820++0x3 line.long 0x0 "DMPR0_B3P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A20++0x3 line.long 0x0 "DMPR0_B3P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C20++0x3 line.long 0x0 "DMPR0_B3P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7020++0x3 line.long 0x0 "DMPR0_B3P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7220++0x3 line.long 0x0 "DMPR0_B3P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7420++0x3 line.long 0x0 "DMPR0_B3P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7820++0x3 line.long 0x0 "DMPR0_B3P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7A20++0x3 line.long 0x0 "DMPR0_B3P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7C20++0x3 line.long 0x0 "DMPR0_B3P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x24++0x3 line.long 0x0 "DMPR1_B0P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x224++0x3 line.long 0x0 "DMPR1_B0P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x424++0x3 line.long 0x0 "DMPR1_B0P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x824++0x3 line.long 0x0 "DMPR1_B0P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA24++0x3 line.long 0x0 "DMPR1_B0P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC24++0x3 line.long 0x0 "DMPR1_B0P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1024++0x3 line.long 0x0 "DMPR1_B0P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1224++0x3 line.long 0x0 "DMPR1_B0P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1424++0x3 line.long 0x0 "DMPR1_B0P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1824++0x3 line.long 0x0 "DMPR1_B0P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1A24++0x3 line.long 0x0 "DMPR1_B0P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1C24++0x3 line.long 0x0 "DMPR1_B0P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2024++0x3 line.long 0x0 "DMPR1_B1P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2224++0x3 line.long 0x0 "DMPR1_B1P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2424++0x3 line.long 0x0 "DMPR1_B1P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2824++0x3 line.long 0x0 "DMPR1_B1P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A24++0x3 line.long 0x0 "DMPR1_B1P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C24++0x3 line.long 0x0 "DMPR1_B1P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3024++0x3 line.long 0x0 "DMPR1_B1P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3224++0x3 line.long 0x0 "DMPR1_B1P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3424++0x3 line.long 0x0 "DMPR1_B1P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3824++0x3 line.long 0x0 "DMPR1_B1P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3A24++0x3 line.long 0x0 "DMPR1_B1P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3C24++0x3 line.long 0x0 "DMPR1_B1P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4024++0x3 line.long 0x0 "DMPR1_B2P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4224++0x3 line.long 0x0 "DMPR1_B2P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4424++0x3 line.long 0x0 "DMPR1_B2P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4824++0x3 line.long 0x0 "DMPR1_B2P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A24++0x3 line.long 0x0 "DMPR1_B2P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C24++0x3 line.long 0x0 "DMPR1_B2P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5024++0x3 line.long 0x0 "DMPR1_B2P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5224++0x3 line.long 0x0 "DMPR1_B2P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5424++0x3 line.long 0x0 "DMPR1_B2P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5824++0x3 line.long 0x0 "DMPR1_B2P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5A24++0x3 line.long 0x0 "DMPR1_B2P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5C24++0x3 line.long 0x0 "DMPR1_B2P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6024++0x3 line.long 0x0 "DMPR1_B3P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6224++0x3 line.long 0x0 "DMPR1_B3P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6424++0x3 line.long 0x0 "DMPR1_B3P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6824++0x3 line.long 0x0 "DMPR1_B3P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A24++0x3 line.long 0x0 "DMPR1_B3P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C24++0x3 line.long 0x0 "DMPR1_B3P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7024++0x3 line.long 0x0 "DMPR1_B3P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7224++0x3 line.long 0x0 "DMPR1_B3P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7424++0x3 line.long 0x0 "DMPR1_B3P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7824++0x3 line.long 0x0 "DMPR1_B3P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7A24++0x3 line.long 0x0 "DMPR1_B3P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7C24++0x3 line.long 0x0 "DMPR1_B3P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x28++0x3 line.long 0x0 "DMPR2_B0P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x228++0x3 line.long 0x0 "DMPR2_B0P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x428++0x3 line.long 0x0 "DMPR2_B0P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x828++0x3 line.long 0x0 "DMPR2_B0P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA28++0x3 line.long 0x0 "DMPR2_B0P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC28++0x3 line.long 0x0 "DMPR2_B0P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1028++0x3 line.long 0x0 "DMPR2_B0P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1228++0x3 line.long 0x0 "DMPR2_B0P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1428++0x3 line.long 0x0 "DMPR2_B0P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1828++0x3 line.long 0x0 "DMPR2_B0P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1A28++0x3 line.long 0x0 "DMPR2_B0P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1C28++0x3 line.long 0x0 "DMPR2_B0P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2028++0x3 line.long 0x0 "DMPR2_B1P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2228++0x3 line.long 0x0 "DMPR2_B1P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2428++0x3 line.long 0x0 "DMPR2_B1P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2828++0x3 line.long 0x0 "DMPR2_B1P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A28++0x3 line.long 0x0 "DMPR2_B1P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C28++0x3 line.long 0x0 "DMPR2_B1P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3028++0x3 line.long 0x0 "DMPR2_B1P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3228++0x3 line.long 0x0 "DMPR2_B1P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3428++0x3 line.long 0x0 "DMPR2_B1P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3828++0x3 line.long 0x0 "DMPR2_B1P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3A28++0x3 line.long 0x0 "DMPR2_B1P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3C28++0x3 line.long 0x0 "DMPR2_B1P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4028++0x3 line.long 0x0 "DMPR2_B2P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4228++0x3 line.long 0x0 "DMPR2_B2P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4428++0x3 line.long 0x0 "DMPR2_B2P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4828++0x3 line.long 0x0 "DMPR2_B2P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A28++0x3 line.long 0x0 "DMPR2_B2P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C28++0x3 line.long 0x0 "DMPR2_B2P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5028++0x3 line.long 0x0 "DMPR2_B2P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5228++0x3 line.long 0x0 "DMPR2_B2P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5428++0x3 line.long 0x0 "DMPR2_B2P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5828++0x3 line.long 0x0 "DMPR2_B2P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5A28++0x3 line.long 0x0 "DMPR2_B2P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5C28++0x3 line.long 0x0 "DMPR2_B2P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6028++0x3 line.long 0x0 "DMPR2_B3P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6228++0x3 line.long 0x0 "DMPR2_B3P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6428++0x3 line.long 0x0 "DMPR2_B3P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6828++0x3 line.long 0x0 "DMPR2_B3P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A28++0x3 line.long 0x0 "DMPR2_B3P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C28++0x3 line.long 0x0 "DMPR2_B3P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7028++0x3 line.long 0x0 "DMPR2_B3P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7228++0x3 line.long 0x0 "DMPR2_B3P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7428++0x3 line.long 0x0 "DMPR2_B3P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7828++0x3 line.long 0x0 "DMPR2_B3P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7A28++0x3 line.long 0x0 "DMPR2_B3P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7C28++0x3 line.long 0x0 "DMPR2_B3P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C++0x3 line.long 0x0 "DMPR3_B0P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x22C++0x3 line.long 0x0 "DMPR3_B0P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x42C++0x3 line.long 0x0 "DMPR3_B0P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x82C++0x3 line.long 0x0 "DMPR3_B0P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xA2C++0x3 line.long 0x0 "DMPR3_B0P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0xC2C++0x3 line.long 0x0 "DMPR3_B0P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x102C++0x3 line.long 0x0 "DMPR3_B0P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x122C++0x3 line.long 0x0 "DMPR3_B0P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x142C++0x3 line.long 0x0 "DMPR3_B0P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x182C++0x3 line.long 0x0 "DMPR3_B0P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1A2C++0x3 line.long 0x0 "DMPR3_B0P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x1C2C++0x3 line.long 0x0 "DMPR3_B0P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x202C++0x3 line.long 0x0 "DMPR3_B1P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x222C++0x3 line.long 0x0 "DMPR3_B1P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x242C++0x3 line.long 0x0 "DMPR3_B1P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x282C++0x3 line.long 0x0 "DMPR3_B1P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2A2C++0x3 line.long 0x0 "DMPR3_B1P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x2C2C++0x3 line.long 0x0 "DMPR3_B1P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x302C++0x3 line.long 0x0 "DMPR3_B1P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x322C++0x3 line.long 0x0 "DMPR3_B1P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x342C++0x3 line.long 0x0 "DMPR3_B1P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x382C++0x3 line.long 0x0 "DMPR3_B1P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3A2C++0x3 line.long 0x0 "DMPR3_B1P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x3C2C++0x3 line.long 0x0 "DMPR3_B1P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x402C++0x3 line.long 0x0 "DMPR3_B2P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x422C++0x3 line.long 0x0 "DMPR3_B2P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x442C++0x3 line.long 0x0 "DMPR3_B2P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x482C++0x3 line.long 0x0 "DMPR3_B2P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4A2C++0x3 line.long 0x0 "DMPR3_B2P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x4C2C++0x3 line.long 0x0 "DMPR3_B2P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x502C++0x3 line.long 0x0 "DMPR3_B2P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x522C++0x3 line.long 0x0 "DMPR3_B2P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x542C++0x3 line.long 0x0 "DMPR3_B2P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x582C++0x3 line.long 0x0 "DMPR3_B2P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5A2C++0x3 line.long 0x0 "DMPR3_B2P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x5C2C++0x3 line.long 0x0 "DMPR3_B2P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x602C++0x3 line.long 0x0 "DMPR3_B3P6T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x622C++0x3 line.long 0x0 "DMPR3_B3P6T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x642C++0x3 line.long 0x0 "DMPR3_B3P6T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x682C++0x3 line.long 0x0 "DMPR3_B3P7T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6A2C++0x3 line.long 0x0 "DMPR3_B3P7T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C2C++0x3 line.long 0x0 "DMPR3_B3P7T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x702C++0x3 line.long 0x0 "DMPR3_B3P8T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x722C++0x3 line.long 0x0 "DMPR3_B3P8T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x742C++0x3 line.long 0x0 "DMPR3_B3P8T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x782C++0x3 line.long 0x0 "DMPR3_B3P9T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7A2C++0x3 line.long 0x0 "DMPR3_B3P9T1,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x7C2C++0x3 line.long 0x0 "DMPR3_B3P9T2,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PR,Bus Domain Protection" group.long 0x6C++0x3 line.long 0x0 "IP3SR_B0P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x26C++0x3 line.long 0x0 "IP3SR_B0P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x46C++0x3 line.long 0x0 "IP3SR_B0P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x86C++0x3 line.long 0x0 "IP3SR_B0P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xA6C++0x3 line.long 0x0 "IP3SR_B0P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xC6C++0x3 line.long 0x0 "IP3SR_B0P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x106C++0x3 line.long 0x0 "IP3SR_B0P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x126C++0x3 line.long 0x0 "IP3SR_B0P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x146C++0x3 line.long 0x0 "IP3SR_B0P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x186C++0x3 line.long 0x0 "IP3SR_B0P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1A6C++0x3 line.long 0x0 "IP3SR_B0P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1C6C++0x3 line.long 0x0 "IP3SR_B0P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x206C++0x3 line.long 0x0 "IP3SR_B1P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x226C++0x3 line.long 0x0 "IP3SR_B1P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x246C++0x3 line.long 0x0 "IP3SR_B1P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x286C++0x3 line.long 0x0 "IP3SR_B1P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2A6C++0x3 line.long 0x0 "IP3SR_B1P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2C6C++0x3 line.long 0x0 "IP3SR_B1P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x306C++0x3 line.long 0x0 "IP3SR_B1P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x326C++0x3 line.long 0x0 "IP3SR_B1P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x346C++0x3 line.long 0x0 "IP3SR_B1P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x386C++0x3 line.long 0x0 "IP3SR_B1P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3A6C++0x3 line.long 0x0 "IP3SR_B1P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3C6C++0x3 line.long 0x0 "IP3SR_B1P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x406C++0x3 line.long 0x0 "IP3SR_B2P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x426C++0x3 line.long 0x0 "IP3SR_B2P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x446C++0x3 line.long 0x0 "IP3SR_B2P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x486C++0x3 line.long 0x0 "IP3SR_B2P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4A6C++0x3 line.long 0x0 "IP3SR_B2P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4C6C++0x3 line.long 0x0 "IP3SR_B2P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x506C++0x3 line.long 0x0 "IP3SR_B2P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x526C++0x3 line.long 0x0 "IP3SR_B2P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x546C++0x3 line.long 0x0 "IP3SR_B2P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x586C++0x3 line.long 0x0 "IP3SR_B2P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5A6C++0x3 line.long 0x0 "IP3SR_B2P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5C6C++0x3 line.long 0x0 "IP3SR_B2P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x606C++0x3 line.long 0x0 "IP3SR_B3P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x626C++0x3 line.long 0x0 "IP3SR_B3P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x646C++0x3 line.long 0x0 "IP3SR_B3P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x686C++0x3 line.long 0x0 "IP3SR_B3P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6A6C++0x3 line.long 0x0 "IP3SR_B3P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6C6C++0x3 line.long 0x0 "IP3SR_B3P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x706C++0x3 line.long 0x0 "IP3SR_B3P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x726C++0x3 line.long 0x0 "IP3SR_B3P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x746C++0x3 line.long 0x0 "IP3SR_B3P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x786C++0x3 line.long 0x0 "IP3SR_B3P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7A6C++0x3 line.long 0x0 "IP3SR_B3P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7C6C++0x3 line.long 0x0 "IP3SR_B3P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x84++0x3 line.long 0x0 "DRV1CTRL_B0P6T0,DRV Control Register1 B0P6T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x284++0x3 line.long 0x0 "DRV1CTRL_B0P6T1,DRV Control Register1 B0P6T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x484++0x3 line.long 0x0 "DRV1CTRL_B0P6T2,DRV Control Register1 B0P6T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x884++0x3 line.long 0x0 "DRV1CTRL_B0P7T0,DRV Control Register1 B0P7T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0xA84++0x3 line.long 0x0 "DRV1CTRL_B0P7T1,DRV Control Register1 B0P7T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0xC84++0x3 line.long 0x0 "DRV1CTRL_B0P7T2,DRV Control Register1 B0P7T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x1084++0x3 line.long 0x0 "DRV1CTRL_B0P8T0,DRV Control Register1 B0P8T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x1284++0x3 line.long 0x0 "DRV1CTRL_B0P8T1,DRV Control Register1 B0P8T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x1484++0x3 line.long 0x0 "DRV1CTRL_B0P8T2,DRV Control Register1 B0P8T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x1884++0x3 line.long 0x0 "DRV1CTRL_B0P9T0,DRV Control Register1 B0P9T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x1A84++0x3 line.long 0x0 "DRV1CTRL_B0P9T1,DRV Control Register1 B0P9T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x1C84++0x3 line.long 0x0 "DRV1CTRL_B0P9T2,DRV Control Register1 B0P9T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2084++0x3 line.long 0x0 "DRV1CTRL_B1P6T0,DRV Control Register1 B1P6T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2284++0x3 line.long 0x0 "DRV1CTRL_B1P6T1,DRV Control Register1 B1P6T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2484++0x3 line.long 0x0 "DRV1CTRL_B1P6T2,DRV Control Register1 B1P6T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2884++0x3 line.long 0x0 "DRV1CTRL_B1P7T0,DRV Control Register1 B1P7T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2A84++0x3 line.long 0x0 "DRV1CTRL_B1P7T1,DRV Control Register1 B1P7T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x2C84++0x3 line.long 0x0 "DRV1CTRL_B1P7T2,DRV Control Register1 B1P7T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x3084++0x3 line.long 0x0 "DRV1CTRL_B1P8T0,DRV Control Register1 B1P8T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x3284++0x3 line.long 0x0 "DRV1CTRL_B1P8T1,DRV Control Register1 B1P8T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x3484++0x3 line.long 0x0 "DRV1CTRL_B1P8T2,DRV Control Register1 B1P8T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x3884++0x3 line.long 0x0 "DRV1CTRL_B1P9T0,DRV Control Register1 B1P9T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x3A84++0x3 line.long 0x0 "DRV1CTRL_B1P9T1,DRV Control Register1 B1P9T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x3C84++0x3 line.long 0x0 "DRV1CTRL_B1P9T2,DRV Control Register1 B1P9T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4084++0x3 line.long 0x0 "DRV1CTRL_B2P6T0,DRV Control Register1 B2P6T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4284++0x3 line.long 0x0 "DRV1CTRL_B2P6T1,DRV Control Register1 B2P6T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4484++0x3 line.long 0x0 "DRV1CTRL_B2P6T2,DRV Control Register1 B2P6T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4884++0x3 line.long 0x0 "DRV1CTRL_B2P7T0,DRV Control Register1 B2P7T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4A84++0x3 line.long 0x0 "DRV1CTRL_B2P7T1,DRV Control Register1 B2P7T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x4C84++0x3 line.long 0x0 "DRV1CTRL_B2P7T2,DRV Control Register1 B2P7T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x5084++0x3 line.long 0x0 "DRV1CTRL_B2P8T0,DRV Control Register1 B2P8T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x5284++0x3 line.long 0x0 "DRV1CTRL_B2P8T1,DRV Control Register1 B2P8T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x5484++0x3 line.long 0x0 "DRV1CTRL_B2P8T2,DRV Control Register1 B2P8T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x5884++0x3 line.long 0x0 "DRV1CTRL_B2P9T0,DRV Control Register1 B2P9T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x5A84++0x3 line.long 0x0 "DRV1CTRL_B2P9T1,DRV Control Register1 B2P9T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x5C84++0x3 line.long 0x0 "DRV1CTRL_B2P9T2,DRV Control Register1 B2P9T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6084++0x3 line.long 0x0 "DRV1CTRL_B3P6T0,DRV Control Register1 B3P6T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6284++0x3 line.long 0x0 "DRV1CTRL_B3P6T1,DRV Control Register1 B3P6T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6484++0x3 line.long 0x0 "DRV1CTRL_B3P6T2,DRV Control Register1 B3P6T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6884++0x3 line.long 0x0 "DRV1CTRL_B3P7T0,DRV Control Register1 B3P7T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6A84++0x3 line.long 0x0 "DRV1CTRL_B3P7T1,DRV Control Register1 B3P7T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x6C84++0x3 line.long 0x0 "DRV1CTRL_B3P7T2,DRV Control Register1 B3P7T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x7084++0x3 line.long 0x0 "DRV1CTRL_B3P8T0,DRV Control Register1 B3P8T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x7284++0x3 line.long 0x0 "DRV1CTRL_B3P8T1,DRV Control Register1 B3P8T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x7484++0x3 line.long 0x0 "DRV1CTRL_B3P8T2,DRV Control Register1 B3P8T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x7884++0x3 line.long 0x0 "DRV1CTRL_B3P9T0,DRV Control Register1 B3P9T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x7A84++0x3 line.long 0x0 "DRV1CTRL_B3P9T1,DRV Control Register1 B3P9T1" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x7C84++0x3 line.long 0x0 "DRV1CTRL_B3P9T2,DRV Control Register1 B3P9T2" hexmask.long 0x0 0.--31. 1. "DRV1CTRL" group.long 0x100++0x3 line.long 0x0 "MODSEL_B0P6T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x300++0x3 line.long 0x0 "MODSEL_B0P6T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x500++0x3 line.long 0x0 "MODSEL_B0P6T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x900++0x3 line.long 0x0 "MODSEL_B0P7T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0xB00++0x3 line.long 0x0 "MODSEL_B0P7T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0xD00++0x3 line.long 0x0 "MODSEL_B0P7T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x1100++0x3 line.long 0x0 "MODSEL_B0P8T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x1300++0x3 line.long 0x0 "MODSEL_B0P8T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x1500++0x3 line.long 0x0 "MODSEL_B0P8T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x1900++0x3 line.long 0x0 "MODSEL_B0P9T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x1B00++0x3 line.long 0x0 "MODSEL_B0P9T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x1D00++0x3 line.long 0x0 "MODSEL_B0P9T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2100++0x3 line.long 0x0 "MODSEL_B1P6T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2300++0x3 line.long 0x0 "MODSEL_B1P6T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2500++0x3 line.long 0x0 "MODSEL_B1P6T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2900++0x3 line.long 0x0 "MODSEL_B1P7T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2B00++0x3 line.long 0x0 "MODSEL_B1P7T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x2D00++0x3 line.long 0x0 "MODSEL_B1P7T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x3100++0x3 line.long 0x0 "MODSEL_B1P8T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x3300++0x3 line.long 0x0 "MODSEL_B1P8T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x3500++0x3 line.long 0x0 "MODSEL_B1P8T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x3900++0x3 line.long 0x0 "MODSEL_B1P9T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x3B00++0x3 line.long 0x0 "MODSEL_B1P9T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x3D00++0x3 line.long 0x0 "MODSEL_B1P9T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4100++0x3 line.long 0x0 "MODSEL_B2P6T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4300++0x3 line.long 0x0 "MODSEL_B2P6T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4500++0x3 line.long 0x0 "MODSEL_B2P6T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4900++0x3 line.long 0x0 "MODSEL_B2P7T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4B00++0x3 line.long 0x0 "MODSEL_B2P7T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x4D00++0x3 line.long 0x0 "MODSEL_B2P7T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x5100++0x3 line.long 0x0 "MODSEL_B2P8T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x5300++0x3 line.long 0x0 "MODSEL_B2P8T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x5500++0x3 line.long 0x0 "MODSEL_B2P8T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x5900++0x3 line.long 0x0 "MODSEL_B2P9T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x5B00++0x3 line.long 0x0 "MODSEL_B2P9T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x5D00++0x3 line.long 0x0 "MODSEL_B2P9T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6100++0x3 line.long 0x0 "MODSEL_B3P6T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6300++0x3 line.long 0x0 "MODSEL_B3P6T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6500++0x3 line.long 0x0 "MODSEL_B3P6T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6900++0x3 line.long 0x0 "MODSEL_B3P7T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6B00++0x3 line.long 0x0 "MODSEL_B3P7T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x6D00++0x3 line.long 0x0 "MODSEL_B3P7T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x7100++0x3 line.long 0x0 "MODSEL_B3P8T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x7300++0x3 line.long 0x0 "MODSEL_B3P8T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x7500++0x3 line.long 0x0 "MODSEL_B3P8T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x7900++0x3 line.long 0x0 "MODSEL_B3P9T0,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x7B00++0x3 line.long 0x0 "MODSEL_B3P9T1,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x7D00++0x3 line.long 0x0 "MODSEL_B3P9T2,Function: MODSELn selects the group for multiple LSI pins with multiplexed pin functions." hexmask.long 0x0 0.--31. 1. "MODSEL" group.long 0x120++0x3 line.long 0x0 "TD0SEL_B0P6T0,TDSEL Control Register0 B0P6T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x320++0x3 line.long 0x0 "TD0SEL_B0P6T1,TDSEL Control Register0 B0P6T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x520++0x3 line.long 0x0 "TD0SEL_B0P6T2,TDSEL Control Register0 B0P6T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x920++0x3 line.long 0x0 "TD0SEL_B0P7T0,TDSEL Control Register0 B0P7T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0xB20++0x3 line.long 0x0 "TD0SEL_B0P7T1,TDSEL Control Register0 B0P7T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0xD20++0x3 line.long 0x0 "TD0SEL_B0P7T2,TDSEL Control Register0 B0P7T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x1120++0x3 line.long 0x0 "TD0SEL_B0P8T0,TDSEL Control Register0 B0P8T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x1320++0x3 line.long 0x0 "TD0SEL_B0P8T1,TDSEL Control Register0 B0P8T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x1520++0x3 line.long 0x0 "TD0SEL_B0P8T2,TDSEL Control Register0 B0P8T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x1920++0x3 line.long 0x0 "TD0SEL_B0P9T0,TDSEL Control Register0 B0P9T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x1B20++0x3 line.long 0x0 "TD0SEL_B0P9T1,TDSEL Control Register0 B0P9T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x1D20++0x3 line.long 0x0 "TD0SEL_B0P9T2,TDSEL Control Register0 B0P9T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2120++0x3 line.long 0x0 "TD0SEL_B1P6T0,TDSEL Control Register0 B1P6T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2320++0x3 line.long 0x0 "TD0SEL_B1P6T1,TDSEL Control Register0 B1P6T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2520++0x3 line.long 0x0 "TD0SEL_B1P6T2,TDSEL Control Register0 B1P6T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2920++0x3 line.long 0x0 "TD0SEL_B1P7T0,TDSEL Control Register0 B1P7T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2B20++0x3 line.long 0x0 "TD0SEL_B1P7T1,TDSEL Control Register0 B1P7T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x2D20++0x3 line.long 0x0 "TD0SEL_B1P7T2,TDSEL Control Register0 B1P7T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x3120++0x3 line.long 0x0 "TD0SEL_B1P8T0,TDSEL Control Register0 B1P8T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x3320++0x3 line.long 0x0 "TD0SEL_B1P8T1,TDSEL Control Register0 B1P8T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x3520++0x3 line.long 0x0 "TD0SEL_B1P8T2,TDSEL Control Register0 B1P8T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x3920++0x3 line.long 0x0 "TD0SEL_B1P9T0,TDSEL Control Register0 B1P9T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x3B20++0x3 line.long 0x0 "TD0SEL_B1P9T1,TDSEL Control Register0 B1P9T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x3D20++0x3 line.long 0x0 "TD0SEL_B1P9T2,TDSEL Control Register0 B1P9T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4120++0x3 line.long 0x0 "TD0SEL_B2P6T0,TDSEL Control Register0 B2P6T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4320++0x3 line.long 0x0 "TD0SEL_B2P6T1,TDSEL Control Register0 B2P6T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4520++0x3 line.long 0x0 "TD0SEL_B2P6T2,TDSEL Control Register0 B2P6T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4920++0x3 line.long 0x0 "TD0SEL_B2P7T0,TDSEL Control Register0 B2P7T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4B20++0x3 line.long 0x0 "TD0SEL_B2P7T1,TDSEL Control Register0 B2P7T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x4D20++0x3 line.long 0x0 "TD0SEL_B2P7T2,TDSEL Control Register0 B2P7T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x5120++0x3 line.long 0x0 "TD0SEL_B2P8T0,TDSEL Control Register0 B2P8T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x5320++0x3 line.long 0x0 "TD0SEL_B2P8T1,TDSEL Control Register0 B2P8T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x5520++0x3 line.long 0x0 "TD0SEL_B2P8T2,TDSEL Control Register0 B2P8T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x5920++0x3 line.long 0x0 "TD0SEL_B2P9T0,TDSEL Control Register0 B2P9T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x5B20++0x3 line.long 0x0 "TD0SEL_B2P9T1,TDSEL Control Register0 B2P9T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x5D20++0x3 line.long 0x0 "TD0SEL_B2P9T2,TDSEL Control Register0 B2P9T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6120++0x3 line.long 0x0 "TD0SEL_B3P6T0,TDSEL Control Register0 B3P6T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6320++0x3 line.long 0x0 "TD0SEL_B3P6T1,TDSEL Control Register0 B3P6T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6520++0x3 line.long 0x0 "TD0SEL_B3P6T2,TDSEL Control Register0 B3P6T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6920++0x3 line.long 0x0 "TD0SEL_B3P7T0,TDSEL Control Register0 B3P7T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6B20++0x3 line.long 0x0 "TD0SEL_B3P7T1,TDSEL Control Register0 B3P7T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x6D20++0x3 line.long 0x0 "TD0SEL_B3P7T2,TDSEL Control Register0 B3P7T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x7120++0x3 line.long 0x0 "TD0SEL_B3P8T0,TDSEL Control Register0 B3P8T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x7320++0x3 line.long 0x0 "TD0SEL_B3P8T1,TDSEL Control Register0 B3P8T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x7520++0x3 line.long 0x0 "TD0SEL_B3P8T2,TDSEL Control Register0 B3P8T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x7920++0x3 line.long 0x0 "TD0SEL_B3P9T0,TDSEL Control Register0 B3P9T0" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x7B20++0x3 line.long 0x0 "TD0SEL_B3P9T1,TDSEL Control Register0 B3P9T1" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x7D20++0x3 line.long 0x0 "TD0SEL_B3P9T2,TDSEL Control Register0 B3P9T2" hexmask.long 0x0 0.--31. 1. "TD0SEL" group.long 0x124++0x3 line.long 0x0 "TD1SEL_B0P6T0,TDSEL Control Register1 B0P6T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x324++0x3 line.long 0x0 "TD1SEL_B0P6T1,TDSEL Control Register1 B0P6T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x524++0x3 line.long 0x0 "TD1SEL_B0P6T2,TDSEL Control Register1 B0P6T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x924++0x3 line.long 0x0 "TD1SEL_B0P7T0,TDSEL Control Register1 B0P7T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0xB24++0x3 line.long 0x0 "TD1SEL_B0P7T1,TDSEL Control Register1 B0P7T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0xD24++0x3 line.long 0x0 "TD1SEL_B0P7T2,TDSEL Control Register1 B0P7T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x1124++0x3 line.long 0x0 "TD1SEL_B0P8T0,TDSEL Control Register1 B0P8T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x1324++0x3 line.long 0x0 "TD1SEL_B0P8T1,TDSEL Control Register1 B0P8T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x1524++0x3 line.long 0x0 "TD1SEL_B0P8T2,TDSEL Control Register1 B0P8T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x1924++0x3 line.long 0x0 "TD1SEL_B0P9T0,TDSEL Control Register1 B0P9T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x1B24++0x3 line.long 0x0 "TD1SEL_B0P9T1,TDSEL Control Register1 B0P9T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x1D24++0x3 line.long 0x0 "TD1SEL_B0P9T2,TDSEL Control Register1 B0P9T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2124++0x3 line.long 0x0 "TD1SEL_B1P6T0,TDSEL Control Register1 B1P6T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2324++0x3 line.long 0x0 "TD1SEL_B1P6T1,TDSEL Control Register1 B1P6T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2524++0x3 line.long 0x0 "TD1SEL_B1P6T2,TDSEL Control Register1 B1P6T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2924++0x3 line.long 0x0 "TD1SEL_B1P7T0,TDSEL Control Register1 B1P7T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2B24++0x3 line.long 0x0 "TD1SEL_B1P7T1,TDSEL Control Register1 B1P7T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x2D24++0x3 line.long 0x0 "TD1SEL_B1P7T2,TDSEL Control Register1 B1P7T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x3124++0x3 line.long 0x0 "TD1SEL_B1P8T0,TDSEL Control Register1 B1P8T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x3324++0x3 line.long 0x0 "TD1SEL_B1P8T1,TDSEL Control Register1 B1P8T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x3524++0x3 line.long 0x0 "TD1SEL_B1P8T2,TDSEL Control Register1 B1P8T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x3924++0x3 line.long 0x0 "TD1SEL_B1P9T0,TDSEL Control Register1 B1P9T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x3B24++0x3 line.long 0x0 "TD1SEL_B1P9T1,TDSEL Control Register1 B1P9T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x3D24++0x3 line.long 0x0 "TD1SEL_B1P9T2,TDSEL Control Register1 B1P9T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4124++0x3 line.long 0x0 "TD1SEL_B2P6T0,TDSEL Control Register1 B2P6T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4324++0x3 line.long 0x0 "TD1SEL_B2P6T1,TDSEL Control Register1 B2P6T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4524++0x3 line.long 0x0 "TD1SEL_B2P6T2,TDSEL Control Register1 B2P6T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4924++0x3 line.long 0x0 "TD1SEL_B2P7T0,TDSEL Control Register1 B2P7T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4B24++0x3 line.long 0x0 "TD1SEL_B2P7T1,TDSEL Control Register1 B2P7T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x4D24++0x3 line.long 0x0 "TD1SEL_B2P7T2,TDSEL Control Register1 B2P7T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x5124++0x3 line.long 0x0 "TD1SEL_B2P8T0,TDSEL Control Register1 B2P8T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x5324++0x3 line.long 0x0 "TD1SEL_B2P8T1,TDSEL Control Register1 B2P8T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x5524++0x3 line.long 0x0 "TD1SEL_B2P8T2,TDSEL Control Register1 B2P8T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x5924++0x3 line.long 0x0 "TD1SEL_B2P9T0,TDSEL Control Register1 B2P9T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x5B24++0x3 line.long 0x0 "TD1SEL_B2P9T1,TDSEL Control Register1 B2P9T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x5D24++0x3 line.long 0x0 "TD1SEL_B2P9T2,TDSEL Control Register1 B2P9T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6124++0x3 line.long 0x0 "TD1SEL_B3P6T0,TDSEL Control Register1 B3P6T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6324++0x3 line.long 0x0 "TD1SEL_B3P6T1,TDSEL Control Register1 B3P6T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6524++0x3 line.long 0x0 "TD1SEL_B3P6T2,TDSEL Control Register1 B3P6T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6924++0x3 line.long 0x0 "TD1SEL_B3P7T0,TDSEL Control Register1 B3P7T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6B24++0x3 line.long 0x0 "TD1SEL_B3P7T1,TDSEL Control Register1 B3P7T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x6D24++0x3 line.long 0x0 "TD1SEL_B3P7T2,TDSEL Control Register1 B3P7T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x7124++0x3 line.long 0x0 "TD1SEL_B3P8T0,TDSEL Control Register1 B3P8T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x7324++0x3 line.long 0x0 "TD1SEL_B3P8T1,TDSEL Control Register1 B3P8T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x7524++0x3 line.long 0x0 "TD1SEL_B3P8T2,TDSEL Control Register1 B3P8T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x7924++0x3 line.long 0x0 "TD1SEL_B3P9T0,TDSEL Control Register1 B3P9T0" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x7B24++0x3 line.long 0x0 "TD1SEL_B3P9T1,TDSEL Control Register1 B3P9T1" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x7D24++0x3 line.long 0x0 "TD1SEL_B3P9T2,TDSEL Control Register1 B3P9T2" hexmask.long 0x0 0.--31. 1. "TD1SEL" group.long 0x140++0x3 line.long 0x0 "BIPSR0_B0P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x340++0x3 line.long 0x0 "BIPSR0_B0P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x540++0x3 line.long 0x0 "BIPSR0_B0P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x940++0x3 line.long 0x0 "BIPSR0_B0P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB40++0x3 line.long 0x0 "BIPSR0_B0P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD40++0x3 line.long 0x0 "BIPSR0_B0P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1140++0x3 line.long 0x0 "BIPSR0_B0P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1340++0x3 line.long 0x0 "BIPSR0_B0P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1540++0x3 line.long 0x0 "BIPSR0_B0P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1940++0x3 line.long 0x0 "BIPSR0_B0P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1B40++0x3 line.long 0x0 "BIPSR0_B0P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1D40++0x3 line.long 0x0 "BIPSR0_B0P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2140++0x3 line.long 0x0 "BIPSR0_B1P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2340++0x3 line.long 0x0 "BIPSR0_B1P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2540++0x3 line.long 0x0 "BIPSR0_B1P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2940++0x3 line.long 0x0 "BIPSR0_B1P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B40++0x3 line.long 0x0 "BIPSR0_B1P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D40++0x3 line.long 0x0 "BIPSR0_B1P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3140++0x3 line.long 0x0 "BIPSR0_B1P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3340++0x3 line.long 0x0 "BIPSR0_B1P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3540++0x3 line.long 0x0 "BIPSR0_B1P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3940++0x3 line.long 0x0 "BIPSR0_B1P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3B40++0x3 line.long 0x0 "BIPSR0_B1P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3D40++0x3 line.long 0x0 "BIPSR0_B1P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4140++0x3 line.long 0x0 "BIPSR0_B2P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4340++0x3 line.long 0x0 "BIPSR0_B2P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4540++0x3 line.long 0x0 "BIPSR0_B2P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4940++0x3 line.long 0x0 "BIPSR0_B2P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B40++0x3 line.long 0x0 "BIPSR0_B2P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D40++0x3 line.long 0x0 "BIPSR0_B2P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5140++0x3 line.long 0x0 "BIPSR0_B2P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5340++0x3 line.long 0x0 "BIPSR0_B2P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5540++0x3 line.long 0x0 "BIPSR0_B2P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5940++0x3 line.long 0x0 "BIPSR0_B2P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5B40++0x3 line.long 0x0 "BIPSR0_B2P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5D40++0x3 line.long 0x0 "BIPSR0_B2P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6140++0x3 line.long 0x0 "BIPSR0_B3P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6340++0x3 line.long 0x0 "BIPSR0_B3P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6540++0x3 line.long 0x0 "BIPSR0_B3P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6940++0x3 line.long 0x0 "BIPSR0_B3P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B40++0x3 line.long 0x0 "BIPSR0_B3P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D40++0x3 line.long 0x0 "BIPSR0_B3P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7140++0x3 line.long 0x0 "BIPSR0_B3P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7340++0x3 line.long 0x0 "BIPSR0_B3P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7540++0x3 line.long 0x0 "BIPSR0_B3P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7940++0x3 line.long 0x0 "BIPSR0_B3P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7B40++0x3 line.long 0x0 "BIPSR0_B3P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7D40++0x3 line.long 0x0 "BIPSR0_B3P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x144++0x3 line.long 0x0 "BIPSR1_B0P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x344++0x3 line.long 0x0 "BIPSR1_B0P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x544++0x3 line.long 0x0 "BIPSR1_B0P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x944++0x3 line.long 0x0 "BIPSR1_B0P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB44++0x3 line.long 0x0 "BIPSR1_B0P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD44++0x3 line.long 0x0 "BIPSR1_B0P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1144++0x3 line.long 0x0 "BIPSR1_B0P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1344++0x3 line.long 0x0 "BIPSR1_B0P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1544++0x3 line.long 0x0 "BIPSR1_B0P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1944++0x3 line.long 0x0 "BIPSR1_B0P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1B44++0x3 line.long 0x0 "BIPSR1_B0P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1D44++0x3 line.long 0x0 "BIPSR1_B0P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2144++0x3 line.long 0x0 "BIPSR1_B1P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2344++0x3 line.long 0x0 "BIPSR1_B1P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2544++0x3 line.long 0x0 "BIPSR1_B1P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2944++0x3 line.long 0x0 "BIPSR1_B1P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B44++0x3 line.long 0x0 "BIPSR1_B1P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D44++0x3 line.long 0x0 "BIPSR1_B1P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3144++0x3 line.long 0x0 "BIPSR1_B1P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3344++0x3 line.long 0x0 "BIPSR1_B1P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3544++0x3 line.long 0x0 "BIPSR1_B1P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3944++0x3 line.long 0x0 "BIPSR1_B1P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3B44++0x3 line.long 0x0 "BIPSR1_B1P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3D44++0x3 line.long 0x0 "BIPSR1_B1P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4144++0x3 line.long 0x0 "BIPSR1_B2P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4344++0x3 line.long 0x0 "BIPSR1_B2P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4544++0x3 line.long 0x0 "BIPSR1_B2P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4944++0x3 line.long 0x0 "BIPSR1_B2P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B44++0x3 line.long 0x0 "BIPSR1_B2P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D44++0x3 line.long 0x0 "BIPSR1_B2P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5144++0x3 line.long 0x0 "BIPSR1_B2P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5344++0x3 line.long 0x0 "BIPSR1_B2P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5544++0x3 line.long 0x0 "BIPSR1_B2P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5944++0x3 line.long 0x0 "BIPSR1_B2P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5B44++0x3 line.long 0x0 "BIPSR1_B2P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5D44++0x3 line.long 0x0 "BIPSR1_B2P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6144++0x3 line.long 0x0 "BIPSR1_B3P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6344++0x3 line.long 0x0 "BIPSR1_B3P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6544++0x3 line.long 0x0 "BIPSR1_B3P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6944++0x3 line.long 0x0 "BIPSR1_B3P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B44++0x3 line.long 0x0 "BIPSR1_B3P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D44++0x3 line.long 0x0 "BIPSR1_B3P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7144++0x3 line.long 0x0 "BIPSR1_B3P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7344++0x3 line.long 0x0 "BIPSR1_B3P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7544++0x3 line.long 0x0 "BIPSR1_B3P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7944++0x3 line.long 0x0 "BIPSR1_B3P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7B44++0x3 line.long 0x0 "BIPSR1_B3P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7D44++0x3 line.long 0x0 "BIPSR1_B3P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x148++0x3 line.long 0x0 "BIPSR2_B0P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x348++0x3 line.long 0x0 "BIPSR2_B0P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x548++0x3 line.long 0x0 "BIPSR2_B0P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x948++0x3 line.long 0x0 "BIPSR2_B0P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB48++0x3 line.long 0x0 "BIPSR2_B0P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD48++0x3 line.long 0x0 "BIPSR2_B0P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1148++0x3 line.long 0x0 "BIPSR2_B0P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1348++0x3 line.long 0x0 "BIPSR2_B0P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1548++0x3 line.long 0x0 "BIPSR2_B0P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1948++0x3 line.long 0x0 "BIPSR2_B0P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1B48++0x3 line.long 0x0 "BIPSR2_B0P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1D48++0x3 line.long 0x0 "BIPSR2_B0P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2148++0x3 line.long 0x0 "BIPSR2_B1P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2348++0x3 line.long 0x0 "BIPSR2_B1P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2548++0x3 line.long 0x0 "BIPSR2_B1P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2948++0x3 line.long 0x0 "BIPSR2_B1P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B48++0x3 line.long 0x0 "BIPSR2_B1P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D48++0x3 line.long 0x0 "BIPSR2_B1P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3148++0x3 line.long 0x0 "BIPSR2_B1P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3348++0x3 line.long 0x0 "BIPSR2_B1P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3548++0x3 line.long 0x0 "BIPSR2_B1P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3948++0x3 line.long 0x0 "BIPSR2_B1P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3B48++0x3 line.long 0x0 "BIPSR2_B1P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3D48++0x3 line.long 0x0 "BIPSR2_B1P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4148++0x3 line.long 0x0 "BIPSR2_B2P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4348++0x3 line.long 0x0 "BIPSR2_B2P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4548++0x3 line.long 0x0 "BIPSR2_B2P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4948++0x3 line.long 0x0 "BIPSR2_B2P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B48++0x3 line.long 0x0 "BIPSR2_B2P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D48++0x3 line.long 0x0 "BIPSR2_B2P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5148++0x3 line.long 0x0 "BIPSR2_B2P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5348++0x3 line.long 0x0 "BIPSR2_B2P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5548++0x3 line.long 0x0 "BIPSR2_B2P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5948++0x3 line.long 0x0 "BIPSR2_B2P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5B48++0x3 line.long 0x0 "BIPSR2_B2P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5D48++0x3 line.long 0x0 "BIPSR2_B2P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6148++0x3 line.long 0x0 "BIPSR2_B3P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6348++0x3 line.long 0x0 "BIPSR2_B3P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6548++0x3 line.long 0x0 "BIPSR2_B3P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6948++0x3 line.long 0x0 "BIPSR2_B3P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B48++0x3 line.long 0x0 "BIPSR2_B3P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D48++0x3 line.long 0x0 "BIPSR2_B3P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7148++0x3 line.long 0x0 "BIPSR2_B3P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7348++0x3 line.long 0x0 "BIPSR2_B3P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7548++0x3 line.long 0x0 "BIPSR2_B3P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7948++0x3 line.long 0x0 "BIPSR2_B3P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7B48++0x3 line.long 0x0 "BIPSR2_B3P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7D48++0x3 line.long 0x0 "BIPSR2_B3P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x14C++0x3 line.long 0x0 "BIPSR3_B0P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x34C++0x3 line.long 0x0 "BIPSR3_B0P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x54C++0x3 line.long 0x0 "BIPSR3_B0P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x94C++0x3 line.long 0x0 "BIPSR3_B0P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xB4C++0x3 line.long 0x0 "BIPSR3_B0P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0xD4C++0x3 line.long 0x0 "BIPSR3_B0P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x114C++0x3 line.long 0x0 "BIPSR3_B0P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x134C++0x3 line.long 0x0 "BIPSR3_B0P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x154C++0x3 line.long 0x0 "BIPSR3_B0P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x194C++0x3 line.long 0x0 "BIPSR3_B0P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1B4C++0x3 line.long 0x0 "BIPSR3_B0P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x1D4C++0x3 line.long 0x0 "BIPSR3_B0P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x214C++0x3 line.long 0x0 "BIPSR3_B1P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x234C++0x3 line.long 0x0 "BIPSR3_B1P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x254C++0x3 line.long 0x0 "BIPSR3_B1P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x294C++0x3 line.long 0x0 "BIPSR3_B1P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2B4C++0x3 line.long 0x0 "BIPSR3_B1P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x2D4C++0x3 line.long 0x0 "BIPSR3_B1P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x314C++0x3 line.long 0x0 "BIPSR3_B1P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x334C++0x3 line.long 0x0 "BIPSR3_B1P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x354C++0x3 line.long 0x0 "BIPSR3_B1P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x394C++0x3 line.long 0x0 "BIPSR3_B1P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3B4C++0x3 line.long 0x0 "BIPSR3_B1P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x3D4C++0x3 line.long 0x0 "BIPSR3_B1P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x414C++0x3 line.long 0x0 "BIPSR3_B2P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x434C++0x3 line.long 0x0 "BIPSR3_B2P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x454C++0x3 line.long 0x0 "BIPSR3_B2P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x494C++0x3 line.long 0x0 "BIPSR3_B2P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4B4C++0x3 line.long 0x0 "BIPSR3_B2P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x4D4C++0x3 line.long 0x0 "BIPSR3_B2P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x514C++0x3 line.long 0x0 "BIPSR3_B2P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x534C++0x3 line.long 0x0 "BIPSR3_B2P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x554C++0x3 line.long 0x0 "BIPSR3_B2P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x594C++0x3 line.long 0x0 "BIPSR3_B2P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5B4C++0x3 line.long 0x0 "BIPSR3_B2P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x5D4C++0x3 line.long 0x0 "BIPSR3_B2P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x614C++0x3 line.long 0x0 "BIPSR3_B3P6T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x634C++0x3 line.long 0x0 "BIPSR3_B3P6T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x654C++0x3 line.long 0x0 "BIPSR3_B3P6T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x694C++0x3 line.long 0x0 "BIPSR3_B3P7T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6B4C++0x3 line.long 0x0 "BIPSR3_B3P7T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x6D4C++0x3 line.long 0x0 "BIPSR3_B3P7T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x714C++0x3 line.long 0x0 "BIPSR3_B3P8T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x734C++0x3 line.long 0x0 "BIPSR3_B3P8T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x754C++0x3 line.long 0x0 "BIPSR3_B3P8T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x794C++0x3 line.long 0x0 "BIPSR3_B3P9T0,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7B4C++0x3 line.long 0x0 "BIPSR3_B3P9T1,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x7D4C++0x3 line.long 0x0 "BIPSR3_B3P9T2,Function: IP*SRn selects the functions of the multiplexed LSI pins." hexmask.long 0x0 0.--31. 1. "IP0SR,The functions of the LSI pins are selected according to the table below." group.long 0x160++0x3 line.long 0x0 "PSER_B0P6T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x360++0x3 line.long 0x0 "PSER_B0P6T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x560++0x3 line.long 0x0 "PSER_B0P6T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x960++0x3 line.long 0x0 "PSER_B0P7T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0xB60++0x3 line.long 0x0 "PSER_B0P7T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0xD60++0x3 line.long 0x0 "PSER_B0P7T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x1160++0x3 line.long 0x0 "PSER_B0P8T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x1360++0x3 line.long 0x0 "PSER_B0P8T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x1560++0x3 line.long 0x0 "PSER_B0P8T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x1960++0x3 line.long 0x0 "PSER_B0P9T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x1B60++0x3 line.long 0x0 "PSER_B0P9T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x1D60++0x3 line.long 0x0 "PSER_B0P9T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2160++0x3 line.long 0x0 "PSER_B1P6T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2360++0x3 line.long 0x0 "PSER_B1P6T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2560++0x3 line.long 0x0 "PSER_B1P6T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2960++0x3 line.long 0x0 "PSER_B1P7T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2B60++0x3 line.long 0x0 "PSER_B1P7T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x2D60++0x3 line.long 0x0 "PSER_B1P7T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x3160++0x3 line.long 0x0 "PSER_B1P8T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x3360++0x3 line.long 0x0 "PSER_B1P8T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x3560++0x3 line.long 0x0 "PSER_B1P8T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x3960++0x3 line.long 0x0 "PSER_B1P9T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x3B60++0x3 line.long 0x0 "PSER_B1P9T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x3D60++0x3 line.long 0x0 "PSER_B1P9T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4160++0x3 line.long 0x0 "PSER_B2P6T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4360++0x3 line.long 0x0 "PSER_B2P6T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4560++0x3 line.long 0x0 "PSER_B2P6T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4960++0x3 line.long 0x0 "PSER_B2P7T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4B60++0x3 line.long 0x0 "PSER_B2P7T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x4D60++0x3 line.long 0x0 "PSER_B2P7T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x5160++0x3 line.long 0x0 "PSER_B2P8T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x5360++0x3 line.long 0x0 "PSER_B2P8T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x5560++0x3 line.long 0x0 "PSER_B2P8T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x5960++0x3 line.long 0x0 "PSER_B2P9T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x5B60++0x3 line.long 0x0 "PSER_B2P9T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x5D60++0x3 line.long 0x0 "PSER_B2P9T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6160++0x3 line.long 0x0 "PSER_B3P6T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6360++0x3 line.long 0x0 "PSER_B3P6T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6560++0x3 line.long 0x0 "PSER_B3P6T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6960++0x3 line.long 0x0 "PSER_B3P7T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6B60++0x3 line.long 0x0 "PSER_B3P7T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x6D60++0x3 line.long 0x0 "PSER_B3P7T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x7160++0x3 line.long 0x0 "PSER_B3P8T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x7360++0x3 line.long 0x0 "PSER_B3P8T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x7560++0x3 line.long 0x0 "PSER_B3P8T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x7960++0x3 line.long 0x0 "PSER_B3P9T0,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x7B60++0x3 line.long 0x0 "PSER_B3P9T1,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x7D60++0x3 line.long 0x0 "PSER_B3P9T2,The register (PSERn) to enable / disable PSS Rregister." hexmask.long 0x0 0.--31. 1. "PSER,0: PSSR disable." group.long 0x164++0x3 line.long 0x0 "PS0SR_B0P6T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x364++0x3 line.long 0x0 "PS0SR_B0P6T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x564++0x3 line.long 0x0 "PS0SR_B0P6T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x964++0x3 line.long 0x0 "PS0SR_B0P7T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0xB64++0x3 line.long 0x0 "PS0SR_B0P7T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0xD64++0x3 line.long 0x0 "PS0SR_B0P7T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x1164++0x3 line.long 0x0 "PS0SR_B0P8T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x1364++0x3 line.long 0x0 "PS0SR_B0P8T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x1564++0x3 line.long 0x0 "PS0SR_B0P8T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x1964++0x3 line.long 0x0 "PS0SR_B0P9T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x1B64++0x3 line.long 0x0 "PS0SR_B0P9T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x1D64++0x3 line.long 0x0 "PS0SR_B0P9T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2164++0x3 line.long 0x0 "PS0SR_B1P6T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2364++0x3 line.long 0x0 "PS0SR_B1P6T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2564++0x3 line.long 0x0 "PS0SR_B1P6T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2964++0x3 line.long 0x0 "PS0SR_B1P7T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2B64++0x3 line.long 0x0 "PS0SR_B1P7T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x2D64++0x3 line.long 0x0 "PS0SR_B1P7T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x3164++0x3 line.long 0x0 "PS0SR_B1P8T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x3364++0x3 line.long 0x0 "PS0SR_B1P8T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x3564++0x3 line.long 0x0 "PS0SR_B1P8T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x3964++0x3 line.long 0x0 "PS0SR_B1P9T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x3B64++0x3 line.long 0x0 "PS0SR_B1P9T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x3D64++0x3 line.long 0x0 "PS0SR_B1P9T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4164++0x3 line.long 0x0 "PS0SR_B2P6T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4364++0x3 line.long 0x0 "PS0SR_B2P6T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4564++0x3 line.long 0x0 "PS0SR_B2P6T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4964++0x3 line.long 0x0 "PS0SR_B2P7T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4B64++0x3 line.long 0x0 "PS0SR_B2P7T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x4D64++0x3 line.long 0x0 "PS0SR_B2P7T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x5164++0x3 line.long 0x0 "PS0SR_B2P8T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x5364++0x3 line.long 0x0 "PS0SR_B2P8T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x5564++0x3 line.long 0x0 "PS0SR_B2P8T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x5964++0x3 line.long 0x0 "PS0SR_B2P9T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x5B64++0x3 line.long 0x0 "PS0SR_B2P9T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x5D64++0x3 line.long 0x0 "PS0SR_B2P9T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6164++0x3 line.long 0x0 "PS0SR_B3P6T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6364++0x3 line.long 0x0 "PS0SR_B3P6T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6564++0x3 line.long 0x0 "PS0SR_B3P6T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6964++0x3 line.long 0x0 "PS0SR_B3P7T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6B64++0x3 line.long 0x0 "PS0SR_B3P7T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x6D64++0x3 line.long 0x0 "PS0SR_B3P7T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x7164++0x3 line.long 0x0 "PS0SR_B3P8T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x7364++0x3 line.long 0x0 "PS0SR_B3P8T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x7564++0x3 line.long 0x0 "PS0SR_B3P8T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x7964++0x3 line.long 0x0 "PS0SR_B3P9T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x7B64++0x3 line.long 0x0 "PS0SR_B3P9T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x7D64++0x3 line.long 0x0 "PS0SR_B3P9T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS0SR,b'00=initial state" group.long 0x168++0x3 line.long 0x0 "PS1SR_B0P6T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x368++0x3 line.long 0x0 "PS1SR_B0P6T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x568++0x3 line.long 0x0 "PS1SR_B0P6T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x968++0x3 line.long 0x0 "PS1SR_B0P7T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0xB68++0x3 line.long 0x0 "PS1SR_B0P7T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0xD68++0x3 line.long 0x0 "PS1SR_B0P7T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x1168++0x3 line.long 0x0 "PS1SR_B0P8T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x1368++0x3 line.long 0x0 "PS1SR_B0P8T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x1568++0x3 line.long 0x0 "PS1SR_B0P8T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x1968++0x3 line.long 0x0 "PS1SR_B0P9T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x1B68++0x3 line.long 0x0 "PS1SR_B0P9T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x1D68++0x3 line.long 0x0 "PS1SR_B0P9T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2168++0x3 line.long 0x0 "PS1SR_B1P6T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2368++0x3 line.long 0x0 "PS1SR_B1P6T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2568++0x3 line.long 0x0 "PS1SR_B1P6T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2968++0x3 line.long 0x0 "PS1SR_B1P7T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2B68++0x3 line.long 0x0 "PS1SR_B1P7T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x2D68++0x3 line.long 0x0 "PS1SR_B1P7T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x3168++0x3 line.long 0x0 "PS1SR_B1P8T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x3368++0x3 line.long 0x0 "PS1SR_B1P8T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x3568++0x3 line.long 0x0 "PS1SR_B1P8T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x3968++0x3 line.long 0x0 "PS1SR_B1P9T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x3B68++0x3 line.long 0x0 "PS1SR_B1P9T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x3D68++0x3 line.long 0x0 "PS1SR_B1P9T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4168++0x3 line.long 0x0 "PS1SR_B2P6T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4368++0x3 line.long 0x0 "PS1SR_B2P6T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4568++0x3 line.long 0x0 "PS1SR_B2P6T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4968++0x3 line.long 0x0 "PS1SR_B2P7T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4B68++0x3 line.long 0x0 "PS1SR_B2P7T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x4D68++0x3 line.long 0x0 "PS1SR_B2P7T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x5168++0x3 line.long 0x0 "PS1SR_B2P8T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x5368++0x3 line.long 0x0 "PS1SR_B2P8T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x5568++0x3 line.long 0x0 "PS1SR_B2P8T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x5968++0x3 line.long 0x0 "PS1SR_B2P9T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x5B68++0x3 line.long 0x0 "PS1SR_B2P9T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x5D68++0x3 line.long 0x0 "PS1SR_B2P9T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6168++0x3 line.long 0x0 "PS1SR_B3P6T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6368++0x3 line.long 0x0 "PS1SR_B3P6T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6568++0x3 line.long 0x0 "PS1SR_B3P6T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6968++0x3 line.long 0x0 "PS1SR_B3P7T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6B68++0x3 line.long 0x0 "PS1SR_B3P7T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x6D68++0x3 line.long 0x0 "PS1SR_B3P7T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x7168++0x3 line.long 0x0 "PS1SR_B3P8T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x7368++0x3 line.long 0x0 "PS1SR_B3P8T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x7568++0x3 line.long 0x0 "PS1SR_B3P8T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x7968++0x3 line.long 0x0 "PS1SR_B3P9T0,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x7B68++0x3 line.long 0x0 "PS1SR_B3P9T1,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x7D68++0x3 line.long 0x0 "PS1SR_B3P9T2,Registers (PS*SRn) that select 4 types of Port Safe State (initial state or HiZ or Pull-Down or Pull-Up) with 2 bits." hexmask.long 0x0 0.--31. 1. "PS1SR,b'00=initial state" group.long 0x180++0x3 line.long 0x0 "IOINTSEL_B0P6T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x380++0x3 line.long 0x0 "IOINTSEL_B0P6T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x580++0x3 line.long 0x0 "IOINTSEL_B0P6T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x980++0x3 line.long 0x0 "IOINTSEL_B0P7T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0xB80++0x3 line.long 0x0 "IOINTSEL_B0P7T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0xD80++0x3 line.long 0x0 "IOINTSEL_B0P7T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x1180++0x3 line.long 0x0 "IOINTSEL_B0P8T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x1380++0x3 line.long 0x0 "IOINTSEL_B0P8T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x1580++0x3 line.long 0x0 "IOINTSEL_B0P8T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x1980++0x3 line.long 0x0 "IOINTSEL_B0P9T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x1B80++0x3 line.long 0x0 "IOINTSEL_B0P9T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x1D80++0x3 line.long 0x0 "IOINTSEL_B0P9T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2180++0x3 line.long 0x0 "IOINTSEL_B1P6T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2380++0x3 line.long 0x0 "IOINTSEL_B1P6T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2580++0x3 line.long 0x0 "IOINTSEL_B1P6T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2980++0x3 line.long 0x0 "IOINTSEL_B1P7T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2B80++0x3 line.long 0x0 "IOINTSEL_B1P7T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x2D80++0x3 line.long 0x0 "IOINTSEL_B1P7T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x3180++0x3 line.long 0x0 "IOINTSEL_B1P8T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x3380++0x3 line.long 0x0 "IOINTSEL_B1P8T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x3580++0x3 line.long 0x0 "IOINTSEL_B1P8T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x3980++0x3 line.long 0x0 "IOINTSEL_B1P9T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x3B80++0x3 line.long 0x0 "IOINTSEL_B1P9T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x3D80++0x3 line.long 0x0 "IOINTSEL_B1P9T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4180++0x3 line.long 0x0 "IOINTSEL_B2P6T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4380++0x3 line.long 0x0 "IOINTSEL_B2P6T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4580++0x3 line.long 0x0 "IOINTSEL_B2P6T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4980++0x3 line.long 0x0 "IOINTSEL_B2P7T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4B80++0x3 line.long 0x0 "IOINTSEL_B2P7T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x4D80++0x3 line.long 0x0 "IOINTSEL_B2P7T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x5180++0x3 line.long 0x0 "IOINTSEL_B2P8T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x5380++0x3 line.long 0x0 "IOINTSEL_B2P8T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x5580++0x3 line.long 0x0 "IOINTSEL_B2P8T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x5980++0x3 line.long 0x0 "IOINTSEL_B2P9T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x5B80++0x3 line.long 0x0 "IOINTSEL_B2P9T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x5D80++0x3 line.long 0x0 "IOINTSEL_B2P9T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6180++0x3 line.long 0x0 "IOINTSEL_B3P6T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6380++0x3 line.long 0x0 "IOINTSEL_B3P6T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6580++0x3 line.long 0x0 "IOINTSEL_B3P6T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6980++0x3 line.long 0x0 "IOINTSEL_B3P7T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6B80++0x3 line.long 0x0 "IOINTSEL_B3P7T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x6D80++0x3 line.long 0x0 "IOINTSEL_B3P7T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x7180++0x3 line.long 0x0 "IOINTSEL_B3P8T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x7380++0x3 line.long 0x0 "IOINTSEL_B3P8T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x7580++0x3 line.long 0x0 "IOINTSEL_B3P8T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x7980++0x3 line.long 0x0 "IOINTSEL_B3P9T0,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x7B80++0x3 line.long 0x0 "IOINTSEL_B3P9T1,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x7D80++0x3 line.long 0x0 "IOINTSEL_B3P9T2,IOINTSELn selects either general input/output mode or interrupt input mode for each of the port pins 0 to 31 of the GPIO group. When general input / output mode is selected for a port. it is also necessary to select either input or output.." hexmask.long 0x0 0.--31. 1. "IOINTSEL,Selects either general input/output mode or interrupt input mode for each port using the bits corresponding to the port numbers." group.long 0x184++0x3 line.long 0x0 "INOUTSEL_B0P6T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x384++0x3 line.long 0x0 "INOUTSEL_B0P6T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x584++0x3 line.long 0x0 "INOUTSEL_B0P6T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x984++0x3 line.long 0x0 "INOUTSEL_B0P7T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0xB84++0x3 line.long 0x0 "INOUTSEL_B0P7T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0xD84++0x3 line.long 0x0 "INOUTSEL_B0P7T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x1184++0x3 line.long 0x0 "INOUTSEL_B0P8T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x1384++0x3 line.long 0x0 "INOUTSEL_B0P8T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x1584++0x3 line.long 0x0 "INOUTSEL_B0P8T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x1984++0x3 line.long 0x0 "INOUTSEL_B0P9T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x1B84++0x3 line.long 0x0 "INOUTSEL_B0P9T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x1D84++0x3 line.long 0x0 "INOUTSEL_B0P9T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2184++0x3 line.long 0x0 "INOUTSEL_B1P6T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2384++0x3 line.long 0x0 "INOUTSEL_B1P6T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2584++0x3 line.long 0x0 "INOUTSEL_B1P6T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2984++0x3 line.long 0x0 "INOUTSEL_B1P7T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2B84++0x3 line.long 0x0 "INOUTSEL_B1P7T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x2D84++0x3 line.long 0x0 "INOUTSEL_B1P7T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x3184++0x3 line.long 0x0 "INOUTSEL_B1P8T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x3384++0x3 line.long 0x0 "INOUTSEL_B1P8T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x3584++0x3 line.long 0x0 "INOUTSEL_B1P8T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x3984++0x3 line.long 0x0 "INOUTSEL_B1P9T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x3B84++0x3 line.long 0x0 "INOUTSEL_B1P9T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x3D84++0x3 line.long 0x0 "INOUTSEL_B1P9T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4184++0x3 line.long 0x0 "INOUTSEL_B2P6T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4384++0x3 line.long 0x0 "INOUTSEL_B2P6T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4584++0x3 line.long 0x0 "INOUTSEL_B2P6T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4984++0x3 line.long 0x0 "INOUTSEL_B2P7T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4B84++0x3 line.long 0x0 "INOUTSEL_B2P7T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x4D84++0x3 line.long 0x0 "INOUTSEL_B2P7T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x5184++0x3 line.long 0x0 "INOUTSEL_B2P8T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x5384++0x3 line.long 0x0 "INOUTSEL_B2P8T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x5584++0x3 line.long 0x0 "INOUTSEL_B2P8T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x5984++0x3 line.long 0x0 "INOUTSEL_B2P9T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x5B84++0x3 line.long 0x0 "INOUTSEL_B2P9T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x5D84++0x3 line.long 0x0 "INOUTSEL_B2P9T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6184++0x3 line.long 0x0 "INOUTSEL_B3P6T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6384++0x3 line.long 0x0 "INOUTSEL_B3P6T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6584++0x3 line.long 0x0 "INOUTSEL_B3P6T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6984++0x3 line.long 0x0 "INOUTSEL_B3P7T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6B84++0x3 line.long 0x0 "INOUTSEL_B3P7T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x6D84++0x3 line.long 0x0 "INOUTSEL_B3P7T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x7184++0x3 line.long 0x0 "INOUTSEL_B3P8T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x7384++0x3 line.long 0x0 "INOUTSEL_B3P8T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x7584++0x3 line.long 0x0 "INOUTSEL_B3P8T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x7984++0x3 line.long 0x0 "INOUTSEL_B3P9T0,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x7B84++0x3 line.long 0x0 "INOUTSEL_B3P9T1,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x7D84++0x3 line.long 0x0 "INOUTSEL_B3P9T2,INOUTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register. Specifically. INOUTSEL selects either general input or general output mode for a port using the bit.." hexmask.long 0x0 0.--31. 1. "INOUTSEL,Selects either general input mode or general output mode for each port using the bits corresponding to the port numbers." group.long 0x188++0x3 line.long 0x0 "OUTDT_B0P6T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x388++0x3 line.long 0x0 "OUTDT_B0P6T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x588++0x3 line.long 0x0 "OUTDT_B0P6T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x988++0x3 line.long 0x0 "OUTDT_B0P7T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0xB88++0x3 line.long 0x0 "OUTDT_B0P7T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0xD88++0x3 line.long 0x0 "OUTDT_B0P7T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x1188++0x3 line.long 0x0 "OUTDT_B0P8T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x1388++0x3 line.long 0x0 "OUTDT_B0P8T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x1588++0x3 line.long 0x0 "OUTDT_B0P8T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x1988++0x3 line.long 0x0 "OUTDT_B0P9T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x1B88++0x3 line.long 0x0 "OUTDT_B0P9T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x1D88++0x3 line.long 0x0 "OUTDT_B0P9T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2188++0x3 line.long 0x0 "OUTDT_B1P6T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2388++0x3 line.long 0x0 "OUTDT_B1P6T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2588++0x3 line.long 0x0 "OUTDT_B1P6T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2988++0x3 line.long 0x0 "OUTDT_B1P7T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2B88++0x3 line.long 0x0 "OUTDT_B1P7T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x2D88++0x3 line.long 0x0 "OUTDT_B1P7T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x3188++0x3 line.long 0x0 "OUTDT_B1P8T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x3388++0x3 line.long 0x0 "OUTDT_B1P8T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x3588++0x3 line.long 0x0 "OUTDT_B1P8T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x3988++0x3 line.long 0x0 "OUTDT_B1P9T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x3B88++0x3 line.long 0x0 "OUTDT_B1P9T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x3D88++0x3 line.long 0x0 "OUTDT_B1P9T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4188++0x3 line.long 0x0 "OUTDT_B2P6T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4388++0x3 line.long 0x0 "OUTDT_B2P6T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4588++0x3 line.long 0x0 "OUTDT_B2P6T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4988++0x3 line.long 0x0 "OUTDT_B2P7T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4B88++0x3 line.long 0x0 "OUTDT_B2P7T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x4D88++0x3 line.long 0x0 "OUTDT_B2P7T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x5188++0x3 line.long 0x0 "OUTDT_B2P8T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x5388++0x3 line.long 0x0 "OUTDT_B2P8T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x5588++0x3 line.long 0x0 "OUTDT_B2P8T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x5988++0x3 line.long 0x0 "OUTDT_B2P9T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x5B88++0x3 line.long 0x0 "OUTDT_B2P9T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x5D88++0x3 line.long 0x0 "OUTDT_B2P9T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6188++0x3 line.long 0x0 "OUTDT_B3P6T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6388++0x3 line.long 0x0 "OUTDT_B3P6T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6588++0x3 line.long 0x0 "OUTDT_B3P6T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6988++0x3 line.long 0x0 "OUTDT_B3P7T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6B88++0x3 line.long 0x0 "OUTDT_B3P7T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x6D88++0x3 line.long 0x0 "OUTDT_B3P7T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x7188++0x3 line.long 0x0 "OUTDT_B3P8T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x7388++0x3 line.long 0x0 "OUTDT_B3P8T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x7588++0x3 line.long 0x0 "OUTDT_B3P8T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x7988++0x3 line.long 0x0 "OUTDT_B3P9T0,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x7B88++0x3 line.long 0x0 "OUTDT_B3P9T1,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." group.long 0x7D88++0x3 line.long 0x0 "OUTDT_B3P9T2,OUTDTn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. Specifically. the.." hexmask.long 0x0 0.--31. 1. "OUTDT,Allows the port to output the value set in the bit corresponding to the port number when the port is appropriately set by IOINTSEL INOUTSEL and OUTDTSEL." rgroup.long 0x18C++0x3 line.long 0x0 "INDT_B0P6T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x38C++0x3 line.long 0x0 "INDT_B0P6T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x58C++0x3 line.long 0x0 "INDT_B0P6T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x98C++0x3 line.long 0x0 "INDT_B0P7T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0xB8C++0x3 line.long 0x0 "INDT_B0P7T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0xD8C++0x3 line.long 0x0 "INDT_B0P7T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x118C++0x3 line.long 0x0 "INDT_B0P8T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x138C++0x3 line.long 0x0 "INDT_B0P8T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x158C++0x3 line.long 0x0 "INDT_B0P8T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x198C++0x3 line.long 0x0 "INDT_B0P9T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x1B8C++0x3 line.long 0x0 "INDT_B0P9T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x1D8C++0x3 line.long 0x0 "INDT_B0P9T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x218C++0x3 line.long 0x0 "INDT_B1P6T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x238C++0x3 line.long 0x0 "INDT_B1P6T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x258C++0x3 line.long 0x0 "INDT_B1P6T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x298C++0x3 line.long 0x0 "INDT_B1P7T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x2B8C++0x3 line.long 0x0 "INDT_B1P7T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x2D8C++0x3 line.long 0x0 "INDT_B1P7T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x318C++0x3 line.long 0x0 "INDT_B1P8T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x338C++0x3 line.long 0x0 "INDT_B1P8T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x358C++0x3 line.long 0x0 "INDT_B1P8T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x398C++0x3 line.long 0x0 "INDT_B1P9T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x3B8C++0x3 line.long 0x0 "INDT_B1P9T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x3D8C++0x3 line.long 0x0 "INDT_B1P9T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x418C++0x3 line.long 0x0 "INDT_B2P6T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x438C++0x3 line.long 0x0 "INDT_B2P6T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x458C++0x3 line.long 0x0 "INDT_B2P6T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x498C++0x3 line.long 0x0 "INDT_B2P7T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x4B8C++0x3 line.long 0x0 "INDT_B2P7T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x4D8C++0x3 line.long 0x0 "INDT_B2P7T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x518C++0x3 line.long 0x0 "INDT_B2P8T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x538C++0x3 line.long 0x0 "INDT_B2P8T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x558C++0x3 line.long 0x0 "INDT_B2P8T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x598C++0x3 line.long 0x0 "INDT_B2P9T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x5B8C++0x3 line.long 0x0 "INDT_B2P9T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x5D8C++0x3 line.long 0x0 "INDT_B2P9T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x618C++0x3 line.long 0x0 "INDT_B3P6T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x638C++0x3 line.long 0x0 "INDT_B3P6T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x658C++0x3 line.long 0x0 "INDT_B3P6T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x698C++0x3 line.long 0x0 "INDT_B3P7T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x6B8C++0x3 line.long 0x0 "INDT_B3P7T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x6D8C++0x3 line.long 0x0 "INDT_B3P7T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x718C++0x3 line.long 0x0 "INDT_B3P8T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x738C++0x3 line.long 0x0 "INDT_B3P8T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x758C++0x3 line.long 0x0 "INDT_B3P8T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x798C++0x3 line.long 0x0 "INDT_B3P9T0,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x7B8C++0x3 line.long 0x0 "INDT_B3P9T1,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x7D8C++0x3 line.long 0x0 "INDT_B3P9T2,INDTn is a register that can read the status of General-Purpose Input / Output Ports." hexmask.long 0x0 0.--31. 1. "INDT,Each bit reflects the value received through the corresponding port pin." rgroup.long 0x190++0x3 line.long 0x0 "INTDT_B0P6T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x390++0x3 line.long 0x0 "INTDT_B0P6T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x590++0x3 line.long 0x0 "INTDT_B0P6T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x990++0x3 line.long 0x0 "INTDT_B0P7T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0xB90++0x3 line.long 0x0 "INTDT_B0P7T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0xD90++0x3 line.long 0x0 "INTDT_B0P7T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x1190++0x3 line.long 0x0 "INTDT_B0P8T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x1390++0x3 line.long 0x0 "INTDT_B0P8T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x1590++0x3 line.long 0x0 "INTDT_B0P8T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x1990++0x3 line.long 0x0 "INTDT_B0P9T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x1B90++0x3 line.long 0x0 "INTDT_B0P9T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x1D90++0x3 line.long 0x0 "INTDT_B0P9T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2190++0x3 line.long 0x0 "INTDT_B1P6T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2390++0x3 line.long 0x0 "INTDT_B1P6T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2590++0x3 line.long 0x0 "INTDT_B1P6T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2990++0x3 line.long 0x0 "INTDT_B1P7T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2B90++0x3 line.long 0x0 "INTDT_B1P7T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x2D90++0x3 line.long 0x0 "INTDT_B1P7T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x3190++0x3 line.long 0x0 "INTDT_B1P8T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x3390++0x3 line.long 0x0 "INTDT_B1P8T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x3590++0x3 line.long 0x0 "INTDT_B1P8T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x3990++0x3 line.long 0x0 "INTDT_B1P9T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x3B90++0x3 line.long 0x0 "INTDT_B1P9T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x3D90++0x3 line.long 0x0 "INTDT_B1P9T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4190++0x3 line.long 0x0 "INTDT_B2P6T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4390++0x3 line.long 0x0 "INTDT_B2P6T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4590++0x3 line.long 0x0 "INTDT_B2P6T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4990++0x3 line.long 0x0 "INTDT_B2P7T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4B90++0x3 line.long 0x0 "INTDT_B2P7T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x4D90++0x3 line.long 0x0 "INTDT_B2P7T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x5190++0x3 line.long 0x0 "INTDT_B2P8T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x5390++0x3 line.long 0x0 "INTDT_B2P8T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x5590++0x3 line.long 0x0 "INTDT_B2P8T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x5990++0x3 line.long 0x0 "INTDT_B2P9T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x5B90++0x3 line.long 0x0 "INTDT_B2P9T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x5D90++0x3 line.long 0x0 "INTDT_B2P9T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6190++0x3 line.long 0x0 "INTDT_B3P6T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6390++0x3 line.long 0x0 "INTDT_B3P6T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6590++0x3 line.long 0x0 "INTDT_B3P6T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6990++0x3 line.long 0x0 "INTDT_B3P7T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6B90++0x3 line.long 0x0 "INTDT_B3P7T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x6D90++0x3 line.long 0x0 "INTDT_B3P7T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x7190++0x3 line.long 0x0 "INTDT_B3P8T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x7390++0x3 line.long 0x0 "INTDT_B3P8T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x7590++0x3 line.long 0x0 "INTDT_B3P8T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x7990++0x3 line.long 0x0 "INTDT_B3P9T0,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x7B90++0x3 line.long 0x0 "INTDT_B3P9T1,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." rgroup.long 0x7D90++0x3 line.long 0x0 "INTDT_B3P9T2,INTDTn is valid only when interrupt input mode is selected by the general IO/interrupt switching register. Specifically. when an interrupt is input via a port pin when INTDTn is valid. the bit in INTDTn corresponding to the port indicates.." hexmask.long 0x0 0.--31. 1. "INTDT,Each bit indicates the input of an interrupt signal on the corresponding port pin." group.long 0x194++0x3 line.long 0x0 "INTCLR_B0P6T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x394++0x3 line.long 0x0 "INTCLR_B0P6T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x594++0x3 line.long 0x0 "INTCLR_B0P6T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x994++0x3 line.long 0x0 "INTCLR_B0P7T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0xB94++0x3 line.long 0x0 "INTCLR_B0P7T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0xD94++0x3 line.long 0x0 "INTCLR_B0P7T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x1194++0x3 line.long 0x0 "INTCLR_B0P8T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x1394++0x3 line.long 0x0 "INTCLR_B0P8T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x1594++0x3 line.long 0x0 "INTCLR_B0P8T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x1994++0x3 line.long 0x0 "INTCLR_B0P9T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x1B94++0x3 line.long 0x0 "INTCLR_B0P9T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x1D94++0x3 line.long 0x0 "INTCLR_B0P9T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2194++0x3 line.long 0x0 "INTCLR_B1P6T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2394++0x3 line.long 0x0 "INTCLR_B1P6T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2594++0x3 line.long 0x0 "INTCLR_B1P6T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2994++0x3 line.long 0x0 "INTCLR_B1P7T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2B94++0x3 line.long 0x0 "INTCLR_B1P7T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x2D94++0x3 line.long 0x0 "INTCLR_B1P7T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x3194++0x3 line.long 0x0 "INTCLR_B1P8T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x3394++0x3 line.long 0x0 "INTCLR_B1P8T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x3594++0x3 line.long 0x0 "INTCLR_B1P8T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x3994++0x3 line.long 0x0 "INTCLR_B1P9T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x3B94++0x3 line.long 0x0 "INTCLR_B1P9T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x3D94++0x3 line.long 0x0 "INTCLR_B1P9T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4194++0x3 line.long 0x0 "INTCLR_B2P6T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4394++0x3 line.long 0x0 "INTCLR_B2P6T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4594++0x3 line.long 0x0 "INTCLR_B2P6T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4994++0x3 line.long 0x0 "INTCLR_B2P7T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4B94++0x3 line.long 0x0 "INTCLR_B2P7T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x4D94++0x3 line.long 0x0 "INTCLR_B2P7T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x5194++0x3 line.long 0x0 "INTCLR_B2P8T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x5394++0x3 line.long 0x0 "INTCLR_B2P8T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x5594++0x3 line.long 0x0 "INTCLR_B2P8T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x5994++0x3 line.long 0x0 "INTCLR_B2P9T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x5B94++0x3 line.long 0x0 "INTCLR_B2P9T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x5D94++0x3 line.long 0x0 "INTCLR_B2P9T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6194++0x3 line.long 0x0 "INTCLR_B3P6T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6394++0x3 line.long 0x0 "INTCLR_B3P6T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6594++0x3 line.long 0x0 "INTCLR_B3P6T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6994++0x3 line.long 0x0 "INTCLR_B3P7T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6B94++0x3 line.long 0x0 "INTCLR_B3P7T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x6D94++0x3 line.long 0x0 "INTCLR_B3P7T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x7194++0x3 line.long 0x0 "INTCLR_B3P8T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x7394++0x3 line.long 0x0 "INTCLR_B3P8T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x7594++0x3 line.long 0x0 "INTCLR_B3P8T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x7994++0x3 line.long 0x0 "INTCLR_B3P9T0,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x7B94++0x3 line.long 0x0 "INTCLR_B3P9T1,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x7D94++0x3 line.long 0x0 "INTCLR_B3P9T2,When the interrupt display register is currently indicates the reception of the interrupt input on the port for which the edge detection is selected by the edge/level select register (with configuring for one edge/both edge select register).." hexmask.long 0x0 0.--31. 1. "INTCLR,Writing 1 to bits corresponding to port numbers clears the corresponding bits in the interrupt display register." group.long 0x198++0x3 line.long 0x0 "INTMSK_B0P6T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x398++0x3 line.long 0x0 "INTMSK_B0P6T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x598++0x3 line.long 0x0 "INTMSK_B0P6T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x998++0x3 line.long 0x0 "INTMSK_B0P7T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0xB98++0x3 line.long 0x0 "INTMSK_B0P7T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0xD98++0x3 line.long 0x0 "INTMSK_B0P7T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x1198++0x3 line.long 0x0 "INTMSK_B0P8T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x1398++0x3 line.long 0x0 "INTMSK_B0P8T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x1598++0x3 line.long 0x0 "INTMSK_B0P8T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x1998++0x3 line.long 0x0 "INTMSK_B0P9T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x1B98++0x3 line.long 0x0 "INTMSK_B0P9T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x1D98++0x3 line.long 0x0 "INTMSK_B0P9T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2198++0x3 line.long 0x0 "INTMSK_B1P6T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2398++0x3 line.long 0x0 "INTMSK_B1P6T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2598++0x3 line.long 0x0 "INTMSK_B1P6T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2998++0x3 line.long 0x0 "INTMSK_B1P7T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2B98++0x3 line.long 0x0 "INTMSK_B1P7T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x2D98++0x3 line.long 0x0 "INTMSK_B1P7T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x3198++0x3 line.long 0x0 "INTMSK_B1P8T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x3398++0x3 line.long 0x0 "INTMSK_B1P8T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x3598++0x3 line.long 0x0 "INTMSK_B1P8T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x3998++0x3 line.long 0x0 "INTMSK_B1P9T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x3B98++0x3 line.long 0x0 "INTMSK_B1P9T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x3D98++0x3 line.long 0x0 "INTMSK_B1P9T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4198++0x3 line.long 0x0 "INTMSK_B2P6T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4398++0x3 line.long 0x0 "INTMSK_B2P6T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4598++0x3 line.long 0x0 "INTMSK_B2P6T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4998++0x3 line.long 0x0 "INTMSK_B2P7T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4B98++0x3 line.long 0x0 "INTMSK_B2P7T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x4D98++0x3 line.long 0x0 "INTMSK_B2P7T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x5198++0x3 line.long 0x0 "INTMSK_B2P8T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x5398++0x3 line.long 0x0 "INTMSK_B2P8T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x5598++0x3 line.long 0x0 "INTMSK_B2P8T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x5998++0x3 line.long 0x0 "INTMSK_B2P9T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x5B98++0x3 line.long 0x0 "INTMSK_B2P9T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x5D98++0x3 line.long 0x0 "INTMSK_B2P9T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6198++0x3 line.long 0x0 "INTMSK_B3P6T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6398++0x3 line.long 0x0 "INTMSK_B3P6T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6598++0x3 line.long 0x0 "INTMSK_B3P6T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6998++0x3 line.long 0x0 "INTMSK_B3P7T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6B98++0x3 line.long 0x0 "INTMSK_B3P7T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x6D98++0x3 line.long 0x0 "INTMSK_B3P7T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x7198++0x3 line.long 0x0 "INTMSK_B3P8T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x7398++0x3 line.long 0x0 "INTMSK_B3P8T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x7598++0x3 line.long 0x0 "INTMSK_B3P8T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x7998++0x3 line.long 0x0 "INTMSK_B3P9T0,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x7B98++0x3 line.long 0x0 "INTMSK_B3P9T1,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x7D98++0x3 line.long 0x0 "INTMSK_B3P9T2,INTMSKn masks the interrupt requests indicated by the interrupt display register of GPIO.ch. Interrupts can be separately masked using the corresponding bits in INTMSKn. When all the bits currently indicating the reception of the interrupt.." hexmask.long 0x0 0.--31. 1. "INTMSK,Setting a mask to the bit disables the corresponding interrupt signal to be output to the interrupt control block." group.long 0x19C++0x3 line.long 0x0 "MSKCLR_B0P6T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x39C++0x3 line.long 0x0 "MSKCLR_B0P6T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x59C++0x3 line.long 0x0 "MSKCLR_B0P6T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x99C++0x3 line.long 0x0 "MSKCLR_B0P7T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0xB9C++0x3 line.long 0x0 "MSKCLR_B0P7T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0xD9C++0x3 line.long 0x0 "MSKCLR_B0P7T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x119C++0x3 line.long 0x0 "MSKCLR_B0P8T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x139C++0x3 line.long 0x0 "MSKCLR_B0P8T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x159C++0x3 line.long 0x0 "MSKCLR_B0P8T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x199C++0x3 line.long 0x0 "MSKCLR_B0P9T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x1B9C++0x3 line.long 0x0 "MSKCLR_B0P9T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x1D9C++0x3 line.long 0x0 "MSKCLR_B0P9T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x219C++0x3 line.long 0x0 "MSKCLR_B1P6T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x239C++0x3 line.long 0x0 "MSKCLR_B1P6T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x259C++0x3 line.long 0x0 "MSKCLR_B1P6T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x299C++0x3 line.long 0x0 "MSKCLR_B1P7T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x2B9C++0x3 line.long 0x0 "MSKCLR_B1P7T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x2D9C++0x3 line.long 0x0 "MSKCLR_B1P7T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x319C++0x3 line.long 0x0 "MSKCLR_B1P8T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x339C++0x3 line.long 0x0 "MSKCLR_B1P8T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x359C++0x3 line.long 0x0 "MSKCLR_B1P8T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x399C++0x3 line.long 0x0 "MSKCLR_B1P9T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x3B9C++0x3 line.long 0x0 "MSKCLR_B1P9T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x3D9C++0x3 line.long 0x0 "MSKCLR_B1P9T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x419C++0x3 line.long 0x0 "MSKCLR_B2P6T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x439C++0x3 line.long 0x0 "MSKCLR_B2P6T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x459C++0x3 line.long 0x0 "MSKCLR_B2P6T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x499C++0x3 line.long 0x0 "MSKCLR_B2P7T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x4B9C++0x3 line.long 0x0 "MSKCLR_B2P7T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x4D9C++0x3 line.long 0x0 "MSKCLR_B2P7T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x519C++0x3 line.long 0x0 "MSKCLR_B2P8T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x539C++0x3 line.long 0x0 "MSKCLR_B2P8T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x559C++0x3 line.long 0x0 "MSKCLR_B2P8T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x599C++0x3 line.long 0x0 "MSKCLR_B2P9T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x5B9C++0x3 line.long 0x0 "MSKCLR_B2P9T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x5D9C++0x3 line.long 0x0 "MSKCLR_B2P9T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x619C++0x3 line.long 0x0 "MSKCLR_B3P6T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x639C++0x3 line.long 0x0 "MSKCLR_B3P6T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x659C++0x3 line.long 0x0 "MSKCLR_B3P6T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x699C++0x3 line.long 0x0 "MSKCLR_B3P7T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x6B9C++0x3 line.long 0x0 "MSKCLR_B3P7T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x6D9C++0x3 line.long 0x0 "MSKCLR_B3P7T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x719C++0x3 line.long 0x0 "MSKCLR_B3P8T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x739C++0x3 line.long 0x0 "MSKCLR_B3P8T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x759C++0x3 line.long 0x0 "MSKCLR_B3P8T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x799C++0x3 line.long 0x0 "MSKCLR_B3P9T0,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x7B9C++0x3 line.long 0x0 "MSKCLR_B3P9T1,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x7D9C++0x3 line.long 0x0 "MSKCLR_B3P9T2,MSKCLRn cancels masks that are set by the interrupt mask register of GPIO.ch*A. Each mask can be canceled (cleared) by writing 1 to the corresponding bit in MSKCLRn. Only writing 1 to MSKCLRn is effective; MSKCLRn is always read as 0." hexmask.long 0x0 0.--31. 1. "MSKCLR,Setting a mask to the bit disables the corresponding alternative interrupt signal to be output to the interrupt control block." group.long 0x1A0++0x3 line.long 0x0 "POSNEG_B0P6T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x3A0++0x3 line.long 0x0 "POSNEG_B0P6T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x5A0++0x3 line.long 0x0 "POSNEG_B0P6T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x9A0++0x3 line.long 0x0 "POSNEG_B0P7T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0xBA0++0x3 line.long 0x0 "POSNEG_B0P7T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0xDA0++0x3 line.long 0x0 "POSNEG_B0P7T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x11A0++0x3 line.long 0x0 "POSNEG_B0P8T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x13A0++0x3 line.long 0x0 "POSNEG_B0P8T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x15A0++0x3 line.long 0x0 "POSNEG_B0P8T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x19A0++0x3 line.long 0x0 "POSNEG_B0P9T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x1BA0++0x3 line.long 0x0 "POSNEG_B0P9T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x1DA0++0x3 line.long 0x0 "POSNEG_B0P9T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x21A0++0x3 line.long 0x0 "POSNEG_B1P6T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x23A0++0x3 line.long 0x0 "POSNEG_B1P6T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x25A0++0x3 line.long 0x0 "POSNEG_B1P6T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x29A0++0x3 line.long 0x0 "POSNEG_B1P7T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x2BA0++0x3 line.long 0x0 "POSNEG_B1P7T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x2DA0++0x3 line.long 0x0 "POSNEG_B1P7T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x31A0++0x3 line.long 0x0 "POSNEG_B1P8T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x33A0++0x3 line.long 0x0 "POSNEG_B1P8T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x35A0++0x3 line.long 0x0 "POSNEG_B1P8T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x39A0++0x3 line.long 0x0 "POSNEG_B1P9T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x3BA0++0x3 line.long 0x0 "POSNEG_B1P9T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x3DA0++0x3 line.long 0x0 "POSNEG_B1P9T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x41A0++0x3 line.long 0x0 "POSNEG_B2P6T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x43A0++0x3 line.long 0x0 "POSNEG_B2P6T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x45A0++0x3 line.long 0x0 "POSNEG_B2P6T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x49A0++0x3 line.long 0x0 "POSNEG_B2P7T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x4BA0++0x3 line.long 0x0 "POSNEG_B2P7T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x4DA0++0x3 line.long 0x0 "POSNEG_B2P7T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x51A0++0x3 line.long 0x0 "POSNEG_B2P8T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x53A0++0x3 line.long 0x0 "POSNEG_B2P8T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x55A0++0x3 line.long 0x0 "POSNEG_B2P8T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x59A0++0x3 line.long 0x0 "POSNEG_B2P9T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x5BA0++0x3 line.long 0x0 "POSNEG_B2P9T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x5DA0++0x3 line.long 0x0 "POSNEG_B2P9T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x61A0++0x3 line.long 0x0 "POSNEG_B3P6T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x63A0++0x3 line.long 0x0 "POSNEG_B3P6T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x65A0++0x3 line.long 0x0 "POSNEG_B3P6T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x69A0++0x3 line.long 0x0 "POSNEG_B3P7T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x6BA0++0x3 line.long 0x0 "POSNEG_B3P7T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x6DA0++0x3 line.long 0x0 "POSNEG_B3P7T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x71A0++0x3 line.long 0x0 "POSNEG_B3P8T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x73A0++0x3 line.long 0x0 "POSNEG_B3P8T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x75A0++0x3 line.long 0x0 "POSNEG_B3P8T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x79A0++0x3 line.long 0x0 "POSNEG_B3P9T0,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x7BA0++0x3 line.long 0x0 "POSNEG_B3P9T1,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x7DA0++0x3 line.long 0x0 "POSNEG_B3P9T2,POSNEGn selects the polarity (positive or negative logic) of each port pin in general input mode. general output mode. or interrupt input mode. POSNEGn should be set before mode selection." hexmask.long 0x0 0.--31. 1. "POSNEG,Selects the polarity (positive or negative logic) of each port pin." group.long 0x1A4++0x3 line.long 0x0 "EDGLEVEL_B0P6T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x3A4++0x3 line.long 0x0 "EDGLEVEL_B0P6T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x5A4++0x3 line.long 0x0 "EDGLEVEL_B0P6T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x9A4++0x3 line.long 0x0 "EDGLEVEL_B0P7T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0xBA4++0x3 line.long 0x0 "EDGLEVEL_B0P7T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0xDA4++0x3 line.long 0x0 "EDGLEVEL_B0P7T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x11A4++0x3 line.long 0x0 "EDGLEVEL_B0P8T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x13A4++0x3 line.long 0x0 "EDGLEVEL_B0P8T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x15A4++0x3 line.long 0x0 "EDGLEVEL_B0P8T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x19A4++0x3 line.long 0x0 "EDGLEVEL_B0P9T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x1BA4++0x3 line.long 0x0 "EDGLEVEL_B0P9T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x1DA4++0x3 line.long 0x0 "EDGLEVEL_B0P9T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x21A4++0x3 line.long 0x0 "EDGLEVEL_B1P6T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x23A4++0x3 line.long 0x0 "EDGLEVEL_B1P6T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x25A4++0x3 line.long 0x0 "EDGLEVEL_B1P6T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x29A4++0x3 line.long 0x0 "EDGLEVEL_B1P7T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x2BA4++0x3 line.long 0x0 "EDGLEVEL_B1P7T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x2DA4++0x3 line.long 0x0 "EDGLEVEL_B1P7T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x31A4++0x3 line.long 0x0 "EDGLEVEL_B1P8T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x33A4++0x3 line.long 0x0 "EDGLEVEL_B1P8T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x35A4++0x3 line.long 0x0 "EDGLEVEL_B1P8T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x39A4++0x3 line.long 0x0 "EDGLEVEL_B1P9T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x3BA4++0x3 line.long 0x0 "EDGLEVEL_B1P9T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x3DA4++0x3 line.long 0x0 "EDGLEVEL_B1P9T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x41A4++0x3 line.long 0x0 "EDGLEVEL_B2P6T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x43A4++0x3 line.long 0x0 "EDGLEVEL_B2P6T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x45A4++0x3 line.long 0x0 "EDGLEVEL_B2P6T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x49A4++0x3 line.long 0x0 "EDGLEVEL_B2P7T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x4BA4++0x3 line.long 0x0 "EDGLEVEL_B2P7T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x4DA4++0x3 line.long 0x0 "EDGLEVEL_B2P7T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x51A4++0x3 line.long 0x0 "EDGLEVEL_B2P8T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x53A4++0x3 line.long 0x0 "EDGLEVEL_B2P8T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x55A4++0x3 line.long 0x0 "EDGLEVEL_B2P8T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x59A4++0x3 line.long 0x0 "EDGLEVEL_B2P9T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x5BA4++0x3 line.long 0x0 "EDGLEVEL_B2P9T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x5DA4++0x3 line.long 0x0 "EDGLEVEL_B2P9T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x61A4++0x3 line.long 0x0 "EDGLEVEL_B3P6T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x63A4++0x3 line.long 0x0 "EDGLEVEL_B3P6T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x65A4++0x3 line.long 0x0 "EDGLEVEL_B3P6T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x69A4++0x3 line.long 0x0 "EDGLEVEL_B3P7T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x6BA4++0x3 line.long 0x0 "EDGLEVEL_B3P7T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x6DA4++0x3 line.long 0x0 "EDGLEVEL_B3P7T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x71A4++0x3 line.long 0x0 "EDGLEVEL_B3P8T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x73A4++0x3 line.long 0x0 "EDGLEVEL_B3P8T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x75A4++0x3 line.long 0x0 "EDGLEVEL_B3P8T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x79A4++0x3 line.long 0x0 "EDGLEVEL_B3P9T0,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x7BA4++0x3 line.long 0x0 "EDGLEVEL_B3P9T1,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x7DA4++0x3 line.long 0x0 "EDGLEVEL_B3P9T2,EDGLEVELn is valid only for the ports for which interrupt input mode is selected by the general IO/interrupt switching register. Specifically. EDGLEVELn selects the detection conditions (edge or level) of the interrupt input signal on.." hexmask.long 0x0 0.--31. 1. "EDGLEVEL,Selects the level or edge as detection conditions of the interrupt input signal on each port pin for which interrupt input mode is selected." group.long 0x1A8++0x3 line.long 0x0 "FILONOFF_B0P6T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x3A8++0x3 line.long 0x0 "FILONOFF_B0P6T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x5A8++0x3 line.long 0x0 "FILONOFF_B0P6T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x9A8++0x3 line.long 0x0 "FILONOFF_B0P7T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0xBA8++0x3 line.long 0x0 "FILONOFF_B0P7T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0xDA8++0x3 line.long 0x0 "FILONOFF_B0P7T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x11A8++0x3 line.long 0x0 "FILONOFF_B0P8T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x13A8++0x3 line.long 0x0 "FILONOFF_B0P8T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x15A8++0x3 line.long 0x0 "FILONOFF_B0P8T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x19A8++0x3 line.long 0x0 "FILONOFF_B0P9T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x1BA8++0x3 line.long 0x0 "FILONOFF_B0P9T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x1DA8++0x3 line.long 0x0 "FILONOFF_B0P9T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x21A8++0x3 line.long 0x0 "FILONOFF_B1P6T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x23A8++0x3 line.long 0x0 "FILONOFF_B1P6T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x25A8++0x3 line.long 0x0 "FILONOFF_B1P6T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x29A8++0x3 line.long 0x0 "FILONOFF_B1P7T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x2BA8++0x3 line.long 0x0 "FILONOFF_B1P7T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x2DA8++0x3 line.long 0x0 "FILONOFF_B1P7T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x31A8++0x3 line.long 0x0 "FILONOFF_B1P8T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x33A8++0x3 line.long 0x0 "FILONOFF_B1P8T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x35A8++0x3 line.long 0x0 "FILONOFF_B1P8T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x39A8++0x3 line.long 0x0 "FILONOFF_B1P9T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x3BA8++0x3 line.long 0x0 "FILONOFF_B1P9T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x3DA8++0x3 line.long 0x0 "FILONOFF_B1P9T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x41A8++0x3 line.long 0x0 "FILONOFF_B2P6T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x43A8++0x3 line.long 0x0 "FILONOFF_B2P6T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x45A8++0x3 line.long 0x0 "FILONOFF_B2P6T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x49A8++0x3 line.long 0x0 "FILONOFF_B2P7T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x4BA8++0x3 line.long 0x0 "FILONOFF_B2P7T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x4DA8++0x3 line.long 0x0 "FILONOFF_B2P7T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x51A8++0x3 line.long 0x0 "FILONOFF_B2P8T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x53A8++0x3 line.long 0x0 "FILONOFF_B2P8T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x55A8++0x3 line.long 0x0 "FILONOFF_B2P8T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x59A8++0x3 line.long 0x0 "FILONOFF_B2P9T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x5BA8++0x3 line.long 0x0 "FILONOFF_B2P9T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x5DA8++0x3 line.long 0x0 "FILONOFF_B2P9T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x61A8++0x3 line.long 0x0 "FILONOFF_B3P6T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x63A8++0x3 line.long 0x0 "FILONOFF_B3P6T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x65A8++0x3 line.long 0x0 "FILONOFF_B3P6T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x69A8++0x3 line.long 0x0 "FILONOFF_B3P7T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x6BA8++0x3 line.long 0x0 "FILONOFF_B3P7T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x6DA8++0x3 line.long 0x0 "FILONOFF_B3P7T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x71A8++0x3 line.long 0x0 "FILONOFF_B3P8T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x73A8++0x3 line.long 0x0 "FILONOFF_B3P8T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x75A8++0x3 line.long 0x0 "FILONOFF_B3P8T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x79A8++0x3 line.long 0x0 "FILONOFF_B3P9T0,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x7BA8++0x3 line.long 0x0 "FILONOFF_B3P9T1,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x7DA8++0x3 line.long 0x0 "FILONOFF_B3P9T2,FILONOFFn prevents chattering input to the port pins of each GPIO group. For details. refer to section 6.3.5. Handling of Input Signals on Port Pins." hexmask.long 0x0 0.--31. 1. "FILONOFF,Enables or disables the chattering prevention function." group.long 0x1AC++0x3 line.long 0x0 "FILCLKSEL_B0P6T0,Chattering Prevention Clock Select Register B0P6T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x3AC++0x3 line.long 0x0 "FILCLKSEL_B0P6T1,Chattering Prevention Clock Select Register B0P6T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x5AC++0x3 line.long 0x0 "FILCLKSEL_B0P6T2,Chattering Prevention Clock Select Register B0P6T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x9AC++0x3 line.long 0x0 "FILCLKSEL_B0P7T0,Chattering Prevention Clock Select Register B0P7T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0xBAC++0x3 line.long 0x0 "FILCLKSEL_B0P7T1,Chattering Prevention Clock Select Register B0P7T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0xDAC++0x3 line.long 0x0 "FILCLKSEL_B0P7T2,Chattering Prevention Clock Select Register B0P7T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x11AC++0x3 line.long 0x0 "FILCLKSEL_B0P8T0,Chattering Prevention Clock Select Register B0P8T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x13AC++0x3 line.long 0x0 "FILCLKSEL_B0P8T1,Chattering Prevention Clock Select Register B0P8T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x15AC++0x3 line.long 0x0 "FILCLKSEL_B0P8T2,Chattering Prevention Clock Select Register B0P8T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x19AC++0x3 line.long 0x0 "FILCLKSEL_B0P9T0,Chattering Prevention Clock Select Register B0P9T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x1BAC++0x3 line.long 0x0 "FILCLKSEL_B0P9T1,Chattering Prevention Clock Select Register B0P9T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x1DAC++0x3 line.long 0x0 "FILCLKSEL_B0P9T2,Chattering Prevention Clock Select Register B0P9T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x21AC++0x3 line.long 0x0 "FILCLKSEL_B1P6T0,Chattering Prevention Clock Select Register B1P6T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x23AC++0x3 line.long 0x0 "FILCLKSEL_B1P6T1,Chattering Prevention Clock Select Register B1P6T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x25AC++0x3 line.long 0x0 "FILCLKSEL_B1P6T2,Chattering Prevention Clock Select Register B1P6T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x29AC++0x3 line.long 0x0 "FILCLKSEL_B1P7T0,Chattering Prevention Clock Select Register B1P7T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x2BAC++0x3 line.long 0x0 "FILCLKSEL_B1P7T1,Chattering Prevention Clock Select Register B1P7T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x2DAC++0x3 line.long 0x0 "FILCLKSEL_B1P7T2,Chattering Prevention Clock Select Register B1P7T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x31AC++0x3 line.long 0x0 "FILCLKSEL_B1P8T0,Chattering Prevention Clock Select Register B1P8T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x33AC++0x3 line.long 0x0 "FILCLKSEL_B1P8T1,Chattering Prevention Clock Select Register B1P8T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x35AC++0x3 line.long 0x0 "FILCLKSEL_B1P8T2,Chattering Prevention Clock Select Register B1P8T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x39AC++0x3 line.long 0x0 "FILCLKSEL_B1P9T0,Chattering Prevention Clock Select Register B1P9T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x3BAC++0x3 line.long 0x0 "FILCLKSEL_B1P9T1,Chattering Prevention Clock Select Register B1P9T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x3DAC++0x3 line.long 0x0 "FILCLKSEL_B1P9T2,Chattering Prevention Clock Select Register B1P9T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x41AC++0x3 line.long 0x0 "FILCLKSEL_B2P6T0,Chattering Prevention Clock Select Register B2P6T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x43AC++0x3 line.long 0x0 "FILCLKSEL_B2P6T1,Chattering Prevention Clock Select Register B2P6T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x45AC++0x3 line.long 0x0 "FILCLKSEL_B2P6T2,Chattering Prevention Clock Select Register B2P6T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x49AC++0x3 line.long 0x0 "FILCLKSEL_B2P7T0,Chattering Prevention Clock Select Register B2P7T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x4BAC++0x3 line.long 0x0 "FILCLKSEL_B2P7T1,Chattering Prevention Clock Select Register B2P7T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x4DAC++0x3 line.long 0x0 "FILCLKSEL_B2P7T2,Chattering Prevention Clock Select Register B2P7T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x51AC++0x3 line.long 0x0 "FILCLKSEL_B2P8T0,Chattering Prevention Clock Select Register B2P8T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x53AC++0x3 line.long 0x0 "FILCLKSEL_B2P8T1,Chattering Prevention Clock Select Register B2P8T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x55AC++0x3 line.long 0x0 "FILCLKSEL_B2P8T2,Chattering Prevention Clock Select Register B2P8T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x59AC++0x3 line.long 0x0 "FILCLKSEL_B2P9T0,Chattering Prevention Clock Select Register B2P9T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x5BAC++0x3 line.long 0x0 "FILCLKSEL_B2P9T1,Chattering Prevention Clock Select Register B2P9T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x5DAC++0x3 line.long 0x0 "FILCLKSEL_B2P9T2,Chattering Prevention Clock Select Register B2P9T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x61AC++0x3 line.long 0x0 "FILCLKSEL_B3P6T0,Chattering Prevention Clock Select Register B3P6T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x63AC++0x3 line.long 0x0 "FILCLKSEL_B3P6T1,Chattering Prevention Clock Select Register B3P6T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x65AC++0x3 line.long 0x0 "FILCLKSEL_B3P6T2,Chattering Prevention Clock Select Register B3P6T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x69AC++0x3 line.long 0x0 "FILCLKSEL_B3P7T0,Chattering Prevention Clock Select Register B3P7T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x6BAC++0x3 line.long 0x0 "FILCLKSEL_B3P7T1,Chattering Prevention Clock Select Register B3P7T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x6DAC++0x3 line.long 0x0 "FILCLKSEL_B3P7T2,Chattering Prevention Clock Select Register B3P7T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x71AC++0x3 line.long 0x0 "FILCLKSEL_B3P8T0,Chattering Prevention Clock Select Register B3P8T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x73AC++0x3 line.long 0x0 "FILCLKSEL_B3P8T1,Chattering Prevention Clock Select Register B3P8T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x75AC++0x3 line.long 0x0 "FILCLKSEL_B3P8T2,Chattering Prevention Clock Select Register B3P8T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x79AC++0x3 line.long 0x0 "FILCLKSEL_B3P9T0,Chattering Prevention Clock Select Register B3P9T0" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x7BAC++0x3 line.long 0x0 "FILCLKSEL_B3P9T1,Chattering Prevention Clock Select Register B3P9T1" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x7DAC++0x3 line.long 0x0 "FILCLKSEL_B3P9T2,Chattering Prevention Clock Select Register B3P9T2" hexmask.long.word 0x0 0.--15. 1. "FILCLKSEL,Set the division ratio of filter CLOCK." group.long 0x1C0++0x3 line.long 0x0 "OUTDTSEL_B0P6T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x3C0++0x3 line.long 0x0 "OUTDTSEL_B0P6T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x5C0++0x3 line.long 0x0 "OUTDTSEL_B0P6T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x9C0++0x3 line.long 0x0 "OUTDTSEL_B0P7T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0xBC0++0x3 line.long 0x0 "OUTDTSEL_B0P7T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0xDC0++0x3 line.long 0x0 "OUTDTSEL_B0P7T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x11C0++0x3 line.long 0x0 "OUTDTSEL_B0P8T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x13C0++0x3 line.long 0x0 "OUTDTSEL_B0P8T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x15C0++0x3 line.long 0x0 "OUTDTSEL_B0P8T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x19C0++0x3 line.long 0x0 "OUTDTSEL_B0P9T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x1BC0++0x3 line.long 0x0 "OUTDTSEL_B0P9T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x1DC0++0x3 line.long 0x0 "OUTDTSEL_B0P9T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x21C0++0x3 line.long 0x0 "OUTDTSEL_B1P6T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x23C0++0x3 line.long 0x0 "OUTDTSEL_B1P6T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x25C0++0x3 line.long 0x0 "OUTDTSEL_B1P6T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x29C0++0x3 line.long 0x0 "OUTDTSEL_B1P7T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x2BC0++0x3 line.long 0x0 "OUTDTSEL_B1P7T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x2DC0++0x3 line.long 0x0 "OUTDTSEL_B1P7T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x31C0++0x3 line.long 0x0 "OUTDTSEL_B1P8T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x33C0++0x3 line.long 0x0 "OUTDTSEL_B1P8T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x35C0++0x3 line.long 0x0 "OUTDTSEL_B1P8T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x39C0++0x3 line.long 0x0 "OUTDTSEL_B1P9T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x3BC0++0x3 line.long 0x0 "OUTDTSEL_B1P9T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x3DC0++0x3 line.long 0x0 "OUTDTSEL_B1P9T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x41C0++0x3 line.long 0x0 "OUTDTSEL_B2P6T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x43C0++0x3 line.long 0x0 "OUTDTSEL_B2P6T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x45C0++0x3 line.long 0x0 "OUTDTSEL_B2P6T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x49C0++0x3 line.long 0x0 "OUTDTSEL_B2P7T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x4BC0++0x3 line.long 0x0 "OUTDTSEL_B2P7T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x4DC0++0x3 line.long 0x0 "OUTDTSEL_B2P7T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x51C0++0x3 line.long 0x0 "OUTDTSEL_B2P8T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x53C0++0x3 line.long 0x0 "OUTDTSEL_B2P8T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x55C0++0x3 line.long 0x0 "OUTDTSEL_B2P8T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x59C0++0x3 line.long 0x0 "OUTDTSEL_B2P9T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x5BC0++0x3 line.long 0x0 "OUTDTSEL_B2P9T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x5DC0++0x3 line.long 0x0 "OUTDTSEL_B2P9T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x61C0++0x3 line.long 0x0 "OUTDTSEL_B3P6T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x63C0++0x3 line.long 0x0 "OUTDTSEL_B3P6T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x65C0++0x3 line.long 0x0 "OUTDTSEL_B3P6T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x69C0++0x3 line.long 0x0 "OUTDTSEL_B3P7T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x6BC0++0x3 line.long 0x0 "OUTDTSEL_B3P7T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x6DC0++0x3 line.long 0x0 "OUTDTSEL_B3P7T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x71C0++0x3 line.long 0x0 "OUTDTSEL_B3P8T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x73C0++0x3 line.long 0x0 "OUTDTSEL_B3P8T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x75C0++0x3 line.long 0x0 "OUTDTSEL_B3P8T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x79C0++0x3 line.long 0x0 "OUTDTSEL_B3P9T0,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x7BC0++0x3 line.long 0x0 "OUTDTSEL_B3P9T1,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x7DC0++0x3 line.long 0x0 "OUTDTSEL_B3P9T2,OUTDTSELn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. OUTDTSELn.." hexmask.long 0x0 0.--31. 1. "OUTDTSEL,Choosing whether output data is output by general output register OUTDTn or output data high register OUTDTHn / output data low register OUTDTLn." group.long 0x1C4++0x3 line.long 0x0 "OUTDTH_B0P6T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x3C4++0x3 line.long 0x0 "OUTDTH_B0P6T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x5C4++0x3 line.long 0x0 "OUTDTH_B0P6T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x9C4++0x3 line.long 0x0 "OUTDTH_B0P7T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0xBC4++0x3 line.long 0x0 "OUTDTH_B0P7T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0xDC4++0x3 line.long 0x0 "OUTDTH_B0P7T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x11C4++0x3 line.long 0x0 "OUTDTH_B0P8T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x13C4++0x3 line.long 0x0 "OUTDTH_B0P8T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x15C4++0x3 line.long 0x0 "OUTDTH_B0P8T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x19C4++0x3 line.long 0x0 "OUTDTH_B0P9T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x1BC4++0x3 line.long 0x0 "OUTDTH_B0P9T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x1DC4++0x3 line.long 0x0 "OUTDTH_B0P9T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x21C4++0x3 line.long 0x0 "OUTDTH_B1P6T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x23C4++0x3 line.long 0x0 "OUTDTH_B1P6T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x25C4++0x3 line.long 0x0 "OUTDTH_B1P6T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x29C4++0x3 line.long 0x0 "OUTDTH_B1P7T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x2BC4++0x3 line.long 0x0 "OUTDTH_B1P7T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x2DC4++0x3 line.long 0x0 "OUTDTH_B1P7T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x31C4++0x3 line.long 0x0 "OUTDTH_B1P8T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x33C4++0x3 line.long 0x0 "OUTDTH_B1P8T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x35C4++0x3 line.long 0x0 "OUTDTH_B1P8T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x39C4++0x3 line.long 0x0 "OUTDTH_B1P9T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x3BC4++0x3 line.long 0x0 "OUTDTH_B1P9T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x3DC4++0x3 line.long 0x0 "OUTDTH_B1P9T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x41C4++0x3 line.long 0x0 "OUTDTH_B2P6T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x43C4++0x3 line.long 0x0 "OUTDTH_B2P6T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x45C4++0x3 line.long 0x0 "OUTDTH_B2P6T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x49C4++0x3 line.long 0x0 "OUTDTH_B2P7T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x4BC4++0x3 line.long 0x0 "OUTDTH_B2P7T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x4DC4++0x3 line.long 0x0 "OUTDTH_B2P7T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x51C4++0x3 line.long 0x0 "OUTDTH_B2P8T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x53C4++0x3 line.long 0x0 "OUTDTH_B2P8T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x55C4++0x3 line.long 0x0 "OUTDTH_B2P8T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x59C4++0x3 line.long 0x0 "OUTDTH_B2P9T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x5BC4++0x3 line.long 0x0 "OUTDTH_B2P9T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x5DC4++0x3 line.long 0x0 "OUTDTH_B2P9T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x61C4++0x3 line.long 0x0 "OUTDTH_B3P6T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x63C4++0x3 line.long 0x0 "OUTDTH_B3P6T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x65C4++0x3 line.long 0x0 "OUTDTH_B3P6T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x69C4++0x3 line.long 0x0 "OUTDTH_B3P7T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x6BC4++0x3 line.long 0x0 "OUTDTH_B3P7T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x6DC4++0x3 line.long 0x0 "OUTDTH_B3P7T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x71C4++0x3 line.long 0x0 "OUTDTH_B3P8T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x73C4++0x3 line.long 0x0 "OUTDTH_B3P8T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x75C4++0x3 line.long 0x0 "OUTDTH_B3P8T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x79C4++0x3 line.long 0x0 "OUTDTH_B3P9T0,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x7BC4++0x3 line.long 0x0 "OUTDTH_B3P9T1,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x7DC4++0x3 line.long 0x0 "OUTDTH_B3P9T2,OUTDTHn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTH,Outputting high value data." group.long 0x1C8++0x3 line.long 0x0 "OUTDTL_B0P6T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x3C8++0x3 line.long 0x0 "OUTDTL_B0P6T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x5C8++0x3 line.long 0x0 "OUTDTL_B0P6T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x9C8++0x3 line.long 0x0 "OUTDTL_B0P7T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0xBC8++0x3 line.long 0x0 "OUTDTL_B0P7T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0xDC8++0x3 line.long 0x0 "OUTDTL_B0P7T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x11C8++0x3 line.long 0x0 "OUTDTL_B0P8T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x13C8++0x3 line.long 0x0 "OUTDTL_B0P8T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x15C8++0x3 line.long 0x0 "OUTDTL_B0P8T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x19C8++0x3 line.long 0x0 "OUTDTL_B0P9T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x1BC8++0x3 line.long 0x0 "OUTDTL_B0P9T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x1DC8++0x3 line.long 0x0 "OUTDTL_B0P9T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x21C8++0x3 line.long 0x0 "OUTDTL_B1P6T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x23C8++0x3 line.long 0x0 "OUTDTL_B1P6T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x25C8++0x3 line.long 0x0 "OUTDTL_B1P6T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x29C8++0x3 line.long 0x0 "OUTDTL_B1P7T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x2BC8++0x3 line.long 0x0 "OUTDTL_B1P7T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x2DC8++0x3 line.long 0x0 "OUTDTL_B1P7T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x31C8++0x3 line.long 0x0 "OUTDTL_B1P8T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x33C8++0x3 line.long 0x0 "OUTDTL_B1P8T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x35C8++0x3 line.long 0x0 "OUTDTL_B1P8T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x39C8++0x3 line.long 0x0 "OUTDTL_B1P9T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x3BC8++0x3 line.long 0x0 "OUTDTL_B1P9T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x3DC8++0x3 line.long 0x0 "OUTDTL_B1P9T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x41C8++0x3 line.long 0x0 "OUTDTL_B2P6T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x43C8++0x3 line.long 0x0 "OUTDTL_B2P6T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x45C8++0x3 line.long 0x0 "OUTDTL_B2P6T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x49C8++0x3 line.long 0x0 "OUTDTL_B2P7T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x4BC8++0x3 line.long 0x0 "OUTDTL_B2P7T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x4DC8++0x3 line.long 0x0 "OUTDTL_B2P7T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x51C8++0x3 line.long 0x0 "OUTDTL_B2P8T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x53C8++0x3 line.long 0x0 "OUTDTL_B2P8T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x55C8++0x3 line.long 0x0 "OUTDTL_B2P8T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x59C8++0x3 line.long 0x0 "OUTDTL_B2P9T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x5BC8++0x3 line.long 0x0 "OUTDTL_B2P9T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x5DC8++0x3 line.long 0x0 "OUTDTL_B2P9T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x61C8++0x3 line.long 0x0 "OUTDTL_B3P6T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x63C8++0x3 line.long 0x0 "OUTDTL_B3P6T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x65C8++0x3 line.long 0x0 "OUTDTL_B3P6T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x69C8++0x3 line.long 0x0 "OUTDTL_B3P7T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x6BC8++0x3 line.long 0x0 "OUTDTL_B3P7T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x6DC8++0x3 line.long 0x0 "OUTDTL_B3P7T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x71C8++0x3 line.long 0x0 "OUTDTL_B3P8T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x73C8++0x3 line.long 0x0 "OUTDTL_B3P8T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x75C8++0x3 line.long 0x0 "OUTDTL_B3P8T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x79C8++0x3 line.long 0x0 "OUTDTL_B3P9T0,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x7BC8++0x3 line.long 0x0 "OUTDTL_B3P9T1,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x7DC8++0x3 line.long 0x0 "OUTDTL_B3P9T2,OUTDTLn is valid only for the ports for which general input/output mode is selected by the general IO/interrupt switching register and then general output mode is selected by the general input/output switching register. and the output data.." hexmask.long 0x0 0.--31. 1. "OUTDTL,Outputting low value data." group.long 0x1CC++0x3 line.long 0x0 "BOTHEDGE_B0P6T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x3CC++0x3 line.long 0x0 "BOTHEDGE_B0P6T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x5CC++0x3 line.long 0x0 "BOTHEDGE_B0P6T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x9CC++0x3 line.long 0x0 "BOTHEDGE_B0P7T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0xBCC++0x3 line.long 0x0 "BOTHEDGE_B0P7T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0xDCC++0x3 line.long 0x0 "BOTHEDGE_B0P7T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x11CC++0x3 line.long 0x0 "BOTHEDGE_B0P8T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x13CC++0x3 line.long 0x0 "BOTHEDGE_B0P8T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x15CC++0x3 line.long 0x0 "BOTHEDGE_B0P8T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x19CC++0x3 line.long 0x0 "BOTHEDGE_B0P9T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x1BCC++0x3 line.long 0x0 "BOTHEDGE_B0P9T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x1DCC++0x3 line.long 0x0 "BOTHEDGE_B0P9T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x21CC++0x3 line.long 0x0 "BOTHEDGE_B1P6T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x23CC++0x3 line.long 0x0 "BOTHEDGE_B1P6T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x25CC++0x3 line.long 0x0 "BOTHEDGE_B1P6T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x29CC++0x3 line.long 0x0 "BOTHEDGE_B1P7T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x2BCC++0x3 line.long 0x0 "BOTHEDGE_B1P7T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x2DCC++0x3 line.long 0x0 "BOTHEDGE_B1P7T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x31CC++0x3 line.long 0x0 "BOTHEDGE_B1P8T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x33CC++0x3 line.long 0x0 "BOTHEDGE_B1P8T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x35CC++0x3 line.long 0x0 "BOTHEDGE_B1P8T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x39CC++0x3 line.long 0x0 "BOTHEDGE_B1P9T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x3BCC++0x3 line.long 0x0 "BOTHEDGE_B1P9T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x3DCC++0x3 line.long 0x0 "BOTHEDGE_B1P9T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x41CC++0x3 line.long 0x0 "BOTHEDGE_B2P6T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x43CC++0x3 line.long 0x0 "BOTHEDGE_B2P6T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x45CC++0x3 line.long 0x0 "BOTHEDGE_B2P6T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x49CC++0x3 line.long 0x0 "BOTHEDGE_B2P7T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x4BCC++0x3 line.long 0x0 "BOTHEDGE_B2P7T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x4DCC++0x3 line.long 0x0 "BOTHEDGE_B2P7T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x51CC++0x3 line.long 0x0 "BOTHEDGE_B2P8T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x53CC++0x3 line.long 0x0 "BOTHEDGE_B2P8T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x55CC++0x3 line.long 0x0 "BOTHEDGE_B2P8T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x59CC++0x3 line.long 0x0 "BOTHEDGE_B2P9T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x5BCC++0x3 line.long 0x0 "BOTHEDGE_B2P9T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x5DCC++0x3 line.long 0x0 "BOTHEDGE_B2P9T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x61CC++0x3 line.long 0x0 "BOTHEDGE_B3P6T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x63CC++0x3 line.long 0x0 "BOTHEDGE_B3P6T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x65CC++0x3 line.long 0x0 "BOTHEDGE_B3P6T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x69CC++0x3 line.long 0x0 "BOTHEDGE_B3P7T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x6BCC++0x3 line.long 0x0 "BOTHEDGE_B3P7T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x6DCC++0x3 line.long 0x0 "BOTHEDGE_B3P7T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x71CC++0x3 line.long 0x0 "BOTHEDGE_B3P8T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x73CC++0x3 line.long 0x0 "BOTHEDGE_B3P8T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x75CC++0x3 line.long 0x0 "BOTHEDGE_B3P8T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x79CC++0x3 line.long 0x0 "BOTHEDGE_B3P9T0,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x7BCC++0x3 line.long 0x0 "BOTHEDGE_B3P9T1,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x7DCC++0x3 line.long 0x0 "BOTHEDGE_B3P9T2,BOTHEDGEn is valid only when the edge detection mode is selected by the edge/level select registers. Specially. BOTHEDGEn selects the detection condition (one edge or both edges) of the interrupt input signal on each port pin for which.." hexmask.long 0x0 0.--31. 1. "BOTHEDGE,Selecting one edge or both edge detection condition of the interrupt input signal on each port pin for which interrupt input mode and edge detection mode are selected." group.long 0x1D0++0x3 line.long 0x0 "INEN_B0P6T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x3D0++0x3 line.long 0x0 "INEN_B0P6T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x5D0++0x3 line.long 0x0 "INEN_B0P6T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x9D0++0x3 line.long 0x0 "INEN_B0P7T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0xBD0++0x3 line.long 0x0 "INEN_B0P7T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0xDD0++0x3 line.long 0x0 "INEN_B0P7T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x11D0++0x3 line.long 0x0 "INEN_B0P8T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x13D0++0x3 line.long 0x0 "INEN_B0P8T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x15D0++0x3 line.long 0x0 "INEN_B0P8T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x19D0++0x3 line.long 0x0 "INEN_B0P9T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x1BD0++0x3 line.long 0x0 "INEN_B0P9T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x1DD0++0x3 line.long 0x0 "INEN_B0P9T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x21D0++0x3 line.long 0x0 "INEN_B1P6T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x23D0++0x3 line.long 0x0 "INEN_B1P6T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x25D0++0x3 line.long 0x0 "INEN_B1P6T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x29D0++0x3 line.long 0x0 "INEN_B1P7T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x2BD0++0x3 line.long 0x0 "INEN_B1P7T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x2DD0++0x3 line.long 0x0 "INEN_B1P7T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x31D0++0x3 line.long 0x0 "INEN_B1P8T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x33D0++0x3 line.long 0x0 "INEN_B1P8T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x35D0++0x3 line.long 0x0 "INEN_B1P8T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x39D0++0x3 line.long 0x0 "INEN_B1P9T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x3BD0++0x3 line.long 0x0 "INEN_B1P9T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x3DD0++0x3 line.long 0x0 "INEN_B1P9T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x41D0++0x3 line.long 0x0 "INEN_B2P6T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x43D0++0x3 line.long 0x0 "INEN_B2P6T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x45D0++0x3 line.long 0x0 "INEN_B2P6T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x49D0++0x3 line.long 0x0 "INEN_B2P7T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x4BD0++0x3 line.long 0x0 "INEN_B2P7T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x4DD0++0x3 line.long 0x0 "INEN_B2P7T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x51D0++0x3 line.long 0x0 "INEN_B2P8T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x53D0++0x3 line.long 0x0 "INEN_B2P8T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x55D0++0x3 line.long 0x0 "INEN_B2P8T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x59D0++0x3 line.long 0x0 "INEN_B2P9T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x5BD0++0x3 line.long 0x0 "INEN_B2P9T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x5DD0++0x3 line.long 0x0 "INEN_B2P9T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x61D0++0x3 line.long 0x0 "INEN_B3P6T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x63D0++0x3 line.long 0x0 "INEN_B3P6T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x65D0++0x3 line.long 0x0 "INEN_B3P6T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x69D0++0x3 line.long 0x0 "INEN_B3P7T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x6BD0++0x3 line.long 0x0 "INEN_B3P7T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x6DD0++0x3 line.long 0x0 "INEN_B3P7T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x71D0++0x3 line.long 0x0 "INEN_B3P8T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x73D0++0x3 line.long 0x0 "INEN_B3P8T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x75D0++0x3 line.long 0x0 "INEN_B3P8T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x79D0++0x3 line.long 0x0 "INEN_B3P9T0,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x7BD0++0x3 line.long 0x0 "INEN_B3P9T1,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x7DD0++0x3 line.long 0x0 "INEN_B3P9T2,Create registers that can control IE in GPIO." hexmask.long 0x0 0.--31. 1. "INEN,???" group.long 0x88++0x3 line.long 0x0 "DRV2CTRL_B0P6T0,DRV Control Register2 B0P6T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x288++0x3 line.long 0x0 "DRV2CTRL_B0P6T1,DRV Control Register2 B0P6T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x488++0x3 line.long 0x0 "DRV2CTRL_B0P6T2,DRV Control Register2 B0P6T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x888++0x3 line.long 0x0 "DRV2CTRL_B0P7T0,DRV Control Register2 B0P7T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0xA88++0x3 line.long 0x0 "DRV2CTRL_B0P7T1,DRV Control Register2 B0P7T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0xC88++0x3 line.long 0x0 "DRV2CTRL_B0P7T2,DRV Control Register2 B0P7T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x1088++0x3 line.long 0x0 "DRV2CTRL_B0P8T0,DRV Control Register2 B0P8T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x1288++0x3 line.long 0x0 "DRV2CTRL_B0P8T1,DRV Control Register2 B0P8T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x1488++0x3 line.long 0x0 "DRV2CTRL_B0P8T2,DRV Control Register2 B0P8T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x1888++0x3 line.long 0x0 "DRV2CTRL_B0P9T0,DRV Control Register2 B0P9T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x1A88++0x3 line.long 0x0 "DRV2CTRL_B0P9T1,DRV Control Register2 B0P9T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x1C88++0x3 line.long 0x0 "DRV2CTRL_B0P9T2,DRV Control Register2 B0P9T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2088++0x3 line.long 0x0 "DRV2CTRL_B1P6T0,DRV Control Register2 B1P6T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2288++0x3 line.long 0x0 "DRV2CTRL_B1P6T1,DRV Control Register2 B1P6T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2488++0x3 line.long 0x0 "DRV2CTRL_B1P6T2,DRV Control Register2 B1P6T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2888++0x3 line.long 0x0 "DRV2CTRL_B1P7T0,DRV Control Register2 B1P7T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2A88++0x3 line.long 0x0 "DRV2CTRL_B1P7T1,DRV Control Register2 B1P7T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x2C88++0x3 line.long 0x0 "DRV2CTRL_B1P7T2,DRV Control Register2 B1P7T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x3088++0x3 line.long 0x0 "DRV2CTRL_B1P8T0,DRV Control Register2 B1P8T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x3288++0x3 line.long 0x0 "DRV2CTRL_B1P8T1,DRV Control Register2 B1P8T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x3488++0x3 line.long 0x0 "DRV2CTRL_B1P8T2,DRV Control Register2 B1P8T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x3888++0x3 line.long 0x0 "DRV2CTRL_B1P9T0,DRV Control Register2 B1P9T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x3A88++0x3 line.long 0x0 "DRV2CTRL_B1P9T1,DRV Control Register2 B1P9T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x3C88++0x3 line.long 0x0 "DRV2CTRL_B1P9T2,DRV Control Register2 B1P9T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4088++0x3 line.long 0x0 "DRV2CTRL_B2P6T0,DRV Control Register2 B2P6T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4288++0x3 line.long 0x0 "DRV2CTRL_B2P6T1,DRV Control Register2 B2P6T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4488++0x3 line.long 0x0 "DRV2CTRL_B2P6T2,DRV Control Register2 B2P6T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4888++0x3 line.long 0x0 "DRV2CTRL_B2P7T0,DRV Control Register2 B2P7T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4A88++0x3 line.long 0x0 "DRV2CTRL_B2P7T1,DRV Control Register2 B2P7T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x4C88++0x3 line.long 0x0 "DRV2CTRL_B2P7T2,DRV Control Register2 B2P7T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x5088++0x3 line.long 0x0 "DRV2CTRL_B2P8T0,DRV Control Register2 B2P8T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x5288++0x3 line.long 0x0 "DRV2CTRL_B2P8T1,DRV Control Register2 B2P8T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x5488++0x3 line.long 0x0 "DRV2CTRL_B2P8T2,DRV Control Register2 B2P8T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x5888++0x3 line.long 0x0 "DRV2CTRL_B2P9T0,DRV Control Register2 B2P9T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x5A88++0x3 line.long 0x0 "DRV2CTRL_B2P9T1,DRV Control Register2 B2P9T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x5C88++0x3 line.long 0x0 "DRV2CTRL_B2P9T2,DRV Control Register2 B2P9T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6088++0x3 line.long 0x0 "DRV2CTRL_B3P6T0,DRV Control Register2 B3P6T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6288++0x3 line.long 0x0 "DRV2CTRL_B3P6T1,DRV Control Register2 B3P6T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6488++0x3 line.long 0x0 "DRV2CTRL_B3P6T2,DRV Control Register2 B3P6T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6888++0x3 line.long 0x0 "DRV2CTRL_B3P7T0,DRV Control Register2 B3P7T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6A88++0x3 line.long 0x0 "DRV2CTRL_B3P7T1,DRV Control Register2 B3P7T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x6C88++0x3 line.long 0x0 "DRV2CTRL_B3P7T2,DRV Control Register2 B3P7T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x7088++0x3 line.long 0x0 "DRV2CTRL_B3P8T0,DRV Control Register2 B3P8T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x7288++0x3 line.long 0x0 "DRV2CTRL_B3P8T1,DRV Control Register2 B3P8T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x7488++0x3 line.long 0x0 "DRV2CTRL_B3P8T2,DRV Control Register2 B3P8T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x7888++0x3 line.long 0x0 "DRV2CTRL_B3P9T0,DRV Control Register2 B3P9T0" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x7A88++0x3 line.long 0x0 "DRV2CTRL_B3P9T1,DRV Control Register2 B3P9T1" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x7C88++0x3 line.long 0x0 "DRV2CTRL_B3P9T2,DRV Control Register2 B3P9T2" hexmask.long 0x0 0.--31. 1. "DRV2CTRL" group.long 0x8C++0x3 line.long 0x0 "DRV3CTRL_B0P6T0,DRV Control Register3 B0P6T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x28C++0x3 line.long 0x0 "DRV3CTRL_B0P6T1,DRV Control Register3 B0P6T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x48C++0x3 line.long 0x0 "DRV3CTRL_B0P6T2,DRV Control Register3 B0P6T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x88C++0x3 line.long 0x0 "DRV3CTRL_B0P7T0,DRV Control Register3 B0P7T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0xA8C++0x3 line.long 0x0 "DRV3CTRL_B0P7T1,DRV Control Register3 B0P7T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0xC8C++0x3 line.long 0x0 "DRV3CTRL_B0P7T2,DRV Control Register3 B0P7T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x108C++0x3 line.long 0x0 "DRV3CTRL_B0P8T0,DRV Control Register3 B0P8T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x128C++0x3 line.long 0x0 "DRV3CTRL_B0P8T1,DRV Control Register3 B0P8T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x148C++0x3 line.long 0x0 "DRV3CTRL_B0P8T2,DRV Control Register3 B0P8T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x188C++0x3 line.long 0x0 "DRV3CTRL_B0P9T0,DRV Control Register3 B0P9T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x1A8C++0x3 line.long 0x0 "DRV3CTRL_B0P9T1,DRV Control Register3 B0P9T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x1C8C++0x3 line.long 0x0 "DRV3CTRL_B0P9T2,DRV Control Register3 B0P9T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x208C++0x3 line.long 0x0 "DRV3CTRL_B1P6T0,DRV Control Register3 B1P6T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x228C++0x3 line.long 0x0 "DRV3CTRL_B1P6T1,DRV Control Register3 B1P6T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x248C++0x3 line.long 0x0 "DRV3CTRL_B1P6T2,DRV Control Register3 B1P6T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x288C++0x3 line.long 0x0 "DRV3CTRL_B1P7T0,DRV Control Register3 B1P7T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x2A8C++0x3 line.long 0x0 "DRV3CTRL_B1P7T1,DRV Control Register3 B1P7T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x2C8C++0x3 line.long 0x0 "DRV3CTRL_B1P7T2,DRV Control Register3 B1P7T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x308C++0x3 line.long 0x0 "DRV3CTRL_B1P8T0,DRV Control Register3 B1P8T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x328C++0x3 line.long 0x0 "DRV3CTRL_B1P8T1,DRV Control Register3 B1P8T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x348C++0x3 line.long 0x0 "DRV3CTRL_B1P8T2,DRV Control Register3 B1P8T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x388C++0x3 line.long 0x0 "DRV3CTRL_B1P9T0,DRV Control Register3 B1P9T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x3A8C++0x3 line.long 0x0 "DRV3CTRL_B1P9T1,DRV Control Register3 B1P9T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x3C8C++0x3 line.long 0x0 "DRV3CTRL_B1P9T2,DRV Control Register3 B1P9T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x408C++0x3 line.long 0x0 "DRV3CTRL_B2P6T0,DRV Control Register3 B2P6T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x428C++0x3 line.long 0x0 "DRV3CTRL_B2P6T1,DRV Control Register3 B2P6T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x448C++0x3 line.long 0x0 "DRV3CTRL_B2P6T2,DRV Control Register3 B2P6T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x488C++0x3 line.long 0x0 "DRV3CTRL_B2P7T0,DRV Control Register3 B2P7T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x4A8C++0x3 line.long 0x0 "DRV3CTRL_B2P7T1,DRV Control Register3 B2P7T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x4C8C++0x3 line.long 0x0 "DRV3CTRL_B2P7T2,DRV Control Register3 B2P7T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x508C++0x3 line.long 0x0 "DRV3CTRL_B2P8T0,DRV Control Register3 B2P8T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x528C++0x3 line.long 0x0 "DRV3CTRL_B2P8T1,DRV Control Register3 B2P8T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x548C++0x3 line.long 0x0 "DRV3CTRL_B2P8T2,DRV Control Register3 B2P8T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x588C++0x3 line.long 0x0 "DRV3CTRL_B2P9T0,DRV Control Register3 B2P9T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x5A8C++0x3 line.long 0x0 "DRV3CTRL_B2P9T1,DRV Control Register3 B2P9T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x5C8C++0x3 line.long 0x0 "DRV3CTRL_B2P9T2,DRV Control Register3 B2P9T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x608C++0x3 line.long 0x0 "DRV3CTRL_B3P6T0,DRV Control Register3 B3P6T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x628C++0x3 line.long 0x0 "DRV3CTRL_B3P6T1,DRV Control Register3 B3P6T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x648C++0x3 line.long 0x0 "DRV3CTRL_B3P6T2,DRV Control Register3 B3P6T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x688C++0x3 line.long 0x0 "DRV3CTRL_B3P7T0,DRV Control Register3 B3P7T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x6A8C++0x3 line.long 0x0 "DRV3CTRL_B3P7T1,DRV Control Register3 B3P7T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x6C8C++0x3 line.long 0x0 "DRV3CTRL_B3P7T2,DRV Control Register3 B3P7T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x708C++0x3 line.long 0x0 "DRV3CTRL_B3P8T0,DRV Control Register3 B3P8T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x728C++0x3 line.long 0x0 "DRV3CTRL_B3P8T1,DRV Control Register3 B3P8T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x748C++0x3 line.long 0x0 "DRV3CTRL_B3P8T2,DRV Control Register3 B3P8T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x788C++0x3 line.long 0x0 "DRV3CTRL_B3P9T0,DRV Control Register3 B3P9T0" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x7A8C++0x3 line.long 0x0 "DRV3CTRL_B3P9T1,DRV Control Register3 B3P9T1" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" group.long 0x7C8C++0x3 line.long 0x0 "DRV3CTRL_B3P9T2,DRV Control Register3 B3P9T2" hexmask.long 0x0 0.--31. 1. "DRV3CTRL" tree.end tree "PFC_SYS" base ad:0xE6070000 group.long 0x20++0x3 line.long 0x0 "DM0PRSYS_B0P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x2020++0x3 line.long 0x0 "DM0PRSYS_B1P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x4020++0x3 line.long 0x0 "DM0PRSYS_B2P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x6020++0x3 line.long 0x0 "DM0PRSYS_B3P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x24++0x3 line.long 0x0 "DM1PRSYS_B0P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x2024++0x3 line.long 0x0 "DM1PRSYS_B1P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x4024++0x3 line.long 0x0 "DM1PRSYS_B2P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x6024++0x3 line.long 0x0 "DM1PRSYS_B3P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x28++0x3 line.long 0x0 "DM2PRSYS_B0P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x2028++0x3 line.long 0x0 "DM2PRSYS_B1P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x4028++0x3 line.long 0x0 "DM2PRSYS_B2P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x6028++0x3 line.long 0x0 "DM2PRSYS_B3P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x2C++0x3 line.long 0x0 "DM3PRSYS_B0P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x202C++0x3 line.long 0x0 "DM3PRSYS_B1P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x402C++0x3 line.long 0x0 "DM3PRSYS_B2P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x602C++0x3 line.long 0x0 "DM3PRSYS_B3P10T0,Function: DM*PRn / DM*PRSYS enables / disables writing to the registers from bus domain." hexmask.long 0x0 0.--31. 1. "DM0PRSYS,Bus Domain Protection" group.long 0x80++0x3 line.long 0x0 "DRV0CTRLSYS_B0P10T0,DRV Control Register0 B0P10T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRLSYS" group.long 0x2080++0x3 line.long 0x0 "DRV0CTRLSYS_B1P10T0,DRV Control Register0 B1P10T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRLSYS" group.long 0x4080++0x3 line.long 0x0 "DRV0CTRLSYS_B2P10T0,DRV Control Register0 B2P10T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRLSYS" group.long 0x6080++0x3 line.long 0x0 "DRV0CTRLSYS_B3P10T0,DRV Control Register0 B3P10T0" hexmask.long 0x0 0.--31. 1. "DRV0CTRLSYS" group.long 0xE0++0x3 line.long 0x0 "PUDSYS_B0P10T0,LSI Pin Pull-up/down Control Register B0P10T0" hexmask.long 0x0 0.--31. 1. "PUDSYS" group.long 0x20E0++0x3 line.long 0x0 "PUDSYS_B1P10T0,LSI Pin Pull-up/down Control Register B1P10T0" hexmask.long 0x0 0.--31. 1. "PUDSYS" group.long 0x40E0++0x3 line.long 0x0 "PUDSYS_B2P10T0,LSI Pin Pull-up/down Control Register B2P10T0" hexmask.long 0x0 0.--31. 1. "PUDSYS" group.long 0x60E0++0x3 line.long 0x0 "PUDSYS_B3P10T0,LSI Pin Pull-up/down Control Register B3P10T0" hexmask.long 0x0 0.--31. 1. "PUDSYS" group.long 0x84++0x3 line.long 0x0 "DRV1CTRLSYS_B0P10T0,DRV Control Register1 B0P10T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRLSYS" group.long 0x2084++0x3 line.long 0x0 "DRV1CTRLSYS_B1P10T0,DRV Control Register1 B1P10T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRLSYS" group.long 0x4084++0x3 line.long 0x0 "DRV1CTRLSYS_B2P10T0,DRV Control Register1 B2P10T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRLSYS" group.long 0x6084++0x3 line.long 0x0 "DRV1CTRLSYS_B3P10T0,DRV Control Register1 B3P10T0" hexmask.long 0x0 0.--31. 1. "DRV1CTRLSYS" tree.end tree.end tree "PWM" base ad:0x0 tree "PWM_0" base ad:0xE6E30000 group.long 0x0++0x7 line.long 0x0 "PWMCR0,PWM Control Register" hexmask.long.byte 0x0 16.--19. 1. "CC0,Clock Control" bitfld.long 0x0 15. "CCMD,CC0 Frequency Division Mode" "0: f MHz/2,1: f MHz/23" newline bitfld.long 0x0 11. "SYNC,Specifies whether to allow the set values in the PWM count register (PWMCNT) to be reflected in the timer operation synchronously with setting the PWM control register (PWMCR)." "0: Allows the PWMCNT set values to be reflected in..,1: Allows the PWMCNT set values to be reflected in.." bitfld.long 0x0 5.--6. "FS,Functional safety use only. Keep initial value." "0,1,2,3" newline bitfld.long 0x0 4. "SS0,Single Pulse Output" "0: The timer operates in continuous pulse output mode,1: The timer operates only for a single cycle and.." bitfld.long 0x0 3. "ECEN,Functional safety use only. Keep initial value." "0,1" newline bitfld.long 0x0 0. "EN0,Channel Enable" "0: The channel is held in the idle state,1: The channel outputs high and low levels in a.." line.long 0x4 "PWMCNT0,PWM Count Register" hexmask.long.word 0x4 16.--25. 1. "CYC0,PWM Cycle" hexmask.long.word 0x4 0.--9. 1. "PH0,PWM High-Level Period" group.long 0xC++0x3 line.long 0x0 "PWMEI0,PWM Error Injection Register" bitfld.long 0x0 0. "PWMEI,This register is functional safety use only. Keep initial value." "0,1" tree.end tree "PWM_1" base ad:0xE6E31000 group.long 0x0++0x7 line.long 0x0 "PWMCR1,PWM Control Register" hexmask.long.byte 0x0 16.--19. 1. "CC0,Clock Control" bitfld.long 0x0 15. "CCMD,CC0 Frequency Division Mode" "0: f MHz/2,1: f MHz/23" newline bitfld.long 0x0 11. "SYNC,Specifies whether to allow the set values in the PWM count register (PWMCNT) to be reflected in the timer operation synchronously with setting the PWM control register (PWMCR)." "0: Allows the PWMCNT set values to be reflected in..,1: Allows the PWMCNT set values to be reflected in.." bitfld.long 0x0 5.--6. "FS,Functional safety use only. Keep initial value." "0,1,2,3" newline bitfld.long 0x0 4. "SS0,Single Pulse Output" "0: The timer operates in continuous pulse output mode,1: The timer operates only for a single cycle and.." bitfld.long 0x0 3. "ECEN,Functional safety use only. Keep initial value." "0,1" newline bitfld.long 0x0 0. "EN0,Channel Enable" "0: The channel is held in the idle state,1: The channel outputs high and low levels in a.." line.long 0x4 "PWMCNT1,PWM Count Register" hexmask.long.word 0x4 16.--25. 1. "CYC0,PWM Cycle" hexmask.long.word 0x4 0.--9. 1. "PH0,PWM High-Level Period" group.long 0xC++0x3 line.long 0x0 "PWMEI1,PWM Error Injection Register" bitfld.long 0x0 0. "PWMEI,This register is functional safety use only. Keep initial value." "0,1" tree.end tree "PWM_2" base ad:0xE6E32000 group.long 0x0++0x7 line.long 0x0 "PWMCR2,PWM Control Register" hexmask.long.byte 0x0 16.--19. 1. "CC0,Clock Control" bitfld.long 0x0 15. "CCMD,CC0 Frequency Division Mode" "0: f MHz/2,1: f MHz/23" newline bitfld.long 0x0 11. "SYNC,Specifies whether to allow the set values in the PWM count register (PWMCNT) to be reflected in the timer operation synchronously with setting the PWM control register (PWMCR)." "0: Allows the PWMCNT set values to be reflected in..,1: Allows the PWMCNT set values to be reflected in.." bitfld.long 0x0 5.--6. "FS,Functional safety use only. Keep initial value." "0,1,2,3" newline bitfld.long 0x0 4. "SS0,Single Pulse Output" "0: The timer operates in continuous pulse output mode,1: The timer operates only for a single cycle and.." bitfld.long 0x0 3. "ECEN,Functional safety use only. Keep initial value." "0,1" newline bitfld.long 0x0 0. "EN0,Channel Enable" "0: The channel is held in the idle state,1: The channel outputs high and low levels in a.." line.long 0x4 "PWMCNT2,PWM Count Register" hexmask.long.word 0x4 16.--25. 1. "CYC0,PWM Cycle" hexmask.long.word 0x4 0.--9. 1. "PH0,PWM High-Level Period" group.long 0xC++0x3 line.long 0x0 "PWMEI2,PWM Error Injection Register" bitfld.long 0x0 0. "PWMEI,This register is functional safety use only. Keep initial value." "0,1" tree.end tree "PWM_3" base ad:0xE6E33000 group.long 0x0++0x7 line.long 0x0 "PWMCR3,PWM Control Register" hexmask.long.byte 0x0 16.--19. 1. "CC0,Clock Control" bitfld.long 0x0 15. "CCMD,CC0 Frequency Division Mode" "0: f MHz/2,1: f MHz/23" newline bitfld.long 0x0 11. "SYNC,Specifies whether to allow the set values in the PWM count register (PWMCNT) to be reflected in the timer operation synchronously with setting the PWM control register (PWMCR)." "0: Allows the PWMCNT set values to be reflected in..,1: Allows the PWMCNT set values to be reflected in.." bitfld.long 0x0 5.--6. "FS,Functional safety use only. Keep initial value." "0,1,2,3" newline bitfld.long 0x0 4. "SS0,Single Pulse Output" "0: The timer operates in continuous pulse output mode,1: The timer operates only for a single cycle and.." bitfld.long 0x0 3. "ECEN,Functional safety use only. Keep initial value." "0,1" newline bitfld.long 0x0 0. "EN0,Channel Enable" "0: The channel is held in the idle state,1: The channel outputs high and low levels in a.." line.long 0x4 "PWMCNT3,PWM Count Register" hexmask.long.word 0x4 16.--25. 1. "CYC0,PWM Cycle" hexmask.long.word 0x4 0.--9. 1. "PH0,PWM High-Level Period" group.long 0xC++0x3 line.long 0x0 "PWMEI3,PWM Error Injection Register" bitfld.long 0x0 0. "PWMEI,This register is functional safety use only. Keep initial value." "0,1" tree.end tree "PWM_4" base ad:0xE6E34000 group.long 0x0++0x7 line.long 0x0 "PWMCR4,PWM Control Register" hexmask.long.byte 0x0 16.--19. 1. "CC0,Clock Control" bitfld.long 0x0 15. "CCMD,CC0 Frequency Division Mode" "0: f MHz/2,1: f MHz/23" newline bitfld.long 0x0 11. "SYNC,Specifies whether to allow the set values in the PWM count register (PWMCNT) to be reflected in the timer operation synchronously with setting the PWM control register (PWMCR)." "0: Allows the PWMCNT set values to be reflected in..,1: Allows the PWMCNT set values to be reflected in.." bitfld.long 0x0 5.--6. "FS,Functional safety use only. Keep initial value." "0,1,2,3" newline bitfld.long 0x0 4. "SS0,Single Pulse Output" "0: The timer operates in continuous pulse output mode,1: The timer operates only for a single cycle and.." bitfld.long 0x0 3. "ECEN,Functional safety use only. Keep initial value." "0,1" newline bitfld.long 0x0 0. "EN0,Channel Enable" "0: The channel is held in the idle state,1: The channel outputs high and low levels in a.." line.long 0x4 "PWMCNT4,PWM Count Register" hexmask.long.word 0x4 16.--25. 1. "CYC0,PWM Cycle" hexmask.long.word 0x4 0.--9. 1. "PH0,PWM High-Level Period" group.long 0xC++0x3 line.long 0x0 "PWMEI4,PWM Error Injection Register" bitfld.long 0x0 0. "PWMEI,This register is functional safety use only. Keep initial value." "0,1" tree.end tree.end tree "QOS" base ad:0xE6700000 group.quad 0x0++0xFFF line.quad 0x0 "QOSBW_FIX_QOS_BANK[0] [0],QOSBW FIX QOS BANK0 Register 0" bitfld.quad 0x0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8 "QOSBW_FIX_QOS_BANK[0] [1],QOSBW FIX QOS BANK0 Register 1" bitfld.quad 0x8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x10 "QOSBW_FIX_QOS_BANK[0] [2],QOSBW FIX QOS BANK0 Register 2" bitfld.quad 0x10 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x10 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x10 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x10 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x10 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x10 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x18 "QOSBW_FIX_QOS_BANK[0] [3],QOSBW FIX QOS BANK0 Register 3" bitfld.quad 0x18 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x18 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x18 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x18 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x18 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x18 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x20 "QOSBW_FIX_QOS_BANK[0] [4],QOSBW FIX QOS BANK0 Register 4" bitfld.quad 0x20 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x20 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x20 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x20 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x20 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x20 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x28 "QOSBW_FIX_QOS_BANK[0] [5],QOSBW FIX QOS BANK0 Register 5" bitfld.quad 0x28 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x28 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x28 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x28 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x28 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x28 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x30 "QOSBW_FIX_QOS_BANK[0] [6],QOSBW FIX QOS BANK0 Register 6" bitfld.quad 0x30 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x30 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x30 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x30 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x30 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x30 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x38 "QOSBW_FIX_QOS_BANK[0] [7],QOSBW FIX QOS BANK0 Register 7" bitfld.quad 0x38 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x38 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x38 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x38 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x38 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x38 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x40 "QOSBW_FIX_QOS_BANK[0] [8],QOSBW FIX QOS BANK0 Register 8" bitfld.quad 0x40 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x40 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x40 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x40 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x40 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x40 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x48 "QOSBW_FIX_QOS_BANK[0] [9],QOSBW FIX QOS BANK0 Register 9" bitfld.quad 0x48 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x48 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x48 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x48 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x48 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x48 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x50 "QOSBW_FIX_QOS_BANK[0] [10],QOSBW FIX QOS BANK0 Register 10" bitfld.quad 0x50 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x50 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x50 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x50 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x50 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x50 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x58 "QOSBW_FIX_QOS_BANK[0] [11],QOSBW FIX QOS BANK0 Register 11" bitfld.quad 0x58 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x58 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x58 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x58 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x58 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x58 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x60 "QOSBW_FIX_QOS_BANK[0] [12],QOSBW FIX QOS BANK0 Register 12" bitfld.quad 0x60 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x60 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x60 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x60 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x60 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x60 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x68 "QOSBW_FIX_QOS_BANK[0] [13],QOSBW FIX QOS BANK0 Register 13" bitfld.quad 0x68 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x68 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x68 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x68 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x68 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x68 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x70 "QOSBW_FIX_QOS_BANK[0] [14],QOSBW FIX QOS BANK0 Register 14" bitfld.quad 0x70 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x70 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x70 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x70 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x70 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x70 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x78 "QOSBW_FIX_QOS_BANK[0] [15],QOSBW FIX QOS BANK0 Register 15" bitfld.quad 0x78 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x78 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x78 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x78 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x78 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x78 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x80 "QOSBW_FIX_QOS_BANK[0] [16],QOSBW FIX QOS BANK0 Register 16" bitfld.quad 0x80 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x80 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x80 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x80 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x80 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x80 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x88 "QOSBW_FIX_QOS_BANK[0] [17],QOSBW FIX QOS BANK0 Register 17" bitfld.quad 0x88 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x88 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x88 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x88 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x88 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x88 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x90 "QOSBW_FIX_QOS_BANK[0] [18],QOSBW FIX QOS BANK0 Register 18" bitfld.quad 0x90 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x90 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x90 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x90 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x90 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x90 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x98 "QOSBW_FIX_QOS_BANK[0] [19],QOSBW FIX QOS BANK0 Register 19" bitfld.quad 0x98 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x98 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x98 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x98 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x98 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x98 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA0 "QOSBW_FIX_QOS_BANK[0] [20],QOSBW FIX QOS BANK0 Register 20" bitfld.quad 0xA0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA8 "QOSBW_FIX_QOS_BANK[0] [21],QOSBW FIX QOS BANK0 Register 21" bitfld.quad 0xA8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB0 "QOSBW_FIX_QOS_BANK[0] [22],QOSBW FIX QOS BANK0 Register 22" bitfld.quad 0xB0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB8 "QOSBW_FIX_QOS_BANK[0] [23],QOSBW FIX QOS BANK0 Register 23" bitfld.quad 0xB8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC0 "QOSBW_FIX_QOS_BANK[0] [24],QOSBW FIX QOS BANK0 Register 24" bitfld.quad 0xC0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC8 "QOSBW_FIX_QOS_BANK[0] [25],QOSBW FIX QOS BANK0 Register 25" bitfld.quad 0xC8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD0 "QOSBW_FIX_QOS_BANK[0] [26],QOSBW FIX QOS BANK0 Register 26" bitfld.quad 0xD0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD8 "QOSBW_FIX_QOS_BANK[0] [27],QOSBW FIX QOS BANK0 Register 27" bitfld.quad 0xD8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE0 "QOSBW_FIX_QOS_BANK[0] [28],QOSBW FIX QOS BANK0 Register 28" bitfld.quad 0xE0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE8 "QOSBW_FIX_QOS_BANK[0] [29],QOSBW FIX QOS BANK0 Register 29" bitfld.quad 0xE8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF0 "QOSBW_FIX_QOS_BANK[0] [30],QOSBW FIX QOS BANK0 Register 30" bitfld.quad 0xF0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF8 "QOSBW_FIX_QOS_BANK[0] [31],QOSBW FIX QOS BANK0 Register 31" bitfld.quad 0xF8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x100 "QOSBW_FIX_QOS_BANK[0] [32],QOSBW FIX QOS BANK0 Register 32" bitfld.quad 0x100 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x100 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x100 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x100 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x100 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x100 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x108 "QOSBW_FIX_QOS_BANK[0] [33],QOSBW FIX QOS BANK0 Register 33" bitfld.quad 0x108 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x108 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x108 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x108 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x108 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x108 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x110 "QOSBW_FIX_QOS_BANK[0] [34],QOSBW FIX QOS BANK0 Register 34" bitfld.quad 0x110 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x110 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x110 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x110 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x110 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x110 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x118 "QOSBW_FIX_QOS_BANK[0] [35],QOSBW FIX QOS BANK0 Register 35" bitfld.quad 0x118 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x118 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x118 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x118 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x118 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x118 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x120 "QOSBW_FIX_QOS_BANK[0] [36],QOSBW FIX QOS BANK0 Register 36" bitfld.quad 0x120 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x120 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x120 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x120 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x120 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x120 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x128 "QOSBW_FIX_QOS_BANK[0] [37],QOSBW FIX QOS BANK0 Register 37" bitfld.quad 0x128 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x128 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x128 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x128 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x128 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x128 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x130 "QOSBW_FIX_QOS_BANK[0] [38],QOSBW FIX QOS BANK0 Register 38" bitfld.quad 0x130 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x130 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x130 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x130 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x130 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x130 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x138 "QOSBW_FIX_QOS_BANK[0] [39],QOSBW FIX QOS BANK0 Register 39" bitfld.quad 0x138 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x138 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x138 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x138 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x138 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x138 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x140 "QOSBW_FIX_QOS_BANK[0] [40],QOSBW FIX QOS BANK0 Register 40" bitfld.quad 0x140 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x140 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x140 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x140 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x140 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x140 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x148 "QOSBW_FIX_QOS_BANK[0] [41],QOSBW FIX QOS BANK0 Register 41" bitfld.quad 0x148 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x148 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x148 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x148 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x148 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x148 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x150 "QOSBW_FIX_QOS_BANK[0] [42],QOSBW FIX QOS BANK0 Register 42" bitfld.quad 0x150 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x150 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x150 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x150 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x150 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x150 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x158 "QOSBW_FIX_QOS_BANK[0] [43],QOSBW FIX QOS BANK0 Register 43" bitfld.quad 0x158 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x158 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x158 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x158 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x158 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x158 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x160 "QOSBW_FIX_QOS_BANK[0] [44],QOSBW FIX QOS BANK0 Register 44" bitfld.quad 0x160 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x160 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x160 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x160 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x160 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x160 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x168 "QOSBW_FIX_QOS_BANK[0] [45],QOSBW FIX QOS BANK0 Register 45" bitfld.quad 0x168 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x168 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x168 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x168 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x168 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x168 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x170 "QOSBW_FIX_QOS_BANK[0] [46],QOSBW FIX QOS BANK0 Register 46" bitfld.quad 0x170 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x170 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x170 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x170 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x170 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x170 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x178 "QOSBW_FIX_QOS_BANK[0] [47],QOSBW FIX QOS BANK0 Register 47" bitfld.quad 0x178 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x178 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x178 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x178 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x178 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x178 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x180 "QOSBW_FIX_QOS_BANK[0] [48],QOSBW FIX QOS BANK0 Register 48" bitfld.quad 0x180 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x180 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x180 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x180 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x180 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x180 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x188 "QOSBW_FIX_QOS_BANK[0] [49],QOSBW FIX QOS BANK0 Register 49" bitfld.quad 0x188 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x188 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x188 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x188 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x188 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x188 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x190 "QOSBW_FIX_QOS_BANK[0] [50],QOSBW FIX QOS BANK0 Register 50" bitfld.quad 0x190 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x190 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x190 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x190 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x190 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x190 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x198 "QOSBW_FIX_QOS_BANK[0] [51],QOSBW FIX QOS BANK0 Register 51" bitfld.quad 0x198 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x198 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x198 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x198 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x198 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x198 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1A0 "QOSBW_FIX_QOS_BANK[0] [52],QOSBW FIX QOS BANK0 Register 52" bitfld.quad 0x1A0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1A0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1A0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1A0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1A0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1A0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1A8 "QOSBW_FIX_QOS_BANK[0] [53],QOSBW FIX QOS BANK0 Register 53" bitfld.quad 0x1A8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1A8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1A8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1A8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1A8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1A8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1B0 "QOSBW_FIX_QOS_BANK[0] [54],QOSBW FIX QOS BANK0 Register 54" bitfld.quad 0x1B0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1B0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1B0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1B0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1B0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1B0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1B8 "QOSBW_FIX_QOS_BANK[0] [55],QOSBW FIX QOS BANK0 Register 55" bitfld.quad 0x1B8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1B8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1B8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1B8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1B8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1B8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1C0 "QOSBW_FIX_QOS_BANK[0] [56],QOSBW FIX QOS BANK0 Register 56" bitfld.quad 0x1C0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1C0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1C0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1C0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1C0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1C0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1C8 "QOSBW_FIX_QOS_BANK[0] [57],QOSBW FIX QOS BANK0 Register 57" bitfld.quad 0x1C8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1C8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1C8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1C8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1C8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1C8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1D0 "QOSBW_FIX_QOS_BANK[0] [58],QOSBW FIX QOS BANK0 Register 58" bitfld.quad 0x1D0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1D0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1D0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1D0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1D0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1D0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1D8 "QOSBW_FIX_QOS_BANK[0] [59],QOSBW FIX QOS BANK0 Register 59" bitfld.quad 0x1D8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1D8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1D8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1D8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1D8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1D8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1E0 "QOSBW_FIX_QOS_BANK[0] [60],QOSBW FIX QOS BANK0 Register 60" bitfld.quad 0x1E0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1E0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1E0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1E0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1E0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1E0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1E8 "QOSBW_FIX_QOS_BANK[0] [61],QOSBW FIX QOS BANK0 Register 61" bitfld.quad 0x1E8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1E8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1E8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1E8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1E8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1E8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1F0 "QOSBW_FIX_QOS_BANK[0] [62],QOSBW FIX QOS BANK0 Register 62" bitfld.quad 0x1F0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1F0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1F0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1F0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1F0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1F0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x1F8 "QOSBW_FIX_QOS_BANK[0] [63],QOSBW FIX QOS BANK0 Register 63" bitfld.quad 0x1F8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1F8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x1F8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x1F8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x1F8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x1F8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x200 "QOSBW_FIX_QOS_BANK[0] [64],QOSBW FIX QOS BANK0 Register 64" bitfld.quad 0x200 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x200 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x200 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x200 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x200 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x200 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x208 "QOSBW_FIX_QOS_BANK[0] [65],QOSBW FIX QOS BANK0 Register 65" bitfld.quad 0x208 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x208 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x208 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x208 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x208 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x208 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x210 "QOSBW_FIX_QOS_BANK[0] [66],QOSBW FIX QOS BANK0 Register 66" bitfld.quad 0x210 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x210 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x210 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x210 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x210 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x210 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x218 "QOSBW_FIX_QOS_BANK[0] [67],QOSBW FIX QOS BANK0 Register 67" bitfld.quad 0x218 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x218 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x218 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x218 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x218 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x218 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x220 "QOSBW_FIX_QOS_BANK[0] [68],QOSBW FIX QOS BANK0 Register 68" bitfld.quad 0x220 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x220 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x220 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x220 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x220 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x220 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x228 "QOSBW_FIX_QOS_BANK[0] [69],QOSBW FIX QOS BANK0 Register 69" bitfld.quad 0x228 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x228 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x228 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x228 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x228 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x228 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x230 "QOSBW_FIX_QOS_BANK[0] [70],QOSBW FIX QOS BANK0 Register 70" bitfld.quad 0x230 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x230 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x230 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x230 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x230 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x230 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x238 "QOSBW_FIX_QOS_BANK[0] [71],QOSBW FIX QOS BANK0 Register 71" bitfld.quad 0x238 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x238 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x238 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x238 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x238 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x238 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x240 "QOSBW_FIX_QOS_BANK[0] [72],QOSBW FIX QOS BANK0 Register 72" bitfld.quad 0x240 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x240 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x240 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x240 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x240 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x240 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x248 "QOSBW_FIX_QOS_BANK[0] [73],QOSBW FIX QOS BANK0 Register 73" bitfld.quad 0x248 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x248 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x248 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x248 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x248 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x248 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x250 "QOSBW_FIX_QOS_BANK[0] [74],QOSBW FIX QOS BANK0 Register 74" bitfld.quad 0x250 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x250 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x250 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x250 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x250 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x250 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x258 "QOSBW_FIX_QOS_BANK[0] [75],QOSBW FIX QOS BANK0 Register 75" bitfld.quad 0x258 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x258 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x258 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x258 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x258 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x258 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x260 "QOSBW_FIX_QOS_BANK[0] [76],QOSBW FIX QOS BANK0 Register 76" bitfld.quad 0x260 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x260 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x260 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x260 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x260 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x260 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x268 "QOSBW_FIX_QOS_BANK[0] [77],QOSBW FIX QOS BANK0 Register 77" bitfld.quad 0x268 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x268 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x268 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x268 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x268 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x268 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x270 "QOSBW_FIX_QOS_BANK[0] [78],QOSBW FIX QOS BANK0 Register 78" bitfld.quad 0x270 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x270 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x270 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x270 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x270 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x270 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x278 "QOSBW_FIX_QOS_BANK[0] [79],QOSBW FIX QOS BANK0 Register 79" bitfld.quad 0x278 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x278 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x278 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x278 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x278 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x278 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x280 "QOSBW_FIX_QOS_BANK[0] [80],QOSBW FIX QOS BANK0 Register 80" bitfld.quad 0x280 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x280 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x280 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x280 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x280 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x280 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x288 "QOSBW_FIX_QOS_BANK[0] [81],QOSBW FIX QOS BANK0 Register 81" bitfld.quad 0x288 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x288 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x288 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x288 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x288 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x288 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x290 "QOSBW_FIX_QOS_BANK[0] [82],QOSBW FIX QOS BANK0 Register 82" bitfld.quad 0x290 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x290 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x290 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x290 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x290 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x290 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x298 "QOSBW_FIX_QOS_BANK[0] [83],QOSBW FIX QOS BANK0 Register 83" bitfld.quad 0x298 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x298 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x298 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x298 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x298 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x298 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2A0 "QOSBW_FIX_QOS_BANK[0] [84],QOSBW FIX QOS BANK0 Register 84" bitfld.quad 0x2A0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2A0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2A0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2A0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2A0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2A0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2A8 "QOSBW_FIX_QOS_BANK[0] [85],QOSBW FIX QOS BANK0 Register 85" bitfld.quad 0x2A8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2A8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2A8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2A8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2A8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2A8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2B0 "QOSBW_FIX_QOS_BANK[0] [86],QOSBW FIX QOS BANK0 Register 86" bitfld.quad 0x2B0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2B0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2B0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2B0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2B0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2B0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2B8 "QOSBW_FIX_QOS_BANK[0] [87],QOSBW FIX QOS BANK0 Register 87" bitfld.quad 0x2B8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2B8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2B8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2B8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2B8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2B8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2C0 "QOSBW_FIX_QOS_BANK[0] [88],QOSBW FIX QOS BANK0 Register 88" bitfld.quad 0x2C0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2C0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2C0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2C0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2C0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2C0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2C8 "QOSBW_FIX_QOS_BANK[0] [89],QOSBW FIX QOS BANK0 Register 89" bitfld.quad 0x2C8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2C8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2C8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2C8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2C8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2C8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2D0 "QOSBW_FIX_QOS_BANK[0] [90],QOSBW FIX QOS BANK0 Register 90" bitfld.quad 0x2D0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2D0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2D0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2D0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2D0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2D0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2D8 "QOSBW_FIX_QOS_BANK[0] [91],QOSBW FIX QOS BANK0 Register 91" bitfld.quad 0x2D8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2D8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2D8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2D8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2D8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2D8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2E0 "QOSBW_FIX_QOS_BANK[0] [92],QOSBW FIX QOS BANK0 Register 92" bitfld.quad 0x2E0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2E0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2E0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2E0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2E0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2E0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2E8 "QOSBW_FIX_QOS_BANK[0] [93],QOSBW FIX QOS BANK0 Register 93" bitfld.quad 0x2E8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2E8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2E8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2E8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2E8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2E8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2F0 "QOSBW_FIX_QOS_BANK[0] [94],QOSBW FIX QOS BANK0 Register 94" bitfld.quad 0x2F0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2F0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2F0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2F0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2F0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2F0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x2F8 "QOSBW_FIX_QOS_BANK[0] [95],QOSBW FIX QOS BANK0 Register 95" bitfld.quad 0x2F8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2F8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x2F8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x2F8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x2F8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x2F8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x300 "QOSBW_FIX_QOS_BANK[0] [96],QOSBW FIX QOS BANK0 Register 96" bitfld.quad 0x300 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x300 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x300 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x300 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x300 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x300 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x308 "QOSBW_FIX_QOS_BANK[0] [97],QOSBW FIX QOS BANK0 Register 97" bitfld.quad 0x308 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x308 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x308 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x308 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x308 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x308 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x310 "QOSBW_FIX_QOS_BANK[0] [98],QOSBW FIX QOS BANK0 Register 98" bitfld.quad 0x310 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x310 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x310 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x310 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x310 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x310 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x318 "QOSBW_FIX_QOS_BANK[0] [99],QOSBW FIX QOS BANK0 Register 99" bitfld.quad 0x318 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x318 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x318 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x318 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x318 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x318 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x320 "QOSBW_FIX_QOS_BANK[0] [100],QOSBW FIX QOS BANK0 Register 100" bitfld.quad 0x320 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x320 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x320 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x320 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x320 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x320 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x328 "QOSBW_FIX_QOS_BANK[0] [101],QOSBW FIX QOS BANK0 Register 101" bitfld.quad 0x328 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x328 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x328 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x328 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x328 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x328 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x330 "QOSBW_FIX_QOS_BANK[0] [102],QOSBW FIX QOS BANK0 Register 102" bitfld.quad 0x330 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x330 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x330 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x330 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x330 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x330 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x338 "QOSBW_FIX_QOS_BANK[0] [103],QOSBW FIX QOS BANK0 Register 103" bitfld.quad 0x338 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x338 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x338 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x338 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x338 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x338 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x340 "QOSBW_FIX_QOS_BANK[0] [104],QOSBW FIX QOS BANK0 Register 104" bitfld.quad 0x340 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x340 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x340 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x340 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x340 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x340 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x348 "QOSBW_FIX_QOS_BANK[0] [105],QOSBW FIX QOS BANK0 Register 105" bitfld.quad 0x348 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x348 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x348 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x348 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x348 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x348 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x350 "QOSBW_FIX_QOS_BANK[0] [106],QOSBW FIX QOS BANK0 Register 106" bitfld.quad 0x350 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x350 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x350 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x350 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x350 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x350 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x358 "QOSBW_FIX_QOS_BANK[0] [107],QOSBW FIX QOS BANK0 Register 107" bitfld.quad 0x358 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x358 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x358 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x358 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x358 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x358 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x360 "QOSBW_FIX_QOS_BANK[0] [108],QOSBW FIX QOS BANK0 Register 108" bitfld.quad 0x360 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x360 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x360 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x360 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x360 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x360 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x368 "QOSBW_FIX_QOS_BANK[0] [109],QOSBW FIX QOS BANK0 Register 109" bitfld.quad 0x368 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x368 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x368 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x368 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x368 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x368 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x370 "QOSBW_FIX_QOS_BANK[0] [110],QOSBW FIX QOS BANK0 Register 110" bitfld.quad 0x370 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x370 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x370 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x370 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x370 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x370 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x378 "QOSBW_FIX_QOS_BANK[0] [111],QOSBW FIX QOS BANK0 Register 111" bitfld.quad 0x378 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x378 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x378 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x378 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x378 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x378 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x380 "QOSBW_FIX_QOS_BANK[0] [112],QOSBW FIX QOS BANK0 Register 112" bitfld.quad 0x380 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x380 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x380 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x380 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x380 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x380 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x388 "QOSBW_FIX_QOS_BANK[0] [113],QOSBW FIX QOS BANK0 Register 113" bitfld.quad 0x388 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x388 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x388 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x388 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x388 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x388 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x390 "QOSBW_FIX_QOS_BANK[0] [114],QOSBW FIX QOS BANK0 Register 114" bitfld.quad 0x390 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x390 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x390 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x390 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x390 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x390 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x398 "QOSBW_FIX_QOS_BANK[0] [115],QOSBW FIX QOS BANK0 Register 115" bitfld.quad 0x398 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x398 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x398 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x398 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x398 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x398 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3A0 "QOSBW_FIX_QOS_BANK[0] [116],QOSBW FIX QOS BANK0 Register 116" bitfld.quad 0x3A0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3A0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3A0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3A0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3A0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3A0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3A8 "QOSBW_FIX_QOS_BANK[0] [117],QOSBW FIX QOS BANK0 Register 117" bitfld.quad 0x3A8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3A8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3A8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3A8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3A8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3A8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3B0 "QOSBW_FIX_QOS_BANK[0] [118],QOSBW FIX QOS BANK0 Register 118" bitfld.quad 0x3B0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3B0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3B0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3B0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3B0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3B0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3B8 "QOSBW_FIX_QOS_BANK[0] [119],QOSBW FIX QOS BANK0 Register 119" bitfld.quad 0x3B8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3B8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3B8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3B8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3B8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3B8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3C0 "QOSBW_FIX_QOS_BANK[0] [120],QOSBW FIX QOS BANK0 Register 120" bitfld.quad 0x3C0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3C0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3C0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3C0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3C0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3C0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3C8 "QOSBW_FIX_QOS_BANK[0] [121],QOSBW FIX QOS BANK0 Register 121" bitfld.quad 0x3C8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3C8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3C8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3C8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3C8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3C8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3D0 "QOSBW_FIX_QOS_BANK[0] [122],QOSBW FIX QOS BANK0 Register 122" bitfld.quad 0x3D0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3D0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3D0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3D0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3D0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3D0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3D8 "QOSBW_FIX_QOS_BANK[0] [123],QOSBW FIX QOS BANK0 Register 123" bitfld.quad 0x3D8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3D8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3D8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3D8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3D8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3D8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3E0 "QOSBW_FIX_QOS_BANK[0] [124],QOSBW FIX QOS BANK0 Register 124" bitfld.quad 0x3E0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3E0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3E0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3E0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3E0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3E0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3E8 "QOSBW_FIX_QOS_BANK[0] [125],QOSBW FIX QOS BANK0 Register 125" bitfld.quad 0x3E8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3E8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3E8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3E8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3E8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3E8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3F0 "QOSBW_FIX_QOS_BANK[0] [126],QOSBW FIX QOS BANK0 Register 126" bitfld.quad 0x3F0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3F0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3F0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3F0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3F0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3F0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x3F8 "QOSBW_FIX_QOS_BANK[0] [127],QOSBW FIX QOS BANK0 Register 127" bitfld.quad 0x3F8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3F8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x3F8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x3F8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x3F8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x3F8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x400 "QOSBW_FIX_QOS_BANK[0] [128],QOSBW FIX QOS BANK0 Register 128" bitfld.quad 0x400 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x400 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x400 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x400 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x400 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x400 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x408 "QOSBW_FIX_QOS_BANK[0] [129],QOSBW FIX QOS BANK0 Register 129" bitfld.quad 0x408 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x408 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x408 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x408 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x408 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x408 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x410 "QOSBW_FIX_QOS_BANK[0] [130],QOSBW FIX QOS BANK0 Register 130" bitfld.quad 0x410 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x410 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x410 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x410 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x410 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x410 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x418 "QOSBW_FIX_QOS_BANK[0] [131],QOSBW FIX QOS BANK0 Register 131" bitfld.quad 0x418 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x418 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x418 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x418 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x418 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x418 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x420 "QOSBW_FIX_QOS_BANK[0] [132],QOSBW FIX QOS BANK0 Register 132" bitfld.quad 0x420 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x420 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x420 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x420 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x420 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x420 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x428 "QOSBW_FIX_QOS_BANK[0] [133],QOSBW FIX QOS BANK0 Register 133" bitfld.quad 0x428 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x428 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x428 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x428 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x428 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x428 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x430 "QOSBW_FIX_QOS_BANK[0] [134],QOSBW FIX QOS BANK0 Register 134" bitfld.quad 0x430 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x430 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x430 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x430 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x430 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x430 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x438 "QOSBW_FIX_QOS_BANK[0] [135],QOSBW FIX QOS BANK0 Register 135" bitfld.quad 0x438 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x438 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x438 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x438 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x438 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x438 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x440 "QOSBW_FIX_QOS_BANK[0] [136],QOSBW FIX QOS BANK0 Register 136" bitfld.quad 0x440 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x440 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x440 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x440 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x440 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x440 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x448 "QOSBW_FIX_QOS_BANK[0] [137],QOSBW FIX QOS BANK0 Register 137" bitfld.quad 0x448 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x448 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x448 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x448 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x448 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x448 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x450 "QOSBW_FIX_QOS_BANK[0] [138],QOSBW FIX QOS BANK0 Register 138" bitfld.quad 0x450 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x450 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x450 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x450 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x450 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x450 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x458 "QOSBW_FIX_QOS_BANK[0] [139],QOSBW FIX QOS BANK0 Register 139" bitfld.quad 0x458 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x458 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x458 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x458 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x458 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x458 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x460 "QOSBW_FIX_QOS_BANK[0] [140],QOSBW FIX QOS BANK0 Register 140" bitfld.quad 0x460 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x460 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x460 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x460 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x460 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x460 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x468 "QOSBW_FIX_QOS_BANK[0] [141],QOSBW FIX QOS BANK0 Register 141" bitfld.quad 0x468 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x468 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x468 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x468 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x468 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x468 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x470 "QOSBW_FIX_QOS_BANK[0] [142],QOSBW FIX QOS BANK0 Register 142" bitfld.quad 0x470 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x470 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x470 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x470 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x470 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x470 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x478 "QOSBW_FIX_QOS_BANK[0] [143],QOSBW FIX QOS BANK0 Register 143" bitfld.quad 0x478 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x478 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x478 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x478 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x478 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x478 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x480 "QOSBW_FIX_QOS_BANK[0] [144],QOSBW FIX QOS BANK0 Register 144" bitfld.quad 0x480 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x480 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x480 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x480 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x480 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x480 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x488 "QOSBW_FIX_QOS_BANK[0] [145],QOSBW FIX QOS BANK0 Register 145" bitfld.quad 0x488 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x488 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x488 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x488 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x488 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x488 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x490 "QOSBW_FIX_QOS_BANK[0] [146],QOSBW FIX QOS BANK0 Register 146" bitfld.quad 0x490 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x490 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x490 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x490 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x490 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x490 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x498 "QOSBW_FIX_QOS_BANK[0] [147],QOSBW FIX QOS BANK0 Register 147" bitfld.quad 0x498 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x498 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x498 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x498 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x498 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x498 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4A0 "QOSBW_FIX_QOS_BANK[0] [148],QOSBW FIX QOS BANK0 Register 148" bitfld.quad 0x4A0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4A0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4A0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4A0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4A0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4A0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4A8 "QOSBW_FIX_QOS_BANK[0] [149],QOSBW FIX QOS BANK0 Register 149" bitfld.quad 0x4A8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4A8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4A8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4A8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4A8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4A8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4B0 "QOSBW_FIX_QOS_BANK[0] [150],QOSBW FIX QOS BANK0 Register 150" bitfld.quad 0x4B0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4B0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4B0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4B0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4B0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4B0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4B8 "QOSBW_FIX_QOS_BANK[0] [151],QOSBW FIX QOS BANK0 Register 151" bitfld.quad 0x4B8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4B8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4B8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4B8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4B8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4B8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4C0 "QOSBW_FIX_QOS_BANK[0] [152],QOSBW FIX QOS BANK0 Register 152" bitfld.quad 0x4C0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4C0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4C0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4C0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4C0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4C0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4C8 "QOSBW_FIX_QOS_BANK[0] [153],QOSBW FIX QOS BANK0 Register 153" bitfld.quad 0x4C8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4C8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4C8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4C8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4C8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4C8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4D0 "QOSBW_FIX_QOS_BANK[0] [154],QOSBW FIX QOS BANK0 Register 154" bitfld.quad 0x4D0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4D0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4D0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4D0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4D0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4D0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4D8 "QOSBW_FIX_QOS_BANK[0] [155],QOSBW FIX QOS BANK0 Register 155" bitfld.quad 0x4D8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4D8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4D8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4D8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4D8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4D8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4E0 "QOSBW_FIX_QOS_BANK[0] [156],QOSBW FIX QOS BANK0 Register 156" bitfld.quad 0x4E0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4E0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4E0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4E0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4E0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4E0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4E8 "QOSBW_FIX_QOS_BANK[0] [157],QOSBW FIX QOS BANK0 Register 157" bitfld.quad 0x4E8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4E8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4E8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4E8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4E8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4E8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4F0 "QOSBW_FIX_QOS_BANK[0] [158],QOSBW FIX QOS BANK0 Register 158" bitfld.quad 0x4F0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4F0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4F0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4F0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4F0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4F0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x4F8 "QOSBW_FIX_QOS_BANK[0] [159],QOSBW FIX QOS BANK0 Register 159" bitfld.quad 0x4F8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4F8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x4F8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x4F8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x4F8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x4F8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x500 "QOSBW_FIX_QOS_BANK[0] [160],QOSBW FIX QOS BANK0 Register 160" bitfld.quad 0x500 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x500 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x500 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x500 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x500 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x500 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x508 "QOSBW_FIX_QOS_BANK[0] [161],QOSBW FIX QOS BANK0 Register 161" bitfld.quad 0x508 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x508 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x508 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x508 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x508 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x508 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x510 "QOSBW_FIX_QOS_BANK[0] [162],QOSBW FIX QOS BANK0 Register 162" bitfld.quad 0x510 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x510 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x510 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x510 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x510 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x510 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x518 "QOSBW_FIX_QOS_BANK[0] [163],QOSBW FIX QOS BANK0 Register 163" bitfld.quad 0x518 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x518 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x518 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x518 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x518 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x518 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x520 "QOSBW_FIX_QOS_BANK[0] [164],QOSBW FIX QOS BANK0 Register 164" bitfld.quad 0x520 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x520 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x520 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x520 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x520 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x520 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x528 "QOSBW_FIX_QOS_BANK[0] [165],QOSBW FIX QOS BANK0 Register 165" bitfld.quad 0x528 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x528 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x528 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x528 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x528 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x528 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x530 "QOSBW_FIX_QOS_BANK[0] [166],QOSBW FIX QOS BANK0 Register 166" bitfld.quad 0x530 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x530 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x530 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x530 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x530 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x530 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x538 "QOSBW_FIX_QOS_BANK[0] [167],QOSBW FIX QOS BANK0 Register 167" bitfld.quad 0x538 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x538 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x538 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x538 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x538 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x538 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x540 "QOSBW_FIX_QOS_BANK[0] [168],QOSBW FIX QOS BANK0 Register 168" bitfld.quad 0x540 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x540 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x540 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x540 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x540 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x540 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x548 "QOSBW_FIX_QOS_BANK[0] [169],QOSBW FIX QOS BANK0 Register 169" bitfld.quad 0x548 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x548 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x548 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x548 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x548 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x548 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x550 "QOSBW_FIX_QOS_BANK[0] [170],QOSBW FIX QOS BANK0 Register 170" bitfld.quad 0x550 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x550 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x550 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x550 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x550 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x550 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x558 "QOSBW_FIX_QOS_BANK[0] [171],QOSBW FIX QOS BANK0 Register 171" bitfld.quad 0x558 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x558 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x558 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x558 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x558 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x558 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x560 "QOSBW_FIX_QOS_BANK[0] [172],QOSBW FIX QOS BANK0 Register 172" bitfld.quad 0x560 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x560 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x560 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x560 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x560 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x560 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x568 "QOSBW_FIX_QOS_BANK[0] [173],QOSBW FIX QOS BANK0 Register 173" bitfld.quad 0x568 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x568 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x568 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x568 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x568 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x568 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x570 "QOSBW_FIX_QOS_BANK[0] [174],QOSBW FIX QOS BANK0 Register 174" bitfld.quad 0x570 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x570 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x570 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x570 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x570 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x570 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x578 "QOSBW_FIX_QOS_BANK[0] [175],QOSBW FIX QOS BANK0 Register 175" bitfld.quad 0x578 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x578 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x578 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x578 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x578 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x578 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x580 "QOSBW_FIX_QOS_BANK[0] [176],QOSBW FIX QOS BANK0 Register 176" bitfld.quad 0x580 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x580 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x580 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x580 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x580 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x580 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x588 "QOSBW_FIX_QOS_BANK[0] [177],QOSBW FIX QOS BANK0 Register 177" bitfld.quad 0x588 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x588 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x588 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x588 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x588 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x588 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x590 "QOSBW_FIX_QOS_BANK[0] [178],QOSBW FIX QOS BANK0 Register 178" bitfld.quad 0x590 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x590 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x590 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x590 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x590 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x590 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x598 "QOSBW_FIX_QOS_BANK[0] [179],QOSBW FIX QOS BANK0 Register 179" bitfld.quad 0x598 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x598 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x598 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x598 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x598 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x598 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5A0 "QOSBW_FIX_QOS_BANK[0] [180],QOSBW FIX QOS BANK0 Register 180" bitfld.quad 0x5A0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5A0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5A0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5A0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5A0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5A0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5A8 "QOSBW_FIX_QOS_BANK[0] [181],QOSBW FIX QOS BANK0 Register 181" bitfld.quad 0x5A8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5A8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5A8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5A8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5A8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5A8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5B0 "QOSBW_FIX_QOS_BANK[0] [182],QOSBW FIX QOS BANK0 Register 182" bitfld.quad 0x5B0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5B0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5B0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5B0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5B0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5B0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5B8 "QOSBW_FIX_QOS_BANK[0] [183],QOSBW FIX QOS BANK0 Register 183" bitfld.quad 0x5B8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5B8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5B8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5B8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5B8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5B8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5C0 "QOSBW_FIX_QOS_BANK[0] [184],QOSBW FIX QOS BANK0 Register 184" bitfld.quad 0x5C0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5C0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5C0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5C0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5C0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5C0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5C8 "QOSBW_FIX_QOS_BANK[0] [185],QOSBW FIX QOS BANK0 Register 185" bitfld.quad 0x5C8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5C8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5C8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5C8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5C8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5C8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5D0 "QOSBW_FIX_QOS_BANK[0] [186],QOSBW FIX QOS BANK0 Register 186" bitfld.quad 0x5D0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5D0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5D0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5D0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5D0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5D0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5D8 "QOSBW_FIX_QOS_BANK[0] [187],QOSBW FIX QOS BANK0 Register 187" bitfld.quad 0x5D8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5D8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5D8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5D8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5D8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5D8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5E0 "QOSBW_FIX_QOS_BANK[0] [188],QOSBW FIX QOS BANK0 Register 188" bitfld.quad 0x5E0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5E0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5E0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5E0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5E0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5E0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5E8 "QOSBW_FIX_QOS_BANK[0] [189],QOSBW FIX QOS BANK0 Register 189" bitfld.quad 0x5E8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5E8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5E8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5E8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5E8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5E8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5F0 "QOSBW_FIX_QOS_BANK[0] [190],QOSBW FIX QOS BANK0 Register 190" bitfld.quad 0x5F0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5F0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5F0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5F0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5F0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5F0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x5F8 "QOSBW_FIX_QOS_BANK[0] [191],QOSBW FIX QOS BANK0 Register 191" bitfld.quad 0x5F8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5F8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x5F8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x5F8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x5F8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x5F8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x600 "QOSBW_FIX_QOS_BANK[0] [192],QOSBW FIX QOS BANK0 Register 192" bitfld.quad 0x600 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x600 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x600 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x600 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x600 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x600 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x608 "QOSBW_FIX_QOS_BANK[0] [193],QOSBW FIX QOS BANK0 Register 193" bitfld.quad 0x608 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x608 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x608 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x608 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x608 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x608 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x610 "QOSBW_FIX_QOS_BANK[0] [194],QOSBW FIX QOS BANK0 Register 194" bitfld.quad 0x610 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x610 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x610 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x610 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x610 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x610 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x618 "QOSBW_FIX_QOS_BANK[0] [195],QOSBW FIX QOS BANK0 Register 195" bitfld.quad 0x618 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x618 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x618 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x618 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x618 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x618 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x620 "QOSBW_FIX_QOS_BANK[0] [196],QOSBW FIX QOS BANK0 Register 196" bitfld.quad 0x620 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x620 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x620 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x620 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x620 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x620 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x628 "QOSBW_FIX_QOS_BANK[0] [197],QOSBW FIX QOS BANK0 Register 197" bitfld.quad 0x628 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x628 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x628 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x628 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x628 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x628 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x630 "QOSBW_FIX_QOS_BANK[0] [198],QOSBW FIX QOS BANK0 Register 198" bitfld.quad 0x630 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x630 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x630 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x630 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x630 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x630 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x638 "QOSBW_FIX_QOS_BANK[0] [199],QOSBW FIX QOS BANK0 Register 199" bitfld.quad 0x638 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x638 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x638 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x638 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x638 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x638 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x640 "QOSBW_FIX_QOS_BANK[0] [200],QOSBW FIX QOS BANK0 Register 200" bitfld.quad 0x640 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x640 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x640 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x640 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x640 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x640 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x648 "QOSBW_FIX_QOS_BANK[0] [201],QOSBW FIX QOS BANK0 Register 201" bitfld.quad 0x648 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x648 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x648 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x648 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x648 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x648 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x650 "QOSBW_FIX_QOS_BANK[0] [202],QOSBW FIX QOS BANK0 Register 202" bitfld.quad 0x650 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x650 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x650 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x650 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x650 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x650 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x658 "QOSBW_FIX_QOS_BANK[0] [203],QOSBW FIX QOS BANK0 Register 203" bitfld.quad 0x658 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x658 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x658 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x658 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x658 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x658 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x660 "QOSBW_FIX_QOS_BANK[0] [204],QOSBW FIX QOS BANK0 Register 204" bitfld.quad 0x660 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x660 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x660 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x660 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x660 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x660 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x668 "QOSBW_FIX_QOS_BANK[0] [205],QOSBW FIX QOS BANK0 Register 205" bitfld.quad 0x668 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x668 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x668 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x668 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x668 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x668 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x670 "QOSBW_FIX_QOS_BANK[0] [206],QOSBW FIX QOS BANK0 Register 206" bitfld.quad 0x670 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x670 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x670 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x670 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x670 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x670 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x678 "QOSBW_FIX_QOS_BANK[0] [207],QOSBW FIX QOS BANK0 Register 207" bitfld.quad 0x678 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x678 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x678 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x678 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x678 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x678 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x680 "QOSBW_FIX_QOS_BANK[0] [208],QOSBW FIX QOS BANK0 Register 208" bitfld.quad 0x680 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x680 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x680 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x680 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x680 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x680 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x688 "QOSBW_FIX_QOS_BANK[0] [209],QOSBW FIX QOS BANK0 Register 209" bitfld.quad 0x688 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x688 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x688 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x688 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x688 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x688 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x690 "QOSBW_FIX_QOS_BANK[0] [210],QOSBW FIX QOS BANK0 Register 210" bitfld.quad 0x690 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x690 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x690 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x690 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x690 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x690 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x698 "QOSBW_FIX_QOS_BANK[0] [211],QOSBW FIX QOS BANK0 Register 211" bitfld.quad 0x698 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x698 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x698 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x698 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x698 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x698 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6A0 "QOSBW_FIX_QOS_BANK[0] [212],QOSBW FIX QOS BANK0 Register 212" bitfld.quad 0x6A0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6A0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6A0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6A0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6A0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6A0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6A8 "QOSBW_FIX_QOS_BANK[0] [213],QOSBW FIX QOS BANK0 Register 213" bitfld.quad 0x6A8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6A8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6A8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6A8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6A8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6A8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6B0 "QOSBW_FIX_QOS_BANK[0] [214],QOSBW FIX QOS BANK0 Register 214" bitfld.quad 0x6B0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6B0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6B0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6B0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6B0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6B0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6B8 "QOSBW_FIX_QOS_BANK[0] [215],QOSBW FIX QOS BANK0 Register 215" bitfld.quad 0x6B8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6B8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6B8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6B8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6B8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6B8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6C0 "QOSBW_FIX_QOS_BANK[0] [216],QOSBW FIX QOS BANK0 Register 216" bitfld.quad 0x6C0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6C0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6C0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6C0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6C0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6C0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6C8 "QOSBW_FIX_QOS_BANK[0] [217],QOSBW FIX QOS BANK0 Register 217" bitfld.quad 0x6C8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6C8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6C8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6C8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6C8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6C8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6D0 "QOSBW_FIX_QOS_BANK[0] [218],QOSBW FIX QOS BANK0 Register 218" bitfld.quad 0x6D0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6D0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6D0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6D0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6D0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6D0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6D8 "QOSBW_FIX_QOS_BANK[0] [219],QOSBW FIX QOS BANK0 Register 219" bitfld.quad 0x6D8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6D8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6D8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6D8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6D8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6D8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6E0 "QOSBW_FIX_QOS_BANK[0] [220],QOSBW FIX QOS BANK0 Register 220" bitfld.quad 0x6E0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6E0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6E0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6E0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6E0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6E0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6E8 "QOSBW_FIX_QOS_BANK[0] [221],QOSBW FIX QOS BANK0 Register 221" bitfld.quad 0x6E8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6E8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6E8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6E8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6E8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6E8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6F0 "QOSBW_FIX_QOS_BANK[0] [222],QOSBW FIX QOS BANK0 Register 222" bitfld.quad 0x6F0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6F0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6F0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6F0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6F0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6F0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x6F8 "QOSBW_FIX_QOS_BANK[0] [223],QOSBW FIX QOS BANK0 Register 223" bitfld.quad 0x6F8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6F8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x6F8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x6F8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x6F8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x6F8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x700 "QOSBW_FIX_QOS_BANK[0] [224],QOSBW FIX QOS BANK0 Register 224" bitfld.quad 0x700 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x700 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x700 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x700 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x700 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x700 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x708 "QOSBW_FIX_QOS_BANK[0] [225],QOSBW FIX QOS BANK0 Register 225" bitfld.quad 0x708 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x708 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x708 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x708 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x708 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x708 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x710 "QOSBW_FIX_QOS_BANK[0] [226],QOSBW FIX QOS BANK0 Register 226" bitfld.quad 0x710 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x710 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x710 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x710 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x710 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x710 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x718 "QOSBW_FIX_QOS_BANK[0] [227],QOSBW FIX QOS BANK0 Register 227" bitfld.quad 0x718 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x718 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x718 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x718 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x718 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x718 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x720 "QOSBW_FIX_QOS_BANK[0] [228],QOSBW FIX QOS BANK0 Register 228" bitfld.quad 0x720 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x720 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x720 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x720 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x720 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x720 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x728 "QOSBW_FIX_QOS_BANK[0] [229],QOSBW FIX QOS BANK0 Register 229" bitfld.quad 0x728 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x728 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x728 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x728 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x728 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x728 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x730 "QOSBW_FIX_QOS_BANK[0] [230],QOSBW FIX QOS BANK0 Register 230" bitfld.quad 0x730 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x730 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x730 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x730 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x730 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x730 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x738 "QOSBW_FIX_QOS_BANK[0] [231],QOSBW FIX QOS BANK0 Register 231" bitfld.quad 0x738 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x738 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x738 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x738 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x738 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x738 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x740 "QOSBW_FIX_QOS_BANK[0] [232],QOSBW FIX QOS BANK0 Register 232" bitfld.quad 0x740 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x740 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x740 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x740 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x740 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x740 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x748 "QOSBW_FIX_QOS_BANK[0] [233],QOSBW FIX QOS BANK0 Register 233" bitfld.quad 0x748 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x748 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x748 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x748 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x748 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x748 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x750 "QOSBW_FIX_QOS_BANK[0] [234],QOSBW FIX QOS BANK0 Register 234" bitfld.quad 0x750 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x750 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x750 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x750 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x750 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x750 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x758 "QOSBW_FIX_QOS_BANK[0] [235],QOSBW FIX QOS BANK0 Register 235" bitfld.quad 0x758 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x758 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x758 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x758 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x758 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x758 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x760 "QOSBW_FIX_QOS_BANK[0] [236],QOSBW FIX QOS BANK0 Register 236" bitfld.quad 0x760 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x760 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x760 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x760 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x760 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x760 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x768 "QOSBW_FIX_QOS_BANK[0] [237],QOSBW FIX QOS BANK0 Register 237" bitfld.quad 0x768 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x768 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x768 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x768 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x768 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x768 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x770 "QOSBW_FIX_QOS_BANK[0] [238],QOSBW FIX QOS BANK0 Register 238" bitfld.quad 0x770 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x770 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x770 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x770 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x770 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x770 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x778 "QOSBW_FIX_QOS_BANK[0] [239],QOSBW FIX QOS BANK0 Register 239" bitfld.quad 0x778 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x778 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x778 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x778 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x778 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x778 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x780 "QOSBW_FIX_QOS_BANK[0] [240],QOSBW FIX QOS BANK0 Register 240" bitfld.quad 0x780 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x780 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x780 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x780 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x780 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x780 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x788 "QOSBW_FIX_QOS_BANK[0] [241],QOSBW FIX QOS BANK0 Register 241" bitfld.quad 0x788 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x788 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x788 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x788 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x788 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x788 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x790 "QOSBW_FIX_QOS_BANK[0] [242],QOSBW FIX QOS BANK0 Register 242" bitfld.quad 0x790 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x790 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x790 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x790 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x790 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x790 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x798 "QOSBW_FIX_QOS_BANK[0] [243],QOSBW FIX QOS BANK0 Register 243" bitfld.quad 0x798 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x798 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x798 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x798 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x798 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x798 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7A0 "QOSBW_FIX_QOS_BANK[0] [244],QOSBW FIX QOS BANK0 Register 244" bitfld.quad 0x7A0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7A0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7A0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7A0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7A0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7A0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7A8 "QOSBW_FIX_QOS_BANK[0] [245],QOSBW FIX QOS BANK0 Register 245" bitfld.quad 0x7A8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7A8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7A8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7A8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7A8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7A8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7B0 "QOSBW_FIX_QOS_BANK[0] [246],QOSBW FIX QOS BANK0 Register 246" bitfld.quad 0x7B0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7B0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7B0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7B0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7B0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7B0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7B8 "QOSBW_FIX_QOS_BANK[0] [247],QOSBW FIX QOS BANK0 Register 247" bitfld.quad 0x7B8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7B8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7B8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7B8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7B8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7B8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7C0 "QOSBW_FIX_QOS_BANK[0] [248],QOSBW FIX QOS BANK0 Register 248" bitfld.quad 0x7C0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7C0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7C0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7C0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7C0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7C0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7C8 "QOSBW_FIX_QOS_BANK[0] [249],QOSBW FIX QOS BANK0 Register 249" bitfld.quad 0x7C8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7C8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7C8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7C8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7C8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7C8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7D0 "QOSBW_FIX_QOS_BANK[0] [250],QOSBW FIX QOS BANK0 Register 250" bitfld.quad 0x7D0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7D0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7D0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7D0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7D0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7D0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7D8 "QOSBW_FIX_QOS_BANK[0] [251],QOSBW FIX QOS BANK0 Register 251" bitfld.quad 0x7D8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7D8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7D8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7D8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7D8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7D8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7E0 "QOSBW_FIX_QOS_BANK[0] [252],QOSBW FIX QOS BANK0 Register 252" bitfld.quad 0x7E0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7E0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7E0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7E0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7E0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7E0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7E8 "QOSBW_FIX_QOS_BANK[0] [253],QOSBW FIX QOS BANK0 Register 253" bitfld.quad 0x7E8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7E8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7E8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7E8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7E8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7E8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7F0 "QOSBW_FIX_QOS_BANK[0] [254],QOSBW FIX QOS BANK0 Register 254" bitfld.quad 0x7F0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7F0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7F0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7F0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7F0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7F0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x7F8 "QOSBW_FIX_QOS_BANK[0] [255],QOSBW FIX QOS BANK0 Register 255" bitfld.quad 0x7F8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7F8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x7F8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x7F8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x7F8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x7F8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x800 "QOSBW_FIX_QOS_BANK[0] [256],QOSBW FIX QOS BANK0 Register 256" bitfld.quad 0x800 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x800 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x800 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x800 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x800 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x800 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x808 "QOSBW_FIX_QOS_BANK[0] [257],QOSBW FIX QOS BANK0 Register 257" bitfld.quad 0x808 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x808 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x808 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x808 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x808 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x808 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x810 "QOSBW_FIX_QOS_BANK[0] [258],QOSBW FIX QOS BANK0 Register 258" bitfld.quad 0x810 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x810 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x810 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x810 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x810 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x810 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x818 "QOSBW_FIX_QOS_BANK[0] [259],QOSBW FIX QOS BANK0 Register 259" bitfld.quad 0x818 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x818 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x818 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x818 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x818 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x818 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x820 "QOSBW_FIX_QOS_BANK[0] [260],QOSBW FIX QOS BANK0 Register 260" bitfld.quad 0x820 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x820 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x820 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x820 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x820 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x820 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x828 "QOSBW_FIX_QOS_BANK[0] [261],QOSBW FIX QOS BANK0 Register 261" bitfld.quad 0x828 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x828 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x828 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x828 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x828 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x828 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x830 "QOSBW_FIX_QOS_BANK[0] [262],QOSBW FIX QOS BANK0 Register 262" bitfld.quad 0x830 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x830 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x830 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x830 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x830 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x830 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x838 "QOSBW_FIX_QOS_BANK[0] [263],QOSBW FIX QOS BANK0 Register 263" bitfld.quad 0x838 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x838 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x838 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x838 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x838 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x838 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x840 "QOSBW_FIX_QOS_BANK[0] [264],QOSBW FIX QOS BANK0 Register 264" bitfld.quad 0x840 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x840 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x840 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x840 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x840 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x840 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x848 "QOSBW_FIX_QOS_BANK[0] [265],QOSBW FIX QOS BANK0 Register 265" bitfld.quad 0x848 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x848 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x848 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x848 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x848 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x848 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x850 "QOSBW_FIX_QOS_BANK[0] [266],QOSBW FIX QOS BANK0 Register 266" bitfld.quad 0x850 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x850 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x850 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x850 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x850 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x850 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x858 "QOSBW_FIX_QOS_BANK[0] [267],QOSBW FIX QOS BANK0 Register 267" bitfld.quad 0x858 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x858 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x858 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x858 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x858 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x858 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x860 "QOSBW_FIX_QOS_BANK[0] [268],QOSBW FIX QOS BANK0 Register 268" bitfld.quad 0x860 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x860 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x860 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x860 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x860 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x860 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x868 "QOSBW_FIX_QOS_BANK[0] [269],QOSBW FIX QOS BANK0 Register 269" bitfld.quad 0x868 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x868 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x868 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x868 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x868 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x868 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x870 "QOSBW_FIX_QOS_BANK[0] [270],QOSBW FIX QOS BANK0 Register 270" bitfld.quad 0x870 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x870 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x870 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x870 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x870 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x870 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x878 "QOSBW_FIX_QOS_BANK[0] [271],QOSBW FIX QOS BANK0 Register 271" bitfld.quad 0x878 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x878 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x878 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x878 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x878 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x878 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x880 "QOSBW_FIX_QOS_BANK[0] [272],QOSBW FIX QOS BANK0 Register 272" bitfld.quad 0x880 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x880 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x880 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x880 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x880 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x880 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x888 "QOSBW_FIX_QOS_BANK[0] [273],QOSBW FIX QOS BANK0 Register 273" bitfld.quad 0x888 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x888 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x888 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x888 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x888 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x888 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x890 "QOSBW_FIX_QOS_BANK[0] [274],QOSBW FIX QOS BANK0 Register 274" bitfld.quad 0x890 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x890 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x890 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x890 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x890 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x890 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x898 "QOSBW_FIX_QOS_BANK[0] [275],QOSBW FIX QOS BANK0 Register 275" bitfld.quad 0x898 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x898 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x898 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x898 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x898 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x898 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8A0 "QOSBW_FIX_QOS_BANK[0] [276],QOSBW FIX QOS BANK0 Register 276" bitfld.quad 0x8A0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8A0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8A0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8A0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8A0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8A0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8A8 "QOSBW_FIX_QOS_BANK[0] [277],QOSBW FIX QOS BANK0 Register 277" bitfld.quad 0x8A8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8A8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8A8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8A8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8A8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8A8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8B0 "QOSBW_FIX_QOS_BANK[0] [278],QOSBW FIX QOS BANK0 Register 278" bitfld.quad 0x8B0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8B0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8B0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8B0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8B0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8B0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8B8 "QOSBW_FIX_QOS_BANK[0] [279],QOSBW FIX QOS BANK0 Register 279" bitfld.quad 0x8B8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8B8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8B8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8B8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8B8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8B8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8C0 "QOSBW_FIX_QOS_BANK[0] [280],QOSBW FIX QOS BANK0 Register 280" bitfld.quad 0x8C0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8C0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8C0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8C0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8C0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8C0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8C8 "QOSBW_FIX_QOS_BANK[0] [281],QOSBW FIX QOS BANK0 Register 281" bitfld.quad 0x8C8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8C8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8C8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8C8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8C8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8C8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8D0 "QOSBW_FIX_QOS_BANK[0] [282],QOSBW FIX QOS BANK0 Register 282" bitfld.quad 0x8D0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8D0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8D0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8D0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8D0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8D0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8D8 "QOSBW_FIX_QOS_BANK[0] [283],QOSBW FIX QOS BANK0 Register 283" bitfld.quad 0x8D8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8D8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8D8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8D8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8D8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8D8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8E0 "QOSBW_FIX_QOS_BANK[0] [284],QOSBW FIX QOS BANK0 Register 284" bitfld.quad 0x8E0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8E0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8E0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8E0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8E0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8E0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8E8 "QOSBW_FIX_QOS_BANK[0] [285],QOSBW FIX QOS BANK0 Register 285" bitfld.quad 0x8E8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8E8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8E8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8E8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8E8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8E8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8F0 "QOSBW_FIX_QOS_BANK[0] [286],QOSBW FIX QOS BANK0 Register 286" bitfld.quad 0x8F0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8F0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8F0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8F0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8F0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8F0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x8F8 "QOSBW_FIX_QOS_BANK[0] [287],QOSBW FIX QOS BANK0 Register 287" bitfld.quad 0x8F8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8F8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x8F8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x8F8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x8F8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x8F8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x900 "QOSBW_FIX_QOS_BANK[0] [288],QOSBW FIX QOS BANK0 Register 288" bitfld.quad 0x900 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x900 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x900 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x900 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x900 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x900 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x908 "QOSBW_FIX_QOS_BANK[0] [289],QOSBW FIX QOS BANK0 Register 289" bitfld.quad 0x908 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x908 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x908 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x908 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x908 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x908 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x910 "QOSBW_FIX_QOS_BANK[0] [290],QOSBW FIX QOS BANK0 Register 290" bitfld.quad 0x910 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x910 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x910 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x910 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x910 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x910 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x918 "QOSBW_FIX_QOS_BANK[0] [291],QOSBW FIX QOS BANK0 Register 291" bitfld.quad 0x918 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x918 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x918 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x918 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x918 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x918 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x920 "QOSBW_FIX_QOS_BANK[0] [292],QOSBW FIX QOS BANK0 Register 292" bitfld.quad 0x920 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x920 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x920 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x920 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x920 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x920 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x928 "QOSBW_FIX_QOS_BANK[0] [293],QOSBW FIX QOS BANK0 Register 293" bitfld.quad 0x928 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x928 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x928 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x928 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x928 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x928 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x930 "QOSBW_FIX_QOS_BANK[0] [294],QOSBW FIX QOS BANK0 Register 294" bitfld.quad 0x930 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x930 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x930 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x930 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x930 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x930 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x938 "QOSBW_FIX_QOS_BANK[0] [295],QOSBW FIX QOS BANK0 Register 295" bitfld.quad 0x938 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x938 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x938 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x938 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x938 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x938 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x940 "QOSBW_FIX_QOS_BANK[0] [296],QOSBW FIX QOS BANK0 Register 296" bitfld.quad 0x940 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x940 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x940 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x940 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x940 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x940 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x948 "QOSBW_FIX_QOS_BANK[0] [297],QOSBW FIX QOS BANK0 Register 297" bitfld.quad 0x948 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x948 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x948 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x948 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x948 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x948 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x950 "QOSBW_FIX_QOS_BANK[0] [298],QOSBW FIX QOS BANK0 Register 298" bitfld.quad 0x950 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x950 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x950 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x950 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x950 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x950 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x958 "QOSBW_FIX_QOS_BANK[0] [299],QOSBW FIX QOS BANK0 Register 299" bitfld.quad 0x958 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x958 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x958 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x958 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x958 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x958 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x960 "QOSBW_FIX_QOS_BANK[0] [300],QOSBW FIX QOS BANK0 Register 300" bitfld.quad 0x960 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x960 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x960 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x960 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x960 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x960 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x968 "QOSBW_FIX_QOS_BANK[0] [301],QOSBW FIX QOS BANK0 Register 301" bitfld.quad 0x968 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x968 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x968 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x968 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x968 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x968 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x970 "QOSBW_FIX_QOS_BANK[0] [302],QOSBW FIX QOS BANK0 Register 302" bitfld.quad 0x970 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x970 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x970 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x970 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x970 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x970 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x978 "QOSBW_FIX_QOS_BANK[0] [303],QOSBW FIX QOS BANK0 Register 303" bitfld.quad 0x978 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x978 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x978 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x978 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x978 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x978 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x980 "QOSBW_FIX_QOS_BANK[0] [304],QOSBW FIX QOS BANK0 Register 304" bitfld.quad 0x980 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x980 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x980 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x980 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x980 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x980 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x988 "QOSBW_FIX_QOS_BANK[0] [305],QOSBW FIX QOS BANK0 Register 305" bitfld.quad 0x988 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x988 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x988 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x988 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x988 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x988 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x990 "QOSBW_FIX_QOS_BANK[0] [306],QOSBW FIX QOS BANK0 Register 306" bitfld.quad 0x990 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x990 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x990 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x990 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x990 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x990 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x998 "QOSBW_FIX_QOS_BANK[0] [307],QOSBW FIX QOS BANK0 Register 307" bitfld.quad 0x998 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x998 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x998 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x998 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x998 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x998 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9A0 "QOSBW_FIX_QOS_BANK[0] [308],QOSBW FIX QOS BANK0 Register 308" bitfld.quad 0x9A0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9A0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9A0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9A0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9A0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9A0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9A8 "QOSBW_FIX_QOS_BANK[0] [309],QOSBW FIX QOS BANK0 Register 309" bitfld.quad 0x9A8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9A8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9A8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9A8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9A8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9A8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9B0 "QOSBW_FIX_QOS_BANK[0] [310],QOSBW FIX QOS BANK0 Register 310" bitfld.quad 0x9B0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9B0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9B0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9B0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9B0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9B0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9B8 "QOSBW_FIX_QOS_BANK[0] [311],QOSBW FIX QOS BANK0 Register 311" bitfld.quad 0x9B8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9B8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9B8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9B8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9B8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9B8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9C0 "QOSBW_FIX_QOS_BANK[0] [312],QOSBW FIX QOS BANK0 Register 312" bitfld.quad 0x9C0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9C0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9C0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9C0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9C0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9C0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9C8 "QOSBW_FIX_QOS_BANK[0] [313],QOSBW FIX QOS BANK0 Register 313" bitfld.quad 0x9C8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9C8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9C8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9C8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9C8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9C8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9D0 "QOSBW_FIX_QOS_BANK[0] [314],QOSBW FIX QOS BANK0 Register 314" bitfld.quad 0x9D0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9D0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9D0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9D0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9D0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9D0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9D8 "QOSBW_FIX_QOS_BANK[0] [315],QOSBW FIX QOS BANK0 Register 315" bitfld.quad 0x9D8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9D8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9D8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9D8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9D8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9D8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9E0 "QOSBW_FIX_QOS_BANK[0] [316],QOSBW FIX QOS BANK0 Register 316" bitfld.quad 0x9E0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9E0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9E0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9E0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9E0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9E0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9E8 "QOSBW_FIX_QOS_BANK[0] [317],QOSBW FIX QOS BANK0 Register 317" bitfld.quad 0x9E8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9E8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9E8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9E8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9E8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9E8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9F0 "QOSBW_FIX_QOS_BANK[0] [318],QOSBW FIX QOS BANK0 Register 318" bitfld.quad 0x9F0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9F0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9F0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9F0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9F0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9F0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0x9F8 "QOSBW_FIX_QOS_BANK[0] [319],QOSBW FIX QOS BANK0 Register 319" bitfld.quad 0x9F8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9F8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0x9F8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0x9F8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0x9F8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0x9F8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA00 "QOSBW_FIX_QOS_BANK[0] [320],QOSBW FIX QOS BANK0 Register 320" bitfld.quad 0xA00 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA00 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA00 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA00 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA00 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA00 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA08 "QOSBW_FIX_QOS_BANK[0] [321],QOSBW FIX QOS BANK0 Register 321" bitfld.quad 0xA08 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA08 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA08 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA08 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA08 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA08 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA10 "QOSBW_FIX_QOS_BANK[0] [322],QOSBW FIX QOS BANK0 Register 322" bitfld.quad 0xA10 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA10 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA10 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA10 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA10 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA10 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA18 "QOSBW_FIX_QOS_BANK[0] [323],QOSBW FIX QOS BANK0 Register 323" bitfld.quad 0xA18 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA18 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA18 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA18 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA18 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA18 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA20 "QOSBW_FIX_QOS_BANK[0] [324],QOSBW FIX QOS BANK0 Register 324" bitfld.quad 0xA20 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA20 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA20 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA20 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA20 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA20 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA28 "QOSBW_FIX_QOS_BANK[0] [325],QOSBW FIX QOS BANK0 Register 325" bitfld.quad 0xA28 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA28 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA28 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA28 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA28 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA28 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA30 "QOSBW_FIX_QOS_BANK[0] [326],QOSBW FIX QOS BANK0 Register 326" bitfld.quad 0xA30 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA30 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA30 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA30 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA30 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA30 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA38 "QOSBW_FIX_QOS_BANK[0] [327],QOSBW FIX QOS BANK0 Register 327" bitfld.quad 0xA38 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA38 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA38 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA38 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA38 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA38 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA40 "QOSBW_FIX_QOS_BANK[0] [328],QOSBW FIX QOS BANK0 Register 328" bitfld.quad 0xA40 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA40 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA40 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA40 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA40 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA40 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA48 "QOSBW_FIX_QOS_BANK[0] [329],QOSBW FIX QOS BANK0 Register 329" bitfld.quad 0xA48 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA48 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA48 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA48 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA48 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA48 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA50 "QOSBW_FIX_QOS_BANK[0] [330],QOSBW FIX QOS BANK0 Register 330" bitfld.quad 0xA50 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA50 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA50 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA50 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA50 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA50 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA58 "QOSBW_FIX_QOS_BANK[0] [331],QOSBW FIX QOS BANK0 Register 331" bitfld.quad 0xA58 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA58 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA58 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA58 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA58 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA58 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA60 "QOSBW_FIX_QOS_BANK[0] [332],QOSBW FIX QOS BANK0 Register 332" bitfld.quad 0xA60 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA60 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA60 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA60 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA60 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA60 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA68 "QOSBW_FIX_QOS_BANK[0] [333],QOSBW FIX QOS BANK0 Register 333" bitfld.quad 0xA68 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA68 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA68 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA68 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA68 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA68 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA70 "QOSBW_FIX_QOS_BANK[0] [334],QOSBW FIX QOS BANK0 Register 334" bitfld.quad 0xA70 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA70 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA70 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA70 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA70 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA70 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA78 "QOSBW_FIX_QOS_BANK[0] [335],QOSBW FIX QOS BANK0 Register 335" bitfld.quad 0xA78 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA78 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA78 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA78 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA78 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA78 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA80 "QOSBW_FIX_QOS_BANK[0] [336],QOSBW FIX QOS BANK0 Register 336" bitfld.quad 0xA80 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA80 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA80 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA80 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA80 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA80 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA88 "QOSBW_FIX_QOS_BANK[0] [337],QOSBW FIX QOS BANK0 Register 337" bitfld.quad 0xA88 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA88 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA88 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA88 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA88 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA88 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA90 "QOSBW_FIX_QOS_BANK[0] [338],QOSBW FIX QOS BANK0 Register 338" bitfld.quad 0xA90 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA90 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA90 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA90 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA90 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA90 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xA98 "QOSBW_FIX_QOS_BANK[0] [339],QOSBW FIX QOS BANK0 Register 339" bitfld.quad 0xA98 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA98 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xA98 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xA98 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xA98 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xA98 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAA0 "QOSBW_FIX_QOS_BANK[0] [340],QOSBW FIX QOS BANK0 Register 340" bitfld.quad 0xAA0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAA0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAA0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAA0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAA0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAA0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAA8 "QOSBW_FIX_QOS_BANK[0] [341],QOSBW FIX QOS BANK0 Register 341" bitfld.quad 0xAA8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAA8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAA8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAA8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAA8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAA8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAB0 "QOSBW_FIX_QOS_BANK[0] [342],QOSBW FIX QOS BANK0 Register 342" bitfld.quad 0xAB0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAB0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAB0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAB0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAB0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAB0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAB8 "QOSBW_FIX_QOS_BANK[0] [343],QOSBW FIX QOS BANK0 Register 343" bitfld.quad 0xAB8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAB8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAB8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAB8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAB8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAB8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAC0 "QOSBW_FIX_QOS_BANK[0] [344],QOSBW FIX QOS BANK0 Register 344" bitfld.quad 0xAC0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAC0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAC0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAC0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAC0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAC0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAC8 "QOSBW_FIX_QOS_BANK[0] [345],QOSBW FIX QOS BANK0 Register 345" bitfld.quad 0xAC8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAC8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAC8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAC8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAC8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAC8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAD0 "QOSBW_FIX_QOS_BANK[0] [346],QOSBW FIX QOS BANK0 Register 346" bitfld.quad 0xAD0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAD0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAD0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAD0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAD0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAD0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAD8 "QOSBW_FIX_QOS_BANK[0] [347],QOSBW FIX QOS BANK0 Register 347" bitfld.quad 0xAD8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAD8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAD8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAD8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAD8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAD8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAE0 "QOSBW_FIX_QOS_BANK[0] [348],QOSBW FIX QOS BANK0 Register 348" bitfld.quad 0xAE0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAE0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAE0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAE0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAE0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAE0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAE8 "QOSBW_FIX_QOS_BANK[0] [349],QOSBW FIX QOS BANK0 Register 349" bitfld.quad 0xAE8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAE8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAE8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAE8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAE8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAE8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAF0 "QOSBW_FIX_QOS_BANK[0] [350],QOSBW FIX QOS BANK0 Register 350" bitfld.quad 0xAF0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAF0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAF0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAF0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAF0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAF0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xAF8 "QOSBW_FIX_QOS_BANK[0] [351],QOSBW FIX QOS BANK0 Register 351" bitfld.quad 0xAF8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAF8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xAF8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xAF8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xAF8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xAF8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB00 "QOSBW_FIX_QOS_BANK[0] [352],QOSBW FIX QOS BANK0 Register 352" bitfld.quad 0xB00 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB00 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB00 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB00 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB00 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB00 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB08 "QOSBW_FIX_QOS_BANK[0] [353],QOSBW FIX QOS BANK0 Register 353" bitfld.quad 0xB08 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB08 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB08 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB08 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB08 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB08 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB10 "QOSBW_FIX_QOS_BANK[0] [354],QOSBW FIX QOS BANK0 Register 354" bitfld.quad 0xB10 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB10 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB10 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB10 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB10 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB10 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB18 "QOSBW_FIX_QOS_BANK[0] [355],QOSBW FIX QOS BANK0 Register 355" bitfld.quad 0xB18 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB18 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB18 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB18 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB18 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB18 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB20 "QOSBW_FIX_QOS_BANK[0] [356],QOSBW FIX QOS BANK0 Register 356" bitfld.quad 0xB20 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB20 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB20 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB20 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB20 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB20 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB28 "QOSBW_FIX_QOS_BANK[0] [357],QOSBW FIX QOS BANK0 Register 357" bitfld.quad 0xB28 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB28 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB28 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB28 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB28 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB28 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB30 "QOSBW_FIX_QOS_BANK[0] [358],QOSBW FIX QOS BANK0 Register 358" bitfld.quad 0xB30 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB30 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB30 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB30 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB30 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB30 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB38 "QOSBW_FIX_QOS_BANK[0] [359],QOSBW FIX QOS BANK0 Register 359" bitfld.quad 0xB38 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB38 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB38 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB38 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB38 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB38 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB40 "QOSBW_FIX_QOS_BANK[0] [360],QOSBW FIX QOS BANK0 Register 360" bitfld.quad 0xB40 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB40 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB40 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB40 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB40 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB40 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB48 "QOSBW_FIX_QOS_BANK[0] [361],QOSBW FIX QOS BANK0 Register 361" bitfld.quad 0xB48 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB48 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB48 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB48 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB48 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB48 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB50 "QOSBW_FIX_QOS_BANK[0] [362],QOSBW FIX QOS BANK0 Register 362" bitfld.quad 0xB50 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB50 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB50 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB50 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB50 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB50 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB58 "QOSBW_FIX_QOS_BANK[0] [363],QOSBW FIX QOS BANK0 Register 363" bitfld.quad 0xB58 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB58 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB58 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB58 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB58 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB58 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB60 "QOSBW_FIX_QOS_BANK[0] [364],QOSBW FIX QOS BANK0 Register 364" bitfld.quad 0xB60 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB60 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB60 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB60 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB60 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB60 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB68 "QOSBW_FIX_QOS_BANK[0] [365],QOSBW FIX QOS BANK0 Register 365" bitfld.quad 0xB68 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB68 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB68 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB68 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB68 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB68 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB70 "QOSBW_FIX_QOS_BANK[0] [366],QOSBW FIX QOS BANK0 Register 366" bitfld.quad 0xB70 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB70 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB70 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB70 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB70 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB70 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB78 "QOSBW_FIX_QOS_BANK[0] [367],QOSBW FIX QOS BANK0 Register 367" bitfld.quad 0xB78 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB78 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB78 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB78 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB78 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB78 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB80 "QOSBW_FIX_QOS_BANK[0] [368],QOSBW FIX QOS BANK0 Register 368" bitfld.quad 0xB80 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB80 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB80 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB80 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB80 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB80 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB88 "QOSBW_FIX_QOS_BANK[0] [369],QOSBW FIX QOS BANK0 Register 369" bitfld.quad 0xB88 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB88 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB88 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB88 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB88 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB88 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB90 "QOSBW_FIX_QOS_BANK[0] [370],QOSBW FIX QOS BANK0 Register 370" bitfld.quad 0xB90 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB90 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB90 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB90 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB90 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB90 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xB98 "QOSBW_FIX_QOS_BANK[0] [371],QOSBW FIX QOS BANK0 Register 371" bitfld.quad 0xB98 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB98 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xB98 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xB98 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xB98 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xB98 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBA0 "QOSBW_FIX_QOS_BANK[0] [372],QOSBW FIX QOS BANK0 Register 372" bitfld.quad 0xBA0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBA0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBA0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBA0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBA0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBA0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBA8 "QOSBW_FIX_QOS_BANK[0] [373],QOSBW FIX QOS BANK0 Register 373" bitfld.quad 0xBA8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBA8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBA8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBA8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBA8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBA8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBB0 "QOSBW_FIX_QOS_BANK[0] [374],QOSBW FIX QOS BANK0 Register 374" bitfld.quad 0xBB0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBB0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBB0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBB0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBB0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBB0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBB8 "QOSBW_FIX_QOS_BANK[0] [375],QOSBW FIX QOS BANK0 Register 375" bitfld.quad 0xBB8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBB8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBB8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBB8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBB8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBB8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBC0 "QOSBW_FIX_QOS_BANK[0] [376],QOSBW FIX QOS BANK0 Register 376" bitfld.quad 0xBC0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBC0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBC0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBC0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBC0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBC0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBC8 "QOSBW_FIX_QOS_BANK[0] [377],QOSBW FIX QOS BANK0 Register 377" bitfld.quad 0xBC8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBC8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBC8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBC8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBC8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBC8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBD0 "QOSBW_FIX_QOS_BANK[0] [378],QOSBW FIX QOS BANK0 Register 378" bitfld.quad 0xBD0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBD0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBD0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBD0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBD0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBD0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBD8 "QOSBW_FIX_QOS_BANK[0] [379],QOSBW FIX QOS BANK0 Register 379" bitfld.quad 0xBD8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBD8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBD8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBD8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBD8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBD8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBE0 "QOSBW_FIX_QOS_BANK[0] [380],QOSBW FIX QOS BANK0 Register 380" bitfld.quad 0xBE0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBE0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBE0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBE0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBE0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBE0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBE8 "QOSBW_FIX_QOS_BANK[0] [381],QOSBW FIX QOS BANK0 Register 381" bitfld.quad 0xBE8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBE8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBE8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBE8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBE8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBE8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBF0 "QOSBW_FIX_QOS_BANK[0] [382],QOSBW FIX QOS BANK0 Register 382" bitfld.quad 0xBF0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBF0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBF0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBF0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBF0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBF0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xBF8 "QOSBW_FIX_QOS_BANK[0] [383],QOSBW FIX QOS BANK0 Register 383" bitfld.quad 0xBF8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBF8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xBF8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xBF8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xBF8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xBF8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC00 "QOSBW_FIX_QOS_BANK[0] [384],QOSBW FIX QOS BANK0 Register 384" bitfld.quad 0xC00 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC00 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC00 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC00 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC00 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC00 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC08 "QOSBW_FIX_QOS_BANK[0] [385],QOSBW FIX QOS BANK0 Register 385" bitfld.quad 0xC08 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC08 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC08 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC08 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC08 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC08 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC10 "QOSBW_FIX_QOS_BANK[0] [386],QOSBW FIX QOS BANK0 Register 386" bitfld.quad 0xC10 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC10 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC10 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC10 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC10 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC10 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC18 "QOSBW_FIX_QOS_BANK[0] [387],QOSBW FIX QOS BANK0 Register 387" bitfld.quad 0xC18 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC18 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC18 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC18 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC18 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC18 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC20 "QOSBW_FIX_QOS_BANK[0] [388],QOSBW FIX QOS BANK0 Register 388" bitfld.quad 0xC20 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC20 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC20 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC20 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC20 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC20 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC28 "QOSBW_FIX_QOS_BANK[0] [389],QOSBW FIX QOS BANK0 Register 389" bitfld.quad 0xC28 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC28 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC28 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC28 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC28 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC28 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC30 "QOSBW_FIX_QOS_BANK[0] [390],QOSBW FIX QOS BANK0 Register 390" bitfld.quad 0xC30 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC30 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC30 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC30 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC30 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC30 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC38 "QOSBW_FIX_QOS_BANK[0] [391],QOSBW FIX QOS BANK0 Register 391" bitfld.quad 0xC38 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC38 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC38 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC38 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC38 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC38 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC40 "QOSBW_FIX_QOS_BANK[0] [392],QOSBW FIX QOS BANK0 Register 392" bitfld.quad 0xC40 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC40 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC40 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC40 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC40 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC40 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC48 "QOSBW_FIX_QOS_BANK[0] [393],QOSBW FIX QOS BANK0 Register 393" bitfld.quad 0xC48 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC48 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC48 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC48 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC48 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC48 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC50 "QOSBW_FIX_QOS_BANK[0] [394],QOSBW FIX QOS BANK0 Register 394" bitfld.quad 0xC50 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC50 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC50 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC50 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC50 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC50 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC58 "QOSBW_FIX_QOS_BANK[0] [395],QOSBW FIX QOS BANK0 Register 395" bitfld.quad 0xC58 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC58 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC58 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC58 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC58 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC58 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC60 "QOSBW_FIX_QOS_BANK[0] [396],QOSBW FIX QOS BANK0 Register 396" bitfld.quad 0xC60 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC60 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC60 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC60 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC60 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC60 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC68 "QOSBW_FIX_QOS_BANK[0] [397],QOSBW FIX QOS BANK0 Register 397" bitfld.quad 0xC68 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC68 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC68 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC68 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC68 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC68 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC70 "QOSBW_FIX_QOS_BANK[0] [398],QOSBW FIX QOS BANK0 Register 398" bitfld.quad 0xC70 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC70 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC70 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC70 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC70 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC70 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC78 "QOSBW_FIX_QOS_BANK[0] [399],QOSBW FIX QOS BANK0 Register 399" bitfld.quad 0xC78 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC78 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC78 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC78 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC78 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC78 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC80 "QOSBW_FIX_QOS_BANK[0] [400],QOSBW FIX QOS BANK0 Register 400" bitfld.quad 0xC80 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC80 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC80 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC80 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC80 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC80 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC88 "QOSBW_FIX_QOS_BANK[0] [401],QOSBW FIX QOS BANK0 Register 401" bitfld.quad 0xC88 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC88 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC88 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC88 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC88 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC88 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC90 "QOSBW_FIX_QOS_BANK[0] [402],QOSBW FIX QOS BANK0 Register 402" bitfld.quad 0xC90 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC90 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC90 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC90 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC90 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC90 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xC98 "QOSBW_FIX_QOS_BANK[0] [403],QOSBW FIX QOS BANK0 Register 403" bitfld.quad 0xC98 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC98 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xC98 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xC98 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xC98 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xC98 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCA0 "QOSBW_FIX_QOS_BANK[0] [404],QOSBW FIX QOS BANK0 Register 404" bitfld.quad 0xCA0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCA0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCA0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCA0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCA0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCA0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCA8 "QOSBW_FIX_QOS_BANK[0] [405],QOSBW FIX QOS BANK0 Register 405" bitfld.quad 0xCA8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCA8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCA8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCA8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCA8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCA8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCB0 "QOSBW_FIX_QOS_BANK[0] [406],QOSBW FIX QOS BANK0 Register 406" bitfld.quad 0xCB0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCB0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCB0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCB0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCB0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCB0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCB8 "QOSBW_FIX_QOS_BANK[0] [407],QOSBW FIX QOS BANK0 Register 407" bitfld.quad 0xCB8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCB8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCB8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCB8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCB8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCB8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCC0 "QOSBW_FIX_QOS_BANK[0] [408],QOSBW FIX QOS BANK0 Register 408" bitfld.quad 0xCC0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCC0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCC0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCC0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCC0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCC0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCC8 "QOSBW_FIX_QOS_BANK[0] [409],QOSBW FIX QOS BANK0 Register 409" bitfld.quad 0xCC8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCC8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCC8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCC8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCC8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCC8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCD0 "QOSBW_FIX_QOS_BANK[0] [410],QOSBW FIX QOS BANK0 Register 410" bitfld.quad 0xCD0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCD0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCD0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCD0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCD0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCD0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCD8 "QOSBW_FIX_QOS_BANK[0] [411],QOSBW FIX QOS BANK0 Register 411" bitfld.quad 0xCD8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCD8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCD8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCD8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCD8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCD8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCE0 "QOSBW_FIX_QOS_BANK[0] [412],QOSBW FIX QOS BANK0 Register 412" bitfld.quad 0xCE0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCE0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCE0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCE0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCE0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCE0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCE8 "QOSBW_FIX_QOS_BANK[0] [413],QOSBW FIX QOS BANK0 Register 413" bitfld.quad 0xCE8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCE8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCE8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCE8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCE8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCE8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCF0 "QOSBW_FIX_QOS_BANK[0] [414],QOSBW FIX QOS BANK0 Register 414" bitfld.quad 0xCF0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCF0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCF0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCF0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCF0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCF0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xCF8 "QOSBW_FIX_QOS_BANK[0] [415],QOSBW FIX QOS BANK0 Register 415" bitfld.quad 0xCF8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCF8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xCF8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xCF8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xCF8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xCF8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD00 "QOSBW_FIX_QOS_BANK[0] [416],QOSBW FIX QOS BANK0 Register 416" bitfld.quad 0xD00 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD00 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD00 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD00 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD00 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD00 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD08 "QOSBW_FIX_QOS_BANK[0] [417],QOSBW FIX QOS BANK0 Register 417" bitfld.quad 0xD08 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD08 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD08 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD08 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD08 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD08 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD10 "QOSBW_FIX_QOS_BANK[0] [418],QOSBW FIX QOS BANK0 Register 418" bitfld.quad 0xD10 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD10 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD10 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD10 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD10 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD10 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD18 "QOSBW_FIX_QOS_BANK[0] [419],QOSBW FIX QOS BANK0 Register 419" bitfld.quad 0xD18 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD18 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD18 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD18 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD18 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD18 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD20 "QOSBW_FIX_QOS_BANK[0] [420],QOSBW FIX QOS BANK0 Register 420" bitfld.quad 0xD20 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD20 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD20 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD20 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD20 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD20 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD28 "QOSBW_FIX_QOS_BANK[0] [421],QOSBW FIX QOS BANK0 Register 421" bitfld.quad 0xD28 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD28 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD28 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD28 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD28 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD28 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD30 "QOSBW_FIX_QOS_BANK[0] [422],QOSBW FIX QOS BANK0 Register 422" bitfld.quad 0xD30 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD30 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD30 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD30 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD30 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD30 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD38 "QOSBW_FIX_QOS_BANK[0] [423],QOSBW FIX QOS BANK0 Register 423" bitfld.quad 0xD38 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD38 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD38 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD38 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD38 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD38 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD40 "QOSBW_FIX_QOS_BANK[0] [424],QOSBW FIX QOS BANK0 Register 424" bitfld.quad 0xD40 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD40 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD40 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD40 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD40 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD40 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD48 "QOSBW_FIX_QOS_BANK[0] [425],QOSBW FIX QOS BANK0 Register 425" bitfld.quad 0xD48 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD48 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD48 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD48 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD48 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD48 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD50 "QOSBW_FIX_QOS_BANK[0] [426],QOSBW FIX QOS BANK0 Register 426" bitfld.quad 0xD50 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD50 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD50 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD50 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD50 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD50 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD58 "QOSBW_FIX_QOS_BANK[0] [427],QOSBW FIX QOS BANK0 Register 427" bitfld.quad 0xD58 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD58 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD58 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD58 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD58 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD58 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD60 "QOSBW_FIX_QOS_BANK[0] [428],QOSBW FIX QOS BANK0 Register 428" bitfld.quad 0xD60 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD60 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD60 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD60 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD60 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD60 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD68 "QOSBW_FIX_QOS_BANK[0] [429],QOSBW FIX QOS BANK0 Register 429" bitfld.quad 0xD68 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD68 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD68 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD68 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD68 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD68 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD70 "QOSBW_FIX_QOS_BANK[0] [430],QOSBW FIX QOS BANK0 Register 430" bitfld.quad 0xD70 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD70 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD70 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD70 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD70 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD70 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD78 "QOSBW_FIX_QOS_BANK[0] [431],QOSBW FIX QOS BANK0 Register 431" bitfld.quad 0xD78 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD78 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD78 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD78 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD78 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD78 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD80 "QOSBW_FIX_QOS_BANK[0] [432],QOSBW FIX QOS BANK0 Register 432" bitfld.quad 0xD80 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD80 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD80 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD80 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD80 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD80 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD88 "QOSBW_FIX_QOS_BANK[0] [433],QOSBW FIX QOS BANK0 Register 433" bitfld.quad 0xD88 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD88 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD88 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD88 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD88 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD88 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD90 "QOSBW_FIX_QOS_BANK[0] [434],QOSBW FIX QOS BANK0 Register 434" bitfld.quad 0xD90 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD90 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD90 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD90 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD90 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD90 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xD98 "QOSBW_FIX_QOS_BANK[0] [435],QOSBW FIX QOS BANK0 Register 435" bitfld.quad 0xD98 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD98 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xD98 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xD98 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xD98 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xD98 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDA0 "QOSBW_FIX_QOS_BANK[0] [436],QOSBW FIX QOS BANK0 Register 436" bitfld.quad 0xDA0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDA0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDA0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDA0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDA0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDA0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDA8 "QOSBW_FIX_QOS_BANK[0] [437],QOSBW FIX QOS BANK0 Register 437" bitfld.quad 0xDA8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDA8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDA8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDA8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDA8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDA8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDB0 "QOSBW_FIX_QOS_BANK[0] [438],QOSBW FIX QOS BANK0 Register 438" bitfld.quad 0xDB0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDB0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDB0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDB0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDB0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDB0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDB8 "QOSBW_FIX_QOS_BANK[0] [439],QOSBW FIX QOS BANK0 Register 439" bitfld.quad 0xDB8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDB8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDB8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDB8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDB8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDB8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDC0 "QOSBW_FIX_QOS_BANK[0] [440],QOSBW FIX QOS BANK0 Register 440" bitfld.quad 0xDC0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDC0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDC0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDC0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDC0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDC0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDC8 "QOSBW_FIX_QOS_BANK[0] [441],QOSBW FIX QOS BANK0 Register 441" bitfld.quad 0xDC8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDC8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDC8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDC8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDC8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDC8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDD0 "QOSBW_FIX_QOS_BANK[0] [442],QOSBW FIX QOS BANK0 Register 442" bitfld.quad 0xDD0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDD0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDD0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDD0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDD0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDD0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDD8 "QOSBW_FIX_QOS_BANK[0] [443],QOSBW FIX QOS BANK0 Register 443" bitfld.quad 0xDD8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDD8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDD8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDD8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDD8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDD8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDE0 "QOSBW_FIX_QOS_BANK[0] [444],QOSBW FIX QOS BANK0 Register 444" bitfld.quad 0xDE0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDE0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDE0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDE0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDE0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDE0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDE8 "QOSBW_FIX_QOS_BANK[0] [445],QOSBW FIX QOS BANK0 Register 445" bitfld.quad 0xDE8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDE8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDE8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDE8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDE8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDE8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDF0 "QOSBW_FIX_QOS_BANK[0] [446],QOSBW FIX QOS BANK0 Register 446" bitfld.quad 0xDF0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDF0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDF0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDF0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDF0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDF0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xDF8 "QOSBW_FIX_QOS_BANK[0] [447],QOSBW FIX QOS BANK0 Register 447" bitfld.quad 0xDF8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDF8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xDF8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xDF8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xDF8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xDF8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE00 "QOSBW_FIX_QOS_BANK[0] [448],QOSBW FIX QOS BANK0 Register 448" bitfld.quad 0xE00 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE00 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE00 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE00 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE00 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE00 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE08 "QOSBW_FIX_QOS_BANK[0] [449],QOSBW FIX QOS BANK0 Register 449" bitfld.quad 0xE08 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE08 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE08 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE08 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE08 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE08 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE10 "QOSBW_FIX_QOS_BANK[0] [450],QOSBW FIX QOS BANK0 Register 450" bitfld.quad 0xE10 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE10 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE10 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE10 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE10 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE10 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE18 "QOSBW_FIX_QOS_BANK[0] [451],QOSBW FIX QOS BANK0 Register 451" bitfld.quad 0xE18 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE18 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE18 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE18 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE18 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE18 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE20 "QOSBW_FIX_QOS_BANK[0] [452],QOSBW FIX QOS BANK0 Register 452" bitfld.quad 0xE20 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE20 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE20 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE20 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE20 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE20 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE28 "QOSBW_FIX_QOS_BANK[0] [453],QOSBW FIX QOS BANK0 Register 453" bitfld.quad 0xE28 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE28 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE28 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE28 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE28 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE28 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE30 "QOSBW_FIX_QOS_BANK[0] [454],QOSBW FIX QOS BANK0 Register 454" bitfld.quad 0xE30 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE30 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE30 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE30 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE30 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE30 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE38 "QOSBW_FIX_QOS_BANK[0] [455],QOSBW FIX QOS BANK0 Register 455" bitfld.quad 0xE38 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE38 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE38 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE38 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE38 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE38 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE40 "QOSBW_FIX_QOS_BANK[0] [456],QOSBW FIX QOS BANK0 Register 456" bitfld.quad 0xE40 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE40 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE40 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE40 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE40 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE40 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE48 "QOSBW_FIX_QOS_BANK[0] [457],QOSBW FIX QOS BANK0 Register 457" bitfld.quad 0xE48 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE48 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE48 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE48 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE48 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE48 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE50 "QOSBW_FIX_QOS_BANK[0] [458],QOSBW FIX QOS BANK0 Register 458" bitfld.quad 0xE50 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE50 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE50 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE50 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE50 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE50 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE58 "QOSBW_FIX_QOS_BANK[0] [459],QOSBW FIX QOS BANK0 Register 459" bitfld.quad 0xE58 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE58 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE58 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE58 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE58 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE58 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE60 "QOSBW_FIX_QOS_BANK[0] [460],QOSBW FIX QOS BANK0 Register 460" bitfld.quad 0xE60 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE60 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE60 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE60 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE60 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE60 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE68 "QOSBW_FIX_QOS_BANK[0] [461],QOSBW FIX QOS BANK0 Register 461" bitfld.quad 0xE68 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE68 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE68 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE68 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE68 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE68 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE70 "QOSBW_FIX_QOS_BANK[0] [462],QOSBW FIX QOS BANK0 Register 462" bitfld.quad 0xE70 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE70 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE70 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE70 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE70 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE70 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE78 "QOSBW_FIX_QOS_BANK[0] [463],QOSBW FIX QOS BANK0 Register 463" bitfld.quad 0xE78 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE78 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE78 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE78 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE78 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE78 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE80 "QOSBW_FIX_QOS_BANK[0] [464],QOSBW FIX QOS BANK0 Register 464" bitfld.quad 0xE80 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE80 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE80 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE80 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE80 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE80 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE88 "QOSBW_FIX_QOS_BANK[0] [465],QOSBW FIX QOS BANK0 Register 465" bitfld.quad 0xE88 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE88 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE88 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE88 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE88 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE88 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE90 "QOSBW_FIX_QOS_BANK[0] [466],QOSBW FIX QOS BANK0 Register 466" bitfld.quad 0xE90 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE90 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE90 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE90 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE90 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE90 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xE98 "QOSBW_FIX_QOS_BANK[0] [467],QOSBW FIX QOS BANK0 Register 467" bitfld.quad 0xE98 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE98 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xE98 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xE98 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xE98 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xE98 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xEA0 "QOSBW_FIX_QOS_BANK[0] [468],QOSBW FIX QOS BANK0 Register 468" bitfld.quad 0xEA0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEA0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xEA0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xEA0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xEA0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xEA0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xEA8 "QOSBW_FIX_QOS_BANK[0] [469],QOSBW FIX QOS BANK0 Register 469" bitfld.quad 0xEA8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEA8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xEA8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xEA8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xEA8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xEA8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xEB0 "QOSBW_FIX_QOS_BANK[0] [470],QOSBW FIX QOS BANK0 Register 470" bitfld.quad 0xEB0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEB0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xEB0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xEB0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xEB0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xEB0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xEB8 "QOSBW_FIX_QOS_BANK[0] [471],QOSBW FIX QOS BANK0 Register 471" bitfld.quad 0xEB8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEB8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xEB8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xEB8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xEB8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xEB8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xEC0 "QOSBW_FIX_QOS_BANK[0] [472],QOSBW FIX QOS BANK0 Register 472" bitfld.quad 0xEC0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEC0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xEC0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xEC0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xEC0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xEC0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xEC8 "QOSBW_FIX_QOS_BANK[0] [473],QOSBW FIX QOS BANK0 Register 473" bitfld.quad 0xEC8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEC8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xEC8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xEC8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xEC8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xEC8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xED0 "QOSBW_FIX_QOS_BANK[0] [474],QOSBW FIX QOS BANK0 Register 474" bitfld.quad 0xED0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xED0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xED0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xED0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xED0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xED0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xED8 "QOSBW_FIX_QOS_BANK[0] [475],QOSBW FIX QOS BANK0 Register 475" bitfld.quad 0xED8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xED8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xED8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xED8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xED8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xED8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xEE0 "QOSBW_FIX_QOS_BANK[0] [476],QOSBW FIX QOS BANK0 Register 476" bitfld.quad 0xEE0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEE0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xEE0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xEE0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xEE0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xEE0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xEE8 "QOSBW_FIX_QOS_BANK[0] [477],QOSBW FIX QOS BANK0 Register 477" bitfld.quad 0xEE8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEE8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xEE8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xEE8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xEE8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xEE8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xEF0 "QOSBW_FIX_QOS_BANK[0] [478],QOSBW FIX QOS BANK0 Register 478" bitfld.quad 0xEF0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEF0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xEF0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xEF0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xEF0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xEF0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xEF8 "QOSBW_FIX_QOS_BANK[0] [479],QOSBW FIX QOS BANK0 Register 479" bitfld.quad 0xEF8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEF8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xEF8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xEF8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xEF8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xEF8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF00 "QOSBW_FIX_QOS_BANK[0] [480],QOSBW FIX QOS BANK0 Register 480" bitfld.quad 0xF00 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF00 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF00 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF00 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF00 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF00 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF08 "QOSBW_FIX_QOS_BANK[0] [481],QOSBW FIX QOS BANK0 Register 481" bitfld.quad 0xF08 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF08 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF08 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF08 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF08 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF08 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF10 "QOSBW_FIX_QOS_BANK[0] [482],QOSBW FIX QOS BANK0 Register 482" bitfld.quad 0xF10 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF10 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF10 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF10 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF10 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF10 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF18 "QOSBW_FIX_QOS_BANK[0] [483],QOSBW FIX QOS BANK0 Register 483" bitfld.quad 0xF18 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF18 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF18 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF18 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF18 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF18 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF20 "QOSBW_FIX_QOS_BANK[0] [484],QOSBW FIX QOS BANK0 Register 484" bitfld.quad 0xF20 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF20 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF20 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF20 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF20 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF20 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF28 "QOSBW_FIX_QOS_BANK[0] [485],QOSBW FIX QOS BANK0 Register 485" bitfld.quad 0xF28 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF28 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF28 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF28 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF28 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF28 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF30 "QOSBW_FIX_QOS_BANK[0] [486],QOSBW FIX QOS BANK0 Register 486" bitfld.quad 0xF30 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF30 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF30 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF30 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF30 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF30 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF38 "QOSBW_FIX_QOS_BANK[0] [487],QOSBW FIX QOS BANK0 Register 487" bitfld.quad 0xF38 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF38 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF38 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF38 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF38 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF38 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF40 "QOSBW_FIX_QOS_BANK[0] [488],QOSBW FIX QOS BANK0 Register 488" bitfld.quad 0xF40 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF40 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF40 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF40 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF40 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF40 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF48 "QOSBW_FIX_QOS_BANK[0] [489],QOSBW FIX QOS BANK0 Register 489" bitfld.quad 0xF48 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF48 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF48 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF48 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF48 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF48 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF50 "QOSBW_FIX_QOS_BANK[0] [490],QOSBW FIX QOS BANK0 Register 490" bitfld.quad 0xF50 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF50 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF50 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF50 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF50 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF50 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF58 "QOSBW_FIX_QOS_BANK[0] [491],QOSBW FIX QOS BANK0 Register 491" bitfld.quad 0xF58 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF58 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF58 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF58 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF58 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF58 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF60 "QOSBW_FIX_QOS_BANK[0] [492],QOSBW FIX QOS BANK0 Register 492" bitfld.quad 0xF60 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF60 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF60 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF60 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF60 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF60 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF68 "QOSBW_FIX_QOS_BANK[0] [493],QOSBW FIX QOS BANK0 Register 493" bitfld.quad 0xF68 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF68 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF68 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF68 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF68 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF68 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF70 "QOSBW_FIX_QOS_BANK[0] [494],QOSBW FIX QOS BANK0 Register 494" bitfld.quad 0xF70 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF70 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF70 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF70 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF70 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF70 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF78 "QOSBW_FIX_QOS_BANK[0] [495],QOSBW FIX QOS BANK0 Register 495" bitfld.quad 0xF78 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF78 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF78 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF78 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF78 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF78 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF80 "QOSBW_FIX_QOS_BANK[0] [496],QOSBW FIX QOS BANK0 Register 496" bitfld.quad 0xF80 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF80 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF80 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF80 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF80 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF80 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF88 "QOSBW_FIX_QOS_BANK[0] [497],QOSBW FIX QOS BANK0 Register 497" bitfld.quad 0xF88 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF88 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF88 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF88 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF88 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF88 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF90 "QOSBW_FIX_QOS_BANK[0] [498],QOSBW FIX QOS BANK0 Register 498" bitfld.quad 0xF90 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF90 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF90 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF90 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF90 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF90 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xF98 "QOSBW_FIX_QOS_BANK[0] [499],QOSBW FIX QOS BANK0 Register 499" bitfld.quad 0xF98 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF98 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xF98 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xF98 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xF98 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xF98 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFA0 "QOSBW_FIX_QOS_BANK[0] [500],QOSBW FIX QOS BANK0 Register 500" bitfld.quad 0xFA0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFA0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFA0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFA0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFA0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFA0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFA8 "QOSBW_FIX_QOS_BANK[0] [501],QOSBW FIX QOS BANK0 Register 501" bitfld.quad 0xFA8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFA8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFA8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFA8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFA8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFA8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFB0 "QOSBW_FIX_QOS_BANK[0] [502],QOSBW FIX QOS BANK0 Register 502" bitfld.quad 0xFB0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFB0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFB0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFB0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFB0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFB0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFB8 "QOSBW_FIX_QOS_BANK[0] [503],QOSBW FIX QOS BANK0 Register 503" bitfld.quad 0xFB8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFB8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFB8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFB8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFB8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFB8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFC0 "QOSBW_FIX_QOS_BANK[0] [504],QOSBW FIX QOS BANK0 Register 504" bitfld.quad 0xFC0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFC0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFC0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFC0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFC0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFC0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFC8 "QOSBW_FIX_QOS_BANK[0] [505],QOSBW FIX QOS BANK0 Register 505" bitfld.quad 0xFC8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFC8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFC8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFC8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFC8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFC8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFD0 "QOSBW_FIX_QOS_BANK[0] [506],QOSBW FIX QOS BANK0 Register 506" bitfld.quad 0xFD0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFD0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFD0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFD0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFD0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFD0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFD8 "QOSBW_FIX_QOS_BANK[0] [507],QOSBW FIX QOS BANK0 Register 507" bitfld.quad 0xFD8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFD8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFD8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFD8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFD8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFD8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFE0 "QOSBW_FIX_QOS_BANK[0] [508],QOSBW FIX QOS BANK0 Register 508" bitfld.quad 0xFE0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFE0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFE0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFE0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFE0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFE0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFE8 "QOSBW_FIX_QOS_BANK[0] [509],QOSBW FIX QOS BANK0 Register 509" bitfld.quad 0xFE8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFE8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFE8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFE8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFE8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFE8 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFF0 "QOSBW_FIX_QOS_BANK[0] [510],QOSBW FIX QOS BANK0 Register 510" bitfld.quad 0xFF0 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFF0 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFF0 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFF0 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFF0 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFF0 0.--15. 1. "FIXQOS_BANK0_0" line.quad 0xFF8 "QOSBW_FIX_QOS_BANK[0] [511],QOSBW FIX QOS BANK0 Register 511" bitfld.quad 0xFF8 50.--52. "FIXQOS_BANK0_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFF8 42.--49. 1. "FIXQOS_BANK0_4" hexmask.quad.word 0xFF8 32.--41. 1. "FIXQOS_BANK0_3" newline hexmask.quad.byte 0xFF8 24.--31. 1. "FIXQOS_BANK0_2" hexmask.quad.byte 0xFF8 16.--23. 1. "FIXQOS_BANK0_1" hexmask.quad.word 0xFF8 0.--15. 1. "FIXQOS_BANK0_0" group.quad 0x1000++0xFFF line.quad 0x0 "QOSBW_FIX_QOS_BANK[1] [0],QOSBW FIX QOS BANK1 Register 0" bitfld.quad 0x0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8 "QOSBW_FIX_QOS_BANK[1] [1],QOSBW FIX QOS BANK1 Register 1" bitfld.quad 0x8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x10 "QOSBW_FIX_QOS_BANK[1] [2],QOSBW FIX QOS BANK1 Register 2" bitfld.quad 0x10 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x10 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x10 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x10 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x10 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x10 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x18 "QOSBW_FIX_QOS_BANK[1] [3],QOSBW FIX QOS BANK1 Register 3" bitfld.quad 0x18 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x18 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x18 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x18 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x18 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x18 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x20 "QOSBW_FIX_QOS_BANK[1] [4],QOSBW FIX QOS BANK1 Register 4" bitfld.quad 0x20 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x20 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x20 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x20 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x20 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x20 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x28 "QOSBW_FIX_QOS_BANK[1] [5],QOSBW FIX QOS BANK1 Register 5" bitfld.quad 0x28 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x28 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x28 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x28 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x28 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x28 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x30 "QOSBW_FIX_QOS_BANK[1] [6],QOSBW FIX QOS BANK1 Register 6" bitfld.quad 0x30 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x30 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x30 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x30 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x30 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x30 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x38 "QOSBW_FIX_QOS_BANK[1] [7],QOSBW FIX QOS BANK1 Register 7" bitfld.quad 0x38 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x38 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x38 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x38 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x38 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x38 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x40 "QOSBW_FIX_QOS_BANK[1] [8],QOSBW FIX QOS BANK1 Register 8" bitfld.quad 0x40 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x40 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x40 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x40 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x40 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x40 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x48 "QOSBW_FIX_QOS_BANK[1] [9],QOSBW FIX QOS BANK1 Register 9" bitfld.quad 0x48 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x48 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x48 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x48 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x48 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x48 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x50 "QOSBW_FIX_QOS_BANK[1] [10],QOSBW FIX QOS BANK1 Register 10" bitfld.quad 0x50 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x50 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x50 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x50 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x50 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x50 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x58 "QOSBW_FIX_QOS_BANK[1] [11],QOSBW FIX QOS BANK1 Register 11" bitfld.quad 0x58 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x58 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x58 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x58 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x58 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x58 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x60 "QOSBW_FIX_QOS_BANK[1] [12],QOSBW FIX QOS BANK1 Register 12" bitfld.quad 0x60 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x60 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x60 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x60 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x60 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x60 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x68 "QOSBW_FIX_QOS_BANK[1] [13],QOSBW FIX QOS BANK1 Register 13" bitfld.quad 0x68 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x68 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x68 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x68 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x68 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x68 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x70 "QOSBW_FIX_QOS_BANK[1] [14],QOSBW FIX QOS BANK1 Register 14" bitfld.quad 0x70 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x70 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x70 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x70 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x70 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x70 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x78 "QOSBW_FIX_QOS_BANK[1] [15],QOSBW FIX QOS BANK1 Register 15" bitfld.quad 0x78 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x78 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x78 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x78 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x78 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x78 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x80 "QOSBW_FIX_QOS_BANK[1] [16],QOSBW FIX QOS BANK1 Register 16" bitfld.quad 0x80 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x80 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x80 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x80 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x80 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x80 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x88 "QOSBW_FIX_QOS_BANK[1] [17],QOSBW FIX QOS BANK1 Register 17" bitfld.quad 0x88 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x88 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x88 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x88 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x88 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x88 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x90 "QOSBW_FIX_QOS_BANK[1] [18],QOSBW FIX QOS BANK1 Register 18" bitfld.quad 0x90 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x90 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x90 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x90 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x90 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x90 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x98 "QOSBW_FIX_QOS_BANK[1] [19],QOSBW FIX QOS BANK1 Register 19" bitfld.quad 0x98 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x98 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x98 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x98 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x98 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x98 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA0 "QOSBW_FIX_QOS_BANK[1] [20],QOSBW FIX QOS BANK1 Register 20" bitfld.quad 0xA0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA8 "QOSBW_FIX_QOS_BANK[1] [21],QOSBW FIX QOS BANK1 Register 21" bitfld.quad 0xA8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB0 "QOSBW_FIX_QOS_BANK[1] [22],QOSBW FIX QOS BANK1 Register 22" bitfld.quad 0xB0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB8 "QOSBW_FIX_QOS_BANK[1] [23],QOSBW FIX QOS BANK1 Register 23" bitfld.quad 0xB8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC0 "QOSBW_FIX_QOS_BANK[1] [24],QOSBW FIX QOS BANK1 Register 24" bitfld.quad 0xC0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC8 "QOSBW_FIX_QOS_BANK[1] [25],QOSBW FIX QOS BANK1 Register 25" bitfld.quad 0xC8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD0 "QOSBW_FIX_QOS_BANK[1] [26],QOSBW FIX QOS BANK1 Register 26" bitfld.quad 0xD0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD8 "QOSBW_FIX_QOS_BANK[1] [27],QOSBW FIX QOS BANK1 Register 27" bitfld.quad 0xD8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE0 "QOSBW_FIX_QOS_BANK[1] [28],QOSBW FIX QOS BANK1 Register 28" bitfld.quad 0xE0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE8 "QOSBW_FIX_QOS_BANK[1] [29],QOSBW FIX QOS BANK1 Register 29" bitfld.quad 0xE8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF0 "QOSBW_FIX_QOS_BANK[1] [30],QOSBW FIX QOS BANK1 Register 30" bitfld.quad 0xF0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF8 "QOSBW_FIX_QOS_BANK[1] [31],QOSBW FIX QOS BANK1 Register 31" bitfld.quad 0xF8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x100 "QOSBW_FIX_QOS_BANK[1] [32],QOSBW FIX QOS BANK1 Register 32" bitfld.quad 0x100 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x100 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x100 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x100 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x100 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x100 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x108 "QOSBW_FIX_QOS_BANK[1] [33],QOSBW FIX QOS BANK1 Register 33" bitfld.quad 0x108 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x108 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x108 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x108 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x108 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x108 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x110 "QOSBW_FIX_QOS_BANK[1] [34],QOSBW FIX QOS BANK1 Register 34" bitfld.quad 0x110 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x110 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x110 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x110 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x110 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x110 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x118 "QOSBW_FIX_QOS_BANK[1] [35],QOSBW FIX QOS BANK1 Register 35" bitfld.quad 0x118 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x118 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x118 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x118 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x118 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x118 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x120 "QOSBW_FIX_QOS_BANK[1] [36],QOSBW FIX QOS BANK1 Register 36" bitfld.quad 0x120 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x120 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x120 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x120 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x120 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x120 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x128 "QOSBW_FIX_QOS_BANK[1] [37],QOSBW FIX QOS BANK1 Register 37" bitfld.quad 0x128 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x128 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x128 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x128 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x128 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x128 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x130 "QOSBW_FIX_QOS_BANK[1] [38],QOSBW FIX QOS BANK1 Register 38" bitfld.quad 0x130 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x130 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x130 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x130 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x130 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x130 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x138 "QOSBW_FIX_QOS_BANK[1] [39],QOSBW FIX QOS BANK1 Register 39" bitfld.quad 0x138 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x138 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x138 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x138 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x138 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x138 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x140 "QOSBW_FIX_QOS_BANK[1] [40],QOSBW FIX QOS BANK1 Register 40" bitfld.quad 0x140 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x140 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x140 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x140 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x140 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x140 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x148 "QOSBW_FIX_QOS_BANK[1] [41],QOSBW FIX QOS BANK1 Register 41" bitfld.quad 0x148 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x148 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x148 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x148 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x148 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x148 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x150 "QOSBW_FIX_QOS_BANK[1] [42],QOSBW FIX QOS BANK1 Register 42" bitfld.quad 0x150 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x150 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x150 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x150 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x150 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x150 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x158 "QOSBW_FIX_QOS_BANK[1] [43],QOSBW FIX QOS BANK1 Register 43" bitfld.quad 0x158 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x158 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x158 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x158 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x158 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x158 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x160 "QOSBW_FIX_QOS_BANK[1] [44],QOSBW FIX QOS BANK1 Register 44" bitfld.quad 0x160 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x160 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x160 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x160 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x160 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x160 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x168 "QOSBW_FIX_QOS_BANK[1] [45],QOSBW FIX QOS BANK1 Register 45" bitfld.quad 0x168 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x168 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x168 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x168 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x168 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x168 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x170 "QOSBW_FIX_QOS_BANK[1] [46],QOSBW FIX QOS BANK1 Register 46" bitfld.quad 0x170 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x170 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x170 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x170 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x170 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x170 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x178 "QOSBW_FIX_QOS_BANK[1] [47],QOSBW FIX QOS BANK1 Register 47" bitfld.quad 0x178 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x178 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x178 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x178 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x178 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x178 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x180 "QOSBW_FIX_QOS_BANK[1] [48],QOSBW FIX QOS BANK1 Register 48" bitfld.quad 0x180 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x180 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x180 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x180 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x180 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x180 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x188 "QOSBW_FIX_QOS_BANK[1] [49],QOSBW FIX QOS BANK1 Register 49" bitfld.quad 0x188 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x188 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x188 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x188 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x188 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x188 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x190 "QOSBW_FIX_QOS_BANK[1] [50],QOSBW FIX QOS BANK1 Register 50" bitfld.quad 0x190 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x190 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x190 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x190 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x190 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x190 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x198 "QOSBW_FIX_QOS_BANK[1] [51],QOSBW FIX QOS BANK1 Register 51" bitfld.quad 0x198 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x198 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x198 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x198 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x198 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x198 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1A0 "QOSBW_FIX_QOS_BANK[1] [52],QOSBW FIX QOS BANK1 Register 52" bitfld.quad 0x1A0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1A0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1A0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1A0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1A0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1A0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1A8 "QOSBW_FIX_QOS_BANK[1] [53],QOSBW FIX QOS BANK1 Register 53" bitfld.quad 0x1A8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1A8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1A8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1A8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1A8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1A8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1B0 "QOSBW_FIX_QOS_BANK[1] [54],QOSBW FIX QOS BANK1 Register 54" bitfld.quad 0x1B0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1B0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1B0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1B0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1B0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1B0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1B8 "QOSBW_FIX_QOS_BANK[1] [55],QOSBW FIX QOS BANK1 Register 55" bitfld.quad 0x1B8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1B8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1B8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1B8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1B8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1B8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1C0 "QOSBW_FIX_QOS_BANK[1] [56],QOSBW FIX QOS BANK1 Register 56" bitfld.quad 0x1C0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1C0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1C0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1C0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1C0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1C0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1C8 "QOSBW_FIX_QOS_BANK[1] [57],QOSBW FIX QOS BANK1 Register 57" bitfld.quad 0x1C8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1C8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1C8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1C8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1C8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1C8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1D0 "QOSBW_FIX_QOS_BANK[1] [58],QOSBW FIX QOS BANK1 Register 58" bitfld.quad 0x1D0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1D0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1D0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1D0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1D0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1D0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1D8 "QOSBW_FIX_QOS_BANK[1] [59],QOSBW FIX QOS BANK1 Register 59" bitfld.quad 0x1D8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1D8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1D8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1D8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1D8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1D8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1E0 "QOSBW_FIX_QOS_BANK[1] [60],QOSBW FIX QOS BANK1 Register 60" bitfld.quad 0x1E0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1E0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1E0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1E0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1E0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1E0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1E8 "QOSBW_FIX_QOS_BANK[1] [61],QOSBW FIX QOS BANK1 Register 61" bitfld.quad 0x1E8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1E8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1E8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1E8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1E8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1E8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1F0 "QOSBW_FIX_QOS_BANK[1] [62],QOSBW FIX QOS BANK1 Register 62" bitfld.quad 0x1F0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1F0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1F0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1F0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1F0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1F0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x1F8 "QOSBW_FIX_QOS_BANK[1] [63],QOSBW FIX QOS BANK1 Register 63" bitfld.quad 0x1F8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x1F8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x1F8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x1F8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x1F8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x1F8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x200 "QOSBW_FIX_QOS_BANK[1] [64],QOSBW FIX QOS BANK1 Register 64" bitfld.quad 0x200 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x200 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x200 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x200 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x200 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x200 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x208 "QOSBW_FIX_QOS_BANK[1] [65],QOSBW FIX QOS BANK1 Register 65" bitfld.quad 0x208 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x208 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x208 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x208 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x208 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x208 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x210 "QOSBW_FIX_QOS_BANK[1] [66],QOSBW FIX QOS BANK1 Register 66" bitfld.quad 0x210 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x210 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x210 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x210 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x210 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x210 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x218 "QOSBW_FIX_QOS_BANK[1] [67],QOSBW FIX QOS BANK1 Register 67" bitfld.quad 0x218 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x218 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x218 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x218 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x218 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x218 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x220 "QOSBW_FIX_QOS_BANK[1] [68],QOSBW FIX QOS BANK1 Register 68" bitfld.quad 0x220 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x220 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x220 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x220 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x220 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x220 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x228 "QOSBW_FIX_QOS_BANK[1] [69],QOSBW FIX QOS BANK1 Register 69" bitfld.quad 0x228 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x228 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x228 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x228 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x228 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x228 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x230 "QOSBW_FIX_QOS_BANK[1] [70],QOSBW FIX QOS BANK1 Register 70" bitfld.quad 0x230 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x230 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x230 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x230 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x230 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x230 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x238 "QOSBW_FIX_QOS_BANK[1] [71],QOSBW FIX QOS BANK1 Register 71" bitfld.quad 0x238 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x238 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x238 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x238 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x238 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x238 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x240 "QOSBW_FIX_QOS_BANK[1] [72],QOSBW FIX QOS BANK1 Register 72" bitfld.quad 0x240 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x240 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x240 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x240 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x240 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x240 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x248 "QOSBW_FIX_QOS_BANK[1] [73],QOSBW FIX QOS BANK1 Register 73" bitfld.quad 0x248 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x248 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x248 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x248 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x248 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x248 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x250 "QOSBW_FIX_QOS_BANK[1] [74],QOSBW FIX QOS BANK1 Register 74" bitfld.quad 0x250 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x250 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x250 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x250 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x250 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x250 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x258 "QOSBW_FIX_QOS_BANK[1] [75],QOSBW FIX QOS BANK1 Register 75" bitfld.quad 0x258 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x258 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x258 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x258 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x258 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x258 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x260 "QOSBW_FIX_QOS_BANK[1] [76],QOSBW FIX QOS BANK1 Register 76" bitfld.quad 0x260 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x260 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x260 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x260 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x260 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x260 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x268 "QOSBW_FIX_QOS_BANK[1] [77],QOSBW FIX QOS BANK1 Register 77" bitfld.quad 0x268 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x268 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x268 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x268 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x268 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x268 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x270 "QOSBW_FIX_QOS_BANK[1] [78],QOSBW FIX QOS BANK1 Register 78" bitfld.quad 0x270 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x270 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x270 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x270 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x270 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x270 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x278 "QOSBW_FIX_QOS_BANK[1] [79],QOSBW FIX QOS BANK1 Register 79" bitfld.quad 0x278 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x278 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x278 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x278 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x278 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x278 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x280 "QOSBW_FIX_QOS_BANK[1] [80],QOSBW FIX QOS BANK1 Register 80" bitfld.quad 0x280 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x280 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x280 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x280 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x280 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x280 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x288 "QOSBW_FIX_QOS_BANK[1] [81],QOSBW FIX QOS BANK1 Register 81" bitfld.quad 0x288 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x288 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x288 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x288 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x288 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x288 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x290 "QOSBW_FIX_QOS_BANK[1] [82],QOSBW FIX QOS BANK1 Register 82" bitfld.quad 0x290 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x290 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x290 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x290 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x290 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x290 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x298 "QOSBW_FIX_QOS_BANK[1] [83],QOSBW FIX QOS BANK1 Register 83" bitfld.quad 0x298 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x298 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x298 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x298 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x298 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x298 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2A0 "QOSBW_FIX_QOS_BANK[1] [84],QOSBW FIX QOS BANK1 Register 84" bitfld.quad 0x2A0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2A0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2A0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2A0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2A0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2A0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2A8 "QOSBW_FIX_QOS_BANK[1] [85],QOSBW FIX QOS BANK1 Register 85" bitfld.quad 0x2A8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2A8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2A8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2A8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2A8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2A8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2B0 "QOSBW_FIX_QOS_BANK[1] [86],QOSBW FIX QOS BANK1 Register 86" bitfld.quad 0x2B0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2B0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2B0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2B0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2B0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2B0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2B8 "QOSBW_FIX_QOS_BANK[1] [87],QOSBW FIX QOS BANK1 Register 87" bitfld.quad 0x2B8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2B8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2B8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2B8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2B8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2B8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2C0 "QOSBW_FIX_QOS_BANK[1] [88],QOSBW FIX QOS BANK1 Register 88" bitfld.quad 0x2C0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2C0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2C0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2C0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2C0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2C0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2C8 "QOSBW_FIX_QOS_BANK[1] [89],QOSBW FIX QOS BANK1 Register 89" bitfld.quad 0x2C8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2C8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2C8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2C8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2C8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2C8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2D0 "QOSBW_FIX_QOS_BANK[1] [90],QOSBW FIX QOS BANK1 Register 90" bitfld.quad 0x2D0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2D0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2D0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2D0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2D0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2D0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2D8 "QOSBW_FIX_QOS_BANK[1] [91],QOSBW FIX QOS BANK1 Register 91" bitfld.quad 0x2D8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2D8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2D8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2D8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2D8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2D8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2E0 "QOSBW_FIX_QOS_BANK[1] [92],QOSBW FIX QOS BANK1 Register 92" bitfld.quad 0x2E0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2E0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2E0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2E0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2E0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2E0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2E8 "QOSBW_FIX_QOS_BANK[1] [93],QOSBW FIX QOS BANK1 Register 93" bitfld.quad 0x2E8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2E8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2E8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2E8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2E8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2E8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2F0 "QOSBW_FIX_QOS_BANK[1] [94],QOSBW FIX QOS BANK1 Register 94" bitfld.quad 0x2F0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2F0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2F0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2F0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2F0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2F0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x2F8 "QOSBW_FIX_QOS_BANK[1] [95],QOSBW FIX QOS BANK1 Register 95" bitfld.quad 0x2F8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x2F8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x2F8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x2F8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x2F8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x2F8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x300 "QOSBW_FIX_QOS_BANK[1] [96],QOSBW FIX QOS BANK1 Register 96" bitfld.quad 0x300 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x300 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x300 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x300 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x300 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x300 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x308 "QOSBW_FIX_QOS_BANK[1] [97],QOSBW FIX QOS BANK1 Register 97" bitfld.quad 0x308 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x308 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x308 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x308 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x308 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x308 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x310 "QOSBW_FIX_QOS_BANK[1] [98],QOSBW FIX QOS BANK1 Register 98" bitfld.quad 0x310 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x310 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x310 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x310 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x310 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x310 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x318 "QOSBW_FIX_QOS_BANK[1] [99],QOSBW FIX QOS BANK1 Register 99" bitfld.quad 0x318 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x318 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x318 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x318 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x318 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x318 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x320 "QOSBW_FIX_QOS_BANK[1] [100],QOSBW FIX QOS BANK1 Register 100" bitfld.quad 0x320 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x320 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x320 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x320 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x320 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x320 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x328 "QOSBW_FIX_QOS_BANK[1] [101],QOSBW FIX QOS BANK1 Register 101" bitfld.quad 0x328 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x328 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x328 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x328 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x328 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x328 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x330 "QOSBW_FIX_QOS_BANK[1] [102],QOSBW FIX QOS BANK1 Register 102" bitfld.quad 0x330 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x330 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x330 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x330 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x330 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x330 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x338 "QOSBW_FIX_QOS_BANK[1] [103],QOSBW FIX QOS BANK1 Register 103" bitfld.quad 0x338 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x338 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x338 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x338 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x338 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x338 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x340 "QOSBW_FIX_QOS_BANK[1] [104],QOSBW FIX QOS BANK1 Register 104" bitfld.quad 0x340 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x340 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x340 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x340 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x340 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x340 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x348 "QOSBW_FIX_QOS_BANK[1] [105],QOSBW FIX QOS BANK1 Register 105" bitfld.quad 0x348 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x348 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x348 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x348 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x348 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x348 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x350 "QOSBW_FIX_QOS_BANK[1] [106],QOSBW FIX QOS BANK1 Register 106" bitfld.quad 0x350 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x350 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x350 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x350 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x350 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x350 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x358 "QOSBW_FIX_QOS_BANK[1] [107],QOSBW FIX QOS BANK1 Register 107" bitfld.quad 0x358 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x358 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x358 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x358 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x358 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x358 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x360 "QOSBW_FIX_QOS_BANK[1] [108],QOSBW FIX QOS BANK1 Register 108" bitfld.quad 0x360 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x360 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x360 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x360 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x360 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x360 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x368 "QOSBW_FIX_QOS_BANK[1] [109],QOSBW FIX QOS BANK1 Register 109" bitfld.quad 0x368 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x368 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x368 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x368 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x368 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x368 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x370 "QOSBW_FIX_QOS_BANK[1] [110],QOSBW FIX QOS BANK1 Register 110" bitfld.quad 0x370 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x370 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x370 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x370 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x370 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x370 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x378 "QOSBW_FIX_QOS_BANK[1] [111],QOSBW FIX QOS BANK1 Register 111" bitfld.quad 0x378 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x378 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x378 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x378 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x378 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x378 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x380 "QOSBW_FIX_QOS_BANK[1] [112],QOSBW FIX QOS BANK1 Register 112" bitfld.quad 0x380 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x380 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x380 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x380 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x380 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x380 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x388 "QOSBW_FIX_QOS_BANK[1] [113],QOSBW FIX QOS BANK1 Register 113" bitfld.quad 0x388 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x388 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x388 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x388 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x388 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x388 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x390 "QOSBW_FIX_QOS_BANK[1] [114],QOSBW FIX QOS BANK1 Register 114" bitfld.quad 0x390 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x390 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x390 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x390 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x390 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x390 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x398 "QOSBW_FIX_QOS_BANK[1] [115],QOSBW FIX QOS BANK1 Register 115" bitfld.quad 0x398 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x398 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x398 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x398 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x398 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x398 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3A0 "QOSBW_FIX_QOS_BANK[1] [116],QOSBW FIX QOS BANK1 Register 116" bitfld.quad 0x3A0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3A0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3A0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3A0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3A0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3A0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3A8 "QOSBW_FIX_QOS_BANK[1] [117],QOSBW FIX QOS BANK1 Register 117" bitfld.quad 0x3A8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3A8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3A8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3A8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3A8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3A8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3B0 "QOSBW_FIX_QOS_BANK[1] [118],QOSBW FIX QOS BANK1 Register 118" bitfld.quad 0x3B0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3B0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3B0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3B0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3B0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3B0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3B8 "QOSBW_FIX_QOS_BANK[1] [119],QOSBW FIX QOS BANK1 Register 119" bitfld.quad 0x3B8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3B8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3B8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3B8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3B8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3B8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3C0 "QOSBW_FIX_QOS_BANK[1] [120],QOSBW FIX QOS BANK1 Register 120" bitfld.quad 0x3C0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3C0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3C0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3C0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3C0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3C0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3C8 "QOSBW_FIX_QOS_BANK[1] [121],QOSBW FIX QOS BANK1 Register 121" bitfld.quad 0x3C8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3C8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3C8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3C8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3C8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3C8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3D0 "QOSBW_FIX_QOS_BANK[1] [122],QOSBW FIX QOS BANK1 Register 122" bitfld.quad 0x3D0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3D0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3D0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3D0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3D0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3D0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3D8 "QOSBW_FIX_QOS_BANK[1] [123],QOSBW FIX QOS BANK1 Register 123" bitfld.quad 0x3D8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3D8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3D8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3D8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3D8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3D8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3E0 "QOSBW_FIX_QOS_BANK[1] [124],QOSBW FIX QOS BANK1 Register 124" bitfld.quad 0x3E0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3E0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3E0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3E0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3E0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3E0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3E8 "QOSBW_FIX_QOS_BANK[1] [125],QOSBW FIX QOS BANK1 Register 125" bitfld.quad 0x3E8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3E8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3E8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3E8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3E8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3E8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3F0 "QOSBW_FIX_QOS_BANK[1] [126],QOSBW FIX QOS BANK1 Register 126" bitfld.quad 0x3F0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3F0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3F0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3F0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3F0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3F0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x3F8 "QOSBW_FIX_QOS_BANK[1] [127],QOSBW FIX QOS BANK1 Register 127" bitfld.quad 0x3F8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x3F8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x3F8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x3F8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x3F8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x3F8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x400 "QOSBW_FIX_QOS_BANK[1] [128],QOSBW FIX QOS BANK1 Register 128" bitfld.quad 0x400 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x400 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x400 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x400 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x400 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x400 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x408 "QOSBW_FIX_QOS_BANK[1] [129],QOSBW FIX QOS BANK1 Register 129" bitfld.quad 0x408 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x408 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x408 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x408 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x408 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x408 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x410 "QOSBW_FIX_QOS_BANK[1] [130],QOSBW FIX QOS BANK1 Register 130" bitfld.quad 0x410 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x410 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x410 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x410 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x410 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x410 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x418 "QOSBW_FIX_QOS_BANK[1] [131],QOSBW FIX QOS BANK1 Register 131" bitfld.quad 0x418 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x418 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x418 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x418 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x418 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x418 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x420 "QOSBW_FIX_QOS_BANK[1] [132],QOSBW FIX QOS BANK1 Register 132" bitfld.quad 0x420 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x420 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x420 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x420 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x420 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x420 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x428 "QOSBW_FIX_QOS_BANK[1] [133],QOSBW FIX QOS BANK1 Register 133" bitfld.quad 0x428 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x428 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x428 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x428 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x428 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x428 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x430 "QOSBW_FIX_QOS_BANK[1] [134],QOSBW FIX QOS BANK1 Register 134" bitfld.quad 0x430 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x430 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x430 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x430 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x430 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x430 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x438 "QOSBW_FIX_QOS_BANK[1] [135],QOSBW FIX QOS BANK1 Register 135" bitfld.quad 0x438 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x438 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x438 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x438 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x438 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x438 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x440 "QOSBW_FIX_QOS_BANK[1] [136],QOSBW FIX QOS BANK1 Register 136" bitfld.quad 0x440 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x440 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x440 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x440 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x440 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x440 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x448 "QOSBW_FIX_QOS_BANK[1] [137],QOSBW FIX QOS BANK1 Register 137" bitfld.quad 0x448 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x448 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x448 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x448 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x448 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x448 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x450 "QOSBW_FIX_QOS_BANK[1] [138],QOSBW FIX QOS BANK1 Register 138" bitfld.quad 0x450 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x450 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x450 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x450 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x450 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x450 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x458 "QOSBW_FIX_QOS_BANK[1] [139],QOSBW FIX QOS BANK1 Register 139" bitfld.quad 0x458 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x458 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x458 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x458 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x458 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x458 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x460 "QOSBW_FIX_QOS_BANK[1] [140],QOSBW FIX QOS BANK1 Register 140" bitfld.quad 0x460 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x460 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x460 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x460 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x460 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x460 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x468 "QOSBW_FIX_QOS_BANK[1] [141],QOSBW FIX QOS BANK1 Register 141" bitfld.quad 0x468 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x468 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x468 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x468 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x468 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x468 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x470 "QOSBW_FIX_QOS_BANK[1] [142],QOSBW FIX QOS BANK1 Register 142" bitfld.quad 0x470 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x470 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x470 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x470 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x470 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x470 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x478 "QOSBW_FIX_QOS_BANK[1] [143],QOSBW FIX QOS BANK1 Register 143" bitfld.quad 0x478 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x478 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x478 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x478 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x478 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x478 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x480 "QOSBW_FIX_QOS_BANK[1] [144],QOSBW FIX QOS BANK1 Register 144" bitfld.quad 0x480 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x480 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x480 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x480 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x480 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x480 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x488 "QOSBW_FIX_QOS_BANK[1] [145],QOSBW FIX QOS BANK1 Register 145" bitfld.quad 0x488 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x488 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x488 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x488 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x488 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x488 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x490 "QOSBW_FIX_QOS_BANK[1] [146],QOSBW FIX QOS BANK1 Register 146" bitfld.quad 0x490 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x490 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x490 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x490 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x490 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x490 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x498 "QOSBW_FIX_QOS_BANK[1] [147],QOSBW FIX QOS BANK1 Register 147" bitfld.quad 0x498 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x498 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x498 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x498 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x498 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x498 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4A0 "QOSBW_FIX_QOS_BANK[1] [148],QOSBW FIX QOS BANK1 Register 148" bitfld.quad 0x4A0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4A0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4A0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4A0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4A0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4A0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4A8 "QOSBW_FIX_QOS_BANK[1] [149],QOSBW FIX QOS BANK1 Register 149" bitfld.quad 0x4A8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4A8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4A8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4A8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4A8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4A8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4B0 "QOSBW_FIX_QOS_BANK[1] [150],QOSBW FIX QOS BANK1 Register 150" bitfld.quad 0x4B0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4B0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4B0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4B0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4B0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4B0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4B8 "QOSBW_FIX_QOS_BANK[1] [151],QOSBW FIX QOS BANK1 Register 151" bitfld.quad 0x4B8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4B8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4B8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4B8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4B8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4B8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4C0 "QOSBW_FIX_QOS_BANK[1] [152],QOSBW FIX QOS BANK1 Register 152" bitfld.quad 0x4C0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4C0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4C0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4C0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4C0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4C0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4C8 "QOSBW_FIX_QOS_BANK[1] [153],QOSBW FIX QOS BANK1 Register 153" bitfld.quad 0x4C8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4C8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4C8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4C8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4C8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4C8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4D0 "QOSBW_FIX_QOS_BANK[1] [154],QOSBW FIX QOS BANK1 Register 154" bitfld.quad 0x4D0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4D0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4D0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4D0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4D0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4D0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4D8 "QOSBW_FIX_QOS_BANK[1] [155],QOSBW FIX QOS BANK1 Register 155" bitfld.quad 0x4D8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4D8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4D8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4D8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4D8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4D8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4E0 "QOSBW_FIX_QOS_BANK[1] [156],QOSBW FIX QOS BANK1 Register 156" bitfld.quad 0x4E0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4E0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4E0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4E0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4E0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4E0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4E8 "QOSBW_FIX_QOS_BANK[1] [157],QOSBW FIX QOS BANK1 Register 157" bitfld.quad 0x4E8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4E8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4E8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4E8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4E8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4E8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4F0 "QOSBW_FIX_QOS_BANK[1] [158],QOSBW FIX QOS BANK1 Register 158" bitfld.quad 0x4F0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4F0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4F0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4F0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4F0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4F0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x4F8 "QOSBW_FIX_QOS_BANK[1] [159],QOSBW FIX QOS BANK1 Register 159" bitfld.quad 0x4F8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x4F8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x4F8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x4F8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x4F8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x4F8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x500 "QOSBW_FIX_QOS_BANK[1] [160],QOSBW FIX QOS BANK1 Register 160" bitfld.quad 0x500 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x500 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x500 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x500 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x500 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x500 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x508 "QOSBW_FIX_QOS_BANK[1] [161],QOSBW FIX QOS BANK1 Register 161" bitfld.quad 0x508 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x508 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x508 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x508 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x508 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x508 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x510 "QOSBW_FIX_QOS_BANK[1] [162],QOSBW FIX QOS BANK1 Register 162" bitfld.quad 0x510 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x510 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x510 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x510 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x510 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x510 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x518 "QOSBW_FIX_QOS_BANK[1] [163],QOSBW FIX QOS BANK1 Register 163" bitfld.quad 0x518 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x518 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x518 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x518 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x518 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x518 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x520 "QOSBW_FIX_QOS_BANK[1] [164],QOSBW FIX QOS BANK1 Register 164" bitfld.quad 0x520 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x520 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x520 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x520 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x520 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x520 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x528 "QOSBW_FIX_QOS_BANK[1] [165],QOSBW FIX QOS BANK1 Register 165" bitfld.quad 0x528 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x528 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x528 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x528 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x528 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x528 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x530 "QOSBW_FIX_QOS_BANK[1] [166],QOSBW FIX QOS BANK1 Register 166" bitfld.quad 0x530 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x530 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x530 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x530 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x530 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x530 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x538 "QOSBW_FIX_QOS_BANK[1] [167],QOSBW FIX QOS BANK1 Register 167" bitfld.quad 0x538 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x538 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x538 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x538 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x538 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x538 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x540 "QOSBW_FIX_QOS_BANK[1] [168],QOSBW FIX QOS BANK1 Register 168" bitfld.quad 0x540 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x540 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x540 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x540 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x540 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x540 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x548 "QOSBW_FIX_QOS_BANK[1] [169],QOSBW FIX QOS BANK1 Register 169" bitfld.quad 0x548 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x548 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x548 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x548 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x548 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x548 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x550 "QOSBW_FIX_QOS_BANK[1] [170],QOSBW FIX QOS BANK1 Register 170" bitfld.quad 0x550 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x550 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x550 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x550 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x550 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x550 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x558 "QOSBW_FIX_QOS_BANK[1] [171],QOSBW FIX QOS BANK1 Register 171" bitfld.quad 0x558 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x558 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x558 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x558 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x558 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x558 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x560 "QOSBW_FIX_QOS_BANK[1] [172],QOSBW FIX QOS BANK1 Register 172" bitfld.quad 0x560 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x560 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x560 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x560 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x560 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x560 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x568 "QOSBW_FIX_QOS_BANK[1] [173],QOSBW FIX QOS BANK1 Register 173" bitfld.quad 0x568 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x568 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x568 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x568 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x568 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x568 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x570 "QOSBW_FIX_QOS_BANK[1] [174],QOSBW FIX QOS BANK1 Register 174" bitfld.quad 0x570 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x570 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x570 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x570 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x570 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x570 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x578 "QOSBW_FIX_QOS_BANK[1] [175],QOSBW FIX QOS BANK1 Register 175" bitfld.quad 0x578 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x578 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x578 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x578 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x578 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x578 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x580 "QOSBW_FIX_QOS_BANK[1] [176],QOSBW FIX QOS BANK1 Register 176" bitfld.quad 0x580 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x580 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x580 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x580 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x580 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x580 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x588 "QOSBW_FIX_QOS_BANK[1] [177],QOSBW FIX QOS BANK1 Register 177" bitfld.quad 0x588 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x588 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x588 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x588 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x588 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x588 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x590 "QOSBW_FIX_QOS_BANK[1] [178],QOSBW FIX QOS BANK1 Register 178" bitfld.quad 0x590 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x590 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x590 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x590 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x590 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x590 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x598 "QOSBW_FIX_QOS_BANK[1] [179],QOSBW FIX QOS BANK1 Register 179" bitfld.quad 0x598 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x598 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x598 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x598 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x598 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x598 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5A0 "QOSBW_FIX_QOS_BANK[1] [180],QOSBW FIX QOS BANK1 Register 180" bitfld.quad 0x5A0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5A0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5A0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5A0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5A0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5A0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5A8 "QOSBW_FIX_QOS_BANK[1] [181],QOSBW FIX QOS BANK1 Register 181" bitfld.quad 0x5A8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5A8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5A8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5A8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5A8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5A8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5B0 "QOSBW_FIX_QOS_BANK[1] [182],QOSBW FIX QOS BANK1 Register 182" bitfld.quad 0x5B0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5B0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5B0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5B0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5B0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5B0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5B8 "QOSBW_FIX_QOS_BANK[1] [183],QOSBW FIX QOS BANK1 Register 183" bitfld.quad 0x5B8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5B8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5B8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5B8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5B8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5B8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5C0 "QOSBW_FIX_QOS_BANK[1] [184],QOSBW FIX QOS BANK1 Register 184" bitfld.quad 0x5C0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5C0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5C0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5C0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5C0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5C0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5C8 "QOSBW_FIX_QOS_BANK[1] [185],QOSBW FIX QOS BANK1 Register 185" bitfld.quad 0x5C8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5C8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5C8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5C8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5C8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5C8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5D0 "QOSBW_FIX_QOS_BANK[1] [186],QOSBW FIX QOS BANK1 Register 186" bitfld.quad 0x5D0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5D0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5D0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5D0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5D0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5D0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5D8 "QOSBW_FIX_QOS_BANK[1] [187],QOSBW FIX QOS BANK1 Register 187" bitfld.quad 0x5D8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5D8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5D8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5D8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5D8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5D8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5E0 "QOSBW_FIX_QOS_BANK[1] [188],QOSBW FIX QOS BANK1 Register 188" bitfld.quad 0x5E0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5E0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5E0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5E0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5E0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5E0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5E8 "QOSBW_FIX_QOS_BANK[1] [189],QOSBW FIX QOS BANK1 Register 189" bitfld.quad 0x5E8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5E8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5E8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5E8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5E8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5E8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5F0 "QOSBW_FIX_QOS_BANK[1] [190],QOSBW FIX QOS BANK1 Register 190" bitfld.quad 0x5F0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5F0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5F0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5F0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5F0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5F0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x5F8 "QOSBW_FIX_QOS_BANK[1] [191],QOSBW FIX QOS BANK1 Register 191" bitfld.quad 0x5F8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x5F8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x5F8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x5F8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x5F8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x5F8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x600 "QOSBW_FIX_QOS_BANK[1] [192],QOSBW FIX QOS BANK1 Register 192" bitfld.quad 0x600 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x600 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x600 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x600 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x600 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x600 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x608 "QOSBW_FIX_QOS_BANK[1] [193],QOSBW FIX QOS BANK1 Register 193" bitfld.quad 0x608 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x608 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x608 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x608 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x608 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x608 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x610 "QOSBW_FIX_QOS_BANK[1] [194],QOSBW FIX QOS BANK1 Register 194" bitfld.quad 0x610 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x610 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x610 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x610 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x610 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x610 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x618 "QOSBW_FIX_QOS_BANK[1] [195],QOSBW FIX QOS BANK1 Register 195" bitfld.quad 0x618 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x618 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x618 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x618 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x618 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x618 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x620 "QOSBW_FIX_QOS_BANK[1] [196],QOSBW FIX QOS BANK1 Register 196" bitfld.quad 0x620 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x620 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x620 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x620 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x620 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x620 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x628 "QOSBW_FIX_QOS_BANK[1] [197],QOSBW FIX QOS BANK1 Register 197" bitfld.quad 0x628 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x628 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x628 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x628 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x628 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x628 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x630 "QOSBW_FIX_QOS_BANK[1] [198],QOSBW FIX QOS BANK1 Register 198" bitfld.quad 0x630 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x630 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x630 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x630 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x630 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x630 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x638 "QOSBW_FIX_QOS_BANK[1] [199],QOSBW FIX QOS BANK1 Register 199" bitfld.quad 0x638 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x638 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x638 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x638 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x638 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x638 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x640 "QOSBW_FIX_QOS_BANK[1] [200],QOSBW FIX QOS BANK1 Register 200" bitfld.quad 0x640 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x640 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x640 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x640 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x640 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x640 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x648 "QOSBW_FIX_QOS_BANK[1] [201],QOSBW FIX QOS BANK1 Register 201" bitfld.quad 0x648 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x648 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x648 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x648 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x648 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x648 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x650 "QOSBW_FIX_QOS_BANK[1] [202],QOSBW FIX QOS BANK1 Register 202" bitfld.quad 0x650 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x650 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x650 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x650 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x650 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x650 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x658 "QOSBW_FIX_QOS_BANK[1] [203],QOSBW FIX QOS BANK1 Register 203" bitfld.quad 0x658 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x658 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x658 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x658 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x658 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x658 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x660 "QOSBW_FIX_QOS_BANK[1] [204],QOSBW FIX QOS BANK1 Register 204" bitfld.quad 0x660 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x660 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x660 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x660 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x660 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x660 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x668 "QOSBW_FIX_QOS_BANK[1] [205],QOSBW FIX QOS BANK1 Register 205" bitfld.quad 0x668 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x668 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x668 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x668 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x668 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x668 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x670 "QOSBW_FIX_QOS_BANK[1] [206],QOSBW FIX QOS BANK1 Register 206" bitfld.quad 0x670 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x670 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x670 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x670 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x670 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x670 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x678 "QOSBW_FIX_QOS_BANK[1] [207],QOSBW FIX QOS BANK1 Register 207" bitfld.quad 0x678 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x678 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x678 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x678 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x678 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x678 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x680 "QOSBW_FIX_QOS_BANK[1] [208],QOSBW FIX QOS BANK1 Register 208" bitfld.quad 0x680 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x680 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x680 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x680 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x680 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x680 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x688 "QOSBW_FIX_QOS_BANK[1] [209],QOSBW FIX QOS BANK1 Register 209" bitfld.quad 0x688 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x688 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x688 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x688 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x688 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x688 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x690 "QOSBW_FIX_QOS_BANK[1] [210],QOSBW FIX QOS BANK1 Register 210" bitfld.quad 0x690 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x690 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x690 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x690 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x690 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x690 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x698 "QOSBW_FIX_QOS_BANK[1] [211],QOSBW FIX QOS BANK1 Register 211" bitfld.quad 0x698 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x698 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x698 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x698 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x698 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x698 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6A0 "QOSBW_FIX_QOS_BANK[1] [212],QOSBW FIX QOS BANK1 Register 212" bitfld.quad 0x6A0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6A0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6A0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6A0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6A0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6A0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6A8 "QOSBW_FIX_QOS_BANK[1] [213],QOSBW FIX QOS BANK1 Register 213" bitfld.quad 0x6A8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6A8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6A8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6A8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6A8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6A8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6B0 "QOSBW_FIX_QOS_BANK[1] [214],QOSBW FIX QOS BANK1 Register 214" bitfld.quad 0x6B0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6B0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6B0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6B0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6B0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6B0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6B8 "QOSBW_FIX_QOS_BANK[1] [215],QOSBW FIX QOS BANK1 Register 215" bitfld.quad 0x6B8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6B8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6B8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6B8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6B8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6B8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6C0 "QOSBW_FIX_QOS_BANK[1] [216],QOSBW FIX QOS BANK1 Register 216" bitfld.quad 0x6C0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6C0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6C0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6C0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6C0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6C0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6C8 "QOSBW_FIX_QOS_BANK[1] [217],QOSBW FIX QOS BANK1 Register 217" bitfld.quad 0x6C8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6C8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6C8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6C8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6C8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6C8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6D0 "QOSBW_FIX_QOS_BANK[1] [218],QOSBW FIX QOS BANK1 Register 218" bitfld.quad 0x6D0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6D0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6D0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6D0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6D0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6D0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6D8 "QOSBW_FIX_QOS_BANK[1] [219],QOSBW FIX QOS BANK1 Register 219" bitfld.quad 0x6D8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6D8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6D8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6D8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6D8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6D8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6E0 "QOSBW_FIX_QOS_BANK[1] [220],QOSBW FIX QOS BANK1 Register 220" bitfld.quad 0x6E0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6E0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6E0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6E0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6E0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6E0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6E8 "QOSBW_FIX_QOS_BANK[1] [221],QOSBW FIX QOS BANK1 Register 221" bitfld.quad 0x6E8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6E8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6E8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6E8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6E8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6E8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6F0 "QOSBW_FIX_QOS_BANK[1] [222],QOSBW FIX QOS BANK1 Register 222" bitfld.quad 0x6F0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6F0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6F0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6F0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6F0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6F0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x6F8 "QOSBW_FIX_QOS_BANK[1] [223],QOSBW FIX QOS BANK1 Register 223" bitfld.quad 0x6F8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x6F8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x6F8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x6F8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x6F8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x6F8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x700 "QOSBW_FIX_QOS_BANK[1] [224],QOSBW FIX QOS BANK1 Register 224" bitfld.quad 0x700 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x700 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x700 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x700 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x700 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x700 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x708 "QOSBW_FIX_QOS_BANK[1] [225],QOSBW FIX QOS BANK1 Register 225" bitfld.quad 0x708 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x708 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x708 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x708 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x708 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x708 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x710 "QOSBW_FIX_QOS_BANK[1] [226],QOSBW FIX QOS BANK1 Register 226" bitfld.quad 0x710 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x710 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x710 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x710 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x710 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x710 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x718 "QOSBW_FIX_QOS_BANK[1] [227],QOSBW FIX QOS BANK1 Register 227" bitfld.quad 0x718 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x718 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x718 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x718 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x718 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x718 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x720 "QOSBW_FIX_QOS_BANK[1] [228],QOSBW FIX QOS BANK1 Register 228" bitfld.quad 0x720 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x720 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x720 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x720 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x720 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x720 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x728 "QOSBW_FIX_QOS_BANK[1] [229],QOSBW FIX QOS BANK1 Register 229" bitfld.quad 0x728 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x728 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x728 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x728 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x728 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x728 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x730 "QOSBW_FIX_QOS_BANK[1] [230],QOSBW FIX QOS BANK1 Register 230" bitfld.quad 0x730 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x730 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x730 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x730 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x730 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x730 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x738 "QOSBW_FIX_QOS_BANK[1] [231],QOSBW FIX QOS BANK1 Register 231" bitfld.quad 0x738 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x738 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x738 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x738 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x738 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x738 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x740 "QOSBW_FIX_QOS_BANK[1] [232],QOSBW FIX QOS BANK1 Register 232" bitfld.quad 0x740 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x740 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x740 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x740 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x740 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x740 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x748 "QOSBW_FIX_QOS_BANK[1] [233],QOSBW FIX QOS BANK1 Register 233" bitfld.quad 0x748 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x748 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x748 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x748 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x748 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x748 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x750 "QOSBW_FIX_QOS_BANK[1] [234],QOSBW FIX QOS BANK1 Register 234" bitfld.quad 0x750 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x750 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x750 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x750 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x750 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x750 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x758 "QOSBW_FIX_QOS_BANK[1] [235],QOSBW FIX QOS BANK1 Register 235" bitfld.quad 0x758 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x758 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x758 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x758 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x758 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x758 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x760 "QOSBW_FIX_QOS_BANK[1] [236],QOSBW FIX QOS BANK1 Register 236" bitfld.quad 0x760 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x760 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x760 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x760 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x760 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x760 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x768 "QOSBW_FIX_QOS_BANK[1] [237],QOSBW FIX QOS BANK1 Register 237" bitfld.quad 0x768 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x768 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x768 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x768 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x768 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x768 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x770 "QOSBW_FIX_QOS_BANK[1] [238],QOSBW FIX QOS BANK1 Register 238" bitfld.quad 0x770 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x770 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x770 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x770 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x770 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x770 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x778 "QOSBW_FIX_QOS_BANK[1] [239],QOSBW FIX QOS BANK1 Register 239" bitfld.quad 0x778 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x778 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x778 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x778 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x778 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x778 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x780 "QOSBW_FIX_QOS_BANK[1] [240],QOSBW FIX QOS BANK1 Register 240" bitfld.quad 0x780 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x780 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x780 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x780 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x780 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x780 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x788 "QOSBW_FIX_QOS_BANK[1] [241],QOSBW FIX QOS BANK1 Register 241" bitfld.quad 0x788 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x788 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x788 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x788 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x788 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x788 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x790 "QOSBW_FIX_QOS_BANK[1] [242],QOSBW FIX QOS BANK1 Register 242" bitfld.quad 0x790 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x790 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x790 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x790 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x790 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x790 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x798 "QOSBW_FIX_QOS_BANK[1] [243],QOSBW FIX QOS BANK1 Register 243" bitfld.quad 0x798 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x798 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x798 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x798 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x798 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x798 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7A0 "QOSBW_FIX_QOS_BANK[1] [244],QOSBW FIX QOS BANK1 Register 244" bitfld.quad 0x7A0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7A0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7A0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7A0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7A0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7A0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7A8 "QOSBW_FIX_QOS_BANK[1] [245],QOSBW FIX QOS BANK1 Register 245" bitfld.quad 0x7A8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7A8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7A8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7A8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7A8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7A8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7B0 "QOSBW_FIX_QOS_BANK[1] [246],QOSBW FIX QOS BANK1 Register 246" bitfld.quad 0x7B0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7B0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7B0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7B0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7B0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7B0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7B8 "QOSBW_FIX_QOS_BANK[1] [247],QOSBW FIX QOS BANK1 Register 247" bitfld.quad 0x7B8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7B8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7B8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7B8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7B8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7B8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7C0 "QOSBW_FIX_QOS_BANK[1] [248],QOSBW FIX QOS BANK1 Register 248" bitfld.quad 0x7C0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7C0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7C0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7C0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7C0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7C0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7C8 "QOSBW_FIX_QOS_BANK[1] [249],QOSBW FIX QOS BANK1 Register 249" bitfld.quad 0x7C8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7C8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7C8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7C8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7C8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7C8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7D0 "QOSBW_FIX_QOS_BANK[1] [250],QOSBW FIX QOS BANK1 Register 250" bitfld.quad 0x7D0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7D0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7D0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7D0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7D0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7D0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7D8 "QOSBW_FIX_QOS_BANK[1] [251],QOSBW FIX QOS BANK1 Register 251" bitfld.quad 0x7D8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7D8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7D8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7D8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7D8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7D8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7E0 "QOSBW_FIX_QOS_BANK[1] [252],QOSBW FIX QOS BANK1 Register 252" bitfld.quad 0x7E0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7E0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7E0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7E0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7E0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7E0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7E8 "QOSBW_FIX_QOS_BANK[1] [253],QOSBW FIX QOS BANK1 Register 253" bitfld.quad 0x7E8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7E8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7E8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7E8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7E8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7E8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7F0 "QOSBW_FIX_QOS_BANK[1] [254],QOSBW FIX QOS BANK1 Register 254" bitfld.quad 0x7F0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7F0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7F0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7F0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7F0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7F0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x7F8 "QOSBW_FIX_QOS_BANK[1] [255],QOSBW FIX QOS BANK1 Register 255" bitfld.quad 0x7F8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x7F8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x7F8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x7F8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x7F8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x7F8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x800 "QOSBW_FIX_QOS_BANK[1] [256],QOSBW FIX QOS BANK1 Register 256" bitfld.quad 0x800 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x800 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x800 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x800 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x800 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x800 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x808 "QOSBW_FIX_QOS_BANK[1] [257],QOSBW FIX QOS BANK1 Register 257" bitfld.quad 0x808 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x808 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x808 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x808 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x808 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x808 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x810 "QOSBW_FIX_QOS_BANK[1] [258],QOSBW FIX QOS BANK1 Register 258" bitfld.quad 0x810 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x810 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x810 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x810 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x810 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x810 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x818 "QOSBW_FIX_QOS_BANK[1] [259],QOSBW FIX QOS BANK1 Register 259" bitfld.quad 0x818 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x818 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x818 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x818 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x818 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x818 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x820 "QOSBW_FIX_QOS_BANK[1] [260],QOSBW FIX QOS BANK1 Register 260" bitfld.quad 0x820 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x820 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x820 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x820 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x820 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x820 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x828 "QOSBW_FIX_QOS_BANK[1] [261],QOSBW FIX QOS BANK1 Register 261" bitfld.quad 0x828 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x828 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x828 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x828 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x828 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x828 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x830 "QOSBW_FIX_QOS_BANK[1] [262],QOSBW FIX QOS BANK1 Register 262" bitfld.quad 0x830 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x830 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x830 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x830 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x830 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x830 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x838 "QOSBW_FIX_QOS_BANK[1] [263],QOSBW FIX QOS BANK1 Register 263" bitfld.quad 0x838 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x838 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x838 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x838 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x838 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x838 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x840 "QOSBW_FIX_QOS_BANK[1] [264],QOSBW FIX QOS BANK1 Register 264" bitfld.quad 0x840 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x840 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x840 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x840 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x840 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x840 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x848 "QOSBW_FIX_QOS_BANK[1] [265],QOSBW FIX QOS BANK1 Register 265" bitfld.quad 0x848 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x848 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x848 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x848 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x848 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x848 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x850 "QOSBW_FIX_QOS_BANK[1] [266],QOSBW FIX QOS BANK1 Register 266" bitfld.quad 0x850 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x850 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x850 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x850 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x850 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x850 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x858 "QOSBW_FIX_QOS_BANK[1] [267],QOSBW FIX QOS BANK1 Register 267" bitfld.quad 0x858 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x858 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x858 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x858 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x858 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x858 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x860 "QOSBW_FIX_QOS_BANK[1] [268],QOSBW FIX QOS BANK1 Register 268" bitfld.quad 0x860 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x860 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x860 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x860 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x860 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x860 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x868 "QOSBW_FIX_QOS_BANK[1] [269],QOSBW FIX QOS BANK1 Register 269" bitfld.quad 0x868 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x868 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x868 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x868 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x868 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x868 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x870 "QOSBW_FIX_QOS_BANK[1] [270],QOSBW FIX QOS BANK1 Register 270" bitfld.quad 0x870 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x870 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x870 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x870 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x870 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x870 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x878 "QOSBW_FIX_QOS_BANK[1] [271],QOSBW FIX QOS BANK1 Register 271" bitfld.quad 0x878 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x878 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x878 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x878 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x878 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x878 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x880 "QOSBW_FIX_QOS_BANK[1] [272],QOSBW FIX QOS BANK1 Register 272" bitfld.quad 0x880 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x880 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x880 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x880 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x880 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x880 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x888 "QOSBW_FIX_QOS_BANK[1] [273],QOSBW FIX QOS BANK1 Register 273" bitfld.quad 0x888 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x888 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x888 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x888 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x888 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x888 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x890 "QOSBW_FIX_QOS_BANK[1] [274],QOSBW FIX QOS BANK1 Register 274" bitfld.quad 0x890 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x890 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x890 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x890 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x890 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x890 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x898 "QOSBW_FIX_QOS_BANK[1] [275],QOSBW FIX QOS BANK1 Register 275" bitfld.quad 0x898 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x898 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x898 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x898 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x898 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x898 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8A0 "QOSBW_FIX_QOS_BANK[1] [276],QOSBW FIX QOS BANK1 Register 276" bitfld.quad 0x8A0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8A0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8A0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8A0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8A0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8A0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8A8 "QOSBW_FIX_QOS_BANK[1] [277],QOSBW FIX QOS BANK1 Register 277" bitfld.quad 0x8A8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8A8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8A8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8A8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8A8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8A8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8B0 "QOSBW_FIX_QOS_BANK[1] [278],QOSBW FIX QOS BANK1 Register 278" bitfld.quad 0x8B0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8B0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8B0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8B0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8B0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8B0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8B8 "QOSBW_FIX_QOS_BANK[1] [279],QOSBW FIX QOS BANK1 Register 279" bitfld.quad 0x8B8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8B8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8B8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8B8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8B8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8B8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8C0 "QOSBW_FIX_QOS_BANK[1] [280],QOSBW FIX QOS BANK1 Register 280" bitfld.quad 0x8C0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8C0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8C0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8C0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8C0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8C0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8C8 "QOSBW_FIX_QOS_BANK[1] [281],QOSBW FIX QOS BANK1 Register 281" bitfld.quad 0x8C8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8C8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8C8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8C8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8C8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8C8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8D0 "QOSBW_FIX_QOS_BANK[1] [282],QOSBW FIX QOS BANK1 Register 282" bitfld.quad 0x8D0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8D0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8D0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8D0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8D0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8D0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8D8 "QOSBW_FIX_QOS_BANK[1] [283],QOSBW FIX QOS BANK1 Register 283" bitfld.quad 0x8D8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8D8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8D8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8D8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8D8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8D8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8E0 "QOSBW_FIX_QOS_BANK[1] [284],QOSBW FIX QOS BANK1 Register 284" bitfld.quad 0x8E0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8E0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8E0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8E0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8E0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8E0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8E8 "QOSBW_FIX_QOS_BANK[1] [285],QOSBW FIX QOS BANK1 Register 285" bitfld.quad 0x8E8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8E8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8E8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8E8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8E8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8E8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8F0 "QOSBW_FIX_QOS_BANK[1] [286],QOSBW FIX QOS BANK1 Register 286" bitfld.quad 0x8F0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8F0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8F0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8F0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8F0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8F0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x8F8 "QOSBW_FIX_QOS_BANK[1] [287],QOSBW FIX QOS BANK1 Register 287" bitfld.quad 0x8F8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x8F8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x8F8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x8F8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x8F8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x8F8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x900 "QOSBW_FIX_QOS_BANK[1] [288],QOSBW FIX QOS BANK1 Register 288" bitfld.quad 0x900 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x900 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x900 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x900 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x900 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x900 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x908 "QOSBW_FIX_QOS_BANK[1] [289],QOSBW FIX QOS BANK1 Register 289" bitfld.quad 0x908 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x908 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x908 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x908 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x908 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x908 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x910 "QOSBW_FIX_QOS_BANK[1] [290],QOSBW FIX QOS BANK1 Register 290" bitfld.quad 0x910 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x910 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x910 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x910 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x910 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x910 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x918 "QOSBW_FIX_QOS_BANK[1] [291],QOSBW FIX QOS BANK1 Register 291" bitfld.quad 0x918 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x918 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x918 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x918 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x918 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x918 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x920 "QOSBW_FIX_QOS_BANK[1] [292],QOSBW FIX QOS BANK1 Register 292" bitfld.quad 0x920 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x920 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x920 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x920 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x920 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x920 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x928 "QOSBW_FIX_QOS_BANK[1] [293],QOSBW FIX QOS BANK1 Register 293" bitfld.quad 0x928 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x928 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x928 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x928 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x928 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x928 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x930 "QOSBW_FIX_QOS_BANK[1] [294],QOSBW FIX QOS BANK1 Register 294" bitfld.quad 0x930 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x930 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x930 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x930 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x930 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x930 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x938 "QOSBW_FIX_QOS_BANK[1] [295],QOSBW FIX QOS BANK1 Register 295" bitfld.quad 0x938 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x938 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x938 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x938 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x938 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x938 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x940 "QOSBW_FIX_QOS_BANK[1] [296],QOSBW FIX QOS BANK1 Register 296" bitfld.quad 0x940 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x940 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x940 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x940 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x940 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x940 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x948 "QOSBW_FIX_QOS_BANK[1] [297],QOSBW FIX QOS BANK1 Register 297" bitfld.quad 0x948 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x948 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x948 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x948 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x948 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x948 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x950 "QOSBW_FIX_QOS_BANK[1] [298],QOSBW FIX QOS BANK1 Register 298" bitfld.quad 0x950 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x950 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x950 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x950 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x950 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x950 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x958 "QOSBW_FIX_QOS_BANK[1] [299],QOSBW FIX QOS BANK1 Register 299" bitfld.quad 0x958 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x958 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x958 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x958 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x958 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x958 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x960 "QOSBW_FIX_QOS_BANK[1] [300],QOSBW FIX QOS BANK1 Register 300" bitfld.quad 0x960 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x960 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x960 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x960 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x960 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x960 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x968 "QOSBW_FIX_QOS_BANK[1] [301],QOSBW FIX QOS BANK1 Register 301" bitfld.quad 0x968 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x968 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x968 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x968 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x968 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x968 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x970 "QOSBW_FIX_QOS_BANK[1] [302],QOSBW FIX QOS BANK1 Register 302" bitfld.quad 0x970 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x970 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x970 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x970 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x970 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x970 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x978 "QOSBW_FIX_QOS_BANK[1] [303],QOSBW FIX QOS BANK1 Register 303" bitfld.quad 0x978 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x978 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x978 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x978 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x978 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x978 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x980 "QOSBW_FIX_QOS_BANK[1] [304],QOSBW FIX QOS BANK1 Register 304" bitfld.quad 0x980 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x980 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x980 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x980 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x980 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x980 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x988 "QOSBW_FIX_QOS_BANK[1] [305],QOSBW FIX QOS BANK1 Register 305" bitfld.quad 0x988 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x988 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x988 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x988 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x988 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x988 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x990 "QOSBW_FIX_QOS_BANK[1] [306],QOSBW FIX QOS BANK1 Register 306" bitfld.quad 0x990 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x990 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x990 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x990 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x990 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x990 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x998 "QOSBW_FIX_QOS_BANK[1] [307],QOSBW FIX QOS BANK1 Register 307" bitfld.quad 0x998 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x998 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x998 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x998 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x998 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x998 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9A0 "QOSBW_FIX_QOS_BANK[1] [308],QOSBW FIX QOS BANK1 Register 308" bitfld.quad 0x9A0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9A0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9A0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9A0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9A0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9A0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9A8 "QOSBW_FIX_QOS_BANK[1] [309],QOSBW FIX QOS BANK1 Register 309" bitfld.quad 0x9A8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9A8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9A8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9A8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9A8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9A8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9B0 "QOSBW_FIX_QOS_BANK[1] [310],QOSBW FIX QOS BANK1 Register 310" bitfld.quad 0x9B0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9B0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9B0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9B0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9B0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9B0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9B8 "QOSBW_FIX_QOS_BANK[1] [311],QOSBW FIX QOS BANK1 Register 311" bitfld.quad 0x9B8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9B8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9B8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9B8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9B8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9B8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9C0 "QOSBW_FIX_QOS_BANK[1] [312],QOSBW FIX QOS BANK1 Register 312" bitfld.quad 0x9C0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9C0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9C0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9C0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9C0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9C0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9C8 "QOSBW_FIX_QOS_BANK[1] [313],QOSBW FIX QOS BANK1 Register 313" bitfld.quad 0x9C8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9C8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9C8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9C8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9C8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9C8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9D0 "QOSBW_FIX_QOS_BANK[1] [314],QOSBW FIX QOS BANK1 Register 314" bitfld.quad 0x9D0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9D0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9D0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9D0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9D0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9D0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9D8 "QOSBW_FIX_QOS_BANK[1] [315],QOSBW FIX QOS BANK1 Register 315" bitfld.quad 0x9D8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9D8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9D8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9D8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9D8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9D8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9E0 "QOSBW_FIX_QOS_BANK[1] [316],QOSBW FIX QOS BANK1 Register 316" bitfld.quad 0x9E0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9E0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9E0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9E0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9E0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9E0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9E8 "QOSBW_FIX_QOS_BANK[1] [317],QOSBW FIX QOS BANK1 Register 317" bitfld.quad 0x9E8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9E8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9E8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9E8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9E8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9E8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9F0 "QOSBW_FIX_QOS_BANK[1] [318],QOSBW FIX QOS BANK1 Register 318" bitfld.quad 0x9F0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9F0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9F0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9F0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9F0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9F0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0x9F8 "QOSBW_FIX_QOS_BANK[1] [319],QOSBW FIX QOS BANK1 Register 319" bitfld.quad 0x9F8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0x9F8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0x9F8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0x9F8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0x9F8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0x9F8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA00 "QOSBW_FIX_QOS_BANK[1] [320],QOSBW FIX QOS BANK1 Register 320" bitfld.quad 0xA00 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA00 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA00 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA00 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA00 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA00 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA08 "QOSBW_FIX_QOS_BANK[1] [321],QOSBW FIX QOS BANK1 Register 321" bitfld.quad 0xA08 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA08 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA08 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA08 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA08 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA08 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA10 "QOSBW_FIX_QOS_BANK[1] [322],QOSBW FIX QOS BANK1 Register 322" bitfld.quad 0xA10 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA10 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA10 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA10 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA10 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA10 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA18 "QOSBW_FIX_QOS_BANK[1] [323],QOSBW FIX QOS BANK1 Register 323" bitfld.quad 0xA18 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA18 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA18 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA18 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA18 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA18 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA20 "QOSBW_FIX_QOS_BANK[1] [324],QOSBW FIX QOS BANK1 Register 324" bitfld.quad 0xA20 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA20 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA20 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA20 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA20 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA20 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA28 "QOSBW_FIX_QOS_BANK[1] [325],QOSBW FIX QOS BANK1 Register 325" bitfld.quad 0xA28 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA28 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA28 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA28 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA28 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA28 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA30 "QOSBW_FIX_QOS_BANK[1] [326],QOSBW FIX QOS BANK1 Register 326" bitfld.quad 0xA30 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA30 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA30 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA30 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA30 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA30 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA38 "QOSBW_FIX_QOS_BANK[1] [327],QOSBW FIX QOS BANK1 Register 327" bitfld.quad 0xA38 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA38 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA38 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA38 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA38 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA38 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA40 "QOSBW_FIX_QOS_BANK[1] [328],QOSBW FIX QOS BANK1 Register 328" bitfld.quad 0xA40 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA40 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA40 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA40 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA40 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA40 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA48 "QOSBW_FIX_QOS_BANK[1] [329],QOSBW FIX QOS BANK1 Register 329" bitfld.quad 0xA48 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA48 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA48 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA48 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA48 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA48 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA50 "QOSBW_FIX_QOS_BANK[1] [330],QOSBW FIX QOS BANK1 Register 330" bitfld.quad 0xA50 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA50 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA50 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA50 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA50 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA50 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA58 "QOSBW_FIX_QOS_BANK[1] [331],QOSBW FIX QOS BANK1 Register 331" bitfld.quad 0xA58 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA58 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA58 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA58 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA58 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA58 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA60 "QOSBW_FIX_QOS_BANK[1] [332],QOSBW FIX QOS BANK1 Register 332" bitfld.quad 0xA60 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA60 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA60 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA60 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA60 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA60 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA68 "QOSBW_FIX_QOS_BANK[1] [333],QOSBW FIX QOS BANK1 Register 333" bitfld.quad 0xA68 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA68 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA68 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA68 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA68 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA68 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA70 "QOSBW_FIX_QOS_BANK[1] [334],QOSBW FIX QOS BANK1 Register 334" bitfld.quad 0xA70 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA70 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA70 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA70 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA70 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA70 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA78 "QOSBW_FIX_QOS_BANK[1] [335],QOSBW FIX QOS BANK1 Register 335" bitfld.quad 0xA78 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA78 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA78 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA78 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA78 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA78 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA80 "QOSBW_FIX_QOS_BANK[1] [336],QOSBW FIX QOS BANK1 Register 336" bitfld.quad 0xA80 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA80 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA80 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA80 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA80 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA80 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA88 "QOSBW_FIX_QOS_BANK[1] [337],QOSBW FIX QOS BANK1 Register 337" bitfld.quad 0xA88 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA88 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA88 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA88 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA88 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA88 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA90 "QOSBW_FIX_QOS_BANK[1] [338],QOSBW FIX QOS BANK1 Register 338" bitfld.quad 0xA90 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA90 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA90 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA90 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA90 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA90 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xA98 "QOSBW_FIX_QOS_BANK[1] [339],QOSBW FIX QOS BANK1 Register 339" bitfld.quad 0xA98 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xA98 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xA98 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xA98 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xA98 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xA98 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAA0 "QOSBW_FIX_QOS_BANK[1] [340],QOSBW FIX QOS BANK1 Register 340" bitfld.quad 0xAA0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAA0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAA0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAA0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAA0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAA0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAA8 "QOSBW_FIX_QOS_BANK[1] [341],QOSBW FIX QOS BANK1 Register 341" bitfld.quad 0xAA8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAA8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAA8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAA8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAA8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAA8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAB0 "QOSBW_FIX_QOS_BANK[1] [342],QOSBW FIX QOS BANK1 Register 342" bitfld.quad 0xAB0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAB0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAB0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAB0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAB0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAB0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAB8 "QOSBW_FIX_QOS_BANK[1] [343],QOSBW FIX QOS BANK1 Register 343" bitfld.quad 0xAB8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAB8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAB8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAB8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAB8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAB8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAC0 "QOSBW_FIX_QOS_BANK[1] [344],QOSBW FIX QOS BANK1 Register 344" bitfld.quad 0xAC0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAC0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAC0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAC0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAC0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAC0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAC8 "QOSBW_FIX_QOS_BANK[1] [345],QOSBW FIX QOS BANK1 Register 345" bitfld.quad 0xAC8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAC8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAC8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAC8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAC8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAC8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAD0 "QOSBW_FIX_QOS_BANK[1] [346],QOSBW FIX QOS BANK1 Register 346" bitfld.quad 0xAD0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAD0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAD0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAD0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAD0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAD0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAD8 "QOSBW_FIX_QOS_BANK[1] [347],QOSBW FIX QOS BANK1 Register 347" bitfld.quad 0xAD8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAD8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAD8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAD8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAD8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAD8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAE0 "QOSBW_FIX_QOS_BANK[1] [348],QOSBW FIX QOS BANK1 Register 348" bitfld.quad 0xAE0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAE0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAE0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAE0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAE0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAE0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAE8 "QOSBW_FIX_QOS_BANK[1] [349],QOSBW FIX QOS BANK1 Register 349" bitfld.quad 0xAE8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAE8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAE8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAE8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAE8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAE8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAF0 "QOSBW_FIX_QOS_BANK[1] [350],QOSBW FIX QOS BANK1 Register 350" bitfld.quad 0xAF0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAF0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAF0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAF0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAF0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAF0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xAF8 "QOSBW_FIX_QOS_BANK[1] [351],QOSBW FIX QOS BANK1 Register 351" bitfld.quad 0xAF8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xAF8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xAF8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xAF8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xAF8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xAF8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB00 "QOSBW_FIX_QOS_BANK[1] [352],QOSBW FIX QOS BANK1 Register 352" bitfld.quad 0xB00 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB00 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB00 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB00 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB00 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB00 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB08 "QOSBW_FIX_QOS_BANK[1] [353],QOSBW FIX QOS BANK1 Register 353" bitfld.quad 0xB08 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB08 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB08 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB08 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB08 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB08 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB10 "QOSBW_FIX_QOS_BANK[1] [354],QOSBW FIX QOS BANK1 Register 354" bitfld.quad 0xB10 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB10 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB10 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB10 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB10 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB10 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB18 "QOSBW_FIX_QOS_BANK[1] [355],QOSBW FIX QOS BANK1 Register 355" bitfld.quad 0xB18 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB18 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB18 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB18 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB18 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB18 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB20 "QOSBW_FIX_QOS_BANK[1] [356],QOSBW FIX QOS BANK1 Register 356" bitfld.quad 0xB20 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB20 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB20 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB20 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB20 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB20 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB28 "QOSBW_FIX_QOS_BANK[1] [357],QOSBW FIX QOS BANK1 Register 357" bitfld.quad 0xB28 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB28 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB28 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB28 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB28 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB28 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB30 "QOSBW_FIX_QOS_BANK[1] [358],QOSBW FIX QOS BANK1 Register 358" bitfld.quad 0xB30 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB30 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB30 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB30 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB30 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB30 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB38 "QOSBW_FIX_QOS_BANK[1] [359],QOSBW FIX QOS BANK1 Register 359" bitfld.quad 0xB38 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB38 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB38 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB38 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB38 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB38 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB40 "QOSBW_FIX_QOS_BANK[1] [360],QOSBW FIX QOS BANK1 Register 360" bitfld.quad 0xB40 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB40 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB40 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB40 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB40 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB40 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB48 "QOSBW_FIX_QOS_BANK[1] [361],QOSBW FIX QOS BANK1 Register 361" bitfld.quad 0xB48 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB48 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB48 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB48 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB48 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB48 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB50 "QOSBW_FIX_QOS_BANK[1] [362],QOSBW FIX QOS BANK1 Register 362" bitfld.quad 0xB50 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB50 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB50 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB50 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB50 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB50 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB58 "QOSBW_FIX_QOS_BANK[1] [363],QOSBW FIX QOS BANK1 Register 363" bitfld.quad 0xB58 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB58 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB58 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB58 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB58 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB58 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB60 "QOSBW_FIX_QOS_BANK[1] [364],QOSBW FIX QOS BANK1 Register 364" bitfld.quad 0xB60 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB60 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB60 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB60 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB60 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB60 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB68 "QOSBW_FIX_QOS_BANK[1] [365],QOSBW FIX QOS BANK1 Register 365" bitfld.quad 0xB68 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB68 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB68 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB68 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB68 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB68 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB70 "QOSBW_FIX_QOS_BANK[1] [366],QOSBW FIX QOS BANK1 Register 366" bitfld.quad 0xB70 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB70 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB70 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB70 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB70 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB70 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB78 "QOSBW_FIX_QOS_BANK[1] [367],QOSBW FIX QOS BANK1 Register 367" bitfld.quad 0xB78 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB78 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB78 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB78 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB78 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB78 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB80 "QOSBW_FIX_QOS_BANK[1] [368],QOSBW FIX QOS BANK1 Register 368" bitfld.quad 0xB80 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB80 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB80 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB80 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB80 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB80 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB88 "QOSBW_FIX_QOS_BANK[1] [369],QOSBW FIX QOS BANK1 Register 369" bitfld.quad 0xB88 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB88 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB88 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB88 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB88 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB88 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB90 "QOSBW_FIX_QOS_BANK[1] [370],QOSBW FIX QOS BANK1 Register 370" bitfld.quad 0xB90 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB90 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB90 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB90 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB90 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB90 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xB98 "QOSBW_FIX_QOS_BANK[1] [371],QOSBW FIX QOS BANK1 Register 371" bitfld.quad 0xB98 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xB98 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xB98 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xB98 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xB98 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xB98 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBA0 "QOSBW_FIX_QOS_BANK[1] [372],QOSBW FIX QOS BANK1 Register 372" bitfld.quad 0xBA0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBA0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBA0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBA0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBA0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBA0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBA8 "QOSBW_FIX_QOS_BANK[1] [373],QOSBW FIX QOS BANK1 Register 373" bitfld.quad 0xBA8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBA8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBA8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBA8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBA8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBA8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBB0 "QOSBW_FIX_QOS_BANK[1] [374],QOSBW FIX QOS BANK1 Register 374" bitfld.quad 0xBB0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBB0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBB0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBB0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBB0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBB0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBB8 "QOSBW_FIX_QOS_BANK[1] [375],QOSBW FIX QOS BANK1 Register 375" bitfld.quad 0xBB8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBB8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBB8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBB8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBB8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBB8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBC0 "QOSBW_FIX_QOS_BANK[1] [376],QOSBW FIX QOS BANK1 Register 376" bitfld.quad 0xBC0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBC0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBC0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBC0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBC0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBC0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBC8 "QOSBW_FIX_QOS_BANK[1] [377],QOSBW FIX QOS BANK1 Register 377" bitfld.quad 0xBC8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBC8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBC8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBC8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBC8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBC8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBD0 "QOSBW_FIX_QOS_BANK[1] [378],QOSBW FIX QOS BANK1 Register 378" bitfld.quad 0xBD0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBD0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBD0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBD0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBD0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBD0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBD8 "QOSBW_FIX_QOS_BANK[1] [379],QOSBW FIX QOS BANK1 Register 379" bitfld.quad 0xBD8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBD8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBD8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBD8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBD8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBD8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBE0 "QOSBW_FIX_QOS_BANK[1] [380],QOSBW FIX QOS BANK1 Register 380" bitfld.quad 0xBE0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBE0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBE0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBE0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBE0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBE0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBE8 "QOSBW_FIX_QOS_BANK[1] [381],QOSBW FIX QOS BANK1 Register 381" bitfld.quad 0xBE8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBE8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBE8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBE8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBE8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBE8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBF0 "QOSBW_FIX_QOS_BANK[1] [382],QOSBW FIX QOS BANK1 Register 382" bitfld.quad 0xBF0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBF0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBF0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBF0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBF0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBF0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xBF8 "QOSBW_FIX_QOS_BANK[1] [383],QOSBW FIX QOS BANK1 Register 383" bitfld.quad 0xBF8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xBF8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xBF8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xBF8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xBF8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xBF8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC00 "QOSBW_FIX_QOS_BANK[1] [384],QOSBW FIX QOS BANK1 Register 384" bitfld.quad 0xC00 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC00 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC00 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC00 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC00 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC00 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC08 "QOSBW_FIX_QOS_BANK[1] [385],QOSBW FIX QOS BANK1 Register 385" bitfld.quad 0xC08 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC08 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC08 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC08 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC08 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC08 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC10 "QOSBW_FIX_QOS_BANK[1] [386],QOSBW FIX QOS BANK1 Register 386" bitfld.quad 0xC10 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC10 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC10 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC10 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC10 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC10 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC18 "QOSBW_FIX_QOS_BANK[1] [387],QOSBW FIX QOS BANK1 Register 387" bitfld.quad 0xC18 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC18 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC18 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC18 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC18 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC18 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC20 "QOSBW_FIX_QOS_BANK[1] [388],QOSBW FIX QOS BANK1 Register 388" bitfld.quad 0xC20 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC20 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC20 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC20 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC20 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC20 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC28 "QOSBW_FIX_QOS_BANK[1] [389],QOSBW FIX QOS BANK1 Register 389" bitfld.quad 0xC28 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC28 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC28 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC28 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC28 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC28 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC30 "QOSBW_FIX_QOS_BANK[1] [390],QOSBW FIX QOS BANK1 Register 390" bitfld.quad 0xC30 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC30 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC30 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC30 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC30 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC30 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC38 "QOSBW_FIX_QOS_BANK[1] [391],QOSBW FIX QOS BANK1 Register 391" bitfld.quad 0xC38 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC38 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC38 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC38 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC38 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC38 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC40 "QOSBW_FIX_QOS_BANK[1] [392],QOSBW FIX QOS BANK1 Register 392" bitfld.quad 0xC40 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC40 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC40 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC40 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC40 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC40 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC48 "QOSBW_FIX_QOS_BANK[1] [393],QOSBW FIX QOS BANK1 Register 393" bitfld.quad 0xC48 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC48 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC48 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC48 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC48 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC48 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC50 "QOSBW_FIX_QOS_BANK[1] [394],QOSBW FIX QOS BANK1 Register 394" bitfld.quad 0xC50 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC50 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC50 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC50 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC50 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC50 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC58 "QOSBW_FIX_QOS_BANK[1] [395],QOSBW FIX QOS BANK1 Register 395" bitfld.quad 0xC58 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC58 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC58 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC58 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC58 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC58 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC60 "QOSBW_FIX_QOS_BANK[1] [396],QOSBW FIX QOS BANK1 Register 396" bitfld.quad 0xC60 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC60 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC60 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC60 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC60 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC60 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC68 "QOSBW_FIX_QOS_BANK[1] [397],QOSBW FIX QOS BANK1 Register 397" bitfld.quad 0xC68 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC68 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC68 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC68 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC68 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC68 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC70 "QOSBW_FIX_QOS_BANK[1] [398],QOSBW FIX QOS BANK1 Register 398" bitfld.quad 0xC70 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC70 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC70 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC70 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC70 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC70 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC78 "QOSBW_FIX_QOS_BANK[1] [399],QOSBW FIX QOS BANK1 Register 399" bitfld.quad 0xC78 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC78 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC78 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC78 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC78 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC78 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC80 "QOSBW_FIX_QOS_BANK[1] [400],QOSBW FIX QOS BANK1 Register 400" bitfld.quad 0xC80 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC80 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC80 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC80 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC80 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC80 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC88 "QOSBW_FIX_QOS_BANK[1] [401],QOSBW FIX QOS BANK1 Register 401" bitfld.quad 0xC88 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC88 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC88 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC88 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC88 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC88 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC90 "QOSBW_FIX_QOS_BANK[1] [402],QOSBW FIX QOS BANK1 Register 402" bitfld.quad 0xC90 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC90 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC90 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC90 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC90 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC90 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xC98 "QOSBW_FIX_QOS_BANK[1] [403],QOSBW FIX QOS BANK1 Register 403" bitfld.quad 0xC98 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xC98 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xC98 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xC98 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xC98 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xC98 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCA0 "QOSBW_FIX_QOS_BANK[1] [404],QOSBW FIX QOS BANK1 Register 404" bitfld.quad 0xCA0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCA0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCA0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCA0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCA0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCA0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCA8 "QOSBW_FIX_QOS_BANK[1] [405],QOSBW FIX QOS BANK1 Register 405" bitfld.quad 0xCA8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCA8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCA8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCA8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCA8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCA8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCB0 "QOSBW_FIX_QOS_BANK[1] [406],QOSBW FIX QOS BANK1 Register 406" bitfld.quad 0xCB0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCB0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCB0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCB0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCB0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCB0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCB8 "QOSBW_FIX_QOS_BANK[1] [407],QOSBW FIX QOS BANK1 Register 407" bitfld.quad 0xCB8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCB8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCB8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCB8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCB8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCB8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCC0 "QOSBW_FIX_QOS_BANK[1] [408],QOSBW FIX QOS BANK1 Register 408" bitfld.quad 0xCC0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCC0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCC0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCC0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCC0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCC0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCC8 "QOSBW_FIX_QOS_BANK[1] [409],QOSBW FIX QOS BANK1 Register 409" bitfld.quad 0xCC8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCC8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCC8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCC8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCC8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCC8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCD0 "QOSBW_FIX_QOS_BANK[1] [410],QOSBW FIX QOS BANK1 Register 410" bitfld.quad 0xCD0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCD0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCD0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCD0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCD0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCD0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCD8 "QOSBW_FIX_QOS_BANK[1] [411],QOSBW FIX QOS BANK1 Register 411" bitfld.quad 0xCD8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCD8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCD8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCD8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCD8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCD8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCE0 "QOSBW_FIX_QOS_BANK[1] [412],QOSBW FIX QOS BANK1 Register 412" bitfld.quad 0xCE0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCE0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCE0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCE0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCE0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCE0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCE8 "QOSBW_FIX_QOS_BANK[1] [413],QOSBW FIX QOS BANK1 Register 413" bitfld.quad 0xCE8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCE8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCE8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCE8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCE8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCE8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCF0 "QOSBW_FIX_QOS_BANK[1] [414],QOSBW FIX QOS BANK1 Register 414" bitfld.quad 0xCF0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCF0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCF0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCF0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCF0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCF0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xCF8 "QOSBW_FIX_QOS_BANK[1] [415],QOSBW FIX QOS BANK1 Register 415" bitfld.quad 0xCF8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xCF8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xCF8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xCF8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xCF8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xCF8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD00 "QOSBW_FIX_QOS_BANK[1] [416],QOSBW FIX QOS BANK1 Register 416" bitfld.quad 0xD00 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD00 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD00 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD00 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD00 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD00 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD08 "QOSBW_FIX_QOS_BANK[1] [417],QOSBW FIX QOS BANK1 Register 417" bitfld.quad 0xD08 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD08 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD08 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD08 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD08 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD08 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD10 "QOSBW_FIX_QOS_BANK[1] [418],QOSBW FIX QOS BANK1 Register 418" bitfld.quad 0xD10 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD10 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD10 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD10 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD10 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD10 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD18 "QOSBW_FIX_QOS_BANK[1] [419],QOSBW FIX QOS BANK1 Register 419" bitfld.quad 0xD18 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD18 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD18 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD18 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD18 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD18 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD20 "QOSBW_FIX_QOS_BANK[1] [420],QOSBW FIX QOS BANK1 Register 420" bitfld.quad 0xD20 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD20 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD20 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD20 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD20 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD20 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD28 "QOSBW_FIX_QOS_BANK[1] [421],QOSBW FIX QOS BANK1 Register 421" bitfld.quad 0xD28 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD28 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD28 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD28 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD28 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD28 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD30 "QOSBW_FIX_QOS_BANK[1] [422],QOSBW FIX QOS BANK1 Register 422" bitfld.quad 0xD30 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD30 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD30 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD30 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD30 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD30 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD38 "QOSBW_FIX_QOS_BANK[1] [423],QOSBW FIX QOS BANK1 Register 423" bitfld.quad 0xD38 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD38 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD38 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD38 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD38 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD38 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD40 "QOSBW_FIX_QOS_BANK[1] [424],QOSBW FIX QOS BANK1 Register 424" bitfld.quad 0xD40 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD40 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD40 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD40 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD40 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD40 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD48 "QOSBW_FIX_QOS_BANK[1] [425],QOSBW FIX QOS BANK1 Register 425" bitfld.quad 0xD48 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD48 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD48 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD48 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD48 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD48 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD50 "QOSBW_FIX_QOS_BANK[1] [426],QOSBW FIX QOS BANK1 Register 426" bitfld.quad 0xD50 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD50 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD50 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD50 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD50 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD50 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD58 "QOSBW_FIX_QOS_BANK[1] [427],QOSBW FIX QOS BANK1 Register 427" bitfld.quad 0xD58 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD58 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD58 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD58 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD58 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD58 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD60 "QOSBW_FIX_QOS_BANK[1] [428],QOSBW FIX QOS BANK1 Register 428" bitfld.quad 0xD60 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD60 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD60 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD60 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD60 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD60 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD68 "QOSBW_FIX_QOS_BANK[1] [429],QOSBW FIX QOS BANK1 Register 429" bitfld.quad 0xD68 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD68 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD68 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD68 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD68 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD68 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD70 "QOSBW_FIX_QOS_BANK[1] [430],QOSBW FIX QOS BANK1 Register 430" bitfld.quad 0xD70 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD70 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD70 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD70 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD70 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD70 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD78 "QOSBW_FIX_QOS_BANK[1] [431],QOSBW FIX QOS BANK1 Register 431" bitfld.quad 0xD78 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD78 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD78 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD78 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD78 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD78 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD80 "QOSBW_FIX_QOS_BANK[1] [432],QOSBW FIX QOS BANK1 Register 432" bitfld.quad 0xD80 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD80 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD80 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD80 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD80 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD80 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD88 "QOSBW_FIX_QOS_BANK[1] [433],QOSBW FIX QOS BANK1 Register 433" bitfld.quad 0xD88 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD88 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD88 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD88 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD88 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD88 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD90 "QOSBW_FIX_QOS_BANK[1] [434],QOSBW FIX QOS BANK1 Register 434" bitfld.quad 0xD90 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD90 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD90 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD90 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD90 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD90 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xD98 "QOSBW_FIX_QOS_BANK[1] [435],QOSBW FIX QOS BANK1 Register 435" bitfld.quad 0xD98 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xD98 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xD98 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xD98 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xD98 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xD98 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDA0 "QOSBW_FIX_QOS_BANK[1] [436],QOSBW FIX QOS BANK1 Register 436" bitfld.quad 0xDA0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDA0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDA0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDA0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDA0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDA0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDA8 "QOSBW_FIX_QOS_BANK[1] [437],QOSBW FIX QOS BANK1 Register 437" bitfld.quad 0xDA8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDA8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDA8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDA8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDA8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDA8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDB0 "QOSBW_FIX_QOS_BANK[1] [438],QOSBW FIX QOS BANK1 Register 438" bitfld.quad 0xDB0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDB0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDB0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDB0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDB0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDB0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDB8 "QOSBW_FIX_QOS_BANK[1] [439],QOSBW FIX QOS BANK1 Register 439" bitfld.quad 0xDB8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDB8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDB8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDB8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDB8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDB8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDC0 "QOSBW_FIX_QOS_BANK[1] [440],QOSBW FIX QOS BANK1 Register 440" bitfld.quad 0xDC0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDC0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDC0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDC0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDC0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDC0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDC8 "QOSBW_FIX_QOS_BANK[1] [441],QOSBW FIX QOS BANK1 Register 441" bitfld.quad 0xDC8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDC8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDC8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDC8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDC8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDC8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDD0 "QOSBW_FIX_QOS_BANK[1] [442],QOSBW FIX QOS BANK1 Register 442" bitfld.quad 0xDD0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDD0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDD0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDD0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDD0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDD0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDD8 "QOSBW_FIX_QOS_BANK[1] [443],QOSBW FIX QOS BANK1 Register 443" bitfld.quad 0xDD8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDD8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDD8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDD8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDD8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDD8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDE0 "QOSBW_FIX_QOS_BANK[1] [444],QOSBW FIX QOS BANK1 Register 444" bitfld.quad 0xDE0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDE0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDE0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDE0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDE0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDE0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDE8 "QOSBW_FIX_QOS_BANK[1] [445],QOSBW FIX QOS BANK1 Register 445" bitfld.quad 0xDE8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDE8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDE8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDE8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDE8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDE8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDF0 "QOSBW_FIX_QOS_BANK[1] [446],QOSBW FIX QOS BANK1 Register 446" bitfld.quad 0xDF0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDF0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDF0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDF0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDF0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDF0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xDF8 "QOSBW_FIX_QOS_BANK[1] [447],QOSBW FIX QOS BANK1 Register 447" bitfld.quad 0xDF8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xDF8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xDF8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xDF8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xDF8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xDF8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE00 "QOSBW_FIX_QOS_BANK[1] [448],QOSBW FIX QOS BANK1 Register 448" bitfld.quad 0xE00 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE00 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE00 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE00 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE00 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE00 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE08 "QOSBW_FIX_QOS_BANK[1] [449],QOSBW FIX QOS BANK1 Register 449" bitfld.quad 0xE08 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE08 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE08 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE08 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE08 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE08 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE10 "QOSBW_FIX_QOS_BANK[1] [450],QOSBW FIX QOS BANK1 Register 450" bitfld.quad 0xE10 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE10 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE10 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE10 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE10 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE10 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE18 "QOSBW_FIX_QOS_BANK[1] [451],QOSBW FIX QOS BANK1 Register 451" bitfld.quad 0xE18 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE18 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE18 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE18 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE18 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE18 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE20 "QOSBW_FIX_QOS_BANK[1] [452],QOSBW FIX QOS BANK1 Register 452" bitfld.quad 0xE20 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE20 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE20 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE20 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE20 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE20 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE28 "QOSBW_FIX_QOS_BANK[1] [453],QOSBW FIX QOS BANK1 Register 453" bitfld.quad 0xE28 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE28 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE28 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE28 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE28 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE28 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE30 "QOSBW_FIX_QOS_BANK[1] [454],QOSBW FIX QOS BANK1 Register 454" bitfld.quad 0xE30 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE30 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE30 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE30 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE30 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE30 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE38 "QOSBW_FIX_QOS_BANK[1] [455],QOSBW FIX QOS BANK1 Register 455" bitfld.quad 0xE38 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE38 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE38 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE38 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE38 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE38 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE40 "QOSBW_FIX_QOS_BANK[1] [456],QOSBW FIX QOS BANK1 Register 456" bitfld.quad 0xE40 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE40 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE40 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE40 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE40 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE40 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE48 "QOSBW_FIX_QOS_BANK[1] [457],QOSBW FIX QOS BANK1 Register 457" bitfld.quad 0xE48 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE48 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE48 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE48 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE48 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE48 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE50 "QOSBW_FIX_QOS_BANK[1] [458],QOSBW FIX QOS BANK1 Register 458" bitfld.quad 0xE50 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE50 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE50 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE50 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE50 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE50 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE58 "QOSBW_FIX_QOS_BANK[1] [459],QOSBW FIX QOS BANK1 Register 459" bitfld.quad 0xE58 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE58 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE58 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE58 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE58 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE58 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE60 "QOSBW_FIX_QOS_BANK[1] [460],QOSBW FIX QOS BANK1 Register 460" bitfld.quad 0xE60 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE60 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE60 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE60 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE60 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE60 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE68 "QOSBW_FIX_QOS_BANK[1] [461],QOSBW FIX QOS BANK1 Register 461" bitfld.quad 0xE68 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE68 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE68 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE68 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE68 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE68 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE70 "QOSBW_FIX_QOS_BANK[1] [462],QOSBW FIX QOS BANK1 Register 462" bitfld.quad 0xE70 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE70 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE70 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE70 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE70 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE70 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE78 "QOSBW_FIX_QOS_BANK[1] [463],QOSBW FIX QOS BANK1 Register 463" bitfld.quad 0xE78 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE78 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE78 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE78 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE78 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE78 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE80 "QOSBW_FIX_QOS_BANK[1] [464],QOSBW FIX QOS BANK1 Register 464" bitfld.quad 0xE80 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE80 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE80 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE80 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE80 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE80 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE88 "QOSBW_FIX_QOS_BANK[1] [465],QOSBW FIX QOS BANK1 Register 465" bitfld.quad 0xE88 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE88 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE88 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE88 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE88 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE88 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE90 "QOSBW_FIX_QOS_BANK[1] [466],QOSBW FIX QOS BANK1 Register 466" bitfld.quad 0xE90 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE90 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE90 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE90 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE90 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE90 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xE98 "QOSBW_FIX_QOS_BANK[1] [467],QOSBW FIX QOS BANK1 Register 467" bitfld.quad 0xE98 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xE98 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xE98 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xE98 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xE98 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xE98 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xEA0 "QOSBW_FIX_QOS_BANK[1] [468],QOSBW FIX QOS BANK1 Register 468" bitfld.quad 0xEA0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEA0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xEA0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xEA0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xEA0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xEA0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xEA8 "QOSBW_FIX_QOS_BANK[1] [469],QOSBW FIX QOS BANK1 Register 469" bitfld.quad 0xEA8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEA8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xEA8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xEA8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xEA8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xEA8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xEB0 "QOSBW_FIX_QOS_BANK[1] [470],QOSBW FIX QOS BANK1 Register 470" bitfld.quad 0xEB0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEB0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xEB0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xEB0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xEB0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xEB0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xEB8 "QOSBW_FIX_QOS_BANK[1] [471],QOSBW FIX QOS BANK1 Register 471" bitfld.quad 0xEB8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEB8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xEB8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xEB8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xEB8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xEB8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xEC0 "QOSBW_FIX_QOS_BANK[1] [472],QOSBW FIX QOS BANK1 Register 472" bitfld.quad 0xEC0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEC0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xEC0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xEC0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xEC0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xEC0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xEC8 "QOSBW_FIX_QOS_BANK[1] [473],QOSBW FIX QOS BANK1 Register 473" bitfld.quad 0xEC8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEC8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xEC8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xEC8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xEC8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xEC8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xED0 "QOSBW_FIX_QOS_BANK[1] [474],QOSBW FIX QOS BANK1 Register 474" bitfld.quad 0xED0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xED0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xED0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xED0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xED0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xED0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xED8 "QOSBW_FIX_QOS_BANK[1] [475],QOSBW FIX QOS BANK1 Register 475" bitfld.quad 0xED8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xED8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xED8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xED8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xED8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xED8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xEE0 "QOSBW_FIX_QOS_BANK[1] [476],QOSBW FIX QOS BANK1 Register 476" bitfld.quad 0xEE0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEE0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xEE0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xEE0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xEE0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xEE0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xEE8 "QOSBW_FIX_QOS_BANK[1] [477],QOSBW FIX QOS BANK1 Register 477" bitfld.quad 0xEE8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEE8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xEE8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xEE8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xEE8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xEE8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xEF0 "QOSBW_FIX_QOS_BANK[1] [478],QOSBW FIX QOS BANK1 Register 478" bitfld.quad 0xEF0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEF0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xEF0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xEF0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xEF0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xEF0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xEF8 "QOSBW_FIX_QOS_BANK[1] [479],QOSBW FIX QOS BANK1 Register 479" bitfld.quad 0xEF8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xEF8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xEF8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xEF8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xEF8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xEF8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF00 "QOSBW_FIX_QOS_BANK[1] [480],QOSBW FIX QOS BANK1 Register 480" bitfld.quad 0xF00 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF00 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF00 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF00 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF00 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF00 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF08 "QOSBW_FIX_QOS_BANK[1] [481],QOSBW FIX QOS BANK1 Register 481" bitfld.quad 0xF08 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF08 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF08 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF08 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF08 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF08 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF10 "QOSBW_FIX_QOS_BANK[1] [482],QOSBW FIX QOS BANK1 Register 482" bitfld.quad 0xF10 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF10 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF10 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF10 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF10 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF10 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF18 "QOSBW_FIX_QOS_BANK[1] [483],QOSBW FIX QOS BANK1 Register 483" bitfld.quad 0xF18 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF18 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF18 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF18 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF18 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF18 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF20 "QOSBW_FIX_QOS_BANK[1] [484],QOSBW FIX QOS BANK1 Register 484" bitfld.quad 0xF20 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF20 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF20 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF20 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF20 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF20 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF28 "QOSBW_FIX_QOS_BANK[1] [485],QOSBW FIX QOS BANK1 Register 485" bitfld.quad 0xF28 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF28 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF28 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF28 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF28 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF28 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF30 "QOSBW_FIX_QOS_BANK[1] [486],QOSBW FIX QOS BANK1 Register 486" bitfld.quad 0xF30 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF30 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF30 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF30 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF30 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF30 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF38 "QOSBW_FIX_QOS_BANK[1] [487],QOSBW FIX QOS BANK1 Register 487" bitfld.quad 0xF38 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF38 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF38 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF38 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF38 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF38 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF40 "QOSBW_FIX_QOS_BANK[1] [488],QOSBW FIX QOS BANK1 Register 488" bitfld.quad 0xF40 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF40 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF40 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF40 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF40 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF40 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF48 "QOSBW_FIX_QOS_BANK[1] [489],QOSBW FIX QOS BANK1 Register 489" bitfld.quad 0xF48 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF48 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF48 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF48 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF48 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF48 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF50 "QOSBW_FIX_QOS_BANK[1] [490],QOSBW FIX QOS BANK1 Register 490" bitfld.quad 0xF50 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF50 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF50 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF50 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF50 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF50 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF58 "QOSBW_FIX_QOS_BANK[1] [491],QOSBW FIX QOS BANK1 Register 491" bitfld.quad 0xF58 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF58 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF58 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF58 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF58 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF58 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF60 "QOSBW_FIX_QOS_BANK[1] [492],QOSBW FIX QOS BANK1 Register 492" bitfld.quad 0xF60 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF60 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF60 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF60 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF60 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF60 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF68 "QOSBW_FIX_QOS_BANK[1] [493],QOSBW FIX QOS BANK1 Register 493" bitfld.quad 0xF68 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF68 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF68 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF68 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF68 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF68 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF70 "QOSBW_FIX_QOS_BANK[1] [494],QOSBW FIX QOS BANK1 Register 494" bitfld.quad 0xF70 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF70 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF70 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF70 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF70 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF70 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF78 "QOSBW_FIX_QOS_BANK[1] [495],QOSBW FIX QOS BANK1 Register 495" bitfld.quad 0xF78 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF78 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF78 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF78 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF78 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF78 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF80 "QOSBW_FIX_QOS_BANK[1] [496],QOSBW FIX QOS BANK1 Register 496" bitfld.quad 0xF80 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF80 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF80 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF80 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF80 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF80 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF88 "QOSBW_FIX_QOS_BANK[1] [497],QOSBW FIX QOS BANK1 Register 497" bitfld.quad 0xF88 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF88 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF88 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF88 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF88 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF88 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF90 "QOSBW_FIX_QOS_BANK[1] [498],QOSBW FIX QOS BANK1 Register 498" bitfld.quad 0xF90 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF90 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF90 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF90 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF90 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF90 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xF98 "QOSBW_FIX_QOS_BANK[1] [499],QOSBW FIX QOS BANK1 Register 499" bitfld.quad 0xF98 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xF98 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xF98 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xF98 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xF98 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xF98 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFA0 "QOSBW_FIX_QOS_BANK[1] [500],QOSBW FIX QOS BANK1 Register 500" bitfld.quad 0xFA0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFA0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFA0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFA0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFA0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFA0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFA8 "QOSBW_FIX_QOS_BANK[1] [501],QOSBW FIX QOS BANK1 Register 501" bitfld.quad 0xFA8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFA8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFA8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFA8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFA8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFA8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFB0 "QOSBW_FIX_QOS_BANK[1] [502],QOSBW FIX QOS BANK1 Register 502" bitfld.quad 0xFB0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFB0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFB0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFB0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFB0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFB0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFB8 "QOSBW_FIX_QOS_BANK[1] [503],QOSBW FIX QOS BANK1 Register 503" bitfld.quad 0xFB8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFB8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFB8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFB8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFB8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFB8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFC0 "QOSBW_FIX_QOS_BANK[1] [504],QOSBW FIX QOS BANK1 Register 504" bitfld.quad 0xFC0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFC0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFC0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFC0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFC0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFC0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFC8 "QOSBW_FIX_QOS_BANK[1] [505],QOSBW FIX QOS BANK1 Register 505" bitfld.quad 0xFC8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFC8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFC8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFC8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFC8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFC8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFD0 "QOSBW_FIX_QOS_BANK[1] [506],QOSBW FIX QOS BANK1 Register 506" bitfld.quad 0xFD0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFD0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFD0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFD0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFD0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFD0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFD8 "QOSBW_FIX_QOS_BANK[1] [507],QOSBW FIX QOS BANK1 Register 507" bitfld.quad 0xFD8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFD8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFD8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFD8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFD8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFD8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFE0 "QOSBW_FIX_QOS_BANK[1] [508],QOSBW FIX QOS BANK1 Register 508" bitfld.quad 0xFE0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFE0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFE0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFE0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFE0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFE0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFE8 "QOSBW_FIX_QOS_BANK[1] [509],QOSBW FIX QOS BANK1 Register 509" bitfld.quad 0xFE8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFE8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFE8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFE8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFE8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFE8 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFF0 "QOSBW_FIX_QOS_BANK[1] [510],QOSBW FIX QOS BANK1 Register 510" bitfld.quad 0xFF0 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFF0 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFF0 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFF0 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFF0 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFF0 0.--15. 1. "FIXQOS_BANK1_0" line.quad 0xFF8 "QOSBW_FIX_QOS_BANK[1] [511],QOSBW FIX QOS BANK1 Register 511" bitfld.quad 0xFF8 50.--52. "FIXQOS_BANK1_5" "0,1,2,3,4,5,6,7" hexmask.quad.byte 0xFF8 42.--49. 1. "FIXQOS_BANK1_4" hexmask.quad.word 0xFF8 32.--41. 1. "FIXQOS_BANK1_3" newline hexmask.quad.byte 0xFF8 24.--31. 1. "FIXQOS_BANK1_2" hexmask.quad.byte 0xFF8 16.--23. 1. "FIXQOS_BANK1_1" hexmask.quad.word 0xFF8 0.--15. 1. "FIXQOS_BANK1_0" group.quad 0x2000++0xFFF line.quad 0x0 "QOSBW_BE_QOS_BANK[0] [0],QOSBW BE QOS BANK0 Register 0" bitfld.quad 0x0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8 "QOSBW_BE_QOS_BANK[0] [1],QOSBW BE QOS BANK0 Register 1" bitfld.quad 0x8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x10 "QOSBW_BE_QOS_BANK[0] [2],QOSBW BE QOS BANK0 Register 2" bitfld.quad 0x10 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x10 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x10 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x10 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x10 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x10 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x18 "QOSBW_BE_QOS_BANK[0] [3],QOSBW BE QOS BANK0 Register 3" bitfld.quad 0x18 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x18 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x18 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x18 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x18 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x18 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x20 "QOSBW_BE_QOS_BANK[0] [4],QOSBW BE QOS BANK0 Register 4" bitfld.quad 0x20 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x20 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x20 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x20 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x20 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x20 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x28 "QOSBW_BE_QOS_BANK[0] [5],QOSBW BE QOS BANK0 Register 5" bitfld.quad 0x28 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x28 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x28 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x28 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x28 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x28 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x30 "QOSBW_BE_QOS_BANK[0] [6],QOSBW BE QOS BANK0 Register 6" bitfld.quad 0x30 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x30 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x30 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x30 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x30 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x30 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x38 "QOSBW_BE_QOS_BANK[0] [7],QOSBW BE QOS BANK0 Register 7" bitfld.quad 0x38 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x38 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x38 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x38 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x38 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x38 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x40 "QOSBW_BE_QOS_BANK[0] [8],QOSBW BE QOS BANK0 Register 8" bitfld.quad 0x40 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x40 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x40 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x40 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x40 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x40 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x48 "QOSBW_BE_QOS_BANK[0] [9],QOSBW BE QOS BANK0 Register 9" bitfld.quad 0x48 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x48 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x48 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x48 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x48 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x48 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x50 "QOSBW_BE_QOS_BANK[0] [10],QOSBW BE QOS BANK0 Register 10" bitfld.quad 0x50 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x50 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x50 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x50 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x50 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x50 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x58 "QOSBW_BE_QOS_BANK[0] [11],QOSBW BE QOS BANK0 Register 11" bitfld.quad 0x58 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x58 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x58 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x58 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x58 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x58 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x60 "QOSBW_BE_QOS_BANK[0] [12],QOSBW BE QOS BANK0 Register 12" bitfld.quad 0x60 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x60 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x60 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x60 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x60 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x60 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x68 "QOSBW_BE_QOS_BANK[0] [13],QOSBW BE QOS BANK0 Register 13" bitfld.quad 0x68 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x68 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x68 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x68 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x68 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x68 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x70 "QOSBW_BE_QOS_BANK[0] [14],QOSBW BE QOS BANK0 Register 14" bitfld.quad 0x70 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x70 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x70 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x70 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x70 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x70 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x78 "QOSBW_BE_QOS_BANK[0] [15],QOSBW BE QOS BANK0 Register 15" bitfld.quad 0x78 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x78 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x78 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x78 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x78 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x78 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x80 "QOSBW_BE_QOS_BANK[0] [16],QOSBW BE QOS BANK0 Register 16" bitfld.quad 0x80 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x80 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x80 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x80 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x80 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x80 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x88 "QOSBW_BE_QOS_BANK[0] [17],QOSBW BE QOS BANK0 Register 17" bitfld.quad 0x88 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x88 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x88 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x88 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x88 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x88 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x90 "QOSBW_BE_QOS_BANK[0] [18],QOSBW BE QOS BANK0 Register 18" bitfld.quad 0x90 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x90 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x90 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x90 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x90 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x90 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x98 "QOSBW_BE_QOS_BANK[0] [19],QOSBW BE QOS BANK0 Register 19" bitfld.quad 0x98 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x98 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x98 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x98 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x98 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x98 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA0 "QOSBW_BE_QOS_BANK[0] [20],QOSBW BE QOS BANK0 Register 20" bitfld.quad 0xA0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA8 "QOSBW_BE_QOS_BANK[0] [21],QOSBW BE QOS BANK0 Register 21" bitfld.quad 0xA8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB0 "QOSBW_BE_QOS_BANK[0] [22],QOSBW BE QOS BANK0 Register 22" bitfld.quad 0xB0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB8 "QOSBW_BE_QOS_BANK[0] [23],QOSBW BE QOS BANK0 Register 23" bitfld.quad 0xB8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC0 "QOSBW_BE_QOS_BANK[0] [24],QOSBW BE QOS BANK0 Register 24" bitfld.quad 0xC0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC8 "QOSBW_BE_QOS_BANK[0] [25],QOSBW BE QOS BANK0 Register 25" bitfld.quad 0xC8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD0 "QOSBW_BE_QOS_BANK[0] [26],QOSBW BE QOS BANK0 Register 26" bitfld.quad 0xD0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD8 "QOSBW_BE_QOS_BANK[0] [27],QOSBW BE QOS BANK0 Register 27" bitfld.quad 0xD8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE0 "QOSBW_BE_QOS_BANK[0] [28],QOSBW BE QOS BANK0 Register 28" bitfld.quad 0xE0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE8 "QOSBW_BE_QOS_BANK[0] [29],QOSBW BE QOS BANK0 Register 29" bitfld.quad 0xE8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF0 "QOSBW_BE_QOS_BANK[0] [30],QOSBW BE QOS BANK0 Register 30" bitfld.quad 0xF0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF8 "QOSBW_BE_QOS_BANK[0] [31],QOSBW BE QOS BANK0 Register 31" bitfld.quad 0xF8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x100 "QOSBW_BE_QOS_BANK[0] [32],QOSBW BE QOS BANK0 Register 32" bitfld.quad 0x100 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x100 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x100 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x100 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x100 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x100 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x108 "QOSBW_BE_QOS_BANK[0] [33],QOSBW BE QOS BANK0 Register 33" bitfld.quad 0x108 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x108 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x108 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x108 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x108 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x108 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x110 "QOSBW_BE_QOS_BANK[0] [34],QOSBW BE QOS BANK0 Register 34" bitfld.quad 0x110 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x110 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x110 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x110 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x110 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x110 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x118 "QOSBW_BE_QOS_BANK[0] [35],QOSBW BE QOS BANK0 Register 35" bitfld.quad 0x118 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x118 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x118 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x118 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x118 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x118 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x120 "QOSBW_BE_QOS_BANK[0] [36],QOSBW BE QOS BANK0 Register 36" bitfld.quad 0x120 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x120 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x120 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x120 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x120 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x120 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x128 "QOSBW_BE_QOS_BANK[0] [37],QOSBW BE QOS BANK0 Register 37" bitfld.quad 0x128 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x128 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x128 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x128 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x128 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x128 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x130 "QOSBW_BE_QOS_BANK[0] [38],QOSBW BE QOS BANK0 Register 38" bitfld.quad 0x130 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x130 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x130 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x130 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x130 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x130 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x138 "QOSBW_BE_QOS_BANK[0] [39],QOSBW BE QOS BANK0 Register 39" bitfld.quad 0x138 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x138 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x138 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x138 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x138 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x138 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x140 "QOSBW_BE_QOS_BANK[0] [40],QOSBW BE QOS BANK0 Register 40" bitfld.quad 0x140 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x140 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x140 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x140 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x140 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x140 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x148 "QOSBW_BE_QOS_BANK[0] [41],QOSBW BE QOS BANK0 Register 41" bitfld.quad 0x148 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x148 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x148 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x148 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x148 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x148 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x150 "QOSBW_BE_QOS_BANK[0] [42],QOSBW BE QOS BANK0 Register 42" bitfld.quad 0x150 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x150 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x150 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x150 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x150 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x150 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x158 "QOSBW_BE_QOS_BANK[0] [43],QOSBW BE QOS BANK0 Register 43" bitfld.quad 0x158 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x158 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x158 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x158 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x158 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x158 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x160 "QOSBW_BE_QOS_BANK[0] [44],QOSBW BE QOS BANK0 Register 44" bitfld.quad 0x160 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x160 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x160 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x160 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x160 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x160 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x168 "QOSBW_BE_QOS_BANK[0] [45],QOSBW BE QOS BANK0 Register 45" bitfld.quad 0x168 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x168 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x168 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x168 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x168 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x168 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x170 "QOSBW_BE_QOS_BANK[0] [46],QOSBW BE QOS BANK0 Register 46" bitfld.quad 0x170 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x170 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x170 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x170 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x170 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x170 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x178 "QOSBW_BE_QOS_BANK[0] [47],QOSBW BE QOS BANK0 Register 47" bitfld.quad 0x178 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x178 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x178 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x178 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x178 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x178 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x180 "QOSBW_BE_QOS_BANK[0] [48],QOSBW BE QOS BANK0 Register 48" bitfld.quad 0x180 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x180 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x180 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x180 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x180 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x180 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x188 "QOSBW_BE_QOS_BANK[0] [49],QOSBW BE QOS BANK0 Register 49" bitfld.quad 0x188 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x188 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x188 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x188 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x188 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x188 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x190 "QOSBW_BE_QOS_BANK[0] [50],QOSBW BE QOS BANK0 Register 50" bitfld.quad 0x190 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x190 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x190 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x190 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x190 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x190 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x198 "QOSBW_BE_QOS_BANK[0] [51],QOSBW BE QOS BANK0 Register 51" bitfld.quad 0x198 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x198 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x198 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x198 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x198 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x198 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1A0 "QOSBW_BE_QOS_BANK[0] [52],QOSBW BE QOS BANK0 Register 52" bitfld.quad 0x1A0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1A0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1A0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1A0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1A0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1A0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1A8 "QOSBW_BE_QOS_BANK[0] [53],QOSBW BE QOS BANK0 Register 53" bitfld.quad 0x1A8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1A8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1A8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1A8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1A8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1A8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1B0 "QOSBW_BE_QOS_BANK[0] [54],QOSBW BE QOS BANK0 Register 54" bitfld.quad 0x1B0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1B0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1B0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1B0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1B0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1B0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1B8 "QOSBW_BE_QOS_BANK[0] [55],QOSBW BE QOS BANK0 Register 55" bitfld.quad 0x1B8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1B8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1B8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1B8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1B8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1B8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1C0 "QOSBW_BE_QOS_BANK[0] [56],QOSBW BE QOS BANK0 Register 56" bitfld.quad 0x1C0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1C0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1C0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1C0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1C0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1C0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1C8 "QOSBW_BE_QOS_BANK[0] [57],QOSBW BE QOS BANK0 Register 57" bitfld.quad 0x1C8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1C8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1C8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1C8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1C8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1C8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1D0 "QOSBW_BE_QOS_BANK[0] [58],QOSBW BE QOS BANK0 Register 58" bitfld.quad 0x1D0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1D0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1D0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1D0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1D0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1D0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1D8 "QOSBW_BE_QOS_BANK[0] [59],QOSBW BE QOS BANK0 Register 59" bitfld.quad 0x1D8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1D8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1D8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1D8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1D8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1D8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1E0 "QOSBW_BE_QOS_BANK[0] [60],QOSBW BE QOS BANK0 Register 60" bitfld.quad 0x1E0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1E0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1E0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1E0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1E0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1E0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1E8 "QOSBW_BE_QOS_BANK[0] [61],QOSBW BE QOS BANK0 Register 61" bitfld.quad 0x1E8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1E8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1E8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1E8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1E8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1E8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1F0 "QOSBW_BE_QOS_BANK[0] [62],QOSBW BE QOS BANK0 Register 62" bitfld.quad 0x1F0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1F0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1F0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1F0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1F0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1F0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x1F8 "QOSBW_BE_QOS_BANK[0] [63],QOSBW BE QOS BANK0 Register 63" bitfld.quad 0x1F8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x1F8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x1F8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x1F8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x1F8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x1F8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x200 "QOSBW_BE_QOS_BANK[0] [64],QOSBW BE QOS BANK0 Register 64" bitfld.quad 0x200 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x200 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x200 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x200 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x200 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x200 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x208 "QOSBW_BE_QOS_BANK[0] [65],QOSBW BE QOS BANK0 Register 65" bitfld.quad 0x208 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x208 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x208 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x208 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x208 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x208 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x210 "QOSBW_BE_QOS_BANK[0] [66],QOSBW BE QOS BANK0 Register 66" bitfld.quad 0x210 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x210 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x210 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x210 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x210 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x210 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x218 "QOSBW_BE_QOS_BANK[0] [67],QOSBW BE QOS BANK0 Register 67" bitfld.quad 0x218 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x218 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x218 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x218 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x218 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x218 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x220 "QOSBW_BE_QOS_BANK[0] [68],QOSBW BE QOS BANK0 Register 68" bitfld.quad 0x220 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x220 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x220 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x220 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x220 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x220 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x228 "QOSBW_BE_QOS_BANK[0] [69],QOSBW BE QOS BANK0 Register 69" bitfld.quad 0x228 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x228 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x228 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x228 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x228 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x228 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x230 "QOSBW_BE_QOS_BANK[0] [70],QOSBW BE QOS BANK0 Register 70" bitfld.quad 0x230 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x230 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x230 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x230 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x230 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x230 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x238 "QOSBW_BE_QOS_BANK[0] [71],QOSBW BE QOS BANK0 Register 71" bitfld.quad 0x238 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x238 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x238 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x238 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x238 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x238 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x240 "QOSBW_BE_QOS_BANK[0] [72],QOSBW BE QOS BANK0 Register 72" bitfld.quad 0x240 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x240 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x240 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x240 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x240 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x240 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x248 "QOSBW_BE_QOS_BANK[0] [73],QOSBW BE QOS BANK0 Register 73" bitfld.quad 0x248 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x248 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x248 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x248 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x248 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x248 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x250 "QOSBW_BE_QOS_BANK[0] [74],QOSBW BE QOS BANK0 Register 74" bitfld.quad 0x250 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x250 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x250 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x250 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x250 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x250 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x258 "QOSBW_BE_QOS_BANK[0] [75],QOSBW BE QOS BANK0 Register 75" bitfld.quad 0x258 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x258 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x258 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x258 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x258 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x258 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x260 "QOSBW_BE_QOS_BANK[0] [76],QOSBW BE QOS BANK0 Register 76" bitfld.quad 0x260 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x260 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x260 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x260 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x260 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x260 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x268 "QOSBW_BE_QOS_BANK[0] [77],QOSBW BE QOS BANK0 Register 77" bitfld.quad 0x268 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x268 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x268 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x268 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x268 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x268 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x270 "QOSBW_BE_QOS_BANK[0] [78],QOSBW BE QOS BANK0 Register 78" bitfld.quad 0x270 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x270 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x270 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x270 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x270 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x270 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x278 "QOSBW_BE_QOS_BANK[0] [79],QOSBW BE QOS BANK0 Register 79" bitfld.quad 0x278 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x278 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x278 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x278 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x278 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x278 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x280 "QOSBW_BE_QOS_BANK[0] [80],QOSBW BE QOS BANK0 Register 80" bitfld.quad 0x280 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x280 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x280 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x280 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x280 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x280 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x288 "QOSBW_BE_QOS_BANK[0] [81],QOSBW BE QOS BANK0 Register 81" bitfld.quad 0x288 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x288 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x288 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x288 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x288 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x288 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x290 "QOSBW_BE_QOS_BANK[0] [82],QOSBW BE QOS BANK0 Register 82" bitfld.quad 0x290 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x290 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x290 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x290 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x290 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x290 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x298 "QOSBW_BE_QOS_BANK[0] [83],QOSBW BE QOS BANK0 Register 83" bitfld.quad 0x298 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x298 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x298 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x298 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x298 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x298 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2A0 "QOSBW_BE_QOS_BANK[0] [84],QOSBW BE QOS BANK0 Register 84" bitfld.quad 0x2A0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2A0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2A0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2A0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2A0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2A0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2A8 "QOSBW_BE_QOS_BANK[0] [85],QOSBW BE QOS BANK0 Register 85" bitfld.quad 0x2A8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2A8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2A8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2A8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2A8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2A8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2B0 "QOSBW_BE_QOS_BANK[0] [86],QOSBW BE QOS BANK0 Register 86" bitfld.quad 0x2B0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2B0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2B0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2B0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2B0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2B0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2B8 "QOSBW_BE_QOS_BANK[0] [87],QOSBW BE QOS BANK0 Register 87" bitfld.quad 0x2B8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2B8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2B8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2B8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2B8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2B8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2C0 "QOSBW_BE_QOS_BANK[0] [88],QOSBW BE QOS BANK0 Register 88" bitfld.quad 0x2C0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2C0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2C0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2C0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2C0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2C0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2C8 "QOSBW_BE_QOS_BANK[0] [89],QOSBW BE QOS BANK0 Register 89" bitfld.quad 0x2C8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2C8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2C8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2C8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2C8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2C8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2D0 "QOSBW_BE_QOS_BANK[0] [90],QOSBW BE QOS BANK0 Register 90" bitfld.quad 0x2D0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2D0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2D0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2D0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2D0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2D0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2D8 "QOSBW_BE_QOS_BANK[0] [91],QOSBW BE QOS BANK0 Register 91" bitfld.quad 0x2D8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2D8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2D8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2D8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2D8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2D8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2E0 "QOSBW_BE_QOS_BANK[0] [92],QOSBW BE QOS BANK0 Register 92" bitfld.quad 0x2E0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2E0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2E0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2E0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2E0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2E0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2E8 "QOSBW_BE_QOS_BANK[0] [93],QOSBW BE QOS BANK0 Register 93" bitfld.quad 0x2E8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2E8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2E8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2E8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2E8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2E8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2F0 "QOSBW_BE_QOS_BANK[0] [94],QOSBW BE QOS BANK0 Register 94" bitfld.quad 0x2F0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2F0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2F0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2F0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2F0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2F0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x2F8 "QOSBW_BE_QOS_BANK[0] [95],QOSBW BE QOS BANK0 Register 95" bitfld.quad 0x2F8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x2F8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x2F8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x2F8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x2F8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x2F8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x300 "QOSBW_BE_QOS_BANK[0] [96],QOSBW BE QOS BANK0 Register 96" bitfld.quad 0x300 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x300 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x300 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x300 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x300 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x300 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x308 "QOSBW_BE_QOS_BANK[0] [97],QOSBW BE QOS BANK0 Register 97" bitfld.quad 0x308 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x308 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x308 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x308 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x308 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x308 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x310 "QOSBW_BE_QOS_BANK[0] [98],QOSBW BE QOS BANK0 Register 98" bitfld.quad 0x310 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x310 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x310 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x310 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x310 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x310 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x318 "QOSBW_BE_QOS_BANK[0] [99],QOSBW BE QOS BANK0 Register 99" bitfld.quad 0x318 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x318 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x318 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x318 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x318 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x318 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x320 "QOSBW_BE_QOS_BANK[0] [100],QOSBW BE QOS BANK0 Register 100" bitfld.quad 0x320 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x320 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x320 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x320 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x320 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x320 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x328 "QOSBW_BE_QOS_BANK[0] [101],QOSBW BE QOS BANK0 Register 101" bitfld.quad 0x328 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x328 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x328 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x328 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x328 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x328 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x330 "QOSBW_BE_QOS_BANK[0] [102],QOSBW BE QOS BANK0 Register 102" bitfld.quad 0x330 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x330 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x330 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x330 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x330 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x330 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x338 "QOSBW_BE_QOS_BANK[0] [103],QOSBW BE QOS BANK0 Register 103" bitfld.quad 0x338 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x338 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x338 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x338 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x338 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x338 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x340 "QOSBW_BE_QOS_BANK[0] [104],QOSBW BE QOS BANK0 Register 104" bitfld.quad 0x340 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x340 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x340 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x340 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x340 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x340 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x348 "QOSBW_BE_QOS_BANK[0] [105],QOSBW BE QOS BANK0 Register 105" bitfld.quad 0x348 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x348 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x348 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x348 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x348 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x348 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x350 "QOSBW_BE_QOS_BANK[0] [106],QOSBW BE QOS BANK0 Register 106" bitfld.quad 0x350 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x350 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x350 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x350 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x350 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x350 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x358 "QOSBW_BE_QOS_BANK[0] [107],QOSBW BE QOS BANK0 Register 107" bitfld.quad 0x358 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x358 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x358 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x358 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x358 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x358 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x360 "QOSBW_BE_QOS_BANK[0] [108],QOSBW BE QOS BANK0 Register 108" bitfld.quad 0x360 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x360 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x360 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x360 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x360 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x360 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x368 "QOSBW_BE_QOS_BANK[0] [109],QOSBW BE QOS BANK0 Register 109" bitfld.quad 0x368 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x368 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x368 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x368 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x368 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x368 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x370 "QOSBW_BE_QOS_BANK[0] [110],QOSBW BE QOS BANK0 Register 110" bitfld.quad 0x370 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x370 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x370 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x370 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x370 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x370 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x378 "QOSBW_BE_QOS_BANK[0] [111],QOSBW BE QOS BANK0 Register 111" bitfld.quad 0x378 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x378 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x378 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x378 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x378 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x378 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x380 "QOSBW_BE_QOS_BANK[0] [112],QOSBW BE QOS BANK0 Register 112" bitfld.quad 0x380 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x380 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x380 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x380 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x380 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x380 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x388 "QOSBW_BE_QOS_BANK[0] [113],QOSBW BE QOS BANK0 Register 113" bitfld.quad 0x388 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x388 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x388 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x388 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x388 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x388 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x390 "QOSBW_BE_QOS_BANK[0] [114],QOSBW BE QOS BANK0 Register 114" bitfld.quad 0x390 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x390 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x390 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x390 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x390 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x390 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x398 "QOSBW_BE_QOS_BANK[0] [115],QOSBW BE QOS BANK0 Register 115" bitfld.quad 0x398 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x398 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x398 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x398 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x398 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x398 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3A0 "QOSBW_BE_QOS_BANK[0] [116],QOSBW BE QOS BANK0 Register 116" bitfld.quad 0x3A0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3A0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3A0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3A0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3A0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3A0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3A8 "QOSBW_BE_QOS_BANK[0] [117],QOSBW BE QOS BANK0 Register 117" bitfld.quad 0x3A8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3A8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3A8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3A8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3A8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3A8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3B0 "QOSBW_BE_QOS_BANK[0] [118],QOSBW BE QOS BANK0 Register 118" bitfld.quad 0x3B0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3B0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3B0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3B0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3B0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3B0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3B8 "QOSBW_BE_QOS_BANK[0] [119],QOSBW BE QOS BANK0 Register 119" bitfld.quad 0x3B8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3B8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3B8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3B8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3B8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3B8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3C0 "QOSBW_BE_QOS_BANK[0] [120],QOSBW BE QOS BANK0 Register 120" bitfld.quad 0x3C0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3C0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3C0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3C0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3C0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3C0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3C8 "QOSBW_BE_QOS_BANK[0] [121],QOSBW BE QOS BANK0 Register 121" bitfld.quad 0x3C8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3C8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3C8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3C8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3C8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3C8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3D0 "QOSBW_BE_QOS_BANK[0] [122],QOSBW BE QOS BANK0 Register 122" bitfld.quad 0x3D0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3D0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3D0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3D0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3D0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3D0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3D8 "QOSBW_BE_QOS_BANK[0] [123],QOSBW BE QOS BANK0 Register 123" bitfld.quad 0x3D8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3D8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3D8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3D8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3D8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3D8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3E0 "QOSBW_BE_QOS_BANK[0] [124],QOSBW BE QOS BANK0 Register 124" bitfld.quad 0x3E0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3E0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3E0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3E0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3E0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3E0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3E8 "QOSBW_BE_QOS_BANK[0] [125],QOSBW BE QOS BANK0 Register 125" bitfld.quad 0x3E8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3E8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3E8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3E8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3E8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3E8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3F0 "QOSBW_BE_QOS_BANK[0] [126],QOSBW BE QOS BANK0 Register 126" bitfld.quad 0x3F0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3F0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3F0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3F0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3F0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3F0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x3F8 "QOSBW_BE_QOS_BANK[0] [127],QOSBW BE QOS BANK0 Register 127" bitfld.quad 0x3F8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x3F8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x3F8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x3F8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x3F8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x3F8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x400 "QOSBW_BE_QOS_BANK[0] [128],QOSBW BE QOS BANK0 Register 128" bitfld.quad 0x400 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x400 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x400 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x400 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x400 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x400 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x408 "QOSBW_BE_QOS_BANK[0] [129],QOSBW BE QOS BANK0 Register 129" bitfld.quad 0x408 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x408 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x408 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x408 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x408 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x408 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x410 "QOSBW_BE_QOS_BANK[0] [130],QOSBW BE QOS BANK0 Register 130" bitfld.quad 0x410 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x410 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x410 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x410 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x410 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x410 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x418 "QOSBW_BE_QOS_BANK[0] [131],QOSBW BE QOS BANK0 Register 131" bitfld.quad 0x418 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x418 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x418 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x418 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x418 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x418 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x420 "QOSBW_BE_QOS_BANK[0] [132],QOSBW BE QOS BANK0 Register 132" bitfld.quad 0x420 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x420 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x420 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x420 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x420 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x420 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x428 "QOSBW_BE_QOS_BANK[0] [133],QOSBW BE QOS BANK0 Register 133" bitfld.quad 0x428 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x428 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x428 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x428 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x428 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x428 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x430 "QOSBW_BE_QOS_BANK[0] [134],QOSBW BE QOS BANK0 Register 134" bitfld.quad 0x430 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x430 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x430 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x430 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x430 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x430 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x438 "QOSBW_BE_QOS_BANK[0] [135],QOSBW BE QOS BANK0 Register 135" bitfld.quad 0x438 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x438 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x438 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x438 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x438 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x438 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x440 "QOSBW_BE_QOS_BANK[0] [136],QOSBW BE QOS BANK0 Register 136" bitfld.quad 0x440 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x440 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x440 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x440 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x440 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x440 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x448 "QOSBW_BE_QOS_BANK[0] [137],QOSBW BE QOS BANK0 Register 137" bitfld.quad 0x448 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x448 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x448 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x448 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x448 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x448 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x450 "QOSBW_BE_QOS_BANK[0] [138],QOSBW BE QOS BANK0 Register 138" bitfld.quad 0x450 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x450 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x450 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x450 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x450 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x450 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x458 "QOSBW_BE_QOS_BANK[0] [139],QOSBW BE QOS BANK0 Register 139" bitfld.quad 0x458 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x458 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x458 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x458 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x458 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x458 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x460 "QOSBW_BE_QOS_BANK[0] [140],QOSBW BE QOS BANK0 Register 140" bitfld.quad 0x460 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x460 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x460 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x460 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x460 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x460 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x468 "QOSBW_BE_QOS_BANK[0] [141],QOSBW BE QOS BANK0 Register 141" bitfld.quad 0x468 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x468 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x468 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x468 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x468 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x468 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x470 "QOSBW_BE_QOS_BANK[0] [142],QOSBW BE QOS BANK0 Register 142" bitfld.quad 0x470 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x470 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x470 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x470 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x470 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x470 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x478 "QOSBW_BE_QOS_BANK[0] [143],QOSBW BE QOS BANK0 Register 143" bitfld.quad 0x478 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x478 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x478 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x478 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x478 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x478 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x480 "QOSBW_BE_QOS_BANK[0] [144],QOSBW BE QOS BANK0 Register 144" bitfld.quad 0x480 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x480 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x480 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x480 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x480 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x480 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x488 "QOSBW_BE_QOS_BANK[0] [145],QOSBW BE QOS BANK0 Register 145" bitfld.quad 0x488 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x488 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x488 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x488 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x488 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x488 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x490 "QOSBW_BE_QOS_BANK[0] [146],QOSBW BE QOS BANK0 Register 146" bitfld.quad 0x490 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x490 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x490 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x490 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x490 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x490 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x498 "QOSBW_BE_QOS_BANK[0] [147],QOSBW BE QOS BANK0 Register 147" bitfld.quad 0x498 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x498 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x498 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x498 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x498 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x498 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4A0 "QOSBW_BE_QOS_BANK[0] [148],QOSBW BE QOS BANK0 Register 148" bitfld.quad 0x4A0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4A0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4A0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4A0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4A0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4A0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4A8 "QOSBW_BE_QOS_BANK[0] [149],QOSBW BE QOS BANK0 Register 149" bitfld.quad 0x4A8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4A8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4A8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4A8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4A8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4A8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4B0 "QOSBW_BE_QOS_BANK[0] [150],QOSBW BE QOS BANK0 Register 150" bitfld.quad 0x4B0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4B0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4B0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4B0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4B0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4B0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4B8 "QOSBW_BE_QOS_BANK[0] [151],QOSBW BE QOS BANK0 Register 151" bitfld.quad 0x4B8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4B8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4B8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4B8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4B8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4B8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4C0 "QOSBW_BE_QOS_BANK[0] [152],QOSBW BE QOS BANK0 Register 152" bitfld.quad 0x4C0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4C0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4C0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4C0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4C0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4C0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4C8 "QOSBW_BE_QOS_BANK[0] [153],QOSBW BE QOS BANK0 Register 153" bitfld.quad 0x4C8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4C8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4C8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4C8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4C8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4C8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4D0 "QOSBW_BE_QOS_BANK[0] [154],QOSBW BE QOS BANK0 Register 154" bitfld.quad 0x4D0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4D0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4D0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4D0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4D0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4D0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4D8 "QOSBW_BE_QOS_BANK[0] [155],QOSBW BE QOS BANK0 Register 155" bitfld.quad 0x4D8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4D8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4D8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4D8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4D8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4D8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4E0 "QOSBW_BE_QOS_BANK[0] [156],QOSBW BE QOS BANK0 Register 156" bitfld.quad 0x4E0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4E0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4E0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4E0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4E0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4E0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4E8 "QOSBW_BE_QOS_BANK[0] [157],QOSBW BE QOS BANK0 Register 157" bitfld.quad 0x4E8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4E8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4E8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4E8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4E8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4E8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4F0 "QOSBW_BE_QOS_BANK[0] [158],QOSBW BE QOS BANK0 Register 158" bitfld.quad 0x4F0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4F0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4F0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4F0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4F0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4F0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x4F8 "QOSBW_BE_QOS_BANK[0] [159],QOSBW BE QOS BANK0 Register 159" bitfld.quad 0x4F8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x4F8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x4F8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x4F8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x4F8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x4F8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x500 "QOSBW_BE_QOS_BANK[0] [160],QOSBW BE QOS BANK0 Register 160" bitfld.quad 0x500 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x500 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x500 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x500 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x500 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x500 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x508 "QOSBW_BE_QOS_BANK[0] [161],QOSBW BE QOS BANK0 Register 161" bitfld.quad 0x508 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x508 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x508 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x508 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x508 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x508 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x510 "QOSBW_BE_QOS_BANK[0] [162],QOSBW BE QOS BANK0 Register 162" bitfld.quad 0x510 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x510 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x510 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x510 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x510 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x510 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x518 "QOSBW_BE_QOS_BANK[0] [163],QOSBW BE QOS BANK0 Register 163" bitfld.quad 0x518 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x518 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x518 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x518 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x518 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x518 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x520 "QOSBW_BE_QOS_BANK[0] [164],QOSBW BE QOS BANK0 Register 164" bitfld.quad 0x520 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x520 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x520 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x520 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x520 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x520 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x528 "QOSBW_BE_QOS_BANK[0] [165],QOSBW BE QOS BANK0 Register 165" bitfld.quad 0x528 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x528 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x528 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x528 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x528 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x528 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x530 "QOSBW_BE_QOS_BANK[0] [166],QOSBW BE QOS BANK0 Register 166" bitfld.quad 0x530 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x530 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x530 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x530 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x530 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x530 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x538 "QOSBW_BE_QOS_BANK[0] [167],QOSBW BE QOS BANK0 Register 167" bitfld.quad 0x538 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x538 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x538 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x538 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x538 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x538 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x540 "QOSBW_BE_QOS_BANK[0] [168],QOSBW BE QOS BANK0 Register 168" bitfld.quad 0x540 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x540 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x540 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x540 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x540 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x540 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x548 "QOSBW_BE_QOS_BANK[0] [169],QOSBW BE QOS BANK0 Register 169" bitfld.quad 0x548 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x548 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x548 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x548 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x548 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x548 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x550 "QOSBW_BE_QOS_BANK[0] [170],QOSBW BE QOS BANK0 Register 170" bitfld.quad 0x550 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x550 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x550 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x550 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x550 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x550 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x558 "QOSBW_BE_QOS_BANK[0] [171],QOSBW BE QOS BANK0 Register 171" bitfld.quad 0x558 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x558 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x558 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x558 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x558 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x558 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x560 "QOSBW_BE_QOS_BANK[0] [172],QOSBW BE QOS BANK0 Register 172" bitfld.quad 0x560 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x560 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x560 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x560 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x560 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x560 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x568 "QOSBW_BE_QOS_BANK[0] [173],QOSBW BE QOS BANK0 Register 173" bitfld.quad 0x568 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x568 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x568 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x568 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x568 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x568 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x570 "QOSBW_BE_QOS_BANK[0] [174],QOSBW BE QOS BANK0 Register 174" bitfld.quad 0x570 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x570 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x570 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x570 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x570 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x570 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x578 "QOSBW_BE_QOS_BANK[0] [175],QOSBW BE QOS BANK0 Register 175" bitfld.quad 0x578 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x578 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x578 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x578 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x578 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x578 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x580 "QOSBW_BE_QOS_BANK[0] [176],QOSBW BE QOS BANK0 Register 176" bitfld.quad 0x580 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x580 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x580 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x580 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x580 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x580 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x588 "QOSBW_BE_QOS_BANK[0] [177],QOSBW BE QOS BANK0 Register 177" bitfld.quad 0x588 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x588 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x588 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x588 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x588 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x588 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x590 "QOSBW_BE_QOS_BANK[0] [178],QOSBW BE QOS BANK0 Register 178" bitfld.quad 0x590 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x590 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x590 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x590 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x590 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x590 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x598 "QOSBW_BE_QOS_BANK[0] [179],QOSBW BE QOS BANK0 Register 179" bitfld.quad 0x598 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x598 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x598 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x598 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x598 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x598 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5A0 "QOSBW_BE_QOS_BANK[0] [180],QOSBW BE QOS BANK0 Register 180" bitfld.quad 0x5A0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5A0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5A0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5A0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5A0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5A0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5A8 "QOSBW_BE_QOS_BANK[0] [181],QOSBW BE QOS BANK0 Register 181" bitfld.quad 0x5A8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5A8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5A8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5A8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5A8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5A8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5B0 "QOSBW_BE_QOS_BANK[0] [182],QOSBW BE QOS BANK0 Register 182" bitfld.quad 0x5B0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5B0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5B0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5B0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5B0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5B0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5B8 "QOSBW_BE_QOS_BANK[0] [183],QOSBW BE QOS BANK0 Register 183" bitfld.quad 0x5B8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5B8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5B8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5B8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5B8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5B8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5C0 "QOSBW_BE_QOS_BANK[0] [184],QOSBW BE QOS BANK0 Register 184" bitfld.quad 0x5C0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5C0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5C0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5C0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5C0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5C0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5C8 "QOSBW_BE_QOS_BANK[0] [185],QOSBW BE QOS BANK0 Register 185" bitfld.quad 0x5C8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5C8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5C8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5C8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5C8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5C8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5D0 "QOSBW_BE_QOS_BANK[0] [186],QOSBW BE QOS BANK0 Register 186" bitfld.quad 0x5D0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5D0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5D0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5D0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5D0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5D0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5D8 "QOSBW_BE_QOS_BANK[0] [187],QOSBW BE QOS BANK0 Register 187" bitfld.quad 0x5D8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5D8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5D8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5D8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5D8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5D8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5E0 "QOSBW_BE_QOS_BANK[0] [188],QOSBW BE QOS BANK0 Register 188" bitfld.quad 0x5E0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5E0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5E0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5E0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5E0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5E0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5E8 "QOSBW_BE_QOS_BANK[0] [189],QOSBW BE QOS BANK0 Register 189" bitfld.quad 0x5E8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5E8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5E8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5E8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5E8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5E8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5F0 "QOSBW_BE_QOS_BANK[0] [190],QOSBW BE QOS BANK0 Register 190" bitfld.quad 0x5F0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5F0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5F0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5F0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5F0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5F0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x5F8 "QOSBW_BE_QOS_BANK[0] [191],QOSBW BE QOS BANK0 Register 191" bitfld.quad 0x5F8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x5F8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x5F8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x5F8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x5F8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x5F8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x600 "QOSBW_BE_QOS_BANK[0] [192],QOSBW BE QOS BANK0 Register 192" bitfld.quad 0x600 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x600 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x600 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x600 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x600 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x600 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x608 "QOSBW_BE_QOS_BANK[0] [193],QOSBW BE QOS BANK0 Register 193" bitfld.quad 0x608 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x608 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x608 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x608 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x608 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x608 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x610 "QOSBW_BE_QOS_BANK[0] [194],QOSBW BE QOS BANK0 Register 194" bitfld.quad 0x610 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x610 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x610 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x610 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x610 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x610 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x618 "QOSBW_BE_QOS_BANK[0] [195],QOSBW BE QOS BANK0 Register 195" bitfld.quad 0x618 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x618 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x618 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x618 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x618 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x618 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x620 "QOSBW_BE_QOS_BANK[0] [196],QOSBW BE QOS BANK0 Register 196" bitfld.quad 0x620 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x620 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x620 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x620 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x620 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x620 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x628 "QOSBW_BE_QOS_BANK[0] [197],QOSBW BE QOS BANK0 Register 197" bitfld.quad 0x628 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x628 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x628 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x628 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x628 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x628 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x630 "QOSBW_BE_QOS_BANK[0] [198],QOSBW BE QOS BANK0 Register 198" bitfld.quad 0x630 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x630 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x630 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x630 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x630 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x630 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x638 "QOSBW_BE_QOS_BANK[0] [199],QOSBW BE QOS BANK0 Register 199" bitfld.quad 0x638 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x638 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x638 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x638 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x638 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x638 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x640 "QOSBW_BE_QOS_BANK[0] [200],QOSBW BE QOS BANK0 Register 200" bitfld.quad 0x640 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x640 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x640 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x640 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x640 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x640 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x648 "QOSBW_BE_QOS_BANK[0] [201],QOSBW BE QOS BANK0 Register 201" bitfld.quad 0x648 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x648 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x648 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x648 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x648 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x648 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x650 "QOSBW_BE_QOS_BANK[0] [202],QOSBW BE QOS BANK0 Register 202" bitfld.quad 0x650 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x650 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x650 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x650 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x650 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x650 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x658 "QOSBW_BE_QOS_BANK[0] [203],QOSBW BE QOS BANK0 Register 203" bitfld.quad 0x658 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x658 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x658 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x658 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x658 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x658 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x660 "QOSBW_BE_QOS_BANK[0] [204],QOSBW BE QOS BANK0 Register 204" bitfld.quad 0x660 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x660 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x660 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x660 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x660 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x660 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x668 "QOSBW_BE_QOS_BANK[0] [205],QOSBW BE QOS BANK0 Register 205" bitfld.quad 0x668 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x668 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x668 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x668 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x668 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x668 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x670 "QOSBW_BE_QOS_BANK[0] [206],QOSBW BE QOS BANK0 Register 206" bitfld.quad 0x670 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x670 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x670 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x670 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x670 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x670 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x678 "QOSBW_BE_QOS_BANK[0] [207],QOSBW BE QOS BANK0 Register 207" bitfld.quad 0x678 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x678 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x678 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x678 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x678 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x678 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x680 "QOSBW_BE_QOS_BANK[0] [208],QOSBW BE QOS BANK0 Register 208" bitfld.quad 0x680 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x680 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x680 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x680 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x680 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x680 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x688 "QOSBW_BE_QOS_BANK[0] [209],QOSBW BE QOS BANK0 Register 209" bitfld.quad 0x688 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x688 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x688 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x688 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x688 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x688 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x690 "QOSBW_BE_QOS_BANK[0] [210],QOSBW BE QOS BANK0 Register 210" bitfld.quad 0x690 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x690 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x690 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x690 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x690 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x690 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x698 "QOSBW_BE_QOS_BANK[0] [211],QOSBW BE QOS BANK0 Register 211" bitfld.quad 0x698 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x698 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x698 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x698 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x698 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x698 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6A0 "QOSBW_BE_QOS_BANK[0] [212],QOSBW BE QOS BANK0 Register 212" bitfld.quad 0x6A0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6A0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6A0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6A0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6A0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6A0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6A8 "QOSBW_BE_QOS_BANK[0] [213],QOSBW BE QOS BANK0 Register 213" bitfld.quad 0x6A8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6A8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6A8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6A8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6A8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6A8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6B0 "QOSBW_BE_QOS_BANK[0] [214],QOSBW BE QOS BANK0 Register 214" bitfld.quad 0x6B0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6B0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6B0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6B0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6B0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6B0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6B8 "QOSBW_BE_QOS_BANK[0] [215],QOSBW BE QOS BANK0 Register 215" bitfld.quad 0x6B8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6B8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6B8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6B8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6B8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6B8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6C0 "QOSBW_BE_QOS_BANK[0] [216],QOSBW BE QOS BANK0 Register 216" bitfld.quad 0x6C0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6C0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6C0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6C0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6C0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6C0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6C8 "QOSBW_BE_QOS_BANK[0] [217],QOSBW BE QOS BANK0 Register 217" bitfld.quad 0x6C8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6C8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6C8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6C8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6C8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6C8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6D0 "QOSBW_BE_QOS_BANK[0] [218],QOSBW BE QOS BANK0 Register 218" bitfld.quad 0x6D0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6D0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6D0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6D0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6D0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6D0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6D8 "QOSBW_BE_QOS_BANK[0] [219],QOSBW BE QOS BANK0 Register 219" bitfld.quad 0x6D8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6D8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6D8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6D8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6D8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6D8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6E0 "QOSBW_BE_QOS_BANK[0] [220],QOSBW BE QOS BANK0 Register 220" bitfld.quad 0x6E0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6E0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6E0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6E0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6E0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6E0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6E8 "QOSBW_BE_QOS_BANK[0] [221],QOSBW BE QOS BANK0 Register 221" bitfld.quad 0x6E8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6E8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6E8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6E8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6E8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6E8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6F0 "QOSBW_BE_QOS_BANK[0] [222],QOSBW BE QOS BANK0 Register 222" bitfld.quad 0x6F0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6F0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6F0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6F0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6F0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6F0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x6F8 "QOSBW_BE_QOS_BANK[0] [223],QOSBW BE QOS BANK0 Register 223" bitfld.quad 0x6F8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x6F8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x6F8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x6F8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x6F8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x6F8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x700 "QOSBW_BE_QOS_BANK[0] [224],QOSBW BE QOS BANK0 Register 224" bitfld.quad 0x700 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x700 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x700 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x700 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x700 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x700 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x708 "QOSBW_BE_QOS_BANK[0] [225],QOSBW BE QOS BANK0 Register 225" bitfld.quad 0x708 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x708 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x708 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x708 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x708 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x708 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x710 "QOSBW_BE_QOS_BANK[0] [226],QOSBW BE QOS BANK0 Register 226" bitfld.quad 0x710 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x710 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x710 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x710 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x710 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x710 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x718 "QOSBW_BE_QOS_BANK[0] [227],QOSBW BE QOS BANK0 Register 227" bitfld.quad 0x718 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x718 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x718 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x718 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x718 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x718 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x720 "QOSBW_BE_QOS_BANK[0] [228],QOSBW BE QOS BANK0 Register 228" bitfld.quad 0x720 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x720 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x720 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x720 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x720 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x720 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x728 "QOSBW_BE_QOS_BANK[0] [229],QOSBW BE QOS BANK0 Register 229" bitfld.quad 0x728 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x728 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x728 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x728 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x728 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x728 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x730 "QOSBW_BE_QOS_BANK[0] [230],QOSBW BE QOS BANK0 Register 230" bitfld.quad 0x730 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x730 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x730 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x730 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x730 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x730 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x738 "QOSBW_BE_QOS_BANK[0] [231],QOSBW BE QOS BANK0 Register 231" bitfld.quad 0x738 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x738 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x738 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x738 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x738 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x738 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x740 "QOSBW_BE_QOS_BANK[0] [232],QOSBW BE QOS BANK0 Register 232" bitfld.quad 0x740 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x740 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x740 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x740 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x740 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x740 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x748 "QOSBW_BE_QOS_BANK[0] [233],QOSBW BE QOS BANK0 Register 233" bitfld.quad 0x748 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x748 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x748 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x748 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x748 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x748 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x750 "QOSBW_BE_QOS_BANK[0] [234],QOSBW BE QOS BANK0 Register 234" bitfld.quad 0x750 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x750 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x750 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x750 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x750 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x750 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x758 "QOSBW_BE_QOS_BANK[0] [235],QOSBW BE QOS BANK0 Register 235" bitfld.quad 0x758 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x758 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x758 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x758 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x758 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x758 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x760 "QOSBW_BE_QOS_BANK[0] [236],QOSBW BE QOS BANK0 Register 236" bitfld.quad 0x760 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x760 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x760 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x760 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x760 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x760 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x768 "QOSBW_BE_QOS_BANK[0] [237],QOSBW BE QOS BANK0 Register 237" bitfld.quad 0x768 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x768 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x768 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x768 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x768 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x768 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x770 "QOSBW_BE_QOS_BANK[0] [238],QOSBW BE QOS BANK0 Register 238" bitfld.quad 0x770 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x770 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x770 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x770 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x770 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x770 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x778 "QOSBW_BE_QOS_BANK[0] [239],QOSBW BE QOS BANK0 Register 239" bitfld.quad 0x778 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x778 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x778 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x778 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x778 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x778 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x780 "QOSBW_BE_QOS_BANK[0] [240],QOSBW BE QOS BANK0 Register 240" bitfld.quad 0x780 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x780 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x780 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x780 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x780 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x780 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x788 "QOSBW_BE_QOS_BANK[0] [241],QOSBW BE QOS BANK0 Register 241" bitfld.quad 0x788 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x788 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x788 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x788 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x788 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x788 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x790 "QOSBW_BE_QOS_BANK[0] [242],QOSBW BE QOS BANK0 Register 242" bitfld.quad 0x790 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x790 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x790 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x790 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x790 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x790 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x798 "QOSBW_BE_QOS_BANK[0] [243],QOSBW BE QOS BANK0 Register 243" bitfld.quad 0x798 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x798 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x798 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x798 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x798 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x798 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7A0 "QOSBW_BE_QOS_BANK[0] [244],QOSBW BE QOS BANK0 Register 244" bitfld.quad 0x7A0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7A0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7A0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7A0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7A0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7A0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7A8 "QOSBW_BE_QOS_BANK[0] [245],QOSBW BE QOS BANK0 Register 245" bitfld.quad 0x7A8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7A8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7A8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7A8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7A8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7A8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7B0 "QOSBW_BE_QOS_BANK[0] [246],QOSBW BE QOS BANK0 Register 246" bitfld.quad 0x7B0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7B0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7B0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7B0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7B0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7B0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7B8 "QOSBW_BE_QOS_BANK[0] [247],QOSBW BE QOS BANK0 Register 247" bitfld.quad 0x7B8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7B8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7B8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7B8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7B8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7B8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7C0 "QOSBW_BE_QOS_BANK[0] [248],QOSBW BE QOS BANK0 Register 248" bitfld.quad 0x7C0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7C0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7C0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7C0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7C0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7C0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7C8 "QOSBW_BE_QOS_BANK[0] [249],QOSBW BE QOS BANK0 Register 249" bitfld.quad 0x7C8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7C8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7C8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7C8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7C8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7C8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7D0 "QOSBW_BE_QOS_BANK[0] [250],QOSBW BE QOS BANK0 Register 250" bitfld.quad 0x7D0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7D0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7D0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7D0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7D0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7D0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7D8 "QOSBW_BE_QOS_BANK[0] [251],QOSBW BE QOS BANK0 Register 251" bitfld.quad 0x7D8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7D8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7D8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7D8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7D8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7D8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7E0 "QOSBW_BE_QOS_BANK[0] [252],QOSBW BE QOS BANK0 Register 252" bitfld.quad 0x7E0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7E0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7E0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7E0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7E0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7E0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7E8 "QOSBW_BE_QOS_BANK[0] [253],QOSBW BE QOS BANK0 Register 253" bitfld.quad 0x7E8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7E8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7E8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7E8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7E8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7E8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7F0 "QOSBW_BE_QOS_BANK[0] [254],QOSBW BE QOS BANK0 Register 254" bitfld.quad 0x7F0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7F0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7F0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7F0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7F0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7F0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x7F8 "QOSBW_BE_QOS_BANK[0] [255],QOSBW BE QOS BANK0 Register 255" bitfld.quad 0x7F8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x7F8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x7F8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x7F8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x7F8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x7F8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x800 "QOSBW_BE_QOS_BANK[0] [256],QOSBW BE QOS BANK0 Register 256" bitfld.quad 0x800 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x800 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x800 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x800 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x800 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x800 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x808 "QOSBW_BE_QOS_BANK[0] [257],QOSBW BE QOS BANK0 Register 257" bitfld.quad 0x808 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x808 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x808 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x808 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x808 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x808 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x810 "QOSBW_BE_QOS_BANK[0] [258],QOSBW BE QOS BANK0 Register 258" bitfld.quad 0x810 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x810 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x810 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x810 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x810 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x810 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x818 "QOSBW_BE_QOS_BANK[0] [259],QOSBW BE QOS BANK0 Register 259" bitfld.quad 0x818 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x818 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x818 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x818 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x818 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x818 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x820 "QOSBW_BE_QOS_BANK[0] [260],QOSBW BE QOS BANK0 Register 260" bitfld.quad 0x820 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x820 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x820 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x820 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x820 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x820 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x828 "QOSBW_BE_QOS_BANK[0] [261],QOSBW BE QOS BANK0 Register 261" bitfld.quad 0x828 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x828 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x828 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x828 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x828 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x828 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x830 "QOSBW_BE_QOS_BANK[0] [262],QOSBW BE QOS BANK0 Register 262" bitfld.quad 0x830 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x830 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x830 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x830 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x830 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x830 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x838 "QOSBW_BE_QOS_BANK[0] [263],QOSBW BE QOS BANK0 Register 263" bitfld.quad 0x838 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x838 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x838 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x838 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x838 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x838 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x840 "QOSBW_BE_QOS_BANK[0] [264],QOSBW BE QOS BANK0 Register 264" bitfld.quad 0x840 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x840 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x840 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x840 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x840 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x840 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x848 "QOSBW_BE_QOS_BANK[0] [265],QOSBW BE QOS BANK0 Register 265" bitfld.quad 0x848 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x848 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x848 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x848 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x848 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x848 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x850 "QOSBW_BE_QOS_BANK[0] [266],QOSBW BE QOS BANK0 Register 266" bitfld.quad 0x850 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x850 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x850 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x850 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x850 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x850 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x858 "QOSBW_BE_QOS_BANK[0] [267],QOSBW BE QOS BANK0 Register 267" bitfld.quad 0x858 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x858 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x858 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x858 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x858 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x858 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x860 "QOSBW_BE_QOS_BANK[0] [268],QOSBW BE QOS BANK0 Register 268" bitfld.quad 0x860 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x860 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x860 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x860 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x860 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x860 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x868 "QOSBW_BE_QOS_BANK[0] [269],QOSBW BE QOS BANK0 Register 269" bitfld.quad 0x868 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x868 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x868 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x868 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x868 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x868 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x870 "QOSBW_BE_QOS_BANK[0] [270],QOSBW BE QOS BANK0 Register 270" bitfld.quad 0x870 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x870 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x870 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x870 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x870 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x870 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x878 "QOSBW_BE_QOS_BANK[0] [271],QOSBW BE QOS BANK0 Register 271" bitfld.quad 0x878 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x878 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x878 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x878 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x878 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x878 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x880 "QOSBW_BE_QOS_BANK[0] [272],QOSBW BE QOS BANK0 Register 272" bitfld.quad 0x880 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x880 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x880 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x880 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x880 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x880 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x888 "QOSBW_BE_QOS_BANK[0] [273],QOSBW BE QOS BANK0 Register 273" bitfld.quad 0x888 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x888 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x888 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x888 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x888 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x888 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x890 "QOSBW_BE_QOS_BANK[0] [274],QOSBW BE QOS BANK0 Register 274" bitfld.quad 0x890 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x890 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x890 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x890 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x890 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x890 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x898 "QOSBW_BE_QOS_BANK[0] [275],QOSBW BE QOS BANK0 Register 275" bitfld.quad 0x898 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x898 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x898 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x898 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x898 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x898 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8A0 "QOSBW_BE_QOS_BANK[0] [276],QOSBW BE QOS BANK0 Register 276" bitfld.quad 0x8A0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8A0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8A0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8A0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8A0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8A0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8A8 "QOSBW_BE_QOS_BANK[0] [277],QOSBW BE QOS BANK0 Register 277" bitfld.quad 0x8A8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8A8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8A8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8A8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8A8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8A8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8B0 "QOSBW_BE_QOS_BANK[0] [278],QOSBW BE QOS BANK0 Register 278" bitfld.quad 0x8B0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8B0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8B0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8B0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8B0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8B0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8B8 "QOSBW_BE_QOS_BANK[0] [279],QOSBW BE QOS BANK0 Register 279" bitfld.quad 0x8B8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8B8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8B8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8B8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8B8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8B8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8C0 "QOSBW_BE_QOS_BANK[0] [280],QOSBW BE QOS BANK0 Register 280" bitfld.quad 0x8C0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8C0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8C0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8C0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8C0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8C0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8C8 "QOSBW_BE_QOS_BANK[0] [281],QOSBW BE QOS BANK0 Register 281" bitfld.quad 0x8C8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8C8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8C8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8C8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8C8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8C8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8D0 "QOSBW_BE_QOS_BANK[0] [282],QOSBW BE QOS BANK0 Register 282" bitfld.quad 0x8D0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8D0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8D0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8D0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8D0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8D0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8D8 "QOSBW_BE_QOS_BANK[0] [283],QOSBW BE QOS BANK0 Register 283" bitfld.quad 0x8D8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8D8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8D8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8D8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8D8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8D8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8E0 "QOSBW_BE_QOS_BANK[0] [284],QOSBW BE QOS BANK0 Register 284" bitfld.quad 0x8E0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8E0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8E0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8E0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8E0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8E0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8E8 "QOSBW_BE_QOS_BANK[0] [285],QOSBW BE QOS BANK0 Register 285" bitfld.quad 0x8E8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8E8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8E8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8E8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8E8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8E8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8F0 "QOSBW_BE_QOS_BANK[0] [286],QOSBW BE QOS BANK0 Register 286" bitfld.quad 0x8F0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8F0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8F0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8F0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8F0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8F0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x8F8 "QOSBW_BE_QOS_BANK[0] [287],QOSBW BE QOS BANK0 Register 287" bitfld.quad 0x8F8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x8F8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x8F8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x8F8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x8F8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x8F8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x900 "QOSBW_BE_QOS_BANK[0] [288],QOSBW BE QOS BANK0 Register 288" bitfld.quad 0x900 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x900 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x900 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x900 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x900 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x900 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x908 "QOSBW_BE_QOS_BANK[0] [289],QOSBW BE QOS BANK0 Register 289" bitfld.quad 0x908 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x908 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x908 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x908 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x908 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x908 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x910 "QOSBW_BE_QOS_BANK[0] [290],QOSBW BE QOS BANK0 Register 290" bitfld.quad 0x910 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x910 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x910 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x910 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x910 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x910 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x918 "QOSBW_BE_QOS_BANK[0] [291],QOSBW BE QOS BANK0 Register 291" bitfld.quad 0x918 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x918 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x918 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x918 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x918 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x918 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x920 "QOSBW_BE_QOS_BANK[0] [292],QOSBW BE QOS BANK0 Register 292" bitfld.quad 0x920 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x920 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x920 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x920 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x920 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x920 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x928 "QOSBW_BE_QOS_BANK[0] [293],QOSBW BE QOS BANK0 Register 293" bitfld.quad 0x928 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x928 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x928 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x928 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x928 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x928 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x930 "QOSBW_BE_QOS_BANK[0] [294],QOSBW BE QOS BANK0 Register 294" bitfld.quad 0x930 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x930 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x930 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x930 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x930 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x930 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x938 "QOSBW_BE_QOS_BANK[0] [295],QOSBW BE QOS BANK0 Register 295" bitfld.quad 0x938 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x938 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x938 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x938 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x938 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x938 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x940 "QOSBW_BE_QOS_BANK[0] [296],QOSBW BE QOS BANK0 Register 296" bitfld.quad 0x940 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x940 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x940 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x940 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x940 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x940 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x948 "QOSBW_BE_QOS_BANK[0] [297],QOSBW BE QOS BANK0 Register 297" bitfld.quad 0x948 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x948 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x948 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x948 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x948 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x948 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x950 "QOSBW_BE_QOS_BANK[0] [298],QOSBW BE QOS BANK0 Register 298" bitfld.quad 0x950 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x950 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x950 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x950 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x950 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x950 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x958 "QOSBW_BE_QOS_BANK[0] [299],QOSBW BE QOS BANK0 Register 299" bitfld.quad 0x958 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x958 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x958 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x958 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x958 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x958 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x960 "QOSBW_BE_QOS_BANK[0] [300],QOSBW BE QOS BANK0 Register 300" bitfld.quad 0x960 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x960 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x960 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x960 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x960 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x960 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x968 "QOSBW_BE_QOS_BANK[0] [301],QOSBW BE QOS BANK0 Register 301" bitfld.quad 0x968 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x968 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x968 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x968 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x968 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x968 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x970 "QOSBW_BE_QOS_BANK[0] [302],QOSBW BE QOS BANK0 Register 302" bitfld.quad 0x970 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x970 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x970 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x970 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x970 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x970 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x978 "QOSBW_BE_QOS_BANK[0] [303],QOSBW BE QOS BANK0 Register 303" bitfld.quad 0x978 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x978 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x978 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x978 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x978 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x978 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x980 "QOSBW_BE_QOS_BANK[0] [304],QOSBW BE QOS BANK0 Register 304" bitfld.quad 0x980 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x980 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x980 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x980 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x980 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x980 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x988 "QOSBW_BE_QOS_BANK[0] [305],QOSBW BE QOS BANK0 Register 305" bitfld.quad 0x988 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x988 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x988 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x988 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x988 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x988 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x990 "QOSBW_BE_QOS_BANK[0] [306],QOSBW BE QOS BANK0 Register 306" bitfld.quad 0x990 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x990 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x990 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x990 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x990 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x990 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x998 "QOSBW_BE_QOS_BANK[0] [307],QOSBW BE QOS BANK0 Register 307" bitfld.quad 0x998 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x998 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x998 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x998 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x998 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x998 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9A0 "QOSBW_BE_QOS_BANK[0] [308],QOSBW BE QOS BANK0 Register 308" bitfld.quad 0x9A0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9A0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9A0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9A0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9A0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9A0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9A8 "QOSBW_BE_QOS_BANK[0] [309],QOSBW BE QOS BANK0 Register 309" bitfld.quad 0x9A8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9A8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9A8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9A8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9A8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9A8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9B0 "QOSBW_BE_QOS_BANK[0] [310],QOSBW BE QOS BANK0 Register 310" bitfld.quad 0x9B0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9B0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9B0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9B0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9B0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9B0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9B8 "QOSBW_BE_QOS_BANK[0] [311],QOSBW BE QOS BANK0 Register 311" bitfld.quad 0x9B8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9B8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9B8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9B8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9B8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9B8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9C0 "QOSBW_BE_QOS_BANK[0] [312],QOSBW BE QOS BANK0 Register 312" bitfld.quad 0x9C0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9C0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9C0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9C0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9C0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9C0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9C8 "QOSBW_BE_QOS_BANK[0] [313],QOSBW BE QOS BANK0 Register 313" bitfld.quad 0x9C8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9C8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9C8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9C8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9C8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9C8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9D0 "QOSBW_BE_QOS_BANK[0] [314],QOSBW BE QOS BANK0 Register 314" bitfld.quad 0x9D0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9D0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9D0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9D0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9D0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9D0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9D8 "QOSBW_BE_QOS_BANK[0] [315],QOSBW BE QOS BANK0 Register 315" bitfld.quad 0x9D8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9D8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9D8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9D8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9D8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9D8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9E0 "QOSBW_BE_QOS_BANK[0] [316],QOSBW BE QOS BANK0 Register 316" bitfld.quad 0x9E0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9E0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9E0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9E0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9E0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9E0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9E8 "QOSBW_BE_QOS_BANK[0] [317],QOSBW BE QOS BANK0 Register 317" bitfld.quad 0x9E8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9E8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9E8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9E8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9E8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9E8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9F0 "QOSBW_BE_QOS_BANK[0] [318],QOSBW BE QOS BANK0 Register 318" bitfld.quad 0x9F0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9F0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9F0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9F0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9F0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9F0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0x9F8 "QOSBW_BE_QOS_BANK[0] [319],QOSBW BE QOS BANK0 Register 319" bitfld.quad 0x9F8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0x9F8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0x9F8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0x9F8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0x9F8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0x9F8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA00 "QOSBW_BE_QOS_BANK[0] [320],QOSBW BE QOS BANK0 Register 320" bitfld.quad 0xA00 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA00 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA00 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA00 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA00 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA00 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA08 "QOSBW_BE_QOS_BANK[0] [321],QOSBW BE QOS BANK0 Register 321" bitfld.quad 0xA08 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA08 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA08 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA08 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA08 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA08 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA10 "QOSBW_BE_QOS_BANK[0] [322],QOSBW BE QOS BANK0 Register 322" bitfld.quad 0xA10 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA10 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA10 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA10 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA10 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA10 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA18 "QOSBW_BE_QOS_BANK[0] [323],QOSBW BE QOS BANK0 Register 323" bitfld.quad 0xA18 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA18 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA18 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA18 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA18 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA18 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA20 "QOSBW_BE_QOS_BANK[0] [324],QOSBW BE QOS BANK0 Register 324" bitfld.quad 0xA20 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA20 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA20 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA20 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA20 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA20 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA28 "QOSBW_BE_QOS_BANK[0] [325],QOSBW BE QOS BANK0 Register 325" bitfld.quad 0xA28 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA28 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA28 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA28 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA28 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA28 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA30 "QOSBW_BE_QOS_BANK[0] [326],QOSBW BE QOS BANK0 Register 326" bitfld.quad 0xA30 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA30 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA30 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA30 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA30 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA30 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA38 "QOSBW_BE_QOS_BANK[0] [327],QOSBW BE QOS BANK0 Register 327" bitfld.quad 0xA38 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA38 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA38 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA38 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA38 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA38 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA40 "QOSBW_BE_QOS_BANK[0] [328],QOSBW BE QOS BANK0 Register 328" bitfld.quad 0xA40 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA40 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA40 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA40 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA40 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA40 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA48 "QOSBW_BE_QOS_BANK[0] [329],QOSBW BE QOS BANK0 Register 329" bitfld.quad 0xA48 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA48 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA48 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA48 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA48 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA48 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA50 "QOSBW_BE_QOS_BANK[0] [330],QOSBW BE QOS BANK0 Register 330" bitfld.quad 0xA50 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA50 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA50 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA50 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA50 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA50 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA58 "QOSBW_BE_QOS_BANK[0] [331],QOSBW BE QOS BANK0 Register 331" bitfld.quad 0xA58 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA58 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA58 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA58 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA58 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA58 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA60 "QOSBW_BE_QOS_BANK[0] [332],QOSBW BE QOS BANK0 Register 332" bitfld.quad 0xA60 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA60 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA60 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA60 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA60 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA60 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA68 "QOSBW_BE_QOS_BANK[0] [333],QOSBW BE QOS BANK0 Register 333" bitfld.quad 0xA68 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA68 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA68 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA68 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA68 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA68 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA70 "QOSBW_BE_QOS_BANK[0] [334],QOSBW BE QOS BANK0 Register 334" bitfld.quad 0xA70 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA70 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA70 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA70 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA70 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA70 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA78 "QOSBW_BE_QOS_BANK[0] [335],QOSBW BE QOS BANK0 Register 335" bitfld.quad 0xA78 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA78 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA78 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA78 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA78 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA78 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA80 "QOSBW_BE_QOS_BANK[0] [336],QOSBW BE QOS BANK0 Register 336" bitfld.quad 0xA80 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA80 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA80 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA80 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA80 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA80 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA88 "QOSBW_BE_QOS_BANK[0] [337],QOSBW BE QOS BANK0 Register 337" bitfld.quad 0xA88 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA88 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA88 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA88 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA88 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA88 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA90 "QOSBW_BE_QOS_BANK[0] [338],QOSBW BE QOS BANK0 Register 338" bitfld.quad 0xA90 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA90 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA90 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA90 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA90 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA90 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xA98 "QOSBW_BE_QOS_BANK[0] [339],QOSBW BE QOS BANK0 Register 339" bitfld.quad 0xA98 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xA98 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xA98 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xA98 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xA98 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xA98 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAA0 "QOSBW_BE_QOS_BANK[0] [340],QOSBW BE QOS BANK0 Register 340" bitfld.quad 0xAA0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAA0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAA0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAA0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAA0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAA0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAA8 "QOSBW_BE_QOS_BANK[0] [341],QOSBW BE QOS BANK0 Register 341" bitfld.quad 0xAA8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAA8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAA8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAA8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAA8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAA8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAB0 "QOSBW_BE_QOS_BANK[0] [342],QOSBW BE QOS BANK0 Register 342" bitfld.quad 0xAB0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAB0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAB0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAB0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAB0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAB0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAB8 "QOSBW_BE_QOS_BANK[0] [343],QOSBW BE QOS BANK0 Register 343" bitfld.quad 0xAB8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAB8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAB8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAB8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAB8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAB8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAC0 "QOSBW_BE_QOS_BANK[0] [344],QOSBW BE QOS BANK0 Register 344" bitfld.quad 0xAC0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAC0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAC0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAC0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAC0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAC0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAC8 "QOSBW_BE_QOS_BANK[0] [345],QOSBW BE QOS BANK0 Register 345" bitfld.quad 0xAC8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAC8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAC8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAC8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAC8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAC8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAD0 "QOSBW_BE_QOS_BANK[0] [346],QOSBW BE QOS BANK0 Register 346" bitfld.quad 0xAD0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAD0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAD0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAD0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAD0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAD0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAD8 "QOSBW_BE_QOS_BANK[0] [347],QOSBW BE QOS BANK0 Register 347" bitfld.quad 0xAD8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAD8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAD8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAD8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAD8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAD8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAE0 "QOSBW_BE_QOS_BANK[0] [348],QOSBW BE QOS BANK0 Register 348" bitfld.quad 0xAE0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAE0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAE0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAE0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAE0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAE0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAE8 "QOSBW_BE_QOS_BANK[0] [349],QOSBW BE QOS BANK0 Register 349" bitfld.quad 0xAE8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAE8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAE8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAE8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAE8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAE8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAF0 "QOSBW_BE_QOS_BANK[0] [350],QOSBW BE QOS BANK0 Register 350" bitfld.quad 0xAF0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAF0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAF0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAF0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAF0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAF0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xAF8 "QOSBW_BE_QOS_BANK[0] [351],QOSBW BE QOS BANK0 Register 351" bitfld.quad 0xAF8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xAF8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xAF8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xAF8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xAF8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xAF8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB00 "QOSBW_BE_QOS_BANK[0] [352],QOSBW BE QOS BANK0 Register 352" bitfld.quad 0xB00 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB00 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB00 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB00 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB00 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB00 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB08 "QOSBW_BE_QOS_BANK[0] [353],QOSBW BE QOS BANK0 Register 353" bitfld.quad 0xB08 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB08 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB08 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB08 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB08 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB08 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB10 "QOSBW_BE_QOS_BANK[0] [354],QOSBW BE QOS BANK0 Register 354" bitfld.quad 0xB10 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB10 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB10 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB10 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB10 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB10 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB18 "QOSBW_BE_QOS_BANK[0] [355],QOSBW BE QOS BANK0 Register 355" bitfld.quad 0xB18 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB18 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB18 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB18 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB18 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB18 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB20 "QOSBW_BE_QOS_BANK[0] [356],QOSBW BE QOS BANK0 Register 356" bitfld.quad 0xB20 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB20 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB20 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB20 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB20 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB20 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB28 "QOSBW_BE_QOS_BANK[0] [357],QOSBW BE QOS BANK0 Register 357" bitfld.quad 0xB28 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB28 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB28 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB28 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB28 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB28 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB30 "QOSBW_BE_QOS_BANK[0] [358],QOSBW BE QOS BANK0 Register 358" bitfld.quad 0xB30 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB30 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB30 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB30 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB30 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB30 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB38 "QOSBW_BE_QOS_BANK[0] [359],QOSBW BE QOS BANK0 Register 359" bitfld.quad 0xB38 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB38 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB38 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB38 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB38 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB38 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB40 "QOSBW_BE_QOS_BANK[0] [360],QOSBW BE QOS BANK0 Register 360" bitfld.quad 0xB40 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB40 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB40 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB40 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB40 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB40 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB48 "QOSBW_BE_QOS_BANK[0] [361],QOSBW BE QOS BANK0 Register 361" bitfld.quad 0xB48 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB48 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB48 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB48 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB48 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB48 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB50 "QOSBW_BE_QOS_BANK[0] [362],QOSBW BE QOS BANK0 Register 362" bitfld.quad 0xB50 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB50 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB50 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB50 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB50 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB50 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB58 "QOSBW_BE_QOS_BANK[0] [363],QOSBW BE QOS BANK0 Register 363" bitfld.quad 0xB58 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB58 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB58 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB58 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB58 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB58 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB60 "QOSBW_BE_QOS_BANK[0] [364],QOSBW BE QOS BANK0 Register 364" bitfld.quad 0xB60 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB60 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB60 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB60 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB60 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB60 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB68 "QOSBW_BE_QOS_BANK[0] [365],QOSBW BE QOS BANK0 Register 365" bitfld.quad 0xB68 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB68 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB68 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB68 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB68 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB68 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB70 "QOSBW_BE_QOS_BANK[0] [366],QOSBW BE QOS BANK0 Register 366" bitfld.quad 0xB70 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB70 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB70 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB70 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB70 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB70 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB78 "QOSBW_BE_QOS_BANK[0] [367],QOSBW BE QOS BANK0 Register 367" bitfld.quad 0xB78 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB78 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB78 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB78 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB78 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB78 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB80 "QOSBW_BE_QOS_BANK[0] [368],QOSBW BE QOS BANK0 Register 368" bitfld.quad 0xB80 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB80 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB80 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB80 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB80 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB80 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB88 "QOSBW_BE_QOS_BANK[0] [369],QOSBW BE QOS BANK0 Register 369" bitfld.quad 0xB88 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB88 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB88 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB88 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB88 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB88 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB90 "QOSBW_BE_QOS_BANK[0] [370],QOSBW BE QOS BANK0 Register 370" bitfld.quad 0xB90 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB90 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB90 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB90 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB90 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB90 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xB98 "QOSBW_BE_QOS_BANK[0] [371],QOSBW BE QOS BANK0 Register 371" bitfld.quad 0xB98 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xB98 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xB98 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xB98 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xB98 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xB98 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBA0 "QOSBW_BE_QOS_BANK[0] [372],QOSBW BE QOS BANK0 Register 372" bitfld.quad 0xBA0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBA0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBA0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBA0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBA0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBA0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBA8 "QOSBW_BE_QOS_BANK[0] [373],QOSBW BE QOS BANK0 Register 373" bitfld.quad 0xBA8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBA8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBA8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBA8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBA8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBA8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBB0 "QOSBW_BE_QOS_BANK[0] [374],QOSBW BE QOS BANK0 Register 374" bitfld.quad 0xBB0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBB0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBB0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBB0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBB0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBB0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBB8 "QOSBW_BE_QOS_BANK[0] [375],QOSBW BE QOS BANK0 Register 375" bitfld.quad 0xBB8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBB8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBB8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBB8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBB8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBB8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBC0 "QOSBW_BE_QOS_BANK[0] [376],QOSBW BE QOS BANK0 Register 376" bitfld.quad 0xBC0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBC0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBC0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBC0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBC0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBC0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBC8 "QOSBW_BE_QOS_BANK[0] [377],QOSBW BE QOS BANK0 Register 377" bitfld.quad 0xBC8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBC8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBC8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBC8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBC8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBC8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBD0 "QOSBW_BE_QOS_BANK[0] [378],QOSBW BE QOS BANK0 Register 378" bitfld.quad 0xBD0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBD0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBD0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBD0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBD0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBD0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBD8 "QOSBW_BE_QOS_BANK[0] [379],QOSBW BE QOS BANK0 Register 379" bitfld.quad 0xBD8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBD8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBD8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBD8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBD8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBD8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBE0 "QOSBW_BE_QOS_BANK[0] [380],QOSBW BE QOS BANK0 Register 380" bitfld.quad 0xBE0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBE0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBE0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBE0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBE0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBE0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBE8 "QOSBW_BE_QOS_BANK[0] [381],QOSBW BE QOS BANK0 Register 381" bitfld.quad 0xBE8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBE8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBE8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBE8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBE8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBE8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBF0 "QOSBW_BE_QOS_BANK[0] [382],QOSBW BE QOS BANK0 Register 382" bitfld.quad 0xBF0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBF0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBF0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBF0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBF0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBF0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xBF8 "QOSBW_BE_QOS_BANK[0] [383],QOSBW BE QOS BANK0 Register 383" bitfld.quad 0xBF8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xBF8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xBF8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xBF8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xBF8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xBF8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC00 "QOSBW_BE_QOS_BANK[0] [384],QOSBW BE QOS BANK0 Register 384" bitfld.quad 0xC00 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC00 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC00 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC00 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC00 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC00 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC08 "QOSBW_BE_QOS_BANK[0] [385],QOSBW BE QOS BANK0 Register 385" bitfld.quad 0xC08 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC08 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC08 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC08 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC08 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC08 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC10 "QOSBW_BE_QOS_BANK[0] [386],QOSBW BE QOS BANK0 Register 386" bitfld.quad 0xC10 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC10 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC10 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC10 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC10 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC10 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC18 "QOSBW_BE_QOS_BANK[0] [387],QOSBW BE QOS BANK0 Register 387" bitfld.quad 0xC18 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC18 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC18 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC18 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC18 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC18 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC20 "QOSBW_BE_QOS_BANK[0] [388],QOSBW BE QOS BANK0 Register 388" bitfld.quad 0xC20 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC20 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC20 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC20 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC20 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC20 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC28 "QOSBW_BE_QOS_BANK[0] [389],QOSBW BE QOS BANK0 Register 389" bitfld.quad 0xC28 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC28 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC28 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC28 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC28 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC28 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC30 "QOSBW_BE_QOS_BANK[0] [390],QOSBW BE QOS BANK0 Register 390" bitfld.quad 0xC30 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC30 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC30 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC30 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC30 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC30 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC38 "QOSBW_BE_QOS_BANK[0] [391],QOSBW BE QOS BANK0 Register 391" bitfld.quad 0xC38 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC38 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC38 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC38 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC38 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC38 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC40 "QOSBW_BE_QOS_BANK[0] [392],QOSBW BE QOS BANK0 Register 392" bitfld.quad 0xC40 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC40 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC40 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC40 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC40 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC40 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC48 "QOSBW_BE_QOS_BANK[0] [393],QOSBW BE QOS BANK0 Register 393" bitfld.quad 0xC48 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC48 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC48 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC48 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC48 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC48 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC50 "QOSBW_BE_QOS_BANK[0] [394],QOSBW BE QOS BANK0 Register 394" bitfld.quad 0xC50 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC50 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC50 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC50 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC50 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC50 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC58 "QOSBW_BE_QOS_BANK[0] [395],QOSBW BE QOS BANK0 Register 395" bitfld.quad 0xC58 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC58 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC58 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC58 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC58 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC58 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC60 "QOSBW_BE_QOS_BANK[0] [396],QOSBW BE QOS BANK0 Register 396" bitfld.quad 0xC60 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC60 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC60 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC60 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC60 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC60 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC68 "QOSBW_BE_QOS_BANK[0] [397],QOSBW BE QOS BANK0 Register 397" bitfld.quad 0xC68 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC68 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC68 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC68 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC68 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC68 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC70 "QOSBW_BE_QOS_BANK[0] [398],QOSBW BE QOS BANK0 Register 398" bitfld.quad 0xC70 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC70 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC70 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC70 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC70 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC70 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC78 "QOSBW_BE_QOS_BANK[0] [399],QOSBW BE QOS BANK0 Register 399" bitfld.quad 0xC78 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC78 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC78 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC78 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC78 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC78 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC80 "QOSBW_BE_QOS_BANK[0] [400],QOSBW BE QOS BANK0 Register 400" bitfld.quad 0xC80 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC80 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC80 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC80 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC80 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC80 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC88 "QOSBW_BE_QOS_BANK[0] [401],QOSBW BE QOS BANK0 Register 401" bitfld.quad 0xC88 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC88 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC88 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC88 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC88 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC88 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC90 "QOSBW_BE_QOS_BANK[0] [402],QOSBW BE QOS BANK0 Register 402" bitfld.quad 0xC90 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC90 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC90 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC90 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC90 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC90 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xC98 "QOSBW_BE_QOS_BANK[0] [403],QOSBW BE QOS BANK0 Register 403" bitfld.quad 0xC98 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xC98 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xC98 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xC98 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xC98 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xC98 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCA0 "QOSBW_BE_QOS_BANK[0] [404],QOSBW BE QOS BANK0 Register 404" bitfld.quad 0xCA0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCA0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCA0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCA0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCA0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCA0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCA8 "QOSBW_BE_QOS_BANK[0] [405],QOSBW BE QOS BANK0 Register 405" bitfld.quad 0xCA8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCA8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCA8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCA8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCA8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCA8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCB0 "QOSBW_BE_QOS_BANK[0] [406],QOSBW BE QOS BANK0 Register 406" bitfld.quad 0xCB0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCB0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCB0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCB0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCB0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCB0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCB8 "QOSBW_BE_QOS_BANK[0] [407],QOSBW BE QOS BANK0 Register 407" bitfld.quad 0xCB8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCB8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCB8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCB8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCB8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCB8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCC0 "QOSBW_BE_QOS_BANK[0] [408],QOSBW BE QOS BANK0 Register 408" bitfld.quad 0xCC0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCC0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCC0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCC0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCC0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCC0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCC8 "QOSBW_BE_QOS_BANK[0] [409],QOSBW BE QOS BANK0 Register 409" bitfld.quad 0xCC8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCC8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCC8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCC8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCC8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCC8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCD0 "QOSBW_BE_QOS_BANK[0] [410],QOSBW BE QOS BANK0 Register 410" bitfld.quad 0xCD0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCD0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCD0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCD0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCD0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCD0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCD8 "QOSBW_BE_QOS_BANK[0] [411],QOSBW BE QOS BANK0 Register 411" bitfld.quad 0xCD8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCD8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCD8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCD8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCD8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCD8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCE0 "QOSBW_BE_QOS_BANK[0] [412],QOSBW BE QOS BANK0 Register 412" bitfld.quad 0xCE0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCE0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCE0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCE0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCE0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCE0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCE8 "QOSBW_BE_QOS_BANK[0] [413],QOSBW BE QOS BANK0 Register 413" bitfld.quad 0xCE8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCE8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCE8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCE8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCE8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCE8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCF0 "QOSBW_BE_QOS_BANK[0] [414],QOSBW BE QOS BANK0 Register 414" bitfld.quad 0xCF0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCF0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCF0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCF0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCF0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCF0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xCF8 "QOSBW_BE_QOS_BANK[0] [415],QOSBW BE QOS BANK0 Register 415" bitfld.quad 0xCF8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xCF8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xCF8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xCF8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xCF8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xCF8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD00 "QOSBW_BE_QOS_BANK[0] [416],QOSBW BE QOS BANK0 Register 416" bitfld.quad 0xD00 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD00 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD00 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD00 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD00 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD00 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD08 "QOSBW_BE_QOS_BANK[0] [417],QOSBW BE QOS BANK0 Register 417" bitfld.quad 0xD08 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD08 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD08 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD08 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD08 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD08 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD10 "QOSBW_BE_QOS_BANK[0] [418],QOSBW BE QOS BANK0 Register 418" bitfld.quad 0xD10 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD10 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD10 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD10 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD10 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD10 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD18 "QOSBW_BE_QOS_BANK[0] [419],QOSBW BE QOS BANK0 Register 419" bitfld.quad 0xD18 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD18 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD18 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD18 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD18 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD18 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD20 "QOSBW_BE_QOS_BANK[0] [420],QOSBW BE QOS BANK0 Register 420" bitfld.quad 0xD20 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD20 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD20 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD20 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD20 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD20 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD28 "QOSBW_BE_QOS_BANK[0] [421],QOSBW BE QOS BANK0 Register 421" bitfld.quad 0xD28 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD28 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD28 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD28 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD28 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD28 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD30 "QOSBW_BE_QOS_BANK[0] [422],QOSBW BE QOS BANK0 Register 422" bitfld.quad 0xD30 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD30 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD30 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD30 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD30 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD30 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD38 "QOSBW_BE_QOS_BANK[0] [423],QOSBW BE QOS BANK0 Register 423" bitfld.quad 0xD38 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD38 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD38 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD38 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD38 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD38 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD40 "QOSBW_BE_QOS_BANK[0] [424],QOSBW BE QOS BANK0 Register 424" bitfld.quad 0xD40 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD40 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD40 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD40 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD40 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD40 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD48 "QOSBW_BE_QOS_BANK[0] [425],QOSBW BE QOS BANK0 Register 425" bitfld.quad 0xD48 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD48 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD48 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD48 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD48 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD48 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD50 "QOSBW_BE_QOS_BANK[0] [426],QOSBW BE QOS BANK0 Register 426" bitfld.quad 0xD50 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD50 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD50 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD50 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD50 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD50 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD58 "QOSBW_BE_QOS_BANK[0] [427],QOSBW BE QOS BANK0 Register 427" bitfld.quad 0xD58 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD58 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD58 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD58 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD58 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD58 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD60 "QOSBW_BE_QOS_BANK[0] [428],QOSBW BE QOS BANK0 Register 428" bitfld.quad 0xD60 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD60 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD60 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD60 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD60 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD60 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD68 "QOSBW_BE_QOS_BANK[0] [429],QOSBW BE QOS BANK0 Register 429" bitfld.quad 0xD68 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD68 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD68 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD68 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD68 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD68 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD70 "QOSBW_BE_QOS_BANK[0] [430],QOSBW BE QOS BANK0 Register 430" bitfld.quad 0xD70 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD70 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD70 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD70 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD70 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD70 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD78 "QOSBW_BE_QOS_BANK[0] [431],QOSBW BE QOS BANK0 Register 431" bitfld.quad 0xD78 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD78 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD78 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD78 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD78 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD78 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD80 "QOSBW_BE_QOS_BANK[0] [432],QOSBW BE QOS BANK0 Register 432" bitfld.quad 0xD80 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD80 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD80 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD80 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD80 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD80 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD88 "QOSBW_BE_QOS_BANK[0] [433],QOSBW BE QOS BANK0 Register 433" bitfld.quad 0xD88 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD88 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD88 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD88 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD88 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD88 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD90 "QOSBW_BE_QOS_BANK[0] [434],QOSBW BE QOS BANK0 Register 434" bitfld.quad 0xD90 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD90 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD90 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD90 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD90 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD90 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xD98 "QOSBW_BE_QOS_BANK[0] [435],QOSBW BE QOS BANK0 Register 435" bitfld.quad 0xD98 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xD98 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xD98 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xD98 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xD98 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xD98 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDA0 "QOSBW_BE_QOS_BANK[0] [436],QOSBW BE QOS BANK0 Register 436" bitfld.quad 0xDA0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDA0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDA0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDA0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDA0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDA0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDA8 "QOSBW_BE_QOS_BANK[0] [437],QOSBW BE QOS BANK0 Register 437" bitfld.quad 0xDA8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDA8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDA8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDA8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDA8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDA8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDB0 "QOSBW_BE_QOS_BANK[0] [438],QOSBW BE QOS BANK0 Register 438" bitfld.quad 0xDB0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDB0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDB0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDB0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDB0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDB0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDB8 "QOSBW_BE_QOS_BANK[0] [439],QOSBW BE QOS BANK0 Register 439" bitfld.quad 0xDB8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDB8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDB8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDB8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDB8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDB8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDC0 "QOSBW_BE_QOS_BANK[0] [440],QOSBW BE QOS BANK0 Register 440" bitfld.quad 0xDC0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDC0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDC0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDC0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDC0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDC0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDC8 "QOSBW_BE_QOS_BANK[0] [441],QOSBW BE QOS BANK0 Register 441" bitfld.quad 0xDC8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDC8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDC8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDC8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDC8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDC8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDD0 "QOSBW_BE_QOS_BANK[0] [442],QOSBW BE QOS BANK0 Register 442" bitfld.quad 0xDD0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDD0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDD0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDD0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDD0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDD0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDD8 "QOSBW_BE_QOS_BANK[0] [443],QOSBW BE QOS BANK0 Register 443" bitfld.quad 0xDD8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDD8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDD8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDD8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDD8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDD8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDE0 "QOSBW_BE_QOS_BANK[0] [444],QOSBW BE QOS BANK0 Register 444" bitfld.quad 0xDE0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDE0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDE0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDE0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDE0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDE0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDE8 "QOSBW_BE_QOS_BANK[0] [445],QOSBW BE QOS BANK0 Register 445" bitfld.quad 0xDE8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDE8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDE8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDE8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDE8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDE8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDF0 "QOSBW_BE_QOS_BANK[0] [446],QOSBW BE QOS BANK0 Register 446" bitfld.quad 0xDF0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDF0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDF0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDF0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDF0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDF0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xDF8 "QOSBW_BE_QOS_BANK[0] [447],QOSBW BE QOS BANK0 Register 447" bitfld.quad 0xDF8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xDF8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xDF8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xDF8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xDF8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xDF8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE00 "QOSBW_BE_QOS_BANK[0] [448],QOSBW BE QOS BANK0 Register 448" bitfld.quad 0xE00 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE00 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE00 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE00 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE00 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE00 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE08 "QOSBW_BE_QOS_BANK[0] [449],QOSBW BE QOS BANK0 Register 449" bitfld.quad 0xE08 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE08 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE08 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE08 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE08 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE08 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE10 "QOSBW_BE_QOS_BANK[0] [450],QOSBW BE QOS BANK0 Register 450" bitfld.quad 0xE10 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE10 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE10 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE10 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE10 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE10 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE18 "QOSBW_BE_QOS_BANK[0] [451],QOSBW BE QOS BANK0 Register 451" bitfld.quad 0xE18 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE18 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE18 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE18 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE18 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE18 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE20 "QOSBW_BE_QOS_BANK[0] [452],QOSBW BE QOS BANK0 Register 452" bitfld.quad 0xE20 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE20 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE20 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE20 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE20 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE20 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE28 "QOSBW_BE_QOS_BANK[0] [453],QOSBW BE QOS BANK0 Register 453" bitfld.quad 0xE28 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE28 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE28 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE28 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE28 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE28 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE30 "QOSBW_BE_QOS_BANK[0] [454],QOSBW BE QOS BANK0 Register 454" bitfld.quad 0xE30 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE30 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE30 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE30 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE30 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE30 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE38 "QOSBW_BE_QOS_BANK[0] [455],QOSBW BE QOS BANK0 Register 455" bitfld.quad 0xE38 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE38 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE38 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE38 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE38 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE38 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE40 "QOSBW_BE_QOS_BANK[0] [456],QOSBW BE QOS BANK0 Register 456" bitfld.quad 0xE40 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE40 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE40 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE40 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE40 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE40 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE48 "QOSBW_BE_QOS_BANK[0] [457],QOSBW BE QOS BANK0 Register 457" bitfld.quad 0xE48 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE48 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE48 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE48 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE48 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE48 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE50 "QOSBW_BE_QOS_BANK[0] [458],QOSBW BE QOS BANK0 Register 458" bitfld.quad 0xE50 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE50 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE50 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE50 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE50 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE50 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE58 "QOSBW_BE_QOS_BANK[0] [459],QOSBW BE QOS BANK0 Register 459" bitfld.quad 0xE58 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE58 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE58 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE58 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE58 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE58 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE60 "QOSBW_BE_QOS_BANK[0] [460],QOSBW BE QOS BANK0 Register 460" bitfld.quad 0xE60 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE60 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE60 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE60 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE60 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE60 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE68 "QOSBW_BE_QOS_BANK[0] [461],QOSBW BE QOS BANK0 Register 461" bitfld.quad 0xE68 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE68 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE68 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE68 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE68 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE68 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE70 "QOSBW_BE_QOS_BANK[0] [462],QOSBW BE QOS BANK0 Register 462" bitfld.quad 0xE70 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE70 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE70 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE70 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE70 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE70 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE78 "QOSBW_BE_QOS_BANK[0] [463],QOSBW BE QOS BANK0 Register 463" bitfld.quad 0xE78 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE78 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE78 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE78 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE78 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE78 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE80 "QOSBW_BE_QOS_BANK[0] [464],QOSBW BE QOS BANK0 Register 464" bitfld.quad 0xE80 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE80 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE80 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE80 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE80 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE80 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE88 "QOSBW_BE_QOS_BANK[0] [465],QOSBW BE QOS BANK0 Register 465" bitfld.quad 0xE88 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE88 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE88 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE88 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE88 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE88 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE90 "QOSBW_BE_QOS_BANK[0] [466],QOSBW BE QOS BANK0 Register 466" bitfld.quad 0xE90 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE90 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE90 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE90 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE90 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE90 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xE98 "QOSBW_BE_QOS_BANK[0] [467],QOSBW BE QOS BANK0 Register 467" bitfld.quad 0xE98 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xE98 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xE98 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xE98 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xE98 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xE98 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xEA0 "QOSBW_BE_QOS_BANK[0] [468],QOSBW BE QOS BANK0 Register 468" bitfld.quad 0xEA0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xEA0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xEA0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xEA0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xEA0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xEA0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xEA8 "QOSBW_BE_QOS_BANK[0] [469],QOSBW BE QOS BANK0 Register 469" bitfld.quad 0xEA8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xEA8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xEA8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xEA8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xEA8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xEA8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xEB0 "QOSBW_BE_QOS_BANK[0] [470],QOSBW BE QOS BANK0 Register 470" bitfld.quad 0xEB0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xEB0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xEB0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xEB0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xEB0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xEB0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xEB8 "QOSBW_BE_QOS_BANK[0] [471],QOSBW BE QOS BANK0 Register 471" bitfld.quad 0xEB8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xEB8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xEB8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xEB8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xEB8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xEB8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xEC0 "QOSBW_BE_QOS_BANK[0] [472],QOSBW BE QOS BANK0 Register 472" bitfld.quad 0xEC0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xEC0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xEC0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xEC0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xEC0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xEC0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xEC8 "QOSBW_BE_QOS_BANK[0] [473],QOSBW BE QOS BANK0 Register 473" bitfld.quad 0xEC8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xEC8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xEC8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xEC8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xEC8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xEC8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xED0 "QOSBW_BE_QOS_BANK[0] [474],QOSBW BE QOS BANK0 Register 474" bitfld.quad 0xED0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xED0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xED0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xED0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xED0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xED0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xED8 "QOSBW_BE_QOS_BANK[0] [475],QOSBW BE QOS BANK0 Register 475" bitfld.quad 0xED8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xED8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xED8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xED8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xED8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xED8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xEE0 "QOSBW_BE_QOS_BANK[0] [476],QOSBW BE QOS BANK0 Register 476" bitfld.quad 0xEE0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xEE0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xEE0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xEE0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xEE0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xEE0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xEE8 "QOSBW_BE_QOS_BANK[0] [477],QOSBW BE QOS BANK0 Register 477" bitfld.quad 0xEE8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xEE8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xEE8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xEE8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xEE8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xEE8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xEF0 "QOSBW_BE_QOS_BANK[0] [478],QOSBW BE QOS BANK0 Register 478" bitfld.quad 0xEF0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xEF0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xEF0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xEF0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xEF0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xEF0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xEF8 "QOSBW_BE_QOS_BANK[0] [479],QOSBW BE QOS BANK0 Register 479" bitfld.quad 0xEF8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xEF8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xEF8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xEF8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xEF8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xEF8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF00 "QOSBW_BE_QOS_BANK[0] [480],QOSBW BE QOS BANK0 Register 480" bitfld.quad 0xF00 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF00 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF00 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF00 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF00 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF00 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF08 "QOSBW_BE_QOS_BANK[0] [481],QOSBW BE QOS BANK0 Register 481" bitfld.quad 0xF08 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF08 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF08 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF08 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF08 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF08 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF10 "QOSBW_BE_QOS_BANK[0] [482],QOSBW BE QOS BANK0 Register 482" bitfld.quad 0xF10 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF10 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF10 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF10 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF10 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF10 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF18 "QOSBW_BE_QOS_BANK[0] [483],QOSBW BE QOS BANK0 Register 483" bitfld.quad 0xF18 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF18 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF18 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF18 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF18 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF18 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF20 "QOSBW_BE_QOS_BANK[0] [484],QOSBW BE QOS BANK0 Register 484" bitfld.quad 0xF20 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF20 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF20 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF20 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF20 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF20 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF28 "QOSBW_BE_QOS_BANK[0] [485],QOSBW BE QOS BANK0 Register 485" bitfld.quad 0xF28 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF28 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF28 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF28 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF28 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF28 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF30 "QOSBW_BE_QOS_BANK[0] [486],QOSBW BE QOS BANK0 Register 486" bitfld.quad 0xF30 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF30 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF30 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF30 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF30 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF30 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF38 "QOSBW_BE_QOS_BANK[0] [487],QOSBW BE QOS BANK0 Register 487" bitfld.quad 0xF38 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF38 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF38 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF38 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF38 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF38 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF40 "QOSBW_BE_QOS_BANK[0] [488],QOSBW BE QOS BANK0 Register 488" bitfld.quad 0xF40 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF40 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF40 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF40 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF40 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF40 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF48 "QOSBW_BE_QOS_BANK[0] [489],QOSBW BE QOS BANK0 Register 489" bitfld.quad 0xF48 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF48 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF48 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF48 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF48 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF48 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF50 "QOSBW_BE_QOS_BANK[0] [490],QOSBW BE QOS BANK0 Register 490" bitfld.quad 0xF50 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF50 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF50 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF50 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF50 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF50 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF58 "QOSBW_BE_QOS_BANK[0] [491],QOSBW BE QOS BANK0 Register 491" bitfld.quad 0xF58 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF58 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF58 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF58 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF58 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF58 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF60 "QOSBW_BE_QOS_BANK[0] [492],QOSBW BE QOS BANK0 Register 492" bitfld.quad 0xF60 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF60 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF60 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF60 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF60 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF60 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF68 "QOSBW_BE_QOS_BANK[0] [493],QOSBW BE QOS BANK0 Register 493" bitfld.quad 0xF68 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF68 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF68 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF68 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF68 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF68 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF70 "QOSBW_BE_QOS_BANK[0] [494],QOSBW BE QOS BANK0 Register 494" bitfld.quad 0xF70 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF70 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF70 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF70 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF70 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF70 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF78 "QOSBW_BE_QOS_BANK[0] [495],QOSBW BE QOS BANK0 Register 495" bitfld.quad 0xF78 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF78 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF78 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF78 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF78 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF78 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF80 "QOSBW_BE_QOS_BANK[0] [496],QOSBW BE QOS BANK0 Register 496" bitfld.quad 0xF80 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF80 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF80 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF80 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF80 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF80 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF88 "QOSBW_BE_QOS_BANK[0] [497],QOSBW BE QOS BANK0 Register 497" bitfld.quad 0xF88 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF88 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF88 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF88 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF88 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF88 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF90 "QOSBW_BE_QOS_BANK[0] [498],QOSBW BE QOS BANK0 Register 498" bitfld.quad 0xF90 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF90 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF90 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF90 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF90 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF90 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xF98 "QOSBW_BE_QOS_BANK[0] [499],QOSBW BE QOS BANK0 Register 499" bitfld.quad 0xF98 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xF98 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xF98 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xF98 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xF98 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xF98 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFA0 "QOSBW_BE_QOS_BANK[0] [500],QOSBW BE QOS BANK0 Register 500" bitfld.quad 0xFA0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFA0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFA0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFA0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFA0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFA0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFA8 "QOSBW_BE_QOS_BANK[0] [501],QOSBW BE QOS BANK0 Register 501" bitfld.quad 0xFA8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFA8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFA8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFA8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFA8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFA8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFB0 "QOSBW_BE_QOS_BANK[0] [502],QOSBW BE QOS BANK0 Register 502" bitfld.quad 0xFB0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFB0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFB0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFB0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFB0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFB0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFB8 "QOSBW_BE_QOS_BANK[0] [503],QOSBW BE QOS BANK0 Register 503" bitfld.quad 0xFB8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFB8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFB8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFB8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFB8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFB8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFC0 "QOSBW_BE_QOS_BANK[0] [504],QOSBW BE QOS BANK0 Register 504" bitfld.quad 0xFC0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFC0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFC0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFC0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFC0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFC0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFC8 "QOSBW_BE_QOS_BANK[0] [505],QOSBW BE QOS BANK0 Register 505" bitfld.quad 0xFC8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFC8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFC8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFC8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFC8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFC8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFD0 "QOSBW_BE_QOS_BANK[0] [506],QOSBW BE QOS BANK0 Register 506" bitfld.quad 0xFD0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFD0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFD0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFD0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFD0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFD0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFD8 "QOSBW_BE_QOS_BANK[0] [507],QOSBW BE QOS BANK0 Register 507" bitfld.quad 0xFD8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFD8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFD8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFD8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFD8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFD8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFE0 "QOSBW_BE_QOS_BANK[0] [508],QOSBW BE QOS BANK0 Register 508" bitfld.quad 0xFE0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFE0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFE0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFE0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFE0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFE0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFE8 "QOSBW_BE_QOS_BANK[0] [509],QOSBW BE QOS BANK0 Register 509" bitfld.quad 0xFE8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFE8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFE8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFE8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFE8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFE8 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFF0 "QOSBW_BE_QOS_BANK[0] [510],QOSBW BE QOS BANK0 Register 510" bitfld.quad 0xFF0 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFF0 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFF0 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFF0 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFF0 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFF0 0.--10. 1. "BEQOS_BANK0_0" line.quad 0xFF8 "QOSBW_BE_QOS_BANK[0] [511],QOSBW BE QOS BANK0 Register 511" bitfld.quad 0xFF8 52.--53. "BEQOS_BANK0_5" "0,1,2,3" hexmask.quad.byte 0xFF8 48.--51. 1. "BEQOS_BANK0_4" hexmask.quad.byte 0xFF8 36.--43. 1. "BEQOS_BANK0_3" newline hexmask.quad.word 0xFF8 20.--35. 1. "BEQOS_BANK0_2" hexmask.quad.word 0xFF8 10.--19. 1. "BEQOS_BANK0_1" hexmask.quad.word 0xFF8 0.--10. 1. "BEQOS_BANK0_0" group.quad 0x3000++0xFFF line.quad 0x0 "QOSBW_BE_QOS_BANK[1] [0],QOSBW BE QOS BANK1 Register 0" bitfld.quad 0x0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8 "QOSBW_BE_QOS_BANK[1] [1],QOSBW BE QOS BANK1 Register 1" bitfld.quad 0x8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x10 "QOSBW_BE_QOS_BANK[1] [2],QOSBW BE QOS BANK1 Register 2" bitfld.quad 0x10 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x10 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x10 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x10 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x10 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x10 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x18 "QOSBW_BE_QOS_BANK[1] [3],QOSBW BE QOS BANK1 Register 3" bitfld.quad 0x18 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x18 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x18 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x18 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x18 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x18 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x20 "QOSBW_BE_QOS_BANK[1] [4],QOSBW BE QOS BANK1 Register 4" bitfld.quad 0x20 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x20 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x20 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x20 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x20 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x20 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x28 "QOSBW_BE_QOS_BANK[1] [5],QOSBW BE QOS BANK1 Register 5" bitfld.quad 0x28 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x28 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x28 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x28 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x28 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x28 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x30 "QOSBW_BE_QOS_BANK[1] [6],QOSBW BE QOS BANK1 Register 6" bitfld.quad 0x30 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x30 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x30 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x30 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x30 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x30 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x38 "QOSBW_BE_QOS_BANK[1] [7],QOSBW BE QOS BANK1 Register 7" bitfld.quad 0x38 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x38 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x38 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x38 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x38 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x38 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x40 "QOSBW_BE_QOS_BANK[1] [8],QOSBW BE QOS BANK1 Register 8" bitfld.quad 0x40 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x40 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x40 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x40 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x40 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x40 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x48 "QOSBW_BE_QOS_BANK[1] [9],QOSBW BE QOS BANK1 Register 9" bitfld.quad 0x48 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x48 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x48 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x48 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x48 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x48 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x50 "QOSBW_BE_QOS_BANK[1] [10],QOSBW BE QOS BANK1 Register 10" bitfld.quad 0x50 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x50 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x50 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x50 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x50 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x50 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x58 "QOSBW_BE_QOS_BANK[1] [11],QOSBW BE QOS BANK1 Register 11" bitfld.quad 0x58 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x58 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x58 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x58 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x58 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x58 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x60 "QOSBW_BE_QOS_BANK[1] [12],QOSBW BE QOS BANK1 Register 12" bitfld.quad 0x60 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x60 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x60 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x60 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x60 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x60 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x68 "QOSBW_BE_QOS_BANK[1] [13],QOSBW BE QOS BANK1 Register 13" bitfld.quad 0x68 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x68 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x68 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x68 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x68 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x68 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x70 "QOSBW_BE_QOS_BANK[1] [14],QOSBW BE QOS BANK1 Register 14" bitfld.quad 0x70 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x70 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x70 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x70 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x70 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x70 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x78 "QOSBW_BE_QOS_BANK[1] [15],QOSBW BE QOS BANK1 Register 15" bitfld.quad 0x78 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x78 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x78 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x78 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x78 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x78 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x80 "QOSBW_BE_QOS_BANK[1] [16],QOSBW BE QOS BANK1 Register 16" bitfld.quad 0x80 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x80 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x80 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x80 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x80 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x80 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x88 "QOSBW_BE_QOS_BANK[1] [17],QOSBW BE QOS BANK1 Register 17" bitfld.quad 0x88 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x88 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x88 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x88 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x88 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x88 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x90 "QOSBW_BE_QOS_BANK[1] [18],QOSBW BE QOS BANK1 Register 18" bitfld.quad 0x90 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x90 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x90 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x90 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x90 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x90 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x98 "QOSBW_BE_QOS_BANK[1] [19],QOSBW BE QOS BANK1 Register 19" bitfld.quad 0x98 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x98 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x98 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x98 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x98 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x98 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA0 "QOSBW_BE_QOS_BANK[1] [20],QOSBW BE QOS BANK1 Register 20" bitfld.quad 0xA0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA8 "QOSBW_BE_QOS_BANK[1] [21],QOSBW BE QOS BANK1 Register 21" bitfld.quad 0xA8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB0 "QOSBW_BE_QOS_BANK[1] [22],QOSBW BE QOS BANK1 Register 22" bitfld.quad 0xB0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB8 "QOSBW_BE_QOS_BANK[1] [23],QOSBW BE QOS BANK1 Register 23" bitfld.quad 0xB8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC0 "QOSBW_BE_QOS_BANK[1] [24],QOSBW BE QOS BANK1 Register 24" bitfld.quad 0xC0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC8 "QOSBW_BE_QOS_BANK[1] [25],QOSBW BE QOS BANK1 Register 25" bitfld.quad 0xC8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD0 "QOSBW_BE_QOS_BANK[1] [26],QOSBW BE QOS BANK1 Register 26" bitfld.quad 0xD0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD8 "QOSBW_BE_QOS_BANK[1] [27],QOSBW BE QOS BANK1 Register 27" bitfld.quad 0xD8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE0 "QOSBW_BE_QOS_BANK[1] [28],QOSBW BE QOS BANK1 Register 28" bitfld.quad 0xE0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE8 "QOSBW_BE_QOS_BANK[1] [29],QOSBW BE QOS BANK1 Register 29" bitfld.quad 0xE8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF0 "QOSBW_BE_QOS_BANK[1] [30],QOSBW BE QOS BANK1 Register 30" bitfld.quad 0xF0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF8 "QOSBW_BE_QOS_BANK[1] [31],QOSBW BE QOS BANK1 Register 31" bitfld.quad 0xF8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x100 "QOSBW_BE_QOS_BANK[1] [32],QOSBW BE QOS BANK1 Register 32" bitfld.quad 0x100 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x100 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x100 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x100 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x100 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x100 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x108 "QOSBW_BE_QOS_BANK[1] [33],QOSBW BE QOS BANK1 Register 33" bitfld.quad 0x108 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x108 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x108 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x108 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x108 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x108 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x110 "QOSBW_BE_QOS_BANK[1] [34],QOSBW BE QOS BANK1 Register 34" bitfld.quad 0x110 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x110 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x110 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x110 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x110 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x110 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x118 "QOSBW_BE_QOS_BANK[1] [35],QOSBW BE QOS BANK1 Register 35" bitfld.quad 0x118 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x118 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x118 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x118 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x118 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x118 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x120 "QOSBW_BE_QOS_BANK[1] [36],QOSBW BE QOS BANK1 Register 36" bitfld.quad 0x120 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x120 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x120 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x120 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x120 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x120 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x128 "QOSBW_BE_QOS_BANK[1] [37],QOSBW BE QOS BANK1 Register 37" bitfld.quad 0x128 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x128 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x128 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x128 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x128 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x128 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x130 "QOSBW_BE_QOS_BANK[1] [38],QOSBW BE QOS BANK1 Register 38" bitfld.quad 0x130 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x130 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x130 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x130 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x130 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x130 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x138 "QOSBW_BE_QOS_BANK[1] [39],QOSBW BE QOS BANK1 Register 39" bitfld.quad 0x138 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x138 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x138 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x138 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x138 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x138 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x140 "QOSBW_BE_QOS_BANK[1] [40],QOSBW BE QOS BANK1 Register 40" bitfld.quad 0x140 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x140 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x140 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x140 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x140 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x140 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x148 "QOSBW_BE_QOS_BANK[1] [41],QOSBW BE QOS BANK1 Register 41" bitfld.quad 0x148 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x148 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x148 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x148 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x148 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x148 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x150 "QOSBW_BE_QOS_BANK[1] [42],QOSBW BE QOS BANK1 Register 42" bitfld.quad 0x150 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x150 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x150 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x150 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x150 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x150 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x158 "QOSBW_BE_QOS_BANK[1] [43],QOSBW BE QOS BANK1 Register 43" bitfld.quad 0x158 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x158 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x158 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x158 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x158 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x158 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x160 "QOSBW_BE_QOS_BANK[1] [44],QOSBW BE QOS BANK1 Register 44" bitfld.quad 0x160 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x160 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x160 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x160 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x160 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x160 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x168 "QOSBW_BE_QOS_BANK[1] [45],QOSBW BE QOS BANK1 Register 45" bitfld.quad 0x168 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x168 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x168 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x168 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x168 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x168 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x170 "QOSBW_BE_QOS_BANK[1] [46],QOSBW BE QOS BANK1 Register 46" bitfld.quad 0x170 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x170 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x170 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x170 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x170 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x170 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x178 "QOSBW_BE_QOS_BANK[1] [47],QOSBW BE QOS BANK1 Register 47" bitfld.quad 0x178 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x178 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x178 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x178 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x178 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x178 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x180 "QOSBW_BE_QOS_BANK[1] [48],QOSBW BE QOS BANK1 Register 48" bitfld.quad 0x180 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x180 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x180 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x180 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x180 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x180 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x188 "QOSBW_BE_QOS_BANK[1] [49],QOSBW BE QOS BANK1 Register 49" bitfld.quad 0x188 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x188 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x188 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x188 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x188 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x188 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x190 "QOSBW_BE_QOS_BANK[1] [50],QOSBW BE QOS BANK1 Register 50" bitfld.quad 0x190 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x190 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x190 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x190 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x190 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x190 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x198 "QOSBW_BE_QOS_BANK[1] [51],QOSBW BE QOS BANK1 Register 51" bitfld.quad 0x198 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x198 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x198 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x198 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x198 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x198 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1A0 "QOSBW_BE_QOS_BANK[1] [52],QOSBW BE QOS BANK1 Register 52" bitfld.quad 0x1A0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1A0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1A0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1A0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1A0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1A0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1A8 "QOSBW_BE_QOS_BANK[1] [53],QOSBW BE QOS BANK1 Register 53" bitfld.quad 0x1A8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1A8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1A8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1A8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1A8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1A8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1B0 "QOSBW_BE_QOS_BANK[1] [54],QOSBW BE QOS BANK1 Register 54" bitfld.quad 0x1B0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1B0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1B0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1B0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1B0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1B0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1B8 "QOSBW_BE_QOS_BANK[1] [55],QOSBW BE QOS BANK1 Register 55" bitfld.quad 0x1B8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1B8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1B8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1B8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1B8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1B8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1C0 "QOSBW_BE_QOS_BANK[1] [56],QOSBW BE QOS BANK1 Register 56" bitfld.quad 0x1C0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1C0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1C0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1C0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1C0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1C0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1C8 "QOSBW_BE_QOS_BANK[1] [57],QOSBW BE QOS BANK1 Register 57" bitfld.quad 0x1C8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1C8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1C8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1C8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1C8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1C8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1D0 "QOSBW_BE_QOS_BANK[1] [58],QOSBW BE QOS BANK1 Register 58" bitfld.quad 0x1D0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1D0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1D0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1D0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1D0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1D0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1D8 "QOSBW_BE_QOS_BANK[1] [59],QOSBW BE QOS BANK1 Register 59" bitfld.quad 0x1D8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1D8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1D8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1D8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1D8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1D8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1E0 "QOSBW_BE_QOS_BANK[1] [60],QOSBW BE QOS BANK1 Register 60" bitfld.quad 0x1E0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1E0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1E0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1E0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1E0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1E0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1E8 "QOSBW_BE_QOS_BANK[1] [61],QOSBW BE QOS BANK1 Register 61" bitfld.quad 0x1E8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1E8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1E8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1E8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1E8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1E8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1F0 "QOSBW_BE_QOS_BANK[1] [62],QOSBW BE QOS BANK1 Register 62" bitfld.quad 0x1F0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1F0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1F0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1F0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1F0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1F0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x1F8 "QOSBW_BE_QOS_BANK[1] [63],QOSBW BE QOS BANK1 Register 63" bitfld.quad 0x1F8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x1F8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x1F8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x1F8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x1F8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x1F8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x200 "QOSBW_BE_QOS_BANK[1] [64],QOSBW BE QOS BANK1 Register 64" bitfld.quad 0x200 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x200 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x200 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x200 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x200 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x200 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x208 "QOSBW_BE_QOS_BANK[1] [65],QOSBW BE QOS BANK1 Register 65" bitfld.quad 0x208 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x208 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x208 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x208 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x208 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x208 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x210 "QOSBW_BE_QOS_BANK[1] [66],QOSBW BE QOS BANK1 Register 66" bitfld.quad 0x210 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x210 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x210 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x210 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x210 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x210 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x218 "QOSBW_BE_QOS_BANK[1] [67],QOSBW BE QOS BANK1 Register 67" bitfld.quad 0x218 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x218 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x218 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x218 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x218 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x218 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x220 "QOSBW_BE_QOS_BANK[1] [68],QOSBW BE QOS BANK1 Register 68" bitfld.quad 0x220 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x220 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x220 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x220 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x220 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x220 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x228 "QOSBW_BE_QOS_BANK[1] [69],QOSBW BE QOS BANK1 Register 69" bitfld.quad 0x228 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x228 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x228 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x228 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x228 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x228 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x230 "QOSBW_BE_QOS_BANK[1] [70],QOSBW BE QOS BANK1 Register 70" bitfld.quad 0x230 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x230 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x230 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x230 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x230 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x230 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x238 "QOSBW_BE_QOS_BANK[1] [71],QOSBW BE QOS BANK1 Register 71" bitfld.quad 0x238 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x238 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x238 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x238 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x238 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x238 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x240 "QOSBW_BE_QOS_BANK[1] [72],QOSBW BE QOS BANK1 Register 72" bitfld.quad 0x240 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x240 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x240 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x240 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x240 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x240 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x248 "QOSBW_BE_QOS_BANK[1] [73],QOSBW BE QOS BANK1 Register 73" bitfld.quad 0x248 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x248 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x248 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x248 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x248 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x248 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x250 "QOSBW_BE_QOS_BANK[1] [74],QOSBW BE QOS BANK1 Register 74" bitfld.quad 0x250 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x250 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x250 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x250 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x250 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x250 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x258 "QOSBW_BE_QOS_BANK[1] [75],QOSBW BE QOS BANK1 Register 75" bitfld.quad 0x258 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x258 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x258 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x258 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x258 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x258 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x260 "QOSBW_BE_QOS_BANK[1] [76],QOSBW BE QOS BANK1 Register 76" bitfld.quad 0x260 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x260 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x260 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x260 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x260 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x260 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x268 "QOSBW_BE_QOS_BANK[1] [77],QOSBW BE QOS BANK1 Register 77" bitfld.quad 0x268 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x268 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x268 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x268 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x268 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x268 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x270 "QOSBW_BE_QOS_BANK[1] [78],QOSBW BE QOS BANK1 Register 78" bitfld.quad 0x270 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x270 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x270 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x270 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x270 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x270 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x278 "QOSBW_BE_QOS_BANK[1] [79],QOSBW BE QOS BANK1 Register 79" bitfld.quad 0x278 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x278 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x278 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x278 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x278 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x278 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x280 "QOSBW_BE_QOS_BANK[1] [80],QOSBW BE QOS BANK1 Register 80" bitfld.quad 0x280 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x280 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x280 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x280 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x280 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x280 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x288 "QOSBW_BE_QOS_BANK[1] [81],QOSBW BE QOS BANK1 Register 81" bitfld.quad 0x288 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x288 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x288 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x288 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x288 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x288 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x290 "QOSBW_BE_QOS_BANK[1] [82],QOSBW BE QOS BANK1 Register 82" bitfld.quad 0x290 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x290 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x290 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x290 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x290 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x290 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x298 "QOSBW_BE_QOS_BANK[1] [83],QOSBW BE QOS BANK1 Register 83" bitfld.quad 0x298 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x298 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x298 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x298 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x298 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x298 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2A0 "QOSBW_BE_QOS_BANK[1] [84],QOSBW BE QOS BANK1 Register 84" bitfld.quad 0x2A0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2A0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2A0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2A0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2A0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2A0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2A8 "QOSBW_BE_QOS_BANK[1] [85],QOSBW BE QOS BANK1 Register 85" bitfld.quad 0x2A8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2A8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2A8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2A8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2A8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2A8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2B0 "QOSBW_BE_QOS_BANK[1] [86],QOSBW BE QOS BANK1 Register 86" bitfld.quad 0x2B0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2B0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2B0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2B0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2B0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2B0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2B8 "QOSBW_BE_QOS_BANK[1] [87],QOSBW BE QOS BANK1 Register 87" bitfld.quad 0x2B8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2B8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2B8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2B8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2B8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2B8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2C0 "QOSBW_BE_QOS_BANK[1] [88],QOSBW BE QOS BANK1 Register 88" bitfld.quad 0x2C0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2C0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2C0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2C0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2C0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2C0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2C8 "QOSBW_BE_QOS_BANK[1] [89],QOSBW BE QOS BANK1 Register 89" bitfld.quad 0x2C8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2C8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2C8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2C8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2C8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2C8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2D0 "QOSBW_BE_QOS_BANK[1] [90],QOSBW BE QOS BANK1 Register 90" bitfld.quad 0x2D0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2D0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2D0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2D0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2D0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2D0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2D8 "QOSBW_BE_QOS_BANK[1] [91],QOSBW BE QOS BANK1 Register 91" bitfld.quad 0x2D8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2D8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2D8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2D8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2D8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2D8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2E0 "QOSBW_BE_QOS_BANK[1] [92],QOSBW BE QOS BANK1 Register 92" bitfld.quad 0x2E0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2E0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2E0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2E0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2E0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2E0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2E8 "QOSBW_BE_QOS_BANK[1] [93],QOSBW BE QOS BANK1 Register 93" bitfld.quad 0x2E8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2E8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2E8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2E8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2E8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2E8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2F0 "QOSBW_BE_QOS_BANK[1] [94],QOSBW BE QOS BANK1 Register 94" bitfld.quad 0x2F0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2F0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2F0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2F0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2F0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2F0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x2F8 "QOSBW_BE_QOS_BANK[1] [95],QOSBW BE QOS BANK1 Register 95" bitfld.quad 0x2F8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x2F8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x2F8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x2F8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x2F8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x2F8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x300 "QOSBW_BE_QOS_BANK[1] [96],QOSBW BE QOS BANK1 Register 96" bitfld.quad 0x300 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x300 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x300 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x300 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x300 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x300 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x308 "QOSBW_BE_QOS_BANK[1] [97],QOSBW BE QOS BANK1 Register 97" bitfld.quad 0x308 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x308 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x308 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x308 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x308 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x308 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x310 "QOSBW_BE_QOS_BANK[1] [98],QOSBW BE QOS BANK1 Register 98" bitfld.quad 0x310 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x310 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x310 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x310 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x310 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x310 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x318 "QOSBW_BE_QOS_BANK[1] [99],QOSBW BE QOS BANK1 Register 99" bitfld.quad 0x318 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x318 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x318 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x318 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x318 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x318 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x320 "QOSBW_BE_QOS_BANK[1] [100],QOSBW BE QOS BANK1 Register 100" bitfld.quad 0x320 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x320 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x320 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x320 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x320 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x320 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x328 "QOSBW_BE_QOS_BANK[1] [101],QOSBW BE QOS BANK1 Register 101" bitfld.quad 0x328 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x328 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x328 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x328 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x328 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x328 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x330 "QOSBW_BE_QOS_BANK[1] [102],QOSBW BE QOS BANK1 Register 102" bitfld.quad 0x330 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x330 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x330 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x330 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x330 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x330 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x338 "QOSBW_BE_QOS_BANK[1] [103],QOSBW BE QOS BANK1 Register 103" bitfld.quad 0x338 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x338 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x338 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x338 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x338 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x338 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x340 "QOSBW_BE_QOS_BANK[1] [104],QOSBW BE QOS BANK1 Register 104" bitfld.quad 0x340 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x340 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x340 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x340 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x340 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x340 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x348 "QOSBW_BE_QOS_BANK[1] [105],QOSBW BE QOS BANK1 Register 105" bitfld.quad 0x348 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x348 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x348 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x348 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x348 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x348 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x350 "QOSBW_BE_QOS_BANK[1] [106],QOSBW BE QOS BANK1 Register 106" bitfld.quad 0x350 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x350 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x350 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x350 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x350 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x350 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x358 "QOSBW_BE_QOS_BANK[1] [107],QOSBW BE QOS BANK1 Register 107" bitfld.quad 0x358 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x358 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x358 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x358 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x358 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x358 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x360 "QOSBW_BE_QOS_BANK[1] [108],QOSBW BE QOS BANK1 Register 108" bitfld.quad 0x360 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x360 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x360 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x360 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x360 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x360 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x368 "QOSBW_BE_QOS_BANK[1] [109],QOSBW BE QOS BANK1 Register 109" bitfld.quad 0x368 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x368 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x368 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x368 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x368 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x368 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x370 "QOSBW_BE_QOS_BANK[1] [110],QOSBW BE QOS BANK1 Register 110" bitfld.quad 0x370 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x370 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x370 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x370 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x370 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x370 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x378 "QOSBW_BE_QOS_BANK[1] [111],QOSBW BE QOS BANK1 Register 111" bitfld.quad 0x378 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x378 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x378 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x378 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x378 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x378 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x380 "QOSBW_BE_QOS_BANK[1] [112],QOSBW BE QOS BANK1 Register 112" bitfld.quad 0x380 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x380 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x380 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x380 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x380 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x380 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x388 "QOSBW_BE_QOS_BANK[1] [113],QOSBW BE QOS BANK1 Register 113" bitfld.quad 0x388 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x388 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x388 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x388 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x388 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x388 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x390 "QOSBW_BE_QOS_BANK[1] [114],QOSBW BE QOS BANK1 Register 114" bitfld.quad 0x390 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x390 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x390 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x390 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x390 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x390 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x398 "QOSBW_BE_QOS_BANK[1] [115],QOSBW BE QOS BANK1 Register 115" bitfld.quad 0x398 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x398 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x398 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x398 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x398 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x398 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3A0 "QOSBW_BE_QOS_BANK[1] [116],QOSBW BE QOS BANK1 Register 116" bitfld.quad 0x3A0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3A0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3A0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3A0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3A0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3A0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3A8 "QOSBW_BE_QOS_BANK[1] [117],QOSBW BE QOS BANK1 Register 117" bitfld.quad 0x3A8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3A8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3A8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3A8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3A8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3A8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3B0 "QOSBW_BE_QOS_BANK[1] [118],QOSBW BE QOS BANK1 Register 118" bitfld.quad 0x3B0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3B0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3B0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3B0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3B0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3B0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3B8 "QOSBW_BE_QOS_BANK[1] [119],QOSBW BE QOS BANK1 Register 119" bitfld.quad 0x3B8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3B8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3B8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3B8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3B8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3B8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3C0 "QOSBW_BE_QOS_BANK[1] [120],QOSBW BE QOS BANK1 Register 120" bitfld.quad 0x3C0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3C0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3C0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3C0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3C0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3C0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3C8 "QOSBW_BE_QOS_BANK[1] [121],QOSBW BE QOS BANK1 Register 121" bitfld.quad 0x3C8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3C8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3C8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3C8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3C8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3C8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3D0 "QOSBW_BE_QOS_BANK[1] [122],QOSBW BE QOS BANK1 Register 122" bitfld.quad 0x3D0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3D0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3D0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3D0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3D0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3D0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3D8 "QOSBW_BE_QOS_BANK[1] [123],QOSBW BE QOS BANK1 Register 123" bitfld.quad 0x3D8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3D8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3D8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3D8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3D8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3D8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3E0 "QOSBW_BE_QOS_BANK[1] [124],QOSBW BE QOS BANK1 Register 124" bitfld.quad 0x3E0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3E0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3E0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3E0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3E0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3E0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3E8 "QOSBW_BE_QOS_BANK[1] [125],QOSBW BE QOS BANK1 Register 125" bitfld.quad 0x3E8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3E8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3E8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3E8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3E8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3E8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3F0 "QOSBW_BE_QOS_BANK[1] [126],QOSBW BE QOS BANK1 Register 126" bitfld.quad 0x3F0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3F0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3F0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3F0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3F0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3F0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x3F8 "QOSBW_BE_QOS_BANK[1] [127],QOSBW BE QOS BANK1 Register 127" bitfld.quad 0x3F8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x3F8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x3F8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x3F8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x3F8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x3F8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x400 "QOSBW_BE_QOS_BANK[1] [128],QOSBW BE QOS BANK1 Register 128" bitfld.quad 0x400 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x400 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x400 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x400 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x400 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x400 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x408 "QOSBW_BE_QOS_BANK[1] [129],QOSBW BE QOS BANK1 Register 129" bitfld.quad 0x408 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x408 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x408 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x408 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x408 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x408 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x410 "QOSBW_BE_QOS_BANK[1] [130],QOSBW BE QOS BANK1 Register 130" bitfld.quad 0x410 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x410 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x410 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x410 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x410 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x410 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x418 "QOSBW_BE_QOS_BANK[1] [131],QOSBW BE QOS BANK1 Register 131" bitfld.quad 0x418 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x418 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x418 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x418 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x418 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x418 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x420 "QOSBW_BE_QOS_BANK[1] [132],QOSBW BE QOS BANK1 Register 132" bitfld.quad 0x420 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x420 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x420 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x420 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x420 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x420 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x428 "QOSBW_BE_QOS_BANK[1] [133],QOSBW BE QOS BANK1 Register 133" bitfld.quad 0x428 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x428 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x428 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x428 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x428 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x428 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x430 "QOSBW_BE_QOS_BANK[1] [134],QOSBW BE QOS BANK1 Register 134" bitfld.quad 0x430 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x430 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x430 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x430 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x430 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x430 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x438 "QOSBW_BE_QOS_BANK[1] [135],QOSBW BE QOS BANK1 Register 135" bitfld.quad 0x438 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x438 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x438 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x438 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x438 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x438 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x440 "QOSBW_BE_QOS_BANK[1] [136],QOSBW BE QOS BANK1 Register 136" bitfld.quad 0x440 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x440 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x440 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x440 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x440 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x440 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x448 "QOSBW_BE_QOS_BANK[1] [137],QOSBW BE QOS BANK1 Register 137" bitfld.quad 0x448 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x448 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x448 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x448 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x448 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x448 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x450 "QOSBW_BE_QOS_BANK[1] [138],QOSBW BE QOS BANK1 Register 138" bitfld.quad 0x450 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x450 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x450 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x450 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x450 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x450 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x458 "QOSBW_BE_QOS_BANK[1] [139],QOSBW BE QOS BANK1 Register 139" bitfld.quad 0x458 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x458 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x458 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x458 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x458 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x458 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x460 "QOSBW_BE_QOS_BANK[1] [140],QOSBW BE QOS BANK1 Register 140" bitfld.quad 0x460 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x460 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x460 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x460 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x460 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x460 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x468 "QOSBW_BE_QOS_BANK[1] [141],QOSBW BE QOS BANK1 Register 141" bitfld.quad 0x468 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x468 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x468 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x468 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x468 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x468 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x470 "QOSBW_BE_QOS_BANK[1] [142],QOSBW BE QOS BANK1 Register 142" bitfld.quad 0x470 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x470 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x470 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x470 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x470 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x470 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x478 "QOSBW_BE_QOS_BANK[1] [143],QOSBW BE QOS BANK1 Register 143" bitfld.quad 0x478 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x478 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x478 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x478 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x478 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x478 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x480 "QOSBW_BE_QOS_BANK[1] [144],QOSBW BE QOS BANK1 Register 144" bitfld.quad 0x480 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x480 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x480 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x480 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x480 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x480 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x488 "QOSBW_BE_QOS_BANK[1] [145],QOSBW BE QOS BANK1 Register 145" bitfld.quad 0x488 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x488 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x488 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x488 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x488 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x488 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x490 "QOSBW_BE_QOS_BANK[1] [146],QOSBW BE QOS BANK1 Register 146" bitfld.quad 0x490 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x490 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x490 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x490 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x490 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x490 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x498 "QOSBW_BE_QOS_BANK[1] [147],QOSBW BE QOS BANK1 Register 147" bitfld.quad 0x498 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x498 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x498 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x498 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x498 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x498 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4A0 "QOSBW_BE_QOS_BANK[1] [148],QOSBW BE QOS BANK1 Register 148" bitfld.quad 0x4A0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4A0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4A0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4A0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4A0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4A0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4A8 "QOSBW_BE_QOS_BANK[1] [149],QOSBW BE QOS BANK1 Register 149" bitfld.quad 0x4A8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4A8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4A8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4A8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4A8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4A8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4B0 "QOSBW_BE_QOS_BANK[1] [150],QOSBW BE QOS BANK1 Register 150" bitfld.quad 0x4B0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4B0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4B0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4B0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4B0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4B0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4B8 "QOSBW_BE_QOS_BANK[1] [151],QOSBW BE QOS BANK1 Register 151" bitfld.quad 0x4B8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4B8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4B8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4B8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4B8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4B8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4C0 "QOSBW_BE_QOS_BANK[1] [152],QOSBW BE QOS BANK1 Register 152" bitfld.quad 0x4C0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4C0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4C0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4C0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4C0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4C0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4C8 "QOSBW_BE_QOS_BANK[1] [153],QOSBW BE QOS BANK1 Register 153" bitfld.quad 0x4C8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4C8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4C8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4C8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4C8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4C8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4D0 "QOSBW_BE_QOS_BANK[1] [154],QOSBW BE QOS BANK1 Register 154" bitfld.quad 0x4D0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4D0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4D0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4D0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4D0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4D0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4D8 "QOSBW_BE_QOS_BANK[1] [155],QOSBW BE QOS BANK1 Register 155" bitfld.quad 0x4D8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4D8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4D8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4D8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4D8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4D8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4E0 "QOSBW_BE_QOS_BANK[1] [156],QOSBW BE QOS BANK1 Register 156" bitfld.quad 0x4E0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4E0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4E0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4E0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4E0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4E0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4E8 "QOSBW_BE_QOS_BANK[1] [157],QOSBW BE QOS BANK1 Register 157" bitfld.quad 0x4E8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4E8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4E8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4E8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4E8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4E8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4F0 "QOSBW_BE_QOS_BANK[1] [158],QOSBW BE QOS BANK1 Register 158" bitfld.quad 0x4F0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4F0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4F0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4F0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4F0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4F0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x4F8 "QOSBW_BE_QOS_BANK[1] [159],QOSBW BE QOS BANK1 Register 159" bitfld.quad 0x4F8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x4F8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x4F8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x4F8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x4F8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x4F8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x500 "QOSBW_BE_QOS_BANK[1] [160],QOSBW BE QOS BANK1 Register 160" bitfld.quad 0x500 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x500 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x500 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x500 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x500 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x500 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x508 "QOSBW_BE_QOS_BANK[1] [161],QOSBW BE QOS BANK1 Register 161" bitfld.quad 0x508 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x508 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x508 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x508 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x508 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x508 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x510 "QOSBW_BE_QOS_BANK[1] [162],QOSBW BE QOS BANK1 Register 162" bitfld.quad 0x510 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x510 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x510 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x510 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x510 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x510 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x518 "QOSBW_BE_QOS_BANK[1] [163],QOSBW BE QOS BANK1 Register 163" bitfld.quad 0x518 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x518 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x518 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x518 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x518 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x518 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x520 "QOSBW_BE_QOS_BANK[1] [164],QOSBW BE QOS BANK1 Register 164" bitfld.quad 0x520 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x520 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x520 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x520 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x520 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x520 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x528 "QOSBW_BE_QOS_BANK[1] [165],QOSBW BE QOS BANK1 Register 165" bitfld.quad 0x528 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x528 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x528 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x528 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x528 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x528 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x530 "QOSBW_BE_QOS_BANK[1] [166],QOSBW BE QOS BANK1 Register 166" bitfld.quad 0x530 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x530 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x530 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x530 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x530 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x530 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x538 "QOSBW_BE_QOS_BANK[1] [167],QOSBW BE QOS BANK1 Register 167" bitfld.quad 0x538 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x538 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x538 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x538 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x538 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x538 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x540 "QOSBW_BE_QOS_BANK[1] [168],QOSBW BE QOS BANK1 Register 168" bitfld.quad 0x540 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x540 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x540 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x540 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x540 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x540 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x548 "QOSBW_BE_QOS_BANK[1] [169],QOSBW BE QOS BANK1 Register 169" bitfld.quad 0x548 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x548 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x548 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x548 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x548 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x548 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x550 "QOSBW_BE_QOS_BANK[1] [170],QOSBW BE QOS BANK1 Register 170" bitfld.quad 0x550 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x550 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x550 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x550 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x550 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x550 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x558 "QOSBW_BE_QOS_BANK[1] [171],QOSBW BE QOS BANK1 Register 171" bitfld.quad 0x558 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x558 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x558 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x558 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x558 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x558 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x560 "QOSBW_BE_QOS_BANK[1] [172],QOSBW BE QOS BANK1 Register 172" bitfld.quad 0x560 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x560 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x560 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x560 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x560 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x560 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x568 "QOSBW_BE_QOS_BANK[1] [173],QOSBW BE QOS BANK1 Register 173" bitfld.quad 0x568 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x568 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x568 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x568 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x568 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x568 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x570 "QOSBW_BE_QOS_BANK[1] [174],QOSBW BE QOS BANK1 Register 174" bitfld.quad 0x570 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x570 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x570 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x570 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x570 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x570 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x578 "QOSBW_BE_QOS_BANK[1] [175],QOSBW BE QOS BANK1 Register 175" bitfld.quad 0x578 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x578 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x578 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x578 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x578 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x578 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x580 "QOSBW_BE_QOS_BANK[1] [176],QOSBW BE QOS BANK1 Register 176" bitfld.quad 0x580 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x580 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x580 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x580 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x580 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x580 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x588 "QOSBW_BE_QOS_BANK[1] [177],QOSBW BE QOS BANK1 Register 177" bitfld.quad 0x588 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x588 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x588 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x588 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x588 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x588 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x590 "QOSBW_BE_QOS_BANK[1] [178],QOSBW BE QOS BANK1 Register 178" bitfld.quad 0x590 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x590 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x590 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x590 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x590 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x590 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x598 "QOSBW_BE_QOS_BANK[1] [179],QOSBW BE QOS BANK1 Register 179" bitfld.quad 0x598 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x598 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x598 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x598 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x598 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x598 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5A0 "QOSBW_BE_QOS_BANK[1] [180],QOSBW BE QOS BANK1 Register 180" bitfld.quad 0x5A0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5A0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5A0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5A0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5A0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5A0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5A8 "QOSBW_BE_QOS_BANK[1] [181],QOSBW BE QOS BANK1 Register 181" bitfld.quad 0x5A8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5A8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5A8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5A8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5A8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5A8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5B0 "QOSBW_BE_QOS_BANK[1] [182],QOSBW BE QOS BANK1 Register 182" bitfld.quad 0x5B0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5B0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5B0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5B0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5B0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5B0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5B8 "QOSBW_BE_QOS_BANK[1] [183],QOSBW BE QOS BANK1 Register 183" bitfld.quad 0x5B8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5B8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5B8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5B8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5B8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5B8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5C0 "QOSBW_BE_QOS_BANK[1] [184],QOSBW BE QOS BANK1 Register 184" bitfld.quad 0x5C0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5C0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5C0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5C0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5C0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5C0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5C8 "QOSBW_BE_QOS_BANK[1] [185],QOSBW BE QOS BANK1 Register 185" bitfld.quad 0x5C8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5C8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5C8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5C8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5C8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5C8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5D0 "QOSBW_BE_QOS_BANK[1] [186],QOSBW BE QOS BANK1 Register 186" bitfld.quad 0x5D0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5D0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5D0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5D0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5D0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5D0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5D8 "QOSBW_BE_QOS_BANK[1] [187],QOSBW BE QOS BANK1 Register 187" bitfld.quad 0x5D8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5D8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5D8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5D8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5D8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5D8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5E0 "QOSBW_BE_QOS_BANK[1] [188],QOSBW BE QOS BANK1 Register 188" bitfld.quad 0x5E0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5E0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5E0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5E0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5E0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5E0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5E8 "QOSBW_BE_QOS_BANK[1] [189],QOSBW BE QOS BANK1 Register 189" bitfld.quad 0x5E8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5E8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5E8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5E8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5E8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5E8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5F0 "QOSBW_BE_QOS_BANK[1] [190],QOSBW BE QOS BANK1 Register 190" bitfld.quad 0x5F0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5F0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5F0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5F0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5F0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5F0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x5F8 "QOSBW_BE_QOS_BANK[1] [191],QOSBW BE QOS BANK1 Register 191" bitfld.quad 0x5F8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x5F8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x5F8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x5F8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x5F8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x5F8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x600 "QOSBW_BE_QOS_BANK[1] [192],QOSBW BE QOS BANK1 Register 192" bitfld.quad 0x600 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x600 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x600 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x600 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x600 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x600 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x608 "QOSBW_BE_QOS_BANK[1] [193],QOSBW BE QOS BANK1 Register 193" bitfld.quad 0x608 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x608 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x608 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x608 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x608 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x608 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x610 "QOSBW_BE_QOS_BANK[1] [194],QOSBW BE QOS BANK1 Register 194" bitfld.quad 0x610 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x610 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x610 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x610 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x610 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x610 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x618 "QOSBW_BE_QOS_BANK[1] [195],QOSBW BE QOS BANK1 Register 195" bitfld.quad 0x618 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x618 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x618 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x618 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x618 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x618 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x620 "QOSBW_BE_QOS_BANK[1] [196],QOSBW BE QOS BANK1 Register 196" bitfld.quad 0x620 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x620 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x620 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x620 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x620 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x620 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x628 "QOSBW_BE_QOS_BANK[1] [197],QOSBW BE QOS BANK1 Register 197" bitfld.quad 0x628 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x628 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x628 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x628 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x628 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x628 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x630 "QOSBW_BE_QOS_BANK[1] [198],QOSBW BE QOS BANK1 Register 198" bitfld.quad 0x630 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x630 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x630 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x630 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x630 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x630 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x638 "QOSBW_BE_QOS_BANK[1] [199],QOSBW BE QOS BANK1 Register 199" bitfld.quad 0x638 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x638 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x638 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x638 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x638 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x638 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x640 "QOSBW_BE_QOS_BANK[1] [200],QOSBW BE QOS BANK1 Register 200" bitfld.quad 0x640 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x640 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x640 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x640 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x640 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x640 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x648 "QOSBW_BE_QOS_BANK[1] [201],QOSBW BE QOS BANK1 Register 201" bitfld.quad 0x648 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x648 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x648 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x648 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x648 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x648 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x650 "QOSBW_BE_QOS_BANK[1] [202],QOSBW BE QOS BANK1 Register 202" bitfld.quad 0x650 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x650 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x650 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x650 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x650 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x650 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x658 "QOSBW_BE_QOS_BANK[1] [203],QOSBW BE QOS BANK1 Register 203" bitfld.quad 0x658 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x658 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x658 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x658 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x658 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x658 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x660 "QOSBW_BE_QOS_BANK[1] [204],QOSBW BE QOS BANK1 Register 204" bitfld.quad 0x660 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x660 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x660 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x660 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x660 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x660 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x668 "QOSBW_BE_QOS_BANK[1] [205],QOSBW BE QOS BANK1 Register 205" bitfld.quad 0x668 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x668 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x668 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x668 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x668 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x668 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x670 "QOSBW_BE_QOS_BANK[1] [206],QOSBW BE QOS BANK1 Register 206" bitfld.quad 0x670 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x670 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x670 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x670 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x670 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x670 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x678 "QOSBW_BE_QOS_BANK[1] [207],QOSBW BE QOS BANK1 Register 207" bitfld.quad 0x678 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x678 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x678 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x678 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x678 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x678 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x680 "QOSBW_BE_QOS_BANK[1] [208],QOSBW BE QOS BANK1 Register 208" bitfld.quad 0x680 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x680 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x680 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x680 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x680 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x680 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x688 "QOSBW_BE_QOS_BANK[1] [209],QOSBW BE QOS BANK1 Register 209" bitfld.quad 0x688 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x688 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x688 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x688 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x688 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x688 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x690 "QOSBW_BE_QOS_BANK[1] [210],QOSBW BE QOS BANK1 Register 210" bitfld.quad 0x690 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x690 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x690 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x690 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x690 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x690 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x698 "QOSBW_BE_QOS_BANK[1] [211],QOSBW BE QOS BANK1 Register 211" bitfld.quad 0x698 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x698 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x698 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x698 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x698 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x698 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6A0 "QOSBW_BE_QOS_BANK[1] [212],QOSBW BE QOS BANK1 Register 212" bitfld.quad 0x6A0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6A0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6A0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6A0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6A0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6A0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6A8 "QOSBW_BE_QOS_BANK[1] [213],QOSBW BE QOS BANK1 Register 213" bitfld.quad 0x6A8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6A8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6A8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6A8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6A8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6A8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6B0 "QOSBW_BE_QOS_BANK[1] [214],QOSBW BE QOS BANK1 Register 214" bitfld.quad 0x6B0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6B0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6B0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6B0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6B0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6B0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6B8 "QOSBW_BE_QOS_BANK[1] [215],QOSBW BE QOS BANK1 Register 215" bitfld.quad 0x6B8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6B8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6B8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6B8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6B8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6B8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6C0 "QOSBW_BE_QOS_BANK[1] [216],QOSBW BE QOS BANK1 Register 216" bitfld.quad 0x6C0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6C0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6C0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6C0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6C0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6C0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6C8 "QOSBW_BE_QOS_BANK[1] [217],QOSBW BE QOS BANK1 Register 217" bitfld.quad 0x6C8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6C8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6C8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6C8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6C8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6C8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6D0 "QOSBW_BE_QOS_BANK[1] [218],QOSBW BE QOS BANK1 Register 218" bitfld.quad 0x6D0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6D0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6D0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6D0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6D0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6D0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6D8 "QOSBW_BE_QOS_BANK[1] [219],QOSBW BE QOS BANK1 Register 219" bitfld.quad 0x6D8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6D8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6D8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6D8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6D8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6D8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6E0 "QOSBW_BE_QOS_BANK[1] [220],QOSBW BE QOS BANK1 Register 220" bitfld.quad 0x6E0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6E0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6E0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6E0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6E0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6E0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6E8 "QOSBW_BE_QOS_BANK[1] [221],QOSBW BE QOS BANK1 Register 221" bitfld.quad 0x6E8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6E8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6E8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6E8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6E8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6E8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6F0 "QOSBW_BE_QOS_BANK[1] [222],QOSBW BE QOS BANK1 Register 222" bitfld.quad 0x6F0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6F0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6F0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6F0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6F0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6F0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x6F8 "QOSBW_BE_QOS_BANK[1] [223],QOSBW BE QOS BANK1 Register 223" bitfld.quad 0x6F8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x6F8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x6F8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x6F8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x6F8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x6F8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x700 "QOSBW_BE_QOS_BANK[1] [224],QOSBW BE QOS BANK1 Register 224" bitfld.quad 0x700 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x700 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x700 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x700 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x700 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x700 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x708 "QOSBW_BE_QOS_BANK[1] [225],QOSBW BE QOS BANK1 Register 225" bitfld.quad 0x708 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x708 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x708 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x708 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x708 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x708 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x710 "QOSBW_BE_QOS_BANK[1] [226],QOSBW BE QOS BANK1 Register 226" bitfld.quad 0x710 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x710 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x710 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x710 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x710 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x710 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x718 "QOSBW_BE_QOS_BANK[1] [227],QOSBW BE QOS BANK1 Register 227" bitfld.quad 0x718 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x718 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x718 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x718 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x718 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x718 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x720 "QOSBW_BE_QOS_BANK[1] [228],QOSBW BE QOS BANK1 Register 228" bitfld.quad 0x720 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x720 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x720 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x720 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x720 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x720 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x728 "QOSBW_BE_QOS_BANK[1] [229],QOSBW BE QOS BANK1 Register 229" bitfld.quad 0x728 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x728 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x728 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x728 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x728 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x728 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x730 "QOSBW_BE_QOS_BANK[1] [230],QOSBW BE QOS BANK1 Register 230" bitfld.quad 0x730 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x730 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x730 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x730 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x730 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x730 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x738 "QOSBW_BE_QOS_BANK[1] [231],QOSBW BE QOS BANK1 Register 231" bitfld.quad 0x738 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x738 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x738 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x738 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x738 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x738 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x740 "QOSBW_BE_QOS_BANK[1] [232],QOSBW BE QOS BANK1 Register 232" bitfld.quad 0x740 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x740 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x740 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x740 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x740 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x740 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x748 "QOSBW_BE_QOS_BANK[1] [233],QOSBW BE QOS BANK1 Register 233" bitfld.quad 0x748 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x748 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x748 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x748 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x748 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x748 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x750 "QOSBW_BE_QOS_BANK[1] [234],QOSBW BE QOS BANK1 Register 234" bitfld.quad 0x750 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x750 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x750 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x750 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x750 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x750 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x758 "QOSBW_BE_QOS_BANK[1] [235],QOSBW BE QOS BANK1 Register 235" bitfld.quad 0x758 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x758 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x758 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x758 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x758 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x758 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x760 "QOSBW_BE_QOS_BANK[1] [236],QOSBW BE QOS BANK1 Register 236" bitfld.quad 0x760 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x760 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x760 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x760 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x760 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x760 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x768 "QOSBW_BE_QOS_BANK[1] [237],QOSBW BE QOS BANK1 Register 237" bitfld.quad 0x768 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x768 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x768 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x768 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x768 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x768 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x770 "QOSBW_BE_QOS_BANK[1] [238],QOSBW BE QOS BANK1 Register 238" bitfld.quad 0x770 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x770 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x770 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x770 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x770 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x770 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x778 "QOSBW_BE_QOS_BANK[1] [239],QOSBW BE QOS BANK1 Register 239" bitfld.quad 0x778 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x778 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x778 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x778 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x778 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x778 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x780 "QOSBW_BE_QOS_BANK[1] [240],QOSBW BE QOS BANK1 Register 240" bitfld.quad 0x780 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x780 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x780 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x780 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x780 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x780 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x788 "QOSBW_BE_QOS_BANK[1] [241],QOSBW BE QOS BANK1 Register 241" bitfld.quad 0x788 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x788 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x788 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x788 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x788 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x788 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x790 "QOSBW_BE_QOS_BANK[1] [242],QOSBW BE QOS BANK1 Register 242" bitfld.quad 0x790 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x790 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x790 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x790 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x790 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x790 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x798 "QOSBW_BE_QOS_BANK[1] [243],QOSBW BE QOS BANK1 Register 243" bitfld.quad 0x798 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x798 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x798 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x798 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x798 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x798 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7A0 "QOSBW_BE_QOS_BANK[1] [244],QOSBW BE QOS BANK1 Register 244" bitfld.quad 0x7A0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7A0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7A0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7A0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7A0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7A0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7A8 "QOSBW_BE_QOS_BANK[1] [245],QOSBW BE QOS BANK1 Register 245" bitfld.quad 0x7A8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7A8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7A8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7A8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7A8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7A8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7B0 "QOSBW_BE_QOS_BANK[1] [246],QOSBW BE QOS BANK1 Register 246" bitfld.quad 0x7B0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7B0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7B0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7B0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7B0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7B0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7B8 "QOSBW_BE_QOS_BANK[1] [247],QOSBW BE QOS BANK1 Register 247" bitfld.quad 0x7B8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7B8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7B8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7B8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7B8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7B8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7C0 "QOSBW_BE_QOS_BANK[1] [248],QOSBW BE QOS BANK1 Register 248" bitfld.quad 0x7C0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7C0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7C0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7C0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7C0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7C0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7C8 "QOSBW_BE_QOS_BANK[1] [249],QOSBW BE QOS BANK1 Register 249" bitfld.quad 0x7C8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7C8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7C8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7C8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7C8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7C8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7D0 "QOSBW_BE_QOS_BANK[1] [250],QOSBW BE QOS BANK1 Register 250" bitfld.quad 0x7D0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7D0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7D0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7D0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7D0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7D0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7D8 "QOSBW_BE_QOS_BANK[1] [251],QOSBW BE QOS BANK1 Register 251" bitfld.quad 0x7D8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7D8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7D8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7D8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7D8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7D8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7E0 "QOSBW_BE_QOS_BANK[1] [252],QOSBW BE QOS BANK1 Register 252" bitfld.quad 0x7E0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7E0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7E0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7E0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7E0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7E0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7E8 "QOSBW_BE_QOS_BANK[1] [253],QOSBW BE QOS BANK1 Register 253" bitfld.quad 0x7E8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7E8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7E8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7E8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7E8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7E8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7F0 "QOSBW_BE_QOS_BANK[1] [254],QOSBW BE QOS BANK1 Register 254" bitfld.quad 0x7F0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7F0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7F0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7F0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7F0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7F0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x7F8 "QOSBW_BE_QOS_BANK[1] [255],QOSBW BE QOS BANK1 Register 255" bitfld.quad 0x7F8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x7F8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x7F8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x7F8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x7F8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x7F8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x800 "QOSBW_BE_QOS_BANK[1] [256],QOSBW BE QOS BANK1 Register 256" bitfld.quad 0x800 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x800 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x800 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x800 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x800 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x800 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x808 "QOSBW_BE_QOS_BANK[1] [257],QOSBW BE QOS BANK1 Register 257" bitfld.quad 0x808 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x808 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x808 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x808 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x808 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x808 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x810 "QOSBW_BE_QOS_BANK[1] [258],QOSBW BE QOS BANK1 Register 258" bitfld.quad 0x810 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x810 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x810 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x810 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x810 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x810 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x818 "QOSBW_BE_QOS_BANK[1] [259],QOSBW BE QOS BANK1 Register 259" bitfld.quad 0x818 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x818 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x818 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x818 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x818 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x818 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x820 "QOSBW_BE_QOS_BANK[1] [260],QOSBW BE QOS BANK1 Register 260" bitfld.quad 0x820 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x820 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x820 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x820 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x820 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x820 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x828 "QOSBW_BE_QOS_BANK[1] [261],QOSBW BE QOS BANK1 Register 261" bitfld.quad 0x828 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x828 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x828 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x828 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x828 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x828 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x830 "QOSBW_BE_QOS_BANK[1] [262],QOSBW BE QOS BANK1 Register 262" bitfld.quad 0x830 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x830 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x830 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x830 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x830 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x830 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x838 "QOSBW_BE_QOS_BANK[1] [263],QOSBW BE QOS BANK1 Register 263" bitfld.quad 0x838 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x838 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x838 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x838 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x838 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x838 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x840 "QOSBW_BE_QOS_BANK[1] [264],QOSBW BE QOS BANK1 Register 264" bitfld.quad 0x840 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x840 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x840 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x840 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x840 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x840 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x848 "QOSBW_BE_QOS_BANK[1] [265],QOSBW BE QOS BANK1 Register 265" bitfld.quad 0x848 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x848 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x848 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x848 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x848 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x848 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x850 "QOSBW_BE_QOS_BANK[1] [266],QOSBW BE QOS BANK1 Register 266" bitfld.quad 0x850 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x850 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x850 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x850 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x850 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x850 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x858 "QOSBW_BE_QOS_BANK[1] [267],QOSBW BE QOS BANK1 Register 267" bitfld.quad 0x858 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x858 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x858 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x858 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x858 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x858 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x860 "QOSBW_BE_QOS_BANK[1] [268],QOSBW BE QOS BANK1 Register 268" bitfld.quad 0x860 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x860 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x860 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x860 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x860 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x860 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x868 "QOSBW_BE_QOS_BANK[1] [269],QOSBW BE QOS BANK1 Register 269" bitfld.quad 0x868 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x868 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x868 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x868 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x868 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x868 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x870 "QOSBW_BE_QOS_BANK[1] [270],QOSBW BE QOS BANK1 Register 270" bitfld.quad 0x870 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x870 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x870 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x870 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x870 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x870 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x878 "QOSBW_BE_QOS_BANK[1] [271],QOSBW BE QOS BANK1 Register 271" bitfld.quad 0x878 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x878 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x878 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x878 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x878 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x878 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x880 "QOSBW_BE_QOS_BANK[1] [272],QOSBW BE QOS BANK1 Register 272" bitfld.quad 0x880 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x880 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x880 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x880 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x880 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x880 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x888 "QOSBW_BE_QOS_BANK[1] [273],QOSBW BE QOS BANK1 Register 273" bitfld.quad 0x888 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x888 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x888 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x888 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x888 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x888 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x890 "QOSBW_BE_QOS_BANK[1] [274],QOSBW BE QOS BANK1 Register 274" bitfld.quad 0x890 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x890 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x890 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x890 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x890 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x890 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x898 "QOSBW_BE_QOS_BANK[1] [275],QOSBW BE QOS BANK1 Register 275" bitfld.quad 0x898 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x898 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x898 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x898 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x898 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x898 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8A0 "QOSBW_BE_QOS_BANK[1] [276],QOSBW BE QOS BANK1 Register 276" bitfld.quad 0x8A0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8A0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8A0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8A0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8A0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8A0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8A8 "QOSBW_BE_QOS_BANK[1] [277],QOSBW BE QOS BANK1 Register 277" bitfld.quad 0x8A8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8A8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8A8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8A8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8A8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8A8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8B0 "QOSBW_BE_QOS_BANK[1] [278],QOSBW BE QOS BANK1 Register 278" bitfld.quad 0x8B0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8B0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8B0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8B0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8B0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8B0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8B8 "QOSBW_BE_QOS_BANK[1] [279],QOSBW BE QOS BANK1 Register 279" bitfld.quad 0x8B8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8B8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8B8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8B8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8B8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8B8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8C0 "QOSBW_BE_QOS_BANK[1] [280],QOSBW BE QOS BANK1 Register 280" bitfld.quad 0x8C0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8C0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8C0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8C0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8C0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8C0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8C8 "QOSBW_BE_QOS_BANK[1] [281],QOSBW BE QOS BANK1 Register 281" bitfld.quad 0x8C8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8C8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8C8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8C8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8C8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8C8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8D0 "QOSBW_BE_QOS_BANK[1] [282],QOSBW BE QOS BANK1 Register 282" bitfld.quad 0x8D0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8D0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8D0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8D0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8D0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8D0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8D8 "QOSBW_BE_QOS_BANK[1] [283],QOSBW BE QOS BANK1 Register 283" bitfld.quad 0x8D8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8D8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8D8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8D8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8D8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8D8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8E0 "QOSBW_BE_QOS_BANK[1] [284],QOSBW BE QOS BANK1 Register 284" bitfld.quad 0x8E0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8E0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8E0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8E0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8E0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8E0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8E8 "QOSBW_BE_QOS_BANK[1] [285],QOSBW BE QOS BANK1 Register 285" bitfld.quad 0x8E8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8E8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8E8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8E8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8E8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8E8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8F0 "QOSBW_BE_QOS_BANK[1] [286],QOSBW BE QOS BANK1 Register 286" bitfld.quad 0x8F0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8F0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8F0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8F0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8F0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8F0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x8F8 "QOSBW_BE_QOS_BANK[1] [287],QOSBW BE QOS BANK1 Register 287" bitfld.quad 0x8F8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x8F8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x8F8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x8F8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x8F8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x8F8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x900 "QOSBW_BE_QOS_BANK[1] [288],QOSBW BE QOS BANK1 Register 288" bitfld.quad 0x900 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x900 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x900 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x900 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x900 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x900 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x908 "QOSBW_BE_QOS_BANK[1] [289],QOSBW BE QOS BANK1 Register 289" bitfld.quad 0x908 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x908 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x908 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x908 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x908 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x908 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x910 "QOSBW_BE_QOS_BANK[1] [290],QOSBW BE QOS BANK1 Register 290" bitfld.quad 0x910 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x910 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x910 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x910 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x910 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x910 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x918 "QOSBW_BE_QOS_BANK[1] [291],QOSBW BE QOS BANK1 Register 291" bitfld.quad 0x918 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x918 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x918 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x918 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x918 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x918 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x920 "QOSBW_BE_QOS_BANK[1] [292],QOSBW BE QOS BANK1 Register 292" bitfld.quad 0x920 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x920 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x920 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x920 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x920 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x920 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x928 "QOSBW_BE_QOS_BANK[1] [293],QOSBW BE QOS BANK1 Register 293" bitfld.quad 0x928 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x928 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x928 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x928 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x928 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x928 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x930 "QOSBW_BE_QOS_BANK[1] [294],QOSBW BE QOS BANK1 Register 294" bitfld.quad 0x930 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x930 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x930 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x930 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x930 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x930 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x938 "QOSBW_BE_QOS_BANK[1] [295],QOSBW BE QOS BANK1 Register 295" bitfld.quad 0x938 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x938 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x938 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x938 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x938 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x938 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x940 "QOSBW_BE_QOS_BANK[1] [296],QOSBW BE QOS BANK1 Register 296" bitfld.quad 0x940 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x940 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x940 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x940 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x940 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x940 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x948 "QOSBW_BE_QOS_BANK[1] [297],QOSBW BE QOS BANK1 Register 297" bitfld.quad 0x948 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x948 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x948 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x948 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x948 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x948 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x950 "QOSBW_BE_QOS_BANK[1] [298],QOSBW BE QOS BANK1 Register 298" bitfld.quad 0x950 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x950 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x950 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x950 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x950 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x950 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x958 "QOSBW_BE_QOS_BANK[1] [299],QOSBW BE QOS BANK1 Register 299" bitfld.quad 0x958 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x958 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x958 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x958 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x958 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x958 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x960 "QOSBW_BE_QOS_BANK[1] [300],QOSBW BE QOS BANK1 Register 300" bitfld.quad 0x960 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x960 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x960 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x960 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x960 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x960 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x968 "QOSBW_BE_QOS_BANK[1] [301],QOSBW BE QOS BANK1 Register 301" bitfld.quad 0x968 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x968 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x968 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x968 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x968 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x968 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x970 "QOSBW_BE_QOS_BANK[1] [302],QOSBW BE QOS BANK1 Register 302" bitfld.quad 0x970 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x970 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x970 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x970 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x970 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x970 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x978 "QOSBW_BE_QOS_BANK[1] [303],QOSBW BE QOS BANK1 Register 303" bitfld.quad 0x978 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x978 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x978 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x978 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x978 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x978 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x980 "QOSBW_BE_QOS_BANK[1] [304],QOSBW BE QOS BANK1 Register 304" bitfld.quad 0x980 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x980 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x980 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x980 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x980 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x980 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x988 "QOSBW_BE_QOS_BANK[1] [305],QOSBW BE QOS BANK1 Register 305" bitfld.quad 0x988 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x988 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x988 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x988 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x988 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x988 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x990 "QOSBW_BE_QOS_BANK[1] [306],QOSBW BE QOS BANK1 Register 306" bitfld.quad 0x990 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x990 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x990 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x990 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x990 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x990 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x998 "QOSBW_BE_QOS_BANK[1] [307],QOSBW BE QOS BANK1 Register 307" bitfld.quad 0x998 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x998 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x998 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x998 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x998 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x998 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9A0 "QOSBW_BE_QOS_BANK[1] [308],QOSBW BE QOS BANK1 Register 308" bitfld.quad 0x9A0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9A0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9A0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9A0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9A0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9A0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9A8 "QOSBW_BE_QOS_BANK[1] [309],QOSBW BE QOS BANK1 Register 309" bitfld.quad 0x9A8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9A8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9A8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9A8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9A8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9A8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9B0 "QOSBW_BE_QOS_BANK[1] [310],QOSBW BE QOS BANK1 Register 310" bitfld.quad 0x9B0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9B0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9B0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9B0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9B0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9B0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9B8 "QOSBW_BE_QOS_BANK[1] [311],QOSBW BE QOS BANK1 Register 311" bitfld.quad 0x9B8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9B8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9B8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9B8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9B8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9B8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9C0 "QOSBW_BE_QOS_BANK[1] [312],QOSBW BE QOS BANK1 Register 312" bitfld.quad 0x9C0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9C0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9C0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9C0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9C0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9C0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9C8 "QOSBW_BE_QOS_BANK[1] [313],QOSBW BE QOS BANK1 Register 313" bitfld.quad 0x9C8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9C8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9C8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9C8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9C8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9C8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9D0 "QOSBW_BE_QOS_BANK[1] [314],QOSBW BE QOS BANK1 Register 314" bitfld.quad 0x9D0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9D0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9D0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9D0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9D0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9D0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9D8 "QOSBW_BE_QOS_BANK[1] [315],QOSBW BE QOS BANK1 Register 315" bitfld.quad 0x9D8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9D8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9D8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9D8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9D8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9D8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9E0 "QOSBW_BE_QOS_BANK[1] [316],QOSBW BE QOS BANK1 Register 316" bitfld.quad 0x9E0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9E0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9E0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9E0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9E0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9E0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9E8 "QOSBW_BE_QOS_BANK[1] [317],QOSBW BE QOS BANK1 Register 317" bitfld.quad 0x9E8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9E8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9E8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9E8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9E8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9E8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9F0 "QOSBW_BE_QOS_BANK[1] [318],QOSBW BE QOS BANK1 Register 318" bitfld.quad 0x9F0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9F0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9F0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9F0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9F0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9F0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0x9F8 "QOSBW_BE_QOS_BANK[1] [319],QOSBW BE QOS BANK1 Register 319" bitfld.quad 0x9F8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0x9F8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0x9F8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0x9F8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0x9F8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0x9F8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA00 "QOSBW_BE_QOS_BANK[1] [320],QOSBW BE QOS BANK1 Register 320" bitfld.quad 0xA00 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA00 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA00 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA00 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA00 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA00 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA08 "QOSBW_BE_QOS_BANK[1] [321],QOSBW BE QOS BANK1 Register 321" bitfld.quad 0xA08 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA08 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA08 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA08 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA08 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA08 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA10 "QOSBW_BE_QOS_BANK[1] [322],QOSBW BE QOS BANK1 Register 322" bitfld.quad 0xA10 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA10 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA10 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA10 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA10 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA10 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA18 "QOSBW_BE_QOS_BANK[1] [323],QOSBW BE QOS BANK1 Register 323" bitfld.quad 0xA18 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA18 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA18 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA18 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA18 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA18 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA20 "QOSBW_BE_QOS_BANK[1] [324],QOSBW BE QOS BANK1 Register 324" bitfld.quad 0xA20 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA20 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA20 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA20 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA20 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA20 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA28 "QOSBW_BE_QOS_BANK[1] [325],QOSBW BE QOS BANK1 Register 325" bitfld.quad 0xA28 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA28 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA28 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA28 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA28 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA28 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA30 "QOSBW_BE_QOS_BANK[1] [326],QOSBW BE QOS BANK1 Register 326" bitfld.quad 0xA30 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA30 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA30 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA30 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA30 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA30 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA38 "QOSBW_BE_QOS_BANK[1] [327],QOSBW BE QOS BANK1 Register 327" bitfld.quad 0xA38 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA38 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA38 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA38 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA38 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA38 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA40 "QOSBW_BE_QOS_BANK[1] [328],QOSBW BE QOS BANK1 Register 328" bitfld.quad 0xA40 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA40 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA40 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA40 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA40 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA40 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA48 "QOSBW_BE_QOS_BANK[1] [329],QOSBW BE QOS BANK1 Register 329" bitfld.quad 0xA48 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA48 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA48 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA48 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA48 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA48 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA50 "QOSBW_BE_QOS_BANK[1] [330],QOSBW BE QOS BANK1 Register 330" bitfld.quad 0xA50 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA50 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA50 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA50 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA50 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA50 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA58 "QOSBW_BE_QOS_BANK[1] [331],QOSBW BE QOS BANK1 Register 331" bitfld.quad 0xA58 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA58 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA58 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA58 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA58 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA58 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA60 "QOSBW_BE_QOS_BANK[1] [332],QOSBW BE QOS BANK1 Register 332" bitfld.quad 0xA60 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA60 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA60 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA60 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA60 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA60 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA68 "QOSBW_BE_QOS_BANK[1] [333],QOSBW BE QOS BANK1 Register 333" bitfld.quad 0xA68 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA68 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA68 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA68 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA68 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA68 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA70 "QOSBW_BE_QOS_BANK[1] [334],QOSBW BE QOS BANK1 Register 334" bitfld.quad 0xA70 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA70 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA70 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA70 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA70 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA70 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA78 "QOSBW_BE_QOS_BANK[1] [335],QOSBW BE QOS BANK1 Register 335" bitfld.quad 0xA78 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA78 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA78 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA78 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA78 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA78 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA80 "QOSBW_BE_QOS_BANK[1] [336],QOSBW BE QOS BANK1 Register 336" bitfld.quad 0xA80 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA80 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA80 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA80 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA80 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA80 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA88 "QOSBW_BE_QOS_BANK[1] [337],QOSBW BE QOS BANK1 Register 337" bitfld.quad 0xA88 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA88 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA88 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA88 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA88 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA88 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA90 "QOSBW_BE_QOS_BANK[1] [338],QOSBW BE QOS BANK1 Register 338" bitfld.quad 0xA90 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA90 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA90 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA90 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA90 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA90 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xA98 "QOSBW_BE_QOS_BANK[1] [339],QOSBW BE QOS BANK1 Register 339" bitfld.quad 0xA98 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xA98 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xA98 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xA98 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xA98 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xA98 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAA0 "QOSBW_BE_QOS_BANK[1] [340],QOSBW BE QOS BANK1 Register 340" bitfld.quad 0xAA0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAA0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAA0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAA0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAA0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAA0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAA8 "QOSBW_BE_QOS_BANK[1] [341],QOSBW BE QOS BANK1 Register 341" bitfld.quad 0xAA8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAA8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAA8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAA8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAA8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAA8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAB0 "QOSBW_BE_QOS_BANK[1] [342],QOSBW BE QOS BANK1 Register 342" bitfld.quad 0xAB0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAB0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAB0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAB0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAB0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAB0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAB8 "QOSBW_BE_QOS_BANK[1] [343],QOSBW BE QOS BANK1 Register 343" bitfld.quad 0xAB8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAB8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAB8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAB8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAB8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAB8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAC0 "QOSBW_BE_QOS_BANK[1] [344],QOSBW BE QOS BANK1 Register 344" bitfld.quad 0xAC0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAC0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAC0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAC0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAC0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAC0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAC8 "QOSBW_BE_QOS_BANK[1] [345],QOSBW BE QOS BANK1 Register 345" bitfld.quad 0xAC8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAC8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAC8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAC8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAC8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAC8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAD0 "QOSBW_BE_QOS_BANK[1] [346],QOSBW BE QOS BANK1 Register 346" bitfld.quad 0xAD0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAD0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAD0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAD0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAD0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAD0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAD8 "QOSBW_BE_QOS_BANK[1] [347],QOSBW BE QOS BANK1 Register 347" bitfld.quad 0xAD8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAD8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAD8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAD8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAD8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAD8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAE0 "QOSBW_BE_QOS_BANK[1] [348],QOSBW BE QOS BANK1 Register 348" bitfld.quad 0xAE0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAE0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAE0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAE0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAE0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAE0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAE8 "QOSBW_BE_QOS_BANK[1] [349],QOSBW BE QOS BANK1 Register 349" bitfld.quad 0xAE8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAE8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAE8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAE8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAE8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAE8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAF0 "QOSBW_BE_QOS_BANK[1] [350],QOSBW BE QOS BANK1 Register 350" bitfld.quad 0xAF0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAF0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAF0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAF0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAF0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAF0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xAF8 "QOSBW_BE_QOS_BANK[1] [351],QOSBW BE QOS BANK1 Register 351" bitfld.quad 0xAF8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xAF8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xAF8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xAF8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xAF8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xAF8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB00 "QOSBW_BE_QOS_BANK[1] [352],QOSBW BE QOS BANK1 Register 352" bitfld.quad 0xB00 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB00 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB00 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB00 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB00 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB00 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB08 "QOSBW_BE_QOS_BANK[1] [353],QOSBW BE QOS BANK1 Register 353" bitfld.quad 0xB08 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB08 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB08 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB08 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB08 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB08 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB10 "QOSBW_BE_QOS_BANK[1] [354],QOSBW BE QOS BANK1 Register 354" bitfld.quad 0xB10 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB10 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB10 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB10 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB10 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB10 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB18 "QOSBW_BE_QOS_BANK[1] [355],QOSBW BE QOS BANK1 Register 355" bitfld.quad 0xB18 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB18 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB18 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB18 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB18 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB18 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB20 "QOSBW_BE_QOS_BANK[1] [356],QOSBW BE QOS BANK1 Register 356" bitfld.quad 0xB20 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB20 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB20 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB20 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB20 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB20 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB28 "QOSBW_BE_QOS_BANK[1] [357],QOSBW BE QOS BANK1 Register 357" bitfld.quad 0xB28 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB28 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB28 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB28 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB28 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB28 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB30 "QOSBW_BE_QOS_BANK[1] [358],QOSBW BE QOS BANK1 Register 358" bitfld.quad 0xB30 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB30 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB30 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB30 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB30 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB30 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB38 "QOSBW_BE_QOS_BANK[1] [359],QOSBW BE QOS BANK1 Register 359" bitfld.quad 0xB38 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB38 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB38 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB38 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB38 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB38 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB40 "QOSBW_BE_QOS_BANK[1] [360],QOSBW BE QOS BANK1 Register 360" bitfld.quad 0xB40 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB40 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB40 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB40 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB40 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB40 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB48 "QOSBW_BE_QOS_BANK[1] [361],QOSBW BE QOS BANK1 Register 361" bitfld.quad 0xB48 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB48 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB48 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB48 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB48 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB48 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB50 "QOSBW_BE_QOS_BANK[1] [362],QOSBW BE QOS BANK1 Register 362" bitfld.quad 0xB50 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB50 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB50 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB50 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB50 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB50 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB58 "QOSBW_BE_QOS_BANK[1] [363],QOSBW BE QOS BANK1 Register 363" bitfld.quad 0xB58 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB58 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB58 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB58 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB58 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB58 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB60 "QOSBW_BE_QOS_BANK[1] [364],QOSBW BE QOS BANK1 Register 364" bitfld.quad 0xB60 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB60 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB60 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB60 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB60 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB60 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB68 "QOSBW_BE_QOS_BANK[1] [365],QOSBW BE QOS BANK1 Register 365" bitfld.quad 0xB68 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB68 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB68 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB68 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB68 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB68 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB70 "QOSBW_BE_QOS_BANK[1] [366],QOSBW BE QOS BANK1 Register 366" bitfld.quad 0xB70 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB70 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB70 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB70 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB70 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB70 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB78 "QOSBW_BE_QOS_BANK[1] [367],QOSBW BE QOS BANK1 Register 367" bitfld.quad 0xB78 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB78 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB78 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB78 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB78 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB78 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB80 "QOSBW_BE_QOS_BANK[1] [368],QOSBW BE QOS BANK1 Register 368" bitfld.quad 0xB80 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB80 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB80 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB80 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB80 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB80 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB88 "QOSBW_BE_QOS_BANK[1] [369],QOSBW BE QOS BANK1 Register 369" bitfld.quad 0xB88 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB88 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB88 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB88 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB88 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB88 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB90 "QOSBW_BE_QOS_BANK[1] [370],QOSBW BE QOS BANK1 Register 370" bitfld.quad 0xB90 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB90 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB90 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB90 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB90 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB90 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xB98 "QOSBW_BE_QOS_BANK[1] [371],QOSBW BE QOS BANK1 Register 371" bitfld.quad 0xB98 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xB98 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xB98 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xB98 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xB98 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xB98 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBA0 "QOSBW_BE_QOS_BANK[1] [372],QOSBW BE QOS BANK1 Register 372" bitfld.quad 0xBA0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBA0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBA0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBA0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBA0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBA0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBA8 "QOSBW_BE_QOS_BANK[1] [373],QOSBW BE QOS BANK1 Register 373" bitfld.quad 0xBA8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBA8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBA8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBA8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBA8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBA8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBB0 "QOSBW_BE_QOS_BANK[1] [374],QOSBW BE QOS BANK1 Register 374" bitfld.quad 0xBB0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBB0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBB0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBB0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBB0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBB0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBB8 "QOSBW_BE_QOS_BANK[1] [375],QOSBW BE QOS BANK1 Register 375" bitfld.quad 0xBB8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBB8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBB8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBB8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBB8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBB8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBC0 "QOSBW_BE_QOS_BANK[1] [376],QOSBW BE QOS BANK1 Register 376" bitfld.quad 0xBC0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBC0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBC0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBC0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBC0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBC0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBC8 "QOSBW_BE_QOS_BANK[1] [377],QOSBW BE QOS BANK1 Register 377" bitfld.quad 0xBC8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBC8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBC8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBC8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBC8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBC8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBD0 "QOSBW_BE_QOS_BANK[1] [378],QOSBW BE QOS BANK1 Register 378" bitfld.quad 0xBD0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBD0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBD0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBD0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBD0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBD0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBD8 "QOSBW_BE_QOS_BANK[1] [379],QOSBW BE QOS BANK1 Register 379" bitfld.quad 0xBD8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBD8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBD8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBD8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBD8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBD8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBE0 "QOSBW_BE_QOS_BANK[1] [380],QOSBW BE QOS BANK1 Register 380" bitfld.quad 0xBE0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBE0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBE0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBE0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBE0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBE0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBE8 "QOSBW_BE_QOS_BANK[1] [381],QOSBW BE QOS BANK1 Register 381" bitfld.quad 0xBE8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBE8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBE8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBE8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBE8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBE8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBF0 "QOSBW_BE_QOS_BANK[1] [382],QOSBW BE QOS BANK1 Register 382" bitfld.quad 0xBF0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBF0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBF0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBF0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBF0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBF0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xBF8 "QOSBW_BE_QOS_BANK[1] [383],QOSBW BE QOS BANK1 Register 383" bitfld.quad 0xBF8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xBF8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xBF8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xBF8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xBF8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xBF8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC00 "QOSBW_BE_QOS_BANK[1] [384],QOSBW BE QOS BANK1 Register 384" bitfld.quad 0xC00 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC00 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC00 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC00 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC00 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC00 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC08 "QOSBW_BE_QOS_BANK[1] [385],QOSBW BE QOS BANK1 Register 385" bitfld.quad 0xC08 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC08 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC08 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC08 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC08 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC08 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC10 "QOSBW_BE_QOS_BANK[1] [386],QOSBW BE QOS BANK1 Register 386" bitfld.quad 0xC10 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC10 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC10 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC10 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC10 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC10 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC18 "QOSBW_BE_QOS_BANK[1] [387],QOSBW BE QOS BANK1 Register 387" bitfld.quad 0xC18 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC18 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC18 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC18 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC18 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC18 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC20 "QOSBW_BE_QOS_BANK[1] [388],QOSBW BE QOS BANK1 Register 388" bitfld.quad 0xC20 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC20 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC20 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC20 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC20 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC20 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC28 "QOSBW_BE_QOS_BANK[1] [389],QOSBW BE QOS BANK1 Register 389" bitfld.quad 0xC28 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC28 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC28 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC28 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC28 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC28 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC30 "QOSBW_BE_QOS_BANK[1] [390],QOSBW BE QOS BANK1 Register 390" bitfld.quad 0xC30 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC30 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC30 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC30 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC30 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC30 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC38 "QOSBW_BE_QOS_BANK[1] [391],QOSBW BE QOS BANK1 Register 391" bitfld.quad 0xC38 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC38 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC38 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC38 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC38 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC38 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC40 "QOSBW_BE_QOS_BANK[1] [392],QOSBW BE QOS BANK1 Register 392" bitfld.quad 0xC40 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC40 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC40 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC40 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC40 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC40 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC48 "QOSBW_BE_QOS_BANK[1] [393],QOSBW BE QOS BANK1 Register 393" bitfld.quad 0xC48 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC48 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC48 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC48 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC48 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC48 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC50 "QOSBW_BE_QOS_BANK[1] [394],QOSBW BE QOS BANK1 Register 394" bitfld.quad 0xC50 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC50 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC50 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC50 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC50 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC50 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC58 "QOSBW_BE_QOS_BANK[1] [395],QOSBW BE QOS BANK1 Register 395" bitfld.quad 0xC58 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC58 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC58 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC58 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC58 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC58 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC60 "QOSBW_BE_QOS_BANK[1] [396],QOSBW BE QOS BANK1 Register 396" bitfld.quad 0xC60 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC60 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC60 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC60 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC60 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC60 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC68 "QOSBW_BE_QOS_BANK[1] [397],QOSBW BE QOS BANK1 Register 397" bitfld.quad 0xC68 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC68 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC68 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC68 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC68 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC68 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC70 "QOSBW_BE_QOS_BANK[1] [398],QOSBW BE QOS BANK1 Register 398" bitfld.quad 0xC70 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC70 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC70 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC70 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC70 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC70 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC78 "QOSBW_BE_QOS_BANK[1] [399],QOSBW BE QOS BANK1 Register 399" bitfld.quad 0xC78 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC78 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC78 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC78 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC78 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC78 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC80 "QOSBW_BE_QOS_BANK[1] [400],QOSBW BE QOS BANK1 Register 400" bitfld.quad 0xC80 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC80 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC80 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC80 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC80 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC80 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC88 "QOSBW_BE_QOS_BANK[1] [401],QOSBW BE QOS BANK1 Register 401" bitfld.quad 0xC88 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC88 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC88 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC88 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC88 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC88 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC90 "QOSBW_BE_QOS_BANK[1] [402],QOSBW BE QOS BANK1 Register 402" bitfld.quad 0xC90 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC90 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC90 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC90 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC90 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC90 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xC98 "QOSBW_BE_QOS_BANK[1] [403],QOSBW BE QOS BANK1 Register 403" bitfld.quad 0xC98 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xC98 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xC98 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xC98 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xC98 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xC98 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCA0 "QOSBW_BE_QOS_BANK[1] [404],QOSBW BE QOS BANK1 Register 404" bitfld.quad 0xCA0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCA0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCA0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCA0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCA0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCA0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCA8 "QOSBW_BE_QOS_BANK[1] [405],QOSBW BE QOS BANK1 Register 405" bitfld.quad 0xCA8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCA8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCA8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCA8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCA8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCA8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCB0 "QOSBW_BE_QOS_BANK[1] [406],QOSBW BE QOS BANK1 Register 406" bitfld.quad 0xCB0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCB0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCB0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCB0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCB0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCB0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCB8 "QOSBW_BE_QOS_BANK[1] [407],QOSBW BE QOS BANK1 Register 407" bitfld.quad 0xCB8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCB8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCB8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCB8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCB8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCB8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCC0 "QOSBW_BE_QOS_BANK[1] [408],QOSBW BE QOS BANK1 Register 408" bitfld.quad 0xCC0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCC0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCC0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCC0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCC0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCC0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCC8 "QOSBW_BE_QOS_BANK[1] [409],QOSBW BE QOS BANK1 Register 409" bitfld.quad 0xCC8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCC8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCC8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCC8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCC8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCC8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCD0 "QOSBW_BE_QOS_BANK[1] [410],QOSBW BE QOS BANK1 Register 410" bitfld.quad 0xCD0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCD0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCD0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCD0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCD0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCD0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCD8 "QOSBW_BE_QOS_BANK[1] [411],QOSBW BE QOS BANK1 Register 411" bitfld.quad 0xCD8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCD8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCD8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCD8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCD8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCD8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCE0 "QOSBW_BE_QOS_BANK[1] [412],QOSBW BE QOS BANK1 Register 412" bitfld.quad 0xCE0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCE0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCE0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCE0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCE0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCE0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCE8 "QOSBW_BE_QOS_BANK[1] [413],QOSBW BE QOS BANK1 Register 413" bitfld.quad 0xCE8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCE8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCE8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCE8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCE8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCE8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCF0 "QOSBW_BE_QOS_BANK[1] [414],QOSBW BE QOS BANK1 Register 414" bitfld.quad 0xCF0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCF0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCF0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCF0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCF0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCF0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xCF8 "QOSBW_BE_QOS_BANK[1] [415],QOSBW BE QOS BANK1 Register 415" bitfld.quad 0xCF8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xCF8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xCF8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xCF8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xCF8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xCF8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD00 "QOSBW_BE_QOS_BANK[1] [416],QOSBW BE QOS BANK1 Register 416" bitfld.quad 0xD00 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD00 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD00 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD00 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD00 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD00 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD08 "QOSBW_BE_QOS_BANK[1] [417],QOSBW BE QOS BANK1 Register 417" bitfld.quad 0xD08 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD08 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD08 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD08 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD08 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD08 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD10 "QOSBW_BE_QOS_BANK[1] [418],QOSBW BE QOS BANK1 Register 418" bitfld.quad 0xD10 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD10 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD10 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD10 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD10 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD10 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD18 "QOSBW_BE_QOS_BANK[1] [419],QOSBW BE QOS BANK1 Register 419" bitfld.quad 0xD18 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD18 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD18 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD18 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD18 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD18 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD20 "QOSBW_BE_QOS_BANK[1] [420],QOSBW BE QOS BANK1 Register 420" bitfld.quad 0xD20 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD20 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD20 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD20 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD20 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD20 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD28 "QOSBW_BE_QOS_BANK[1] [421],QOSBW BE QOS BANK1 Register 421" bitfld.quad 0xD28 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD28 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD28 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD28 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD28 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD28 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD30 "QOSBW_BE_QOS_BANK[1] [422],QOSBW BE QOS BANK1 Register 422" bitfld.quad 0xD30 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD30 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD30 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD30 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD30 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD30 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD38 "QOSBW_BE_QOS_BANK[1] [423],QOSBW BE QOS BANK1 Register 423" bitfld.quad 0xD38 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD38 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD38 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD38 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD38 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD38 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD40 "QOSBW_BE_QOS_BANK[1] [424],QOSBW BE QOS BANK1 Register 424" bitfld.quad 0xD40 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD40 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD40 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD40 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD40 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD40 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD48 "QOSBW_BE_QOS_BANK[1] [425],QOSBW BE QOS BANK1 Register 425" bitfld.quad 0xD48 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD48 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD48 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD48 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD48 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD48 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD50 "QOSBW_BE_QOS_BANK[1] [426],QOSBW BE QOS BANK1 Register 426" bitfld.quad 0xD50 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD50 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD50 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD50 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD50 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD50 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD58 "QOSBW_BE_QOS_BANK[1] [427],QOSBW BE QOS BANK1 Register 427" bitfld.quad 0xD58 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD58 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD58 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD58 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD58 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD58 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD60 "QOSBW_BE_QOS_BANK[1] [428],QOSBW BE QOS BANK1 Register 428" bitfld.quad 0xD60 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD60 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD60 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD60 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD60 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD60 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD68 "QOSBW_BE_QOS_BANK[1] [429],QOSBW BE QOS BANK1 Register 429" bitfld.quad 0xD68 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD68 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD68 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD68 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD68 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD68 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD70 "QOSBW_BE_QOS_BANK[1] [430],QOSBW BE QOS BANK1 Register 430" bitfld.quad 0xD70 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD70 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD70 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD70 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD70 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD70 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD78 "QOSBW_BE_QOS_BANK[1] [431],QOSBW BE QOS BANK1 Register 431" bitfld.quad 0xD78 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD78 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD78 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD78 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD78 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD78 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD80 "QOSBW_BE_QOS_BANK[1] [432],QOSBW BE QOS BANK1 Register 432" bitfld.quad 0xD80 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD80 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD80 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD80 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD80 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD80 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD88 "QOSBW_BE_QOS_BANK[1] [433],QOSBW BE QOS BANK1 Register 433" bitfld.quad 0xD88 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD88 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD88 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD88 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD88 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD88 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD90 "QOSBW_BE_QOS_BANK[1] [434],QOSBW BE QOS BANK1 Register 434" bitfld.quad 0xD90 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD90 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD90 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD90 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD90 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD90 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xD98 "QOSBW_BE_QOS_BANK[1] [435],QOSBW BE QOS BANK1 Register 435" bitfld.quad 0xD98 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xD98 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xD98 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xD98 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xD98 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xD98 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDA0 "QOSBW_BE_QOS_BANK[1] [436],QOSBW BE QOS BANK1 Register 436" bitfld.quad 0xDA0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDA0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDA0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDA0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDA0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDA0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDA8 "QOSBW_BE_QOS_BANK[1] [437],QOSBW BE QOS BANK1 Register 437" bitfld.quad 0xDA8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDA8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDA8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDA8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDA8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDA8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDB0 "QOSBW_BE_QOS_BANK[1] [438],QOSBW BE QOS BANK1 Register 438" bitfld.quad 0xDB0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDB0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDB0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDB0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDB0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDB0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDB8 "QOSBW_BE_QOS_BANK[1] [439],QOSBW BE QOS BANK1 Register 439" bitfld.quad 0xDB8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDB8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDB8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDB8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDB8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDB8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDC0 "QOSBW_BE_QOS_BANK[1] [440],QOSBW BE QOS BANK1 Register 440" bitfld.quad 0xDC0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDC0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDC0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDC0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDC0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDC0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDC8 "QOSBW_BE_QOS_BANK[1] [441],QOSBW BE QOS BANK1 Register 441" bitfld.quad 0xDC8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDC8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDC8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDC8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDC8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDC8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDD0 "QOSBW_BE_QOS_BANK[1] [442],QOSBW BE QOS BANK1 Register 442" bitfld.quad 0xDD0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDD0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDD0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDD0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDD0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDD0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDD8 "QOSBW_BE_QOS_BANK[1] [443],QOSBW BE QOS BANK1 Register 443" bitfld.quad 0xDD8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDD8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDD8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDD8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDD8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDD8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDE0 "QOSBW_BE_QOS_BANK[1] [444],QOSBW BE QOS BANK1 Register 444" bitfld.quad 0xDE0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDE0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDE0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDE0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDE0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDE0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDE8 "QOSBW_BE_QOS_BANK[1] [445],QOSBW BE QOS BANK1 Register 445" bitfld.quad 0xDE8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDE8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDE8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDE8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDE8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDE8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDF0 "QOSBW_BE_QOS_BANK[1] [446],QOSBW BE QOS BANK1 Register 446" bitfld.quad 0xDF0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDF0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDF0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDF0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDF0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDF0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xDF8 "QOSBW_BE_QOS_BANK[1] [447],QOSBW BE QOS BANK1 Register 447" bitfld.quad 0xDF8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xDF8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xDF8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xDF8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xDF8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xDF8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE00 "QOSBW_BE_QOS_BANK[1] [448],QOSBW BE QOS BANK1 Register 448" bitfld.quad 0xE00 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE00 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE00 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE00 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE00 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE00 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE08 "QOSBW_BE_QOS_BANK[1] [449],QOSBW BE QOS BANK1 Register 449" bitfld.quad 0xE08 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE08 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE08 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE08 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE08 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE08 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE10 "QOSBW_BE_QOS_BANK[1] [450],QOSBW BE QOS BANK1 Register 450" bitfld.quad 0xE10 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE10 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE10 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE10 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE10 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE10 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE18 "QOSBW_BE_QOS_BANK[1] [451],QOSBW BE QOS BANK1 Register 451" bitfld.quad 0xE18 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE18 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE18 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE18 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE18 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE18 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE20 "QOSBW_BE_QOS_BANK[1] [452],QOSBW BE QOS BANK1 Register 452" bitfld.quad 0xE20 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE20 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE20 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE20 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE20 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE20 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE28 "QOSBW_BE_QOS_BANK[1] [453],QOSBW BE QOS BANK1 Register 453" bitfld.quad 0xE28 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE28 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE28 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE28 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE28 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE28 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE30 "QOSBW_BE_QOS_BANK[1] [454],QOSBW BE QOS BANK1 Register 454" bitfld.quad 0xE30 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE30 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE30 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE30 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE30 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE30 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE38 "QOSBW_BE_QOS_BANK[1] [455],QOSBW BE QOS BANK1 Register 455" bitfld.quad 0xE38 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE38 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE38 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE38 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE38 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE38 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE40 "QOSBW_BE_QOS_BANK[1] [456],QOSBW BE QOS BANK1 Register 456" bitfld.quad 0xE40 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE40 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE40 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE40 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE40 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE40 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE48 "QOSBW_BE_QOS_BANK[1] [457],QOSBW BE QOS BANK1 Register 457" bitfld.quad 0xE48 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE48 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE48 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE48 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE48 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE48 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE50 "QOSBW_BE_QOS_BANK[1] [458],QOSBW BE QOS BANK1 Register 458" bitfld.quad 0xE50 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE50 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE50 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE50 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE50 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE50 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE58 "QOSBW_BE_QOS_BANK[1] [459],QOSBW BE QOS BANK1 Register 459" bitfld.quad 0xE58 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE58 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE58 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE58 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE58 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE58 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE60 "QOSBW_BE_QOS_BANK[1] [460],QOSBW BE QOS BANK1 Register 460" bitfld.quad 0xE60 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE60 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE60 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE60 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE60 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE60 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE68 "QOSBW_BE_QOS_BANK[1] [461],QOSBW BE QOS BANK1 Register 461" bitfld.quad 0xE68 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE68 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE68 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE68 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE68 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE68 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE70 "QOSBW_BE_QOS_BANK[1] [462],QOSBW BE QOS BANK1 Register 462" bitfld.quad 0xE70 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE70 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE70 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE70 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE70 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE70 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE78 "QOSBW_BE_QOS_BANK[1] [463],QOSBW BE QOS BANK1 Register 463" bitfld.quad 0xE78 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE78 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE78 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE78 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE78 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE78 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE80 "QOSBW_BE_QOS_BANK[1] [464],QOSBW BE QOS BANK1 Register 464" bitfld.quad 0xE80 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE80 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE80 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE80 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE80 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE80 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE88 "QOSBW_BE_QOS_BANK[1] [465],QOSBW BE QOS BANK1 Register 465" bitfld.quad 0xE88 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE88 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE88 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE88 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE88 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE88 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE90 "QOSBW_BE_QOS_BANK[1] [466],QOSBW BE QOS BANK1 Register 466" bitfld.quad 0xE90 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE90 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE90 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE90 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE90 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE90 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xE98 "QOSBW_BE_QOS_BANK[1] [467],QOSBW BE QOS BANK1 Register 467" bitfld.quad 0xE98 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xE98 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xE98 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xE98 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xE98 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xE98 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xEA0 "QOSBW_BE_QOS_BANK[1] [468],QOSBW BE QOS BANK1 Register 468" bitfld.quad 0xEA0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xEA0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xEA0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xEA0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xEA0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xEA0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xEA8 "QOSBW_BE_QOS_BANK[1] [469],QOSBW BE QOS BANK1 Register 469" bitfld.quad 0xEA8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xEA8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xEA8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xEA8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xEA8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xEA8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xEB0 "QOSBW_BE_QOS_BANK[1] [470],QOSBW BE QOS BANK1 Register 470" bitfld.quad 0xEB0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xEB0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xEB0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xEB0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xEB0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xEB0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xEB8 "QOSBW_BE_QOS_BANK[1] [471],QOSBW BE QOS BANK1 Register 471" bitfld.quad 0xEB8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xEB8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xEB8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xEB8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xEB8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xEB8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xEC0 "QOSBW_BE_QOS_BANK[1] [472],QOSBW BE QOS BANK1 Register 472" bitfld.quad 0xEC0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xEC0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xEC0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xEC0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xEC0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xEC0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xEC8 "QOSBW_BE_QOS_BANK[1] [473],QOSBW BE QOS BANK1 Register 473" bitfld.quad 0xEC8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xEC8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xEC8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xEC8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xEC8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xEC8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xED0 "QOSBW_BE_QOS_BANK[1] [474],QOSBW BE QOS BANK1 Register 474" bitfld.quad 0xED0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xED0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xED0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xED0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xED0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xED0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xED8 "QOSBW_BE_QOS_BANK[1] [475],QOSBW BE QOS BANK1 Register 475" bitfld.quad 0xED8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xED8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xED8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xED8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xED8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xED8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xEE0 "QOSBW_BE_QOS_BANK[1] [476],QOSBW BE QOS BANK1 Register 476" bitfld.quad 0xEE0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xEE0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xEE0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xEE0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xEE0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xEE0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xEE8 "QOSBW_BE_QOS_BANK[1] [477],QOSBW BE QOS BANK1 Register 477" bitfld.quad 0xEE8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xEE8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xEE8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xEE8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xEE8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xEE8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xEF0 "QOSBW_BE_QOS_BANK[1] [478],QOSBW BE QOS BANK1 Register 478" bitfld.quad 0xEF0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xEF0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xEF0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xEF0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xEF0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xEF0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xEF8 "QOSBW_BE_QOS_BANK[1] [479],QOSBW BE QOS BANK1 Register 479" bitfld.quad 0xEF8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xEF8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xEF8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xEF8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xEF8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xEF8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF00 "QOSBW_BE_QOS_BANK[1] [480],QOSBW BE QOS BANK1 Register 480" bitfld.quad 0xF00 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF00 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF00 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF00 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF00 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF00 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF08 "QOSBW_BE_QOS_BANK[1] [481],QOSBW BE QOS BANK1 Register 481" bitfld.quad 0xF08 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF08 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF08 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF08 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF08 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF08 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF10 "QOSBW_BE_QOS_BANK[1] [482],QOSBW BE QOS BANK1 Register 482" bitfld.quad 0xF10 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF10 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF10 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF10 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF10 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF10 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF18 "QOSBW_BE_QOS_BANK[1] [483],QOSBW BE QOS BANK1 Register 483" bitfld.quad 0xF18 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF18 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF18 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF18 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF18 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF18 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF20 "QOSBW_BE_QOS_BANK[1] [484],QOSBW BE QOS BANK1 Register 484" bitfld.quad 0xF20 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF20 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF20 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF20 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF20 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF20 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF28 "QOSBW_BE_QOS_BANK[1] [485],QOSBW BE QOS BANK1 Register 485" bitfld.quad 0xF28 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF28 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF28 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF28 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF28 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF28 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF30 "QOSBW_BE_QOS_BANK[1] [486],QOSBW BE QOS BANK1 Register 486" bitfld.quad 0xF30 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF30 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF30 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF30 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF30 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF30 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF38 "QOSBW_BE_QOS_BANK[1] [487],QOSBW BE QOS BANK1 Register 487" bitfld.quad 0xF38 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF38 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF38 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF38 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF38 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF38 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF40 "QOSBW_BE_QOS_BANK[1] [488],QOSBW BE QOS BANK1 Register 488" bitfld.quad 0xF40 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF40 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF40 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF40 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF40 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF40 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF48 "QOSBW_BE_QOS_BANK[1] [489],QOSBW BE QOS BANK1 Register 489" bitfld.quad 0xF48 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF48 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF48 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF48 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF48 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF48 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF50 "QOSBW_BE_QOS_BANK[1] [490],QOSBW BE QOS BANK1 Register 490" bitfld.quad 0xF50 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF50 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF50 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF50 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF50 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF50 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF58 "QOSBW_BE_QOS_BANK[1] [491],QOSBW BE QOS BANK1 Register 491" bitfld.quad 0xF58 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF58 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF58 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF58 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF58 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF58 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF60 "QOSBW_BE_QOS_BANK[1] [492],QOSBW BE QOS BANK1 Register 492" bitfld.quad 0xF60 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF60 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF60 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF60 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF60 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF60 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF68 "QOSBW_BE_QOS_BANK[1] [493],QOSBW BE QOS BANK1 Register 493" bitfld.quad 0xF68 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF68 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF68 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF68 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF68 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF68 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF70 "QOSBW_BE_QOS_BANK[1] [494],QOSBW BE QOS BANK1 Register 494" bitfld.quad 0xF70 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF70 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF70 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF70 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF70 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF70 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF78 "QOSBW_BE_QOS_BANK[1] [495],QOSBW BE QOS BANK1 Register 495" bitfld.quad 0xF78 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF78 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF78 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF78 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF78 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF78 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF80 "QOSBW_BE_QOS_BANK[1] [496],QOSBW BE QOS BANK1 Register 496" bitfld.quad 0xF80 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF80 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF80 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF80 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF80 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF80 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF88 "QOSBW_BE_QOS_BANK[1] [497],QOSBW BE QOS BANK1 Register 497" bitfld.quad 0xF88 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF88 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF88 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF88 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF88 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF88 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF90 "QOSBW_BE_QOS_BANK[1] [498],QOSBW BE QOS BANK1 Register 498" bitfld.quad 0xF90 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF90 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF90 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF90 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF90 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF90 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xF98 "QOSBW_BE_QOS_BANK[1] [499],QOSBW BE QOS BANK1 Register 499" bitfld.quad 0xF98 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xF98 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xF98 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xF98 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xF98 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xF98 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFA0 "QOSBW_BE_QOS_BANK[1] [500],QOSBW BE QOS BANK1 Register 500" bitfld.quad 0xFA0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFA0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFA0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFA0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFA0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFA0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFA8 "QOSBW_BE_QOS_BANK[1] [501],QOSBW BE QOS BANK1 Register 501" bitfld.quad 0xFA8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFA8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFA8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFA8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFA8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFA8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFB0 "QOSBW_BE_QOS_BANK[1] [502],QOSBW BE QOS BANK1 Register 502" bitfld.quad 0xFB0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFB0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFB0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFB0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFB0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFB0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFB8 "QOSBW_BE_QOS_BANK[1] [503],QOSBW BE QOS BANK1 Register 503" bitfld.quad 0xFB8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFB8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFB8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFB8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFB8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFB8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFC0 "QOSBW_BE_QOS_BANK[1] [504],QOSBW BE QOS BANK1 Register 504" bitfld.quad 0xFC0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFC0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFC0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFC0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFC0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFC0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFC8 "QOSBW_BE_QOS_BANK[1] [505],QOSBW BE QOS BANK1 Register 505" bitfld.quad 0xFC8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFC8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFC8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFC8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFC8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFC8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFD0 "QOSBW_BE_QOS_BANK[1] [506],QOSBW BE QOS BANK1 Register 506" bitfld.quad 0xFD0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFD0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFD0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFD0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFD0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFD0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFD8 "QOSBW_BE_QOS_BANK[1] [507],QOSBW BE QOS BANK1 Register 507" bitfld.quad 0xFD8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFD8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFD8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFD8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFD8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFD8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFE0 "QOSBW_BE_QOS_BANK[1] [508],QOSBW BE QOS BANK1 Register 508" bitfld.quad 0xFE0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFE0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFE0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFE0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFE0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFE0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFE8 "QOSBW_BE_QOS_BANK[1] [509],QOSBW BE QOS BANK1 Register 509" bitfld.quad 0xFE8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFE8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFE8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFE8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFE8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFE8 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFF0 "QOSBW_BE_QOS_BANK[1] [510],QOSBW BE QOS BANK1 Register 510" bitfld.quad 0xFF0 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFF0 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFF0 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFF0 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFF0 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFF0 0.--10. 1. "BEQOS_BANK1_0" line.quad 0xFF8 "QOSBW_BE_QOS_BANK[1] [511],QOSBW BE QOS BANK1 Register 511" bitfld.quad 0xFF8 52.--53. "BEQOS_BANK1_5" "0,1,2,3" hexmask.quad.byte 0xFF8 48.--51. 1. "BEQOS_BANK1_4" hexmask.quad.byte 0xFF8 36.--43. 1. "BEQOS_BANK1_3" newline hexmask.quad.word 0xFF8 20.--35. 1. "BEQOS_BANK1_2" hexmask.quad.word 0xFF8 10.--19. 1. "BEQOS_BANK1_1" hexmask.quad.word 0xFF8 0.--10. 1. "BEQOS_BANK1_0" group.long 0x8000++0xF line.long 0x0 "QOSCTRL_SL_INIT,QOSCTRL SL INIT Register" hexmask.long.byte 0x0 24.--27. 1. "refsslot" hexmask.long.byte 0x0 16.--19. 1. "slotsslot" hexmask.long.word 0x0 0.--8. 1. "sslotclk" line.long 0x4 "QOSCTRL_REF_ARS,QOSCTRL REF ARS Register" hexmask.long.word 0x4 16.--24. 1. "arbstopcycle" line.long 0x8 "QOSCTRL_STATQC,QOSCTRL STATQC Register" bitfld.long 0x8 8. "refresh_mode" "0,1" bitfld.long 0x8 0. "statqen" "0,1" line.long 0xC "QOSCTRL_MEMBANK,QOSCTRL MEMBANK Register" bitfld.long 0xC 8. "exe_membank" "0,1" bitfld.long 0xC 0. "membank" "0,1" group.long 0x8030++0xF line.long 0x0 "QOSWT_WTEN,QOSWT WTEN Register" bitfld.long 0x0 0. "wtbank_en" "0,1" line.long 0x4 "QOSWT_WTREF,QOSWT WTREF Register" hexmask.long.word 0x4 16.--31. 1. "wtrefsslot1_enable" hexmask.long.word 0x4 0.--15. 1. "wtrefsslot0_enable" line.long 0x8 "QOSWT_WTSET0,QOSWT WTSET0 Register" hexmask.long.word 0x8 16.--31. 1. "wtperiold0" hexmask.long.byte 0x8 8.--11. 1. "wtsslot0" hexmask.long.byte 0x8 0.--3. 1. "wtslotsslot0" line.long 0xC "QOSWT_WTSET1,QOSWT WTSET1 Register" hexmask.long.word 0xC 16.--31. 1. "wtperiold1" hexmask.long.byte 0xC 8.--11. 1. "wtsslot1" hexmask.long.byte 0xC 0.--3. 1. "wtslotsslot1" group.long 0x8044++0xB line.long 0x0 "QOSCTRL_REF_ENBL,QOSCTRL REF ENBL Register" hexmask.long.word 0x0 0.--15. 1. "refssloten" line.long 0x4 "QOSWT_WTACC,QOSWT WTACC Register" bitfld.long 0x4 0. "wtaccess_en" "0,1" line.long 0x8 "QOSCTRL_BWG,QOSCTRL BWGranularity Register" bitfld.long 0x8 0.--2. "FIXLSB" "0,1,2,3,4,5,6,7" group.long 0x10000++0x3 line.long 0x0 "QOSCTRL_RAS,QOSCTRL RAS Register" hexmask.long.byte 0x0 0.--7. 1. "EnumInit" group.long 0x10018++0x3 line.long 0x0 "QOSCTRL_RAEN,QOSCTRL RAEN Register" bitfld.long 0x0 0. "RAllocEnable" "0,1" group.long 0x10030++0xB line.long 0x0 "QOSCTRL_DANN_LOW,QOSCTRL DANN LOW Register" hexmask.long.byte 0x0 24.--28. 1. "DAccNodeNum_FIX3" hexmask.long.byte 0x0 16.--20. 1. "DAccNodeNum_FIX2" hexmask.long.byte 0x0 8.--12. 1. "DAccNodeNum_FIX1" newline hexmask.long.byte 0x0 0.--4. 1. "DAccNodeNum_FIX0" line.long 0x4 "QOSCTRL_DANN_HIGH,QOSCTRL DANN HIGH Register" hexmask.long.byte 0x4 24.--28. 1. "DAccNodeNum_BE3" hexmask.long.byte 0x4 16.--20. 1. "DAccNodeNum_BE2" hexmask.long.byte 0x4 8.--12. 1. "DAccNodeNum_BE1" newline hexmask.long.byte 0x4 0.--4. 1. "DAccNodeNum_BE0" line.long 0x8 "QOSCTRL_DANT,QOSCTRL DANT Register" hexmask.long.byte 0x8 16.--22. 1. "DAccNodeThreshold2" hexmask.long.byte 0x8 8.--14. 1. "DAccNodeThreshold1" hexmask.long.byte 0x8 0.--6. 1. "DAccNodeThreshold0" group.long 0x10040++0x7 line.long 0x0 "QOSCTRL_EMS_LOW,QOSCTRL EMS LOW Register" bitfld.long 0x0 28.--30. "emaxschedule7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. "emaxschedule6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--22. "emaxschedule5" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "emaxschedule4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. "emaxschedule3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. "emaxschedule2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "emaxschedule1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "emaxschedule0" "0,1,2,3,4,5,6,7" line.long 0x4 "QOSCTRL_EMS_HIGH,QOSCTRL EMS HIGH Register" bitfld.long 0x4 28.--30. "emaxschedule15" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "emaxschedule14" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20.--22. "emaxschedule13" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16.--18. "emaxschedule12" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "emaxschedule11" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "emaxschedule10" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4.--6. "emaxschedule9" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "emaxschedule8" "0,1,2,3,4,5,6,7" group.long 0x10050++0x3 line.long 0x0 "QOSCTRL_INSFC,QOSCTRL INSFC Register" hexmask.long.word 0x0 16.--31. 1. "insfclear_sslot" bitfld.long 0x0 0. "insfclear_en" "0,1" group.long 0x10060++0x3 line.long 0x0 "QOSCTRL_EARLYR,QOSCTRL EARLYR Register" bitfld.long 0x0 0.--1. "early_return_mode" "0,1,2,3" group.long 0x10080++0x3 line.long 0x0 "QOSCTRL_RACNT0,QOSCTRL RACNT0 Register" bitfld.long 0x0 24.--25. "gpu_ticket_mode" "0,1,2,3" bitfld.long 0x0 18.--19. "be_ticket_mask_cycle" "0,1,2,3" bitfld.long 0x0 16.--17. "ticket_mask_cycle" "0,1,2,3" newline bitfld.long 0x0 1. "swapin_inform_disable" "0,1" bitfld.long 0x0 0. "beticket_mask_disable" "0,1" group.long 0x10088++0x3 line.long 0x0 "QOSCTRL_STATGEN0,QOSCTRL STATGEN0 Register" bitfld.long 0x0 12.--13. "vip_ticket_mode" "0,1,2,3" bitfld.long 0x0 8.--9. "imp_ticket_mode" "0,1,2,3" bitfld.long 0x0 4.--5. "cpu_ticket_mode" "0,1,2,3" newline bitfld.long 0x0 0.--1. "gpu_ticket_mode" "0,1,2,3" tree.end tree "RFSO" base ad:0x0 tree "RFSO_0" base ad:0xFFE80000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree "RFSO_1" base ad:0xFFE81000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree "RFSO_2" base ad:0xFFE82000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree "RFSO_3" base ad:0xFFE83000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree "RFSO_4" base ad:0xFFE84000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree "RFSO_5" base ad:0xFFE85000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree "RFSO_6" base ad:0xFFE86000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree "RFSO_7" base ad:0xFFE87000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree "RFSO_8" base ad:0xFFE88000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree "RFSO_9" base ad:0xFFE89000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree "RFSO_10" base ad:0xFFE8A000 group.long 0x0++0xF line.long 0x0 "CNT0_CYC,CNT0_CYC sets the periodical cycle value to the interval timer." hexmask.long 0x0 0.--31. 1. "CNT0_CYC,Specify the periodical cycle value to the interval timer." line.long 0x4 "CNT1_CYC,CNT1_CYC sets the periodical cycle value to the time-out detection timer." hexmask.long 0x4 0.--31. 1. "CNT1_CYC,Specify the periodical cycle value to the time-out detection timer." line.long 0x8 "FSO_CTL,FSO_CTL is a control register of this module." hexmask.long.word 0x8 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x8 8. "ITE,Enables or disables an interval timer (CNT0) interrupt request." "0: Disables the interrupt,1: Enables the interrupt" rbitfld.long 0x8 7. "TOCUNF,Indicates whether a time-out detection timer (CNT1) has stopped when the value of a time-out detection timer (CNT1) is below the lower limit (CNT1_UNS)" "0: A time-out detection timer,1: A time-out detection timer" newline rbitfld.long 0x8 6. "TOI,Indicates whether a time-out detection timer (CNT1) has stopped under the condition that the value of a time-out detection timer (CNT1) is equal to the upper limit (CNT1_CYC) or whether a time-out detection timer (CNT1) has stopped under the.." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 5. "ITI,Indicates whether there is an interval timer (CNT0) interrupt request." "0: There is no interrupt,1: There is an interrupt" rbitfld.long 0x8 4. "TOES,Indicates that time-out error status is appropriately output to the ECM module." "0,1" newline rbitfld.long 0x8 3. "CFES_1,Indicates that the CFEO_1 bit status is appropriately output to the ECM module." "0,1" bitfld.long 0x8 2. "CFEO_1,Sets the expected value verification result during test routine when the CFEO_0 bit is 1." "0,1" bitfld.long 0x8 1. "CFEO_0,Sets the expected value verification result during test routine." "0,1" newline rbitfld.long 0x8 0. "CFES_0,Indicates that the CFEO_0 bit status is appropriately output to the ECM module." "0,1" line.long 0xC "CNT_DIV,CNT_DIV sets the interval timer/time-out detection timer counter clock frequency divisor." hexmask.long 0xC 0.--31. 1. "CNT_DIV,Set the timer counter clock frequency divisor." wgroup.long 0x10++0x3 line.long 0x0 "FSO_CMD,FSO_CMD activates this module and clears the interrupts." hexmask.long.word 0x0 16.--31. 1. "KEYCODE,Register write enable code." bitfld.long 0x0 3. "TOC,Clears a time-out detection timer (CNT1) interrupt." "0,1" bitfld.long 0x0 2. "ITC,Clears an interval timer (CNT0) interrupt." "0,1" newline bitfld.long 0x0 1. "CNTS1,Activates or stops the time-out detection timer (CNT1)." "0,1" bitfld.long 0x0 0. "CNTS0,Activates or stops the interval timer (CNT0)." "0,1" rgroup.long 0x14++0x7 line.long 0x0 "CNT0_STS,CNT0_STS indicates the interval timer value." hexmask.long 0x0 0.--31. 1. "CNT0_STS,Indicates the interval timer value." line.long 0x4 "CNT1_STS,CNT1_STS indicates the time-out detection timer value." hexmask.long 0x4 0.--31. 1. "CNT1_STS,Indicates the time-out detection timer value." group.long 0x1C++0x3 line.long 0x0 "CNT1_UNS,Set time-out detection timer operation minimum cycle register." hexmask.long 0x0 0.--31. 1. "CNT1_UNS,Set minimum cycle value to stop Time-out detection timer." tree.end tree.end tree "RST" base ad:0xE6160000 rgroup.long 0x0++0x7 line.long 0x0 "MODEMR0,Note 1 : Initial value is 0 when LCS=SE. In other case. initial value is depend on MD5 pin." bitfld.long 0x0 31. "MD31,The value of MD31" "0,1" bitfld.long 0x0 31. "MD31,The value of MD31" "0,1" newline bitfld.long 0x0 31. "MD31,The value of MD31" "0,1" bitfld.long 0x0 31. "MD31,The value of MD31" "0,1" newline bitfld.long 0x0 30. "{bitname},Reserved" "0,1" bitfld.long 0x0 30. "{bitname},Reserved" "0,1" newline bitfld.long 0x0 30. "{bitname},Reserved" "0,1" bitfld.long 0x0 30. "{bitname},Reserved" "0,1" newline bitfld.long 0x0 29. "MD29,The value of MD29" "0,1" bitfld.long 0x0 29. "MD29,The value of MD29" "0,1" newline bitfld.long 0x0 29. "MD29,The value of MD29" "0,1" bitfld.long 0x0 29. "MD29,The value of MD29" "0,1" newline bitfld.long 0x0 28. "{bitname},Reserved" "0,1" bitfld.long 0x0 28. "{bitname},Reserved" "0,1" newline bitfld.long 0x0 28. "{bitname},Reserved" "0,1" bitfld.long 0x0 28. "{bitname},Reserved" "0,1" newline bitfld.long 0x0 27. "MD27,The value of MD27" "0,1" bitfld.long 0x0 27. "MD27,The value of MD27" "0,1" newline bitfld.long 0x0 27. "MD27,The value of MD27" "0,1" bitfld.long 0x0 27. "MD27,The value of MD27" "0,1" newline bitfld.long 0x0 26. "{bitname},Reserved" "0,1" bitfld.long 0x0 26. "{bitname},Reserved" "0,1" newline bitfld.long 0x0 26. "{bitname},Reserved" "0,1" bitfld.long 0x0 26. "{bitname},Reserved" "0,1" newline hexmask.long.word 0x0 16.--25. 1. "MD,The value of MD[25:16]" hexmask.long.word 0x0 16.--25. 1. "MD,The value of MD[25:16]" newline hexmask.long.word 0x0 16.--25. 1. "MD,The value of MD[25:16]" hexmask.long.word 0x0 16.--25. 1. "MD,The value of MD[25:16]" newline bitfld.long 0x0 15. "{bitname},Reserved" "0,1" bitfld.long 0x0 15. "{bitname},Reserved" "0,1" newline bitfld.long 0x0 15. "{bitname},Reserved" "0,1" bitfld.long 0x0 15. "{bitname},Reserved" "0,1" newline bitfld.long 0x0 13.--14. "MD,The value of MD[14:13]" "0,1,2,3" bitfld.long 0x0 13.--14. "MD,The value of MD[14:13]" "0,1,2,3" newline bitfld.long 0x0 13.--14. "MD,The value of MD[14:13]" "0,1,2,3" bitfld.long 0x0 13.--14. "MD,The value of MD[14:13]" "0,1,2,3" newline bitfld.long 0x0 12. "{bitname},Reserved" "0,1" bitfld.long 0x0 12. "{bitname},Reserved" "0,1" newline bitfld.long 0x0 12. "{bitname},Reserved" "0,1" bitfld.long 0x0 12. "{bitname},Reserved" "0,1" newline hexmask.long.word 0x0 1.--11. 1. "MD,The value of MD[11:1]" hexmask.long.word 0x0 1.--11. 1. "MD,The value of MD[11:1]" newline hexmask.long.word 0x0 1.--11. 1. "MD,The value of MD[11:1]" hexmask.long.word 0x0 1.--11. 1. "MD,The value of MD[11:1]" newline bitfld.long 0x0 0. "{bitname},Reserved" "0,1" bitfld.long 0x0 0. "{bitname},Reserved" "0,1" newline bitfld.long 0x0 0. "{bitname},Reserved" "0,1" bitfld.long 0x0 0. "{bitname},Reserved" "0,1" line.long 0x4 "MODEMR1,Mode Monitor Register 1" bitfld.long 0x4 30.--31. "{bitname},Reserved" "0,1,2,3" bitfld.long 0x4 30.--31. "{bitname},Reserved" "0,1,2,3" newline bitfld.long 0x4 30.--31. "{bitname},Reserved" "0,1,2,3" bitfld.long 0x4 30.--31. "{bitname},Reserved" "0,1,2,3" newline bitfld.long 0x4 28.--29. "MDT,The value of MDT[1:0]" "0,1,2,3" bitfld.long 0x4 28.--29. "MDT,The value of MDT[1:0]" "0,1,2,3" newline bitfld.long 0x4 28.--29. "MDT,The value of MDT[1:0]" "0,1,2,3" bitfld.long 0x4 28.--29. "MDT,The value of MDT[1:0]" "0,1,2,3" newline hexmask.long.tbyte 0x4 4.--27. 1. "{bitname},Reserved" hexmask.long.tbyte 0x4 4.--27. 1. "{bitname},Reserved" newline hexmask.long.tbyte 0x4 4.--27. 1. "{bitname},Reserved" hexmask.long.tbyte 0x4 4.--27. 1. "{bitname},Reserved" newline bitfld.long 0x4 3. "MD35,The value of MD35" "0,1" bitfld.long 0x4 3. "MD35,The value of MD35" "0,1" newline bitfld.long 0x4 3. "MD35,The value of MD35" "0,1" bitfld.long 0x4 3. "MD35,The value of MD35" "0,1" newline bitfld.long 0x4 2. "{bitname},Reserved" "0,1" bitfld.long 0x4 2. "{bitname},Reserved" "0,1" newline bitfld.long 0x4 2. "{bitname},Reserved" "0,1" bitfld.long 0x4 2. "{bitname},Reserved" "0,1" newline bitfld.long 0x4 0.--1. "MD,The value of MD[33:32]" "0,1,2,3" bitfld.long 0x4 0.--1. "MD,The value of MD[33:32]" "0,1,2,3" newline bitfld.long 0x4 0.--1. "MD,The value of MD[33:32]" "0,1,2,3" bitfld.long 0x4 0.--1. "MD,The value of MD[33:32]" "0,1,2,3" group.long 0x10++0x4B line.long 0x0 "WDTRSTCR,Watchdog Timer Reset Control Register" bitfld.long 0x0 15. "RESBAR2S,Select BAR2 registers reset condition" "0: ICUMXBAR and ICUMXCPCR are initialized only by..,1: ICUMXBAR and ICUMXCPCR are initialized by PRESET#" bitfld.long 0x0 15. "RESBAR2S,Select BAR2 registers reset condition" "0: ICUMXBAR and ICUMXCPCR are initialized only by..,1: ICUMXBAR and ICUMXCPCR are initialized by PRESET#" newline bitfld.long 0x0 15. "RESBAR2S,Select BAR2 registers reset condition" "0: ICUMXBAR and ICUMXCPCR are initialized only by..,1: ICUMXBAR and ICUMXCPCR are initialized by PRESET#" bitfld.long 0x0 15. "RESBAR2S,Select BAR2 registers reset condition" "0: ICUMXBAR and ICUMXCPCR are initialized only by..,1: ICUMXBAR and ICUMXCPCR are initialized by PRESET#" newline bitfld.long 0x0 1. "SWDT_,System WatchDog Reset Mask" "0: Reset request,1: Not reset request" bitfld.long 0x0 1. "SWDT_,System WatchDog Reset Mask" "0: Reset request,1: Not reset request" newline bitfld.long 0x0 1. "SWDT_,System WatchDog Reset Mask" "0: Reset request,1: Not reset request" bitfld.long 0x0 1. "SWDT_,System WatchDog Reset Mask" "0: Reset request,1: Not reset request" newline bitfld.long 0x0 0. "RWDT_,RWDT Reset Mask" "0: Reset request,1: Not reset request" bitfld.long 0x0 0. "RWDT_,RWDT Reset Mask" "0: Reset request,1: Not reset request" newline bitfld.long 0x0 0. "RWDT_,RWDT Reset Mask" "0: Reset request,1: Not reset request" bitfld.long 0x0 0. "RWDT_,RWDT Reset Mask" "0: Reset request,1: Not reset request" line.long 0x4 "RSTOUTCR,PRESETOUT Control Register" bitfld.long 0x4 0. "RESOUT,PRESETOUT# control by software" "0: PRESETOUT# is asserted,1: PRESETOUT# is negated" bitfld.long 0x4 0. "RESOUT,PRESETOUT# control by software" "0: PRESETOUT# is asserted,1: PRESETOUT# is negated" newline bitfld.long 0x4 0. "RESOUT,PRESETOUT# control by software" "0: PRESETOUT# is asserted,1: PRESETOUT# is negated" bitfld.long 0x4 0. "RESOUT,PRESETOUT# control by software" "0: PRESETOUT# is asserted,1: PRESETOUT# is negated" line.long 0x8 "SRESCR0,Soft Power On Reset Control Register 0" bitfld.long 0x8 15. "SPRES,Soft Power On Reset" "0,1" bitfld.long 0x8 15. "SPRES,Soft Power On Reset" "0,1" newline bitfld.long 0x8 15. "SPRES,Soft Power On Reset" "0,1" bitfld.long 0x8 15. "SPRES,Soft Power On Reset" "0,1" line.long 0xC "SRESCR1,Soft Power On Reset Control Register 1" bitfld.long 0xC 0.--1. "PW,Soft Power On Reset Pulse with setting." "0: 100 us,1: 1ms,?,?" bitfld.long 0xC 0.--1. "PW,Soft Power On Reset Pulse with setting." "0: 100 us,1: 1ms,?,?" newline bitfld.long 0xC 0.--1. "PW,Soft Power On Reset Pulse with setting." "0: 100 us,1: 1ms,?,?" bitfld.long 0xC 0.--1. "PW,Soft Power On Reset Pulse with setting." "0: 100 us,1: 1ms,?,?" line.long 0x10 "RSTFR[0],Reset Flag Register 0" bitfld.long 0x10 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x10 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x10 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x10 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x10 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x10 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x10 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x10 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x10 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x10 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x10 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x10 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x10 0. "RPF,Soft Power On Reset detection bit" "0,1" bitfld.long 0x10 0. "RPF,Soft Power On Reset detection bit" "0,1" newline bitfld.long 0x10 0. "RPF,Soft Power On Reset detection bit" "0,1" bitfld.long 0x10 0. "RPF,Soft Power On Reset detection bit" "0,1" line.long 0x14 "RSTFR[1],Reset Flag Register 1" bitfld.long 0x14 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x14 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x14 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x14 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x14 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x14 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x14 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x14 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x14 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x14 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x14 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x14 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x14 0. "RPF,Soft Power On Reset detection bit" "0,1" bitfld.long 0x14 0. "RPF,Soft Power On Reset detection bit" "0,1" newline bitfld.long 0x14 0. "RPF,Soft Power On Reset detection bit" "0,1" bitfld.long 0x14 0. "RPF,Soft Power On Reset detection bit" "0,1" line.long 0x18 "RSTFR[2],Reset Flag Register 2" bitfld.long 0x18 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x18 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x18 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x18 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x18 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x18 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x18 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x18 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x18 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x18 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x18 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x18 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x18 0. "RPF,Soft Power On Reset detection bit" "0,1" bitfld.long 0x18 0. "RPF,Soft Power On Reset detection bit" "0,1" newline bitfld.long 0x18 0. "RPF,Soft Power On Reset detection bit" "0,1" bitfld.long 0x18 0. "RPF,Soft Power On Reset detection bit" "0,1" line.long 0x1C "RSTFR[3],Reset Flag Register 3" bitfld.long 0x1C 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x1C 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x1C 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x1C 3. "RCPRES,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x1C 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x1C 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x1C 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x1C 2. "RCSWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x1C 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x1C 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x1C 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" bitfld.long 0x1C 1. "RCRWDT,Soft Power On Reset Factor Bit" "0,1" newline bitfld.long 0x1C 0. "RPF,Soft Power On Reset detection bit" "0,1" bitfld.long 0x1C 0. "RPF,Soft Power On Reset detection bit" "0,1" newline bitfld.long 0x1C 0. "RPF,Soft Power On Reset detection bit" "0,1" bitfld.long 0x1C 0. "RPF,Soft Power On Reset detection bit" "0,1" line.long 0x20 "STBCHR[0],Standby Flag Register 0" hexmask.long 0x20 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x20 0.--31. 1. "STB[n],defined purely for software purpose" newline hexmask.long 0x20 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x20 0.--31. 1. "STB[n],defined purely for software purpose" line.long 0x24 "STBCHR[1],Standby Flag Register 1" hexmask.long 0x24 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x24 0.--31. 1. "STB[n],defined purely for software purpose" newline hexmask.long 0x24 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x24 0.--31. 1. "STB[n],defined purely for software purpose" line.long 0x28 "STBCHR[2],Standby Flag Register 2" hexmask.long 0x28 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x28 0.--31. 1. "STB[n],defined purely for software purpose" newline hexmask.long 0x28 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x28 0.--31. 1. "STB[n],defined purely for software purpose" line.long 0x2C "STBCHR[3],Standby Flag Register 3" hexmask.long 0x2C 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x2C 0.--31. 1. "STB[n],defined purely for software purpose" newline hexmask.long 0x2C 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x2C 0.--31. 1. "STB[n],defined purely for software purpose" line.long 0x30 "STBCHR[4],Standby Flag Register 4" hexmask.long 0x30 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x30 0.--31. 1. "STB[n],defined purely for software purpose" newline hexmask.long 0x30 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x30 0.--31. 1. "STB[n],defined purely for software purpose" line.long 0x34 "STBCHR[5],Standby Flag Register 5" hexmask.long 0x34 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x34 0.--31. 1. "STB[n],defined purely for software purpose" newline hexmask.long 0x34 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x34 0.--31. 1. "STB[n],defined purely for software purpose" line.long 0x38 "STBCHR[6],Standby Flag Register 6" hexmask.long 0x38 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x38 0.--31. 1. "STB[n],defined purely for software purpose" newline hexmask.long 0x38 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x38 0.--31. 1. "STB[n],defined purely for software purpose" line.long 0x3C "STBCHR[7],Standby Flag Register 7" hexmask.long 0x3C 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x3C 0.--31. 1. "STB[n],defined purely for software purpose" newline hexmask.long 0x3C 0.--31. 1. "STB[n],defined purely for software purpose" hexmask.long 0x3C 0.--31. 1. "STB[n],defined purely for software purpose" line.long 0x40 "APBSFTYCHKR,APB Bus Safety Check Register" hexmask.long 0x40 0.--31. 1. "CHK,defined purely for software purpose" hexmask.long 0x40 0.--31. 1. "CHK,defined purely for software purpose" newline hexmask.long 0x40 0.--31. 1. "CHK,defined purely for software purpose" hexmask.long 0x40 0.--31. 1. "CHK,defined purely for software purpose" line.long 0x44 "ICUMXBAR,ICUMXA Boot Address Register" hexmask.long.tbyte 0x44 9.--31. 1. "RBAR2,ICUMXA Boot Address2" hexmask.long.tbyte 0x44 9.--31. 1. "RBAR2,ICUMXA Boot Address2" newline hexmask.long.tbyte 0x44 9.--31. 1. "RBAR2,ICUMXA Boot Address2" hexmask.long.tbyte 0x44 9.--31. 1. "RBAR2,ICUMXA Boot Address2" newline bitfld.long 0x44 4. "BAREN *3,BAREN bit" "0: RBAR2 is not valid,1: RBAR2 is valid" bitfld.long 0x44 4. "BAREN *3,BAREN bit" "0: RBAR2 is not valid,1: RBAR2 is valid" newline bitfld.long 0x44 4. "BAREN *3,BAREN bit" "0: RBAR2 is not valid,1: RBAR2 is valid" bitfld.long 0x44 4. "BAREN *3,BAREN bit" "0: RBAR2 is not valid,1: RBAR2 is valid" newline bitfld.long 0x44 0.--1. "BTMD,Specifies the Boot area of ICUMXA" "0: RBAR2[31:9] is assigned to Boot address,1: Prohibited,?,?" bitfld.long 0x44 0.--1. "BTMD,Specifies the Boot area of ICUMXA" "0: RBAR2[31:9] is assigned to Boot address,1: Prohibited,?,?" newline bitfld.long 0x44 0.--1. "BTMD,Specifies the Boot area of ICUMXA" "0: RBAR2[31:9] is assigned to Boot address,1: Prohibited,?,?" bitfld.long 0x44 0.--1. "BTMD,Specifies the Boot area of ICUMXA" "0: RBAR2[31:9] is assigned to Boot address,1: Prohibited,?,?" line.long 0x48 "ICUMXCPCR,Note *1 : When MD7=1 and MD6=0. initial value is 1. in other case initial value is 0." hexmask.long 0x48 1.--31. 1. "{bitname},Reserved" hexmask.long 0x48 1.--31. 1. "{bitname},Reserved" newline hexmask.long 0x48 1.--31. 1. "{bitname},Reserved" hexmask.long 0x48 1.--31. 1. "{bitname},Reserved" newline bitfld.long 0x48 0. "ICUMXCPINIT,0: Reset to ICUMXA is asserted. ICUMXA is not booted." "0: Reset to ICUMXA is asserted,1: Reset to ICUMXA is de-asserted" bitfld.long 0x48 0. "ICUMXCPINIT,0: Reset to ICUMXA is asserted. ICUMXA is not booted." "0: Reset to ICUMXA is asserted,1: Reset to ICUMXA is de-asserted" newline bitfld.long 0x48 0. "ICUMXCPINIT,0: Reset to ICUMXA is asserted. ICUMXA is not booted." "0: Reset to ICUMXA is asserted,1: Reset to ICUMXA is de-asserted" bitfld.long 0x48 0. "ICUMXCPINIT,0: Reset to ICUMXA is asserted. ICUMXA is not booted." "0: Reset to ICUMXA is asserted,1: Reset to ICUMXA is de-asserted" group.long 0x68++0x7 line.long 0x0 "RSTPTCSR,Protect Control/Status Register" bitfld.long 0x0 1. "EIE,Enable error interrupt request of write access protection" "0: Disable error interrupt request,1: Enable error interrupt request" bitfld.long 0x0 1. "EIE,Enable error interrupt request of write access protection" "0: Disable error interrupt request,1: Enable error interrupt request" newline bitfld.long 0x0 1. "EIE,Enable error interrupt request of write access protection" "0: Disable error interrupt request,1: Enable error interrupt request" bitfld.long 0x0 1. "EIE,Enable error interrupt request of write access protection" "0: Disable error interrupt request,1: Enable error interrupt request" newline bitfld.long 0x0 0. "ERR,Display the status of error detection on secure access protection" "0: Not detect error,1: Detect error of write access protection to.." bitfld.long 0x0 0. "ERR,Display the status of error detection on secure access protection" "0: Not detect error,1: Detect error of write access protection to.." newline bitfld.long 0x0 0. "ERR,Display the status of error detection on secure access protection" "0: Not detect error,1: Detect error of write access protection to.." bitfld.long 0x0 0. "ERR,Display the status of error detection on secure access protection" "0: Not detect error,1: Detect error of write access protection to.." line.long 0x4 "RSTPTERADR,Protect Error Address Register" hexmask.long.word 0x4 1.--15. 1. "ADDR,Offset address[15:1] of the first illegal write access to the protected registers." hexmask.long.word 0x4 1.--15. 1. "ADDR,Offset address[15:1] of the first illegal write access to the protected registers." newline hexmask.long.word 0x4 1.--15. 1. "ADDR,Offset address[15:1] of the first illegal write access to the protected registers." hexmask.long.word 0x4 1.--15. 1. "ADDR,Offset address[15:1] of the first illegal write access to the protected registers." newline bitfld.long 0x4 0. "ADDR0,Offset address[0] of the first illegal write access to the protected registers." "0,1" bitfld.long 0x4 0. "ADDR0,Offset address[0] of the first illegal write access to the protected registers." "0,1" newline bitfld.long 0x4 0. "ADDR0,Offset address[0] of the first illegal write access to the protected registers." "0,1" bitfld.long 0x4 0. "ADDR0,Offset address[0] of the first illegal write access to the protected registers." "0,1" group.long 0x3800++0x3 line.long 0x0 "RSTD1WACR,Domain 0 Write Access Control REgister" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" group.long 0x3A00++0x3 line.long 0x0 "RSTD[1]WACR,Domain 1 Write Access Control Register" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" group.long 0x3C00++0x3 line.long 0x0 "RSTD[2]WACR,Domain 2 Write Access Control Register" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" group.long 0x3E00++0x3 line.long 0x0 "RSTD[3]WACR,Domain 3 Write Access Control Register" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 27. "RSTPTERADR,Write permission to RSTPTERADR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 26. "RSTPTCSR,Write permission to RSTPTCSR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 22. "ICUMXCPCR,Write permission to ICUMXCPCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 21. "ICUMXBAR,Write permission to ICUMXBAR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 20. "APBSFTYCHKR,Write permission to APBSFTYCHKR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 19. "STBC7,Write permission to STBCHR7 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 18. "STBC6,Write permission to STBCHR6 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 17. "STBC5,Write permission to STBCHR5 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 16. "STBC4,Write permission to STBCHR4 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 15. "STBC3,Write permission to STBCHR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 14. "STBC2,Write permission to STBCHR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 13. "STBC1,Write permission to STBCHR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 12. "STBC0,Write permission to STBCHR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 11. "RSTFR3,Write permission to RSTFR3 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 10. "RSTFR2,Write permission to RSTFR2 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 9. "RSTFR1,Write permission to RSTFR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 8. "RSTFR0,Write permission to RSTFR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 7. "SRESCR1,Write permission to SRESCR1 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 6. "SRESCR0,Write permission to SRESCR0 register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 5. "RSTOUTCR,Write permission to RSTOUTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" newline bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" bitfld.long 0x0 4. "WDTRSTCR,Write permission to WDTRSTCR register from domain n." "0: Prohibit write access,1: Permit write access" tree.end tree "RT_SRAM" base ad:0xFFE90000 group.long 0x0++0x3B line.long 0x0 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x0 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x4 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x4 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x8 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x8 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0xC "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0xC 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x10 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x10 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x14 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x14 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x18 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x18 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x1C "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x1C 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x20 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x20 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x24 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x24 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x28 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x28 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x2C "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x2C 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x30 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x30 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x34 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x34 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." line.long 0x38 "SECDIVnD,Function: The boundary address setting of the secure region." hexmask.long.byte 0x38 0.--7. 1. "DIVADDR,Protection division address [20:13] is set." group.long 0x40++0x3F line.long 0x0 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x0 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x0 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x4 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x4 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x4 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x8 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x8 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x8 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0xC "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0xC 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0xC 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x10 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x10 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x10 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x14 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x14 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x14 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x18 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x18 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x18 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x1C "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x1C 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x1C 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x20 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x20 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x20 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x24 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x24 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x24 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x28 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x28 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x28 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x2C "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x2C 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x2C 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x30 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x30 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x30 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x34 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x34 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x34 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x38 "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x38 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x38 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x3C "SECCTRRnD,Function: Privilege setting of each secure region." bitfld.long 0x3C 19. "SECG0RP,Secure Group0 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 18. "SECG1RP,Secure Group1 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 17. "SECG2RP,Secure Group2 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 16. "SECG3RP,Secure Group3 Read Privilege Setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 15. "SAFG0RP,Safety Group0 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 14. "SAFG1RP,Safety Group1 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 13. "SAFG2RP,Safety Group2 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 12. "SAFG3RP,Safety Group3 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 11. "SAFG4RP,Safety Group4 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 10. "SAFG5RP,Safety Group5 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 9. "SAFG6RP,Safety Group6 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 8. "SAFG7RP,Safety Group7 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 7. "SAFG8RP,Safety Group8 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 6. "SAFG9RP,Safety Group9 Register Read Privilege setting" "0: Has the privilege to Read to this register,1: Does not have the privilege Read to this register" newline bitfld.long 0x3C 5. "SAFG10RP,Safety Group10 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 4. "SAFG11RP,Safety Group11 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 3. "SAFG12RP,Safety Group12 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 2. "SAFG13RP,Safety Group13 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 1. "SAFG14RP,Safety Group14 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 0. "SAFG15RP,Safety Group15 Register Read Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." group.long 0x340++0x3F line.long 0x0 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x0 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x0 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x0 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x0 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x0 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x0 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x4 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x4 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x4 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x4 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x4 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x4 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x4 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x8 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x8 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x8 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x8 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x8 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x8 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x8 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0xC "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0xC 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0xC 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0xC 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0xC 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0xC 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0xC 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x10 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x10 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x10 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x10 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x10 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x10 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x10 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x14 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x14 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x14 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x14 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x14 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x14 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x14 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x18 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x18 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x18 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x18 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x18 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x18 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x18 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x1C "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x1C 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x1C 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x1C 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x1C 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x1C 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x1C 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x20 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x20 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x20 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x20 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x20 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x20 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x20 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x24 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x24 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x24 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x24 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x24 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x24 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x24 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x28 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x28 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x28 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x28 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x28 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x28 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x28 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x2C "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x2C 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x2C 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x2C 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x2C 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x2C 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x2C 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x30 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x30 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x30 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x30 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x30 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x30 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x30 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x34 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x34 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x34 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x34 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x34 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x34 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x34 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x38 "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x38 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x38 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x38 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x38 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x38 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x38 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." line.long 0x3C "SECCTRWnD,Function: Privilege setting of each secure region." bitfld.long 0x3C 19. "SECG0WP,Secure Group0 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x3C 18. "SECG1WP,Secure Group1 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x3C 17. "SECG2WP,Secure Group2 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x3C 16. "SECG3WP,Secure Group3 Write Privilege Setting" "0: Has the privilege to Write to the relevant..,1: Does not have the privilege Write to the.." newline bitfld.long 0x3C 15. "SAFG0WP,Safety Group0 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 14. "SAFG1WP,Safety Group1 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 13. "SAFG2WP,Safety Group2 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 12. "SAFG3WP,Safety Group3 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 11. "SAFG4WP,Safety Group4 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 10. "SAFG5WP,Safety Group5 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 9. "SAFG6WP,Safety Group6 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 8. "SAFG7WP,Safety Group7 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 7. "SAFG8WP,Safety Group8 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 6. "SAFG9WP,Safety Group9 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 5. "SAFG10WP,Safety Group10 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 4. "SAFG11WP,Safety Group11 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 3. "SAFG12WP,Safety Group12 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 2. "SAFG13WP,Safety Group13 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 1. "SAFG14WP,Safety Group14 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." newline bitfld.long 0x3C 0. "SAFG15WP,Safety Group15 Register Write Privilege setting" "0: Has the privilege to read to the relevant..,1: Does not have the privilege read to the relevant.." group.long 0x80++0x7 line.long 0x0 "SECCAUSE,Function: Secure error cause excluding by ICU." bitfld.long 0x0 16. "LOCK,Secure error cause and information is locked." "0,1" newline bitfld.long 0x0 1. "SECERR_R,Secure error detects of read port." "0,1" newline bitfld.long 0x0 0. "SECERR_W,Secure error detects of write port." "0,1" line.long 0x4 "SAFCAUSE,Safety Error Status Register" bitfld.long 0x4 16. "LOCK,Safety error cause and information is locked." "0,1" newline bitfld.long 0x4 1. "SAFERR_R,Safety error detect of read port." "0,1" newline bitfld.long 0x4 0. "SAFERR_W,Safety error detect of write port." "0,1" rgroup.long 0x88++0xF line.long 0x0 "SECERRINF0,Function: Secure error information (error ID) excluding by ICU." hexmask.long 0x0 0.--24. 1. "SECERRID,Secure error axid" line.long 0x4 "SECERRINF1,Function: Secure Error Information (error address) excluding by ICU." hexmask.long 0x4 0.--31. 1. "SECERRADDR,Secure error axaddr [31:0]" line.long 0x8 "SAFERRINF0,Safety Error Information 1 Register" hexmask.long 0x8 0.--24. 1. "SAFERRID,Safety error axid" line.long 0xC "SAFERRINF1,Safety Error Information 2 Register" hexmask.long 0xC 0.--31. 1. "SAFERRADDR,Safety error axaddr [31:0]" group.long 0xA0++0x7 line.long 0x0 "ICUSECCAUSE,Function: Secure error cause by ICU." bitfld.long 0x0 16. "LOCK,ICU secure error cause and information is locked." "0,1" newline bitfld.long 0x0 1. "SECERR_R,Secure error detect of read port." "0,1" newline bitfld.long 0x0 0. "SECERR_W,Secure error detect of write port." "0,1" line.long 0x4 "ICUSAFCAUSE,ICU Safety Error Status Register" bitfld.long 0x4 16. "LOCK,Safety error cause and information is locked." "0,1" newline bitfld.long 0x4 1. "SAFERR_R,Safety error detect of read port." "0,1" newline bitfld.long 0x4 0. "SAFERR_W,Safety error detect of write port." "0,1" rgroup.long 0xA8++0xF line.long 0x0 "ICUSECERRINF0,Function: Secure error information (error ID) by ICU." hexmask.long 0x0 0.--24. 1. "SECERRID,Secure error axid" line.long 0x4 "ICUSECERRINF1,Function: Secure error information (error address) by ICU." hexmask.long 0x4 0.--31. 1. "SECERRADDR,Secure error axaddr [31:0]" line.long 0x8 "ICUSAFERRINF0,ICU Safety Error Information 1 Register" hexmask.long 0x8 0.--24. 1. "SAFERRID,Safety error axid" line.long 0xC "ICUSAFERRINF1,ICU Safety Error Information 2 Register" hexmask.long 0xC 0.--31. 1. "SAFERRADDR,Safety error axaddr [31:0]" group.long 0x100++0x7 line.long 0x0 "ERRBUSCAUSE,EDC Error Status Register" bitfld.long 0x0 7. "ECC_OVF,ECC 1bit/2bit EAB Overflow" "0: No ECC 1bit/2bit EAB Overflow,1: Clear this bit" newline bitfld.long 0x0 6. "ECC_RD_DED,ECC Error detect of Memory Read Data (DED/2bit)" "0: No ECC 2bit Error,1: Clear this bit" newline bitfld.long 0x0 5. "ECC_RD_SED,ECC Error detect of Memory Read Data (SED/1bit)" "0: No ECC 1bit Error,1: Clear this bit" newline bitfld.long 0x0 4. "EDC_WR,EDC Error detect of AXI2RAM Internal Write Data" "0: No Internal Write data ECC Error,1: Clear this bit" newline bitfld.long 0x0 2. "EDC_W,EDC Error detect of AXI W channel" "0: No AXI Wch EDC error,1: Clear this bit" newline bitfld.long 0x0 1. "EDC_AW,EDC Error detect of AXI AW channel" "0: No AXI AWch EDC error,1: Clear this bit" newline bitfld.long 0x0 0. "EDC_AR,EDC Error detect of AXI AR channel" "0: No AXI ARch EDC error,1: Clear this bit" line.long 0x4 "ICUERRBUSCAUSE,ICU EDC Error Status Register" bitfld.long 0x4 7. "ECC_OVF,ECC 1bit/2bit EAB Overflow" "0: No ECC 1bit/2bit EAB Overflow,1: Clear this bit" newline bitfld.long 0x4 6. "ECC_RD_DED,ECC Error detect of Memory Read Data (DED/2bit)" "0: No ECC 2bit Error,1: Clear this bit" newline bitfld.long 0x4 5. "ECC_RD_SED,ECC Error detect of Memory Read Data (SED/1bit)" "0: No ECC 1bit Error,1: Clear this bit" newline bitfld.long 0x4 4. "EDC_WR,EDC Error detect of AXI2RAM Internal Write Data" "0: No Internal Write data ECC Error,1: Clear this bit" newline bitfld.long 0x4 2. "EDC_W,EDC Error detect of AXI W channel" "0: No AXI Wch EDC error,1: Clear this bit" newline bitfld.long 0x4 1. "EDC_AW,EDC Error detect of AXI AW channel" "0: No AXI AWch EDC error,1: Clear this bit" newline bitfld.long 0x4 0. "EDC_AR,EDC Error detect of AXI AR channel" "0: No AXI ARch EDC error,1: Clear this bit" rgroup.long 0x108++0xF line.long 0x0 "ERRBUSINF0,Function: EDC error information (error ID) excluding by ICU." hexmask.long 0x0 0.--24. 1. "ERRBUSID,EDC error axid" line.long 0x4 "ERRBUSINF1,Function: EDC Error Information (error address) excluding by ICU." hexmask.long 0x4 0.--31. 1. "ERRBUSADDR,EDC error axaddr" line.long 0x8 "ICUERRBUSINF0,Function: EDC error information (error ID) of ICU." hexmask.long 0x8 0.--24. 1. "ICUERRBUSID,EDC error axid" line.long 0xC "ICUERRBUSINF1,Function: EDC Error Information (error address) excluding by ICU." hexmask.long 0xC 0.--31. 1. "ICUERRBUSADDR,EDC error axaddr" group.long 0x120++0x7 line.long 0x0 "ECC_CONTROL,ECC Collection Control Register" bitfld.long 0x0 0. "ECC_ENABLE,Read Data ECC correction Enable" "0: Disable,1: Enable" line.long 0x4 "EDC_OFF_NO_ECC,ECC Generation Control Register" bitfld.long 0x4 0. "EDC_OFF_NO_ECC,Enable ECC value written to Memory when EDC disable" "0: ECC value written to memory,1: ECC value not written to memory" rgroup.long 0x128++0x3 line.long 0x0 "ECCINFO,ECC 1bit Or 2bit EAB Information" bitfld.long 0x0 18. "VALID,EAB info valid" "0: N/A,1: VALID info" newline bitfld.long 0x0 16.--17. "VMC_ID,Corresponding VMC number" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "ECC_ADDR,ECC 1bit/2bit error ram address" group.long 0x130++0x3 line.long 0x0 "APBERRCAUSE,APB EDC Error Status Register" bitfld.long 0x0 1. "EDC_WDAT,APB WDATA EDC Error detect" "0: No APB WDATA EDC error,1: Clear this bit" newline bitfld.long 0x0 0. "EDC_ADR,APB ADDR EDC Error detect" "0: No APB ADDR EDC error,1: Clear this bit" rgroup.long 0x134++0x7 line.long 0x0 "APBERRINF0,Function: EDC error information (error ID) excluding by ICU." hexmask.long 0x0 0.--31. 1. "ERR_ADR,APB EDC error ADDRESS" line.long 0x4 "APBERRINF1,Function: EDC Error Information (error address) excluding by ICU." hexmask.long 0x4 0.--31. 1. "ERR_WDAT,APB EDC error WDATA" rgroup.long 0x180++0x3 line.long 0x0 "AFBERREN,AFB Error Enable Register" bitfld.long 0x0 0. "EN_AFB_ERR,AFB Error detect Enable" "0: Not detect Address feedback error,1: Detect Address feedback error" group.long 0x184++0x7 line.long 0x0 "AFBERRCAUSE,AFB Error Status Register" bitfld.long 0x0 0. "AFB_ERR,Address Feedback Error excluding ICU access" "0: No Address feedback error,1: Clear this bit" line.long 0x4 "ICUAFBERRCAUSE,ICU AFB Error Status Register" bitfld.long 0x4 0. "AFB_ERR,Address Feedback Error when ICU accessing" "0: No Address feedback error,1: Clear this bit" rgroup.long 0x18C++0xF line.long 0x0 "AFBERRINFO0,Function: AFB error information (error ID) excluding by ICU." bitfld.long 0x0 25.--26. "VMCID,VMC ID of AFB error" "0: VMC0,1: VMC1,2: VMC2,3: VMC3" newline hexmask.long 0x0 0.--24. 1. "AFBERRID,AFB error axid excluding ICU access" line.long 0x4 "AFBERRINFO1,Function: AFB Error Information (error address) excluding by ICU." hexmask.long 0x4 0.--31. 1. "AFBERRADDR,AFB error axaddr excluding ICU access" line.long 0x8 "ICUAFBERRINF0,Function: AFB error information (error ID) of ICU." bitfld.long 0x8 25.--26. "VMCID,VMC ID of AFB error" "0: VMC0,1: VMC1,2: VMC2,3: VMC3" newline hexmask.long 0x8 0.--24. 1. "AFBERRID,AFB error axid when ICU accessing" line.long 0xC "ICUAFBERRINF1,Function: AFB Error Information (error address) of ICU." hexmask.long 0xC 0.--31. 1. "AFBERRADDR,AFB error axaddr when ICU accessing" group.long 0x200++0x3 line.long 0x0 "MEM_INIT,Function: Initialization request for the memory." bitfld.long 0x0 31. "LOCK,Software Reset Lock" "0: Unlock,1: Lock" newline bitfld.long 0x0 0. "SWRESET,[write (1 only)]" "?,1: running" group.long 0x210++0x7 line.long 0x0 "EX_ADR_MASKL,Function: Address mask for exclusive access. There is a configuration of lower 32 bit." hexmask.long 0x0 0.--31. 1. "EXADRMSKL,Address compare mask of exclusive access (1: compare)" line.long 0x4 "EX_ADR_MASKH,Function: Address mask for exclusive access. There is a configuration of upper 8 bit." hexmask.long.byte 0x4 0.--7. 1. "EXADRMSKH,Address compare mask of exclusive access (1: compare)" group.long 0x280++0xF line.long 0x0 "CKMSCTR,AXI Clock Monitor Control/Status Register" rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline hexmask.long.byte 0x0 25.--30. 1. "- (rsv),Reserved. But connect signals from clock monitor." newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - PQCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline hexmask.long.byte 0x0 19.--23. 1. "- (rsv),Reserved. But connect signals from clock monitor." newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMSCLR,AXI Clock Monitor Error Clear Register" bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMSCMPH,AXI Clock Monitor Limit Count H Register" hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMSCMPL,AXI Clock Monitor Limit Count L Register" hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The lower limit to judge as expected oscillation." rgroup.long 0x290++0x7 line.long 0x0 "CKMSCNT,AXI Clock Monitor Count Register" hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMSCNTE,AXI Clock Monitor Count on Error Register" bitfld.long 0x4 31. "VLD" "0,1" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE" newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE" group.long 0x298++0x3 line.long 0x0 "CKMSMDR,AXI Clock Monitor Mode Register" hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved. (T.B.D.)" group.long 0x2A0++0xF line.long 0x0 "CKMPCTR,APB Clock Monitor Control/Status Register" rbitfld.long 0x0 31. "CHKRES,Check result." "0: Clock oscillates normally,1: Detect unexpected clock oscillation" newline hexmask.long.byte 0x0 25.--30. 1. "- (rsv),Reserved. But connect signals from clock monitor." newline rbitfld.long 0x0 24. "CLRMON,Reference for clear command signal - PQCKMECR.CLRRES" "0: Clear command signal is released,1: Clear command signal is issued" newline hexmask.long.byte 0x0 19.--23. 1. "- (rsv),Reserved. But connect signals from clock monitor." newline rbitfld.long 0x0 18. "RSTM_MON,Reset status for monitor clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 17. "RSTM_SMP,Reset status for sampling clock domain of clock monitor module." "0: Reset signal is issued,1: Reset signal is released" newline rbitfld.long 0x0 16. "ENMON,Operating status." "0: Clock monitor is stopped,1: Clock monitor is operating" newline bitfld.long 0x0 1. "INTEN,Interrupt mask bit." "0: Mask an interrupt,1: Permit to issue an interrupt when clock monitor.." newline bitfld.long 0x0 0. "CHKEN,Enable for checking clock oscillation." "0: Stop clock monitor checking,1: Run clock monitor checking" line.long 0x4 "CKMPCLR,APB Clock Monitor Error Clear Register" bitfld.long 0x4 0. "CLRRES,Clear command signal for check result." "0: Release clear signal,1: Issue clear signal to clock monitor" line.long 0x8 "CKMPCMPH,APB Clock Monitor Limit Count H Register" hexmask.long.tbyte 0x8 0.--23. 1. "CMPH,The upper limit to judge as expected oscillation." line.long 0xC "CKMPCMPL,APB Clock Monitor Limit Count L Register" hexmask.long.tbyte 0xC 0.--23. 1. "CMPL,The lower limit to judge as expected oscillation." rgroup.long 0x2B0++0x7 line.long 0x0 "CKMPCNT,APB Clock Monitor Count Register" hexmask.long.byte 0x0 24.--30. 1. "UPDCNT,The number of times of updating MONCNT." newline hexmask.long.tbyte 0x0 0.--23. 1. "MONCNT,The counter value of clock monitor in the latest sampling period." line.long 0x4 "CKMPCNTE,APB Clock Monitor Count on Error Register" bitfld.long 0x4 31. "VLD" "0,1" newline hexmask.long.byte 0x4 24.--30. 1. "UPDCNTE" newline hexmask.long.tbyte 0x4 0.--23. 1. "MONCNTE" group.long 0x2B8++0x3 line.long 0x0 "CKMPMDR,APB Clock Monitor Mode Register" hexmask.long.word 0x0 0.--15. 1. "MODE,Reserved. (T.B.D.)" rgroup.long 0x2BC++0x3 line.long 0x0 "CKMCSTS,ALL Clock Monitor Status Register" bitfld.long 0x0 1. "CKMS_STS,STS bit[15] of CKM AXICLK" "0,1" newline bitfld.long 0x0 0. "CKMP_STS,STS bit[15] of CKM APBCLK" "0,1" group.long 0x300++0x3 line.long 0x0 "DUMMY_ERROR,Dummy Error Insertion Register" bitfld.long 0x0 22. "DMY_ICU_AFB_ERR,ICU Address Feedback Fault Injection" "0,1" newline bitfld.long 0x0 20. "DMY_ICU_SECERR_[p],ERR_AXI2RAM_ICU_SECERR_p" "?,1: Generate Dummy Error" newline bitfld.long 0x0 19. "DMY_ICU_SAFERR_[p],ERR_AXI2RAM_ICU_SAFERR_p" "?,1: Generate Dummy Error" newline bitfld.long 0x0 18. "DMY_ICU_ECC_2BIT,ERR_AXI2RAM_ICU_ECC_2BIT" "?,1: Generate Dummy Error" newline bitfld.long 0x0 17. "DMY_ICU_ECC_1BIT,ERR_AXI2RAM_ICU_ECC_1BIT" "?,1: Generate Dummy Error" newline bitfld.long 0x0 16. "DMY_ICU_EDC,ERR_AXI2RAM_ICU_EDC" "?,1: Generate Dummy Error" newline bitfld.long 0x0 8. "dmcmp_err_inj,DCLS compare Fault Injection" "0,1" newline bitfld.long 0x0 7. "DMY_APB_ERR,APB EDC Fault Injection" "0,1" newline bitfld.long 0x0 6. "DMY_AFB_ERR,Address Feedback Fault Injection" "0,1" newline bitfld.long 0x0 4. "DMY_SECERR_[p],Pulse　ERR_AXI2RAM_SECERR_p" "?,1: Generate Dummy Error" newline bitfld.long 0x0 3. "DMY_SAFERR_[p],ERR_AXI2RAM_SAFERR_p" "?,1: Generate Dummy Error" newline bitfld.long 0x0 2. "DMY_ECC_2BIT,ERR_AXI2RAM_ECC_2BIT" "?,1: Generate Dummy Error" newline bitfld.long 0x0 1. "DMY_ECC_1BIT,ERR_AXI2RAM_ECC_1BIT" "?,1: Generate Dummy Error" newline bitfld.long 0x0 0. "DMY_EDC,ERR_AXI2RAM_EDC" "?,1: Generate Dummy Error" group.long 0x300++0x3 line.long 0x0 "DMCMP,DCLS Compare Register" bitfld.long 0x0 31. "compare_enable,DCLS compare enable" "0: Disable and Clear,1: Enable" newline bitfld.long 0x0 12. "AXI_AR_CMP_ERR,DCLS AXI ARch Compare Error(Secretive)" "0: No Error,1: Error" newline bitfld.long 0x0 11. "AXI_AW_CMP_ERR,DCLS AXI AWch Compare Error(Secretive)" "0: No Error,1: Error" newline bitfld.long 0x0 10. "AXI_W_CMP_ERR,DCLS AXI Wch Compare Error(Secretive)" "0: No Error,1: Error" newline bitfld.long 0x0 9. "AXI_B_CMP_ERR,DCLS AXI Bch Compare Error(Secretive)" "0: No Error,1: Error" newline bitfld.long 0x0 8. "AXI_R_CMP_ERR,DCLS AXI Rch Compare Error(Secretive)" "0: No Error,1: Error" newline bitfld.long 0x0 7. "VMC0_CMP_ERR,DCLS VMC0 Compare Error(Secretive)" "0: No Error,1: Error" newline bitfld.long 0x0 6. "VMC1_CMP_ERR,DCLS VMC1 Compare Error(Secretive)" "0: No Error,1: Error" newline bitfld.long 0x0 5. "VMC2_CMP_ERR,DCLS VMC2 Compare Error(Secretive)" "0: No Error,1: Error" newline bitfld.long 0x0 4. "VMC3_CMP_ERR,DCLS VMC3 Compare Error(Secretive)" "0: No Error,1: Error" newline bitfld.long 0x0 3. "AXI_ CMP_ERR,DCLS AXI bus Compare Error" "0: No Error,1: Error" newline bitfld.long 0x0 2. "VMC_CMP_ERR,DCLS VMC Compare Error" "0: No Error,1: Error" newline bitfld.long 0x0 1. "APB_CMP_ERR,DCLS APB bus Compare Error" "0: No Error,1: Error" newline bitfld.long 0x0 0. "REG_CMP_ERR,DCLS Register Compare Error" "0: No Error,1: Error" tree.end tree "RWDT" base ad:0xE6020000 group.long 0x0++0xB line.long 0x0 "RWTCNT,RWTCNT is a 16-bit readable/writable register that increments on the selected clock. When an overflow occurs. it generates a Reset. The RWTCNT counter is initialized to H'0000 by a power-on reset and RWDT software reset." hexmask.long.word 0x0 16.--31. 1. "CODE_VAL1,Code value 1" hexmask.long.word 0x0 0.--15. 1. "RWTCNT,Timer Counter Bits" line.long 0x4 "RWTCSRA,RWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count. overflow flag. and enable bit." hexmask.long.tbyte 0x4 8.--31. 1. "CODE_VAL2,Code value 2" bitfld.long 0x4 7. "TME,Starts and stops timer operation." "0: Timer disabled: Count-up stops and RWTCNT value..,1: Timer enabled" newline rbitfld.long 0x4 5. "WRFLG,Write Status Flag" "0,1" bitfld.long 0x4 4. "WOVF,Indicates that the RWTCNT has overflowed. This bit isn't initialized by a generated reset by an overflow of RWDT and section 78. System Watchdog Timer (SWDT). Write 0 to this bit before using the RWDT." "0: No overflow,1: RWTCNT has overflowed" newline bitfld.long 0x4 3. "WOVFE,Overflow Interrupt Disable/Enable" "0: Disables interrupts due to overflow,1: Enables interrupts due to overflow" bitfld.long 0x4 0.--2. "CKS0,RTC Clock Select" "0: RCLK,1: RCLK/4,?,?,?,?,?,?" line.long 0x8 "RWTCSRB,RWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count." hexmask.long.tbyte 0x8 8.--31. 1. "CODE_VAL3,Code value 3" hexmask.long.byte 0x8 0.--5. 1. "CKS1,RCLK Select for RCLK Select Expanded Mode" tree.end tree "SCIF" base ad:0x0 tree "SCIF_0" base ad:0xE6E60000 group.word 0x0++0x1 line.word 0x0 "SCSMR,SCSMR is a 16-bit register that sets the SCIF's serial transfer format and selects the baud rate generator clock source." bitfld.word 0x0 7. "C/A#,Communication Mode" "0: Asynchronous mode,1: Clock synchronous mode" bitfld.word 0x0 6. "CHR,Character Length" "0: 8 bits,1: 7 bits*" newline bitfld.word 0x0 5. "PE,Parity Enable" "0: Disables parity bit addition and check,1: Enables parity bit addition and check" bitfld.word 0x0 4. "O/E#,Parity Mode" "0: Even parity*1,1: Odd parity*2" newline bitfld.word 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit*1,1: 2 stop bits*2" bitfld.word 0x0 0.--1. "CKS,Clock Select 1 and 0" "0: PCK,1: PCK /4,?,?" group.byte 0x4++0x0 line.byte 0x0 "SCBRR,-" group.word 0x8++0x1 line.word 0x0 "SCSCR,SCSCR is a register that enables or disables transmission/reception by the SCIF. enables or disables interrupt requests. and selects transmission/reception clock source for the SCIF." bitfld.word 0x0 11. "TEIE,Transmit End Interrupt Enable" "0: The transmit FIFO data empty,1: The transmit end" bitfld.word 0x0 7. "TIE,Transmit Interrupt Enable" "0: When the TEIE bit is 0,1: When the TEIE bit is 0" newline bitfld.word 0x0 6. "RIE,Receive Interrupt Enable" "0: Disables receive-FIFO-data-full interrupt,1: Enables receive-FIFO-data-full interrupt" bitfld.word 0x0 5. "TE,Transmit Enable" "0: Disables transmission,1: Enables transmission" newline bitfld.word 0x0 4. "RE,Receive Enable" "0: Disables reception,1: Enables reception" bitfld.word 0x0 3. "REIE,Receive Error Interrupt Enable" "0: Disables receive-error interrupt,1: Enables receive-error interrupt" newline bitfld.word 0x0 2. "TOIE,Timeout Interrupt Enable" "0: Disables timeout interrupts,1: Enables timeout interrupts" bitfld.word 0x0 0.--1. "CKE,Clock Enable 1 and 0" "0,1,2,3" wgroup.byte 0xC++0x0 line.byte 0x0 "SCFTDR,-" group.word 0x10++0x1 line.word 0x0 "SCFSR,SCFSR is a 16-bit register. The lower 8 bits are a status flag that indicates the operating status of the SCIF. and the upper 8 bits indicate the number of reception errors of data in the receive FIFO register." hexmask.word.byte 0x0 12.--15. 1. "PER,Parity Error Count" hexmask.word.byte 0x0 8.--11. 1. "FER,Framing Error Count" newline bitfld.word 0x0 7. "ER,Receive Error" "0: Indicates that no framing or parity error has..,1: Indicates that a framing error or a parity error.." bitfld.word 0x0 6. "TEND,Indicates that transmission has been ended * because there was no valid data in SCFTDR when the last bit of the transmit character was transmitted." "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended" newline bitfld.word 0x0 5. "TDFE,Transmit FIFO Data Empty" "0: Indicates that the number of transmit data..,1: Indicates that the number of transmit data in.." bitfld.word 0x0 4. "BRK,Break Detect" "0: Indicates that no break signal has been received,1: Indicates that a break signal has been received" newline rbitfld.word 0x0 3. "FER,Framing Error" "0: Indicates that there is no framing error in the..,1: Indicates that there is a framing error in the.." rbitfld.word 0x0 2. "PER,Parity Error" "0: Indicates that there is no parity error in the..,1: Indicates that there is a parity error in the.." newline bitfld.word 0x0 1. "RDF,Receive FIFO Data Full" "0: Indicates that the number of receive data bytes..,1: Indicates that the number of receive data bytes.." bitfld.word 0x0 0. "DR,Receive Data Ready" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." rgroup.byte 0x14++0x0 line.byte 0x0 "SCFRDR,-" group.word 0x18++0x1 line.word 0x0 "SCFCR,SCFCR is a register that resets data counts and sets the number of trigger data bytes for the transmit and receive FIFO registers. It also has a loopback test enable bit." bitfld.word 0x0 8.--10. "RSTRG,RTS Output Active Trigger" "0: 15,1: 1,?,?,?,?,?,?" bitfld.word 0x0 6.--7. "RTRG,Receive FIFO Data Count Trigger" "0,1,2,3" newline bitfld.word 0x0 4.--5. "TTRG,Transmit FIFO Data Count Trigger" "0: 8,1: 4,?,?" bitfld.word 0x0 3. "MCE,Modem Control Enable" "0: Disables modem signals,1: Enables modem signals" newline bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" newline bitfld.word 0x0 0. "LOOP,Loopback Test" "0: Disables the loopback test,1: Enables the loopback test" rgroup.word 0x1C++0x1 line.word 0x0 "SCFDR,SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and that in SCFRDR." hexmask.word.byte 0x0 8.--12. 1. "T,These bits show the number of data bytes untransmitted and still stored in SCFTDR." hexmask.word.byte 0x0 0.--4. 1. "R,These bits show the number of receive data stored in SCFRDR in bytes." group.word 0x20++0x1 line.word 0x0 "SCSPTR,SCSPTR controls multiplexed input/output and data on the serial communication interface (SCIF) ports. Bits 1 and 0 control breaks in serial transmission/reception by reading input data from the RX pin and writing output data to the TX pin. Bits 3.." bitfld.word 0x0 7. "RTSIO,Serial Port RTS# Pin Input/output" "0: Indicates that this bit does not output the..,1: Indicates that this bit outputs the value of the.." bitfld.word 0x0 6. "RTSDT,Serial Port RTS# Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 5. "CTSIO,Serial Port CTS# Pin Input/output" "0: Indicates that the CTSDT bit value is not output..,1: Indicates that the CTSDT bit value is output to.." bitfld.word 0x0 4. "CTSDT,Serial Port CTS# Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 3. "SCKIO,Serial Port Clock Pin Input/output" "0: Indicates that the SCKDT bit value is not output..,1: Indicates that the SCKDT bit value is output to.." bitfld.word 0x0 2. "SCKDT,Serial Port Clock Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 1. "SPB2IO,Serial Port Break Input/Output" "0: Indicates that the SPB2DT bit value is not..,1: Indicates that the SPB2DT bit value is output to.." bitfld.word 0x0 0. "SPB2DT,Serial Port Break Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" group.word 0x24++0x1 line.word 0x0 "SCLSR,-" bitfld.word 0x0 2. "TO,Timeout" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." bitfld.word 0x0 0. "ORER,Overrun Error" "0: Indicates that data is being received or has..,1: Indicates that an overrun error has occurred in.." group.word 0x30++0x1 line.word 0x0 "DL,-" hexmask.word 0x0 0.--15. 1. "DL,Specifies a division value of frequency clock generated in BRG." group.word 0x34++0x1 line.word 0x0 "CKS,-" bitfld.word 0x0 15. "CKS,This bit switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)." "0: Selects the frequency divided clock,1: Selects the external clock" bitfld.word 0x0 14. "XIN,Selects the baud rate generator clock source for the external clock between SCIF_CLK and SCKi." "0: Selects the external clock,1: Selects the internal clock" tree.end tree "SCIF_1" base ad:0xE6E68000 group.word 0x0++0x1 line.word 0x0 "SCSMR,SCSMR is a 16-bit register that sets the SCIF's serial transfer format and selects the baud rate generator clock source." bitfld.word 0x0 7. "C/A#,Communication Mode" "0: Asynchronous mode,1: Clock synchronous mode" bitfld.word 0x0 6. "CHR,Character Length" "0: 8 bits,1: 7 bits*" newline bitfld.word 0x0 5. "PE,Parity Enable" "0: Disables parity bit addition and check,1: Enables parity bit addition and check" bitfld.word 0x0 4. "O/E#,Parity Mode" "0: Even parity*1,1: Odd parity*2" newline bitfld.word 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit*1,1: 2 stop bits*2" bitfld.word 0x0 0.--1. "CKS,Clock Select 1 and 0" "0: PCK,1: PCK /4,?,?" group.byte 0x4++0x0 line.byte 0x0 "SCBRR,-" group.word 0x8++0x1 line.word 0x0 "SCSCR,SCSCR is a register that enables or disables transmission/reception by the SCIF. enables or disables interrupt requests. and selects transmission/reception clock source for the SCIF." bitfld.word 0x0 11. "TEIE,Transmit End Interrupt Enable" "0: The transmit FIFO data empty,1: The transmit end" bitfld.word 0x0 7. "TIE,Transmit Interrupt Enable" "0: When the TEIE bit is 0,1: When the TEIE bit is 0" newline bitfld.word 0x0 6. "RIE,Receive Interrupt Enable" "0: Disables receive-FIFO-data-full interrupt,1: Enables receive-FIFO-data-full interrupt" bitfld.word 0x0 5. "TE,Transmit Enable" "0: Disables transmission,1: Enables transmission" newline bitfld.word 0x0 4. "RE,Receive Enable" "0: Disables reception,1: Enables reception" bitfld.word 0x0 3. "REIE,Receive Error Interrupt Enable" "0: Disables receive-error interrupt,1: Enables receive-error interrupt" newline bitfld.word 0x0 2. "TOIE,Timeout Interrupt Enable" "0: Disables timeout interrupts,1: Enables timeout interrupts" bitfld.word 0x0 0.--1. "CKE,Clock Enable 1 and 0" "0,1,2,3" wgroup.byte 0xC++0x0 line.byte 0x0 "SCFTDR,-" group.word 0x10++0x1 line.word 0x0 "SCFSR,SCFSR is a 16-bit register. The lower 8 bits are a status flag that indicates the operating status of the SCIF. and the upper 8 bits indicate the number of reception errors of data in the receive FIFO register." hexmask.word.byte 0x0 12.--15. 1. "PER,Parity Error Count" hexmask.word.byte 0x0 8.--11. 1. "FER,Framing Error Count" newline bitfld.word 0x0 7. "ER,Receive Error" "0: Indicates that no framing or parity error has..,1: Indicates that a framing error or a parity error.." bitfld.word 0x0 6. "TEND,Indicates that transmission has been ended * because there was no valid data in SCFTDR when the last bit of the transmit character was transmitted." "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended" newline bitfld.word 0x0 5. "TDFE,Transmit FIFO Data Empty" "0: Indicates that the number of transmit data..,1: Indicates that the number of transmit data in.." bitfld.word 0x0 4. "BRK,Break Detect" "0: Indicates that no break signal has been received,1: Indicates that a break signal has been received" newline rbitfld.word 0x0 3. "FER,Framing Error" "0: Indicates that there is no framing error in the..,1: Indicates that there is a framing error in the.." rbitfld.word 0x0 2. "PER,Parity Error" "0: Indicates that there is no parity error in the..,1: Indicates that there is a parity error in the.." newline bitfld.word 0x0 1. "RDF,Receive FIFO Data Full" "0: Indicates that the number of receive data bytes..,1: Indicates that the number of receive data bytes.." bitfld.word 0x0 0. "DR,Receive Data Ready" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." rgroup.byte 0x14++0x0 line.byte 0x0 "SCFRDR,-" group.word 0x18++0x1 line.word 0x0 "SCFCR,SCFCR is a register that resets data counts and sets the number of trigger data bytes for the transmit and receive FIFO registers. It also has a loopback test enable bit." bitfld.word 0x0 8.--10. "RSTRG,RTS Output Active Trigger" "0: 15,1: 1,?,?,?,?,?,?" bitfld.word 0x0 6.--7. "RTRG,Receive FIFO Data Count Trigger" "0,1,2,3" newline bitfld.word 0x0 4.--5. "TTRG,Transmit FIFO Data Count Trigger" "0: 8,1: 4,?,?" bitfld.word 0x0 3. "MCE,Modem Control Enable" "0: Disables modem signals,1: Enables modem signals" newline bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" newline bitfld.word 0x0 0. "LOOP,Loopback Test" "0: Disables the loopback test,1: Enables the loopback test" rgroup.word 0x1C++0x1 line.word 0x0 "SCFDR,SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and that in SCFRDR." hexmask.word.byte 0x0 8.--12. 1. "T,These bits show the number of data bytes untransmitted and still stored in SCFTDR." hexmask.word.byte 0x0 0.--4. 1. "R,These bits show the number of receive data stored in SCFRDR in bytes." group.word 0x20++0x1 line.word 0x0 "SCSPTR,SCSPTR controls multiplexed input/output and data on the serial communication interface (SCIF) ports. Bits 1 and 0 control breaks in serial transmission/reception by reading input data from the RX pin and writing output data to the TX pin. Bits 3.." bitfld.word 0x0 7. "RTSIO,Serial Port RTS# Pin Input/output" "0: Indicates that this bit does not output the..,1: Indicates that this bit outputs the value of the.." bitfld.word 0x0 6. "RTSDT,Serial Port RTS# Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 5. "CTSIO,Serial Port CTS# Pin Input/output" "0: Indicates that the CTSDT bit value is not output..,1: Indicates that the CTSDT bit value is output to.." bitfld.word 0x0 4. "CTSDT,Serial Port CTS# Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 3. "SCKIO,Serial Port Clock Pin Input/output" "0: Indicates that the SCKDT bit value is not output..,1: Indicates that the SCKDT bit value is output to.." bitfld.word 0x0 2. "SCKDT,Serial Port Clock Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 1. "SPB2IO,Serial Port Break Input/Output" "0: Indicates that the SPB2DT bit value is not..,1: Indicates that the SPB2DT bit value is output to.." bitfld.word 0x0 0. "SPB2DT,Serial Port Break Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" group.word 0x24++0x1 line.word 0x0 "SCLSR,-" bitfld.word 0x0 2. "TO,Timeout" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." bitfld.word 0x0 0. "ORER,Overrun Error" "0: Indicates that data is being received or has..,1: Indicates that an overrun error has occurred in.." group.word 0x30++0x1 line.word 0x0 "DL,-" hexmask.word 0x0 0.--15. 1. "DL,Specifies a division value of frequency clock generated in BRG." group.word 0x34++0x1 line.word 0x0 "CKS,-" bitfld.word 0x0 15. "CKS,This bit switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)." "0: Selects the frequency divided clock,1: Selects the external clock" bitfld.word 0x0 14. "XIN,Selects the baud rate generator clock source for the external clock between SCIF_CLK and SCKi." "0: Selects the external clock,1: Selects the internal clock" tree.end tree "SCIF_2" base ad:0xE6C50000 group.word 0x0++0x1 line.word 0x0 "SCSMR,SCSMR is a 16-bit register that sets the SCIF's serial transfer format and selects the baud rate generator clock source." bitfld.word 0x0 7. "C/A#,Communication Mode" "0: Asynchronous mode,1: Clock synchronous mode" bitfld.word 0x0 6. "CHR,Character Length" "0: 8 bits,1: 7 bits*" newline bitfld.word 0x0 5. "PE,Parity Enable" "0: Disables parity bit addition and check,1: Enables parity bit addition and check" bitfld.word 0x0 4. "O/E#,Parity Mode" "0: Even parity*1,1: Odd parity*2" newline bitfld.word 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit*1,1: 2 stop bits*2" bitfld.word 0x0 0.--1. "CKS,Clock Select 1 and 0" "0: PCK,1: PCK /4,?,?" group.byte 0x4++0x0 line.byte 0x0 "SCBRR,-" group.word 0x8++0x1 line.word 0x0 "SCSCR,SCSCR is a register that enables or disables transmission/reception by the SCIF. enables or disables interrupt requests. and selects transmission/reception clock source for the SCIF." bitfld.word 0x0 11. "TEIE,Transmit End Interrupt Enable" "0: The transmit FIFO data empty,1: The transmit end" bitfld.word 0x0 7. "TIE,Transmit Interrupt Enable" "0: When the TEIE bit is 0,1: When the TEIE bit is 0" newline bitfld.word 0x0 6. "RIE,Receive Interrupt Enable" "0: Disables receive-FIFO-data-full interrupt,1: Enables receive-FIFO-data-full interrupt" bitfld.word 0x0 5. "TE,Transmit Enable" "0: Disables transmission,1: Enables transmission" newline bitfld.word 0x0 4. "RE,Receive Enable" "0: Disables reception,1: Enables reception" bitfld.word 0x0 3. "REIE,Receive Error Interrupt Enable" "0: Disables receive-error interrupt,1: Enables receive-error interrupt" newline bitfld.word 0x0 2. "TOIE,Timeout Interrupt Enable" "0: Disables timeout interrupts,1: Enables timeout interrupts" bitfld.word 0x0 0.--1. "CKE,Clock Enable 1 and 0" "0,1,2,3" wgroup.byte 0xC++0x0 line.byte 0x0 "SCFTDR,-" group.word 0x10++0x1 line.word 0x0 "SCFSR,SCFSR is a 16-bit register. The lower 8 bits are a status flag that indicates the operating status of the SCIF. and the upper 8 bits indicate the number of reception errors of data in the receive FIFO register." hexmask.word.byte 0x0 12.--15. 1. "PER,Parity Error Count" hexmask.word.byte 0x0 8.--11. 1. "FER,Framing Error Count" newline bitfld.word 0x0 7. "ER,Receive Error" "0: Indicates that no framing or parity error has..,1: Indicates that a framing error or a parity error.." bitfld.word 0x0 6. "TEND,Indicates that transmission has been ended * because there was no valid data in SCFTDR when the last bit of the transmit character was transmitted." "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended" newline bitfld.word 0x0 5. "TDFE,Transmit FIFO Data Empty" "0: Indicates that the number of transmit data..,1: Indicates that the number of transmit data in.." bitfld.word 0x0 4. "BRK,Break Detect" "0: Indicates that no break signal has been received,1: Indicates that a break signal has been received" newline rbitfld.word 0x0 3. "FER,Framing Error" "0: Indicates that there is no framing error in the..,1: Indicates that there is a framing error in the.." rbitfld.word 0x0 2. "PER,Parity Error" "0: Indicates that there is no parity error in the..,1: Indicates that there is a parity error in the.." newline bitfld.word 0x0 1. "RDF,Receive FIFO Data Full" "0: Indicates that the number of receive data bytes..,1: Indicates that the number of receive data bytes.." bitfld.word 0x0 0. "DR,Receive Data Ready" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." rgroup.byte 0x14++0x0 line.byte 0x0 "SCFRDR,-" group.word 0x18++0x1 line.word 0x0 "SCFCR,SCFCR is a register that resets data counts and sets the number of trigger data bytes for the transmit and receive FIFO registers. It also has a loopback test enable bit." bitfld.word 0x0 8.--10. "RSTRG,RTS Output Active Trigger" "0: 15,1: 1,?,?,?,?,?,?" bitfld.word 0x0 6.--7. "RTRG,Receive FIFO Data Count Trigger" "0,1,2,3" newline bitfld.word 0x0 4.--5. "TTRG,Transmit FIFO Data Count Trigger" "0: 8,1: 4,?,?" bitfld.word 0x0 3. "MCE,Modem Control Enable" "0: Disables modem signals,1: Enables modem signals" newline bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" newline bitfld.word 0x0 0. "LOOP,Loopback Test" "0: Disables the loopback test,1: Enables the loopback test" rgroup.word 0x1C++0x1 line.word 0x0 "SCFDR,SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and that in SCFRDR." hexmask.word.byte 0x0 8.--12. 1. "T,These bits show the number of data bytes untransmitted and still stored in SCFTDR." hexmask.word.byte 0x0 0.--4. 1. "R,These bits show the number of receive data stored in SCFRDR in bytes." group.word 0x20++0x1 line.word 0x0 "SCSPTR,SCSPTR controls multiplexed input/output and data on the serial communication interface (SCIF) ports. Bits 1 and 0 control breaks in serial transmission/reception by reading input data from the RX pin and writing output data to the TX pin. Bits 3.." bitfld.word 0x0 7. "RTSIO,Serial Port RTS# Pin Input/output" "0: Indicates that this bit does not output the..,1: Indicates that this bit outputs the value of the.." bitfld.word 0x0 6. "RTSDT,Serial Port RTS# Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 5. "CTSIO,Serial Port CTS# Pin Input/output" "0: Indicates that the CTSDT bit value is not output..,1: Indicates that the CTSDT bit value is output to.." bitfld.word 0x0 4. "CTSDT,Serial Port CTS# Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 3. "SCKIO,Serial Port Clock Pin Input/output" "0: Indicates that the SCKDT bit value is not output..,1: Indicates that the SCKDT bit value is output to.." bitfld.word 0x0 2. "SCKDT,Serial Port Clock Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 1. "SPB2IO,Serial Port Break Input/Output" "0: Indicates that the SPB2DT bit value is not..,1: Indicates that the SPB2DT bit value is output to.." bitfld.word 0x0 0. "SPB2DT,Serial Port Break Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" group.word 0x24++0x1 line.word 0x0 "SCLSR,-" bitfld.word 0x0 2. "TO,Timeout" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." bitfld.word 0x0 0. "ORER,Overrun Error" "0: Indicates that data is being received or has..,1: Indicates that an overrun error has occurred in.." group.word 0x30++0x1 line.word 0x0 "DL,-" hexmask.word 0x0 0.--15. 1. "DL,Specifies a division value of frequency clock generated in BRG." group.word 0x34++0x1 line.word 0x0 "CKS,-" bitfld.word 0x0 15. "CKS,This bit switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)." "0: Selects the frequency divided clock,1: Selects the external clock" bitfld.word 0x0 14. "XIN,Selects the baud rate generator clock source for the external clock between SCIF_CLK and SCKi." "0: Selects the external clock,1: Selects the internal clock" tree.end tree "SCIF_3" base ad:0xE6C40000 group.word 0x0++0x1 line.word 0x0 "SCSMR,SCSMR is a 16-bit register that sets the SCIF's serial transfer format and selects the baud rate generator clock source." bitfld.word 0x0 7. "C/A#,Communication Mode" "0: Asynchronous mode,1: Clock synchronous mode" bitfld.word 0x0 6. "CHR,Character Length" "0: 8 bits,1: 7 bits*" newline bitfld.word 0x0 5. "PE,Parity Enable" "0: Disables parity bit addition and check,1: Enables parity bit addition and check" bitfld.word 0x0 4. "O/E#,Parity Mode" "0: Even parity*1,1: Odd parity*2" newline bitfld.word 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit*1,1: 2 stop bits*2" bitfld.word 0x0 0.--1. "CKS,Clock Select 1 and 0" "0: PCK,1: PCK /4,?,?" group.byte 0x4++0x0 line.byte 0x0 "SCBRR,-" group.word 0x8++0x1 line.word 0x0 "SCSCR,SCSCR is a register that enables or disables transmission/reception by the SCIF. enables or disables interrupt requests. and selects transmission/reception clock source for the SCIF." bitfld.word 0x0 11. "TEIE,Transmit End Interrupt Enable" "0: The transmit FIFO data empty,1: The transmit end" bitfld.word 0x0 7. "TIE,Transmit Interrupt Enable" "0: When the TEIE bit is 0,1: When the TEIE bit is 0" newline bitfld.word 0x0 6. "RIE,Receive Interrupt Enable" "0: Disables receive-FIFO-data-full interrupt,1: Enables receive-FIFO-data-full interrupt" bitfld.word 0x0 5. "TE,Transmit Enable" "0: Disables transmission,1: Enables transmission" newline bitfld.word 0x0 4. "RE,Receive Enable" "0: Disables reception,1: Enables reception" bitfld.word 0x0 3. "REIE,Receive Error Interrupt Enable" "0: Disables receive-error interrupt,1: Enables receive-error interrupt" newline bitfld.word 0x0 2. "TOIE,Timeout Interrupt Enable" "0: Disables timeout interrupts,1: Enables timeout interrupts" bitfld.word 0x0 0.--1. "CKE,Clock Enable 1 and 0" "0,1,2,3" wgroup.byte 0xC++0x0 line.byte 0x0 "SCFTDR,-" group.word 0x10++0x1 line.word 0x0 "SCFSR,SCFSR is a 16-bit register. The lower 8 bits are a status flag that indicates the operating status of the SCIF. and the upper 8 bits indicate the number of reception errors of data in the receive FIFO register." hexmask.word.byte 0x0 12.--15. 1. "PER,Parity Error Count" hexmask.word.byte 0x0 8.--11. 1. "FER,Framing Error Count" newline bitfld.word 0x0 7. "ER,Receive Error" "0: Indicates that no framing or parity error has..,1: Indicates that a framing error or a parity error.." bitfld.word 0x0 6. "TEND,Indicates that transmission has been ended * because there was no valid data in SCFTDR when the last bit of the transmit character was transmitted." "0: Indicates that transmission is in progress,1: Indicates that transmission has been ended" newline bitfld.word 0x0 5. "TDFE,Transmit FIFO Data Empty" "0: Indicates that the number of transmit data..,1: Indicates that the number of transmit data in.." bitfld.word 0x0 4. "BRK,Break Detect" "0: Indicates that no break signal has been received,1: Indicates that a break signal has been received" newline rbitfld.word 0x0 3. "FER,Framing Error" "0: Indicates that there is no framing error in the..,1: Indicates that there is a framing error in the.." rbitfld.word 0x0 2. "PER,Parity Error" "0: Indicates that there is no parity error in the..,1: Indicates that there is a parity error in the.." newline bitfld.word 0x0 1. "RDF,Receive FIFO Data Full" "0: Indicates that the number of receive data bytes..,1: Indicates that the number of receive data bytes.." bitfld.word 0x0 0. "DR,Receive Data Ready" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." rgroup.byte 0x14++0x0 line.byte 0x0 "SCFRDR,-" group.word 0x18++0x1 line.word 0x0 "SCFCR,SCFCR is a register that resets data counts and sets the number of trigger data bytes for the transmit and receive FIFO registers. It also has a loopback test enable bit." bitfld.word 0x0 8.--10. "RSTRG,RTS Output Active Trigger" "0: 15,1: 1,?,?,?,?,?,?" bitfld.word 0x0 6.--7. "RTRG,Receive FIFO Data Count Trigger" "0,1,2,3" newline bitfld.word 0x0 4.--5. "TTRG,Transmit FIFO Data Count Trigger" "0: 8,1: 4,?,?" bitfld.word 0x0 3. "MCE,Modem Control Enable" "0: Disables modem signals,1: Enables modem signals" newline bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset" "0: Disables the reset,1: Enables the reset" newline bitfld.word 0x0 0. "LOOP,Loopback Test" "0: Disables the loopback test,1: Enables the loopback test" rgroup.word 0x1C++0x1 line.word 0x0 "SCFDR,SCFDR is a 16-bit register that indicates the number of data bytes stored in SCFTDR and that in SCFRDR." hexmask.word.byte 0x0 8.--12. 1. "T,These bits show the number of data bytes untransmitted and still stored in SCFTDR." hexmask.word.byte 0x0 0.--4. 1. "R,These bits show the number of receive data stored in SCFRDR in bytes." group.word 0x20++0x1 line.word 0x0 "SCSPTR,SCSPTR controls multiplexed input/output and data on the serial communication interface (SCIF) ports. Bits 1 and 0 control breaks in serial transmission/reception by reading input data from the RX pin and writing output data to the TX pin. Bits 3.." bitfld.word 0x0 7. "RTSIO,Serial Port RTS# Pin Input/output" "0: Indicates that this bit does not output the..,1: Indicates that this bit outputs the value of the.." bitfld.word 0x0 6. "RTSDT,Serial Port RTS# Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 5. "CTSIO,Serial Port CTS# Pin Input/output" "0: Indicates that the CTSDT bit value is not output..,1: Indicates that the CTSDT bit value is output to.." bitfld.word 0x0 4. "CTSDT,Serial Port CTS# Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 3. "SCKIO,Serial Port Clock Pin Input/output" "0: Indicates that the SCKDT bit value is not output..,1: Indicates that the SCKDT bit value is output to.." bitfld.word 0x0 2. "SCKDT,Serial Port Clock Pin Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" newline bitfld.word 0x0 1. "SPB2IO,Serial Port Break Input/Output" "0: Indicates that the SPB2DT bit value is not..,1: Indicates that the SPB2DT bit value is output to.." bitfld.word 0x0 0. "SPB2DT,Serial Port Break Data" "0: Indicates that the input/output data is low level,1: Indicates that the input/output data is high level" group.word 0x24++0x1 line.word 0x0 "SCLSR,-" bitfld.word 0x0 2. "TO,Timeout" "0: Indicates that data is being received or has..,1: Indicates that no further receive data has been.." bitfld.word 0x0 0. "ORER,Overrun Error" "0: Indicates that data is being received or has..,1: Indicates that an overrun error has occurred in.." group.word 0x30++0x1 line.word 0x0 "DL,-" hexmask.word 0x0 0.--15. 1. "DL,Specifies a division value of frequency clock generated in BRG." group.word 0x34++0x1 line.word 0x0 "CKS,-" bitfld.word 0x0 15. "CKS,This bit switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)." "0: Selects the frequency divided clock,1: Selects the external clock" bitfld.word 0x0 14. "XIN,Selects the baud rate generator clock source for the external clock between SCIF_CLK and SCKi." "0: Selects the external clock,1: Selects the internal clock" tree.end tree.end tree "SRCR" base ad:0xE6150000 group.long 0x0++0x3B line.long 0x0 "SRCR0,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x0 31. "ocv3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 30. "ocv2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 29. "ocv1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 28. "ocv0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 27. "imppsc0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 26. "impdma0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 25. "imp1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 24. "imp0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 23. "spmc0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x0 22. "impcnn0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 21. "radsp1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 20. "radsp0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 19. "isp3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 18. "isp2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 17. "isp1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 16. "isp0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 14. "cle3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 13. "cle2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x0 12. "cle1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 11. "cle0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 10. "umfl1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 9. "umfl0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 8. "smps1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 2. "disp1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 1. "disp0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x0 0. "rgx,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x4 "SRCR1,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x4 22. "adg,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 21. "spmi1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 20. "spmi0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 19. "ipmmuir,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 18. "impslv,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 17. "impldmam,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 16. "impdta,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 9. "spmc1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 8. "impcnn1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x4 7. "ocv5,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 6. "imppsc1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 5. "impdma1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 4. "imp3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 3. "imp2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 2. "spmc2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 1. "impcnn2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x4 0. "ocv4,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x8 "SRCR2,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x8 16. "avb5,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x8 15. "avb4,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x8 14. "avb3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x8 13. "avb2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x8 12. "avb1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x8 11. "avb0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0xC "SRCR3,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0xC 31. "csi4lnk0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0xC 30. "csd,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0xC 29. "cr0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0xC 28. "canfd,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0xC 14. "ocv7,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0xC 13. "ocv6,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x10 "SRCR4,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x10 15. "dsitxlink0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to.." "0,1" bitfld.long 0x10 14. "doc2ch,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x10 13. "ipmmuvi1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x10 12. "ipmmuvi0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x10 11. "dis0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x10 6. "dbs1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x10 5. "dbs0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x10 4. "dbprend,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x10 3. "dbplend,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x10 2. "csi4lnk3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x10 1. "csi4lnk2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x10 0. "csi4lnk1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x14 "SRCR5,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." rbitfld.long 0x14 31. "intap,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 30. "ims1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 29. "ims0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 28. "imr3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 27. "imr2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 26. "imr1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 25. "imr0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 24. "i2c6,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 23. "i2c5,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline rbitfld.long 0x14 22. "i2c4,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 21. "i2c3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 20. "i2c2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 19. "i2c1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 18. "i2c0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 17. "hscif3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x14 16. "hscif2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x14 15. "hscif1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x14 14. "hscif0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x14 13. "fray,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x14 9. "fcpvd1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x14 8. "fcpvd0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x14 7. "fcpcs,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x18 "SRCR6,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x18 31. "rtdm1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 30. "rtdm0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 29. "rpc,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 28. "pwm0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 26.--27. "pci23,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1,2,3" bitfld.long 0x18 24.--25. "pci01,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1,2,3" bitfld.long 0x18 23. "msi5,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 22. "msi4,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 21. "msi3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x18 20. "msi2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 19. "msi1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 18. "msi0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 17. "mfi,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 16. "iv1es,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" hexmask.long.byte 0x18 12.--15. 1. "ispcs,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." bitfld.long 0x18 11. "irqc,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 10. "ipmmuvip1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 9. "ipmmuvip0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x18 8. "inttp,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 7. "ipmmuvc,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 6. "ipmmurt1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 5. "ipmmurt0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 4. "ipmmupv0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 3. "ipmmumm,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 2. "ipmmuds1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 1. "ipmmuds0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x18 0. "ipc,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x1C "SRCR7,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x1C 31. "vin01,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 30. "vin00,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 29. "vcp4l,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 18. "tpu0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 17. "tmu4,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 16. "tmu3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 15. "tmu2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 14. "tmu1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 13. "tmu0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x1C 12. "bkbuf,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 11. "sysram0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 10. "sydm2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 9. "sydm1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 8. "stat,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 7. "secrom,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 6. "sdhi0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 5. "scif4,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 4. "scif3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x1C 3. "scif1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 2. "scif0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 1. "rtdm3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x1C 0. "rtdm2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x20 "SRCR8,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x20 31. "vspd1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 30. "vspd0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 29. "vin37,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 28. "vin36,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 27. "vin35,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 26. "vin34,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 25. "vin33,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 24. "vin32,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 23. "vin31,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x20 22. "vin30,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 21. "vin27,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 20. "vin26,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 19. "vin25,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 18. "vin24,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 17. "vin23,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 16. "vin22,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 15. "vin21,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 14. "vin20,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x20 13. "vin17,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 12. "vin16,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 11. "vin15,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 10. "vin14,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 9. "vin13,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 8. "vin12,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 7. "vin11,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 6. "vin10,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 5. "vin07,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x20 4. "vin06,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 3. "vin05,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 2. "vin04,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 1. "vin03,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x20 0. "vin02,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x24 "SRCR9,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x24 20. "ucmt,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 19. "tsc,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 18. "pfc3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 17. "pfc2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 16. "pfc1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 15. "pfc0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 14. "ecmtop,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 13. "cmt3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 12. "cmt2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x24 11. "cmt1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 10. "cmt0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 8.--9. "aps0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1,2,3" bitfld.long 0x24 7. "wdt,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 6. "wcrc3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 5. "wcrc2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 4. "wcrc1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x24 3. "wcrc0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x28 "SRCR10,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x28 31. "vspx3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x28 30. "vspx2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x28 29. "vspx1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x28 28. "vspx0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x28 27. "radsp1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x28 25. "radsp0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x28 24. "rgc,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x28 23. "rgxb,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x28 22. "CA76_10,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x28 17. "CA76_00,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x2C "SRCR11,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." rbitfld.long 0x2C 30. "CA76_01,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 29. "CA76_11,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 28. "swdt,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" rbitfld.long 0x2C 26. "rgxpvc,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 25. "rgxpvde,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 24. "pci23,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 23. "pci23,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 22. "pci01,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 21. "pci01,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x2C 20. "lbs,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 19. "intap,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 18. "fray,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 17. "fbc,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x2C 16. "CA76_02,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" hexmask.long.word 0x2C 0.--15. 1. "CA76_12,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." line.long 0x30 "SRCR12,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x30 30. "fso,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 22. "scmt,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 21. "pfc33,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 20. "pfc32,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 19. "pfc31,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 18. "pfc23,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 17. "pfc22,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 16. "pfc21,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 15. "pfc13,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x30 14. "pfc12,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 13. "pfc11,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 12. "pfc03,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 11. "pfc02,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 10. "pfc01,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 9. "wwdt9,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 8. "wwdt8,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 7. "wwdt7,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 6. "wwdt6,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x30 5. "wwdt5,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 4. "wwdt4,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 3. "wwdt3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 2. "wwdt2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 1. "wwdt1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x30 0. "wwdt0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x34 "SRCR13,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x34 31. "pfc1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 30. "pfc0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 28.--29. "fuse,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1,2,3" bitfld.long 0x34 27. "wwdt9,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 26. "wwdt8,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 25. "wwdt7,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 24. "wwdt6,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 23. "wwdt5,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 22. "wwdt4,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x34 21. "wwdt3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 20. "wwdt2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 19. "wwdt1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 18. "wwdt0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 17. "syncg,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 15.--16. "reset,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1,2,3" bitfld.long 0x34 14. "lpd,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 11. "dbe,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x34 4. "mti,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" line.long 0x38 "SRCR14,Software Reset Register (SRCRn (n = 0 to 23)) ---> Same register configuration as previous Gen3 series." bitfld.long 0x38 27. "ckmir20,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 24. "ckmir10,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 14. "ckmdd1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 13. "ckmdd0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 12. "ckmmm,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 11. "ckmir0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 10. "ckmvip,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 9. "ckmvc,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 8. "ckmvio,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" newline bitfld.long 0x38 7. "ckmpe1,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 6. "ckmpe0,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 5. "ckmrt,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 4. "ckm3dg,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 3. "sys,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 2. "swc,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 1. "pfc3,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" bitfld.long 0x38 0. "pfc2,Each SRCRn is a 32-bit readable/writable register. Each bit is assigned to a module in the chip. Writing 1 to the bit resets the corresponding module. Writing 1 to a given the bit of the software reset clearing register (SRSTCLRn (n = 0 to 23)).." "0,1" tree.end tree "SWDT" base ad:0xE6030000 group.long 0x0++0xB line.long 0x0 "SWTCNT,SWTCNT is a 16-bit readable/writable register that increments on the selected clock. When an overflow occurs. it generates a reset. The SWTCNT counter is initialized to H'F488 by a power-on reset." hexmask.long.word 0x0 16.--31. 1. "CODE_VAL1,Code value 1" hexmask.long.word 0x0 0.--15. 1. "SWTCNT,Timer Counter Bits" line.long 0x4 "SWTCSRA,SWTCSRA is an 8-bit readable/writable register composed of bits to select the clock used for the count. overflow flag. and enable bit." hexmask.long.tbyte 0x4 8.--31. 1. "CODE_VAL2,Code value 2" bitfld.long 0x4 7. "TME,Starts and stops timer operation." "0: Timer disabled: Count-up stops and SWTCNT value..,1: Timer enabled" newline rbitfld.long 0x4 5. "WRFLG,Write Status Flag" "0,1" bitfld.long 0x4 4. "WOVF,Indicates that the SWTCNT has overflowed. This bit isn't initialized by a generated reset by an overflow of section 77. RCLK Watchdog Timer (RWDT) and System Watchdog Timer. Write 0 to this bit before using the System Watchdog Timer." "0: No overflow,1: SWTCNT has overflowed" newline bitfld.long 0x4 3. "WOVFE,Overflow Interrupt Disable/Enable" "0: Disables interrupts due to overflow,1: Enables interrupts due to overflow" bitfld.long 0x4 0.--2. "CKS0,RTC Clock Select" "0: OSCCLK,1: OSCCLK /4,?,?,?,?,?,?" line.long 0x8 "SWTCSRB,SWTCSRB is an 8-bit readable/writable register composed of bits to select the clock used for the count." hexmask.long.tbyte 0x8 8.--31. 1. "CODE_VAL3,Code value 3" hexmask.long.byte 0x8 0.--5. 1. "CKS1,OSCCLK Select for OSCCLK Select Expanded Mode" tree.end tree "SYSC" base ad:0x0 tree "SYSC_0" base ad:0xE6180000 rgroup.long 0x0++0x3 line.long 0x0 "SYSCSR,SYSC Status Register" bitfld.long 0x0 0.--1. "BUSY,Indicates whether the SYSC is processing Power-ON or Power-OFF sequence." "0: Processing Power-ON or OFF sequence,?,?,?" group.long 0x10++0x7 line.long 0x0 "SYSCPTCSR,Protect Control/Status Register" bitfld.long 0x0 2. "EIEI,Write access protection Error Interrupt request Enable for INTC." "0: Disable error interrupt request for INTC,1: Enable error interrupt request for INTC" bitfld.long 0x0 1. "EIE,Write access protection Error Interrupt request Enable for ECM (FuSa)." "0: Disable error interrupt request for ECM,1: Enable error interrupt request for ECM" newline bitfld.long 0x0 0. "ERR,Indicates Write access protection Error status." "0: Not detected Write access protection error,1: Detected Write access protection error" line.long 0x4 "SYSCPTERADR,Protect Error Address Register" bitfld.long 0x4 16. "CLR,Write access protection error address clear" "0,1" hexmask.long.word 0x4 0.--15. 1. "ADR,First Write access protection error address." group.long 0x20++0x7 line.long 0x0 "SYSCRDNCSR,HW Redundant Error Control/Status Register" hexmask.long.word 0x0 16.--31. 1. "EIE,HW Redundant Error Interrupt Enable" hexmask.long.word 0x0 0.--15. 1. "ERR,HW Redundant Error Status" line.long 0x4 "SYSCRDNIR,HW Redundant Error Injection Register" hexmask.long.word 0x4 0.--15. 1. "ERIN,Injects HW Redundant Error" group.long 0x30++0x3 line.long 0x0 "SYSCAPBACR,APB BUS Access Check Register" hexmask.long 0x0 0.--31. 1. "VAL,APB BUS Access Check Register for FuSa" rgroup.long 0x800++0xF line.long 0x0 "SYSCPONSR0,Power-ON Status Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON status for PDR00-31 power domains." line.long 0x4 "SYSCPONSR1,Power-ON Status Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON status for PDR32-63 power domains." line.long 0x8 "SYSCPOFFSR0,Power-OFF Status Register 0" hexmask.long 0x8 0.--31. 1. "PDR,Power-OFF Status for PDR31-00 power domains." line.long 0xC "SYSCPOFFSR1,Power-OFF Status Register 1" hexmask.long 0xC 0.--31. 1. "PDR,Power-OFF Status for PDR63-32 power domains." group.long 0x810++0x7 line.long 0x0 "SYSCISCR0,Interrupt Status/Clear Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt status for PDR00-31 power domains." line.long 0x4 "SYSCISCR1,Interrupt Status/Clear Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt status for PDR32-63 power domains." group.long 0x820++0x7 line.long 0x0 "SYSCIER0,Interrupt Enable Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt Enable for PDR00-31 power domains." line.long 0x4 "SYSCIER1,Interrupt Enable Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt Enable for PDR32-63 power domains." group.long 0x830++0x7 line.long 0x0 "SYSCIMR0,Interrupt Mask Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Mask complete interrupt request to INTC for PDR00-31 power domains." line.long 0x4 "SYSCIMR1,Interrupt Mask Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Mask complete interrupt request to INTC for PDR32-63 power domains." group.long 0x860++0x1F line.long 0x0 "SYSCISOEHSR0,Isolation Error High Status/Clear Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Isolation Error High Status/Clear" line.long 0x4 "SYSCISOEHSR1,Isolation Error High Status/Clear Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Isolation Error High Status/Clear" line.long 0x8 "SYSCISOELSR0,Isolation Error Low Status/Clear Register 0" hexmask.long 0x8 0.--31. 1. "PDR,Isolation Error Low Status/Clear" line.long 0xC "SYSCISOELSR1,Isolation Error Low Status/Clear Register 1" hexmask.long 0xC 0.--31. 1. "PDR,Isolation Error Low Status/Clear" line.long 0x10 "SYSCISOEHIR0,Isolation Error High Injection Register 0" hexmask.long 0x10 0.--31. 1. "PDR,Isolation Error High Injection for PDR00-31" line.long 0x14 "SYSCISOEHIR1,Isolation Error High Injection Register 1" hexmask.long 0x14 0.--31. 1. "PDR,Isolation Error High Injection for PDR32-63" line.long 0x18 "SYSCISOELIR0,Isolation Error Low Injection Register 0" hexmask.long 0x18 0.--31. 1. "PDR,Isolation Error Low Injection for PDR00-31" line.long 0x1C "SYSCISOELIR1,Isolation Error Low Injection Register 1" hexmask.long 0x1C 0.--31. 1. "PDR,Isolation Error Low Injection for PDR32-63" rgroup.long 0x1000++0x3 line.long 0x0 "PDRSR0,Power Domain Status Register 0" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1040++0x3 line.long 0x0 "PDRSR1,Power Domain Status Register 1" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1080++0x3 line.long 0x0 "PDRSR2,Power Domain Status Register 2" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x10C0++0x3 line.long 0x0 "PDRSR3,Power Domain Status Register 3" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1100++0x3 line.long 0x0 "PDRSR4,Power Domain Status Register 4" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1140++0x3 line.long 0x0 "PDRSR5,Power Domain Status Register 5" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1180++0x3 line.long 0x0 "PDRSR6,Power Domain Status Register 6" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x11C0++0x3 line.long 0x0 "PDRSR7,Power Domain Status Register 7" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1200++0x3 line.long 0x0 "PDRSR8,Power Domain Status Register 8" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1240++0x3 line.long 0x0 "PDRSR9,Power Domain Status Register 9" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1280++0x3 line.long 0x0 "PDRSR10,Power Domain Status Register 10" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x12C0++0x3 line.long 0x0 "PDRSR11,Power Domain Status Register 11" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1300++0x3 line.long 0x0 "PDRSR12,Power Domain Status Register 12" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1340++0x3 line.long 0x0 "PDRSR13,Power Domain Status Register 13" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1380++0x3 line.long 0x0 "PDRSR14,Power Domain Status Register 14" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x13C0++0x3 line.long 0x0 "PDRSR15,Power Domain Status Register 15" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1400++0x3 line.long 0x0 "PDRSR16,Power Domain Status Register 16" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1440++0x3 line.long 0x0 "PDRSR17,Power Domain Status Register 17" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1480++0x3 line.long 0x0 "PDRSR18,Power Domain Status Register 18" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x14C0++0x3 line.long 0x0 "PDRSR19,Power Domain Status Register 19" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1500++0x3 line.long 0x0 "PDRSR20,Power Domain Status Register 20" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1540++0x3 line.long 0x0 "PDRSR21,Power Domain Status Register 21" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1580++0x3 line.long 0x0 "PDRSR22,Power Domain Status Register 22" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x15C0++0x3 line.long 0x0 "PDRSR23,Power Domain Status Register 23" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1600++0x3 line.long 0x0 "PDRSR24,Power Domain Status Register 24" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1640++0x3 line.long 0x0 "PDRSR25,Power Domain Status Register 25" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1680++0x3 line.long 0x0 "PDRSR26,Power Domain Status Register 26" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x16C0++0x3 line.long 0x0 "PDRSR27,Power Domain Status Register 27" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1700++0x3 line.long 0x0 "PDRSR28,Power Domain Status Register 28" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1740++0x3 line.long 0x0 "PDRSR29,Power Domain Status Register 29" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1780++0x3 line.long 0x0 "PDRSR30,Power Domain Status Register 30" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x17C0++0x3 line.long 0x0 "PDRSR31,Power Domain Status Register 31" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1800++0x3 line.long 0x0 "PDRSR32,Power Domain Status Register 32" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1840++0x3 line.long 0x0 "PDRSR33,Power Domain Status Register 33" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1880++0x3 line.long 0x0 "PDRSR34,Power Domain Status Register 34" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x18C0++0x3 line.long 0x0 "PDRSR35,Power Domain Status Register 35" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1900++0x3 line.long 0x0 "PDRSR36,Power Domain Status Register 36" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1940++0x3 line.long 0x0 "PDRSR37,Power Domain Status Register 37" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1980++0x3 line.long 0x0 "PDRSR38,Power Domain Status Register 38" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x19C0++0x3 line.long 0x0 "PDRSR39,Power Domain Status Register 39" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A00++0x3 line.long 0x0 "PDRSR40,Power Domain Status Register 40" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A40++0x3 line.long 0x0 "PDRSR41,Power Domain Status Register 41" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A80++0x3 line.long 0x0 "PDRSR42,Power Domain Status Register 42" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1AC0++0x3 line.long 0x0 "PDRSR43,Power Domain Status Register 43" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B00++0x3 line.long 0x0 "PDRSR44,Power Domain Status Register 44" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B40++0x3 line.long 0x0 "PDRSR45,Power Domain Status Register 45" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B80++0x3 line.long 0x0 "PDRSR46,Power Domain Status Register 46" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1BC0++0x3 line.long 0x0 "PDRSR47,Power Domain Status Register 47" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C00++0x3 line.long 0x0 "PDRSR48,Power Domain Status Register 48" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C40++0x3 line.long 0x0 "PDRSR49,Power Domain Status Register 49" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C80++0x3 line.long 0x0 "PDRSR50,Power Domain Status Register 50" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1CC0++0x3 line.long 0x0 "PDRSR51,Power Domain Status Register 51" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D00++0x3 line.long 0x0 "PDRSR52,Power Domain Status Register 52" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D40++0x3 line.long 0x0 "PDRSR53,Power Domain Status Register 53" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D80++0x3 line.long 0x0 "PDRSR54,Power Domain Status Register 54" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1DC0++0x3 line.long 0x0 "PDRSR55,Power Domain Status Register 55" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E00++0x3 line.long 0x0 "PDRSR56,Power Domain Status Register 56" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E40++0x3 line.long 0x0 "PDRSR57,Power Domain Status Register 57" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E80++0x3 line.long 0x0 "PDRSR58,Power Domain Status Register 58" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1EC0++0x3 line.long 0x0 "PDRSR59,Power Domain Status Register 59" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F00++0x3 line.long 0x0 "PDRSR60,Power Domain Status Register 60" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F40++0x3 line.long 0x0 "PDRSR61,Power Domain Status Register 61" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F80++0x3 line.long 0x0 "PDRSR62,Power Domain Status Register 62" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1FC0++0x3 line.long 0x0 "PDRSR63,Power Domain Status Register 63" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" wgroup.long 0x1004++0x3 line.long 0x0 "PDRONCR0,Power Domain Power-ON Control Register 0" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1044++0x3 line.long 0x0 "PDRONCR1,Power Domain Power-ON Control Register 1" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1084++0x3 line.long 0x0 "PDRONCR2,Power Domain Power-ON Control Register 2" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x10C4++0x3 line.long 0x0 "PDRONCR3,Power Domain Power-ON Control Register 3" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1104++0x3 line.long 0x0 "PDRONCR4,Power Domain Power-ON Control Register 4" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1144++0x3 line.long 0x0 "PDRONCR5,Power Domain Power-ON Control Register 5" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1184++0x3 line.long 0x0 "PDRONCR6,Power Domain Power-ON Control Register 6" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x11C4++0x3 line.long 0x0 "PDRONCR7,Power Domain Power-ON Control Register 7" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1204++0x3 line.long 0x0 "PDRONCR8,Power Domain Power-ON Control Register 8" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1244++0x3 line.long 0x0 "PDRONCR9,Power Domain Power-ON Control Register 9" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1284++0x3 line.long 0x0 "PDRONCR10,Power Domain Power-ON Control Register 10" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x12C4++0x3 line.long 0x0 "PDRONCR11,Power Domain Power-ON Control Register 11" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1304++0x3 line.long 0x0 "PDRONCR12,Power Domain Power-ON Control Register 12" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1344++0x3 line.long 0x0 "PDRONCR13,Power Domain Power-ON Control Register 13" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1384++0x3 line.long 0x0 "PDRONCR14,Power Domain Power-ON Control Register 14" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x13C4++0x3 line.long 0x0 "PDRONCR15,Power Domain Power-ON Control Register 15" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1404++0x3 line.long 0x0 "PDRONCR16,Power Domain Power-ON Control Register 16" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1444++0x3 line.long 0x0 "PDRONCR17,Power Domain Power-ON Control Register 17" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1484++0x3 line.long 0x0 "PDRONCR18,Power Domain Power-ON Control Register 18" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x14C4++0x3 line.long 0x0 "PDRONCR19,Power Domain Power-ON Control Register 19" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1504++0x3 line.long 0x0 "PDRONCR20,Power Domain Power-ON Control Register 20" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1544++0x3 line.long 0x0 "PDRONCR21,Power Domain Power-ON Control Register 21" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1584++0x3 line.long 0x0 "PDRONCR22,Power Domain Power-ON Control Register 22" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x15C4++0x3 line.long 0x0 "PDRONCR23,Power Domain Power-ON Control Register 23" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1604++0x3 line.long 0x0 "PDRONCR24,Power Domain Power-ON Control Register 24" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1644++0x3 line.long 0x0 "PDRONCR25,Power Domain Power-ON Control Register 25" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1684++0x3 line.long 0x0 "PDRONCR26,Power Domain Power-ON Control Register 26" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x16C4++0x3 line.long 0x0 "PDRONCR27,Power Domain Power-ON Control Register 27" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1704++0x3 line.long 0x0 "PDRONCR28,Power Domain Power-ON Control Register 28" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1744++0x3 line.long 0x0 "PDRONCR29,Power Domain Power-ON Control Register 29" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1784++0x3 line.long 0x0 "PDRONCR30,Power Domain Power-ON Control Register 30" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x17C4++0x3 line.long 0x0 "PDRONCR31,Power Domain Power-ON Control Register 31" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1804++0x3 line.long 0x0 "PDRONCR32,Power Domain Power-ON Control Register 32" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1844++0x3 line.long 0x0 "PDRONCR33,Power Domain Power-ON Control Register 33" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1884++0x3 line.long 0x0 "PDRONCR34,Power Domain Power-ON Control Register 34" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x18C4++0x3 line.long 0x0 "PDRONCR35,Power Domain Power-ON Control Register 35" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1904++0x3 line.long 0x0 "PDRONCR36,Power Domain Power-ON Control Register 36" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1944++0x3 line.long 0x0 "PDRONCR37,Power Domain Power-ON Control Register 37" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1984++0x3 line.long 0x0 "PDRONCR38,Power Domain Power-ON Control Register 38" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x19C4++0x3 line.long 0x0 "PDRONCR39,Power Domain Power-ON Control Register 39" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A04++0x3 line.long 0x0 "PDRONCR40,Power Domain Power-ON Control Register 40" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A44++0x3 line.long 0x0 "PDRONCR41,Power Domain Power-ON Control Register 41" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A84++0x3 line.long 0x0 "PDRONCR42,Power Domain Power-ON Control Register 42" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1AC4++0x3 line.long 0x0 "PDRONCR43,Power Domain Power-ON Control Register 43" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B04++0x3 line.long 0x0 "PDRONCR44,Power Domain Power-ON Control Register 44" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B44++0x3 line.long 0x0 "PDRONCR45,Power Domain Power-ON Control Register 45" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B84++0x3 line.long 0x0 "PDRONCR46,Power Domain Power-ON Control Register 46" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1BC4++0x3 line.long 0x0 "PDRONCR47,Power Domain Power-ON Control Register 47" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C04++0x3 line.long 0x0 "PDRONCR48,Power Domain Power-ON Control Register 48" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C44++0x3 line.long 0x0 "PDRONCR49,Power Domain Power-ON Control Register 49" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C84++0x3 line.long 0x0 "PDRONCR50,Power Domain Power-ON Control Register 50" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1CC4++0x3 line.long 0x0 "PDRONCR51,Power Domain Power-ON Control Register 51" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D04++0x3 line.long 0x0 "PDRONCR52,Power Domain Power-ON Control Register 52" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D44++0x3 line.long 0x0 "PDRONCR53,Power Domain Power-ON Control Register 53" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D84++0x3 line.long 0x0 "PDRONCR54,Power Domain Power-ON Control Register 54" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1DC4++0x3 line.long 0x0 "PDRONCR55,Power Domain Power-ON Control Register 55" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E04++0x3 line.long 0x0 "PDRONCR56,Power Domain Power-ON Control Register 56" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E44++0x3 line.long 0x0 "PDRONCR57,Power Domain Power-ON Control Register 57" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E84++0x3 line.long 0x0 "PDRONCR58,Power Domain Power-ON Control Register 58" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1EC4++0x3 line.long 0x0 "PDRONCR59,Power Domain Power-ON Control Register 59" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F04++0x3 line.long 0x0 "PDRONCR60,Power Domain Power-ON Control Register 60" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F44++0x3 line.long 0x0 "PDRONCR61,Power Domain Power-ON Control Register 61" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F84++0x3 line.long 0x0 "PDRONCR62,Power Domain Power-ON Control Register 62" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1FC4++0x3 line.long 0x0 "PDRONCR63,Power Domain Power-ON Control Register 63" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1008++0x3 line.long 0x0 "PDROFFCR0,Power Domain Power-OFF Control Register 0" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1048++0x3 line.long 0x0 "PDROFFCR1,Power Domain Power-OFF Control Register 1" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1088++0x3 line.long 0x0 "PDROFFCR2,Power Domain Power-OFF Control Register 2" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x10C8++0x3 line.long 0x0 "PDROFFCR3,Power Domain Power-OFF Control Register 3" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1108++0x3 line.long 0x0 "PDROFFCR4,Power Domain Power-OFF Control Register 4" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1148++0x3 line.long 0x0 "PDROFFCR5,Power Domain Power-OFF Control Register 5" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1188++0x3 line.long 0x0 "PDROFFCR6,Power Domain Power-OFF Control Register 6" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x11C8++0x3 line.long 0x0 "PDROFFCR7,Power Domain Power-OFF Control Register 7" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1208++0x3 line.long 0x0 "PDROFFCR8,Power Domain Power-OFF Control Register 8" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1248++0x3 line.long 0x0 "PDROFFCR9,Power Domain Power-OFF Control Register 9" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1288++0x3 line.long 0x0 "PDROFFCR10,Power Domain Power-OFF Control Register 10" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x12C8++0x3 line.long 0x0 "PDROFFCR11,Power Domain Power-OFF Control Register 11" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1308++0x3 line.long 0x0 "PDROFFCR12,Power Domain Power-OFF Control Register 12" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1348++0x3 line.long 0x0 "PDROFFCR13,Power Domain Power-OFF Control Register 13" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1388++0x3 line.long 0x0 "PDROFFCR14,Power Domain Power-OFF Control Register 14" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x13C8++0x3 line.long 0x0 "PDROFFCR15,Power Domain Power-OFF Control Register 15" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1408++0x3 line.long 0x0 "PDROFFCR16,Power Domain Power-OFF Control Register 16" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1448++0x3 line.long 0x0 "PDROFFCR17,Power Domain Power-OFF Control Register 17" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1488++0x3 line.long 0x0 "PDROFFCR18,Power Domain Power-OFF Control Register 18" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x14C8++0x3 line.long 0x0 "PDROFFCR19,Power Domain Power-OFF Control Register 19" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1508++0x3 line.long 0x0 "PDROFFCR20,Power Domain Power-OFF Control Register 20" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1548++0x3 line.long 0x0 "PDROFFCR21,Power Domain Power-OFF Control Register 21" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1588++0x3 line.long 0x0 "PDROFFCR22,Power Domain Power-OFF Control Register 22" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x15C8++0x3 line.long 0x0 "PDROFFCR23,Power Domain Power-OFF Control Register 23" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1608++0x3 line.long 0x0 "PDROFFCR24,Power Domain Power-OFF Control Register 24" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1648++0x3 line.long 0x0 "PDROFFCR25,Power Domain Power-OFF Control Register 25" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1688++0x3 line.long 0x0 "PDROFFCR26,Power Domain Power-OFF Control Register 26" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x16C8++0x3 line.long 0x0 "PDROFFCR27,Power Domain Power-OFF Control Register 27" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1708++0x3 line.long 0x0 "PDROFFCR28,Power Domain Power-OFF Control Register 28" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1748++0x3 line.long 0x0 "PDROFFCR29,Power Domain Power-OFF Control Register 29" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1788++0x3 line.long 0x0 "PDROFFCR30,Power Domain Power-OFF Control Register 30" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x17C8++0x3 line.long 0x0 "PDROFFCR31,Power Domain Power-OFF Control Register 31" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1808++0x3 line.long 0x0 "PDROFFCR32,Power Domain Power-OFF Control Register 32" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1848++0x3 line.long 0x0 "PDROFFCR33,Power Domain Power-OFF Control Register 33" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1888++0x3 line.long 0x0 "PDROFFCR34,Power Domain Power-OFF Control Register 34" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x18C8++0x3 line.long 0x0 "PDROFFCR35,Power Domain Power-OFF Control Register 35" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1908++0x3 line.long 0x0 "PDROFFCR36,Power Domain Power-OFF Control Register 36" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1948++0x3 line.long 0x0 "PDROFFCR37,Power Domain Power-OFF Control Register 37" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1988++0x3 line.long 0x0 "PDROFFCR38,Power Domain Power-OFF Control Register 38" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x19C8++0x3 line.long 0x0 "PDROFFCR39,Power Domain Power-OFF Control Register 39" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A08++0x3 line.long 0x0 "PDROFFCR40,Power Domain Power-OFF Control Register 40" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A48++0x3 line.long 0x0 "PDROFFCR41,Power Domain Power-OFF Control Register 41" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A88++0x3 line.long 0x0 "PDROFFCR42,Power Domain Power-OFF Control Register 42" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1AC8++0x3 line.long 0x0 "PDROFFCR43,Power Domain Power-OFF Control Register 43" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B08++0x3 line.long 0x0 "PDROFFCR44,Power Domain Power-OFF Control Register 44" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B48++0x3 line.long 0x0 "PDROFFCR45,Power Domain Power-OFF Control Register 45" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B88++0x3 line.long 0x0 "PDROFFCR46,Power Domain Power-OFF Control Register 46" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1BC8++0x3 line.long 0x0 "PDROFFCR47,Power Domain Power-OFF Control Register 47" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C08++0x3 line.long 0x0 "PDROFFCR48,Power Domain Power-OFF Control Register 48" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C48++0x3 line.long 0x0 "PDROFFCR49,Power Domain Power-OFF Control Register 49" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C88++0x3 line.long 0x0 "PDROFFCR50,Power Domain Power-OFF Control Register 50" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1CC8++0x3 line.long 0x0 "PDROFFCR51,Power Domain Power-OFF Control Register 51" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D08++0x3 line.long 0x0 "PDROFFCR52,Power Domain Power-OFF Control Register 52" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D48++0x3 line.long 0x0 "PDROFFCR53,Power Domain Power-OFF Control Register 53" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D88++0x3 line.long 0x0 "PDROFFCR54,Power Domain Power-OFF Control Register 54" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1DC8++0x3 line.long 0x0 "PDROFFCR55,Power Domain Power-OFF Control Register 55" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E08++0x3 line.long 0x0 "PDROFFCR56,Power Domain Power-OFF Control Register 56" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E48++0x3 line.long 0x0 "PDROFFCR57,Power Domain Power-OFF Control Register 57" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E88++0x3 line.long 0x0 "PDROFFCR58,Power Domain Power-OFF Control Register 58" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1EC8++0x3 line.long 0x0 "PDROFFCR59,Power Domain Power-OFF Control Register 59" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F08++0x3 line.long 0x0 "PDROFFCR60,Power Domain Power-OFF Control Register 60" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F48++0x3 line.long 0x0 "PDROFFCR61,Power Domain Power-OFF Control Register 61" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F88++0x3 line.long 0x0 "PDROFFCR62,Power Domain Power-OFF Control Register 62" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1FC8++0x3 line.long 0x0 "PDROFFCR63,Power Domain Power-OFF Control Register 63" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" group.long 0x3000++0x17 line.long 0x0 "SYSCD0WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD0WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD0WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD0WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD0WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD0WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." group.long 0x3020++0x17 line.long 0x0 "SYSCD1WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD1WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD1WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD1WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD1WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD1WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." group.long 0x3040++0x17 line.long 0x0 "SYSCD2WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD2WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD2WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD2WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD2WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD2WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." group.long 0x3060++0x17 line.long 0x0 "SYSCD3WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD3WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD3WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD3WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD3WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD3WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." tree.end tree "SYSC_1" base ad:0xE6184000 rgroup.long 0x0++0x3 line.long 0x0 "SYSCSR,SYSC Status Register" bitfld.long 0x0 0.--1. "BUSY,Indicates whether the SYSC is processing Power-ON or Power-OFF sequence." "0: Processing Power-ON or OFF sequence,?,?,?" group.long 0x10++0x7 line.long 0x0 "SYSCPTCSR,Protect Control/Status Register" bitfld.long 0x0 2. "EIEI,Write access protection Error Interrupt request Enable for INTC." "0: Disable error interrupt request for INTC,1: Enable error interrupt request for INTC" bitfld.long 0x0 1. "EIE,Write access protection Error Interrupt request Enable for ECM (FuSa)." "0: Disable error interrupt request for ECM,1: Enable error interrupt request for ECM" newline bitfld.long 0x0 0. "ERR,Indicates Write access protection Error status." "0: Not detected Write access protection error,1: Detected Write access protection error" line.long 0x4 "SYSCPTERADR,Protect Error Address Register" bitfld.long 0x4 16. "CLR,Write access protection error address clear" "0,1" hexmask.long.word 0x4 0.--15. 1. "ADR,First Write access protection error address." group.long 0x20++0x7 line.long 0x0 "SYSCRDNCSR,HW Redundant Error Control/Status Register" hexmask.long.word 0x0 16.--31. 1. "EIE,HW Redundant Error Interrupt Enable" hexmask.long.word 0x0 0.--15. 1. "ERR,HW Redundant Error Status" line.long 0x4 "SYSCRDNIR,HW Redundant Error Injection Register" hexmask.long.word 0x4 0.--15. 1. "ERIN,Injects HW Redundant Error" group.long 0x30++0x3 line.long 0x0 "SYSCAPBACR,APB BUS Access Check Register" hexmask.long 0x0 0.--31. 1. "VAL,APB BUS Access Check Register for FuSa" rgroup.long 0x800++0xF line.long 0x0 "SYSCPONSR0,Power-ON Status Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON status for PDR00-31 power domains." line.long 0x4 "SYSCPONSR1,Power-ON Status Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON status for PDR32-63 power domains." line.long 0x8 "SYSCPOFFSR0,Power-OFF Status Register 0" hexmask.long 0x8 0.--31. 1. "PDR,Power-OFF Status for PDR31-00 power domains." line.long 0xC "SYSCPOFFSR1,Power-OFF Status Register 1" hexmask.long 0xC 0.--31. 1. "PDR,Power-OFF Status for PDR63-32 power domains." group.long 0x810++0x7 line.long 0x0 "SYSCISCR0,Interrupt Status/Clear Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt status for PDR00-31 power domains." line.long 0x4 "SYSCISCR1,Interrupt Status/Clear Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt status for PDR32-63 power domains." group.long 0x820++0x7 line.long 0x0 "SYSCIER0,Interrupt Enable Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt Enable for PDR00-31 power domains." line.long 0x4 "SYSCIER1,Interrupt Enable Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt Enable for PDR32-63 power domains." group.long 0x830++0x7 line.long 0x0 "SYSCIMR0,Interrupt Mask Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Mask complete interrupt request to INTC for PDR00-31 power domains." line.long 0x4 "SYSCIMR1,Interrupt Mask Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Mask complete interrupt request to INTC for PDR32-63 power domains." group.long 0x860++0x1F line.long 0x0 "SYSCISOEHSR0,Isolation Error High Status/Clear Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Isolation Error High Status/Clear" line.long 0x4 "SYSCISOEHSR1,Isolation Error High Status/Clear Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Isolation Error High Status/Clear" line.long 0x8 "SYSCISOELSR0,Isolation Error Low Status/Clear Register 0" hexmask.long 0x8 0.--31. 1. "PDR,Isolation Error Low Status/Clear" line.long 0xC "SYSCISOELSR1,Isolation Error Low Status/Clear Register 1" hexmask.long 0xC 0.--31. 1. "PDR,Isolation Error Low Status/Clear" line.long 0x10 "SYSCISOEHIR0,Isolation Error High Injection Register 0" hexmask.long 0x10 0.--31. 1. "PDR,Isolation Error High Injection for PDR00-31" line.long 0x14 "SYSCISOEHIR1,Isolation Error High Injection Register 1" hexmask.long 0x14 0.--31. 1. "PDR,Isolation Error High Injection for PDR32-63" line.long 0x18 "SYSCISOELIR0,Isolation Error Low Injection Register 0" hexmask.long 0x18 0.--31. 1. "PDR,Isolation Error Low Injection for PDR00-31" line.long 0x1C "SYSCISOELIR1,Isolation Error Low Injection Register 1" hexmask.long 0x1C 0.--31. 1. "PDR,Isolation Error Low Injection for PDR32-63" rgroup.long 0x1000++0x3 line.long 0x0 "PDRSR0,Power Domain Status Register 0" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1040++0x3 line.long 0x0 "PDRSR1,Power Domain Status Register 1" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1080++0x3 line.long 0x0 "PDRSR2,Power Domain Status Register 2" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x10C0++0x3 line.long 0x0 "PDRSR3,Power Domain Status Register 3" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1100++0x3 line.long 0x0 "PDRSR4,Power Domain Status Register 4" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1140++0x3 line.long 0x0 "PDRSR5,Power Domain Status Register 5" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1180++0x3 line.long 0x0 "PDRSR6,Power Domain Status Register 6" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x11C0++0x3 line.long 0x0 "PDRSR7,Power Domain Status Register 7" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1200++0x3 line.long 0x0 "PDRSR8,Power Domain Status Register 8" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1240++0x3 line.long 0x0 "PDRSR9,Power Domain Status Register 9" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1280++0x3 line.long 0x0 "PDRSR10,Power Domain Status Register 10" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x12C0++0x3 line.long 0x0 "PDRSR11,Power Domain Status Register 11" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1300++0x3 line.long 0x0 "PDRSR12,Power Domain Status Register 12" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1340++0x3 line.long 0x0 "PDRSR13,Power Domain Status Register 13" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1380++0x3 line.long 0x0 "PDRSR14,Power Domain Status Register 14" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x13C0++0x3 line.long 0x0 "PDRSR15,Power Domain Status Register 15" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1400++0x3 line.long 0x0 "PDRSR16,Power Domain Status Register 16" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1440++0x3 line.long 0x0 "PDRSR17,Power Domain Status Register 17" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1480++0x3 line.long 0x0 "PDRSR18,Power Domain Status Register 18" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x14C0++0x3 line.long 0x0 "PDRSR19,Power Domain Status Register 19" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1500++0x3 line.long 0x0 "PDRSR20,Power Domain Status Register 20" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1540++0x3 line.long 0x0 "PDRSR21,Power Domain Status Register 21" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1580++0x3 line.long 0x0 "PDRSR22,Power Domain Status Register 22" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x15C0++0x3 line.long 0x0 "PDRSR23,Power Domain Status Register 23" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1600++0x3 line.long 0x0 "PDRSR24,Power Domain Status Register 24" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1640++0x3 line.long 0x0 "PDRSR25,Power Domain Status Register 25" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1680++0x3 line.long 0x0 "PDRSR26,Power Domain Status Register 26" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x16C0++0x3 line.long 0x0 "PDRSR27,Power Domain Status Register 27" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1700++0x3 line.long 0x0 "PDRSR28,Power Domain Status Register 28" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1740++0x3 line.long 0x0 "PDRSR29,Power Domain Status Register 29" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1780++0x3 line.long 0x0 "PDRSR30,Power Domain Status Register 30" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x17C0++0x3 line.long 0x0 "PDRSR31,Power Domain Status Register 31" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1800++0x3 line.long 0x0 "PDRSR32,Power Domain Status Register 32" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1840++0x3 line.long 0x0 "PDRSR33,Power Domain Status Register 33" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1880++0x3 line.long 0x0 "PDRSR34,Power Domain Status Register 34" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x18C0++0x3 line.long 0x0 "PDRSR35,Power Domain Status Register 35" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1900++0x3 line.long 0x0 "PDRSR36,Power Domain Status Register 36" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1940++0x3 line.long 0x0 "PDRSR37,Power Domain Status Register 37" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1980++0x3 line.long 0x0 "PDRSR38,Power Domain Status Register 38" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x19C0++0x3 line.long 0x0 "PDRSR39,Power Domain Status Register 39" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A00++0x3 line.long 0x0 "PDRSR40,Power Domain Status Register 40" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A40++0x3 line.long 0x0 "PDRSR41,Power Domain Status Register 41" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A80++0x3 line.long 0x0 "PDRSR42,Power Domain Status Register 42" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1AC0++0x3 line.long 0x0 "PDRSR43,Power Domain Status Register 43" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B00++0x3 line.long 0x0 "PDRSR44,Power Domain Status Register 44" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B40++0x3 line.long 0x0 "PDRSR45,Power Domain Status Register 45" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B80++0x3 line.long 0x0 "PDRSR46,Power Domain Status Register 46" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1BC0++0x3 line.long 0x0 "PDRSR47,Power Domain Status Register 47" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C00++0x3 line.long 0x0 "PDRSR48,Power Domain Status Register 48" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C40++0x3 line.long 0x0 "PDRSR49,Power Domain Status Register 49" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C80++0x3 line.long 0x0 "PDRSR50,Power Domain Status Register 50" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1CC0++0x3 line.long 0x0 "PDRSR51,Power Domain Status Register 51" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D00++0x3 line.long 0x0 "PDRSR52,Power Domain Status Register 52" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D40++0x3 line.long 0x0 "PDRSR53,Power Domain Status Register 53" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D80++0x3 line.long 0x0 "PDRSR54,Power Domain Status Register 54" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1DC0++0x3 line.long 0x0 "PDRSR55,Power Domain Status Register 55" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E00++0x3 line.long 0x0 "PDRSR56,Power Domain Status Register 56" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E40++0x3 line.long 0x0 "PDRSR57,Power Domain Status Register 57" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E80++0x3 line.long 0x0 "PDRSR58,Power Domain Status Register 58" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1EC0++0x3 line.long 0x0 "PDRSR59,Power Domain Status Register 59" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F00++0x3 line.long 0x0 "PDRSR60,Power Domain Status Register 60" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F40++0x3 line.long 0x0 "PDRSR61,Power Domain Status Register 61" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F80++0x3 line.long 0x0 "PDRSR62,Power Domain Status Register 62" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1FC0++0x3 line.long 0x0 "PDRSR63,Power Domain Status Register 63" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" wgroup.long 0x1004++0x3 line.long 0x0 "PDRONCR0,Power Domain Power-ON Control Register 0" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1044++0x3 line.long 0x0 "PDRONCR1,Power Domain Power-ON Control Register 1" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1084++0x3 line.long 0x0 "PDRONCR2,Power Domain Power-ON Control Register 2" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x10C4++0x3 line.long 0x0 "PDRONCR3,Power Domain Power-ON Control Register 3" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1104++0x3 line.long 0x0 "PDRONCR4,Power Domain Power-ON Control Register 4" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1144++0x3 line.long 0x0 "PDRONCR5,Power Domain Power-ON Control Register 5" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1184++0x3 line.long 0x0 "PDRONCR6,Power Domain Power-ON Control Register 6" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x11C4++0x3 line.long 0x0 "PDRONCR7,Power Domain Power-ON Control Register 7" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1204++0x3 line.long 0x0 "PDRONCR8,Power Domain Power-ON Control Register 8" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1244++0x3 line.long 0x0 "PDRONCR9,Power Domain Power-ON Control Register 9" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1284++0x3 line.long 0x0 "PDRONCR10,Power Domain Power-ON Control Register 10" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x12C4++0x3 line.long 0x0 "PDRONCR11,Power Domain Power-ON Control Register 11" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1304++0x3 line.long 0x0 "PDRONCR12,Power Domain Power-ON Control Register 12" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1344++0x3 line.long 0x0 "PDRONCR13,Power Domain Power-ON Control Register 13" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1384++0x3 line.long 0x0 "PDRONCR14,Power Domain Power-ON Control Register 14" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x13C4++0x3 line.long 0x0 "PDRONCR15,Power Domain Power-ON Control Register 15" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1404++0x3 line.long 0x0 "PDRONCR16,Power Domain Power-ON Control Register 16" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1444++0x3 line.long 0x0 "PDRONCR17,Power Domain Power-ON Control Register 17" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1484++0x3 line.long 0x0 "PDRONCR18,Power Domain Power-ON Control Register 18" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x14C4++0x3 line.long 0x0 "PDRONCR19,Power Domain Power-ON Control Register 19" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1504++0x3 line.long 0x0 "PDRONCR20,Power Domain Power-ON Control Register 20" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1544++0x3 line.long 0x0 "PDRONCR21,Power Domain Power-ON Control Register 21" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1584++0x3 line.long 0x0 "PDRONCR22,Power Domain Power-ON Control Register 22" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x15C4++0x3 line.long 0x0 "PDRONCR23,Power Domain Power-ON Control Register 23" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1604++0x3 line.long 0x0 "PDRONCR24,Power Domain Power-ON Control Register 24" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1644++0x3 line.long 0x0 "PDRONCR25,Power Domain Power-ON Control Register 25" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1684++0x3 line.long 0x0 "PDRONCR26,Power Domain Power-ON Control Register 26" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x16C4++0x3 line.long 0x0 "PDRONCR27,Power Domain Power-ON Control Register 27" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1704++0x3 line.long 0x0 "PDRONCR28,Power Domain Power-ON Control Register 28" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1744++0x3 line.long 0x0 "PDRONCR29,Power Domain Power-ON Control Register 29" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1784++0x3 line.long 0x0 "PDRONCR30,Power Domain Power-ON Control Register 30" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x17C4++0x3 line.long 0x0 "PDRONCR31,Power Domain Power-ON Control Register 31" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1804++0x3 line.long 0x0 "PDRONCR32,Power Domain Power-ON Control Register 32" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1844++0x3 line.long 0x0 "PDRONCR33,Power Domain Power-ON Control Register 33" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1884++0x3 line.long 0x0 "PDRONCR34,Power Domain Power-ON Control Register 34" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x18C4++0x3 line.long 0x0 "PDRONCR35,Power Domain Power-ON Control Register 35" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1904++0x3 line.long 0x0 "PDRONCR36,Power Domain Power-ON Control Register 36" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1944++0x3 line.long 0x0 "PDRONCR37,Power Domain Power-ON Control Register 37" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1984++0x3 line.long 0x0 "PDRONCR38,Power Domain Power-ON Control Register 38" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x19C4++0x3 line.long 0x0 "PDRONCR39,Power Domain Power-ON Control Register 39" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A04++0x3 line.long 0x0 "PDRONCR40,Power Domain Power-ON Control Register 40" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A44++0x3 line.long 0x0 "PDRONCR41,Power Domain Power-ON Control Register 41" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A84++0x3 line.long 0x0 "PDRONCR42,Power Domain Power-ON Control Register 42" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1AC4++0x3 line.long 0x0 "PDRONCR43,Power Domain Power-ON Control Register 43" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B04++0x3 line.long 0x0 "PDRONCR44,Power Domain Power-ON Control Register 44" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B44++0x3 line.long 0x0 "PDRONCR45,Power Domain Power-ON Control Register 45" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B84++0x3 line.long 0x0 "PDRONCR46,Power Domain Power-ON Control Register 46" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1BC4++0x3 line.long 0x0 "PDRONCR47,Power Domain Power-ON Control Register 47" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C04++0x3 line.long 0x0 "PDRONCR48,Power Domain Power-ON Control Register 48" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C44++0x3 line.long 0x0 "PDRONCR49,Power Domain Power-ON Control Register 49" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C84++0x3 line.long 0x0 "PDRONCR50,Power Domain Power-ON Control Register 50" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1CC4++0x3 line.long 0x0 "PDRONCR51,Power Domain Power-ON Control Register 51" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D04++0x3 line.long 0x0 "PDRONCR52,Power Domain Power-ON Control Register 52" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D44++0x3 line.long 0x0 "PDRONCR53,Power Domain Power-ON Control Register 53" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D84++0x3 line.long 0x0 "PDRONCR54,Power Domain Power-ON Control Register 54" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1DC4++0x3 line.long 0x0 "PDRONCR55,Power Domain Power-ON Control Register 55" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E04++0x3 line.long 0x0 "PDRONCR56,Power Domain Power-ON Control Register 56" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E44++0x3 line.long 0x0 "PDRONCR57,Power Domain Power-ON Control Register 57" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E84++0x3 line.long 0x0 "PDRONCR58,Power Domain Power-ON Control Register 58" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1EC4++0x3 line.long 0x0 "PDRONCR59,Power Domain Power-ON Control Register 59" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F04++0x3 line.long 0x0 "PDRONCR60,Power Domain Power-ON Control Register 60" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F44++0x3 line.long 0x0 "PDRONCR61,Power Domain Power-ON Control Register 61" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F84++0x3 line.long 0x0 "PDRONCR62,Power Domain Power-ON Control Register 62" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1FC4++0x3 line.long 0x0 "PDRONCR63,Power Domain Power-ON Control Register 63" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1008++0x3 line.long 0x0 "PDROFFCR0,Power Domain Power-OFF Control Register 0" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1048++0x3 line.long 0x0 "PDROFFCR1,Power Domain Power-OFF Control Register 1" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1088++0x3 line.long 0x0 "PDROFFCR2,Power Domain Power-OFF Control Register 2" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x10C8++0x3 line.long 0x0 "PDROFFCR3,Power Domain Power-OFF Control Register 3" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1108++0x3 line.long 0x0 "PDROFFCR4,Power Domain Power-OFF Control Register 4" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1148++0x3 line.long 0x0 "PDROFFCR5,Power Domain Power-OFF Control Register 5" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1188++0x3 line.long 0x0 "PDROFFCR6,Power Domain Power-OFF Control Register 6" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x11C8++0x3 line.long 0x0 "PDROFFCR7,Power Domain Power-OFF Control Register 7" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1208++0x3 line.long 0x0 "PDROFFCR8,Power Domain Power-OFF Control Register 8" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1248++0x3 line.long 0x0 "PDROFFCR9,Power Domain Power-OFF Control Register 9" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1288++0x3 line.long 0x0 "PDROFFCR10,Power Domain Power-OFF Control Register 10" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x12C8++0x3 line.long 0x0 "PDROFFCR11,Power Domain Power-OFF Control Register 11" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1308++0x3 line.long 0x0 "PDROFFCR12,Power Domain Power-OFF Control Register 12" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1348++0x3 line.long 0x0 "PDROFFCR13,Power Domain Power-OFF Control Register 13" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1388++0x3 line.long 0x0 "PDROFFCR14,Power Domain Power-OFF Control Register 14" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x13C8++0x3 line.long 0x0 "PDROFFCR15,Power Domain Power-OFF Control Register 15" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1408++0x3 line.long 0x0 "PDROFFCR16,Power Domain Power-OFF Control Register 16" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1448++0x3 line.long 0x0 "PDROFFCR17,Power Domain Power-OFF Control Register 17" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1488++0x3 line.long 0x0 "PDROFFCR18,Power Domain Power-OFF Control Register 18" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x14C8++0x3 line.long 0x0 "PDROFFCR19,Power Domain Power-OFF Control Register 19" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1508++0x3 line.long 0x0 "PDROFFCR20,Power Domain Power-OFF Control Register 20" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1548++0x3 line.long 0x0 "PDROFFCR21,Power Domain Power-OFF Control Register 21" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1588++0x3 line.long 0x0 "PDROFFCR22,Power Domain Power-OFF Control Register 22" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x15C8++0x3 line.long 0x0 "PDROFFCR23,Power Domain Power-OFF Control Register 23" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1608++0x3 line.long 0x0 "PDROFFCR24,Power Domain Power-OFF Control Register 24" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1648++0x3 line.long 0x0 "PDROFFCR25,Power Domain Power-OFF Control Register 25" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1688++0x3 line.long 0x0 "PDROFFCR26,Power Domain Power-OFF Control Register 26" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x16C8++0x3 line.long 0x0 "PDROFFCR27,Power Domain Power-OFF Control Register 27" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1708++0x3 line.long 0x0 "PDROFFCR28,Power Domain Power-OFF Control Register 28" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1748++0x3 line.long 0x0 "PDROFFCR29,Power Domain Power-OFF Control Register 29" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1788++0x3 line.long 0x0 "PDROFFCR30,Power Domain Power-OFF Control Register 30" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x17C8++0x3 line.long 0x0 "PDROFFCR31,Power Domain Power-OFF Control Register 31" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1808++0x3 line.long 0x0 "PDROFFCR32,Power Domain Power-OFF Control Register 32" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1848++0x3 line.long 0x0 "PDROFFCR33,Power Domain Power-OFF Control Register 33" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1888++0x3 line.long 0x0 "PDROFFCR34,Power Domain Power-OFF Control Register 34" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x18C8++0x3 line.long 0x0 "PDROFFCR35,Power Domain Power-OFF Control Register 35" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1908++0x3 line.long 0x0 "PDROFFCR36,Power Domain Power-OFF Control Register 36" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1948++0x3 line.long 0x0 "PDROFFCR37,Power Domain Power-OFF Control Register 37" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1988++0x3 line.long 0x0 "PDROFFCR38,Power Domain Power-OFF Control Register 38" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x19C8++0x3 line.long 0x0 "PDROFFCR39,Power Domain Power-OFF Control Register 39" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A08++0x3 line.long 0x0 "PDROFFCR40,Power Domain Power-OFF Control Register 40" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A48++0x3 line.long 0x0 "PDROFFCR41,Power Domain Power-OFF Control Register 41" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A88++0x3 line.long 0x0 "PDROFFCR42,Power Domain Power-OFF Control Register 42" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1AC8++0x3 line.long 0x0 "PDROFFCR43,Power Domain Power-OFF Control Register 43" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B08++0x3 line.long 0x0 "PDROFFCR44,Power Domain Power-OFF Control Register 44" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B48++0x3 line.long 0x0 "PDROFFCR45,Power Domain Power-OFF Control Register 45" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B88++0x3 line.long 0x0 "PDROFFCR46,Power Domain Power-OFF Control Register 46" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1BC8++0x3 line.long 0x0 "PDROFFCR47,Power Domain Power-OFF Control Register 47" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C08++0x3 line.long 0x0 "PDROFFCR48,Power Domain Power-OFF Control Register 48" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C48++0x3 line.long 0x0 "PDROFFCR49,Power Domain Power-OFF Control Register 49" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C88++0x3 line.long 0x0 "PDROFFCR50,Power Domain Power-OFF Control Register 50" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1CC8++0x3 line.long 0x0 "PDROFFCR51,Power Domain Power-OFF Control Register 51" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D08++0x3 line.long 0x0 "PDROFFCR52,Power Domain Power-OFF Control Register 52" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D48++0x3 line.long 0x0 "PDROFFCR53,Power Domain Power-OFF Control Register 53" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D88++0x3 line.long 0x0 "PDROFFCR54,Power Domain Power-OFF Control Register 54" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1DC8++0x3 line.long 0x0 "PDROFFCR55,Power Domain Power-OFF Control Register 55" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E08++0x3 line.long 0x0 "PDROFFCR56,Power Domain Power-OFF Control Register 56" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E48++0x3 line.long 0x0 "PDROFFCR57,Power Domain Power-OFF Control Register 57" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E88++0x3 line.long 0x0 "PDROFFCR58,Power Domain Power-OFF Control Register 58" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1EC8++0x3 line.long 0x0 "PDROFFCR59,Power Domain Power-OFF Control Register 59" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F08++0x3 line.long 0x0 "PDROFFCR60,Power Domain Power-OFF Control Register 60" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F48++0x3 line.long 0x0 "PDROFFCR61,Power Domain Power-OFF Control Register 61" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F88++0x3 line.long 0x0 "PDROFFCR62,Power Domain Power-OFF Control Register 62" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1FC8++0x3 line.long 0x0 "PDROFFCR63,Power Domain Power-OFF Control Register 63" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" group.long 0x3000++0x17 line.long 0x0 "SYSCD0WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD0WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD0WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD0WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD0WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD0WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." group.long 0x3020++0x17 line.long 0x0 "SYSCD1WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD1WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD1WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD1WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD1WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD1WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." group.long 0x3040++0x17 line.long 0x0 "SYSCD2WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD2WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD2WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD2WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD2WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD2WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." group.long 0x3060++0x17 line.long 0x0 "SYSCD3WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD3WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD3WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD3WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD3WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD3WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." tree.end tree "SYSC_2" base ad:0xE6188000 rgroup.long 0x0++0x3 line.long 0x0 "SYSCSR,SYSC Status Register" bitfld.long 0x0 0.--1. "BUSY,Indicates whether the SYSC is processing Power-ON or Power-OFF sequence." "0: Processing Power-ON or OFF sequence,?,?,?" group.long 0x10++0x7 line.long 0x0 "SYSCPTCSR,Protect Control/Status Register" bitfld.long 0x0 2. "EIEI,Write access protection Error Interrupt request Enable for INTC." "0: Disable error interrupt request for INTC,1: Enable error interrupt request for INTC" bitfld.long 0x0 1. "EIE,Write access protection Error Interrupt request Enable for ECM (FuSa)." "0: Disable error interrupt request for ECM,1: Enable error interrupt request for ECM" newline bitfld.long 0x0 0. "ERR,Indicates Write access protection Error status." "0: Not detected Write access protection error,1: Detected Write access protection error" line.long 0x4 "SYSCPTERADR,Protect Error Address Register" bitfld.long 0x4 16. "CLR,Write access protection error address clear" "0,1" hexmask.long.word 0x4 0.--15. 1. "ADR,First Write access protection error address." group.long 0x20++0x7 line.long 0x0 "SYSCRDNCSR,HW Redundant Error Control/Status Register" hexmask.long.word 0x0 16.--31. 1. "EIE,HW Redundant Error Interrupt Enable" hexmask.long.word 0x0 0.--15. 1. "ERR,HW Redundant Error Status" line.long 0x4 "SYSCRDNIR,HW Redundant Error Injection Register" hexmask.long.word 0x4 0.--15. 1. "ERIN,Injects HW Redundant Error" group.long 0x30++0x3 line.long 0x0 "SYSCAPBACR,APB BUS Access Check Register" hexmask.long 0x0 0.--31. 1. "VAL,APB BUS Access Check Register for FuSa" rgroup.long 0x800++0xF line.long 0x0 "SYSCPONSR0,Power-ON Status Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON status for PDR00-31 power domains." line.long 0x4 "SYSCPONSR1,Power-ON Status Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON status for PDR32-63 power domains." line.long 0x8 "SYSCPOFFSR0,Power-OFF Status Register 0" hexmask.long 0x8 0.--31. 1. "PDR,Power-OFF Status for PDR31-00 power domains." line.long 0xC "SYSCPOFFSR1,Power-OFF Status Register 1" hexmask.long 0xC 0.--31. 1. "PDR,Power-OFF Status for PDR63-32 power domains." group.long 0x810++0x7 line.long 0x0 "SYSCISCR0,Interrupt Status/Clear Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt status for PDR00-31 power domains." line.long 0x4 "SYSCISCR1,Interrupt Status/Clear Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt status for PDR32-63 power domains." group.long 0x820++0x7 line.long 0x0 "SYSCIER0,Interrupt Enable Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt Enable for PDR00-31 power domains." line.long 0x4 "SYSCIER1,Interrupt Enable Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt Enable for PDR32-63 power domains." group.long 0x830++0x7 line.long 0x0 "SYSCIMR0,Interrupt Mask Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Mask complete interrupt request to INTC for PDR00-31 power domains." line.long 0x4 "SYSCIMR1,Interrupt Mask Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Mask complete interrupt request to INTC for PDR32-63 power domains." group.long 0x860++0x1F line.long 0x0 "SYSCISOEHSR0,Isolation Error High Status/Clear Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Isolation Error High Status/Clear" line.long 0x4 "SYSCISOEHSR1,Isolation Error High Status/Clear Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Isolation Error High Status/Clear" line.long 0x8 "SYSCISOELSR0,Isolation Error Low Status/Clear Register 0" hexmask.long 0x8 0.--31. 1. "PDR,Isolation Error Low Status/Clear" line.long 0xC "SYSCISOELSR1,Isolation Error Low Status/Clear Register 1" hexmask.long 0xC 0.--31. 1. "PDR,Isolation Error Low Status/Clear" line.long 0x10 "SYSCISOEHIR0,Isolation Error High Injection Register 0" hexmask.long 0x10 0.--31. 1. "PDR,Isolation Error High Injection for PDR00-31" line.long 0x14 "SYSCISOEHIR1,Isolation Error High Injection Register 1" hexmask.long 0x14 0.--31. 1. "PDR,Isolation Error High Injection for PDR32-63" line.long 0x18 "SYSCISOELIR0,Isolation Error Low Injection Register 0" hexmask.long 0x18 0.--31. 1. "PDR,Isolation Error Low Injection for PDR00-31" line.long 0x1C "SYSCISOELIR1,Isolation Error Low Injection Register 1" hexmask.long 0x1C 0.--31. 1. "PDR,Isolation Error Low Injection for PDR32-63" rgroup.long 0x1000++0x3 line.long 0x0 "PDRSR0,Power Domain Status Register 0" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1040++0x3 line.long 0x0 "PDRSR1,Power Domain Status Register 1" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1080++0x3 line.long 0x0 "PDRSR2,Power Domain Status Register 2" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x10C0++0x3 line.long 0x0 "PDRSR3,Power Domain Status Register 3" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1100++0x3 line.long 0x0 "PDRSR4,Power Domain Status Register 4" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1140++0x3 line.long 0x0 "PDRSR5,Power Domain Status Register 5" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1180++0x3 line.long 0x0 "PDRSR6,Power Domain Status Register 6" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x11C0++0x3 line.long 0x0 "PDRSR7,Power Domain Status Register 7" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1200++0x3 line.long 0x0 "PDRSR8,Power Domain Status Register 8" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1240++0x3 line.long 0x0 "PDRSR9,Power Domain Status Register 9" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1280++0x3 line.long 0x0 "PDRSR10,Power Domain Status Register 10" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x12C0++0x3 line.long 0x0 "PDRSR11,Power Domain Status Register 11" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1300++0x3 line.long 0x0 "PDRSR12,Power Domain Status Register 12" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1340++0x3 line.long 0x0 "PDRSR13,Power Domain Status Register 13" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1380++0x3 line.long 0x0 "PDRSR14,Power Domain Status Register 14" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x13C0++0x3 line.long 0x0 "PDRSR15,Power Domain Status Register 15" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1400++0x3 line.long 0x0 "PDRSR16,Power Domain Status Register 16" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1440++0x3 line.long 0x0 "PDRSR17,Power Domain Status Register 17" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1480++0x3 line.long 0x0 "PDRSR18,Power Domain Status Register 18" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x14C0++0x3 line.long 0x0 "PDRSR19,Power Domain Status Register 19" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1500++0x3 line.long 0x0 "PDRSR20,Power Domain Status Register 20" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1540++0x3 line.long 0x0 "PDRSR21,Power Domain Status Register 21" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1580++0x3 line.long 0x0 "PDRSR22,Power Domain Status Register 22" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x15C0++0x3 line.long 0x0 "PDRSR23,Power Domain Status Register 23" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1600++0x3 line.long 0x0 "PDRSR24,Power Domain Status Register 24" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1640++0x3 line.long 0x0 "PDRSR25,Power Domain Status Register 25" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1680++0x3 line.long 0x0 "PDRSR26,Power Domain Status Register 26" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x16C0++0x3 line.long 0x0 "PDRSR27,Power Domain Status Register 27" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1700++0x3 line.long 0x0 "PDRSR28,Power Domain Status Register 28" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1740++0x3 line.long 0x0 "PDRSR29,Power Domain Status Register 29" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1780++0x3 line.long 0x0 "PDRSR30,Power Domain Status Register 30" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x17C0++0x3 line.long 0x0 "PDRSR31,Power Domain Status Register 31" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1800++0x3 line.long 0x0 "PDRSR32,Power Domain Status Register 32" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1840++0x3 line.long 0x0 "PDRSR33,Power Domain Status Register 33" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1880++0x3 line.long 0x0 "PDRSR34,Power Domain Status Register 34" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x18C0++0x3 line.long 0x0 "PDRSR35,Power Domain Status Register 35" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1900++0x3 line.long 0x0 "PDRSR36,Power Domain Status Register 36" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1940++0x3 line.long 0x0 "PDRSR37,Power Domain Status Register 37" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1980++0x3 line.long 0x0 "PDRSR38,Power Domain Status Register 38" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x19C0++0x3 line.long 0x0 "PDRSR39,Power Domain Status Register 39" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A00++0x3 line.long 0x0 "PDRSR40,Power Domain Status Register 40" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A40++0x3 line.long 0x0 "PDRSR41,Power Domain Status Register 41" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A80++0x3 line.long 0x0 "PDRSR42,Power Domain Status Register 42" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1AC0++0x3 line.long 0x0 "PDRSR43,Power Domain Status Register 43" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B00++0x3 line.long 0x0 "PDRSR44,Power Domain Status Register 44" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B40++0x3 line.long 0x0 "PDRSR45,Power Domain Status Register 45" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B80++0x3 line.long 0x0 "PDRSR46,Power Domain Status Register 46" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1BC0++0x3 line.long 0x0 "PDRSR47,Power Domain Status Register 47" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C00++0x3 line.long 0x0 "PDRSR48,Power Domain Status Register 48" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C40++0x3 line.long 0x0 "PDRSR49,Power Domain Status Register 49" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C80++0x3 line.long 0x0 "PDRSR50,Power Domain Status Register 50" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1CC0++0x3 line.long 0x0 "PDRSR51,Power Domain Status Register 51" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D00++0x3 line.long 0x0 "PDRSR52,Power Domain Status Register 52" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D40++0x3 line.long 0x0 "PDRSR53,Power Domain Status Register 53" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D80++0x3 line.long 0x0 "PDRSR54,Power Domain Status Register 54" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1DC0++0x3 line.long 0x0 "PDRSR55,Power Domain Status Register 55" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E00++0x3 line.long 0x0 "PDRSR56,Power Domain Status Register 56" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E40++0x3 line.long 0x0 "PDRSR57,Power Domain Status Register 57" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E80++0x3 line.long 0x0 "PDRSR58,Power Domain Status Register 58" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1EC0++0x3 line.long 0x0 "PDRSR59,Power Domain Status Register 59" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F00++0x3 line.long 0x0 "PDRSR60,Power Domain Status Register 60" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F40++0x3 line.long 0x0 "PDRSR61,Power Domain Status Register 61" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F80++0x3 line.long 0x0 "PDRSR62,Power Domain Status Register 62" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1FC0++0x3 line.long 0x0 "PDRSR63,Power Domain Status Register 63" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" wgroup.long 0x1004++0x3 line.long 0x0 "PDRONCR0,Power Domain Power-ON Control Register 0" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1044++0x3 line.long 0x0 "PDRONCR1,Power Domain Power-ON Control Register 1" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1084++0x3 line.long 0x0 "PDRONCR2,Power Domain Power-ON Control Register 2" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x10C4++0x3 line.long 0x0 "PDRONCR3,Power Domain Power-ON Control Register 3" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1104++0x3 line.long 0x0 "PDRONCR4,Power Domain Power-ON Control Register 4" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1144++0x3 line.long 0x0 "PDRONCR5,Power Domain Power-ON Control Register 5" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1184++0x3 line.long 0x0 "PDRONCR6,Power Domain Power-ON Control Register 6" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x11C4++0x3 line.long 0x0 "PDRONCR7,Power Domain Power-ON Control Register 7" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1204++0x3 line.long 0x0 "PDRONCR8,Power Domain Power-ON Control Register 8" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1244++0x3 line.long 0x0 "PDRONCR9,Power Domain Power-ON Control Register 9" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1284++0x3 line.long 0x0 "PDRONCR10,Power Domain Power-ON Control Register 10" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x12C4++0x3 line.long 0x0 "PDRONCR11,Power Domain Power-ON Control Register 11" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1304++0x3 line.long 0x0 "PDRONCR12,Power Domain Power-ON Control Register 12" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1344++0x3 line.long 0x0 "PDRONCR13,Power Domain Power-ON Control Register 13" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1384++0x3 line.long 0x0 "PDRONCR14,Power Domain Power-ON Control Register 14" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x13C4++0x3 line.long 0x0 "PDRONCR15,Power Domain Power-ON Control Register 15" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1404++0x3 line.long 0x0 "PDRONCR16,Power Domain Power-ON Control Register 16" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1444++0x3 line.long 0x0 "PDRONCR17,Power Domain Power-ON Control Register 17" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1484++0x3 line.long 0x0 "PDRONCR18,Power Domain Power-ON Control Register 18" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x14C4++0x3 line.long 0x0 "PDRONCR19,Power Domain Power-ON Control Register 19" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1504++0x3 line.long 0x0 "PDRONCR20,Power Domain Power-ON Control Register 20" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1544++0x3 line.long 0x0 "PDRONCR21,Power Domain Power-ON Control Register 21" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1584++0x3 line.long 0x0 "PDRONCR22,Power Domain Power-ON Control Register 22" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x15C4++0x3 line.long 0x0 "PDRONCR23,Power Domain Power-ON Control Register 23" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1604++0x3 line.long 0x0 "PDRONCR24,Power Domain Power-ON Control Register 24" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1644++0x3 line.long 0x0 "PDRONCR25,Power Domain Power-ON Control Register 25" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1684++0x3 line.long 0x0 "PDRONCR26,Power Domain Power-ON Control Register 26" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x16C4++0x3 line.long 0x0 "PDRONCR27,Power Domain Power-ON Control Register 27" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1704++0x3 line.long 0x0 "PDRONCR28,Power Domain Power-ON Control Register 28" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1744++0x3 line.long 0x0 "PDRONCR29,Power Domain Power-ON Control Register 29" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1784++0x3 line.long 0x0 "PDRONCR30,Power Domain Power-ON Control Register 30" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x17C4++0x3 line.long 0x0 "PDRONCR31,Power Domain Power-ON Control Register 31" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1804++0x3 line.long 0x0 "PDRONCR32,Power Domain Power-ON Control Register 32" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1844++0x3 line.long 0x0 "PDRONCR33,Power Domain Power-ON Control Register 33" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1884++0x3 line.long 0x0 "PDRONCR34,Power Domain Power-ON Control Register 34" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x18C4++0x3 line.long 0x0 "PDRONCR35,Power Domain Power-ON Control Register 35" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1904++0x3 line.long 0x0 "PDRONCR36,Power Domain Power-ON Control Register 36" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1944++0x3 line.long 0x0 "PDRONCR37,Power Domain Power-ON Control Register 37" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1984++0x3 line.long 0x0 "PDRONCR38,Power Domain Power-ON Control Register 38" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x19C4++0x3 line.long 0x0 "PDRONCR39,Power Domain Power-ON Control Register 39" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A04++0x3 line.long 0x0 "PDRONCR40,Power Domain Power-ON Control Register 40" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A44++0x3 line.long 0x0 "PDRONCR41,Power Domain Power-ON Control Register 41" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A84++0x3 line.long 0x0 "PDRONCR42,Power Domain Power-ON Control Register 42" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1AC4++0x3 line.long 0x0 "PDRONCR43,Power Domain Power-ON Control Register 43" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B04++0x3 line.long 0x0 "PDRONCR44,Power Domain Power-ON Control Register 44" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B44++0x3 line.long 0x0 "PDRONCR45,Power Domain Power-ON Control Register 45" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B84++0x3 line.long 0x0 "PDRONCR46,Power Domain Power-ON Control Register 46" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1BC4++0x3 line.long 0x0 "PDRONCR47,Power Domain Power-ON Control Register 47" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C04++0x3 line.long 0x0 "PDRONCR48,Power Domain Power-ON Control Register 48" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C44++0x3 line.long 0x0 "PDRONCR49,Power Domain Power-ON Control Register 49" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C84++0x3 line.long 0x0 "PDRONCR50,Power Domain Power-ON Control Register 50" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1CC4++0x3 line.long 0x0 "PDRONCR51,Power Domain Power-ON Control Register 51" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D04++0x3 line.long 0x0 "PDRONCR52,Power Domain Power-ON Control Register 52" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D44++0x3 line.long 0x0 "PDRONCR53,Power Domain Power-ON Control Register 53" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D84++0x3 line.long 0x0 "PDRONCR54,Power Domain Power-ON Control Register 54" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1DC4++0x3 line.long 0x0 "PDRONCR55,Power Domain Power-ON Control Register 55" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E04++0x3 line.long 0x0 "PDRONCR56,Power Domain Power-ON Control Register 56" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E44++0x3 line.long 0x0 "PDRONCR57,Power Domain Power-ON Control Register 57" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E84++0x3 line.long 0x0 "PDRONCR58,Power Domain Power-ON Control Register 58" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1EC4++0x3 line.long 0x0 "PDRONCR59,Power Domain Power-ON Control Register 59" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F04++0x3 line.long 0x0 "PDRONCR60,Power Domain Power-ON Control Register 60" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F44++0x3 line.long 0x0 "PDRONCR61,Power Domain Power-ON Control Register 61" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F84++0x3 line.long 0x0 "PDRONCR62,Power Domain Power-ON Control Register 62" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1FC4++0x3 line.long 0x0 "PDRONCR63,Power Domain Power-ON Control Register 63" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1008++0x3 line.long 0x0 "PDROFFCR0,Power Domain Power-OFF Control Register 0" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1048++0x3 line.long 0x0 "PDROFFCR1,Power Domain Power-OFF Control Register 1" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1088++0x3 line.long 0x0 "PDROFFCR2,Power Domain Power-OFF Control Register 2" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x10C8++0x3 line.long 0x0 "PDROFFCR3,Power Domain Power-OFF Control Register 3" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1108++0x3 line.long 0x0 "PDROFFCR4,Power Domain Power-OFF Control Register 4" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1148++0x3 line.long 0x0 "PDROFFCR5,Power Domain Power-OFF Control Register 5" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1188++0x3 line.long 0x0 "PDROFFCR6,Power Domain Power-OFF Control Register 6" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x11C8++0x3 line.long 0x0 "PDROFFCR7,Power Domain Power-OFF Control Register 7" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1208++0x3 line.long 0x0 "PDROFFCR8,Power Domain Power-OFF Control Register 8" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1248++0x3 line.long 0x0 "PDROFFCR9,Power Domain Power-OFF Control Register 9" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1288++0x3 line.long 0x0 "PDROFFCR10,Power Domain Power-OFF Control Register 10" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x12C8++0x3 line.long 0x0 "PDROFFCR11,Power Domain Power-OFF Control Register 11" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1308++0x3 line.long 0x0 "PDROFFCR12,Power Domain Power-OFF Control Register 12" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1348++0x3 line.long 0x0 "PDROFFCR13,Power Domain Power-OFF Control Register 13" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1388++0x3 line.long 0x0 "PDROFFCR14,Power Domain Power-OFF Control Register 14" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x13C8++0x3 line.long 0x0 "PDROFFCR15,Power Domain Power-OFF Control Register 15" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1408++0x3 line.long 0x0 "PDROFFCR16,Power Domain Power-OFF Control Register 16" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1448++0x3 line.long 0x0 "PDROFFCR17,Power Domain Power-OFF Control Register 17" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1488++0x3 line.long 0x0 "PDROFFCR18,Power Domain Power-OFF Control Register 18" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x14C8++0x3 line.long 0x0 "PDROFFCR19,Power Domain Power-OFF Control Register 19" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1508++0x3 line.long 0x0 "PDROFFCR20,Power Domain Power-OFF Control Register 20" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1548++0x3 line.long 0x0 "PDROFFCR21,Power Domain Power-OFF Control Register 21" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1588++0x3 line.long 0x0 "PDROFFCR22,Power Domain Power-OFF Control Register 22" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x15C8++0x3 line.long 0x0 "PDROFFCR23,Power Domain Power-OFF Control Register 23" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1608++0x3 line.long 0x0 "PDROFFCR24,Power Domain Power-OFF Control Register 24" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1648++0x3 line.long 0x0 "PDROFFCR25,Power Domain Power-OFF Control Register 25" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1688++0x3 line.long 0x0 "PDROFFCR26,Power Domain Power-OFF Control Register 26" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x16C8++0x3 line.long 0x0 "PDROFFCR27,Power Domain Power-OFF Control Register 27" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1708++0x3 line.long 0x0 "PDROFFCR28,Power Domain Power-OFF Control Register 28" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1748++0x3 line.long 0x0 "PDROFFCR29,Power Domain Power-OFF Control Register 29" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1788++0x3 line.long 0x0 "PDROFFCR30,Power Domain Power-OFF Control Register 30" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x17C8++0x3 line.long 0x0 "PDROFFCR31,Power Domain Power-OFF Control Register 31" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1808++0x3 line.long 0x0 "PDROFFCR32,Power Domain Power-OFF Control Register 32" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1848++0x3 line.long 0x0 "PDROFFCR33,Power Domain Power-OFF Control Register 33" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1888++0x3 line.long 0x0 "PDROFFCR34,Power Domain Power-OFF Control Register 34" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x18C8++0x3 line.long 0x0 "PDROFFCR35,Power Domain Power-OFF Control Register 35" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1908++0x3 line.long 0x0 "PDROFFCR36,Power Domain Power-OFF Control Register 36" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1948++0x3 line.long 0x0 "PDROFFCR37,Power Domain Power-OFF Control Register 37" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1988++0x3 line.long 0x0 "PDROFFCR38,Power Domain Power-OFF Control Register 38" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x19C8++0x3 line.long 0x0 "PDROFFCR39,Power Domain Power-OFF Control Register 39" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A08++0x3 line.long 0x0 "PDROFFCR40,Power Domain Power-OFF Control Register 40" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A48++0x3 line.long 0x0 "PDROFFCR41,Power Domain Power-OFF Control Register 41" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A88++0x3 line.long 0x0 "PDROFFCR42,Power Domain Power-OFF Control Register 42" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1AC8++0x3 line.long 0x0 "PDROFFCR43,Power Domain Power-OFF Control Register 43" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B08++0x3 line.long 0x0 "PDROFFCR44,Power Domain Power-OFF Control Register 44" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B48++0x3 line.long 0x0 "PDROFFCR45,Power Domain Power-OFF Control Register 45" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B88++0x3 line.long 0x0 "PDROFFCR46,Power Domain Power-OFF Control Register 46" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1BC8++0x3 line.long 0x0 "PDROFFCR47,Power Domain Power-OFF Control Register 47" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C08++0x3 line.long 0x0 "PDROFFCR48,Power Domain Power-OFF Control Register 48" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C48++0x3 line.long 0x0 "PDROFFCR49,Power Domain Power-OFF Control Register 49" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C88++0x3 line.long 0x0 "PDROFFCR50,Power Domain Power-OFF Control Register 50" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1CC8++0x3 line.long 0x0 "PDROFFCR51,Power Domain Power-OFF Control Register 51" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D08++0x3 line.long 0x0 "PDROFFCR52,Power Domain Power-OFF Control Register 52" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D48++0x3 line.long 0x0 "PDROFFCR53,Power Domain Power-OFF Control Register 53" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D88++0x3 line.long 0x0 "PDROFFCR54,Power Domain Power-OFF Control Register 54" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1DC8++0x3 line.long 0x0 "PDROFFCR55,Power Domain Power-OFF Control Register 55" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E08++0x3 line.long 0x0 "PDROFFCR56,Power Domain Power-OFF Control Register 56" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E48++0x3 line.long 0x0 "PDROFFCR57,Power Domain Power-OFF Control Register 57" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E88++0x3 line.long 0x0 "PDROFFCR58,Power Domain Power-OFF Control Register 58" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1EC8++0x3 line.long 0x0 "PDROFFCR59,Power Domain Power-OFF Control Register 59" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F08++0x3 line.long 0x0 "PDROFFCR60,Power Domain Power-OFF Control Register 60" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F48++0x3 line.long 0x0 "PDROFFCR61,Power Domain Power-OFF Control Register 61" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F88++0x3 line.long 0x0 "PDROFFCR62,Power Domain Power-OFF Control Register 62" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1FC8++0x3 line.long 0x0 "PDROFFCR63,Power Domain Power-OFF Control Register 63" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" group.long 0x3000++0x17 line.long 0x0 "SYSCD0WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD0WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD0WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD0WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD0WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD0WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." group.long 0x3020++0x17 line.long 0x0 "SYSCD1WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD1WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD1WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD1WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD1WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD1WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." group.long 0x3040++0x17 line.long 0x0 "SYSCD2WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD2WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD2WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD2WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD2WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD2WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." group.long 0x3060++0x17 line.long 0x0 "SYSCD3WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD3WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD3WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD3WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD3WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD3WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." tree.end tree "SYSC_3" base ad:0xE618C000 rgroup.long 0x0++0x3 line.long 0x0 "SYSCSR,SYSC Status Register" bitfld.long 0x0 0.--1. "BUSY,Indicates whether the SYSC is processing Power-ON or Power-OFF sequence." "0: Processing Power-ON or OFF sequence,?,?,?" group.long 0x10++0x7 line.long 0x0 "SYSCPTCSR,Protect Control/Status Register" bitfld.long 0x0 2. "EIEI,Write access protection Error Interrupt request Enable for INTC." "0: Disable error interrupt request for INTC,1: Enable error interrupt request for INTC" bitfld.long 0x0 1. "EIE,Write access protection Error Interrupt request Enable for ECM (FuSa)." "0: Disable error interrupt request for ECM,1: Enable error interrupt request for ECM" newline bitfld.long 0x0 0. "ERR,Indicates Write access protection Error status." "0: Not detected Write access protection error,1: Detected Write access protection error" line.long 0x4 "SYSCPTERADR,Protect Error Address Register" bitfld.long 0x4 16. "CLR,Write access protection error address clear" "0,1" hexmask.long.word 0x4 0.--15. 1. "ADR,First Write access protection error address." group.long 0x20++0x7 line.long 0x0 "SYSCRDNCSR,HW Redundant Error Control/Status Register" hexmask.long.word 0x0 16.--31. 1. "EIE,HW Redundant Error Interrupt Enable" hexmask.long.word 0x0 0.--15. 1. "ERR,HW Redundant Error Status" line.long 0x4 "SYSCRDNIR,HW Redundant Error Injection Register" hexmask.long.word 0x4 0.--15. 1. "ERIN,Injects HW Redundant Error" group.long 0x30++0x3 line.long 0x0 "SYSCAPBACR,APB BUS Access Check Register" hexmask.long 0x0 0.--31. 1. "VAL,APB BUS Access Check Register for FuSa" rgroup.long 0x800++0xF line.long 0x0 "SYSCPONSR0,Power-ON Status Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON status for PDR00-31 power domains." line.long 0x4 "SYSCPONSR1,Power-ON Status Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON status for PDR32-63 power domains." line.long 0x8 "SYSCPOFFSR0,Power-OFF Status Register 0" hexmask.long 0x8 0.--31. 1. "PDR,Power-OFF Status for PDR31-00 power domains." line.long 0xC "SYSCPOFFSR1,Power-OFF Status Register 1" hexmask.long 0xC 0.--31. 1. "PDR,Power-OFF Status for PDR63-32 power domains." group.long 0x810++0x7 line.long 0x0 "SYSCISCR0,Interrupt Status/Clear Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt status for PDR00-31 power domains." line.long 0x4 "SYSCISCR1,Interrupt Status/Clear Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt status for PDR32-63 power domains." group.long 0x820++0x7 line.long 0x0 "SYSCIER0,Interrupt Enable Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt Enable for PDR00-31 power domains." line.long 0x4 "SYSCIER1,Interrupt Enable Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Power-ON or OFF process complete interrupt Enable for PDR32-63 power domains." group.long 0x830++0x7 line.long 0x0 "SYSCIMR0,Interrupt Mask Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Mask complete interrupt request to INTC for PDR00-31 power domains." line.long 0x4 "SYSCIMR1,Interrupt Mask Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Mask complete interrupt request to INTC for PDR32-63 power domains." group.long 0x860++0x1F line.long 0x0 "SYSCISOEHSR0,Isolation Error High Status/Clear Register 0" hexmask.long 0x0 0.--31. 1. "PDR,Isolation Error High Status/Clear" line.long 0x4 "SYSCISOEHSR1,Isolation Error High Status/Clear Register 1" hexmask.long 0x4 0.--31. 1. "PDR,Isolation Error High Status/Clear" line.long 0x8 "SYSCISOELSR0,Isolation Error Low Status/Clear Register 0" hexmask.long 0x8 0.--31. 1. "PDR,Isolation Error Low Status/Clear" line.long 0xC "SYSCISOELSR1,Isolation Error Low Status/Clear Register 1" hexmask.long 0xC 0.--31. 1. "PDR,Isolation Error Low Status/Clear" line.long 0x10 "SYSCISOEHIR0,Isolation Error High Injection Register 0" hexmask.long 0x10 0.--31. 1. "PDR,Isolation Error High Injection for PDR00-31" line.long 0x14 "SYSCISOEHIR1,Isolation Error High Injection Register 1" hexmask.long 0x14 0.--31. 1. "PDR,Isolation Error High Injection for PDR32-63" line.long 0x18 "SYSCISOELIR0,Isolation Error Low Injection Register 0" hexmask.long 0x18 0.--31. 1. "PDR,Isolation Error Low Injection for PDR00-31" line.long 0x1C "SYSCISOELIR1,Isolation Error Low Injection Register 1" hexmask.long 0x1C 0.--31. 1. "PDR,Isolation Error Low Injection for PDR32-63" rgroup.long 0x1000++0x3 line.long 0x0 "PDRSR0,Power Domain Status Register 0" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1040++0x3 line.long 0x0 "PDRSR1,Power Domain Status Register 1" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1080++0x3 line.long 0x0 "PDRSR2,Power Domain Status Register 2" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x10C0++0x3 line.long 0x0 "PDRSR3,Power Domain Status Register 3" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1100++0x3 line.long 0x0 "PDRSR4,Power Domain Status Register 4" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1140++0x3 line.long 0x0 "PDRSR5,Power Domain Status Register 5" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1180++0x3 line.long 0x0 "PDRSR6,Power Domain Status Register 6" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x11C0++0x3 line.long 0x0 "PDRSR7,Power Domain Status Register 7" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1200++0x3 line.long 0x0 "PDRSR8,Power Domain Status Register 8" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1240++0x3 line.long 0x0 "PDRSR9,Power Domain Status Register 9" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1280++0x3 line.long 0x0 "PDRSR10,Power Domain Status Register 10" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x12C0++0x3 line.long 0x0 "PDRSR11,Power Domain Status Register 11" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1300++0x3 line.long 0x0 "PDRSR12,Power Domain Status Register 12" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1340++0x3 line.long 0x0 "PDRSR13,Power Domain Status Register 13" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1380++0x3 line.long 0x0 "PDRSR14,Power Domain Status Register 14" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x13C0++0x3 line.long 0x0 "PDRSR15,Power Domain Status Register 15" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1400++0x3 line.long 0x0 "PDRSR16,Power Domain Status Register 16" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1440++0x3 line.long 0x0 "PDRSR17,Power Domain Status Register 17" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1480++0x3 line.long 0x0 "PDRSR18,Power Domain Status Register 18" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x14C0++0x3 line.long 0x0 "PDRSR19,Power Domain Status Register 19" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1500++0x3 line.long 0x0 "PDRSR20,Power Domain Status Register 20" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1540++0x3 line.long 0x0 "PDRSR21,Power Domain Status Register 21" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1580++0x3 line.long 0x0 "PDRSR22,Power Domain Status Register 22" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x15C0++0x3 line.long 0x0 "PDRSR23,Power Domain Status Register 23" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1600++0x3 line.long 0x0 "PDRSR24,Power Domain Status Register 24" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1640++0x3 line.long 0x0 "PDRSR25,Power Domain Status Register 25" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1680++0x3 line.long 0x0 "PDRSR26,Power Domain Status Register 26" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x16C0++0x3 line.long 0x0 "PDRSR27,Power Domain Status Register 27" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1700++0x3 line.long 0x0 "PDRSR28,Power Domain Status Register 28" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1740++0x3 line.long 0x0 "PDRSR29,Power Domain Status Register 29" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1780++0x3 line.long 0x0 "PDRSR30,Power Domain Status Register 30" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x17C0++0x3 line.long 0x0 "PDRSR31,Power Domain Status Register 31" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1800++0x3 line.long 0x0 "PDRSR32,Power Domain Status Register 32" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1840++0x3 line.long 0x0 "PDRSR33,Power Domain Status Register 33" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1880++0x3 line.long 0x0 "PDRSR34,Power Domain Status Register 34" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x18C0++0x3 line.long 0x0 "PDRSR35,Power Domain Status Register 35" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1900++0x3 line.long 0x0 "PDRSR36,Power Domain Status Register 36" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1940++0x3 line.long 0x0 "PDRSR37,Power Domain Status Register 37" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1980++0x3 line.long 0x0 "PDRSR38,Power Domain Status Register 38" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x19C0++0x3 line.long 0x0 "PDRSR39,Power Domain Status Register 39" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A00++0x3 line.long 0x0 "PDRSR40,Power Domain Status Register 40" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A40++0x3 line.long 0x0 "PDRSR41,Power Domain Status Register 41" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1A80++0x3 line.long 0x0 "PDRSR42,Power Domain Status Register 42" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1AC0++0x3 line.long 0x0 "PDRSR43,Power Domain Status Register 43" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B00++0x3 line.long 0x0 "PDRSR44,Power Domain Status Register 44" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B40++0x3 line.long 0x0 "PDRSR45,Power Domain Status Register 45" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1B80++0x3 line.long 0x0 "PDRSR46,Power Domain Status Register 46" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1BC0++0x3 line.long 0x0 "PDRSR47,Power Domain Status Register 47" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C00++0x3 line.long 0x0 "PDRSR48,Power Domain Status Register 48" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C40++0x3 line.long 0x0 "PDRSR49,Power Domain Status Register 49" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1C80++0x3 line.long 0x0 "PDRSR50,Power Domain Status Register 50" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1CC0++0x3 line.long 0x0 "PDRSR51,Power Domain Status Register 51" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D00++0x3 line.long 0x0 "PDRSR52,Power Domain Status Register 52" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D40++0x3 line.long 0x0 "PDRSR53,Power Domain Status Register 53" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1D80++0x3 line.long 0x0 "PDRSR54,Power Domain Status Register 54" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1DC0++0x3 line.long 0x0 "PDRSR55,Power Domain Status Register 55" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E00++0x3 line.long 0x0 "PDRSR56,Power Domain Status Register 56" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E40++0x3 line.long 0x0 "PDRSR57,Power Domain Status Register 57" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1E80++0x3 line.long 0x0 "PDRSR58,Power Domain Status Register 58" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1EC0++0x3 line.long 0x0 "PDRSR59,Power Domain Status Register 59" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F00++0x3 line.long 0x0 "PDRSR60,Power Domain Status Register 60" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F40++0x3 line.long 0x0 "PDRSR61,Power Domain Status Register 61" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1F80++0x3 line.long 0x0 "PDRSR62,Power Domain Status Register 62" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" rgroup.long 0x1FC0++0x3 line.long 0x0 "PDRSR63,Power Domain Status Register 63" bitfld.long 0x0 12. "ON_STATE,Indicates status of Power-ON sequence." "0: Not processing Power-ON sequence,1: Processing Power ON sequence" bitfld.long 0x0 8. "OFF_STATE,Indicates status of Power-OFF sequence." "0: Not processing Power-OFF sequence,1: Processing Power OFF sequence" newline bitfld.long 0x0 4. "ON,Indicates Power-ON state." "0: Not Power-ON state,1: Power-ON state" bitfld.long 0x0 0. "OFF,Indicates Power-OFF state." "0: Not Power-OFF state,1: Power-OFF state" wgroup.long 0x1004++0x3 line.long 0x0 "PDRONCR0,Power Domain Power-ON Control Register 0" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1044++0x3 line.long 0x0 "PDRONCR1,Power Domain Power-ON Control Register 1" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1084++0x3 line.long 0x0 "PDRONCR2,Power Domain Power-ON Control Register 2" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x10C4++0x3 line.long 0x0 "PDRONCR3,Power Domain Power-ON Control Register 3" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1104++0x3 line.long 0x0 "PDRONCR4,Power Domain Power-ON Control Register 4" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1144++0x3 line.long 0x0 "PDRONCR5,Power Domain Power-ON Control Register 5" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1184++0x3 line.long 0x0 "PDRONCR6,Power Domain Power-ON Control Register 6" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x11C4++0x3 line.long 0x0 "PDRONCR7,Power Domain Power-ON Control Register 7" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1204++0x3 line.long 0x0 "PDRONCR8,Power Domain Power-ON Control Register 8" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1244++0x3 line.long 0x0 "PDRONCR9,Power Domain Power-ON Control Register 9" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1284++0x3 line.long 0x0 "PDRONCR10,Power Domain Power-ON Control Register 10" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x12C4++0x3 line.long 0x0 "PDRONCR11,Power Domain Power-ON Control Register 11" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1304++0x3 line.long 0x0 "PDRONCR12,Power Domain Power-ON Control Register 12" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1344++0x3 line.long 0x0 "PDRONCR13,Power Domain Power-ON Control Register 13" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1384++0x3 line.long 0x0 "PDRONCR14,Power Domain Power-ON Control Register 14" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x13C4++0x3 line.long 0x0 "PDRONCR15,Power Domain Power-ON Control Register 15" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1404++0x3 line.long 0x0 "PDRONCR16,Power Domain Power-ON Control Register 16" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1444++0x3 line.long 0x0 "PDRONCR17,Power Domain Power-ON Control Register 17" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1484++0x3 line.long 0x0 "PDRONCR18,Power Domain Power-ON Control Register 18" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x14C4++0x3 line.long 0x0 "PDRONCR19,Power Domain Power-ON Control Register 19" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1504++0x3 line.long 0x0 "PDRONCR20,Power Domain Power-ON Control Register 20" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1544++0x3 line.long 0x0 "PDRONCR21,Power Domain Power-ON Control Register 21" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1584++0x3 line.long 0x0 "PDRONCR22,Power Domain Power-ON Control Register 22" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x15C4++0x3 line.long 0x0 "PDRONCR23,Power Domain Power-ON Control Register 23" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1604++0x3 line.long 0x0 "PDRONCR24,Power Domain Power-ON Control Register 24" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1644++0x3 line.long 0x0 "PDRONCR25,Power Domain Power-ON Control Register 25" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1684++0x3 line.long 0x0 "PDRONCR26,Power Domain Power-ON Control Register 26" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x16C4++0x3 line.long 0x0 "PDRONCR27,Power Domain Power-ON Control Register 27" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1704++0x3 line.long 0x0 "PDRONCR28,Power Domain Power-ON Control Register 28" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1744++0x3 line.long 0x0 "PDRONCR29,Power Domain Power-ON Control Register 29" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1784++0x3 line.long 0x0 "PDRONCR30,Power Domain Power-ON Control Register 30" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x17C4++0x3 line.long 0x0 "PDRONCR31,Power Domain Power-ON Control Register 31" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1804++0x3 line.long 0x0 "PDRONCR32,Power Domain Power-ON Control Register 32" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1844++0x3 line.long 0x0 "PDRONCR33,Power Domain Power-ON Control Register 33" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1884++0x3 line.long 0x0 "PDRONCR34,Power Domain Power-ON Control Register 34" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x18C4++0x3 line.long 0x0 "PDRONCR35,Power Domain Power-ON Control Register 35" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1904++0x3 line.long 0x0 "PDRONCR36,Power Domain Power-ON Control Register 36" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1944++0x3 line.long 0x0 "PDRONCR37,Power Domain Power-ON Control Register 37" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1984++0x3 line.long 0x0 "PDRONCR38,Power Domain Power-ON Control Register 38" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x19C4++0x3 line.long 0x0 "PDRONCR39,Power Domain Power-ON Control Register 39" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A04++0x3 line.long 0x0 "PDRONCR40,Power Domain Power-ON Control Register 40" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A44++0x3 line.long 0x0 "PDRONCR41,Power Domain Power-ON Control Register 41" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1A84++0x3 line.long 0x0 "PDRONCR42,Power Domain Power-ON Control Register 42" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1AC4++0x3 line.long 0x0 "PDRONCR43,Power Domain Power-ON Control Register 43" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B04++0x3 line.long 0x0 "PDRONCR44,Power Domain Power-ON Control Register 44" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B44++0x3 line.long 0x0 "PDRONCR45,Power Domain Power-ON Control Register 45" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1B84++0x3 line.long 0x0 "PDRONCR46,Power Domain Power-ON Control Register 46" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1BC4++0x3 line.long 0x0 "PDRONCR47,Power Domain Power-ON Control Register 47" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C04++0x3 line.long 0x0 "PDRONCR48,Power Domain Power-ON Control Register 48" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C44++0x3 line.long 0x0 "PDRONCR49,Power Domain Power-ON Control Register 49" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1C84++0x3 line.long 0x0 "PDRONCR50,Power Domain Power-ON Control Register 50" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1CC4++0x3 line.long 0x0 "PDRONCR51,Power Domain Power-ON Control Register 51" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D04++0x3 line.long 0x0 "PDRONCR52,Power Domain Power-ON Control Register 52" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D44++0x3 line.long 0x0 "PDRONCR53,Power Domain Power-ON Control Register 53" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1D84++0x3 line.long 0x0 "PDRONCR54,Power Domain Power-ON Control Register 54" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1DC4++0x3 line.long 0x0 "PDRONCR55,Power Domain Power-ON Control Register 55" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E04++0x3 line.long 0x0 "PDRONCR56,Power Domain Power-ON Control Register 56" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E44++0x3 line.long 0x0 "PDRONCR57,Power Domain Power-ON Control Register 57" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1E84++0x3 line.long 0x0 "PDRONCR58,Power Domain Power-ON Control Register 58" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1EC4++0x3 line.long 0x0 "PDRONCR59,Power Domain Power-ON Control Register 59" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F04++0x3 line.long 0x0 "PDRONCR60,Power Domain Power-ON Control Register 60" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F44++0x3 line.long 0x0 "PDRONCR61,Power Domain Power-ON Control Register 61" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1F84++0x3 line.long 0x0 "PDRONCR62,Power Domain Power-ON Control Register 62" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1FC4++0x3 line.long 0x0 "PDRONCR63,Power Domain Power-ON Control Register 63" bitfld.long 0x0 0. "PWRON,Power-ON request." "0,1" wgroup.long 0x1008++0x3 line.long 0x0 "PDROFFCR0,Power Domain Power-OFF Control Register 0" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1048++0x3 line.long 0x0 "PDROFFCR1,Power Domain Power-OFF Control Register 1" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1088++0x3 line.long 0x0 "PDROFFCR2,Power Domain Power-OFF Control Register 2" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x10C8++0x3 line.long 0x0 "PDROFFCR3,Power Domain Power-OFF Control Register 3" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1108++0x3 line.long 0x0 "PDROFFCR4,Power Domain Power-OFF Control Register 4" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1148++0x3 line.long 0x0 "PDROFFCR5,Power Domain Power-OFF Control Register 5" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1188++0x3 line.long 0x0 "PDROFFCR6,Power Domain Power-OFF Control Register 6" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x11C8++0x3 line.long 0x0 "PDROFFCR7,Power Domain Power-OFF Control Register 7" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1208++0x3 line.long 0x0 "PDROFFCR8,Power Domain Power-OFF Control Register 8" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1248++0x3 line.long 0x0 "PDROFFCR9,Power Domain Power-OFF Control Register 9" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1288++0x3 line.long 0x0 "PDROFFCR10,Power Domain Power-OFF Control Register 10" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x12C8++0x3 line.long 0x0 "PDROFFCR11,Power Domain Power-OFF Control Register 11" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1308++0x3 line.long 0x0 "PDROFFCR12,Power Domain Power-OFF Control Register 12" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1348++0x3 line.long 0x0 "PDROFFCR13,Power Domain Power-OFF Control Register 13" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1388++0x3 line.long 0x0 "PDROFFCR14,Power Domain Power-OFF Control Register 14" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x13C8++0x3 line.long 0x0 "PDROFFCR15,Power Domain Power-OFF Control Register 15" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1408++0x3 line.long 0x0 "PDROFFCR16,Power Domain Power-OFF Control Register 16" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1448++0x3 line.long 0x0 "PDROFFCR17,Power Domain Power-OFF Control Register 17" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1488++0x3 line.long 0x0 "PDROFFCR18,Power Domain Power-OFF Control Register 18" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x14C8++0x3 line.long 0x0 "PDROFFCR19,Power Domain Power-OFF Control Register 19" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1508++0x3 line.long 0x0 "PDROFFCR20,Power Domain Power-OFF Control Register 20" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1548++0x3 line.long 0x0 "PDROFFCR21,Power Domain Power-OFF Control Register 21" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1588++0x3 line.long 0x0 "PDROFFCR22,Power Domain Power-OFF Control Register 22" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x15C8++0x3 line.long 0x0 "PDROFFCR23,Power Domain Power-OFF Control Register 23" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1608++0x3 line.long 0x0 "PDROFFCR24,Power Domain Power-OFF Control Register 24" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1648++0x3 line.long 0x0 "PDROFFCR25,Power Domain Power-OFF Control Register 25" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1688++0x3 line.long 0x0 "PDROFFCR26,Power Domain Power-OFF Control Register 26" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x16C8++0x3 line.long 0x0 "PDROFFCR27,Power Domain Power-OFF Control Register 27" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1708++0x3 line.long 0x0 "PDROFFCR28,Power Domain Power-OFF Control Register 28" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1748++0x3 line.long 0x0 "PDROFFCR29,Power Domain Power-OFF Control Register 29" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1788++0x3 line.long 0x0 "PDROFFCR30,Power Domain Power-OFF Control Register 30" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x17C8++0x3 line.long 0x0 "PDROFFCR31,Power Domain Power-OFF Control Register 31" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1808++0x3 line.long 0x0 "PDROFFCR32,Power Domain Power-OFF Control Register 32" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1848++0x3 line.long 0x0 "PDROFFCR33,Power Domain Power-OFF Control Register 33" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1888++0x3 line.long 0x0 "PDROFFCR34,Power Domain Power-OFF Control Register 34" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x18C8++0x3 line.long 0x0 "PDROFFCR35,Power Domain Power-OFF Control Register 35" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1908++0x3 line.long 0x0 "PDROFFCR36,Power Domain Power-OFF Control Register 36" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1948++0x3 line.long 0x0 "PDROFFCR37,Power Domain Power-OFF Control Register 37" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1988++0x3 line.long 0x0 "PDROFFCR38,Power Domain Power-OFF Control Register 38" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x19C8++0x3 line.long 0x0 "PDROFFCR39,Power Domain Power-OFF Control Register 39" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A08++0x3 line.long 0x0 "PDROFFCR40,Power Domain Power-OFF Control Register 40" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A48++0x3 line.long 0x0 "PDROFFCR41,Power Domain Power-OFF Control Register 41" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1A88++0x3 line.long 0x0 "PDROFFCR42,Power Domain Power-OFF Control Register 42" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1AC8++0x3 line.long 0x0 "PDROFFCR43,Power Domain Power-OFF Control Register 43" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B08++0x3 line.long 0x0 "PDROFFCR44,Power Domain Power-OFF Control Register 44" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B48++0x3 line.long 0x0 "PDROFFCR45,Power Domain Power-OFF Control Register 45" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1B88++0x3 line.long 0x0 "PDROFFCR46,Power Domain Power-OFF Control Register 46" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1BC8++0x3 line.long 0x0 "PDROFFCR47,Power Domain Power-OFF Control Register 47" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C08++0x3 line.long 0x0 "PDROFFCR48,Power Domain Power-OFF Control Register 48" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C48++0x3 line.long 0x0 "PDROFFCR49,Power Domain Power-OFF Control Register 49" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1C88++0x3 line.long 0x0 "PDROFFCR50,Power Domain Power-OFF Control Register 50" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1CC8++0x3 line.long 0x0 "PDROFFCR51,Power Domain Power-OFF Control Register 51" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D08++0x3 line.long 0x0 "PDROFFCR52,Power Domain Power-OFF Control Register 52" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D48++0x3 line.long 0x0 "PDROFFCR53,Power Domain Power-OFF Control Register 53" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1D88++0x3 line.long 0x0 "PDROFFCR54,Power Domain Power-OFF Control Register 54" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1DC8++0x3 line.long 0x0 "PDROFFCR55,Power Domain Power-OFF Control Register 55" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E08++0x3 line.long 0x0 "PDROFFCR56,Power Domain Power-OFF Control Register 56" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E48++0x3 line.long 0x0 "PDROFFCR57,Power Domain Power-OFF Control Register 57" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1E88++0x3 line.long 0x0 "PDROFFCR58,Power Domain Power-OFF Control Register 58" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1EC8++0x3 line.long 0x0 "PDROFFCR59,Power Domain Power-OFF Control Register 59" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F08++0x3 line.long 0x0 "PDROFFCR60,Power Domain Power-OFF Control Register 60" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F48++0x3 line.long 0x0 "PDROFFCR61,Power Domain Power-OFF Control Register 61" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1F88++0x3 line.long 0x0 "PDROFFCR62,Power Domain Power-OFF Control Register 62" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" wgroup.long 0x1FC8++0x3 line.long 0x0 "PDROFFCR63,Power Domain Power-OFF Control Register 63" bitfld.long 0x0 0. "PWROFF,Power-OFF request." "0,1" group.long 0x3000++0x17 line.long 0x0 "SYSCD0WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD0WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD0WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD0WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD0WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD0WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D0WACRm,Domain[n] Write access control for Common Registers." group.long 0x3020++0x17 line.long 0x0 "SYSCD1WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD1WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD1WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD1WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD1WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD1WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D1WACRm,Domain[n] Write access control for Common Registers." group.long 0x3040++0x17 line.long 0x0 "SYSCD2WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD2WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD2WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD2WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD2WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD2WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D2WACRm,Domain[n] Write access control for Common Registers." group.long 0x3060++0x17 line.long 0x0 "SYSCD3WACR0,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x0 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x4 "SYSCD3WACR1,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x4 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x8 "SYSCD3WACR2,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x8 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0xC "SYSCD3WACR3,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0xC 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x10 "SYSCD3WACR4,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x10 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." line.long 0x14 "SYSCD3WACR5,This register can be written by only Domain0 address. (H’E618_0000- H’E618_3FFC)" hexmask.long 0x14 0.--31. 1. "D3WACRm,Domain[n] Write access control for Common Registers." tree.end tree.end tree "TMU" base ad:0x0 tree "TMU_0" base ad:0xE61E0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_1" base ad:0xE61E0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_2" base ad:0xE61E0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_3" base ad:0xE6FC0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_4" base ad:0xE6FC0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_5" base ad:0xE6FC0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_6" base ad:0xE6FD0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_7" base ad:0xE6FD0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_8" base ad:0xE6FD0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_9" base ad:0xE6FE0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_10" base ad:0xE6FE0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_11" base ad:0xE6FE0000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_12" base ad:0xFFC00000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_13" base ad:0xFFC00000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree "TMU_14" base ad:0xFFC00000 rgroup.long 0x2C++0x3 line.long 0x0 "TCPR5,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR5" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR8,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function. When.." hexmask.long 0x0 0.--31. 1. "TCPR8" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR11,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR11" rgroup.long 0x2C++0x3 line.long 0x0 "TCPR14,TCPR5. TCPR8. TCPR11*1 and TCPR14*1 are read-only 32-bit registers used for the input capture function provided only in channels 5. 8. 11*1 and 14*1. The ICPE and CKEG bits in TCR5. TCR8. TCR11*1 and TCR14*1 control the input capture function." hexmask.long 0x0 0.--31. 1. "TCPR14" group.byte 0x4++0x0 line.byte 0x0 "TSTR0,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR2,Counter Start 2" "0: TCNT2 count halted,1: TCNT2 counts" bitfld.byte 0x0 1. "STR1,Counter Start 1" "0: TCNT1 count halted,1: TCNT1 counts" bitfld.byte 0x0 0. "STR0,Counter Start 0" "0: TCNT0 count halted,1: TCNT0 counts" group.long 0x8++0x7 line.long 0x0 "TCOR0,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR0" line.long 0x4 "TCNT0,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT0" group.word 0x10++0x1 line.word 0x0 "TCR0,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x17 line.long 0x0 "TCOR1,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR1" line.long 0x4 "TCNT1,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT1" line.long 0x8 "TCR1,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x8 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x8 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x8 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x8 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" line.long 0xC "TCOR2,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0xC 0.--31. 1. "TCOR2" line.long 0x10 "TCNT2,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x10 0.--31. 1. "TCNT2" line.long 0x14 "TCR2,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.long 0x14 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.long 0x14 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.long 0x14 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.long 0x14 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR3,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR5,Counter Start 5" "0: TCNT5 count halted,1: TCNT5 counts" bitfld.byte 0x0 1. "STR4,Counter Start 4" "0: TCNT4 count halted,1: TCNT4 counts" bitfld.byte 0x0 0. "STR3,Counter Start 3" "0: TCNT3 count halted,1: TCNT3 counts" group.long 0x8++0x7 line.long 0x0 "TCOR3,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR3" line.long 0x4 "TCNT3,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT3" group.word 0x10++0x1 line.word 0x0 "TCR3,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR4,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR4" line.long 0x4 "TCNT4,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT4" group.word 0x1C++0x1 line.word 0x0 "TCR4,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR5,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR5" line.long 0x4 "TCNT5,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT5" group.word 0x28++0x1 line.word 0x0 "TCR5,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR6,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR8,Counter Start 8" "0: TCNT8 count halted,1: TCNT8 counts" bitfld.byte 0x0 1. "STR7,Counter Start 7" "0: TCNT7 count halted,1: TCNT7 counts" bitfld.byte 0x0 0. "STR6,Counter Start 6" "0: TCNT6 count halted,1: TCNT6 counts" group.long 0x8++0x7 line.long 0x0 "TCOR6,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR6" line.long 0x4 "TCNT6,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT6" group.word 0x10++0x1 line.word 0x0 "TCR6,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR7,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR7" line.long 0x4 "TCNT7,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT7" group.word 0x1C++0x1 line.word 0x0 "TCR7,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR8,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR8" line.long 0x4 "TCNT8,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT8" group.word 0x28++0x1 line.word 0x0 "TCR8,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR9,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR11,Counter Start 11" "0: TCNT11 count halted,1: TCNT11 counts" bitfld.byte 0x0 1. "STR10,Counter Start 10" "0: TCNT10 count halted,1: TCNT10 counts" bitfld.byte 0x0 0. "STR9,Counter Start 9" "0: TCNT9 count halted,1: TCNT9 counts" group.long 0x8++0x7 line.long 0x0 "TCOR9,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR9" line.long 0x4 "TCNT9,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT9" group.word 0x10++0x1 line.word 0x0 "TCR9,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR10,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR10" line.long 0x4 "TCNT10,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT10" group.word 0x1C++0x1 line.word 0x0 "TCR10,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR11,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR11" line.long 0x4 "TCNT11,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT11" group.word 0x28++0x1 line.word 0x0 "TCR11,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.byte 0x4++0x0 line.byte 0x0 "TSTR12,TSTR are 8-bit readable/writable registers that select whether to run or halt the TCNT." bitfld.byte 0x0 2. "STR14,Counter Start 14" "0: TCNT14 count halted,1: TCNT14 counts" bitfld.byte 0x0 1. "STR13,Counter Start 13" "0: TCNT13 count halted,1: TCNT13 counts" bitfld.byte 0x0 0. "STR12,Counter Start 12" "0: TCNT12 count halted,1: TCNT12 counts" group.long 0x8++0x7 line.long 0x0 "TCOR12,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR12" line.long 0x4 "TCNT12,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT12" group.word 0x10++0x1 line.word 0x0 "TCR12,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x14++0x7 line.long 0x0 "TCOR13,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR13" line.long 0x4 "TCNT13,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT13" group.word 0x1C++0x1 line.word 0x0 "TCR13,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" newline bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" group.long 0x20++0x7 line.long 0x0 "TCOR14,TCOR are 32-bit readable/writable registers. After underflow has been generated according to the result of the TCNT countdown. the value of TCOR is set to TCNT and TCNT continues countdown from the value." hexmask.long 0x0 0.--31. 1. "TCOR14" line.long 0x4 "TCNT14,TCNT are 32-bit readable/writable registers that count down upon the input clock selected using the bits TPSC2 to TPSC0 in TCR." hexmask.long 0x4 0.--31. 1. "TCNT14" group.word 0x28++0x1 line.word 0x0 "TCR14,TCR are 16-bit readable/writable registers that select a count clock and edge when an external clock is selected. and control an interrupt generation when the flag that indicates the generation of a TCNT is set to 1." bitfld.word 0x0 9. "ICPF,Input Capture Interrupt Flag" "0: No input capture has occurred,1: Input capture has occurred" bitfld.word 0x0 8. "UNF,Underflow Flag" "0: TCNT has not underflowed,1: TCNT has underflowed" bitfld.word 0x0 6.--7. "ICPE,Input Capture Control" "0: Input capture function is not used,1: Reserved,?,?" newline bitfld.word 0x0 5. "UNIE,Underflow Interrupt Control" "0: Interrupt due to underflow,1: Interrupt due to underflow" bitfld.word 0x0 3.--4. "CKEG,Clock Edge" "0: Count/capture register set on rising edge,1: Count/capture register set on falling edge,?,?" bitfld.word 0x0 0.--2. "TPSC,Timer Pre-scaler 2 to 0" "0: Count on,1: Count on,?,?,?,?,?,?" tree.end tree.end tree "TPU" base ad:0xE6E80000 group.word 0x0++0x1 line.word 0x0 "TSTR,TSTR is used to start or stop the timer counter (TCNT) of timers 0 to 3." bitfld.word 0x0 4. "TMST,Motor Control Sequence Start" "0: Stops motor control sequence,1: Starts motor control sequence" bitfld.word 0x0 3. "CST3,Counter Start" "0: Stops the TCNT3 counting operation,1: Starts the TCNT3 counting operation" newline bitfld.word 0x0 2. "CST2,Counter Start" "0: Stops the TCNT2 counting operation,1: Starts the TCNT2 counting operation" bitfld.word 0x0 1. "CST1,Counter Start" "0: Stops the TCNT1 counting operation,1: Starts the TCNT1 counting operation" newline bitfld.word 0x0 0. "CST0,Counter Start" "0: Stops the TCNT0 counting operation,1: Starts the TCNT0 counting operation" group.word 0x100++0x1 line.word 0x0 "TMIR,TMIR is used to configure operation in the motor control mode." bitfld.word 0x0 4. "TDMAE,Selection of DMA Use" "0: DMA is not used,1: DMA is used" bitfld.word 0x0 3. "MTRPATDOWN,Operation and Stop Patterns Transition Ascending/Descending Select" "0: Ascending,1: Descending" newline bitfld.word 0x0 1.--2. "MTRPATKIND[1:0|,Operation and Stop Pattern Type Select" "0: Four,1: Eight,?,?" bitfld.word 0x0 0. "MTRON,TPU Mode/Stepping Motor Control Mode Select" "0: TPU mode,1: Stepping motor control mode" group.word 0x104++0x1 line.word 0x0 "TMRR,TMRR is used to place timer 0 in to the deceleration state from the normal state. in the motor control mode." bitfld.word 0x0 1. "REDUON0,This bit is used to force a transition of timer 0 to the deceleration (or stop) state from the normal state in motor control mode. Note that the state transition only proceeds when pattern 0 is the currently specified pattern. Setting this bit.." "0: No operation,1: Timer 0 is forcibly placed in the deceleration" bitfld.word 0x0 0. "REDUON,This bit is used to force a transition of timer 0 to the deceleration (or stop) state from the normal state in motor control mode. Setting this bit has no effect if timer 0 is not in the normal state. This bit is automatically cleared to 0 when.." "0: No operation,1: Timer 0 is forcibly placed in the deceleration" rgroup.word 0x108++0x1 line.word 0x0 "TMSR,TMSR is a read-only register that indicates the sequence state in motor control mode." bitfld.word 0x0 3. "SITR,This bit indicates the sequence state in motor control mode." "0: The sequence state is not deceleration,1: The sequence state is deceleration" bitfld.word 0x0 2. "SITT,This bit indicates the sequence state in motor control mode." "0: The sequence state is not normal,1: The sequence state is normal" newline bitfld.word 0x0 1. "SITA,This bit indicates the sequence state in motor control mode." "0: The sequence state is not acceleration,1: The sequence state is acceleration" bitfld.word 0x0 0. "SITS,This bit indicates the sequence state in motor control mode." "0: The sequence state is not stop,1: The sequence state is stop" group.word 0x110++0x1 line.word 0x0 "TMMPR0,TMMPR0 is used to set motor operation patterns [3] to [0] in motor control mode." bitfld.word 0x0 15. "MP33,Motor Operation Pattern [3] in Motor Control Mode" "0,1" bitfld.word 0x0 14. "MP33,Motor Operation Pattern [3] in Motor Control Mode" "0,1" newline bitfld.word 0x0 13. "MP33,Motor Operation Pattern [3] in Motor Control Mode" "0,1" bitfld.word 0x0 12. "MP33,Motor Operation Pattern [3] in Motor Control Mode" "0,1" newline bitfld.word 0x0 11. "MP23,Motor Operation Pattern [2] in Motor Control Mode" "0,1" bitfld.word 0x0 10. "MP23,Motor Operation Pattern [2] in Motor Control Mode" "0,1" newline bitfld.word 0x0 9. "MP23,Motor Operation Pattern [2] in Motor Control Mode" "0,1" bitfld.word 0x0 8. "MP23,Motor Operation Pattern [2] in Motor Control Mode" "0,1" newline bitfld.word 0x0 7. "MP13,Motor Operation Pattern [1] in Motor Control Mode" "0,1" bitfld.word 0x0 6. "MP13,Motor Operation Pattern [1] in Motor Control Mode" "0,1" newline bitfld.word 0x0 5. "MP13,Motor Operation Pattern [1] in Motor Control Mode" "0,1" bitfld.word 0x0 4. "MP13,Motor Operation Pattern [1] in Motor Control Mode" "0,1" newline bitfld.word 0x0 3. "MP03,Motor Operation Pattern [0] in Motor Control Mode" "0,1" bitfld.word 0x0 2. "MP03,Motor Operation Pattern [0] in Motor Control Mode" "0,1" newline bitfld.word 0x0 1. "MP03,Motor Operation Pattern [0] in Motor Control Mode" "0,1" bitfld.word 0x0 0. "MP03,Motor Operation Pattern [0] in Motor Control Mode" "0,1" group.word 0x114++0x1 line.word 0x0 "TMMPR1,TMMPR1 is used to set motor operation pattern [7] to [4] in motor control mode." bitfld.word 0x0 15. "MP73,Motor Operation Pattern [7] in Motor Control Mode" "0,1" bitfld.word 0x0 14. "MP73,Motor Operation Pattern [7] in Motor Control Mode" "0,1" newline bitfld.word 0x0 13. "MP73,Motor Operation Pattern [7] in Motor Control Mode" "0,1" bitfld.word 0x0 12. "MP73,Motor Operation Pattern [7] in Motor Control Mode" "0,1" newline bitfld.word 0x0 11. "MP63,Motor Operation Pattern [6] in Motor Control Mode" "0,1" bitfld.word 0x0 10. "MP63,Motor Operation Pattern [6] in Motor Control Mode" "0,1" newline bitfld.word 0x0 9. "MP63,Motor Operation Pattern [6] in Motor Control Mode" "0,1" bitfld.word 0x0 8. "MP63,Motor Operation Pattern [6] in Motor Control Mode" "0,1" newline bitfld.word 0x0 7. "MP53,Motor Operation Pattern [5] in Motor Control Mode" "0,1" bitfld.word 0x0 6. "MP53,Motor Operation Pattern [5] in Motor Control Mode" "0,1" newline bitfld.word 0x0 5. "MP53,Motor Operation Pattern [5] in Motor Control Mode" "0,1" bitfld.word 0x0 4. "MP53,Motor Operation Pattern [5] in Motor Control Mode" "0,1" newline bitfld.word 0x0 3. "MP43,Motor Operation Pattern [4] in Motor Control Mode" "0,1" bitfld.word 0x0 2. "MP43,Motor Operation Pattern [4] in Motor Control Mode" "0,1" newline bitfld.word 0x0 1. "MP43,Motor Operation Pattern [4] in Motor Control Mode" "0,1" bitfld.word 0x0 0. "MP43,Motor Operation Pattern [4] in Motor Control Mode" "0,1" group.word 0x118++0x1 line.word 0x0 "TMSPR0,TMSPR0 is used to set motor stop pattern (3) to (0) in motor control mode." bitfld.word 0x0 15. "SP33,Motor Stop Pattern (3) in Motor Control Mode" "0,1" bitfld.word 0x0 14. "SP33,Motor Stop Pattern (3) in Motor Control Mode" "0,1" newline bitfld.word 0x0 13. "SP33,Motor Stop Pattern (3) in Motor Control Mode" "0,1" bitfld.word 0x0 12. "SP33,Motor Stop Pattern (3) in Motor Control Mode" "0,1" newline bitfld.word 0x0 11. "SP23,Motor Stop Pattern (2) in Motor Control Mode" "0,1" bitfld.word 0x0 10. "SP23,Motor Stop Pattern (2) in Motor Control Mode" "0,1" newline bitfld.word 0x0 9. "SP23,Motor Stop Pattern (2) in Motor Control Mode" "0,1" bitfld.word 0x0 8. "SP23,Motor Stop Pattern (2) in Motor Control Mode" "0,1" newline bitfld.word 0x0 7. "SP13,Motor Stop Pattern (1) in Motor Control Mode" "0,1" bitfld.word 0x0 6. "SP13,Motor Stop Pattern (1) in Motor Control Mode" "0,1" newline bitfld.word 0x0 5. "SP13,Motor Stop Pattern (1) in Motor Control Mode" "0,1" bitfld.word 0x0 4. "SP13,Motor Stop Pattern (1) in Motor Control Mode" "0,1" newline bitfld.word 0x0 3. "SP03,Motor Stop Pattern (0) in Motor Control Mode" "0,1" bitfld.word 0x0 2. "SP03,Motor Stop Pattern (0) in Motor Control Mode" "0,1" newline bitfld.word 0x0 1. "SP03,Motor Stop Pattern (0) in Motor Control Mode" "0,1" bitfld.word 0x0 0. "SP03,Motor Stop Pattern (0) in Motor Control Mode" "0,1" group.word 0x11C++0x1 line.word 0x0 "TMSPR1,TMSPR1 is used to set motor stop pattern (7) to (4) in motor control mode." bitfld.word 0x0 15. "SP73,Motor Stop Pattern (7) in Motor Control Mode" "0,1" bitfld.word 0x0 14. "SP73,Motor Stop Pattern (7) in Motor Control Mode" "0,1" newline bitfld.word 0x0 13. "SP73,Motor Stop Pattern (7) in Motor Control Mode" "0,1" bitfld.word 0x0 12. "SP73,Motor Stop Pattern (7) in Motor Control Mode" "0,1" newline bitfld.word 0x0 11. "SP63,Motor Stop Pattern (6) in Motor Control Mode" "0,1" bitfld.word 0x0 10. "SP63,Motor Stop Pattern (6) in Motor Control Mode" "0,1" newline bitfld.word 0x0 9. "SP63,Motor Stop Pattern (6) in Motor Control Mode" "0,1" bitfld.word 0x0 8. "SP63,Motor Stop Pattern (6) in Motor Control Mode" "0,1" newline bitfld.word 0x0 7. "SP53,Motor Stop Pattern (5) in Motor Control Mode" "0,1" bitfld.word 0x0 6. "SP53,Motor Stop Pattern (5) in Motor Control Mode" "0,1" newline bitfld.word 0x0 5. "SP53,Motor Stop Pattern (5) in Motor Control Mode" "0,1" bitfld.word 0x0 4. "SP53,Motor Stop Pattern (5) in Motor Control Mode" "0,1" newline bitfld.word 0x0 3. "SP43,Motor Stop Pattern (4) in Motor Control Mode" "0,1" bitfld.word 0x0 2. "SP43,Motor Stop Pattern (4) in Motor Control Mode" "0,1" newline bitfld.word 0x0 1. "SP43,Motor Stop Pattern (4) in Motor Control Mode" "0,1" bitfld.word 0x0 0. "SP43,Motor Stop Pattern (4) in Motor Control Mode" "0,1" group.word 0x120++0x1 line.word 0x0 "TMOPR,TMOPR is used to specify the motor output pattern in motor control mode. When read. it indicates the pattern currently being output. Writing to this register while the sequence is in the stop state leads to output of the pattern with the.." bitfld.word 0x0 0.--2. "NOWPAT,In motor control mode " "0,1,2,3,4,5,6,7" group.word 0x130++0x1 line.word 0x0 "TMASR,TMASR is used to set the number of steps in the acceleration state of motor control mode. TMASR is initialized to H'0000 by a reset." hexmask.word 0x0 0.--15. 1. "AS,Specify the number of steps in the acceleration state of motor control mode." group.word 0x134++0x1 line.word 0x0 "TMTSR,TMTSR is used to set the number of steps in the normal state of motor control mode. TMTSR is initialized to H'0000 by a reset." hexmask.word 0x0 0.--15. 1. "TS,Specify the number of steps in the normal state of motor control mode." group.word 0x138++0x1 line.word 0x0 "TMRSR,TMRSR is used to set the number of steps in the deceleration state of motor control mode. TMRSR is initialized to H'0000 by a reset." hexmask.word 0x0 0.--15. 1. "RS,Specify the number of steps in the deceleration state of motor control mode." group.word 0x140++0x1 line.word 0x0 "TMSCR,TMSCR indicates or controls the value of the sequence counter in motor control mode. Writing to this register is only allowed when the motor control mode is in use and the current state is the normal state." hexmask.word 0x0 0.--15. 1. "SC,Value of Sequence Counter in Motor Control Mode" rgroup.word 0x144++0x1 line.word 0x0 "TMTCR,TMTCR is a read-only register that indicates the number of steps in the normal state of motor control mode. TMTCR is initialized to H'0000 by a reset." hexmask.word 0x0 0.--15. 1. "TCR,Indicate the number of steps in the normal state of motor control mode." tree.end tree "TSC" base ad:0x0 tree "TSC_0" base ad:0xE6190000 rgroup.long 0x0++0x3 line.long 0x0 "THSIRQSTR,THS Temperature Error Status Register" bitfld.long 0x0 2. "IRQ3,Temperature Error3 Status" "0: Not detected,1: Temperature Error3 for thermal sensor is detected" newline bitfld.long 0x0 1. "IRQ2,Temperature Error2 Status" "0: Not detected,1: Temperature Error2 for thermal sensor is detected" newline bitfld.long 0x0 0. "IRQ1,Temperature Error1 Status" "0: Not detected,1: Temperature Error1 for thermal sensor is detected" group.long 0x4++0x1F line.long 0x0 "IRQSTR,Temperature Error Status Register" bitfld.long 0x0 5. "TEMPD3_STR,TEMPD3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 4. "TEMPD2_STR,TEMPD2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 3. "TEMPD1_STR,TEMPD1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 2. "TEMP3_STR,TEMP3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." newline bitfld.long 0x0 1. "TEMP2_STR,TEMP2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." newline bitfld.long 0x0 0. "TEMP1_STR,TEMP1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." line.long 0x4 "IRQMSK,Temperature Error Mask Register" bitfld.long 0x4 5. "TEMPD3_MSK,This bit selects masking or non-masking of TEMPD3 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 4. "TEMPD2_MSK,This bit selects masking or non-masking of TEMPD2 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 3. "TEMPD1_MSK,This bit selects masking or non-masking of TEMPD1 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 2. "TEMP3_MSK,This bit selects masking or non-masking of TEMP3 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 1. "TEMP2_MSK,This bit selects masking or non-masking of TEMP2 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 0. "TEMP1_MSK,This bit selects masking or non-masking of TEMP1 error requests." "0: Errors are masked,1: The mask is cleared" line.long 0x8 "IRQCTL,Threshold Edge/Level Register" bitfld.long 0x8 5. "TEMPD3_EL,Specifies the method for detection of the TEMPD3 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 4. "TEMPD2_EL,Specifies the method for detection of the TEMPD2 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 3. "TEMPD1_EL,Specifies the method for detection of the TEMPD1 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 2. "TEMP3_EL,Specifies the method for detection of the TEMP3 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 1. "TEMP2_EL,Specifies the method for detection of the TEMP2 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 0. "TEMP1_EL,Specifies the method for detection of the TEMP1 error signal input." "0: Edge detection,1: Level detection" line.long 0xC "IRQEN,Temperature Error Enable Register" bitfld.long 0xC 5. "TEMPD3_EN,This bit enables or disables TEMPD3 errors." "0: TEMPD3 errors are disabled,1: TEMPD3 errors are enabled" newline bitfld.long 0xC 4. "TEMPD2_EN,This bit enables or disables TEMPD2 errors." "0: TEMPD2 errors are disabled,1: TEMPD2 errors are enabled" newline bitfld.long 0xC 3. "TEMPD1_EN,This bit enables or disables TEMPD1 errors." "0: TEMPD1 errors are disabled,1: TEMPD1 errors are enabled" newline bitfld.long 0xC 2. "TEMP3_EN,This bit enables or disables TEMP3 errors." "0: TEMP3 errors are disabled,1: TEMP3 errors are enabled" newline bitfld.long 0xC 1. "TEMP2_EN,This bit enables or disables TEMP2 errors." "0: TEMP2 errors are disabled,1: TEMP2 errors are enabled" newline bitfld.long 0xC 0. "TEMP1_EN,This bit enables or disables TEMP1 errors." "0: TEMP1 errors are disabled,1: TEMP1 errors are enabled" line.long 0x10 "IRQTEMP1,Temperature Error 1 Register" bitfld.long 0x10 12.--13. "IRQTEMP1,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors." "0,1,2,3" newline hexmask.long.word 0x10 0.--11. 1. "IRQTEMP1,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors." line.long 0x14 "IRQTEMP2,Temperature Error 2 Register" bitfld.long 0x14 12.--13. "IRQTEMP2,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors." "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "IRQTEMP2,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors." line.long 0x18 "IRQTEMP3,Temperature Error 3 Register" bitfld.long 0x18 12.--13. "IRQTEMP3,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors." "0,1,2,3" newline hexmask.long.word 0x18 0.--11. 1. "IRQTEMP3,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors." line.long 0x1C "THCTR,Control Register" bitfld.long 0x1C 28.--30. "VOLSELB,Select the chip internal voltage monitor input" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline bitfld.long 0x1C 24. "CTCTL,Select write condition of THREFTAP THCNTSEN and VMCNTSEN" "0: Inhibit write of these bits,1: Allow write of these bits" newline bitfld.long 0x1C 20. "CIVMTST,THS/CIVM failure check mode" "0: Normal mode,1: THS/CIVM failure check mode" newline bitfld.long 0x1C 18.--19. "VMCNTSEN,Select the bit number of A/D converter in CIVM" "0: 10bits,1: 12bits,?,?" newline bitfld.long 0x1C 16.--17. "THCNTSEN,Select the bit number of A/D converter in THS" "0: 12bits,1: 10bits,?,?" newline bitfld.long 0x1C 12.--14. "VOLSELA,Select the chip internal voltage monitor input" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline bitfld.long 0x1C 8.--9. "SENSSEL,Select the use sensor" "0: THS,1: THS ON only,?,?" newline bitfld.long 0x1C 6. "PONM,Select mode signal" "0: Normal mode,1: Power-on mode" newline bitfld.long 0x1C 5. "THEN,Enabling/disabling of thermal sensor" "0: Enabled,1: Disabled" newline bitfld.long 0x1C 0. "THSST,Enabling/disabling of the A/D converter for the thermal sensor" "0: Disabled,1: Enabled" rgroup.long 0x24++0x43 line.long 0x0 "THSTR,Status Register" bitfld.long 0x0 3. "THACKMON,THACK signal monitor" "0: Not detected,1: THCODE was generated" newline bitfld.long 0x0 2. "THCNTOV_MON,THCNTOV signal monitor" "0: Not detected,1: Detected overflow" newline bitfld.long 0x0 1. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1" newline bitfld.long 0x0 0. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0" line.long 0x4 "TEMP_YN,Temperature1 Register ( Y(n) )" bitfld.long 0x4 12.--13. "TEMP_CODE_YN,These bits indicate the digital value for the temperature detected by the thermal sensor." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "TEMP_CODE_YN,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x8 "VOLT,Voltage Register" hexmask.long.byte 0x8 10.--13. 1. "VOLT_CODE,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." newline hexmask.long.word 0x8 0.--9. 1. "VOLT_CODE,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." line.long 0xC "TEMP_X,Temperature1 Register ( X(n) )" hexmask.long.word 0xC 0.--13. 1. "TEMP_X,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x10 "TEMP_YN1,Temperature2 Register ( Y(n-1) )" hexmask.long.word 0x10 0.--13. 1. "TEMP_YN1,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x14 "TEMP_X1,Temperature3 Register ( X(n-1) )" hexmask.long.word 0x14 0.--13. 1. "TEMP_X1,These bits indicate the digital value for the one before temperature detected by the thermal sensor." line.long 0x18 "THINITSTR,Power ON Initial Temperature Status Register" bitfld.long 0x18 3. "NRMEND,Completion flag of capturing the temperatures in the power-on mode" "0: Not complete,1: Complete" newline bitfld.long 0x18 2. "THTMP3,Detection of capturing the third temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" newline bitfld.long 0x18 1. "THTMP2,Detection of capturing the second temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" newline bitfld.long 0x18 0. "THTMP1,Detection of capturing the first temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" line.long 0x1C "THCODE_INT1,Power ON Initial 1 Temperature Register" hexmask.long.word 0x1C 0.--11. 1. "THCODE_INT1,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x20 "THCODE_INT2,Power ON Initial 2 Temperature Register" hexmask.long.word 0x20 0.--11. 1. "THCODE_INT2,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x24 "THCODE_INT3,Power ON Initial 3 Temperature Register" hexmask.long.word 0x24 0.--11. 1. "THCODE_INT3,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x28 "CVCREG,Convert Correction Register" hexmask.long.word 0x28 0.--11. 1. "CCREG,Parameter to be used in adjusting the characteristics" line.long 0x2C "THCODE1,THCODE Parameter1 Register" hexmask.long.word 0x2C 0.--11. 1. "THCODE1,Parameter to be used in adjusting the characteristics" line.long 0x30 "THCODE2,THCODE Parameter2 Register" hexmask.long.word 0x30 0.--11. 1. "THCODE2,Parameter to be used in adjusting the characteristics" line.long 0x34 "THCODE3,THCODE Parameter3 Register" hexmask.long.word 0x34 0.--11. 1. "THCODE3,Parameter to be used in adjusting the characteristics" line.long 0x38 "PTAT1,PTAT Parameter1 Register" hexmask.long.word 0x38 16.--27. 1. "PTAT1_0,Parameter to be used in adjusting the characteristics." newline hexmask.long.word 0x38 0.--11. 1. "PTAT1,Parameter to be used in adjusting the characteristics" line.long 0x3C "PTAT2,PTAT Parameter2 Register" hexmask.long.word 0x3C 0.--11. 1. "PTAT2,Parameter to be used in adjusting the characteristics" line.long 0x40 "PTAT3,PTAT Parameter3 Register" hexmask.long.word 0x40 16.--27. 1. "PTAT3_0,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x40 0.--11. 1. "PTAT3,Parameter to be used in adjusting the characteristics" group.long 0x6C++0x13 line.long 0x0 "IRQ_INJECTION,Error Injection Register" bitfld.long 0x0 5. "TEMPD3_INJ,TEMPD3 Error Injection" "0: IRQTEMP3 Error Injection Disable,1: IRQTEMP3 Error Injection Enable" newline bitfld.long 0x0 4. "TEMPD2_INJ,TEMPD2 Error Injection" "0: IRQTEMP2 Error Injection Disable,1: IRQTEMP2 Error Injection Enable" newline bitfld.long 0x0 3. "TEMPD1_INJ,TEMPD1 Error Injection" "0: IRQTEMP1 Error Injection Disable,1: IRQTEMP1 Error Injection Enable" newline bitfld.long 0x0 2. "TEMP3_INJ,TEMP3 Error Injection" "0: IRQTEMP3 Error Injection Disable,1: IRQTEMP3 Error Injection Enable" newline bitfld.long 0x0 1. "TEMP2_INJ,TEMP2 Error Injection" "0: IRQTEMP2 Error Injection Disable,1: IRQTEMP2 Error Injection Enable" newline bitfld.long 0x0 0. "TEMP1_INJ,TEMP1 Error Injection" "0: IRQTEMP1 Error Injection Disable,1: IRQTEMP1 Error Injection Enable" line.long 0x4 "ACK_TIMEOUT,Ack Timeout Register" hexmask.long.word 0x4 0.--13. 1. "ACK_TIMEOUT_REG,THACK timeout setting" line.long 0x8 "TSC_ERROR_CTL,TSC Error Control Register" bitfld.long 0x8 0. "TSC_ERR_CTL,TSC error injection" "0: Error injection off,1: Error injection on" line.long 0xC "THSOUTCTL,THS Output Control Register" bitfld.long 0xC 28. "THACKMASK,THACK mask enable" "0: Disable THACK mask,1: Enable THACK mask" newline bitfld.long 0xC 24. "THCNTOVCTL,THCNTOV select" "0: THCNTOV from THS,1: THCNTOV_TESTDT" newline bitfld.long 0xC 20. "THCODECTL,THCODE select" "0: THCODE from THS,1: THCODE_TESTDT" newline bitfld.long 0xC 16. "THCNTOV_TESTDT,THCNTOV test data setting" "0,1" newline hexmask.long.word 0xC 0.--13. 1. "THCODE_TESTDT,THCODE test data setting" line.long 0x10 "SEQ_RESET,Sequence Reset Register" bitfld.long 0x10 0. "SEQ_RESET,This bit initializes the sequence and error value." "0,1" rgroup.long 0x80++0x1F line.long 0x0 "PON_TEMP,Power On Temperature Register" hexmask.long.word 0x0 0.--13. 1. "PON_TEMP_CODE_YN,These bits indicate the digital value detected by the temperature sensor during Power On mode." line.long 0x4 "NML_TEMP,Normal Temperature Register" hexmask.long.word 0x4 0.--13. 1. "NML_TEMP_CODE_YN,These bits indicate the digital value detected by the temperature sensor during Normal mode." line.long 0x8 "NML_VOLT,Normal Voltage Register" hexmask.long.word 0x8 0.--13. 1. "NML_VOLT_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during Normal mode." line.long 0xC "CIVMTST_VOLT1,CIVM Test Voltage1 Register" hexmask.long.word 0xC 0.--13. 1. "CIVMTST_VOLT1_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode1." line.long 0x10 "CIVMTST_VOLT2,CIVM Test Voltage2 Register" hexmask.long.word 0x10 0.--13. 1. "CIVMTST_VOLT2_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode2." line.long 0x14 "CIVMTST_VOLT3,CIVM Test Voltage3 Register" hexmask.long.word 0x14 0.--13. 1. "CIVMTST_VOLT3_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode3." line.long 0x18 "CIVMTST_VOLT4,CIVM Test Voltage4 Register" hexmask.long.word 0x18 0.--13. 1. "CIVMTST_VOLT4_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode4." line.long 0x1C "MANTST_VOLT,Manual Test Voltage Register" hexmask.long.word 0x1C 0.--13. 1. "MANTST_VOLT_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during Manual test mode." rgroup.long 0xA8++0x3 line.long 0x0 "VOLT_YN,Voltage Register ( Y(n) )" hexmask.long.word 0x0 0.--11. 1. "VOLT_CODE_YN,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." rgroup.long 0xB0++0x3 line.long 0x0 "VOLT_X,Voltage 1 Register ( X(n) )" hexmask.long.word 0x0 0.--13. 1. "VOLT_CODE_X,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." rgroup.long 0xB8++0x3 line.long 0x0 "VOLT_X1,Voltage 2 Register ( X(n-1) )" hexmask.long.word 0x0 0.--13. 1. "VOLT_CODE_X1,These bits indicate the digital value for the one before voltage detected by the chip internal voltage monitor." rgroup.long 0xD0++0x27 line.long 0x0 "VMCODE1,VMCODE Parameter1 Register" hexmask.long.word 0x0 16.--25. 1. "VMCODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x0 0.--9. 1. "VMCODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x4 "VMCODE2,VMCODE Parameter2 Register" hexmask.long.word 0x4 16.--25. 1. "VMCODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x4 0.--9. 1. "VMCODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x8 "VMCODE3,VMCODE Parameter3 Register" hexmask.long.word 0x8 16.--25. 1. "VMCODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x8 0.--9. 1. "VMCODE3_L,Parameter to be used in adjusting the characteristics" line.long 0xC "HVMCODE1,High VMCODE Parameter1 Register" hexmask.long.word 0xC 16.--25. 1. "VC18CODE1,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0xC 0.--9. 1. "VM11CODE1,Parameter to be used in adjusting the characteristics" line.long 0x10 "HVMCODE2,High VMCODE Parameter2 Register" hexmask.long.word 0x10 16.--25. 1. "VC18CODE2,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x10 0.--9. 1. "VM11CODE2,Parameter to be used in adjusting the characteristics" line.long 0x14 "HVMCODE3,High VMCODE Parameter3 Register" hexmask.long.word 0x14 16.--25. 1. "VC18CODE3,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x14 0.--9. 1. "VM11CODE3,Parameter to be used in adjusting the characteristics" line.long 0x18 "INBUF_OFF1,Input Buffer Offset1 Register" hexmask.long.word 0x18 0.--9. 1. "INBUF_OFF1" line.long 0x1C "INBUF_OFF2,Input Buffer Offset2 Register" hexmask.long.word 0x1C 0.--9. 1. "INBUF_OFF2" line.long 0x20 "INBUF_OFF3,Input Buffer Offset3 Register" hexmask.long.word 0x20 0.--9. 1. "INBUF_OFF3" line.long 0x24 "THS_RATIO,THS RATIO Register" hexmask.long.word 0x24 0.--15. 1. "THS_RATIO" group.long 0x100++0x3 line.long 0x0 "CVM_EN,CVM Enable Register" bitfld.long 0x0 0. "CVM_EN,This bit is a value enable signal." "0,1" rgroup.long 0x108++0x3 line.long 0x0 "CVM_CTRL_BK,CVM Control Readback Register" bitfld.long 0x0 12. "THEN_BK,This bit can monitor the readback value of THEN in THCTR register." "0,1" newline bitfld.long 0x0 8. "OUTPC_BK,This bit can monitor the readback value of OUTPC in CVM_CTRL register." "0,1" newline bitfld.long 0x0 4. "EXTERNAL_FS_BK,This bit can monitor the readback value of EXTERNAL_FS in CVM_CTRL register." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CHOICE_PLACE_BK,These bits can monitor the readback value of CHOICE_PLACE [3:0] in CVM_CTRL register." rgroup.long 0x128++0xF line.long 0x0 "STATMON1,State Monitor1 Register" hexmask.long.byte 0x0 24.--31. 1. "NML_STAT,Normal sequence state monitor" newline hexmask.long.byte 0x0 16.--23. 1. "PON_STAT,Power on sequence state monitor" newline hexmask.long.byte 0x0 8.--15. 1. "TST_STAT,Test sequence state monitor" newline hexmask.long.byte 0x0 0.--7. 1. "CTRL_STAT,Sequence control state monitor" line.long 0x4 "STATMON2,State Monitor2 Register" hexmask.long.byte 0x4 8.--15. 1. "MANTST_STAT,Manual test sequence state monitor" newline hexmask.long.byte 0x4 0.--7. 1. "CIVMTST_STAT,CIVM test sequence state monitor" line.long 0x8 "TSC_ERROR_MON,TSC Error Monitor Register" bitfld.long 0x8 7. "ERR_ACKTOV,THACK timeout error status" "0: no error,1: THACK timeout error" newline bitfld.long 0x8 6. "ERR_TST4,THCODE connection check(Test4) error status" "0: no error,1: THCODE connection check" newline bitfld.long 0x8 5. "ERR_TST5,THCODE connection check(Test5) error status" "0: no error,1: THCODE connection check" newline bitfld.long 0x8 4. "ERR_THCODE,THCODE error status" "0: no error,1: THCODE error" newline bitfld.long 0x8 3. "ERR_THCNTOV,THCNTOV error status" "0: no error,1: THCNTOV error" newline bitfld.long 0x8 2. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1" newline bitfld.long 0x8 1. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0" newline bitfld.long 0x8 0. "TSC_ERROR,TSC error status" "0: no error,1: TSC error" line.long 0xC "THCODE_MON,THCODE Monitor Register" bitfld.long 0xC 30. "TST4_THCNTOV,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test4)." "0,1" newline hexmask.long.word 0xC 16.--29. 1. "TST4_THCODE,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test4)." newline bitfld.long 0xC 14. "TST5_THCNTOV,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test5)." "0,1" newline hexmask.long.word 0xC 0.--13. 1. "TST5_THCODE,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test5)." group.long 0x138++0x3 line.long 0x0 "MANTST_SET_DT,Manual Test Mode Data Register" bitfld.long 0x0 28. "MANTST_REG,Manual test mode" "0: Normal mode,1: Manual test mode" newline bitfld.long 0x0 24. "MAN_THCHOP,Select the Manual THCHOP mode" "0: THCHOP=0 on Manual test mode,1: THCHOP=1 on Manual test mode" newline bitfld.long 0x0 12.--13. "MAN_THCNTSEL,Select the bit number of A/D converter for manual test" "0: 12bits,1: 10bits,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "MAN_THMODE,Select THMODE for manual test." newline bitfld.long 0x0 4.--6. "MAN_THVMSEL_A,Select chip internal voltage monitor input for manual test" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "MAN_THVMSEL_B,Select chip internal voltage monitor input for manual test" rgroup.long 0x13C++0x7 line.long 0x0 "TMR_DT,Timer Data Register" hexmask.long.tbyte 0x0 12.--29. 1. "ACKTMR,THACK timer monitor" newline hexmask.long.word 0x0 0.--9. 1. "GPTMR,General purpose timer monitor" line.long 0x4 "SEQ_ACT_MON,Sequence Act Signal Monitor Register" bitfld.long 0x4 17. "TSTSEQ_DONE,This bit indicates that the THCODE Connection Test Sequence has completed" "0: Not completed,1: Completed" newline bitfld.long 0x4 16. "STBYSEQ_DONE,This bit indicates that the THS Standby Setting Sequence has completed" "0: Not completed,1: Completed" newline hexmask.long.byte 0x4 0.--4. 1. "SEQ_ACT,Sequence Act Flag monitor" rgroup.long 0x150++0x23 line.long 0x0 "VM06CODE1,VM06CODE Parameter1 Register" hexmask.long.word 0x0 16.--25. 1. "VM06CODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x0 0.--9. 1. "VM06CODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x4 "VM06CODE2,VM06CODE Parameter2 Register" hexmask.long.word 0x4 16.--25. 1. "VM06CODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x4 0.--9. 1. "VM06CODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x8 "VM06CODE3,VM06CODE Parameter3 Register" hexmask.long.word 0x8 16.--25. 1. "VM06CODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x8 0.--9. 1. "VM06CODE3_L,Parameter to be used in adjusting the characteristics" line.long 0xC "VM11CODE1,VM11CODE Parameter1 Register" hexmask.long.word 0xC 16.--25. 1. "VM11CODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0xC 0.--9. 1. "VM11CODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x10 "VM11CODE2,VM11CODE Parameter2 Register" hexmask.long.word 0x10 16.--25. 1. "VM11CODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x10 0.--9. 1. "VM11CODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x14 "VM11CODE3,VM11CODE Parameter3 Register" hexmask.long.word 0x14 16.--25. 1. "VM11CODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x14 0.--9. 1. "VM11CODE3_L,Parameter to be used in adjusting the characteristics" line.long 0x18 "VMCVMCODE1,VCC VMCODE Parameter1 Register" hexmask.long.word 0x18 16.--25. 1. "VCCVMCODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x18 0.--9. 1. "VCCVMCODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x1C "VMCVMCODE2,VCC VMCODE Parameter2 Register" hexmask.long.word 0x1C 16.--25. 1. "VCCVMCODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x1C 0.--9. 1. "VCCVMCODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x20 "VMCVMCODE3,VCC VMCODE Parameter3 Register" hexmask.long.word 0x20 16.--25. 1. "VCCVMCODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x20 0.--9. 1. "VCCVMCODE3_L,Parameter to be used in adjusting the characteristics" tree.end tree "TSC_1" base ad:0xE6190000 rgroup.long 0x0++0x3 line.long 0x0 "THSIRQSTR,THS Temperature Error Status Register" bitfld.long 0x0 2. "IRQ3,Temperature Error3 Status" "0: Not detected,1: Temperature Error3 for thermal sensor is detected" newline bitfld.long 0x0 1. "IRQ2,Temperature Error2 Status" "0: Not detected,1: Temperature Error2 for thermal sensor is detected" newline bitfld.long 0x0 0. "IRQ1,Temperature Error1 Status" "0: Not detected,1: Temperature Error1 for thermal sensor is detected" group.long 0x4++0x1F line.long 0x0 "IRQSTR,Temperature Error Status Register" bitfld.long 0x0 5. "TEMPD3_STR,TEMPD3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 4. "TEMPD2_STR,TEMPD2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 3. "TEMPD1_STR,TEMPD1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 2. "TEMP3_STR,TEMP3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." newline bitfld.long 0x0 1. "TEMP2_STR,TEMP2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." newline bitfld.long 0x0 0. "TEMP1_STR,TEMP1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." line.long 0x4 "IRQMSK,Temperature Error Mask Register" bitfld.long 0x4 5. "TEMPD3_MSK,This bit selects masking or non-masking of TEMPD3 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 4. "TEMPD2_MSK,This bit selects masking or non-masking of TEMPD2 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 3. "TEMPD1_MSK,This bit selects masking or non-masking of TEMPD1 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 2. "TEMP3_MSK,This bit selects masking or non-masking of TEMP3 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 1. "TEMP2_MSK,This bit selects masking or non-masking of TEMP2 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 0. "TEMP1_MSK,This bit selects masking or non-masking of TEMP1 error requests." "0: Errors are masked,1: The mask is cleared" line.long 0x8 "IRQCTL,Threshold Edge/Level Register" bitfld.long 0x8 5. "TEMPD3_EL,Specifies the method for detection of the TEMPD3 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 4. "TEMPD2_EL,Specifies the method for detection of the TEMPD2 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 3. "TEMPD1_EL,Specifies the method for detection of the TEMPD1 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 2. "TEMP3_EL,Specifies the method for detection of the TEMP3 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 1. "TEMP2_EL,Specifies the method for detection of the TEMP2 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 0. "TEMP1_EL,Specifies the method for detection of the TEMP1 error signal input." "0: Edge detection,1: Level detection" line.long 0xC "IRQEN,Temperature Error Enable Register" bitfld.long 0xC 5. "TEMPD3_EN,This bit enables or disables TEMPD3 errors." "0: TEMPD3 errors are disabled,1: TEMPD3 errors are enabled" newline bitfld.long 0xC 4. "TEMPD2_EN,This bit enables or disables TEMPD2 errors." "0: TEMPD2 errors are disabled,1: TEMPD2 errors are enabled" newline bitfld.long 0xC 3. "TEMPD1_EN,This bit enables or disables TEMPD1 errors." "0: TEMPD1 errors are disabled,1: TEMPD1 errors are enabled" newline bitfld.long 0xC 2. "TEMP3_EN,This bit enables or disables TEMP3 errors." "0: TEMP3 errors are disabled,1: TEMP3 errors are enabled" newline bitfld.long 0xC 1. "TEMP2_EN,This bit enables or disables TEMP2 errors." "0: TEMP2 errors are disabled,1: TEMP2 errors are enabled" newline bitfld.long 0xC 0. "TEMP1_EN,This bit enables or disables TEMP1 errors." "0: TEMP1 errors are disabled,1: TEMP1 errors are enabled" line.long 0x10 "IRQTEMP1,Temperature Error 1 Register" bitfld.long 0x10 12.--13. "IRQTEMP1,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors." "0,1,2,3" newline hexmask.long.word 0x10 0.--11. 1. "IRQTEMP1,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors." line.long 0x14 "IRQTEMP2,Temperature Error 2 Register" bitfld.long 0x14 12.--13. "IRQTEMP2,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors." "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "IRQTEMP2,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors." line.long 0x18 "IRQTEMP3,Temperature Error 3 Register" bitfld.long 0x18 12.--13. "IRQTEMP3,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors." "0,1,2,3" newline hexmask.long.word 0x18 0.--11. 1. "IRQTEMP3,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors." line.long 0x1C "THCTR,Control Register" bitfld.long 0x1C 28.--30. "VOLSELB,Select the chip internal voltage monitor input" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline bitfld.long 0x1C 24. "CTCTL,Select write condition of THREFTAP THCNTSEN and VMCNTSEN" "0: Inhibit write of these bits,1: Allow write of these bits" newline bitfld.long 0x1C 20. "CIVMTST,THS/CIVM failure check mode" "0: Normal mode,1: THS/CIVM failure check mode" newline bitfld.long 0x1C 18.--19. "VMCNTSEN,Select the bit number of A/D converter in CIVM" "0: 10bits,1: 12bits,?,?" newline bitfld.long 0x1C 16.--17. "THCNTSEN,Select the bit number of A/D converter in THS" "0: 12bits,1: 10bits,?,?" newline bitfld.long 0x1C 12.--14. "VOLSELA,Select the chip internal voltage monitor input" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline bitfld.long 0x1C 8.--9. "SENSSEL,Select the use sensor" "0: THS,1: THS ON only,?,?" newline bitfld.long 0x1C 6. "PONM,Select mode signal" "0: Normal mode,1: Power-on mode" newline bitfld.long 0x1C 5. "THEN,Enabling/disabling of thermal sensor" "0: Enabled,1: Disabled" newline bitfld.long 0x1C 0. "THSST,Enabling/disabling of the A/D converter for the thermal sensor" "0: Disabled,1: Enabled" rgroup.long 0x24++0x47 line.long 0x0 "THSTR,Status Register" bitfld.long 0x0 3. "THACKMON,THACK signal monitor" "0: Not detected,1: THCODE was generated" newline bitfld.long 0x0 2. "THCNTOV_MON,THCNTOV signal monitor" "0: Not detected,1: Detected overflow" newline bitfld.long 0x0 1. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1" newline bitfld.long 0x0 0. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0" line.long 0x4 "TEMP_YN,Temperature1 Register ( Y(n) )" bitfld.long 0x4 12.--13. "TEMP_CODE_YN,These bits indicate the digital value for the temperature detected by the thermal sensor." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "TEMP_CODE_YN,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x8 "VOLT,Voltage Register" hexmask.long.byte 0x8 10.--13. 1. "VOLT_CODE,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." newline hexmask.long.word 0x8 0.--9. 1. "VOLT_CODE,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." line.long 0xC "TEMP_X,Temperature1 Register ( X(n) )" hexmask.long.word 0xC 0.--13. 1. "TEMP_X,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x10 "TEMP_YN1,Temperature2 Register ( Y(n-1) )" hexmask.long.word 0x10 0.--13. 1. "TEMP_YN1,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x14 "TEMP_X1,Temperature3 Register ( X(n-1) )" hexmask.long.word 0x14 0.--13. 1. "TEMP_X1,These bits indicate the digital value for the one before temperature detected by the thermal sensor." line.long 0x18 "THINITSTR,Power ON Initial Temperature Status Register" bitfld.long 0x18 3. "NRMEND,Completion flag of capturing the temperatures in the power-on mode" "0: Not complete,1: Complete" newline bitfld.long 0x18 2. "THTMP3,Detection of capturing the third temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" newline bitfld.long 0x18 1. "THTMP2,Detection of capturing the second temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" newline bitfld.long 0x18 0. "THTMP1,Detection of capturing the first temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" line.long 0x1C "THCODE_INT1,Power ON Initial 1 Temperature Register" hexmask.long.word 0x1C 0.--11. 1. "THCODE_INT1,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x20 "THCODE_INT2,Power ON Initial 2 Temperature Register" hexmask.long.word 0x20 0.--11. 1. "THCODE_INT2,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x24 "THCODE_INT3,Power ON Initial 3 Temperature Register" hexmask.long.word 0x24 0.--11. 1. "THCODE_INT3,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x28 "CVCREG,Convert Correction Register" hexmask.long.word 0x28 0.--11. 1. "CCREG,Parameter to be used in adjusting the characteristics" line.long 0x2C "THCODE1,THCODE Parameter1 Register" hexmask.long.word 0x2C 0.--11. 1. "THCODE1,Parameter to be used in adjusting the characteristics" line.long 0x30 "THCODE2,THCODE Parameter2 Register" hexmask.long.word 0x30 0.--11. 1. "THCODE2,Parameter to be used in adjusting the characteristics" line.long 0x34 "THCODE3,THCODE Parameter3 Register" hexmask.long.word 0x34 0.--11. 1. "THCODE3,Parameter to be used in adjusting the characteristics" line.long 0x38 "PTAT1,PTAT Parameter1 Register" hexmask.long.word 0x38 16.--27. 1. "PTAT1_0,Parameter to be used in adjusting the characteristics." newline hexmask.long.word 0x38 0.--11. 1. "PTAT1,Parameter to be used in adjusting the characteristics" line.long 0x3C "PTAT2,PTAT Parameter2 Register" hexmask.long.word 0x3C 0.--11. 1. "PTAT2,Parameter to be used in adjusting the characteristics" line.long 0x40 "PTAT3,PTAT Parameter3 Register" hexmask.long.word 0x40 16.--27. 1. "PTAT3_0,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x40 0.--11. 1. "PTAT3,Parameter to be used in adjusting the characteristics" line.long 0x44 "THSCP,Software Correction Parameter Register" bitfld.long 0x44 20. "FTHCSEL6,Select the condition for acquiring THCODE3" "0,1" newline bitfld.long 0x44 16. "FTHCSEL3,Select the condition for acquiring THCODE2" "0,1" newline bitfld.long 0x44 14.--15. "COR_PARA_VLD,Check the valid value of adjusting parameter." "0,1,2,3" newline hexmask.long.word 0x44 0.--13. 1. "CIVM_RES_MEM" group.long 0x6C++0x13 line.long 0x0 "IRQ_INJECTION,Error Injection Register" bitfld.long 0x0 5. "TEMPD3_INJ,TEMPD3 Error Injection" "0: IRQTEMP3 Error Injection Disable,1: IRQTEMP3 Error Injection Enable" newline bitfld.long 0x0 4. "TEMPD2_INJ,TEMPD2 Error Injection" "0: IRQTEMP2 Error Injection Disable,1: IRQTEMP2 Error Injection Enable" newline bitfld.long 0x0 3. "TEMPD1_INJ,TEMPD1 Error Injection" "0: IRQTEMP1 Error Injection Disable,1: IRQTEMP1 Error Injection Enable" newline bitfld.long 0x0 2. "TEMP3_INJ,TEMP3 Error Injection" "0: IRQTEMP3 Error Injection Disable,1: IRQTEMP3 Error Injection Enable" newline bitfld.long 0x0 1. "TEMP2_INJ,TEMP2 Error Injection" "0: IRQTEMP2 Error Injection Disable,1: IRQTEMP2 Error Injection Enable" newline bitfld.long 0x0 0. "TEMP1_INJ,TEMP1 Error Injection" "0: IRQTEMP1 Error Injection Disable,1: IRQTEMP1 Error Injection Enable" line.long 0x4 "ACK_TIMEOUT,Ack Timeout Register" hexmask.long.word 0x4 0.--13. 1. "ACK_TIMEOUT_REG,THACK timeout setting" line.long 0x8 "TSC_ERROR_CTL,TSC Error Control Register" bitfld.long 0x8 0. "TSC_ERR_CTL,TSC error injection" "0: Error injection off,1: Error injection on" line.long 0xC "THSOUTCTL,THS Output Control Register" bitfld.long 0xC 28. "THACKMASK,THACK mask enable" "0: Disable THACK mask,1: Enable THACK mask" newline bitfld.long 0xC 24. "THCNTOVCTL,THCNTOV select" "0: THCNTOV from THS,1: THCNTOV_TESTDT" newline bitfld.long 0xC 20. "THCODECTL,THCODE select" "0: THCODE from THS,1: THCODE_TESTDT" newline bitfld.long 0xC 16. "THCNTOV_TESTDT,THCNTOV test data setting" "0,1" newline hexmask.long.word 0xC 0.--13. 1. "THCODE_TESTDT,THCODE test data setting" line.long 0x10 "SEQ_RESET,Sequence Reset Register" bitfld.long 0x10 0. "SEQ_RESET,This bit initializes the sequence and error value." "0,1" rgroup.long 0x80++0x1F line.long 0x0 "PON_TEMP,Power On Temperature Register" hexmask.long.word 0x0 0.--13. 1. "PON_TEMP_CODE_YN,These bits indicate the digital value detected by the temperature sensor during Power On mode." line.long 0x4 "NML_TEMP,Normal Temperature Register" hexmask.long.word 0x4 0.--13. 1. "NML_TEMP_CODE_YN,These bits indicate the digital value detected by the temperature sensor during Normal mode." line.long 0x8 "NML_VOLT,Normal Voltage Register" hexmask.long.word 0x8 0.--13. 1. "NML_VOLT_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during Normal mode." line.long 0xC "CIVMTST_VOLT1,CIVM Test Voltage1 Register" hexmask.long.word 0xC 0.--13. 1. "CIVMTST_VOLT1_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode1." line.long 0x10 "CIVMTST_VOLT2,CIVM Test Voltage2 Register" hexmask.long.word 0x10 0.--13. 1. "CIVMTST_VOLT2_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode2." line.long 0x14 "CIVMTST_VOLT3,CIVM Test Voltage3 Register" hexmask.long.word 0x14 0.--13. 1. "CIVMTST_VOLT3_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode3." line.long 0x18 "CIVMTST_VOLT4,CIVM Test Voltage4 Register" hexmask.long.word 0x18 0.--13. 1. "CIVMTST_VOLT4_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode4." line.long 0x1C "MANTST_VOLT,Manual Test Voltage Register" hexmask.long.word 0x1C 0.--13. 1. "MANTST_VOLT_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during Manual test mode." rgroup.long 0xA8++0x3 line.long 0x0 "VOLT_YN,Voltage Register ( Y(n) )" hexmask.long.word 0x0 0.--11. 1. "VOLT_CODE_YN,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." rgroup.long 0xB0++0x3 line.long 0x0 "VOLT_X,Voltage 1 Register ( X(n) )" hexmask.long.word 0x0 0.--13. 1. "VOLT_CODE_X,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." rgroup.long 0xB8++0x3 line.long 0x0 "VOLT_X1,Voltage 2 Register ( X(n-1) )" hexmask.long.word 0x0 0.--13. 1. "VOLT_CODE_X1,These bits indicate the digital value for the one before voltage detected by the chip internal voltage monitor." rgroup.long 0xD0++0x27 line.long 0x0 "VMCODE1,VMCODE Parameter1 Register" hexmask.long.word 0x0 16.--25. 1. "VMCODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x0 0.--9. 1. "VMCODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x4 "VMCODE2,VMCODE Parameter2 Register" hexmask.long.word 0x4 16.--25. 1. "VMCODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x4 0.--9. 1. "VMCODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x8 "VMCODE3,VMCODE Parameter3 Register" hexmask.long.word 0x8 16.--25. 1. "VMCODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x8 0.--9. 1. "VMCODE3_L,Parameter to be used in adjusting the characteristics" line.long 0xC "HVMCODE1,High VMCODE Parameter1 Register" hexmask.long.word 0xC 16.--25. 1. "VC18CODE1,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0xC 0.--9. 1. "VM11CODE1,Parameter to be used in adjusting the characteristics" line.long 0x10 "HVMCODE2,High VMCODE Parameter2 Register" hexmask.long.word 0x10 16.--25. 1. "VC18CODE2,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x10 0.--9. 1. "VM11CODE2,Parameter to be used in adjusting the characteristics" line.long 0x14 "HVMCODE3,High VMCODE Parameter3 Register" hexmask.long.word 0x14 16.--25. 1. "VC18CODE3,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x14 0.--9. 1. "VM11CODE3,Parameter to be used in adjusting the characteristics" line.long 0x18 "INBUF_OFF1,Input Buffer Offset1 Register" hexmask.long.word 0x18 0.--9. 1. "INBUF_OFF1" line.long 0x1C "INBUF_OFF2,Input Buffer Offset2 Register" hexmask.long.word 0x1C 0.--9. 1. "INBUF_OFF2" line.long 0x20 "INBUF_OFF3,Input Buffer Offset3 Register" hexmask.long.word 0x20 0.--9. 1. "INBUF_OFF3" line.long 0x24 "THS_RATIO,THS RATIO Register" hexmask.long.word 0x24 0.--15. 1. "THS_RATIO" group.long 0x100++0x7 line.long 0x0 "CVM_EN,CVM Enable Register" bitfld.long 0x0 0. "CVM_EN,This bit is a value enable signal." "0,1" line.long 0x4 "CVM_CTRL,CVM Control Register" bitfld.long 0x4 8. "OUTPC,This bit is a switching signal for CVM function" "0: Idle mode,1: CVM mode" newline bitfld.long 0x4 4. "EXTERNAL_FS,This bit is a switch bit which select VTHREF and VTHSENSE terminal." "0: CVM output,1: THS output" newline hexmask.long.byte 0x4 0.--3. 1. "CHOICE_PLACE,These bits can select the enable/disable of CVM function at each thermal sensor module." rgroup.long 0x108++0x7 line.long 0x0 "CVM_CTRL_BK,CVM Control Readback Register" bitfld.long 0x0 12. "THEN_BK,This bit can monitor the readback value of THEN in THCTR register." "0,1" newline bitfld.long 0x0 8. "OUTPC_BK,This bit can monitor the readback value of OUTPC in CVM_CTRL register." "0,1" newline bitfld.long 0x0 4. "EXTERNAL_FS_BK,This bit can monitor the readback value of EXTERNAL_FS in CVM_CTRL register." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CHOICE_PLACE_BK,These bits can monitor the readback value of CHOICE_PLACE [3:0] in CVM_CTRL register." line.long 0x4 "CVM_DETECT_MON,CVM Detection Voltage Setting Monitor Register" bitfld.long 0x4 24.--26. "MODE_MAX_MON,These bits can monitor the applicable trimming bits for maximum voltage side." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--19. 1. "TRIM_MAX_MON,These bits can monitor the applicable trimming bits for maximum voltage side." newline bitfld.long 0x4 8.--10. "MODE_MIN_MON,These bits can monitor the applicable trimming bits for minimum voltage side." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "TRIM_MIN_MON,These bits can monitor the applicable trimming bits for minimum voltage side." group.long 0x110++0x3 line.long 0x0 "CVM_DETECT_MANUAL_SET,CVM Detection Voltage Manual Setting Register" bitfld.long 0x0 28. "CVM_DETECT_SEL_MAX,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register." "0: The values of bits 26 to 24 and bits 19 to 16 in..,1: The values of bits 26 to 24 and bits 19 to 16 in.." newline bitfld.long 0x0 24.--26. "MODE_MAX,When bit 1 in CVM_CTRL register is 1’b1 these bits are enabled." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "TRIM_MAX,When bit 1 in CVM_CTRL register is 1’b1 these bits are enabled." newline bitfld.long 0x0 12. "CVM_DETECT_SEL_MIN,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register." "0: The values of bits 10 to 8 and bits 3 to 0 in..,1: The values of bits 10 to 8 and bits 3 to 0 in.." newline bitfld.long 0x0 8.--10. "MODE_MIN,When bit 0 in CVM_CTRL register is 1’b1 these bits are enabled." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "TRIM_MIN,When bit 0 in CVM_CTRL register is 1’b1 these bits are enabled." rgroup.long 0x114++0x7 line.long 0x0 "CVM_DETECT_SET_BK,CVM Detection Voltage Setting Readback Register" bitfld.long 0x0 24.--26. "MODE_MAX_BK,These bits can monitor the readback value of MODE_MAX[2:0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "TRIM_MAX_BK,These bits can monitor the readback value of TRIM_MAX[3:0]." newline bitfld.long 0x0 8.--10. "MODE_MIN_BK,These bits can monitor the readback value of MODE_MIN[2:0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "TRIM_MIN_BK,These bits can monitor the readback value of TRIM_MIN[3:0]." line.long 0x4 "CVM_TOFF_MON,CVM Temp Offset Monitor Register" hexmask.long.byte 0x4 0.--3. 1. "TOFF_MON,These bits can monitor trimming values." group.long 0x11C++0x3 line.long 0x0 "CVM_TOFF_MANUAL_SET,CVM Temp Offset Manual Setting Register" bitfld.long 0x0 12. "TOFF_SEL,This bit selects either CVM_TOFF_MON register or CVM_TOFF_MANUAL_SET register." "0: Select value that bit 3 to 0 in CVM_TOFF_MON..,1: Select value that bit 3 to 0 in.." newline hexmask.long.byte 0x0 0.--3. 1. "TOFF,When bit 4 in CVM_CTRL register is 1’b1 these bits are enabled." rgroup.long 0x120++0x17 line.long 0x0 "CVM_TOFF_BK,CVM Temp Offset Readback Register" hexmask.long.byte 0x0 0.--3. 1. "TOFF_BK,These bits can monitor the readback value of TOFF[3:0]." line.long 0x4 "CVM_VMOUT_BK,CVM Voltage Monitor Output Readback Register" bitfld.long 0x4 0.--1. "VMOUT_BK,These bits can monitor the switch signal of analog voltage." "0: Under Voltage,1: Normal,?,?" line.long 0x8 "STATMON1,State Monitor1 Register" hexmask.long.byte 0x8 24.--31. 1. "NML_STAT,Normal sequence state monitor" newline hexmask.long.byte 0x8 16.--23. 1. "PON_STAT,Power on sequence state monitor" newline hexmask.long.byte 0x8 8.--15. 1. "TST_STAT,Test sequence state monitor" newline hexmask.long.byte 0x8 0.--7. 1. "CTRL_STAT,Sequence control state monitor" line.long 0xC "STATMON2,State Monitor2 Register" hexmask.long.byte 0xC 8.--15. 1. "MANTST_STAT,Manual test sequence state monitor" newline hexmask.long.byte 0xC 0.--7. 1. "CIVMTST_STAT,CIVM test sequence state monitor" line.long 0x10 "TSC_ERROR_MON,TSC Error Monitor Register" bitfld.long 0x10 7. "ERR_ACKTOV,THACK timeout error status" "0: no error,1: THACK timeout error" newline bitfld.long 0x10 6. "ERR_TST4,THCODE connection check(Test4) error status" "0: no error,1: THCODE connection check" newline bitfld.long 0x10 5. "ERR_TST5,THCODE connection check(Test5) error status" "0: no error,1: THCODE connection check" newline bitfld.long 0x10 4. "ERR_THCODE,THCODE error status" "0: no error,1: THCODE error" newline bitfld.long 0x10 3. "ERR_THCNTOV,THCNTOV error status" "0: no error,1: THCNTOV error" newline bitfld.long 0x10 2. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1" newline bitfld.long 0x10 1. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0" newline bitfld.long 0x10 0. "TSC_ERROR,TSC error status" "0: no error,1: TSC error" line.long 0x14 "THCODE_MON,THCODE Monitor Register" bitfld.long 0x14 30. "TST4_THCNTOV,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test4)." "0,1" newline hexmask.long.word 0x14 16.--29. 1. "TST4_THCODE,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test4)." newline bitfld.long 0x14 14. "TST5_THCNTOV,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test5)." "0,1" newline hexmask.long.word 0x14 0.--13. 1. "TST5_THCODE,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test5)." group.long 0x138++0x3 line.long 0x0 "MANTST_SET_DT,Manual Test Mode Data Register" bitfld.long 0x0 28. "MANTST_REG,Manual test mode" "0: Normal mode,1: Manual test mode" newline bitfld.long 0x0 24. "MAN_THCHOP,Select the Manual THCHOP mode" "0: THCHOP=0 on Manual test mode,1: THCHOP=1 on Manual test mode" newline bitfld.long 0x0 12.--13. "MAN_THCNTSEL,Select the bit number of A/D converter for manual test" "0: 12bits,1: 10bits,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "MAN_THMODE,Select THMODE for manual test." newline bitfld.long 0x0 4.--6. "MAN_THVMSEL_A,Select chip internal voltage monitor input for manual test" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "MAN_THVMSEL_B,Select chip internal voltage monitor input for manual test" rgroup.long 0x13C++0x7 line.long 0x0 "TMR_DT,Timer Data Register" hexmask.long.tbyte 0x0 12.--29. 1. "ACKTMR,THACK timer monitor" newline hexmask.long.word 0x0 0.--9. 1. "GPTMR,General purpose timer monitor" line.long 0x4 "SEQ_ACT_MON,Sequence Act Signal Monitor Register" bitfld.long 0x4 17. "TSTSEQ_DONE,This bit indicates that the THCODE Connection Test Sequence has completed" "0: Not completed,1: Completed" newline bitfld.long 0x4 16. "STBYSEQ_DONE,This bit indicates that the THS Standby Setting Sequence has completed" "0: Not completed,1: Completed" newline hexmask.long.byte 0x4 0.--4. 1. "SEQ_ACT,Sequence Act Flag monitor" group.long 0x144++0x3 line.long 0x0 "VMMSK_CTRL,CVM Mask Control Register" bitfld.long 0x0 2. "CVMC_MSK_CTL_N,This bit selects masking or non-masking of CVM error at thermal sensor #2 module" "0: CVM error is masked,1: The mask is cleared" newline bitfld.long 0x0 1. "CVMB_MSKCTL_N,This bit selects masking or non-masking of CVM error at thermal sensor #3 module" "0: CVM error is masked,1: The mask is cleared" rgroup.long 0x148++0x2B line.long 0x0 "VMMSK_CTRL_MON,CVM Mask Control Monitor Register" bitfld.long 0x0 20.--21. "VMC_08_S,These bits can monitor CVM status of thermal sensor #2" "0: Under Voltage,1: Normal,?,?" newline bitfld.long 0x0 18.--19. "VMB_08_S,These bits can monitor CVM status of thermal sensor #3" "0: Under Voltage,1: Normal,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "VMCHPL_OUT,These bits can monitor the enable / disable of the CVM function on each thermal sensor module." line.long 0x4 "VM_MON,CVM Monitor Register" bitfld.long 0x4 0.--1. "VM_08_S,These bits can monitor CVM status" "0: Under Voltage,1: Normal,?,?" line.long 0x8 "VM06CODE1,VM06CODE Parameter1 Register" hexmask.long.word 0x8 16.--25. 1. "VM06CODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x8 0.--9. 1. "VM06CODE1_L,Parameter to be used in adjusting the characteristics" line.long 0xC "VM06CODE2,VM06CODE Parameter2 Register" hexmask.long.word 0xC 16.--25. 1. "VM06CODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0xC 0.--9. 1. "VM06CODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x10 "VM06CODE3,VM06CODE Parameter3 Register" hexmask.long.word 0x10 16.--25. 1. "VM06CODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x10 0.--9. 1. "VM06CODE3_L,Parameter to be used in adjusting the characteristics" line.long 0x14 "VM11CODE1,VM11CODE Parameter1 Register" hexmask.long.word 0x14 16.--25. 1. "VM11CODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x14 0.--9. 1. "VM11CODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x18 "VM11CODE2,VM11CODE Parameter2 Register" hexmask.long.word 0x18 16.--25. 1. "VM11CODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x18 0.--9. 1. "VM11CODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x1C "VM11CODE3,VM11CODE Parameter3 Register" hexmask.long.word 0x1C 16.--25. 1. "VM11CODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x1C 0.--9. 1. "VM11CODE3_L,Parameter to be used in adjusting the characteristics" line.long 0x20 "VMCVMCODE1,VCC VMCODE Parameter1 Register" hexmask.long.word 0x20 16.--25. 1. "VCCVMCODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x20 0.--9. 1. "VCCVMCODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x24 "VMCVMCODE2,VCC VMCODE Parameter2 Register" hexmask.long.word 0x24 16.--25. 1. "VCCVMCODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x24 0.--9. 1. "VCCVMCODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x28 "VMCVMCODE3,VCC VMCODE Parameter3 Register" hexmask.long.word 0x28 16.--25. 1. "VCCVMCODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x28 0.--9. 1. "VCCVMCODE3_L,Parameter to be used in adjusting the characteristics" tree.end tree "TSC_2" base ad:0xE61A0000 rgroup.long 0x0++0x3 line.long 0x0 "THSIRQSTR,THS Temperature Error Status Register" bitfld.long 0x0 2. "IRQ3,Temperature Error3 Status" "0: Not detected,1: Temperature Error3 for thermal sensor is detected" newline bitfld.long 0x0 1. "IRQ2,Temperature Error2 Status" "0: Not detected,1: Temperature Error2 for thermal sensor is detected" newline bitfld.long 0x0 0. "IRQ1,Temperature Error1 Status" "0: Not detected,1: Temperature Error1 for thermal sensor is detected" group.long 0x4++0x1F line.long 0x0 "IRQSTR,Temperature Error Status Register" bitfld.long 0x0 5. "TEMPD3_STR,TEMPD3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 4. "TEMPD2_STR,TEMPD2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 3. "TEMPD1_STR,TEMPD1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 2. "TEMP3_STR,TEMP3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." newline bitfld.long 0x0 1. "TEMP2_STR,TEMP2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." newline bitfld.long 0x0 0. "TEMP1_STR,TEMP1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." line.long 0x4 "IRQMSK,Temperature Error Mask Register" bitfld.long 0x4 5. "TEMPD3_MSK,This bit selects masking or non-masking of TEMPD3 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 4. "TEMPD2_MSK,This bit selects masking or non-masking of TEMPD2 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 3. "TEMPD1_MSK,This bit selects masking or non-masking of TEMPD1 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 2. "TEMP3_MSK,This bit selects masking or non-masking of TEMP3 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 1. "TEMP2_MSK,This bit selects masking or non-masking of TEMP2 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 0. "TEMP1_MSK,This bit selects masking or non-masking of TEMP1 error requests." "0: Errors are masked,1: The mask is cleared" line.long 0x8 "IRQCTL,Threshold Edge/Level Register" bitfld.long 0x8 5. "TEMPD3_EL,Specifies the method for detection of the TEMPD3 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 4. "TEMPD2_EL,Specifies the method for detection of the TEMPD2 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 3. "TEMPD1_EL,Specifies the method for detection of the TEMPD1 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 2. "TEMP3_EL,Specifies the method for detection of the TEMP3 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 1. "TEMP2_EL,Specifies the method for detection of the TEMP2 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 0. "TEMP1_EL,Specifies the method for detection of the TEMP1 error signal input." "0: Edge detection,1: Level detection" line.long 0xC "IRQEN,Temperature Error Enable Register" bitfld.long 0xC 5. "TEMPD3_EN,This bit enables or disables TEMPD3 errors." "0: TEMPD3 errors are disabled,1: TEMPD3 errors are enabled" newline bitfld.long 0xC 4. "TEMPD2_EN,This bit enables or disables TEMPD2 errors." "0: TEMPD2 errors are disabled,1: TEMPD2 errors are enabled" newline bitfld.long 0xC 3. "TEMPD1_EN,This bit enables or disables TEMPD1 errors." "0: TEMPD1 errors are disabled,1: TEMPD1 errors are enabled" newline bitfld.long 0xC 2. "TEMP3_EN,This bit enables or disables TEMP3 errors." "0: TEMP3 errors are disabled,1: TEMP3 errors are enabled" newline bitfld.long 0xC 1. "TEMP2_EN,This bit enables or disables TEMP2 errors." "0: TEMP2 errors are disabled,1: TEMP2 errors are enabled" newline bitfld.long 0xC 0. "TEMP1_EN,This bit enables or disables TEMP1 errors." "0: TEMP1 errors are disabled,1: TEMP1 errors are enabled" line.long 0x10 "IRQTEMP1,Temperature Error 1 Register" bitfld.long 0x10 12.--13. "IRQTEMP1,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors." "0,1,2,3" newline hexmask.long.word 0x10 0.--11. 1. "IRQTEMP1,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors." line.long 0x14 "IRQTEMP2,Temperature Error 2 Register" bitfld.long 0x14 12.--13. "IRQTEMP2,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors." "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "IRQTEMP2,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors." line.long 0x18 "IRQTEMP3,Temperature Error 3 Register" bitfld.long 0x18 12.--13. "IRQTEMP3,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors." "0,1,2,3" newline hexmask.long.word 0x18 0.--11. 1. "IRQTEMP3,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors." line.long 0x1C "THCTR,Control Register" bitfld.long 0x1C 28.--30. "VOLSELB,Select the chip internal voltage monitor input" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline bitfld.long 0x1C 24. "CTCTL,Select write condition of THREFTAP THCNTSEN and VMCNTSEN" "0: Inhibit write of these bits,1: Allow write of these bits" newline bitfld.long 0x1C 20. "CIVMTST,THS/CIVM failure check mode" "0: Normal mode,1: THS/CIVM failure check mode" newline bitfld.long 0x1C 18.--19. "VMCNTSEN,Select the bit number of A/D converter in CIVM" "0: 10bits,1: 12bits,?,?" newline bitfld.long 0x1C 16.--17. "THCNTSEN,Select the bit number of A/D converter in THS" "0: 12bits,1: 10bits,?,?" newline bitfld.long 0x1C 12.--14. "VOLSELA,Select the chip internal voltage monitor input" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline bitfld.long 0x1C 8.--9. "SENSSEL,Select the use sensor" "0: THS,1: THS ON only,?,?" newline bitfld.long 0x1C 6. "PONM,Select mode signal" "0: Normal mode,1: Power-on mode" newline bitfld.long 0x1C 5. "THEN,Enabling/disabling of thermal sensor" "0: Enabled,1: Disabled" newline bitfld.long 0x1C 0. "THSST,Enabling/disabling of the A/D converter for the thermal sensor" "0: Disabled,1: Enabled" rgroup.long 0x24++0x43 line.long 0x0 "THSTR,Status Register" bitfld.long 0x0 3. "THACKMON,THACK signal monitor" "0: Not detected,1: THCODE was generated" newline bitfld.long 0x0 2. "THCNTOV_MON,THCNTOV signal monitor" "0: Not detected,1: Detected overflow" newline bitfld.long 0x0 1. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1" newline bitfld.long 0x0 0. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0" line.long 0x4 "TEMP_YN,Temperature1 Register ( Y(n) )" bitfld.long 0x4 12.--13. "TEMP_CODE_YN,These bits indicate the digital value for the temperature detected by the thermal sensor." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "TEMP_CODE_YN,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x8 "VOLT,Voltage Register" hexmask.long.byte 0x8 10.--13. 1. "VOLT_CODE,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." newline hexmask.long.word 0x8 0.--9. 1. "VOLT_CODE,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." line.long 0xC "TEMP_X,Temperature1 Register ( X(n) )" hexmask.long.word 0xC 0.--13. 1. "TEMP_X,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x10 "TEMP_YN1,Temperature2 Register ( Y(n-1) )" hexmask.long.word 0x10 0.--13. 1. "TEMP_YN1,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x14 "TEMP_X1,Temperature3 Register ( X(n-1) )" hexmask.long.word 0x14 0.--13. 1. "TEMP_X1,These bits indicate the digital value for the one before temperature detected by the thermal sensor." line.long 0x18 "THINITSTR,Power ON Initial Temperature Status Register" bitfld.long 0x18 3. "NRMEND,Completion flag of capturing the temperatures in the power-on mode" "0: Not complete,1: Complete" newline bitfld.long 0x18 2. "THTMP3,Detection of capturing the third temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" newline bitfld.long 0x18 1. "THTMP2,Detection of capturing the second temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" newline bitfld.long 0x18 0. "THTMP1,Detection of capturing the first temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" line.long 0x1C "THCODE_INT1,Power ON Initial 1 Temperature Register" hexmask.long.word 0x1C 0.--11. 1. "THCODE_INT1,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x20 "THCODE_INT2,Power ON Initial 2 Temperature Register" hexmask.long.word 0x20 0.--11. 1. "THCODE_INT2,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x24 "THCODE_INT3,Power ON Initial 3 Temperature Register" hexmask.long.word 0x24 0.--11. 1. "THCODE_INT3,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x28 "CVCREG,Convert Correction Register" hexmask.long.word 0x28 0.--11. 1. "CCREG,Parameter to be used in adjusting the characteristics" line.long 0x2C "THCODE1,THCODE Parameter1 Register" hexmask.long.word 0x2C 0.--11. 1. "THCODE1,Parameter to be used in adjusting the characteristics" line.long 0x30 "THCODE2,THCODE Parameter2 Register" hexmask.long.word 0x30 0.--11. 1. "THCODE2,Parameter to be used in adjusting the characteristics" line.long 0x34 "THCODE3,THCODE Parameter3 Register" hexmask.long.word 0x34 0.--11. 1. "THCODE3,Parameter to be used in adjusting the characteristics" line.long 0x38 "PTAT1,PTAT Parameter1 Register" hexmask.long.word 0x38 16.--27. 1. "PTAT1_0,Parameter to be used in adjusting the characteristics." newline hexmask.long.word 0x38 0.--11. 1. "PTAT1,Parameter to be used in adjusting the characteristics" line.long 0x3C "PTAT2,PTAT Parameter2 Register" hexmask.long.word 0x3C 0.--11. 1. "PTAT2,Parameter to be used in adjusting the characteristics" line.long 0x40 "PTAT3,PTAT Parameter3 Register" hexmask.long.word 0x40 16.--27. 1. "PTAT3_0,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x40 0.--11. 1. "PTAT3,Parameter to be used in adjusting the characteristics" group.long 0x6C++0x13 line.long 0x0 "IRQ_INJECTION,Error Injection Register" bitfld.long 0x0 5. "TEMPD3_INJ,TEMPD3 Error Injection" "0: IRQTEMP3 Error Injection Disable,1: IRQTEMP3 Error Injection Enable" newline bitfld.long 0x0 4. "TEMPD2_INJ,TEMPD2 Error Injection" "0: IRQTEMP2 Error Injection Disable,1: IRQTEMP2 Error Injection Enable" newline bitfld.long 0x0 3. "TEMPD1_INJ,TEMPD1 Error Injection" "0: IRQTEMP1 Error Injection Disable,1: IRQTEMP1 Error Injection Enable" newline bitfld.long 0x0 2. "TEMP3_INJ,TEMP3 Error Injection" "0: IRQTEMP3 Error Injection Disable,1: IRQTEMP3 Error Injection Enable" newline bitfld.long 0x0 1. "TEMP2_INJ,TEMP2 Error Injection" "0: IRQTEMP2 Error Injection Disable,1: IRQTEMP2 Error Injection Enable" newline bitfld.long 0x0 0. "TEMP1_INJ,TEMP1 Error Injection" "0: IRQTEMP1 Error Injection Disable,1: IRQTEMP1 Error Injection Enable" line.long 0x4 "ACK_TIMEOUT,Ack Timeout Register" hexmask.long.word 0x4 0.--13. 1. "ACK_TIMEOUT_REG,THACK timeout setting" line.long 0x8 "TSC_ERROR_CTL,TSC Error Control Register" bitfld.long 0x8 0. "TSC_ERR_CTL,TSC error injection" "0: Error injection off,1: Error injection on" line.long 0xC "THSOUTCTL,THS Output Control Register" bitfld.long 0xC 28. "THACKMASK,THACK mask enable" "0: Disable THACK mask,1: Enable THACK mask" newline bitfld.long 0xC 24. "THCNTOVCTL,THCNTOV select" "0: THCNTOV from THS,1: THCNTOV_TESTDT" newline bitfld.long 0xC 20. "THCODECTL,THCODE select" "0: THCODE from THS,1: THCODE_TESTDT" newline bitfld.long 0xC 16. "THCNTOV_TESTDT,THCNTOV test data setting" "0,1" newline hexmask.long.word 0xC 0.--13. 1. "THCODE_TESTDT,THCODE test data setting" line.long 0x10 "SEQ_RESET,Sequence Reset Register" bitfld.long 0x10 0. "SEQ_RESET,This bit initializes the sequence and error value." "0,1" rgroup.long 0x80++0x1F line.long 0x0 "PON_TEMP,Power On Temperature Register" hexmask.long.word 0x0 0.--13. 1. "PON_TEMP_CODE_YN,These bits indicate the digital value detected by the temperature sensor during Power On mode." line.long 0x4 "NML_TEMP,Normal Temperature Register" hexmask.long.word 0x4 0.--13. 1. "NML_TEMP_CODE_YN,These bits indicate the digital value detected by the temperature sensor during Normal mode." line.long 0x8 "NML_VOLT,Normal Voltage Register" hexmask.long.word 0x8 0.--13. 1. "NML_VOLT_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during Normal mode." line.long 0xC "CIVMTST_VOLT1,CIVM Test Voltage1 Register" hexmask.long.word 0xC 0.--13. 1. "CIVMTST_VOLT1_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode1." line.long 0x10 "CIVMTST_VOLT2,CIVM Test Voltage2 Register" hexmask.long.word 0x10 0.--13. 1. "CIVMTST_VOLT2_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode2." line.long 0x14 "CIVMTST_VOLT3,CIVM Test Voltage3 Register" hexmask.long.word 0x14 0.--13. 1. "CIVMTST_VOLT3_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode3." line.long 0x18 "CIVMTST_VOLT4,CIVM Test Voltage4 Register" hexmask.long.word 0x18 0.--13. 1. "CIVMTST_VOLT4_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode4." line.long 0x1C "MANTST_VOLT,Manual Test Voltage Register" hexmask.long.word 0x1C 0.--13. 1. "MANTST_VOLT_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during Manual test mode." rgroup.long 0xA8++0x3 line.long 0x0 "VOLT_YN,Voltage Register ( Y(n) )" hexmask.long.word 0x0 0.--11. 1. "VOLT_CODE_YN,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." rgroup.long 0xB0++0x3 line.long 0x0 "VOLT_X,Voltage 1 Register ( X(n) )" hexmask.long.word 0x0 0.--13. 1. "VOLT_CODE_X,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." rgroup.long 0xB8++0x3 line.long 0x0 "VOLT_X1,Voltage 2 Register ( X(n-1) )" hexmask.long.word 0x0 0.--13. 1. "VOLT_CODE_X1,These bits indicate the digital value for the one before voltage detected by the chip internal voltage monitor." rgroup.long 0xD0++0x27 line.long 0x0 "VMCODE1,VMCODE Parameter1 Register" hexmask.long.word 0x0 16.--25. 1. "VMCODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x0 0.--9. 1. "VMCODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x4 "VMCODE2,VMCODE Parameter2 Register" hexmask.long.word 0x4 16.--25. 1. "VMCODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x4 0.--9. 1. "VMCODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x8 "VMCODE3,VMCODE Parameter3 Register" hexmask.long.word 0x8 16.--25. 1. "VMCODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x8 0.--9. 1. "VMCODE3_L,Parameter to be used in adjusting the characteristics" line.long 0xC "HVMCODE1,High VMCODE Parameter1 Register" hexmask.long.word 0xC 16.--25. 1. "VC18CODE1,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0xC 0.--9. 1. "VM11CODE1,Parameter to be used in adjusting the characteristics" line.long 0x10 "HVMCODE2,High VMCODE Parameter2 Register" hexmask.long.word 0x10 16.--25. 1. "VC18CODE2,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x10 0.--9. 1. "VM11CODE2,Parameter to be used in adjusting the characteristics" line.long 0x14 "HVMCODE3,High VMCODE Parameter3 Register" hexmask.long.word 0x14 16.--25. 1. "VC18CODE3,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x14 0.--9. 1. "VM11CODE3,Parameter to be used in adjusting the characteristics" line.long 0x18 "INBUF_OFF1,Input Buffer Offset1 Register" hexmask.long.word 0x18 0.--9. 1. "INBUF_OFF1" line.long 0x1C "INBUF_OFF2,Input Buffer Offset2 Register" hexmask.long.word 0x1C 0.--9. 1. "INBUF_OFF2" line.long 0x20 "INBUF_OFF3,Input Buffer Offset3 Register" hexmask.long.word 0x20 0.--9. 1. "INBUF_OFF3" line.long 0x24 "THS_RATIO,THS RATIO Register" hexmask.long.word 0x24 0.--15. 1. "THS_RATIO" group.long 0x100++0x3 line.long 0x0 "CVM_EN,CVM Enable Register" bitfld.long 0x0 0. "CVM_EN,This bit is a value enable signal." "0,1" rgroup.long 0x108++0x7 line.long 0x0 "CVM_CTRL_BK,CVM Control Readback Register" bitfld.long 0x0 12. "THEN_BK,This bit can monitor the readback value of THEN in THCTR register." "0,1" newline bitfld.long 0x0 8. "OUTPC_BK,This bit can monitor the readback value of OUTPC in CVM_CTRL register." "0,1" newline bitfld.long 0x0 4. "EXTERNAL_FS_BK,This bit can monitor the readback value of EXTERNAL_FS in CVM_CTRL register." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CHOICE_PLACE_BK,These bits can monitor the readback value of CHOICE_PLACE [3:0] in CVM_CTRL register." line.long 0x4 "CVM_DETECT_MON,CVM Detection Voltage Setting Monitor Register" bitfld.long 0x4 24.--26. "MODE_MAX_MON,These bits can monitor the applicable trimming bits for maximum voltage side." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--19. 1. "TRIM_MAX_MON,These bits can monitor the applicable trimming bits for maximum voltage side." newline bitfld.long 0x4 8.--10. "MODE_MIN_MON,These bits can monitor the applicable trimming bits for minimum voltage side." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "TRIM_MIN_MON,These bits can monitor the applicable trimming bits for minimum voltage side." group.long 0x110++0x3 line.long 0x0 "CVM_DETECT_MANUAL_SET,CVM Detection Voltage Manual Setting Register" bitfld.long 0x0 28. "CVM_DETECT_SEL_MAX,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register." "0: The values of bits 26 to 24 and bits 19 to 16 in..,1: The values of bits 26 to 24 and bits 19 to 16 in.." newline bitfld.long 0x0 24.--26. "MODE_MAX,When bit 1 in CVM_CTRL register is 1’b1 these bits are enabled." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "TRIM_MAX,When bit 1 in CVM_CTRL register is 1’b1 these bits are enabled." newline bitfld.long 0x0 12. "CVM_DETECT_SEL_MIN,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register." "0: The values of bits 10 to 8 and bits 3 to 0 in..,1: The values of bits 10 to 8 and bits 3 to 0 in.." newline bitfld.long 0x0 8.--10. "MODE_MIN,When bit 0 in CVM_CTRL register is 1’b1 these bits are enabled." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "TRIM_MIN,When bit 0 in CVM_CTRL register is 1’b1 these bits are enabled." rgroup.long 0x114++0x7 line.long 0x0 "CVM_DETECT_SET_BK,CVM Detection Voltage Setting Readback Register" bitfld.long 0x0 24.--26. "MODE_MAX_BK,These bits can monitor the readback value of MODE_MAX[2:0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "TRIM_MAX_BK,These bits can monitor the readback value of TRIM_MAX[3:0]." newline bitfld.long 0x0 8.--10. "MODE_MIN_BK,These bits can monitor the readback value of MODE_MIN[2:0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "TRIM_MIN_BK,These bits can monitor the readback value of TRIM_MIN[3:0]." line.long 0x4 "CVM_TOFF_MON,CVM Temp Offset Monitor Register" hexmask.long.byte 0x4 0.--3. 1. "TOFF_MON,These bits can monitor trimming values." group.long 0x11C++0x3 line.long 0x0 "CVM_TOFF_MANUAL_SET,CVM Temp Offset Manual Setting Register" bitfld.long 0x0 12. "TOFF_SEL,This bit selects either CVM_TOFF_MON register or CVM_TOFF_MANUAL_SET register." "0: Select value that bit 3 to 0 in CVM_TOFF_MON..,1: Select value that bit 3 to 0 in.." newline hexmask.long.byte 0x0 0.--3. 1. "TOFF,When bit 4 in CVM_CTRL register is 1’b1 these bits are enabled." rgroup.long 0x120++0x3 line.long 0x0 "CVM_TOFF_BK,CVM Temp Offset Readback Register" hexmask.long.byte 0x0 0.--3. 1. "TOFF_BK,These bits can monitor the readback value of TOFF[3:0]." rgroup.long 0x128++0xF line.long 0x0 "STATMON1,State Monitor1 Register" hexmask.long.byte 0x0 24.--31. 1. "NML_STAT,Normal sequence state monitor" newline hexmask.long.byte 0x0 16.--23. 1. "PON_STAT,Power on sequence state monitor" newline hexmask.long.byte 0x0 8.--15. 1. "TST_STAT,Test sequence state monitor" newline hexmask.long.byte 0x0 0.--7. 1. "CTRL_STAT,Sequence control state monitor" line.long 0x4 "STATMON2,State Monitor2 Register" hexmask.long.byte 0x4 8.--15. 1. "MANTST_STAT,Manual test sequence state monitor" newline hexmask.long.byte 0x4 0.--7. 1. "CIVMTST_STAT,CIVM test sequence state monitor" line.long 0x8 "TSC_ERROR_MON,TSC Error Monitor Register" bitfld.long 0x8 7. "ERR_ACKTOV,THACK timeout error status" "0: no error,1: THACK timeout error" newline bitfld.long 0x8 6. "ERR_TST4,THCODE connection check(Test4) error status" "0: no error,1: THCODE connection check" newline bitfld.long 0x8 5. "ERR_TST5,THCODE connection check(Test5) error status" "0: no error,1: THCODE connection check" newline bitfld.long 0x8 4. "ERR_THCODE,THCODE error status" "0: no error,1: THCODE error" newline bitfld.long 0x8 3. "ERR_THCNTOV,THCNTOV error status" "0: no error,1: THCNTOV error" newline bitfld.long 0x8 2. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1" newline bitfld.long 0x8 1. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0" newline bitfld.long 0x8 0. "TSC_ERROR,TSC error status" "0: no error,1: TSC error" line.long 0xC "THCODE_MON,THCODE Monitor Register" bitfld.long 0xC 30. "TST4_THCNTOV,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test4)." "0,1" newline hexmask.long.word 0xC 16.--29. 1. "TST4_THCODE,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test4)." newline bitfld.long 0xC 14. "TST5_THCNTOV,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test5)." "0,1" newline hexmask.long.word 0xC 0.--13. 1. "TST5_THCODE,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test5)." group.long 0x138++0x3 line.long 0x0 "MANTST_SET_DT,Manual Test Mode Data Register" bitfld.long 0x0 28. "MANTST_REG,Manual test mode" "0: Normal mode,1: Manual test mode" newline bitfld.long 0x0 24. "MAN_THCHOP,Select the Manual THCHOP mode" "0: THCHOP=0 on Manual test mode,1: THCHOP=1 on Manual test mode" newline bitfld.long 0x0 12.--13. "MAN_THCNTSEL,Select the bit number of A/D converter for manual test" "0: 12bits,1: 10bits,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "MAN_THMODE,Select THMODE for manual test." newline bitfld.long 0x0 4.--6. "MAN_THVMSEL_A,Select chip internal voltage monitor input for manual test" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "MAN_THVMSEL_B,Select chip internal voltage monitor input for manual test" rgroup.long 0x13C++0x7 line.long 0x0 "TMR_DT,Timer Data Register" hexmask.long.tbyte 0x0 12.--29. 1. "ACKTMR,THACK timer monitor" newline hexmask.long.word 0x0 0.--9. 1. "GPTMR,General purpose timer monitor" line.long 0x4 "SEQ_ACT_MON,Sequence Act Signal Monitor Register" bitfld.long 0x4 17. "TSTSEQ_DONE,This bit indicates that the THCODE Connection Test Sequence has completed" "0: Not completed,1: Completed" newline bitfld.long 0x4 16. "STBYSEQ_DONE,This bit indicates that the THS Standby Setting Sequence has completed" "0: Not completed,1: Completed" newline hexmask.long.byte 0x4 0.--4. 1. "SEQ_ACT,Sequence Act Flag monitor" rgroup.long 0x14C++0x27 line.long 0x0 "VM_MON,CVM Monitor Register" bitfld.long 0x0 0.--1. "VM_08_S,These bits can monitor CVM status" "0: Under Voltage,1: Normal,?,?" line.long 0x4 "VM06CODE1,VM06CODE Parameter1 Register" hexmask.long.word 0x4 16.--25. 1. "VM06CODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x4 0.--9. 1. "VM06CODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x8 "VM06CODE2,VM06CODE Parameter2 Register" hexmask.long.word 0x8 16.--25. 1. "VM06CODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x8 0.--9. 1. "VM06CODE2_L,Parameter to be used in adjusting the characteristics" line.long 0xC "VM06CODE3,VM06CODE Parameter3 Register" hexmask.long.word 0xC 16.--25. 1. "VM06CODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0xC 0.--9. 1. "VM06CODE3_L,Parameter to be used in adjusting the characteristics" line.long 0x10 "VM11CODE1,VM11CODE Parameter1 Register" hexmask.long.word 0x10 16.--25. 1. "VM11CODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x10 0.--9. 1. "VM11CODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x14 "VM11CODE2,VM11CODE Parameter2 Register" hexmask.long.word 0x14 16.--25. 1. "VM11CODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x14 0.--9. 1. "VM11CODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x18 "VM11CODE3,VM11CODE Parameter3 Register" hexmask.long.word 0x18 16.--25. 1. "VM11CODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x18 0.--9. 1. "VM11CODE3_L,Parameter to be used in adjusting the characteristics" line.long 0x1C "VMCVMCODE1,VCC VMCODE Parameter1 Register" hexmask.long.word 0x1C 16.--25. 1. "VCCVMCODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x1C 0.--9. 1. "VCCVMCODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x20 "VMCVMCODE2,VCC VMCODE Parameter2 Register" hexmask.long.word 0x20 16.--25. 1. "VCCVMCODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x20 0.--9. 1. "VCCVMCODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x24 "VMCVMCODE3,VCC VMCODE Parameter3 Register" hexmask.long.word 0x24 16.--25. 1. "VCCVMCODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x24 0.--9. 1. "VCCVMCODE3_L,Parameter to be used in adjusting the characteristics" tree.end tree "TSC_3" base ad:0xE61A0000 rgroup.long 0x0++0x3 line.long 0x0 "THSIRQSTR,THS Temperature Error Status Register" bitfld.long 0x0 2. "IRQ3,Temperature Error3 Status" "0: Not detected,1: Temperature Error3 for thermal sensor is detected" newline bitfld.long 0x0 1. "IRQ2,Temperature Error2 Status" "0: Not detected,1: Temperature Error2 for thermal sensor is detected" newline bitfld.long 0x0 0. "IRQ1,Temperature Error1 Status" "0: Not detected,1: Temperature Error1 for thermal sensor is detected" group.long 0x4++0x1F line.long 0x0 "IRQSTR,Temperature Error Status Register" bitfld.long 0x0 5. "TEMPD3_STR,TEMPD3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 4. "TEMPD2_STR,TEMPD2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 3. "TEMPD1_STR,TEMPD1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 2. "TEMP3_STR,TEMP3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." newline bitfld.long 0x0 1. "TEMP2_STR,TEMP2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." newline bitfld.long 0x0 0. "TEMP1_STR,TEMP1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." line.long 0x4 "IRQMSK,Temperature Error Mask Register" bitfld.long 0x4 5. "TEMPD3_MSK,This bit selects masking or non-masking of TEMPD3 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 4. "TEMPD2_MSK,This bit selects masking or non-masking of TEMPD2 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 3. "TEMPD1_MSK,This bit selects masking or non-masking of TEMPD1 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 2. "TEMP3_MSK,This bit selects masking or non-masking of TEMP3 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 1. "TEMP2_MSK,This bit selects masking or non-masking of TEMP2 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 0. "TEMP1_MSK,This bit selects masking or non-masking of TEMP1 error requests." "0: Errors are masked,1: The mask is cleared" line.long 0x8 "IRQCTL,Threshold Edge/Level Register" bitfld.long 0x8 5. "TEMPD3_EL,Specifies the method for detection of the TEMPD3 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 4. "TEMPD2_EL,Specifies the method for detection of the TEMPD2 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 3. "TEMPD1_EL,Specifies the method for detection of the TEMPD1 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 2. "TEMP3_EL,Specifies the method for detection of the TEMP3 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 1. "TEMP2_EL,Specifies the method for detection of the TEMP2 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 0. "TEMP1_EL,Specifies the method for detection of the TEMP1 error signal input." "0: Edge detection,1: Level detection" line.long 0xC "IRQEN,Temperature Error Enable Register" bitfld.long 0xC 5. "TEMPD3_EN,This bit enables or disables TEMPD3 errors." "0: TEMPD3 errors are disabled,1: TEMPD3 errors are enabled" newline bitfld.long 0xC 4. "TEMPD2_EN,This bit enables or disables TEMPD2 errors." "0: TEMPD2 errors are disabled,1: TEMPD2 errors are enabled" newline bitfld.long 0xC 3. "TEMPD1_EN,This bit enables or disables TEMPD1 errors." "0: TEMPD1 errors are disabled,1: TEMPD1 errors are enabled" newline bitfld.long 0xC 2. "TEMP3_EN,This bit enables or disables TEMP3 errors." "0: TEMP3 errors are disabled,1: TEMP3 errors are enabled" newline bitfld.long 0xC 1. "TEMP2_EN,This bit enables or disables TEMP2 errors." "0: TEMP2 errors are disabled,1: TEMP2 errors are enabled" newline bitfld.long 0xC 0. "TEMP1_EN,This bit enables or disables TEMP1 errors." "0: TEMP1 errors are disabled,1: TEMP1 errors are enabled" line.long 0x10 "IRQTEMP1,Temperature Error 1 Register" bitfld.long 0x10 12.--13. "IRQTEMP1,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors." "0,1,2,3" newline hexmask.long.word 0x10 0.--11. 1. "IRQTEMP1,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors." line.long 0x14 "IRQTEMP2,Temperature Error 2 Register" bitfld.long 0x14 12.--13. "IRQTEMP2,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors." "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "IRQTEMP2,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors." line.long 0x18 "IRQTEMP3,Temperature Error 3 Register" bitfld.long 0x18 12.--13. "IRQTEMP3,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors." "0,1,2,3" newline hexmask.long.word 0x18 0.--11. 1. "IRQTEMP3,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors." line.long 0x1C "THCTR,Control Register" bitfld.long 0x1C 28.--30. "VOLSELB,Select the chip internal voltage monitor input" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline bitfld.long 0x1C 24. "CTCTL,Select write condition of THREFTAP THCNTSEN and VMCNTSEN" "0: Inhibit write of these bits,1: Allow write of these bits" newline bitfld.long 0x1C 20. "CIVMTST,THS/CIVM failure check mode" "0: Normal mode,1: THS/CIVM failure check mode" newline bitfld.long 0x1C 18.--19. "VMCNTSEN,Select the bit number of A/D converter in CIVM" "0: 10bits,1: 12bits,?,?" newline bitfld.long 0x1C 16.--17. "THCNTSEN,Select the bit number of A/D converter in THS" "0: 12bits,1: 10bits,?,?" newline bitfld.long 0x1C 12.--14. "VOLSELA,Select the chip internal voltage monitor input" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline bitfld.long 0x1C 8.--9. "SENSSEL,Select the use sensor" "0: THS,1: THS ON only,?,?" newline bitfld.long 0x1C 6. "PONM,Select mode signal" "0: Normal mode,1: Power-on mode" newline bitfld.long 0x1C 5. "THEN,Enabling/disabling of thermal sensor" "0: Enabled,1: Disabled" newline bitfld.long 0x1C 0. "THSST,Enabling/disabling of the A/D converter for the thermal sensor" "0: Disabled,1: Enabled" rgroup.long 0x24++0x43 line.long 0x0 "THSTR,Status Register" bitfld.long 0x0 3. "THACKMON,THACK signal monitor" "0: Not detected,1: THCODE was generated" newline bitfld.long 0x0 2. "THCNTOV_MON,THCNTOV signal monitor" "0: Not detected,1: Detected overflow" newline bitfld.long 0x0 1. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1" newline bitfld.long 0x0 0. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0" line.long 0x4 "TEMP_YN,Temperature1 Register ( Y(n) )" bitfld.long 0x4 12.--13. "TEMP_CODE_YN,These bits indicate the digital value for the temperature detected by the thermal sensor." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "TEMP_CODE_YN,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x8 "VOLT,Voltage Register" hexmask.long.byte 0x8 10.--13. 1. "VOLT_CODE,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." newline hexmask.long.word 0x8 0.--9. 1. "VOLT_CODE,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." line.long 0xC "TEMP_X,Temperature1 Register ( X(n) )" hexmask.long.word 0xC 0.--13. 1. "TEMP_X,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x10 "TEMP_YN1,Temperature2 Register ( Y(n-1) )" hexmask.long.word 0x10 0.--13. 1. "TEMP_YN1,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x14 "TEMP_X1,Temperature3 Register ( X(n-1) )" hexmask.long.word 0x14 0.--13. 1. "TEMP_X1,These bits indicate the digital value for the one before temperature detected by the thermal sensor." line.long 0x18 "THINITSTR,Power ON Initial Temperature Status Register" bitfld.long 0x18 3. "NRMEND,Completion flag of capturing the temperatures in the power-on mode" "0: Not complete,1: Complete" newline bitfld.long 0x18 2. "THTMP3,Detection of capturing the third temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" newline bitfld.long 0x18 1. "THTMP2,Detection of capturing the second temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" newline bitfld.long 0x18 0. "THTMP1,Detection of capturing the first temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" line.long 0x1C "THCODE_INT1,Power ON Initial 1 Temperature Register" hexmask.long.word 0x1C 0.--11. 1. "THCODE_INT1,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x20 "THCODE_INT2,Power ON Initial 2 Temperature Register" hexmask.long.word 0x20 0.--11. 1. "THCODE_INT2,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x24 "THCODE_INT3,Power ON Initial 3 Temperature Register" hexmask.long.word 0x24 0.--11. 1. "THCODE_INT3,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x28 "CVCREG,Convert Correction Register" hexmask.long.word 0x28 0.--11. 1. "CCREG,Parameter to be used in adjusting the characteristics" line.long 0x2C "THCODE1,THCODE Parameter1 Register" hexmask.long.word 0x2C 0.--11. 1. "THCODE1,Parameter to be used in adjusting the characteristics" line.long 0x30 "THCODE2,THCODE Parameter2 Register" hexmask.long.word 0x30 0.--11. 1. "THCODE2,Parameter to be used in adjusting the characteristics" line.long 0x34 "THCODE3,THCODE Parameter3 Register" hexmask.long.word 0x34 0.--11. 1. "THCODE3,Parameter to be used in adjusting the characteristics" line.long 0x38 "PTAT1,PTAT Parameter1 Register" hexmask.long.word 0x38 16.--27. 1. "PTAT1_0,Parameter to be used in adjusting the characteristics." newline hexmask.long.word 0x38 0.--11. 1. "PTAT1,Parameter to be used in adjusting the characteristics" line.long 0x3C "PTAT2,PTAT Parameter2 Register" hexmask.long.word 0x3C 0.--11. 1. "PTAT2,Parameter to be used in adjusting the characteristics" line.long 0x40 "PTAT3,PTAT Parameter3 Register" hexmask.long.word 0x40 16.--27. 1. "PTAT3_0,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x40 0.--11. 1. "PTAT3,Parameter to be used in adjusting the characteristics" group.long 0x6C++0x13 line.long 0x0 "IRQ_INJECTION,Error Injection Register" bitfld.long 0x0 5. "TEMPD3_INJ,TEMPD3 Error Injection" "0: IRQTEMP3 Error Injection Disable,1: IRQTEMP3 Error Injection Enable" newline bitfld.long 0x0 4. "TEMPD2_INJ,TEMPD2 Error Injection" "0: IRQTEMP2 Error Injection Disable,1: IRQTEMP2 Error Injection Enable" newline bitfld.long 0x0 3. "TEMPD1_INJ,TEMPD1 Error Injection" "0: IRQTEMP1 Error Injection Disable,1: IRQTEMP1 Error Injection Enable" newline bitfld.long 0x0 2. "TEMP3_INJ,TEMP3 Error Injection" "0: IRQTEMP3 Error Injection Disable,1: IRQTEMP3 Error Injection Enable" newline bitfld.long 0x0 1. "TEMP2_INJ,TEMP2 Error Injection" "0: IRQTEMP2 Error Injection Disable,1: IRQTEMP2 Error Injection Enable" newline bitfld.long 0x0 0. "TEMP1_INJ,TEMP1 Error Injection" "0: IRQTEMP1 Error Injection Disable,1: IRQTEMP1 Error Injection Enable" line.long 0x4 "ACK_TIMEOUT,Ack Timeout Register" hexmask.long.word 0x4 0.--13. 1. "ACK_TIMEOUT_REG,THACK timeout setting" line.long 0x8 "TSC_ERROR_CTL,TSC Error Control Register" bitfld.long 0x8 0. "TSC_ERR_CTL,TSC error injection" "0: Error injection off,1: Error injection on" line.long 0xC "THSOUTCTL,THS Output Control Register" bitfld.long 0xC 28. "THACKMASK,THACK mask enable" "0: Disable THACK mask,1: Enable THACK mask" newline bitfld.long 0xC 24. "THCNTOVCTL,THCNTOV select" "0: THCNTOV from THS,1: THCNTOV_TESTDT" newline bitfld.long 0xC 20. "THCODECTL,THCODE select" "0: THCODE from THS,1: THCODE_TESTDT" newline bitfld.long 0xC 16. "THCNTOV_TESTDT,THCNTOV test data setting" "0,1" newline hexmask.long.word 0xC 0.--13. 1. "THCODE_TESTDT,THCODE test data setting" line.long 0x10 "SEQ_RESET,Sequence Reset Register" bitfld.long 0x10 0. "SEQ_RESET,This bit initializes the sequence and error value." "0,1" rgroup.long 0x80++0x1F line.long 0x0 "PON_TEMP,Power On Temperature Register" hexmask.long.word 0x0 0.--13. 1. "PON_TEMP_CODE_YN,These bits indicate the digital value detected by the temperature sensor during Power On mode." line.long 0x4 "NML_TEMP,Normal Temperature Register" hexmask.long.word 0x4 0.--13. 1. "NML_TEMP_CODE_YN,These bits indicate the digital value detected by the temperature sensor during Normal mode." line.long 0x8 "NML_VOLT,Normal Voltage Register" hexmask.long.word 0x8 0.--13. 1. "NML_VOLT_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during Normal mode." line.long 0xC "CIVMTST_VOLT1,CIVM Test Voltage1 Register" hexmask.long.word 0xC 0.--13. 1. "CIVMTST_VOLT1_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode1." line.long 0x10 "CIVMTST_VOLT2,CIVM Test Voltage2 Register" hexmask.long.word 0x10 0.--13. 1. "CIVMTST_VOLT2_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode2." line.long 0x14 "CIVMTST_VOLT3,CIVM Test Voltage3 Register" hexmask.long.word 0x14 0.--13. 1. "CIVMTST_VOLT3_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode3." line.long 0x18 "CIVMTST_VOLT4,CIVM Test Voltage4 Register" hexmask.long.word 0x18 0.--13. 1. "CIVMTST_VOLT4_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode4." line.long 0x1C "MANTST_VOLT,Manual Test Voltage Register" hexmask.long.word 0x1C 0.--13. 1. "MANTST_VOLT_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during Manual test mode." rgroup.long 0xA8++0x3 line.long 0x0 "VOLT_YN,Voltage Register ( Y(n) )" hexmask.long.word 0x0 0.--11. 1. "VOLT_CODE_YN,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." rgroup.long 0xB0++0x3 line.long 0x0 "VOLT_X,Voltage 1 Register ( X(n) )" hexmask.long.word 0x0 0.--13. 1. "VOLT_CODE_X,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." rgroup.long 0xB8++0x3 line.long 0x0 "VOLT_X1,Voltage 2 Register ( X(n-1) )" hexmask.long.word 0x0 0.--13. 1. "VOLT_CODE_X1,These bits indicate the digital value for the one before voltage detected by the chip internal voltage monitor." rgroup.long 0xD0++0x27 line.long 0x0 "VMCODE1,VMCODE Parameter1 Register" hexmask.long.word 0x0 16.--25. 1. "VMCODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x0 0.--9. 1. "VMCODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x4 "VMCODE2,VMCODE Parameter2 Register" hexmask.long.word 0x4 16.--25. 1. "VMCODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x4 0.--9. 1. "VMCODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x8 "VMCODE3,VMCODE Parameter3 Register" hexmask.long.word 0x8 16.--25. 1. "VMCODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x8 0.--9. 1. "VMCODE3_L,Parameter to be used in adjusting the characteristics" line.long 0xC "HVMCODE1,High VMCODE Parameter1 Register" hexmask.long.word 0xC 16.--25. 1. "VC18CODE1,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0xC 0.--9. 1. "VM11CODE1,Parameter to be used in adjusting the characteristics" line.long 0x10 "HVMCODE2,High VMCODE Parameter2 Register" hexmask.long.word 0x10 16.--25. 1. "VC18CODE2,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x10 0.--9. 1. "VM11CODE2,Parameter to be used in adjusting the characteristics" line.long 0x14 "HVMCODE3,High VMCODE Parameter3 Register" hexmask.long.word 0x14 16.--25. 1. "VC18CODE3,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x14 0.--9. 1. "VM11CODE3,Parameter to be used in adjusting the characteristics" line.long 0x18 "INBUF_OFF1,Input Buffer Offset1 Register" hexmask.long.word 0x18 0.--9. 1. "INBUF_OFF1" line.long 0x1C "INBUF_OFF2,Input Buffer Offset2 Register" hexmask.long.word 0x1C 0.--9. 1. "INBUF_OFF2" line.long 0x20 "INBUF_OFF3,Input Buffer Offset3 Register" hexmask.long.word 0x20 0.--9. 1. "INBUF_OFF3" line.long 0x24 "THS_RATIO,THS RATIO Register" hexmask.long.word 0x24 0.--15. 1. "THS_RATIO" group.long 0x100++0x3 line.long 0x0 "CVM_EN,CVM Enable Register" bitfld.long 0x0 0. "CVM_EN,This bit is a value enable signal." "0,1" rgroup.long 0x108++0x7 line.long 0x0 "CVM_CTRL_BK,CVM Control Readback Register" bitfld.long 0x0 12. "THEN_BK,This bit can monitor the readback value of THEN in THCTR register." "0,1" newline bitfld.long 0x0 8. "OUTPC_BK,This bit can monitor the readback value of OUTPC in CVM_CTRL register." "0,1" newline bitfld.long 0x0 4. "EXTERNAL_FS_BK,This bit can monitor the readback value of EXTERNAL_FS in CVM_CTRL register." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CHOICE_PLACE_BK,These bits can monitor the readback value of CHOICE_PLACE [3:0] in CVM_CTRL register." line.long 0x4 "CVM_DETECT_MON,CVM Detection Voltage Setting Monitor Register" bitfld.long 0x4 24.--26. "MODE_MAX_MON,These bits can monitor the applicable trimming bits for maximum voltage side." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--19. 1. "TRIM_MAX_MON,These bits can monitor the applicable trimming bits for maximum voltage side." newline bitfld.long 0x4 8.--10. "MODE_MIN_MON,These bits can monitor the applicable trimming bits for minimum voltage side." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "TRIM_MIN_MON,These bits can monitor the applicable trimming bits for minimum voltage side." group.long 0x110++0x3 line.long 0x0 "CVM_DETECT_MANUAL_SET,CVM Detection Voltage Manual Setting Register" bitfld.long 0x0 28. "CVM_DETECT_SEL_MAX,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register." "0: The values of bits 26 to 24 and bits 19 to 16 in..,1: The values of bits 26 to 24 and bits 19 to 16 in.." newline bitfld.long 0x0 24.--26. "MODE_MAX,When bit 1 in CVM_CTRL register is 1’b1 these bits are enabled." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "TRIM_MAX,When bit 1 in CVM_CTRL register is 1’b1 these bits are enabled." newline bitfld.long 0x0 12. "CVM_DETECT_SEL_MIN,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register." "0: The values of bits 10 to 8 and bits 3 to 0 in..,1: The values of bits 10 to 8 and bits 3 to 0 in.." newline bitfld.long 0x0 8.--10. "MODE_MIN,When bit 0 in CVM_CTRL register is 1’b1 these bits are enabled." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "TRIM_MIN,When bit 0 in CVM_CTRL register is 1’b1 these bits are enabled." rgroup.long 0x114++0x7 line.long 0x0 "CVM_DETECT_SET_BK,CVM Detection Voltage Setting Readback Register" bitfld.long 0x0 24.--26. "MODE_MAX_BK,These bits can monitor the readback value of MODE_MAX[2:0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "TRIM_MAX_BK,These bits can monitor the readback value of TRIM_MAX[3:0]." newline bitfld.long 0x0 8.--10. "MODE_MIN_BK,These bits can monitor the readback value of MODE_MIN[2:0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "TRIM_MIN_BK,These bits can monitor the readback value of TRIM_MIN[3:0]." line.long 0x4 "CVM_TOFF_MON,CVM Temp Offset Monitor Register" hexmask.long.byte 0x4 0.--3. 1. "TOFF_MON,These bits can monitor trimming values." group.long 0x11C++0x3 line.long 0x0 "CVM_TOFF_MANUAL_SET,CVM Temp Offset Manual Setting Register" bitfld.long 0x0 12. "TOFF_SEL,This bit selects either CVM_TOFF_MON register or CVM_TOFF_MANUAL_SET register." "0: Select value that bit 3 to 0 in CVM_TOFF_MON..,1: Select value that bit 3 to 0 in.." newline hexmask.long.byte 0x0 0.--3. 1. "TOFF,When bit 4 in CVM_CTRL register is 1’b1 these bits are enabled." rgroup.long 0x120++0x3 line.long 0x0 "CVM_TOFF_BK,CVM Temp Offset Readback Register" hexmask.long.byte 0x0 0.--3. 1. "TOFF_BK,These bits can monitor the readback value of TOFF[3:0]." rgroup.long 0x128++0xF line.long 0x0 "STATMON1,State Monitor1 Register" hexmask.long.byte 0x0 24.--31. 1. "NML_STAT,Normal sequence state monitor" newline hexmask.long.byte 0x0 16.--23. 1. "PON_STAT,Power on sequence state monitor" newline hexmask.long.byte 0x0 8.--15. 1. "TST_STAT,Test sequence state monitor" newline hexmask.long.byte 0x0 0.--7. 1. "CTRL_STAT,Sequence control state monitor" line.long 0x4 "STATMON2,State Monitor2 Register" hexmask.long.byte 0x4 8.--15. 1. "MANTST_STAT,Manual test sequence state monitor" newline hexmask.long.byte 0x4 0.--7. 1. "CIVMTST_STAT,CIVM test sequence state monitor" line.long 0x8 "TSC_ERROR_MON,TSC Error Monitor Register" bitfld.long 0x8 7. "ERR_ACKTOV,THACK timeout error status" "0: no error,1: THACK timeout error" newline bitfld.long 0x8 6. "ERR_TST4,THCODE connection check(Test4) error status" "0: no error,1: THCODE connection check" newline bitfld.long 0x8 5. "ERR_TST5,THCODE connection check(Test5) error status" "0: no error,1: THCODE connection check" newline bitfld.long 0x8 4. "ERR_THCODE,THCODE error status" "0: no error,1: THCODE error" newline bitfld.long 0x8 3. "ERR_THCNTOV,THCNTOV error status" "0: no error,1: THCNTOV error" newline bitfld.long 0x8 2. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1" newline bitfld.long 0x8 1. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0" newline bitfld.long 0x8 0. "TSC_ERROR,TSC error status" "0: no error,1: TSC error" line.long 0xC "THCODE_MON,THCODE Monitor Register" bitfld.long 0xC 30. "TST4_THCNTOV,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test4)." "0,1" newline hexmask.long.word 0xC 16.--29. 1. "TST4_THCODE,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test4)." newline bitfld.long 0xC 14. "TST5_THCNTOV,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test5)." "0,1" newline hexmask.long.word 0xC 0.--13. 1. "TST5_THCODE,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test5)." group.long 0x138++0x3 line.long 0x0 "MANTST_SET_DT,Manual Test Mode Data Register" bitfld.long 0x0 28. "MANTST_REG,Manual test mode" "0: Normal mode,1: Manual test mode" newline bitfld.long 0x0 24. "MAN_THCHOP,Select the Manual THCHOP mode" "0: THCHOP=0 on Manual test mode,1: THCHOP=1 on Manual test mode" newline bitfld.long 0x0 12.--13. "MAN_THCNTSEL,Select the bit number of A/D converter for manual test" "0: 12bits,1: 10bits,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "MAN_THMODE,Select THMODE for manual test." newline bitfld.long 0x0 4.--6. "MAN_THVMSEL_A,Select chip internal voltage monitor input for manual test" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "MAN_THVMSEL_B,Select chip internal voltage monitor input for manual test" rgroup.long 0x13C++0x7 line.long 0x0 "TMR_DT,Timer Data Register" hexmask.long.tbyte 0x0 12.--29. 1. "ACKTMR,THACK timer monitor" newline hexmask.long.word 0x0 0.--9. 1. "GPTMR,General purpose timer monitor" line.long 0x4 "SEQ_ACT_MON,Sequence Act Signal Monitor Register" bitfld.long 0x4 17. "TSTSEQ_DONE,This bit indicates that the THCODE Connection Test Sequence has completed" "0: Not completed,1: Completed" newline bitfld.long 0x4 16. "STBYSEQ_DONE,This bit indicates that the THS Standby Setting Sequence has completed" "0: Not completed,1: Completed" newline hexmask.long.byte 0x4 0.--4. 1. "SEQ_ACT,Sequence Act Flag monitor" rgroup.long 0x14C++0x27 line.long 0x0 "VM_MON,CVM Monitor Register" bitfld.long 0x0 0.--1. "VM_08_S,These bits can monitor CVM status" "0: Under Voltage,1: Normal,?,?" line.long 0x4 "VM06CODE1,VM06CODE Parameter1 Register" hexmask.long.word 0x4 16.--25. 1. "VM06CODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x4 0.--9. 1. "VM06CODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x8 "VM06CODE2,VM06CODE Parameter2 Register" hexmask.long.word 0x8 16.--25. 1. "VM06CODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x8 0.--9. 1. "VM06CODE2_L,Parameter to be used in adjusting the characteristics" line.long 0xC "VM06CODE3,VM06CODE Parameter3 Register" hexmask.long.word 0xC 16.--25. 1. "VM06CODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0xC 0.--9. 1. "VM06CODE3_L,Parameter to be used in adjusting the characteristics" line.long 0x10 "VM11CODE1,VM11CODE Parameter1 Register" hexmask.long.word 0x10 16.--25. 1. "VM11CODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x10 0.--9. 1. "VM11CODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x14 "VM11CODE2,VM11CODE Parameter2 Register" hexmask.long.word 0x14 16.--25. 1. "VM11CODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x14 0.--9. 1. "VM11CODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x18 "VM11CODE3,VM11CODE Parameter3 Register" hexmask.long.word 0x18 16.--25. 1. "VM11CODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x18 0.--9. 1. "VM11CODE3_L,Parameter to be used in adjusting the characteristics" line.long 0x1C "VMCVMCODE1,VCC VMCODE Parameter1 Register" hexmask.long.word 0x1C 16.--25. 1. "VCCVMCODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x1C 0.--9. 1. "VCCVMCODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x20 "VMCVMCODE2,VCC VMCODE Parameter2 Register" hexmask.long.word 0x20 16.--25. 1. "VCCVMCODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x20 0.--9. 1. "VCCVMCODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x24 "VMCVMCODE3,VCC VMCODE Parameter3 Register" hexmask.long.word 0x24 16.--25. 1. "VCCVMCODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x24 0.--9. 1. "VCCVMCODE3_L,Parameter to be used in adjusting the characteristics" tree.end tree "TSC_4" base ad:0xE61B0000 rgroup.long 0x0++0x3 line.long 0x0 "THSIRQSTR,THS Temperature Error Status Register" bitfld.long 0x0 2. "IRQ3,Temperature Error3 Status" "0: Not detected,1: Temperature Error3 for thermal sensor is detected" newline bitfld.long 0x0 1. "IRQ2,Temperature Error2 Status" "0: Not detected,1: Temperature Error2 for thermal sensor is detected" newline bitfld.long 0x0 0. "IRQ1,Temperature Error1 Status" "0: Not detected,1: Temperature Error1 for thermal sensor is detected" group.long 0x4++0x1F line.long 0x0 "IRQSTR,Temperature Error Status Register" bitfld.long 0x0 5. "TEMPD3_STR,TEMPD3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 4. "TEMPD2_STR,TEMPD2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 3. "TEMPD1_STR,TEMPD1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it falls below.." newline bitfld.long 0x0 2. "TEMP3_STR,TEMP3 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." newline bitfld.long 0x0 1. "TEMP2_STR,TEMP2 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." newline bitfld.long 0x0 0. "TEMP1_STR,TEMP1 Detection Status" "0: Not detected,1: TEMP_CODE [11:0] bits detect that it exceeds the.." line.long 0x4 "IRQMSK,Temperature Error Mask Register" bitfld.long 0x4 5. "TEMPD3_MSK,This bit selects masking or non-masking of TEMPD3 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 4. "TEMPD2_MSK,This bit selects masking or non-masking of TEMPD2 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 3. "TEMPD1_MSK,This bit selects masking or non-masking of TEMPD1 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 2. "TEMP3_MSK,This bit selects masking or non-masking of TEMP3 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 1. "TEMP2_MSK,This bit selects masking or non-masking of TEMP2 error requests." "0: Errors are masked,1: The mask is cleared" newline bitfld.long 0x4 0. "TEMP1_MSK,This bit selects masking or non-masking of TEMP1 error requests." "0: Errors are masked,1: The mask is cleared" line.long 0x8 "IRQCTL,Threshold Edge/Level Register" bitfld.long 0x8 5. "TEMPD3_EL,Specifies the method for detection of the TEMPD3 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 4. "TEMPD2_EL,Specifies the method for detection of the TEMPD2 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 3. "TEMPD1_EL,Specifies the method for detection of the TEMPD1 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 2. "TEMP3_EL,Specifies the method for detection of the TEMP3 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 1. "TEMP2_EL,Specifies the method for detection of the TEMP2 error signal input." "0: Edge detection,1: Level detection" newline bitfld.long 0x8 0. "TEMP1_EL,Specifies the method for detection of the TEMP1 error signal input." "0: Edge detection,1: Level detection" line.long 0xC "IRQEN,Temperature Error Enable Register" bitfld.long 0xC 5. "TEMPD3_EN,This bit enables or disables TEMPD3 errors." "0: TEMPD3 errors are disabled,1: TEMPD3 errors are enabled" newline bitfld.long 0xC 4. "TEMPD2_EN,This bit enables or disables TEMPD2 errors." "0: TEMPD2 errors are disabled,1: TEMPD2 errors are enabled" newline bitfld.long 0xC 3. "TEMPD1_EN,This bit enables or disables TEMPD1 errors." "0: TEMPD1 errors are disabled,1: TEMPD1 errors are enabled" newline bitfld.long 0xC 2. "TEMP3_EN,This bit enables or disables TEMP3 errors." "0: TEMP3 errors are disabled,1: TEMP3 errors are enabled" newline bitfld.long 0xC 1. "TEMP2_EN,This bit enables or disables TEMP2 errors." "0: TEMP2 errors are disabled,1: TEMP2 errors are enabled" newline bitfld.long 0xC 0. "TEMP1_EN,This bit enables or disables TEMP1 errors." "0: TEMP1 errors are disabled,1: TEMP1 errors are enabled" line.long 0x10 "IRQTEMP1,Temperature Error 1 Register" bitfld.long 0x10 12.--13. "IRQTEMP1,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors." "0,1,2,3" newline hexmask.long.word 0x10 0.--11. 1. "IRQTEMP1,These bits set the first threshold value of the temperature for TEMP1 and TEMPD1 errors." line.long 0x14 "IRQTEMP2,Temperature Error 2 Register" bitfld.long 0x14 12.--13. "IRQTEMP2,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors." "0,1,2,3" newline hexmask.long.word 0x14 0.--11. 1. "IRQTEMP2,These bits set the second threshold value of the temperature for TEMP2 and TEMPD2 errors." line.long 0x18 "IRQTEMP3,Temperature Error 3 Register" bitfld.long 0x18 12.--13. "IRQTEMP3,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors." "0,1,2,3" newline hexmask.long.word 0x18 0.--11. 1. "IRQTEMP3,These bits set the third threshold value of the temperature for TEMP3 and TEMPD3 errors." line.long 0x1C "THCTR,Control Register" bitfld.long 0x1C 28.--30. "VOLSELB,Select the chip internal voltage monitor input" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline bitfld.long 0x1C 24. "CTCTL,Select write condition of THREFTAP THCNTSEN and VMCNTSEN" "0: Inhibit write of these bits,1: Allow write of these bits" newline bitfld.long 0x1C 20. "CIVMTST,THS/CIVM failure check mode" "0: Normal mode,1: THS/CIVM failure check mode" newline bitfld.long 0x1C 18.--19. "VMCNTSEN,Select the bit number of A/D converter in CIVM" "0: 10bits,1: 12bits,?,?" newline bitfld.long 0x1C 16.--17. "THCNTSEN,Select the bit number of A/D converter in THS" "0: 12bits,1: 10bits,?,?" newline bitfld.long 0x1C 12.--14. "VOLSELA,Select the chip internal voltage monitor input" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline bitfld.long 0x1C 8.--9. "SENSSEL,Select the use sensor" "0: THS,1: THS ON only,?,?" newline bitfld.long 0x1C 6. "PONM,Select mode signal" "0: Normal mode,1: Power-on mode" newline bitfld.long 0x1C 5. "THEN,Enabling/disabling of thermal sensor" "0: Enabled,1: Disabled" newline bitfld.long 0x1C 0. "THSST,Enabling/disabling of the A/D converter for the thermal sensor" "0: Disabled,1: Enabled" rgroup.long 0x24++0x43 line.long 0x0 "THSTR,Status Register" bitfld.long 0x0 3. "THACKMON,THACK signal monitor" "0: Not detected,1: THCODE was generated" newline bitfld.long 0x0 2. "THCNTOV_MON,THCNTOV signal monitor" "0: Not detected,1: Detected overflow" newline bitfld.long 0x0 1. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1" newline bitfld.long 0x0 0. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0" line.long 0x4 "TEMP_YN,Temperature1 Register ( Y(n) )" bitfld.long 0x4 12.--13. "TEMP_CODE_YN,These bits indicate the digital value for the temperature detected by the thermal sensor." "0,1,2,3" newline hexmask.long.word 0x4 0.--11. 1. "TEMP_CODE_YN,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x8 "VOLT,Voltage Register" hexmask.long.byte 0x8 10.--13. 1. "VOLT_CODE,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." newline hexmask.long.word 0x8 0.--9. 1. "VOLT_CODE,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." line.long 0xC "TEMP_X,Temperature1 Register ( X(n) )" hexmask.long.word 0xC 0.--13. 1. "TEMP_X,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x10 "TEMP_YN1,Temperature2 Register ( Y(n-1) )" hexmask.long.word 0x10 0.--13. 1. "TEMP_YN1,These bits indicate the digital value for the temperature detected by the thermal sensor." line.long 0x14 "TEMP_X1,Temperature3 Register ( X(n-1) )" hexmask.long.word 0x14 0.--13. 1. "TEMP_X1,These bits indicate the digital value for the one before temperature detected by the thermal sensor." line.long 0x18 "THINITSTR,Power ON Initial Temperature Status Register" bitfld.long 0x18 3. "NRMEND,Completion flag of capturing the temperatures in the power-on mode" "0: Not complete,1: Complete" newline bitfld.long 0x18 2. "THTMP3,Detection of capturing the third temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" newline bitfld.long 0x18 1. "THTMP2,Detection of capturing the second temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" newline bitfld.long 0x18 0. "THTMP1,Detection of capturing the first temperature to be used for correcting the characteristics of the thermal sensor in the power-on mode" "0: The temperature has not been captured,1: The temperature has been captured" line.long 0x1C "THCODE_INT1,Power ON Initial 1 Temperature Register" hexmask.long.word 0x1C 0.--11. 1. "THCODE_INT1,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x20 "THCODE_INT2,Power ON Initial 2 Temperature Register" hexmask.long.word 0x20 0.--11. 1. "THCODE_INT2,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x24 "THCODE_INT3,Power ON Initial 3 Temperature Register" hexmask.long.word 0x24 0.--11. 1. "THCODE_INT3,These bits indicate the temperature which was captured when the chip was starting up and is to be used in adjusting the characteristics." line.long 0x28 "CVCREG,Convert Correction Register" hexmask.long.word 0x28 0.--11. 1. "CCREG,Parameter to be used in adjusting the characteristics" line.long 0x2C "THCODE1,THCODE Parameter1 Register" hexmask.long.word 0x2C 0.--11. 1. "THCODE1,Parameter to be used in adjusting the characteristics" line.long 0x30 "THCODE2,THCODE Parameter2 Register" hexmask.long.word 0x30 0.--11. 1. "THCODE2,Parameter to be used in adjusting the characteristics" line.long 0x34 "THCODE3,THCODE Parameter3 Register" hexmask.long.word 0x34 0.--11. 1. "THCODE3,Parameter to be used in adjusting the characteristics" line.long 0x38 "PTAT1,PTAT Parameter1 Register" hexmask.long.word 0x38 16.--27. 1. "PTAT1_0,Parameter to be used in adjusting the characteristics." newline hexmask.long.word 0x38 0.--11. 1. "PTAT1,Parameter to be used in adjusting the characteristics" line.long 0x3C "PTAT2,PTAT Parameter2 Register" hexmask.long.word 0x3C 0.--11. 1. "PTAT2,Parameter to be used in adjusting the characteristics" line.long 0x40 "PTAT3,PTAT Parameter3 Register" hexmask.long.word 0x40 16.--27. 1. "PTAT3_0,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x40 0.--11. 1. "PTAT3,Parameter to be used in adjusting the characteristics" group.long 0x6C++0x13 line.long 0x0 "IRQ_INJECTION,Error Injection Register" bitfld.long 0x0 5. "TEMPD3_INJ,TEMPD3 Error Injection" "0: IRQTEMP3 Error Injection Disable,1: IRQTEMP3 Error Injection Enable" newline bitfld.long 0x0 4. "TEMPD2_INJ,TEMPD2 Error Injection" "0: IRQTEMP2 Error Injection Disable,1: IRQTEMP2 Error Injection Enable" newline bitfld.long 0x0 3. "TEMPD1_INJ,TEMPD1 Error Injection" "0: IRQTEMP1 Error Injection Disable,1: IRQTEMP1 Error Injection Enable" newline bitfld.long 0x0 2. "TEMP3_INJ,TEMP3 Error Injection" "0: IRQTEMP3 Error Injection Disable,1: IRQTEMP3 Error Injection Enable" newline bitfld.long 0x0 1. "TEMP2_INJ,TEMP2 Error Injection" "0: IRQTEMP2 Error Injection Disable,1: IRQTEMP2 Error Injection Enable" newline bitfld.long 0x0 0. "TEMP1_INJ,TEMP1 Error Injection" "0: IRQTEMP1 Error Injection Disable,1: IRQTEMP1 Error Injection Enable" line.long 0x4 "ACK_TIMEOUT,Ack Timeout Register" hexmask.long.word 0x4 0.--13. 1. "ACK_TIMEOUT_REG,THACK timeout setting" line.long 0x8 "TSC_ERROR_CTL,TSC Error Control Register" bitfld.long 0x8 0. "TSC_ERR_CTL,TSC error injection" "0: Error injection off,1: Error injection on" line.long 0xC "THSOUTCTL,THS Output Control Register" bitfld.long 0xC 28. "THACKMASK,THACK mask enable" "0: Disable THACK mask,1: Enable THACK mask" newline bitfld.long 0xC 24. "THCNTOVCTL,THCNTOV select" "0: THCNTOV from THS,1: THCNTOV_TESTDT" newline bitfld.long 0xC 20. "THCODECTL,THCODE select" "0: THCODE from THS,1: THCODE_TESTDT" newline bitfld.long 0xC 16. "THCNTOV_TESTDT,THCNTOV test data setting" "0,1" newline hexmask.long.word 0xC 0.--13. 1. "THCODE_TESTDT,THCODE test data setting" line.long 0x10 "SEQ_RESET,Sequence Reset Register" bitfld.long 0x10 0. "SEQ_RESET,This bit initializes the sequence and error value." "0,1" rgroup.long 0x80++0x1F line.long 0x0 "PON_TEMP,Power On Temperature Register" hexmask.long.word 0x0 0.--13. 1. "PON_TEMP_CODE_YN,These bits indicate the digital value detected by the temperature sensor during Power On mode." line.long 0x4 "NML_TEMP,Normal Temperature Register" hexmask.long.word 0x4 0.--13. 1. "NML_TEMP_CODE_YN,These bits indicate the digital value detected by the temperature sensor during Normal mode." line.long 0x8 "NML_VOLT,Normal Voltage Register" hexmask.long.word 0x8 0.--13. 1. "NML_VOLT_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during Normal mode." line.long 0xC "CIVMTST_VOLT1,CIVM Test Voltage1 Register" hexmask.long.word 0xC 0.--13. 1. "CIVMTST_VOLT1_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode1." line.long 0x10 "CIVMTST_VOLT2,CIVM Test Voltage2 Register" hexmask.long.word 0x10 0.--13. 1. "CIVMTST_VOLT2_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode2." line.long 0x14 "CIVMTST_VOLT3,CIVM Test Voltage3 Register" hexmask.long.word 0x14 0.--13. 1. "CIVMTST_VOLT3_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode3." line.long 0x18 "CIVMTST_VOLT4,CIVM Test Voltage4 Register" hexmask.long.word 0x18 0.--13. 1. "CIVMTST_VOLT4_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during CIVM test mode4." line.long 0x1C "MANTST_VOLT,Manual Test Voltage Register" hexmask.long.word 0x1C 0.--13. 1. "MANTST_VOLT_CODE_YN,These bits indicate the digital value detected by the chip internal voltage monitor during Manual test mode." rgroup.long 0xA8++0x3 line.long 0x0 "VOLT_YN,Voltage Register ( Y(n) )" hexmask.long.word 0x0 0.--11. 1. "VOLT_CODE_YN,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." rgroup.long 0xB0++0x3 line.long 0x0 "VOLT_X,Voltage 1 Register ( X(n) )" hexmask.long.word 0x0 0.--13. 1. "VOLT_CODE_X,These bits indicate the digital value for the voltage detected by the chip internal voltage monitor." rgroup.long 0xB8++0x3 line.long 0x0 "VOLT_X1,Voltage 2 Register ( X(n-1) )" hexmask.long.word 0x0 0.--13. 1. "VOLT_CODE_X1,These bits indicate the digital value for the one before voltage detected by the chip internal voltage monitor." rgroup.long 0xD0++0x27 line.long 0x0 "VMCODE1,VMCODE Parameter1 Register" hexmask.long.word 0x0 16.--25. 1. "VMCODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x0 0.--9. 1. "VMCODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x4 "VMCODE2,VMCODE Parameter2 Register" hexmask.long.word 0x4 16.--25. 1. "VMCODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x4 0.--9. 1. "VMCODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x8 "VMCODE3,VMCODE Parameter3 Register" hexmask.long.word 0x8 16.--25. 1. "VMCODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x8 0.--9. 1. "VMCODE3_L,Parameter to be used in adjusting the characteristics" line.long 0xC "HVMCODE1,High VMCODE Parameter1 Register" hexmask.long.word 0xC 16.--25. 1. "VC18CODE1,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0xC 0.--9. 1. "VM11CODE1,Parameter to be used in adjusting the characteristics" line.long 0x10 "HVMCODE2,High VMCODE Parameter2 Register" hexmask.long.word 0x10 16.--25. 1. "VC18CODE2,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x10 0.--9. 1. "VM11CODE2,Parameter to be used in adjusting the characteristics" line.long 0x14 "HVMCODE3,High VMCODE Parameter3 Register" hexmask.long.word 0x14 16.--25. 1. "VC18CODE3,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x14 0.--9. 1. "VM11CODE3,Parameter to be used in adjusting the characteristics" line.long 0x18 "INBUF_OFF1,Input Buffer Offset1 Register" hexmask.long.word 0x18 0.--9. 1. "INBUF_OFF1" line.long 0x1C "INBUF_OFF2,Input Buffer Offset2 Register" hexmask.long.word 0x1C 0.--9. 1. "INBUF_OFF2" line.long 0x20 "INBUF_OFF3,Input Buffer Offset3 Register" hexmask.long.word 0x20 0.--9. 1. "INBUF_OFF3" line.long 0x24 "THS_RATIO,THS RATIO Register" hexmask.long.word 0x24 0.--15. 1. "THS_RATIO" group.long 0x100++0x3 line.long 0x0 "CVM_EN,CVM Enable Register" bitfld.long 0x0 0. "CVM_EN,This bit is a value enable signal." "0,1" rgroup.long 0x108++0x7 line.long 0x0 "CVM_CTRL_BK,CVM Control Readback Register" bitfld.long 0x0 12. "THEN_BK,This bit can monitor the readback value of THEN in THCTR register." "0,1" newline bitfld.long 0x0 8. "OUTPC_BK,This bit can monitor the readback value of OUTPC in CVM_CTRL register." "0,1" newline bitfld.long 0x0 4. "EXTERNAL_FS_BK,This bit can monitor the readback value of EXTERNAL_FS in CVM_CTRL register." "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CHOICE_PLACE_BK,These bits can monitor the readback value of CHOICE_PLACE [3:0] in CVM_CTRL register." line.long 0x4 "CVM_DETECT_MON,CVM Detection Voltage Setting Monitor Register" bitfld.long 0x4 24.--26. "MODE_MAX_MON,These bits can monitor the applicable trimming bits for maximum voltage side." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--19. 1. "TRIM_MAX_MON,These bits can monitor the applicable trimming bits for maximum voltage side." newline bitfld.long 0x4 8.--10. "MODE_MIN_MON,These bits can monitor the applicable trimming bits for minimum voltage side." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--3. 1. "TRIM_MIN_MON,These bits can monitor the applicable trimming bits for minimum voltage side." group.long 0x110++0x3 line.long 0x0 "CVM_DETECT_MANUAL_SET,CVM Detection Voltage Manual Setting Register" bitfld.long 0x0 28. "CVM_DETECT_SEL_MAX,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register." "0: The values of bits 26 to 24 and bits 19 to 16 in..,1: The values of bits 26 to 24 and bits 19 to 16 in.." newline bitfld.long 0x0 24.--26. "MODE_MAX,When bit 1 in CVM_CTRL register is 1’b1 these bits are enabled." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "TRIM_MAX,When bit 1 in CVM_CTRL register is 1’b1 these bits are enabled." newline bitfld.long 0x0 12. "CVM_DETECT_SEL_MIN,This bit selects either CVM_DETECT_MON register or CVM_MANUAL_SET register." "0: The values of bits 10 to 8 and bits 3 to 0 in..,1: The values of bits 10 to 8 and bits 3 to 0 in.." newline bitfld.long 0x0 8.--10. "MODE_MIN,When bit 0 in CVM_CTRL register is 1’b1 these bits are enabled." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "TRIM_MIN,When bit 0 in CVM_CTRL register is 1’b1 these bits are enabled." rgroup.long 0x114++0x7 line.long 0x0 "CVM_DETECT_SET_BK,CVM Detection Voltage Setting Readback Register" bitfld.long 0x0 24.--26. "MODE_MAX_BK,These bits can monitor the readback value of MODE_MAX[2:0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--19. 1. "TRIM_MAX_BK,These bits can monitor the readback value of TRIM_MAX[3:0]." newline bitfld.long 0x0 8.--10. "MODE_MIN_BK,These bits can monitor the readback value of MODE_MIN[2:0]." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "TRIM_MIN_BK,These bits can monitor the readback value of TRIM_MIN[3:0]." line.long 0x4 "CVM_TOFF_MON,CVM Temp Offset Monitor Register" hexmask.long.byte 0x4 0.--3. 1. "TOFF_MON,These bits can monitor trimming values." group.long 0x11C++0x3 line.long 0x0 "CVM_TOFF_MANUAL_SET,CVM Temp Offset Manual Setting Register" bitfld.long 0x0 12. "TOFF_SEL,This bit selects either CVM_TOFF_MON register or CVM_TOFF_MANUAL_SET register." "0: Select value that bit 3 to 0 in CVM_TOFF_MON..,1: Select value that bit 3 to 0 in.." newline hexmask.long.byte 0x0 0.--3. 1. "TOFF,When bit 4 in CVM_CTRL register is 1’b1 these bits are enabled." rgroup.long 0x120++0x3 line.long 0x0 "CVM_TOFF_BK,CVM Temp Offset Readback Register" hexmask.long.byte 0x0 0.--3. 1. "TOFF_BK,These bits can monitor the readback value of TOFF[3:0]." rgroup.long 0x128++0xF line.long 0x0 "STATMON1,State Monitor1 Register" hexmask.long.byte 0x0 24.--31. 1. "NML_STAT,Normal sequence state monitor" newline hexmask.long.byte 0x0 16.--23. 1. "PON_STAT,Power on sequence state monitor" newline hexmask.long.byte 0x0 8.--15. 1. "TST_STAT,Test sequence state monitor" newline hexmask.long.byte 0x0 0.--7. 1. "CTRL_STAT,Sequence control state monitor" line.long 0x4 "STATMON2,State Monitor2 Register" hexmask.long.byte 0x4 8.--15. 1. "MANTST_STAT,Manual test sequence state monitor" newline hexmask.long.byte 0x4 0.--7. 1. "CIVMTST_STAT,CIVM test sequence state monitor" line.long 0x8 "TSC_ERROR_MON,TSC Error Monitor Register" bitfld.long 0x8 7. "ERR_ACKTOV,THACK timeout error status" "0: no error,1: THACK timeout error" newline bitfld.long 0x8 6. "ERR_TST4,THCODE connection check(Test4) error status" "0: no error,1: THCODE connection check" newline bitfld.long 0x8 5. "ERR_TST5,THCODE connection check(Test5) error status" "0: no error,1: THCODE connection check" newline bitfld.long 0x8 4. "ERR_THCODE,THCODE error status" "0: no error,1: THCODE error" newline bitfld.long 0x8 3. "ERR_THCNTOV,THCNTOV error status" "0: no error,1: THCNTOV error" newline bitfld.long 0x8 2. "THFAIL1,This bit is set to 1 when all of the THCODE bits are 1" "0: Normal operation,1: All of the THCODE bits are all 1" newline bitfld.long 0x8 1. "THFAIL0,This bit is set to 1 when all of the THCODE bits are 0" "0: Normal operation,1: All of the THCODE bits are all 0" newline bitfld.long 0x8 0. "TSC_ERROR,TSC error status" "0: no error,1: TSC error" line.long 0xC "THCODE_MON,THCODE Monitor Register" bitfld.long 0xC 30. "TST4_THCNTOV,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test4)." "0,1" newline hexmask.long.word 0xC 16.--29. 1. "TST4_THCODE,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test4)." newline bitfld.long 0xC 14. "TST5_THCNTOV,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test5)." "0,1" newline hexmask.long.word 0xC 0.--13. 1. "TST5_THCODE,These bits indicate the digital value detected by the thermal sensor monitor during THCODE connection check(Test5)." group.long 0x138++0x3 line.long 0x0 "MANTST_SET_DT,Manual Test Mode Data Register" bitfld.long 0x0 28. "MANTST_REG,Manual test mode" "0: Normal mode,1: Manual test mode" newline bitfld.long 0x0 24. "MAN_THCHOP,Select the Manual THCHOP mode" "0: THCHOP=0 on Manual test mode,1: THCHOP=1 on Manual test mode" newline bitfld.long 0x0 12.--13. "MAN_THCNTSEL,Select the bit number of A/D converter for manual test" "0: 12bits,1: 10bits,?,?" newline hexmask.long.byte 0x0 8.--11. 1. "MAN_THMODE,Select THMODE for manual test." newline bitfld.long 0x0 4.--6. "MAN_THVMSEL_A,Select chip internal voltage monitor input for manual test" "0: VDD_DVFS0,1: VTHS1REF0,?,?,?,?,?,?" newline hexmask.long.byte 0x0 0.--3. 1. "MAN_THVMSEL_B,Select chip internal voltage monitor input for manual test" rgroup.long 0x13C++0x7 line.long 0x0 "TMR_DT,Timer Data Register" hexmask.long.tbyte 0x0 12.--29. 1. "ACKTMR,THACK timer monitor" newline hexmask.long.word 0x0 0.--9. 1. "GPTMR,General purpose timer monitor" line.long 0x4 "SEQ_ACT_MON,Sequence Act Signal Monitor Register" bitfld.long 0x4 17. "TSTSEQ_DONE,This bit indicates that the THCODE Connection Test Sequence has completed" "0: Not completed,1: Completed" newline bitfld.long 0x4 16. "STBYSEQ_DONE,This bit indicates that the THS Standby Setting Sequence has completed" "0: Not completed,1: Completed" newline hexmask.long.byte 0x4 0.--4. 1. "SEQ_ACT,Sequence Act Flag monitor" rgroup.long 0x14C++0x27 line.long 0x0 "VM_MON,CVM Monitor Register" bitfld.long 0x0 0.--1. "VM_08_S,These bits can monitor CVM status" "0: Under Voltage,1: Normal,?,?" line.long 0x4 "VM06CODE1,VM06CODE Parameter1 Register" hexmask.long.word 0x4 16.--25. 1. "VM06CODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x4 0.--9. 1. "VM06CODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x8 "VM06CODE2,VM06CODE Parameter2 Register" hexmask.long.word 0x8 16.--25. 1. "VM06CODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x8 0.--9. 1. "VM06CODE2_L,Parameter to be used in adjusting the characteristics" line.long 0xC "VM06CODE3,VM06CODE Parameter3 Register" hexmask.long.word 0xC 16.--25. 1. "VM06CODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0xC 0.--9. 1. "VM06CODE3_L,Parameter to be used in adjusting the characteristics" line.long 0x10 "VM11CODE1,VM11CODE Parameter1 Register" hexmask.long.word 0x10 16.--25. 1. "VM11CODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x10 0.--9. 1. "VM11CODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x14 "VM11CODE2,VM11CODE Parameter2 Register" hexmask.long.word 0x14 16.--25. 1. "VM11CODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x14 0.--9. 1. "VM11CODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x18 "VM11CODE3,VM11CODE Parameter3 Register" hexmask.long.word 0x18 16.--25. 1. "VM11CODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x18 0.--9. 1. "VM11CODE3_L,Parameter to be used in adjusting the characteristics" line.long 0x1C "VMCVMCODE1,VCC VMCODE Parameter1 Register" hexmask.long.word 0x1C 16.--25. 1. "VCCVMCODE1_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x1C 0.--9. 1. "VCCVMCODE1_L,Parameter to be used in adjusting the characteristics" line.long 0x20 "VMCVMCODE2,VCC VMCODE Parameter2 Register" hexmask.long.word 0x20 16.--25. 1. "VCCVMCODE2_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x20 0.--9. 1. "VCCVMCODE2_L,Parameter to be used in adjusting the characteristics" line.long 0x24 "VMCVMCODE3,VCC VMCODE Parameter3 Register" hexmask.long.word 0x24 16.--25. 1. "VCCVMCODE3_H,Parameter to be used in adjusting the characteristics" newline hexmask.long.word 0x24 0.--9. 1. "VCCVMCODE3_L,Parameter to be used in adjusting the characteristics" tree.end tree.end tree "VCP" base ad:0xFE910000 group.long 0x180++0x7 line.long 0x0 "VLC_EDC_CTL,VP_VLC_EDC_CTL controls SRAM-EDC checking function and injecting dummy EDC error for testing." bitfld.long 0x0 24. "FEN,This bit forces the EDC error notification signal (errreq_vcp4l_vedc_p) to be asserted." "0: Does not assert EDC error notification signal..,1: Asserts EDC error notification signal forcibly" bitfld.long 0x0 0. "DIS,This bit specifies the disable flag of EDC checking function." "0: Enables SRAM-EDC checking function,1: Disables SRAM-EDC checking function" line.long 0x4 "VLC_EDC_STA,VP_VLC_EDC_CTL indicates the status of a SRAM-EDC error. If EDC error occurs. the error status flag is set to 1. VCPL4 issues the error notification signal to the external error controller if the VP_VLC_EDC_CTRL.DIS is 0 and the status bit is.." bitfld.long 0x4 0. "ESTA,This bit indicates SRAM-EDC error." "0: no error,1: error occurred" group.long 0x380++0x7 line.long 0x0 "CE_EDC_CTL,VP_VLC_EDC_CTL controls SRAM-EDC checking function and injecting dummy EDC error for testing." bitfld.long 0x0 24. "FEN,This bit forces the EDC error notification signal (errreq_vcp4l_cedc_p) to be asserted." "0: Does not assert EDC error notification signal..,1: Asserts EDC error notification signal forcibly" bitfld.long 0x0 0. "DIS,This bit specifies the disable flag of EDC checking function." "0: Enables SRAM-EDC checking function,1: Disables SRAM-EDC checking function" line.long 0x4 "CE_EDC_STA,VP_CE_EDC_CTL indicates the status of a SRAM-EDC error. If EDC error occurs. the error status flag is set to 1. VCPL4 issues the error notification signal to the external error controller if the VP_CE_EDC_CTRL.DIS is 0 and the status bit is 1." bitfld.long 0x4 0. "ESTA,This bit indicates SRAM-EDC error." "0: no error,1: error occurred" tree.end tree "WCRC" base ad:0x0 tree "WCRC_0" group.long 0x0++0x3 line.long 0x0 "WCRCm_CAIPn_EN,WCRCm_CAIPn_EN is a register that sets enable the data transfer to/from each port for CAIP_Lite_n interface in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CAIP_Lite_n,1: Enable transferring data to CAIP_Lite_n" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command port,1: Enable input to Data/Command port" group.long 0x10++0x3 line.long 0x0 "WCRCm_CAIPn_SIZE,WCRCm_CAIPn_SIZE is a register that sets transfer size of 1 block data for CAIP_Lite_n interface." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x20++0x3 line.long 0x0 "WCRCm_CAIPn_STOP,WCRCm_CAIPn_STOP is a register that stop transfer to CAIP_Lite_n interface." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x30++0x3 line.long 0x0 "WCRCm_CAIPn_CMDEN,WCRCm_CAIPn_CMDEN is a register that sets enable command function for CAIP_Lite_n module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" wgroup.long 0x80++0x3 line.long 0x0 "WCRCm_CAIPn_WAIT,WCRCm_CAIPn_WAIT is a register that wait subsequent command for CAIP_Lite_n interface." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x90++0x3 line.long 0x0 "WCRCm_CAIPn_RES_SIZE,WCRCm_CAIPn_RES_SIZE is a register that sets output size of result data at once for CAIP_Lite_n interface." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x200++0x3 line.long 0x0 "WCRCm_CAIPn_STS,WCRCm_CAIPn_STS is a register that indicates the state of operation related to CAIP_Lite_n module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CAIPn_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0x240++0x3 line.long 0x0 "WCRCm_CAIPn_INTEN,WCRCm_CAIPn_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_n module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CAIPn_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0x280++0x3 line.long 0x0 "WCRCm_CAIPn_ECMEN,WCRCm_CAIPn_ECMEN is a register that sets enable for error notification to ECM module on operation related to CAIP_Lite_n module." group.long 0x400++0x3 line.long 0x0 "WCRCm_CAIPp_EN,WCRCm_CAIPp_EN is a register that sets enable the data transfer to/from each ports for CAIP_Lite_p interface in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CAIP_Lite_p,1: Enable transferring data to CAIP_Lite_p" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command port,1: Enable input to Data/Command port" group.long 0x410++0x3 line.long 0x0 "WCRCm_CAIPp_SIZE,WCRCm_CAIPp_SIZE is a register that sets transfer size of 1 block data to CAIP_Lite_p interface." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x420++0x3 line.long 0x0 "WCRCm_CAIPp_STOP,WCRCm_CAIPp_STOP is a register that stop transfer to CAIP_Lite_p interface." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x430++0x3 line.long 0x0 "WCRCm_CAIPp_CMDEN,WCRCm_CAIPp_CMDEN is a register that sets enable command function for CAIP_Lite_p module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" wgroup.long 0x480++0x3 line.long 0x0 "WCRCm_CAIPp_WAIT,WCRCm_CAIPp_WAIT is a register that wait subsequent command for CAIP_Lite_p interface." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x490++0x3 line.long 0x0 "WCRCm_CAIPp_RES_SIZE,WCRCm_CAIPp_RES_SIZE is a register that sets output size of result data at once for CAIP_Lite_p interface." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x600++0x3 line.long 0x0 "WCRCm_CAIPp_STS,WCRCm_CAIPp_STS is a register that indicates the state of operation related to CAIP_Lite_p module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CAIPp_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0x640++0x3 line.long 0x0 "WCRCm_CAIPp_INTEN,WCRCm_CAIPp_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_p module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CAIPp_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0x680++0x3 line.long 0x0 "WCRCm_CAIPp_ECMEN,WCRCm_CAIPp_ECMEN is a register that sets enable for error notification to ECM module on operation related to CAIP_Lite_p module." group.long 0x800++0x3 line.long 0x0 "WCRCm_CRCm_EN,WCRCm_CRCm_EN is a register that sets enable the data transfer to/from each port for CRCm module in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CRCm,1: Enable transferring data to CRCm" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command/Expected data port,1: Enable input to Data/Command/Expected data port" group.long 0x810++0x3 line.long 0x0 "WCRCm_CRCm_SIZE,WCRCm_CRCm_SIZE is a register that sets transfer size of 1 packet to CRCm module." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x820++0x3 line.long 0x0 "WCRCm_CRCm_STOP,WCRCm_CRCm_STOP is a register that stop transfer to CRCm module." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x830++0x3 line.long 0x0 "WCRCm_CRCm_CMDEN,WCRCm_CRCm_CMDEN is a register that sets enable command function for CRCm module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" group.long 0x840++0x3 line.long 0x0 "WCRCm_CRCm_COMP,WCRCm_CRCm_COMP is a register that sets enable comparing CRC result from CRCm module with expected data in FIFO." bitfld.long 0x0 16.--17. "CMP_FREQ,Set the frequency of comparing.(コンペアの頻度を設定。)" "0,1,2,3" bitfld.long 0x0 1. "EXP_REQSEL,Select DMA Transfer request source for transferring expected data." "0: dmareq_wcrcm_crcm_in,1: dmareq_wcrcm_crcm_res" newline bitfld.long 0x0 0. "CMP_EN,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function" rgroup.long 0x850++0x3 line.long 0x0 "WCRCm_CRCm_COMP_RES,WCRCm_CRCm_COMP_RES is a register that indicates the result of comparing CRC for CRCm module." hexmask.long.word 0x0 0.--15. 1. "CMP_RES,The result of comparing CRC" group.long 0x860++0x3 line.long 0x0 "WCRCm_CRCm_FMT,WCRCm_CRCm_FMT is a register that set format of input data for CRCm module." bitfld.long 0x0 0.--1. "IN_FMT,Data format of E2E input data" "0,1,2,3" group.long 0x870++0x3 line.long 0x0 "WCRCm_CRCm_CONV,WCRCm_CRCm_CONV is a register that sets CRC conversion size to once for CRCm module." hexmask.long.tbyte 0x0 0.--20. 1. "CONV,CRC conversion size specification" wgroup.long 0x880++0x3 line.long 0x0 "WCRCm_CRCm_WAIT,WCRCm_CRCm_WAIT is a register that wait subsequent command for CRCm module." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x890++0x3 line.long 0x0 "WCRCm_CRCm_RES_SIZE,WCRCm_CRCm_RES_SIZE is a register that sets output size of result data at once for CRCm module." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x910++0x3 line.long 0x0 "WCRCm_CRCm_INIT_CRC,WCRCm_CRCm_INIT_CRC is a register that sets CRC code value to DCRAnCOUT register at auto clear." hexmask.long 0x0 0.--31. 1. "INIT_CODE,CRC code value to DCRAnCOUT register at auto clear." group.long 0xA00++0x3 line.long 0x0 "WCRCm_CRCm_STS,WCRCm_CRCm_STS is a register that indicates the state of operation related to CRCm module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CRCm_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 13. "COMP_ERR,Indicates the error of comparing CRC." "0: No comparing error or not comparing,1: Mismatch has occurred" newline bitfld.long 0x0 12. "COMP_DONE,Indicates the state of comparing CRC." "0: Comparison in progress or not comparing,1: Comparing is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0xA40++0x3 line.long 0x0 "WCRCm_CRCm_INTEN,WCRCm_CRCm_INTEN is a register that sets enable for the interrupt of operation related to CRCm module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CRCm_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 13. "COMP_ERR_IE,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 12. "COMP_DONE_IE,Interrupt for the complete of comparing CRC enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0xA80++0x3 line.long 0x0 "WCRCm_CRCm_ECMEN,WCRCm_CRCm_ECMEN is a register that sets enable for error notification to ECM module on operation related to CRCm module." bitfld.long 0x0 13. "COMP_ERR_OE,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification" group.long 0xC00++0x3 line.long 0x0 "WCRCm_KCRCm_EN,WCRCm_KCRCm_EN is a register that sets enable the data transfer to/from each port for KCRCm module in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to KCRCm,1: Enable transferring data to KCRCm" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command/Expected data port,1: Enable input to Data/Command/Expected data port" group.long 0xC10++0x3 line.long 0x0 "WCRCm_KCRCm_SIZE,WCRCm_KCRCm_SIZE is a register that sets transfer size of 1 packet to KCRCm module." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0xC20++0x3 line.long 0x0 "WCRCm_KCRCm_STOP,WCRCm_KCRCm_STOP is a register that stop transfer to KCRCm module." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0xC30++0x3 line.long 0x0 "WCRCm_KCRCm_CMDEN,WCRCm_KCRCm_CMDEN is a register that sets enable command function for KCRCm module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" group.long 0xC40++0x3 line.long 0x0 "WCRCm_KCRCm_COMP,WCRCm_KCRCm_COMP is a register that sets enable comparing CRC result from KCRCm module with expected data in FIFO." bitfld.long 0x0 16.--17. "CMP_FREQ,Set the frequency of comparing.(コンペアの頻度を設定。)" "0,1,2,3" bitfld.long 0x0 1. "EXP_REQSEL,Select DMA Transfer request source for transferring expected data." "0: dmareq_wcrcm_kcrcn_in,1: dmareq_wcrcm_kcrcn_res" newline bitfld.long 0x0 0. "CMP_EN,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function" rgroup.long 0xC50++0x3 line.long 0x0 "WCRCm_KCRCm_COMP_RES,WCRCm_KCRCm_COMP_RES is a register that indicates the result of comparing CRC for KCRCm module." hexmask.long.word 0x0 0.--15. 1. "CMP_RES,The result of comparing CRC" group.long 0xC60++0x3 line.long 0x0 "WCRCm_KCRCm_FMT,WCRCm_KCRCm_FMT is a register that set format of input data for KCRCm module." bitfld.long 0x0 0.--1. "IN_FMT,Data format of E2E input data" "0,1,2,3" group.long 0xC70++0x3 line.long 0x0 "WCRCm_KCRCm_CONV,WCRCm_KCRCm_CONV is a register that sets CRC conversion size to once for KCRCm module." hexmask.long.tbyte 0x0 0.--20. 1. "CONV,CRC conversion size specification" wgroup.long 0xC80++0x3 line.long 0x0 "WCRCm_KCRCm_WAIT,WCRCm_KCRCm_WAIT is a register that wait subsequent command for KCRCm module." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0xC90++0x3 line.long 0x0 "WCRCm_KCRCm_RES_SIZE,WCRCm_KCRCm_RES_SIZE is a register that sets output size of result data at once for KCRCm module." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0xD10++0x3 line.long 0x0 "WCRCm_KCRCm_INIT_CRC,WCRCm_KCRCm_INIT_CRC is a register that sets CRC code value to KCRCmCOUT register at auto clear." hexmask.long 0x0 0.--31. 1. "INIT_CODE,CRC code value to KCRCmDOUT register at auto clear." group.long 0xE00++0x3 line.long 0x0 "WCRCm_KCRCm_STS,WCRCm_KCRCm_STS is a register that indicates the state of operation related to KCRCm module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_KCRCm_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 13. "COMP_ERR,Indicates the error of comparing CRC." "0: No comparing error or not comparing,1: Mismatch has occurred" newline bitfld.long 0x0 12. "COMP_DONE,Indicates the state of comparing CRC." "0: Comparison in progress or not comparing,1: Comparing is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0xE40++0x3 line.long 0x0 "WCRCm_KCRCm_INTEN,WCRCm_KCRCm_INTEN is a register that sets enable for the interrupt of operation related to KCRCm module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_KCRCm_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 13. "COMP_ERR_IE,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 12. "COMP_DONE_IE,Interrupt for the complete of comparing CRC enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0xE80++0x3 line.long 0x0 "WCRCm_KCRCm_ECMEN,WCRCm_KCRCm_ECMEN is a register that sets enable for error notification to ECM module on operation related to KCRCm module." bitfld.long 0x0 13. "COMP_ERR_OE,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification" group.long 0xF00++0x3 line.long 0x0 "WCRCm_COMMON_STS,WCRCm_COMMON_STS is a register that indicates the state of operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR,Indicates the error of EDC." "0: No EDC error,1: EDC error has occurred" group.long 0xF40++0x3 line.long 0x0 "WCRCm_COMMON_INTEN,WCRCm_COMMON_INTEN is a register that sets enable for the interrupt of operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR_IE,Interrupt for the error of EDC enable" "0: Disable interrupt,1: Enable interrupt" group.long 0xF80++0x3 line.long 0x0 "WCRCm_COMMON_ECMEN,WCRCm_COMMON_ECMEN is a register that sets enable for error notification to ECM module on operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR_OE,Error notification for EDC error enable" "0: Disable notification,1: Enable notification" group.long 0xFC0++0x3 line.long 0x0 "WCRCm_ERRINJ,WCRCm_ERRINJ is a register that sets enable error injection for bus data signal or EDC code signal." hexmask.long.word 0x0 16.--31. 1. "CODE,Code value" bitfld.long 0x0 0.--2. "ERR_INJ,Error injection enable" "0: Disables single bit error for EDC code signal,1: Enables double bit error for EDC code signal,?,?,?,?,?,?" tree.end tree "WCRC_1" group.long 0x0++0x3 line.long 0x0 "WCRCm_CAIPn_EN,WCRCm_CAIPn_EN is a register that sets enable the data transfer to/from each port for CAIP_Lite_n interface in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CAIP_Lite_n,1: Enable transferring data to CAIP_Lite_n" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command port,1: Enable input to Data/Command port" group.long 0x10++0x3 line.long 0x0 "WCRCm_CAIPn_SIZE,WCRCm_CAIPn_SIZE is a register that sets transfer size of 1 block data for CAIP_Lite_n interface." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x20++0x3 line.long 0x0 "WCRCm_CAIPn_STOP,WCRCm_CAIPn_STOP is a register that stop transfer to CAIP_Lite_n interface." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x30++0x3 line.long 0x0 "WCRCm_CAIPn_CMDEN,WCRCm_CAIPn_CMDEN is a register that sets enable command function for CAIP_Lite_n module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" wgroup.long 0x80++0x3 line.long 0x0 "WCRCm_CAIPn_WAIT,WCRCm_CAIPn_WAIT is a register that wait subsequent command for CAIP_Lite_n interface." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x90++0x3 line.long 0x0 "WCRCm_CAIPn_RES_SIZE,WCRCm_CAIPn_RES_SIZE is a register that sets output size of result data at once for CAIP_Lite_n interface." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x200++0x3 line.long 0x0 "WCRCm_CAIPn_STS,WCRCm_CAIPn_STS is a register that indicates the state of operation related to CAIP_Lite_n module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CAIPn_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0x240++0x3 line.long 0x0 "WCRCm_CAIPn_INTEN,WCRCm_CAIPn_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_n module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CAIPn_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0x280++0x3 line.long 0x0 "WCRCm_CAIPn_ECMEN,WCRCm_CAIPn_ECMEN is a register that sets enable for error notification to ECM module on operation related to CAIP_Lite_n module." group.long 0x400++0x3 line.long 0x0 "WCRCm_CAIPp_EN,WCRCm_CAIPp_EN is a register that sets enable the data transfer to/from each ports for CAIP_Lite_p interface in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CAIP_Lite_p,1: Enable transferring data to CAIP_Lite_p" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command port,1: Enable input to Data/Command port" group.long 0x410++0x3 line.long 0x0 "WCRCm_CAIPp_SIZE,WCRCm_CAIPp_SIZE is a register that sets transfer size of 1 block data to CAIP_Lite_p interface." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x420++0x3 line.long 0x0 "WCRCm_CAIPp_STOP,WCRCm_CAIPp_STOP is a register that stop transfer to CAIP_Lite_p interface." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x430++0x3 line.long 0x0 "WCRCm_CAIPp_CMDEN,WCRCm_CAIPp_CMDEN is a register that sets enable command function for CAIP_Lite_p module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" wgroup.long 0x480++0x3 line.long 0x0 "WCRCm_CAIPp_WAIT,WCRCm_CAIPp_WAIT is a register that wait subsequent command for CAIP_Lite_p interface." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x490++0x3 line.long 0x0 "WCRCm_CAIPp_RES_SIZE,WCRCm_CAIPp_RES_SIZE is a register that sets output size of result data at once for CAIP_Lite_p interface." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x600++0x3 line.long 0x0 "WCRCm_CAIPp_STS,WCRCm_CAIPp_STS is a register that indicates the state of operation related to CAIP_Lite_p module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CAIPp_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0x640++0x3 line.long 0x0 "WCRCm_CAIPp_INTEN,WCRCm_CAIPp_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_p module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CAIPp_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0x680++0x3 line.long 0x0 "WCRCm_CAIPp_ECMEN,WCRCm_CAIPp_ECMEN is a register that sets enable for error notification to ECM module on operation related to CAIP_Lite_p module." group.long 0x800++0x3 line.long 0x0 "WCRCm_CRCm_EN,WCRCm_CRCm_EN is a register that sets enable the data transfer to/from each port for CRCm module in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CRCm,1: Enable transferring data to CRCm" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command/Expected data port,1: Enable input to Data/Command/Expected data port" group.long 0x810++0x3 line.long 0x0 "WCRCm_CRCm_SIZE,WCRCm_CRCm_SIZE is a register that sets transfer size of 1 packet to CRCm module." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x820++0x3 line.long 0x0 "WCRCm_CRCm_STOP,WCRCm_CRCm_STOP is a register that stop transfer to CRCm module." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x830++0x3 line.long 0x0 "WCRCm_CRCm_CMDEN,WCRCm_CRCm_CMDEN is a register that sets enable command function for CRCm module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" group.long 0x840++0x3 line.long 0x0 "WCRCm_CRCm_COMP,WCRCm_CRCm_COMP is a register that sets enable comparing CRC result from CRCm module with expected data in FIFO." bitfld.long 0x0 16.--17. "CMP_FREQ,Set the frequency of comparing.(コンペアの頻度を設定。)" "0,1,2,3" bitfld.long 0x0 1. "EXP_REQSEL,Select DMA Transfer request source for transferring expected data." "0: dmareq_wcrcm_crcm_in,1: dmareq_wcrcm_crcm_res" newline bitfld.long 0x0 0. "CMP_EN,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function" rgroup.long 0x850++0x3 line.long 0x0 "WCRCm_CRCm_COMP_RES,WCRCm_CRCm_COMP_RES is a register that indicates the result of comparing CRC for CRCm module." hexmask.long.word 0x0 0.--15. 1. "CMP_RES,The result of comparing CRC" group.long 0x860++0x3 line.long 0x0 "WCRCm_CRCm_FMT,WCRCm_CRCm_FMT is a register that set format of input data for CRCm module." bitfld.long 0x0 0.--1. "IN_FMT,Data format of E2E input data" "0,1,2,3" group.long 0x870++0x3 line.long 0x0 "WCRCm_CRCm_CONV,WCRCm_CRCm_CONV is a register that sets CRC conversion size to once for CRCm module." hexmask.long.tbyte 0x0 0.--20. 1. "CONV,CRC conversion size specification" wgroup.long 0x880++0x3 line.long 0x0 "WCRCm_CRCm_WAIT,WCRCm_CRCm_WAIT is a register that wait subsequent command for CRCm module." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x890++0x3 line.long 0x0 "WCRCm_CRCm_RES_SIZE,WCRCm_CRCm_RES_SIZE is a register that sets output size of result data at once for CRCm module." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x910++0x3 line.long 0x0 "WCRCm_CRCm_INIT_CRC,WCRCm_CRCm_INIT_CRC is a register that sets CRC code value to DCRAnCOUT register at auto clear." hexmask.long 0x0 0.--31. 1. "INIT_CODE,CRC code value to DCRAnCOUT register at auto clear." group.long 0xA00++0x3 line.long 0x0 "WCRCm_CRCm_STS,WCRCm_CRCm_STS is a register that indicates the state of operation related to CRCm module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CRCm_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 13. "COMP_ERR,Indicates the error of comparing CRC." "0: No comparing error or not comparing,1: Mismatch has occurred" newline bitfld.long 0x0 12. "COMP_DONE,Indicates the state of comparing CRC." "0: Comparison in progress or not comparing,1: Comparing is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0xA40++0x3 line.long 0x0 "WCRCm_CRCm_INTEN,WCRCm_CRCm_INTEN is a register that sets enable for the interrupt of operation related to CRCm module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CRCm_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 13. "COMP_ERR_IE,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 12. "COMP_DONE_IE,Interrupt for the complete of comparing CRC enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0xA80++0x3 line.long 0x0 "WCRCm_CRCm_ECMEN,WCRCm_CRCm_ECMEN is a register that sets enable for error notification to ECM module on operation related to CRCm module." bitfld.long 0x0 13. "COMP_ERR_OE,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification" group.long 0xC00++0x3 line.long 0x0 "WCRCm_KCRCm_EN,WCRCm_KCRCm_EN is a register that sets enable the data transfer to/from each port for KCRCm module in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to KCRCm,1: Enable transferring data to KCRCm" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command/Expected data port,1: Enable input to Data/Command/Expected data port" group.long 0xC10++0x3 line.long 0x0 "WCRCm_KCRCm_SIZE,WCRCm_KCRCm_SIZE is a register that sets transfer size of 1 packet to KCRCm module." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0xC20++0x3 line.long 0x0 "WCRCm_KCRCm_STOP,WCRCm_KCRCm_STOP is a register that stop transfer to KCRCm module." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0xC30++0x3 line.long 0x0 "WCRCm_KCRCm_CMDEN,WCRCm_KCRCm_CMDEN is a register that sets enable command function for KCRCm module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" group.long 0xC40++0x3 line.long 0x0 "WCRCm_KCRCm_COMP,WCRCm_KCRCm_COMP is a register that sets enable comparing CRC result from KCRCm module with expected data in FIFO." bitfld.long 0x0 16.--17. "CMP_FREQ,Set the frequency of comparing.(コンペアの頻度を設定。)" "0,1,2,3" bitfld.long 0x0 1. "EXP_REQSEL,Select DMA Transfer request source for transferring expected data." "0: dmareq_wcrcm_kcrcn_in,1: dmareq_wcrcm_kcrcn_res" newline bitfld.long 0x0 0. "CMP_EN,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function" rgroup.long 0xC50++0x3 line.long 0x0 "WCRCm_KCRCm_COMP_RES,WCRCm_KCRCm_COMP_RES is a register that indicates the result of comparing CRC for KCRCm module." hexmask.long.word 0x0 0.--15. 1. "CMP_RES,The result of comparing CRC" group.long 0xC60++0x3 line.long 0x0 "WCRCm_KCRCm_FMT,WCRCm_KCRCm_FMT is a register that set format of input data for KCRCm module." bitfld.long 0x0 0.--1. "IN_FMT,Data format of E2E input data" "0,1,2,3" group.long 0xC70++0x3 line.long 0x0 "WCRCm_KCRCm_CONV,WCRCm_KCRCm_CONV is a register that sets CRC conversion size to once for KCRCm module." hexmask.long.tbyte 0x0 0.--20. 1. "CONV,CRC conversion size specification" wgroup.long 0xC80++0x3 line.long 0x0 "WCRCm_KCRCm_WAIT,WCRCm_KCRCm_WAIT is a register that wait subsequent command for KCRCm module." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0xC90++0x3 line.long 0x0 "WCRCm_KCRCm_RES_SIZE,WCRCm_KCRCm_RES_SIZE is a register that sets output size of result data at once for KCRCm module." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0xD10++0x3 line.long 0x0 "WCRCm_KCRCm_INIT_CRC,WCRCm_KCRCm_INIT_CRC is a register that sets CRC code value to KCRCmCOUT register at auto clear." hexmask.long 0x0 0.--31. 1. "INIT_CODE,CRC code value to KCRCmDOUT register at auto clear." group.long 0xE00++0x3 line.long 0x0 "WCRCm_KCRCm_STS,WCRCm_KCRCm_STS is a register that indicates the state of operation related to KCRCm module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_KCRCm_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 13. "COMP_ERR,Indicates the error of comparing CRC." "0: No comparing error or not comparing,1: Mismatch has occurred" newline bitfld.long 0x0 12. "COMP_DONE,Indicates the state of comparing CRC." "0: Comparison in progress or not comparing,1: Comparing is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0xE40++0x3 line.long 0x0 "WCRCm_KCRCm_INTEN,WCRCm_KCRCm_INTEN is a register that sets enable for the interrupt of operation related to KCRCm module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_KCRCm_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 13. "COMP_ERR_IE,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 12. "COMP_DONE_IE,Interrupt for the complete of comparing CRC enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0xE80++0x3 line.long 0x0 "WCRCm_KCRCm_ECMEN,WCRCm_KCRCm_ECMEN is a register that sets enable for error notification to ECM module on operation related to KCRCm module." bitfld.long 0x0 13. "COMP_ERR_OE,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification" group.long 0xF00++0x3 line.long 0x0 "WCRCm_COMMON_STS,WCRCm_COMMON_STS is a register that indicates the state of operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR,Indicates the error of EDC." "0: No EDC error,1: EDC error has occurred" group.long 0xF40++0x3 line.long 0x0 "WCRCm_COMMON_INTEN,WCRCm_COMMON_INTEN is a register that sets enable for the interrupt of operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR_IE,Interrupt for the error of EDC enable" "0: Disable interrupt,1: Enable interrupt" group.long 0xF80++0x3 line.long 0x0 "WCRCm_COMMON_ECMEN,WCRCm_COMMON_ECMEN is a register that sets enable for error notification to ECM module on operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR_OE,Error notification for EDC error enable" "0: Disable notification,1: Enable notification" group.long 0xFC0++0x3 line.long 0x0 "WCRCm_ERRINJ,WCRCm_ERRINJ is a register that sets enable error injection for bus data signal or EDC code signal." hexmask.long.word 0x0 16.--31. 1. "CODE,Code value" bitfld.long 0x0 0.--2. "ERR_INJ,Error injection enable" "0: Disables single bit error for EDC code signal,1: Enables double bit error for EDC code signal,?,?,?,?,?,?" tree.end tree "WCRC_2" group.long 0x0++0x3 line.long 0x0 "WCRCm_CAIPn_EN,WCRCm_CAIPn_EN is a register that sets enable the data transfer to/from each port for CAIP_Lite_n interface in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CAIP_Lite_n,1: Enable transferring data to CAIP_Lite_n" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command port,1: Enable input to Data/Command port" group.long 0x10++0x3 line.long 0x0 "WCRCm_CAIPn_SIZE,WCRCm_CAIPn_SIZE is a register that sets transfer size of 1 block data for CAIP_Lite_n interface." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x20++0x3 line.long 0x0 "WCRCm_CAIPn_STOP,WCRCm_CAIPn_STOP is a register that stop transfer to CAIP_Lite_n interface." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x30++0x3 line.long 0x0 "WCRCm_CAIPn_CMDEN,WCRCm_CAIPn_CMDEN is a register that sets enable command function for CAIP_Lite_n module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" wgroup.long 0x80++0x3 line.long 0x0 "WCRCm_CAIPn_WAIT,WCRCm_CAIPn_WAIT is a register that wait subsequent command for CAIP_Lite_n interface." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x90++0x3 line.long 0x0 "WCRCm_CAIPn_RES_SIZE,WCRCm_CAIPn_RES_SIZE is a register that sets output size of result data at once for CAIP_Lite_n interface." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x200++0x3 line.long 0x0 "WCRCm_CAIPn_STS,WCRCm_CAIPn_STS is a register that indicates the state of operation related to CAIP_Lite_n module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CAIPn_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0x240++0x3 line.long 0x0 "WCRCm_CAIPn_INTEN,WCRCm_CAIPn_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_n module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CAIPn_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0x280++0x3 line.long 0x0 "WCRCm_CAIPn_ECMEN,WCRCm_CAIPn_ECMEN is a register that sets enable for error notification to ECM module on operation related to CAIP_Lite_n module." group.long 0x400++0x3 line.long 0x0 "WCRCm_CAIPp_EN,WCRCm_CAIPp_EN is a register that sets enable the data transfer to/from each ports for CAIP_Lite_p interface in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CAIP_Lite_p,1: Enable transferring data to CAIP_Lite_p" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command port,1: Enable input to Data/Command port" group.long 0x410++0x3 line.long 0x0 "WCRCm_CAIPp_SIZE,WCRCm_CAIPp_SIZE is a register that sets transfer size of 1 block data to CAIP_Lite_p interface." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x420++0x3 line.long 0x0 "WCRCm_CAIPp_STOP,WCRCm_CAIPp_STOP is a register that stop transfer to CAIP_Lite_p interface." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x430++0x3 line.long 0x0 "WCRCm_CAIPp_CMDEN,WCRCm_CAIPp_CMDEN is a register that sets enable command function for CAIP_Lite_p module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" wgroup.long 0x480++0x3 line.long 0x0 "WCRCm_CAIPp_WAIT,WCRCm_CAIPp_WAIT is a register that wait subsequent command for CAIP_Lite_p interface." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x490++0x3 line.long 0x0 "WCRCm_CAIPp_RES_SIZE,WCRCm_CAIPp_RES_SIZE is a register that sets output size of result data at once for CAIP_Lite_p interface." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x600++0x3 line.long 0x0 "WCRCm_CAIPp_STS,WCRCm_CAIPp_STS is a register that indicates the state of operation related to CAIP_Lite_p module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CAIPp_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0x640++0x3 line.long 0x0 "WCRCm_CAIPp_INTEN,WCRCm_CAIPp_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_p module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CAIPp_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0x680++0x3 line.long 0x0 "WCRCm_CAIPp_ECMEN,WCRCm_CAIPp_ECMEN is a register that sets enable for error notification to ECM module on operation related to CAIP_Lite_p module." group.long 0x800++0x3 line.long 0x0 "WCRCm_CRCm_EN,WCRCm_CRCm_EN is a register that sets enable the data transfer to/from each port for CRCm module in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CRCm,1: Enable transferring data to CRCm" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command/Expected data port,1: Enable input to Data/Command/Expected data port" group.long 0x810++0x3 line.long 0x0 "WCRCm_CRCm_SIZE,WCRCm_CRCm_SIZE is a register that sets transfer size of 1 packet to CRCm module." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x820++0x3 line.long 0x0 "WCRCm_CRCm_STOP,WCRCm_CRCm_STOP is a register that stop transfer to CRCm module." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x830++0x3 line.long 0x0 "WCRCm_CRCm_CMDEN,WCRCm_CRCm_CMDEN is a register that sets enable command function for CRCm module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" group.long 0x840++0x3 line.long 0x0 "WCRCm_CRCm_COMP,WCRCm_CRCm_COMP is a register that sets enable comparing CRC result from CRCm module with expected data in FIFO." bitfld.long 0x0 16.--17. "CMP_FREQ,Set the frequency of comparing.(コンペアの頻度を設定。)" "0,1,2,3" bitfld.long 0x0 1. "EXP_REQSEL,Select DMA Transfer request source for transferring expected data." "0: dmareq_wcrcm_crcm_in,1: dmareq_wcrcm_crcm_res" newline bitfld.long 0x0 0. "CMP_EN,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function" rgroup.long 0x850++0x3 line.long 0x0 "WCRCm_CRCm_COMP_RES,WCRCm_CRCm_COMP_RES is a register that indicates the result of comparing CRC for CRCm module." hexmask.long.word 0x0 0.--15. 1. "CMP_RES,The result of comparing CRC" group.long 0x860++0x3 line.long 0x0 "WCRCm_CRCm_FMT,WCRCm_CRCm_FMT is a register that set format of input data for CRCm module." bitfld.long 0x0 0.--1. "IN_FMT,Data format of E2E input data" "0,1,2,3" group.long 0x870++0x3 line.long 0x0 "WCRCm_CRCm_CONV,WCRCm_CRCm_CONV is a register that sets CRC conversion size to once for CRCm module." hexmask.long.tbyte 0x0 0.--20. 1. "CONV,CRC conversion size specification" wgroup.long 0x880++0x3 line.long 0x0 "WCRCm_CRCm_WAIT,WCRCm_CRCm_WAIT is a register that wait subsequent command for CRCm module." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x890++0x3 line.long 0x0 "WCRCm_CRCm_RES_SIZE,WCRCm_CRCm_RES_SIZE is a register that sets output size of result data at once for CRCm module." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x910++0x3 line.long 0x0 "WCRCm_CRCm_INIT_CRC,WCRCm_CRCm_INIT_CRC is a register that sets CRC code value to DCRAnCOUT register at auto clear." hexmask.long 0x0 0.--31. 1. "INIT_CODE,CRC code value to DCRAnCOUT register at auto clear." group.long 0xA00++0x3 line.long 0x0 "WCRCm_CRCm_STS,WCRCm_CRCm_STS is a register that indicates the state of operation related to CRCm module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CRCm_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 13. "COMP_ERR,Indicates the error of comparing CRC." "0: No comparing error or not comparing,1: Mismatch has occurred" newline bitfld.long 0x0 12. "COMP_DONE,Indicates the state of comparing CRC." "0: Comparison in progress or not comparing,1: Comparing is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0xA40++0x3 line.long 0x0 "WCRCm_CRCm_INTEN,WCRCm_CRCm_INTEN is a register that sets enable for the interrupt of operation related to CRCm module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CRCm_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 13. "COMP_ERR_IE,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 12. "COMP_DONE_IE,Interrupt for the complete of comparing CRC enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0xA80++0x3 line.long 0x0 "WCRCm_CRCm_ECMEN,WCRCm_CRCm_ECMEN is a register that sets enable for error notification to ECM module on operation related to CRCm module." bitfld.long 0x0 13. "COMP_ERR_OE,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification" group.long 0xC00++0x3 line.long 0x0 "WCRCm_KCRCm_EN,WCRCm_KCRCm_EN is a register that sets enable the data transfer to/from each port for KCRCm module in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to KCRCm,1: Enable transferring data to KCRCm" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command/Expected data port,1: Enable input to Data/Command/Expected data port" group.long 0xC10++0x3 line.long 0x0 "WCRCm_KCRCm_SIZE,WCRCm_KCRCm_SIZE is a register that sets transfer size of 1 packet to KCRCm module." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0xC20++0x3 line.long 0x0 "WCRCm_KCRCm_STOP,WCRCm_KCRCm_STOP is a register that stop transfer to KCRCm module." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0xC30++0x3 line.long 0x0 "WCRCm_KCRCm_CMDEN,WCRCm_KCRCm_CMDEN is a register that sets enable command function for KCRCm module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" group.long 0xC40++0x3 line.long 0x0 "WCRCm_KCRCm_COMP,WCRCm_KCRCm_COMP is a register that sets enable comparing CRC result from KCRCm module with expected data in FIFO." bitfld.long 0x0 16.--17. "CMP_FREQ,Set the frequency of comparing.(コンペアの頻度を設定。)" "0,1,2,3" bitfld.long 0x0 1. "EXP_REQSEL,Select DMA Transfer request source for transferring expected data." "0: dmareq_wcrcm_kcrcn_in,1: dmareq_wcrcm_kcrcn_res" newline bitfld.long 0x0 0. "CMP_EN,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function" rgroup.long 0xC50++0x3 line.long 0x0 "WCRCm_KCRCm_COMP_RES,WCRCm_KCRCm_COMP_RES is a register that indicates the result of comparing CRC for KCRCm module." hexmask.long.word 0x0 0.--15. 1. "CMP_RES,The result of comparing CRC" group.long 0xC60++0x3 line.long 0x0 "WCRCm_KCRCm_FMT,WCRCm_KCRCm_FMT is a register that set format of input data for KCRCm module." bitfld.long 0x0 0.--1. "IN_FMT,Data format of E2E input data" "0,1,2,3" group.long 0xC70++0x3 line.long 0x0 "WCRCm_KCRCm_CONV,WCRCm_KCRCm_CONV is a register that sets CRC conversion size to once for KCRCm module." hexmask.long.tbyte 0x0 0.--20. 1. "CONV,CRC conversion size specification" wgroup.long 0xC80++0x3 line.long 0x0 "WCRCm_KCRCm_WAIT,WCRCm_KCRCm_WAIT is a register that wait subsequent command for KCRCm module." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0xC90++0x3 line.long 0x0 "WCRCm_KCRCm_RES_SIZE,WCRCm_KCRCm_RES_SIZE is a register that sets output size of result data at once for KCRCm module." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0xD10++0x3 line.long 0x0 "WCRCm_KCRCm_INIT_CRC,WCRCm_KCRCm_INIT_CRC is a register that sets CRC code value to KCRCmCOUT register at auto clear." hexmask.long 0x0 0.--31. 1. "INIT_CODE,CRC code value to KCRCmDOUT register at auto clear." group.long 0xE00++0x3 line.long 0x0 "WCRCm_KCRCm_STS,WCRCm_KCRCm_STS is a register that indicates the state of operation related to KCRCm module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_KCRCm_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 13. "COMP_ERR,Indicates the error of comparing CRC." "0: No comparing error or not comparing,1: Mismatch has occurred" newline bitfld.long 0x0 12. "COMP_DONE,Indicates the state of comparing CRC." "0: Comparison in progress or not comparing,1: Comparing is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0xE40++0x3 line.long 0x0 "WCRCm_KCRCm_INTEN,WCRCm_KCRCm_INTEN is a register that sets enable for the interrupt of operation related to KCRCm module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_KCRCm_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 13. "COMP_ERR_IE,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 12. "COMP_DONE_IE,Interrupt for the complete of comparing CRC enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0xE80++0x3 line.long 0x0 "WCRCm_KCRCm_ECMEN,WCRCm_KCRCm_ECMEN is a register that sets enable for error notification to ECM module on operation related to KCRCm module." bitfld.long 0x0 13. "COMP_ERR_OE,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification" group.long 0xF00++0x3 line.long 0x0 "WCRCm_COMMON_STS,WCRCm_COMMON_STS is a register that indicates the state of operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR,Indicates the error of EDC." "0: No EDC error,1: EDC error has occurred" group.long 0xF40++0x3 line.long 0x0 "WCRCm_COMMON_INTEN,WCRCm_COMMON_INTEN is a register that sets enable for the interrupt of operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR_IE,Interrupt for the error of EDC enable" "0: Disable interrupt,1: Enable interrupt" group.long 0xF80++0x3 line.long 0x0 "WCRCm_COMMON_ECMEN,WCRCm_COMMON_ECMEN is a register that sets enable for error notification to ECM module on operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR_OE,Error notification for EDC error enable" "0: Disable notification,1: Enable notification" group.long 0xFC0++0x3 line.long 0x0 "WCRCm_ERRINJ,WCRCm_ERRINJ is a register that sets enable error injection for bus data signal or EDC code signal." hexmask.long.word 0x0 16.--31. 1. "CODE,Code value" bitfld.long 0x0 0.--2. "ERR_INJ,Error injection enable" "0: Disables single bit error for EDC code signal,1: Enables double bit error for EDC code signal,?,?,?,?,?,?" tree.end tree "WCRC_3" group.long 0x0++0x3 line.long 0x0 "WCRCm_CAIPn_EN,WCRCm_CAIPn_EN is a register that sets enable the data transfer to/from each port for CAIP_Lite_n interface in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CAIP_Lite_n,1: Enable transferring data to CAIP_Lite_n" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command port,1: Enable input to Data/Command port" group.long 0x10++0x3 line.long 0x0 "WCRCm_CAIPn_SIZE,WCRCm_CAIPn_SIZE is a register that sets transfer size of 1 block data for CAIP_Lite_n interface." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x20++0x3 line.long 0x0 "WCRCm_CAIPn_STOP,WCRCm_CAIPn_STOP is a register that stop transfer to CAIP_Lite_n interface." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x30++0x3 line.long 0x0 "WCRCm_CAIPn_CMDEN,WCRCm_CAIPn_CMDEN is a register that sets enable command function for CAIP_Lite_n module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" wgroup.long 0x80++0x3 line.long 0x0 "WCRCm_CAIPn_WAIT,WCRCm_CAIPn_WAIT is a register that wait subsequent command for CAIP_Lite_n interface." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x90++0x3 line.long 0x0 "WCRCm_CAIPn_RES_SIZE,WCRCm_CAIPn_RES_SIZE is a register that sets output size of result data at once for CAIP_Lite_n interface." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x200++0x3 line.long 0x0 "WCRCm_CAIPn_STS,WCRCm_CAIPn_STS is a register that indicates the state of operation related to CAIP_Lite_n module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CAIPn_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0x240++0x3 line.long 0x0 "WCRCm_CAIPn_INTEN,WCRCm_CAIPn_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_n module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CAIPn_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0x280++0x3 line.long 0x0 "WCRCm_CAIPn_ECMEN,WCRCm_CAIPn_ECMEN is a register that sets enable for error notification to ECM module on operation related to CAIP_Lite_n module." group.long 0x400++0x3 line.long 0x0 "WCRCm_CAIPp_EN,WCRCm_CAIPp_EN is a register that sets enable the data transfer to/from each ports for CAIP_Lite_p interface in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CAIP_Lite_p,1: Enable transferring data to CAIP_Lite_p" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command port,1: Enable input to Data/Command port" group.long 0x410++0x3 line.long 0x0 "WCRCm_CAIPp_SIZE,WCRCm_CAIPp_SIZE is a register that sets transfer size of 1 block data to CAIP_Lite_p interface." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x420++0x3 line.long 0x0 "WCRCm_CAIPp_STOP,WCRCm_CAIPp_STOP is a register that stop transfer to CAIP_Lite_p interface." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x430++0x3 line.long 0x0 "WCRCm_CAIPp_CMDEN,WCRCm_CAIPp_CMDEN is a register that sets enable command function for CAIP_Lite_p module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" wgroup.long 0x480++0x3 line.long 0x0 "WCRCm_CAIPp_WAIT,WCRCm_CAIPp_WAIT is a register that wait subsequent command for CAIP_Lite_p interface." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x490++0x3 line.long 0x0 "WCRCm_CAIPp_RES_SIZE,WCRCm_CAIPp_RES_SIZE is a register that sets output size of result data at once for CAIP_Lite_p interface." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x600++0x3 line.long 0x0 "WCRCm_CAIPp_STS,WCRCm_CAIPp_STS is a register that indicates the state of operation related to CAIP_Lite_p module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CAIPp_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0x640++0x3 line.long 0x0 "WCRCm_CAIPp_INTEN,WCRCm_CAIPp_INTEN is a register that sets enable for the interrupt of operation related to CAIP_Lite_p module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CAIPp_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0x680++0x3 line.long 0x0 "WCRCm_CAIPp_ECMEN,WCRCm_CAIPp_ECMEN is a register that sets enable for error notification to ECM module on operation related to CAIP_Lite_p module." group.long 0x800++0x3 line.long 0x0 "WCRCm_CRCm_EN,WCRCm_CRCm_EN is a register that sets enable the data transfer to/from each port for CRCm module in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to CRCm,1: Enable transferring data to CRCm" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command/Expected data port,1: Enable input to Data/Command/Expected data port" group.long 0x810++0x3 line.long 0x0 "WCRCm_CRCm_SIZE,WCRCm_CRCm_SIZE is a register that sets transfer size of 1 packet to CRCm module." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0x820++0x3 line.long 0x0 "WCRCm_CRCm_STOP,WCRCm_CRCm_STOP is a register that stop transfer to CRCm module." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0x830++0x3 line.long 0x0 "WCRCm_CRCm_CMDEN,WCRCm_CRCm_CMDEN is a register that sets enable command function for CRCm module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" group.long 0x840++0x3 line.long 0x0 "WCRCm_CRCm_COMP,WCRCm_CRCm_COMP is a register that sets enable comparing CRC result from CRCm module with expected data in FIFO." bitfld.long 0x0 16.--17. "CMP_FREQ,Set the frequency of comparing.(コンペアの頻度を設定。)" "0,1,2,3" bitfld.long 0x0 1. "EXP_REQSEL,Select DMA Transfer request source for transferring expected data." "0: dmareq_wcrcm_crcm_in,1: dmareq_wcrcm_crcm_res" newline bitfld.long 0x0 0. "CMP_EN,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function" rgroup.long 0x850++0x3 line.long 0x0 "WCRCm_CRCm_COMP_RES,WCRCm_CRCm_COMP_RES is a register that indicates the result of comparing CRC for CRCm module." hexmask.long.word 0x0 0.--15. 1. "CMP_RES,The result of comparing CRC" group.long 0x860++0x3 line.long 0x0 "WCRCm_CRCm_FMT,WCRCm_CRCm_FMT is a register that set format of input data for CRCm module." bitfld.long 0x0 0.--1. "IN_FMT,Data format of E2E input data" "0,1,2,3" group.long 0x870++0x3 line.long 0x0 "WCRCm_CRCm_CONV,WCRCm_CRCm_CONV is a register that sets CRC conversion size to once for CRCm module." hexmask.long.tbyte 0x0 0.--20. 1. "CONV,CRC conversion size specification" wgroup.long 0x880++0x3 line.long 0x0 "WCRCm_CRCm_WAIT,WCRCm_CRCm_WAIT is a register that wait subsequent command for CRCm module." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0x890++0x3 line.long 0x0 "WCRCm_CRCm_RES_SIZE,WCRCm_CRCm_RES_SIZE is a register that sets output size of result data at once for CRCm module." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0x910++0x3 line.long 0x0 "WCRCm_CRCm_INIT_CRC,WCRCm_CRCm_INIT_CRC is a register that sets CRC code value to DCRAnCOUT register at auto clear." hexmask.long 0x0 0.--31. 1. "INIT_CODE,CRC code value to DCRAnCOUT register at auto clear." group.long 0xA00++0x3 line.long 0x0 "WCRCm_CRCm_STS,WCRCm_CRCm_STS is a register that indicates the state of operation related to CRCm module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_CRCm_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 13. "COMP_ERR,Indicates the error of comparing CRC." "0: No comparing error or not comparing,1: Mismatch has occurred" newline bitfld.long 0x0 12. "COMP_DONE,Indicates the state of comparing CRC." "0: Comparison in progress or not comparing,1: Comparing is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0xA40++0x3 line.long 0x0 "WCRCm_CRCm_INTEN,WCRCm_CRCm_INTEN is a register that sets enable for the interrupt of operation related to CRCm module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_CRCm_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 13. "COMP_ERR_IE,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 12. "COMP_DONE_IE,Interrupt for the complete of comparing CRC enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0xA80++0x3 line.long 0x0 "WCRCm_CRCm_ECMEN,WCRCm_CRCm_ECMEN is a register that sets enable for error notification to ECM module on operation related to CRCm module." bitfld.long 0x0 13. "COMP_ERR_OE,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification" group.long 0xC00++0x3 line.long 0x0 "WCRCm_KCRCm_EN,WCRCm_KCRCm_EN is a register that sets enable the data transfer to/from each port for KCRCm module in FIFO." bitfld.long 0x0 16. "OUT_EN,(データ転送イネーブル)" "0: Disable output from Data port,1: Enable output from Data port" bitfld.long 0x0 8. "RES_EN,(結果出力イネーブル)" "0: Disable output from Result port,1: Enable output from Result port" newline bitfld.long 0x0 1. "TRANS_EN,(転送イネーブル)" "0: Disable transferring data to KCRCm,1: Enable transferring data to KCRCm" bitfld.long 0x0 0. "IN_EN,(入力イネーブル)" "0: Disable input to Data/Command/Expected data port,1: Enable input to Data/Command/Expected data port" group.long 0xC10++0x3 line.long 0x0 "WCRCm_KCRCm_SIZE,WCRCm_KCRCm_SIZE is a register that sets transfer size of 1 packet to KCRCm module." hexmask.long 0x0 0.--24. 1. "SIZE,(バイト数設定)" wgroup.long 0xC20++0x3 line.long 0x0 "WCRCm_KCRCm_STOP,WCRCm_KCRCm_STOP is a register that stop transfer to KCRCm module." bitfld.long 0x0 0. "STOP,1: Stop data transfer." "?,1: Stop data transfer" group.long 0xC30++0x3 line.long 0x0 "WCRCm_KCRCm_CMDEN,WCRCm_KCRCm_CMDEN is a register that sets enable command function for KCRCm module." bitfld.long 0x0 0. "CMD_EN,Command function enable" "0: Disable command function,1: Enable command function" group.long 0xC40++0x3 line.long 0x0 "WCRCm_KCRCm_COMP,WCRCm_KCRCm_COMP is a register that sets enable comparing CRC result from KCRCm module with expected data in FIFO." bitfld.long 0x0 16.--17. "CMP_FREQ,Set the frequency of comparing.(コンペアの頻度を設定。)" "0,1,2,3" bitfld.long 0x0 1. "EXP_REQSEL,Select DMA Transfer request source for transferring expected data." "0: dmareq_wcrcm_kcrcn_in,1: dmareq_wcrcm_kcrcn_res" newline bitfld.long 0x0 0. "CMP_EN,Comparing CRC result with expected data enable" "0: Disable comparing function,1: Enable comparing function" rgroup.long 0xC50++0x3 line.long 0x0 "WCRCm_KCRCm_COMP_RES,WCRCm_KCRCm_COMP_RES is a register that indicates the result of comparing CRC for KCRCm module." hexmask.long.word 0x0 0.--15. 1. "CMP_RES,The result of comparing CRC" group.long 0xC60++0x3 line.long 0x0 "WCRCm_KCRCm_FMT,WCRCm_KCRCm_FMT is a register that set format of input data for KCRCm module." bitfld.long 0x0 0.--1. "IN_FMT,Data format of E2E input data" "0,1,2,3" group.long 0xC70++0x3 line.long 0x0 "WCRCm_KCRCm_CONV,WCRCm_KCRCm_CONV is a register that sets CRC conversion size to once for KCRCm module." hexmask.long.tbyte 0x0 0.--20. 1. "CONV,CRC conversion size specification" wgroup.long 0xC80++0x3 line.long 0x0 "WCRCm_KCRCm_WAIT,WCRCm_KCRCm_WAIT is a register that wait subsequent command for KCRCm module." bitfld.long 0x0 0. "WAIT,1: Wait subsequent command for 128 cycles @ 533MHz." "?,1: Wait subsequent command for 128 cycles @ 533MHz" group.long 0xC90++0x3 line.long 0x0 "WCRCm_KCRCm_RES_SIZE,WCRCm_KCRCm_RES_SIZE is a register that sets output size of result data at once for KCRCm module." bitfld.long 0x0 0.--1. "RES_SIZE,Result size specification" "0: 16byte,1: 32byte,?,?" group.long 0xD10++0x3 line.long 0x0 "WCRCm_KCRCm_INIT_CRC,WCRCm_KCRCm_INIT_CRC is a register that sets CRC code value to KCRCmCOUT register at auto clear." hexmask.long 0x0 0.--31. 1. "INIT_CODE,CRC code value to KCRCmDOUT register at auto clear." group.long 0xE00++0x3 line.long 0x0 "WCRCm_KCRCm_STS,WCRCm_KCRCm_STS is a register that indicates the state of operation related to KCRCm module." bitfld.long 0x0 31. "STOP_DONE,Indicates the state of stop operation by WCRCm_KCRCm_STOP register." "0: Stop operation in progress or not done,1: Stop operation is done" bitfld.long 0x0 24. "CMD_DONE,Indicates the state of command function." "0: Accessing to register by command in progress or..,1: Accessing to register by command is done" newline bitfld.long 0x0 20. "RES_DONE,Indicates the state of result data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" bitfld.long 0x0 13. "COMP_ERR,Indicates the error of comparing CRC." "0: No comparing error or not comparing,1: Mismatch has occurred" newline bitfld.long 0x0 12. "COMP_DONE,Indicates the state of comparing CRC." "0: Comparison in progress or not comparing,1: Comparing is done" bitfld.long 0x0 0. "TRANS_DONE,Indicates the state of input data transfer." "0: Transfer in progress or not transferring,1: Transfer is done" group.long 0xE40++0x3 line.long 0x0 "WCRCm_KCRCm_INTEN,WCRCm_KCRCm_INTEN is a register that sets enable for the interrupt of operation related to KCRCm module." bitfld.long 0x0 31. "STOP_DONE_IE,Interrupt for the complete of stop operation by WCRCm_KCRCm_STOP register." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 24. "CMD_DONE_IE,Interrupt for the complete of command function enable." "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 20. "RES_DONE_IE,Interrupt for the complete of result data transfer enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 13. "COMP_ERR_IE,Interrupt for the error of comparing CRC enable" "0: Disable interrupt,1: Enable interrupt" newline bitfld.long 0x0 12. "COMP_DONE_IE,Interrupt for the complete of comparing CRC enable." "0: Disable interrupt,1: Enable interrupt" bitfld.long 0x0 0. "TRANS_DONE_IE,Interrupt for the complete of input data transfer enable." "0: Disable interrupt,1: Enable interrupt" group.long 0xE80++0x3 line.long 0x0 "WCRCm_KCRCm_ECMEN,WCRCm_KCRCm_ECMEN is a register that sets enable for error notification to ECM module on operation related to KCRCm module." bitfld.long 0x0 13. "COMP_ERR_OE,Error notification for the error of comparing CRC enable" "0: Disable notification,1: Enable notification" group.long 0xF00++0x3 line.long 0x0 "WCRCm_COMMON_STS,WCRCm_COMMON_STS is a register that indicates the state of operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR,Indicates the error of EDC." "0: No EDC error,1: EDC error has occurred" group.long 0xF40++0x3 line.long 0x0 "WCRCm_COMMON_INTEN,WCRCm_COMMON_INTEN is a register that sets enable for the interrupt of operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR_IE,Interrupt for the error of EDC enable" "0: Disable interrupt,1: Enable interrupt" group.long 0xF80++0x3 line.long 0x0 "WCRCm_COMMON_ECMEN,WCRCm_COMMON_ECMEN is a register that sets enable for error notification to ECM module on operation related to WCRCm module." bitfld.long 0x0 16. "EDC_ERR_OE,Error notification for EDC error enable" "0: Disable notification,1: Enable notification" group.long 0xFC0++0x3 line.long 0x0 "WCRCm_ERRINJ,WCRCm_ERRINJ is a register that sets enable error injection for bus data signal or EDC code signal." hexmask.long.word 0x0 16.--31. 1. "CODE,Code value" bitfld.long 0x0 0.--2. "ERR_INJ,Error injection enable" "0: Disables single bit error for EDC code signal,1: Enables double bit error for EDC code signal,?,?,?,?,?,?" tree.end tree.end tree "WWDT" base ad:0x0 tree "WWDT_0" base ad:0xFFC90000 group.byte 0x0++0x0 line.byte 0x0 "WDTA0WDTE0,Note: n = 0 to 9" bitfld.byte 0x0 7. "WDTA0RUN,Watchdog timer count start or stop." "0,1" group.byte 0xC++0x0 line.byte 0x0 "WDTA0MD0,Note: n = 0 to 9" bitfld.byte 0x0 6. "WDTA0OVF2,Interval time mode." "0,1" bitfld.byte 0x0 5. "WDTA0OVF1,Interval time mode." "0,1" bitfld.byte 0x0 4. "WDTA0OVF0,Interval time mode." "0,1" bitfld.byte 0x0 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled" bitfld.byte 0x0 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode" bitfld.byte 0x0 1. "WDTA0WS1,Window Size selection" "0,1" bitfld.byte 0x0 0. "WDTA0WS0,Window Size selection" "0,1" tree.end tree "WWDT_1" base ad:0xFFCA0000 group.byte 0x0++0x0 line.byte 0x0 "WDTA0WDTE0,Note: n = 0 to 9" bitfld.byte 0x0 7. "WDTA0RUN,Watchdog timer count start or stop." "0,1" group.byte 0xC++0x0 line.byte 0x0 "WDTA0MD0,Note: n = 0 to 9" bitfld.byte 0x0 6. "WDTA0OVF2,Interval time mode." "0,1" bitfld.byte 0x0 5. "WDTA0OVF1,Interval time mode." "0,1" bitfld.byte 0x0 4. "WDTA0OVF0,Interval time mode." "0,1" bitfld.byte 0x0 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled" bitfld.byte 0x0 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode" bitfld.byte 0x0 1. "WDTA0WS1,Window Size selection" "0,1" bitfld.byte 0x0 0. "WDTA0WS0,Window Size selection" "0,1" tree.end tree "WWDT_2" base ad:0xFFCB0000 group.byte 0x0++0x0 line.byte 0x0 "WDTA0WDTE0,Note: n = 0 to 9" bitfld.byte 0x0 7. "WDTA0RUN,Watchdog timer count start or stop." "0,1" group.byte 0xC++0x0 line.byte 0x0 "WDTA0MD0,Note: n = 0 to 9" bitfld.byte 0x0 6. "WDTA0OVF2,Interval time mode." "0,1" bitfld.byte 0x0 5. "WDTA0OVF1,Interval time mode." "0,1" bitfld.byte 0x0 4. "WDTA0OVF0,Interval time mode." "0,1" bitfld.byte 0x0 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled" bitfld.byte 0x0 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode" bitfld.byte 0x0 1. "WDTA0WS1,Window Size selection" "0,1" bitfld.byte 0x0 0. "WDTA0WS0,Window Size selection" "0,1" tree.end tree "WWDT_3" base ad:0xFFCC0000 group.byte 0x0++0x0 line.byte 0x0 "WDTA0WDTE0,Note: n = 0 to 9" bitfld.byte 0x0 7. "WDTA0RUN,Watchdog timer count start or stop." "0,1" group.byte 0xC++0x0 line.byte 0x0 "WDTA0MD0,Note: n = 0 to 9" bitfld.byte 0x0 6. "WDTA0OVF2,Interval time mode." "0,1" bitfld.byte 0x0 5. "WDTA0OVF1,Interval time mode." "0,1" bitfld.byte 0x0 4. "WDTA0OVF0,Interval time mode." "0,1" bitfld.byte 0x0 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled" bitfld.byte 0x0 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode" bitfld.byte 0x0 1. "WDTA0WS1,Window Size selection" "0,1" bitfld.byte 0x0 0. "WDTA0WS0,Window Size selection" "0,1" tree.end tree "WWDT_4" base ad:0xFFCF0000 group.byte 0x0++0x0 line.byte 0x0 "WDTA0WDTE0,Note: n = 0 to 9" bitfld.byte 0x0 7. "WDTA0RUN,Watchdog timer count start or stop." "0,1" group.byte 0xC++0x0 line.byte 0x0 "WDTA0MD0,Note: n = 0 to 9" bitfld.byte 0x0 6. "WDTA0OVF2,Interval time mode." "0,1" bitfld.byte 0x0 5. "WDTA0OVF1,Interval time mode." "0,1" bitfld.byte 0x0 4. "WDTA0OVF0,Interval time mode." "0,1" bitfld.byte 0x0 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled" bitfld.byte 0x0 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode" bitfld.byte 0x0 1. "WDTA0WS1,Window Size selection" "0,1" bitfld.byte 0x0 0. "WDTA0WS0,Window Size selection" "0,1" tree.end tree "WWDT_5" base ad:0xFFEF0000 group.byte 0x0++0x0 line.byte 0x0 "WDTA0WDTE0,Note: n = 0 to 9" bitfld.byte 0x0 7. "WDTA0RUN,Watchdog timer count start or stop." "0,1" group.byte 0xC++0x0 line.byte 0x0 "WDTA0MD0,Note: n = 0 to 9" bitfld.byte 0x0 6. "WDTA0OVF2,Interval time mode." "0,1" bitfld.byte 0x0 5. "WDTA0OVF1,Interval time mode." "0,1" bitfld.byte 0x0 4. "WDTA0OVF0,Interval time mode." "0,1" bitfld.byte 0x0 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled" bitfld.byte 0x0 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode" bitfld.byte 0x0 1. "WDTA0WS1,Window Size selection" "0,1" bitfld.byte 0x0 0. "WDTA0WS0,Window Size selection" "0,1" tree.end tree "WWDT_6" base ad:0xFFF10000 group.byte 0x0++0x0 line.byte 0x0 "WDTA0WDTE0,Note: n = 0 to 9" bitfld.byte 0x0 7. "WDTA0RUN,Watchdog timer count start or stop." "0,1" group.byte 0xC++0x0 line.byte 0x0 "WDTA0MD0,Note: n = 0 to 9" bitfld.byte 0x0 6. "WDTA0OVF2,Interval time mode." "0,1" bitfld.byte 0x0 5. "WDTA0OVF1,Interval time mode." "0,1" bitfld.byte 0x0 4. "WDTA0OVF0,Interval time mode." "0,1" bitfld.byte 0x0 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled" bitfld.byte 0x0 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode" bitfld.byte 0x0 1. "WDTA0WS1,Window Size selection" "0,1" bitfld.byte 0x0 0. "WDTA0WS0,Window Size selection" "0,1" tree.end tree "WWDT_7" base ad:0xFFF20000 group.byte 0x0++0x0 line.byte 0x0 "WDTA0WDTE0,Note: n = 0 to 9" bitfld.byte 0x0 7. "WDTA0RUN,Watchdog timer count start or stop." "0,1" group.byte 0xC++0x0 line.byte 0x0 "WDTA0MD0,Note: n = 0 to 9" bitfld.byte 0x0 6. "WDTA0OVF2,Interval time mode." "0,1" bitfld.byte 0x0 5. "WDTA0OVF1,Interval time mode." "0,1" bitfld.byte 0x0 4. "WDTA0OVF0,Interval time mode." "0,1" bitfld.byte 0x0 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled" bitfld.byte 0x0 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode" bitfld.byte 0x0 1. "WDTA0WS1,Window Size selection" "0,1" bitfld.byte 0x0 0. "WDTA0WS0,Window Size selection" "0,1" tree.end tree "WWDT_8" base ad:0xFFF30000 group.byte 0x0++0x0 line.byte 0x0 "WDTA0WDTE0,Note: n = 0 to 9" bitfld.byte 0x0 7. "WDTA0RUN,Watchdog timer count start or stop." "0,1" group.byte 0xC++0x0 line.byte 0x0 "WDTA0MD0,Note: n = 0 to 9" bitfld.byte 0x0 6. "WDTA0OVF2,Interval time mode." "0,1" bitfld.byte 0x0 5. "WDTA0OVF1,Interval time mode." "0,1" bitfld.byte 0x0 4. "WDTA0OVF0,Interval time mode." "0,1" bitfld.byte 0x0 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled" bitfld.byte 0x0 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode" bitfld.byte 0x0 1. "WDTA0WS1,Window Size selection" "0,1" bitfld.byte 0x0 0. "WDTA0WS0,Window Size selection" "0,1" tree.end tree "WWDT_9" base ad:0xFFF40000 group.byte 0x0++0x0 line.byte 0x0 "WDTA0WDTE0,Note: n = 0 to 9" bitfld.byte 0x0 7. "WDTA0RUN,Watchdog timer count start or stop." "0,1" group.byte 0xC++0x0 line.byte 0x0 "WDTA0MD0,Note: n = 0 to 9" bitfld.byte 0x0 6. "WDTA0OVF2,Interval time mode." "0,1" bitfld.byte 0x0 5. "WDTA0OVF1,Interval time mode." "0,1" bitfld.byte 0x0 4. "WDTA0OVF0,Interval time mode." "0,1" bitfld.byte 0x0 3. "WDTA0WIE,75% interrupt enable" "0: 75% interrupt is disabled,1: 75% interrupt is enabled" bitfld.byte 0x0 2. "WDTA0ERM,Error mode" "0: NMI mode,1: Reset mode" bitfld.byte 0x0 1. "WDTA0WS1,Window Size selection" "0,1" bitfld.byte 0x0 0. "WDTA0WS0,Window Size selection" "0,1" tree.end tree.end newline AUTOINDENT.OFF